26118 lines
7.2 MiB
26118 lines
7.2 MiB
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a>
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Data Structures</h2></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_a_d_c___type_def.html">ADC_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Analog to Digital Converter <br />
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<a href="struct_a_d_c___type_def.html#details">More...</a><br /></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_a_d_c___common___type_def.html">ADC_Common_TypeDef</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_a_n___tx_mail_box___type_def.html">CAN_TxMailBox_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Controller Area Network TxMailBox. <a href="struct_c_a_n___tx_mail_box___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html">CAN_FIFOMailBox_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Controller Area Network FIFOMailBox. <a href="struct_c_a_n___f_i_f_o_mail_box___type_def.html#details">More...</a><br /></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_a_n___filter_register___type_def.html">CAN_FilterRegister_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Controller Area Network FilterRegister. <a href="struct_c_a_n___filter_register___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_a_n___type_def.html">CAN_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Controller Area Network. <a href="struct_c_a_n___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_r_c___type_def.html">CRC_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">CRC calculation unit. <a href="struct_c_r_c___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html">DAC_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Digital to Analog Converter. <a href="struct_d_a_c___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_b_g_m_c_u___type_def.html">DBGMCU_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Debug MCU. <a href="struct_d_b_g_m_c_u___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_c_m_i___type_def.html">DCMI_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DCMI. <a href="struct_d_c_m_i___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DMA Controller. <a href="struct_d_m_a___stream___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_m_a___type_def.html">DMA_TypeDef</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_t_h___type_def.html">ETH_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Ethernet MAC. <a href="struct_e_t_h___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_x_t_i___type_def.html">EXTI_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">External Interrupt/Event Controller. <a href="struct_e_x_t_i___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_l_a_s_h___type_def.html">FLASH_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">FLASH Registers. <a href="struct_f_l_a_s_h___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_s_m_c___bank1___type_def.html">FSMC_Bank1_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Flexible Static Memory Controller. <a href="struct_f_s_m_c___bank1___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_s_m_c___bank1_e___type_def.html">FSMC_Bank1E_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Flexible Static Memory Controller Bank1E. <a href="struct_f_s_m_c___bank1_e___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_s_m_c___bank2__3___type_def.html">FSMC_Bank2_3_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Flexible Static Memory Controller Bank2. <a href="struct_f_s_m_c___bank2__3___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_s_m_c___bank4___type_def.html">FSMC_Bank4_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Flexible Static Memory Controller Bank4. <a href="struct_f_s_m_c___bank4___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">General Purpose I/O. <a href="struct_g_p_i_o___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_y_s_c_f_g___type_def.html">SYSCFG_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">System configuration controller. <a href="struct_s_y_s_c_f_g___type_def.html#details">More...</a><br /></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i2_c___type_def.html">I2C_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Inter-integrated Circuit Interface. <a href="struct_i2_c___type_def.html#details">More...</a><br /></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i_w_d_g___type_def.html">IWDG_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Independent WATCHDOG. <a href="struct_i_w_d_g___type_def.html#details">More...</a><br /></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_p_w_r___type_def.html">PWR_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Power Control. <a href="struct_p_w_r___type_def.html#details">More...</a><br /></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_c_c___type_def.html">RCC_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Reset and Clock Control. <a href="struct_r_c_c___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_t_c___type_def.html">RTC_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Real-Time Clock. <a href="struct_r_t_c___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_d_i_o___type_def.html">SDIO_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">SD host Interface. <a href="struct_s_d_i_o___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_p_i___type_def.html">SPI_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Serial Peripheral Interface. <a href="struct_s_p_i___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">TIM. <a href="struct_t_i_m___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Universal Synchronous Asynchronous Receiver Transmitter. <a href="struct_u_s_a_r_t___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_w_w_d_g___type_def.html">WWDG_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Window WATCHDOG. <a href="struct_w_w_d_g___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_n_g___type_def.html">RNG_TypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">RNG. <a href="struct_r_n_g___type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_u_s_b___o_t_g___global_type_def.html">USB_OTG_GlobalTypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">USB_OTG_Core_Registers. <a href="struct_u_s_b___o_t_g___global_type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_u_s_b___o_t_g___device_type_def.html">USB_OTG_DeviceTypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">USB_OTG_device_Registers. <a href="struct_u_s_b___o_t_g___device_type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_u_s_b___o_t_g___i_n_endpoint_type_def.html">USB_OTG_INEndpointTypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">USB_OTG_IN_Endpoint-Specific_Register. <a href="struct_u_s_b___o_t_g___i_n_endpoint_type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_u_s_b___o_t_g___o_u_t_endpoint_type_def.html">USB_OTG_OUTEndpointTypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">USB_OTG_OUT_Endpoint-Specific_Registers. <a href="struct_u_s_b___o_t_g___o_u_t_endpoint_type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_u_s_b___o_t_g___host_type_def.html">USB_OTG_HostTypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">USB_OTG_Host_Mode_Register_Structures. <a href="struct_u_s_b___o_t_g___host_type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_u_s_b___o_t_g___host_channel_type_def.html">USB_OTG_HostChannelTypeDef</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">USB_OTG_Host_Channel_Specific_Registers. <a href="struct_u_s_b___o_t_g___host_channel_type_def.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct__memory.html">_memory</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:ga45a97e4bb8b6ce7c334acc5f45ace3ba" id="r_ga45a97e4bb8b6ce7c334acc5f45ace3ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___configuration__section__for___c_m_s_i_s.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba">__CM4_REV</a>   0x0001U</td></tr>
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<tr class="memdesc:ga45a97e4bb8b6ce7c334acc5f45ace3ba"><td class="mdescLeft"> </td><td class="mdescRight">Configuration of the Cortex-M4 Processor and Core Peripherals. <br /></td></tr>
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<tr class="separator:ga45a97e4bb8b6ce7c334acc5f45ace3ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4127d1b31aaf336fab3d7329d117f448" id="r_ga4127d1b31aaf336fab3d7329d117f448"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___configuration__section__for___c_m_s_i_s.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a>   1U</td></tr>
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<tr class="separator:ga4127d1b31aaf336fab3d7329d117f448"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3fe3587d5100c787e02102ce3944460" id="r_gae3fe3587d5100c787e02102ce3944460"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>   4U</td></tr>
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<tr class="separator:gae3fe3587d5100c787e02102ce3944460"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab58771b4ec03f9bdddc84770f7c95c68" id="r_gab58771b4ec03f9bdddc84770f7c95c68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___configuration__section__for___c_m_s_i_s.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a>   0U</td></tr>
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<tr class="separator:gab58771b4ec03f9bdddc84770f7c95c68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1ba8a48ca926bddc88be9bfd7d42641" id="r_gac1ba8a48ca926bddc88be9bfd7d42641"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___configuration__section__for___c_m_s_i_s.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a>   1U</td></tr>
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<tr class="separator:gac1ba8a48ca926bddc88be9bfd7d42641"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70479d84b2227bd03eca17d75ced09c1" id="r_ga70479d84b2227bd03eca17d75ced09c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__interrupt__number__definition.html#ga70479d84b2227bd03eca17d75ced09c1">HASH_RNG_IRQn</a>   <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a90c4647e57cff99fac635c532802c4b5">RNG_IRQn</a></td></tr>
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<tr class="separator:ga70479d84b2227bd03eca17d75ced09c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a1f7e664b3e091fee94976b33bbf7b9" id="r_ga4a1f7e664b3e091fee94976b33bbf7b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga4a1f7e664b3e091fee94976b33bbf7b9">FLASH_BASE_SHIFT</a>   0x08000000UL</td></tr>
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<tr class="separator:ga4a1f7e664b3e091fee94976b33bbf7b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77155e7666b070a9653f0a43d11f2004" id="r_ga77155e7666b070a9653f0a43d11f2004"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga77155e7666b070a9653f0a43d11f2004">FLASH_END_SHIFT</a>   0x080FFFFFUL</td></tr>
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<tr class="separator:ga77155e7666b070a9653f0a43d11f2004"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d06a3566d8983055baf9e883e0198ef" id="r_ga2d06a3566d8983055baf9e883e0198ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga2d06a3566d8983055baf9e883e0198ef">CCMDATARAM_BASE_SHIFT</a>   0x10000000UL</td></tr>
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<tr class="separator:ga2d06a3566d8983055baf9e883e0198ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86d258a24d1cef85ee0333fcaf6398a8" id="r_ga86d258a24d1cef85ee0333fcaf6398a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga86d258a24d1cef85ee0333fcaf6398a8">CCMDATARAM_END_SHIFT</a>   0x1000FFFFUL</td></tr>
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<tr class="separator:ga86d258a24d1cef85ee0333fcaf6398a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ea2ceeb2a729bb1072d98cf7c3ceb6e" id="r_ga1ea2ceeb2a729bb1072d98cf7c3ceb6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga1ea2ceeb2a729bb1072d98cf7c3ceb6e">FLASH_OTP_BASE_SHIFT</a>   0x1FFF7800UL</td></tr>
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<tr class="separator:ga1ea2ceeb2a729bb1072d98cf7c3ceb6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46ebe9214ddc2503af753a11fd5ccb80" id="r_ga46ebe9214ddc2503af753a11fd5ccb80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga46ebe9214ddc2503af753a11fd5ccb80">FLASH_OTP_END_SHIFT</a>   0x1FFF7A0FUL</td></tr>
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<tr class="separator:ga46ebe9214ddc2503af753a11fd5ccb80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac53e3a39a0ebd3520aaa373ae44ff838" id="r_gac53e3a39a0ebd3520aaa373ae44ff838"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gac53e3a39a0ebd3520aaa373ae44ff838">SRAM1_BASE_SHIFT</a>   0x20000000UL</td></tr>
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<tr class="separator:gac53e3a39a0ebd3520aaa373ae44ff838"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff8892343768799209d59c2c33848222" id="r_gaff8892343768799209d59c2c33848222"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaff8892343768799209d59c2c33848222">SRAM2_BASE_SHIFT</a>   0x2001C000UL</td></tr>
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<tr class="separator:gaff8892343768799209d59c2c33848222"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d4c99653d22992b3b4b1537ade15d21" id="r_ga9d4c99653d22992b3b4b1537ade15d21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga9d4c99653d22992b3b4b1537ade15d21">SRAM1_BB_BASE_SHIFT</a>   0x22000000UL</td></tr>
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<tr class="separator:ga9d4c99653d22992b3b4b1537ade15d21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1654496a485d04270e2208afa8e4fd5c" id="r_ga1654496a485d04270e2208afa8e4fd5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga1654496a485d04270e2208afa8e4fd5c">SRAM2_BB_BASE_SHIFT</a>   0x22380000UL</td></tr>
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<tr class="separator:ga1654496a485d04270e2208afa8e4fd5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1294c8e27eb23b591c5195504e4dfd23" id="r_ga1294c8e27eb23b591c5195504e4dfd23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga1294c8e27eb23b591c5195504e4dfd23">PERIPH_BASE_SHIFT</a>   0x40000000UL</td></tr>
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<tr class="separator:ga1294c8e27eb23b591c5195504e4dfd23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabac8d912551188d0039d016d16f7c0b0" id="r_gabac8d912551188d0039d016d16f7c0b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gabac8d912551188d0039d016d16f7c0b0">BKPSRAM_BASE_SHIFT</a>   0x40024000UL</td></tr>
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<tr class="separator:gabac8d912551188d0039d016d16f7c0b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33c4df718741b5cb60ca3fffe8969672" id="r_ga33c4df718741b5cb60ca3fffe8969672"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga33c4df718741b5cb60ca3fffe8969672">PERIPH_BB_BASE_SHIFT</a>   0x42000000UL</td></tr>
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<tr class="separator:ga33c4df718741b5cb60ca3fffe8969672"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa850b97b5338b2a9891acbf23788fd14" id="r_gaa850b97b5338b2a9891acbf23788fd14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaa850b97b5338b2a9891acbf23788fd14">BKPSRAM_BB_BASE_SHIFT</a>   0x42480000UL</td></tr>
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<tr class="separator:gaa850b97b5338b2a9891acbf23788fd14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae359dc044d8a99c9634a01abdbab704b" id="r_gae359dc044d8a99c9634a01abdbab704b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gae359dc044d8a99c9634a01abdbab704b">FSMC_R_BASE_SHIFT</a>   0xA0000000UL</td></tr>
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<tr class="separator:gae359dc044d8a99c9634a01abdbab704b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ddc1e9172ba6fe724328595a3fadcf2" id="r_ga4ddc1e9172ba6fe724328595a3fadcf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga4ddc1e9172ba6fe724328595a3fadcf2">MCU_MEM_END</a>   0xA0000FFFUL</td></tr>
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<tr class="separator:ga4ddc1e9172ba6fe724328595a3fadcf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71542ecbf91e5a2e4e7657ebf4743bb0" id="r_ga71542ecbf91e5a2e4e7657ebf4743bb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga71542ecbf91e5a2e4e7657ebf4743bb0">CCMDATARAM_SIZE</a>   0x10000UL /* (64 KB) */</td></tr>
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<tr class="separator:ga71542ecbf91e5a2e4e7657ebf4743bb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf1c7f7eb345f8e1b617fd1b16320111" id="r_gacf1c7f7eb345f8e1b617fd1b16320111"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gacf1c7f7eb345f8e1b617fd1b16320111">SRAM1_SIZE</a>   0x1C000UL /* (112 KB) */</td></tr>
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<tr class="separator:gacf1c7f7eb345f8e1b617fd1b16320111"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad89e757d25db6160b1aedeb58fcdac09" id="r_gad89e757d25db6160b1aedeb58fcdac09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad89e757d25db6160b1aedeb58fcdac09">SRAM2_SIZE</a>   0x4000UL /* (16 KB) */</td></tr>
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<tr class="separator:gad89e757d25db6160b1aedeb58fcdac09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe7470549838cd29d6f2d7245f17176c" id="r_gafe7470549838cd29d6f2d7245f17176c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gafe7470549838cd29d6f2d7245f17176c">BKPSRAM_SIZE</a>   0x1000UL /* (4 KB) */</td></tr>
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<tr class="separator:gafe7470549838cd29d6f2d7245f17176c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae69620948dea1b76e0ab7843ab719db7" id="r_gae69620948dea1b76e0ab7843ab719db7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gae69620948dea1b76e0ab7843ab719db7">FLASH_SIZE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga2d06a3566d8983055baf9e883e0198ef">CCMDATARAM_BASE_SHIFT</a> - <a class="el" href="group___peripheral__memory__map.html#ga4a1f7e664b3e091fee94976b33bbf7b9">FLASH_BASE_SHIFT</a>)</td></tr>
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<tr class="separator:gae69620948dea1b76e0ab7843ab719db7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb3e2951c91f038686e0cbcd4321814b" id="r_gacb3e2951c91f038686e0cbcd4321814b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gacb3e2951c91f038686e0cbcd4321814b">FLASH_OTP_SIZE</a>   (<a class="el" href="group___peripheral__memory__map.html#gac53e3a39a0ebd3520aaa373ae44ff838">SRAM1_BASE_SHIFT</a> - <a class="el" href="group___peripheral__memory__map.html#ga1ea2ceeb2a729bb1072d98cf7c3ceb6e">FLASH_OTP_BASE_SHIFT</a>)</td></tr>
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<tr class="separator:gacb3e2951c91f038686e0cbcd4321814b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d759a2722aeeb47a81dd047d4e1790e" id="r_ga4d759a2722aeeb47a81dd047d4e1790e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga4d759a2722aeeb47a81dd047d4e1790e">SRAM1_BB_SIZE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga1654496a485d04270e2208afa8e4fd5c">SRAM2_BB_BASE_SHIFT</a> - <a class="el" href="group___peripheral__memory__map.html#ga9d4c99653d22992b3b4b1537ade15d21">SRAM1_BB_BASE_SHIFT</a>)</td></tr>
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<tr class="separator:ga4d759a2722aeeb47a81dd047d4e1790e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga146845582d93b1fa90c52f43f704c178" id="r_ga146845582d93b1fa90c52f43f704c178"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga146845582d93b1fa90c52f43f704c178">SRAM2_BB_SIZE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga1294c8e27eb23b591c5195504e4dfd23">PERIPH_BASE_SHIFT</a> - <a class="el" href="group___peripheral__memory__map.html#ga1654496a485d04270e2208afa8e4fd5c">SRAM2_BB_BASE_SHIFT</a>)</td></tr>
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<tr class="separator:ga146845582d93b1fa90c52f43f704c178"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf91d23524f40a61d32fea568949043d0" id="r_gaf91d23524f40a61d32fea568949043d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaf91d23524f40a61d32fea568949043d0">PERIPH_SIZE</a>   (<a class="el" href="group___peripheral__memory__map.html#gabac8d912551188d0039d016d16f7c0b0">BKPSRAM_BASE_SHIFT</a> - <a class="el" href="group___peripheral__memory__map.html#ga1294c8e27eb23b591c5195504e4dfd23">PERIPH_BASE_SHIFT</a>)</td></tr>
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<tr class="separator:gaf91d23524f40a61d32fea568949043d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16c53e8ec3bcf87a7d170220d774956c" id="r_ga16c53e8ec3bcf87a7d170220d774956c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga16c53e8ec3bcf87a7d170220d774956c">PERIPH_BB_SIZE</a>   (<a class="el" href="group___peripheral__memory__map.html#gaa850b97b5338b2a9891acbf23788fd14">BKPSRAM_BB_BASE_SHIFT</a> - <a class="el" href="group___peripheral__memory__map.html#ga33c4df718741b5cb60ca3fffe8969672">PERIPH_BB_BASE_SHIFT</a>)</td></tr>
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<tr class="separator:ga16c53e8ec3bcf87a7d170220d774956c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36147b9ef36c5be4745a45162cd85be4" id="r_ga36147b9ef36c5be4745a45162cd85be4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga36147b9ef36c5be4745a45162cd85be4">FSMC_R_SIZE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga4ddc1e9172ba6fe724328595a3fadcf2">MCU_MEM_END</a> - <a class="el" href="group___peripheral__memory__map.html#gae359dc044d8a99c9634a01abdbab704b">FSMC_R_BASE_SHIFT</a>)</td></tr>
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<tr class="separator:ga36147b9ef36c5be4745a45162cd85be4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23a9099a5f8fc9c6e253c0eecb2be8db" id="r_ga23a9099a5f8fc9c6e253c0eecb2be8db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga23a9099a5f8fc9c6e253c0eecb2be8db">FLASH_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gabea1f1810ebeac402164b42ab54bcdf9">MCU_MEM.CCMDATARAM_BASE</a>)</td></tr>
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<tr class="separator:ga23a9099a5f8fc9c6e253c0eecb2be8db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabea1f1810ebeac402164b42ab54bcdf9" id="r_gabea1f1810ebeac402164b42ab54bcdf9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gabea1f1810ebeac402164b42ab54bcdf9">CCMDATARAM_BASE</a>   (MCU_MEM.CCMDATARAM_BASE)</td></tr>
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<tr class="separator:gabea1f1810ebeac402164b42ab54bcdf9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d0fbfb8894012dbbb96754b95e562cd" id="r_ga7d0fbfb8894012dbbb96754b95e562cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga7d0fbfb8894012dbbb96754b95e562cd">SRAM1_BASE</a>   (MCU_MEM.SRAM1_BASE)</td></tr>
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<tr class="separator:ga7d0fbfb8894012dbbb96754b95e562cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbb42a3d0a8a90a79d2146e4014241b1" id="r_gadbb42a3d0a8a90a79d2146e4014241b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gadbb42a3d0a8a90a79d2146e4014241b1">SRAM2_BASE</a>   (MCU_MEM.SRAM2_BASE)</td></tr>
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<tr class="separator:gadbb42a3d0a8a90a79d2146e4014241b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9171f49478fa86d932f89e78e73b88b0" id="r_ga9171f49478fa86d932f89e78e73b88b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">PERIPH_BASE</a>   (MCU_MEM.PERIPH_BASE)</td></tr>
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<tr class="separator:ga9171f49478fa86d932f89e78e73b88b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52e57051bdf8909222b36e5408a48f32" id="r_ga52e57051bdf8909222b36e5408a48f32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga52e57051bdf8909222b36e5408a48f32">BKPSRAM_BASE</a>   (MCU_MEM.BKPSRAM_BASE)</td></tr>
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<tr class="separator:ga52e57051bdf8909222b36e5408a48f32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaddf0e199dccba83272b20c9fb4d3aaed" id="r_gaddf0e199dccba83272b20c9fb4d3aaed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaddf0e199dccba83272b20c9fb4d3aaed">FSMC_R_BASE</a>   (MCU_MEM.FSMC_R_BASE)</td></tr>
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<tr class="separator:gaddf0e199dccba83272b20c9fb4d3aaed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4c4f61082e4b168f29d9cf97dc3ca5c" id="r_gac4c4f61082e4b168f29d9cf97dc3ca5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gac4c4f61082e4b168f29d9cf97dc3ca5c">SRAM1_BB_BASE</a>   (MCU_MEM.SRAM1_BB_BASE)</td></tr>
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<tr class="separator:gac4c4f61082e4b168f29d9cf97dc3ca5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac33cb6edadf184ab9860d77089503922" id="r_gac33cb6edadf184ab9860d77089503922"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gac33cb6edadf184ab9860d77089503922">SRAM2_BB_BASE</a>   (MCU_MEM.SRAM2_BB_BASE)</td></tr>
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<tr class="separator:gac33cb6edadf184ab9860d77089503922"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed7efc100877000845c236ccdc9e144a" id="r_gaed7efc100877000845c236ccdc9e144a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a>   (MCU_MEM.PERIPH_BB_BASE)</td></tr>
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<tr class="separator:gaed7efc100877000845c236ccdc9e144a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee19a30c9fa326bb10b547e4eaf4e250" id="r_gaee19a30c9fa326bb10b547e4eaf4e250"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaee19a30c9fa326bb10b547e4eaf4e250">BKPSRAM_BB_BASE</a>   (MCU_MEM.BKPSRAM_BB_BASE)</td></tr>
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<tr class="separator:gaee19a30c9fa326bb10b547e4eaf4e250"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8be554f354e5aa65370f6db63d4f3ee4" id="r_ga8be554f354e5aa65370f6db63d4f3ee4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga8be554f354e5aa65370f6db63d4f3ee4">FLASH_END</a>   (MCU_MEM.FLASH_END)</td></tr>
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<tr class="separator:ga8be554f354e5aa65370f6db63d4f3ee4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91d296a67aec0da8f31c368cbc0eea94" id="r_ga91d296a67aec0da8f31c368cbc0eea94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga91d296a67aec0da8f31c368cbc0eea94">FLASH_OTP_BASE</a>   (MCU_MEM.FLASH_OTP_BASE)</td></tr>
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<tr class="separator:ga91d296a67aec0da8f31c368cbc0eea94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bec9c5a91e312fca36f256f508ceee1" id="r_ga5bec9c5a91e312fca36f256f508ceee1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga5bec9c5a91e312fca36f256f508ceee1">FLASH_OTP_END</a>   (MCU_MEM.FLASH_OTP_END)</td></tr>
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<tr class="separator:ga5bec9c5a91e312fca36f256f508ceee1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fbe263946209e6f09faf93512bd2f9a" id="r_ga9fbe263946209e6f09faf93512bd2f9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga9fbe263946209e6f09faf93512bd2f9a">CCMDATARAM_END</a>   (MCU_MEM.CCMDATARAM_END)</td></tr>
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<tr class="separator:ga9fbe263946209e6f09faf93512bd2f9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05e8f3d2e5868754a7cd88614955aecc" id="r_ga05e8f3d2e5868754a7cd88614955aecc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga05e8f3d2e5868754a7cd88614955aecc">SRAM_BASE</a>   <a class="el" href="group___peripheral__memory__map.html#ga7d0fbfb8894012dbbb96754b95e562cd">SRAM1_BASE</a></td></tr>
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<tr class="separator:ga05e8f3d2e5868754a7cd88614955aecc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3548b6e2f017f39d399358f3ac98454" id="r_gad3548b6e2f017f39d399358f3ac98454"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad3548b6e2f017f39d399358f3ac98454">SRAM_BB_BASE</a>   <a class="el" href="group___peripheral__memory__map.html#gac4c4f61082e4b168f29d9cf97dc3ca5c">SRAM1_BB_BASE</a></td></tr>
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<tr class="separator:gad3548b6e2f017f39d399358f3ac98454"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45666d911f39addd4c8c0a0ac3388cfb" id="r_ga45666d911f39addd4c8c0a0ac3388cfb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a>   <a class="el" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">PERIPH_BASE</a></td></tr>
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<tr class="separator:ga45666d911f39addd4c8c0a0ac3388cfb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25b99d6065f1c8f751e78f43ade652cb" id="r_ga25b99d6065f1c8f751e78f43ade652cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">PERIPH_BASE</a> + 0x00010000UL)</td></tr>
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<tr class="separator:ga25b99d6065f1c8f751e78f43ade652cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga811a9a4ca17f0a50354a9169541d56c4" id="r_ga811a9a4ca17f0a50354a9169541d56c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">PERIPH_BASE</a> + 0x00020000UL)</td></tr>
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<tr class="separator:ga811a9a4ca17f0a50354a9169541d56c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeedaa71d22a1948492365e2cd26cfd46" id="r_gaeedaa71d22a1948492365e2cd26cfd46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaeedaa71d22a1948492365e2cd26cfd46">AHB2PERIPH_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">PERIPH_BASE</a> + 0x10000000UL)</td></tr>
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<tr class="separator:gaeedaa71d22a1948492365e2cd26cfd46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00d0fe6ad532ab32f0f81cafca8d3aa5" id="r_ga00d0fe6ad532ab32f0f81cafca8d3aa5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga00d0fe6ad532ab32f0f81cafca8d3aa5">TIM2_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x0000UL)</td></tr>
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<tr class="separator:ga00d0fe6ad532ab32f0f81cafca8d3aa5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0c34a518f87e1e505cd2332e989564a" id="r_gaf0c34a518f87e1e505cd2332e989564a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaf0c34a518f87e1e505cd2332e989564a">TIM3_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x0400UL)</td></tr>
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<tr class="separator:gaf0c34a518f87e1e505cd2332e989564a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56e2d44b0002f316527b8913866a370d" id="r_ga56e2d44b0002f316527b8913866a370d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga56e2d44b0002f316527b8913866a370d">TIM4_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x0800UL)</td></tr>
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<tr class="separator:ga56e2d44b0002f316527b8913866a370d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e1671477190d065ba7c944558336d7e" id="r_ga3e1671477190d065ba7c944558336d7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga3e1671477190d065ba7c944558336d7e">TIM5_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x0C00UL)</td></tr>
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<tr class="separator:ga3e1671477190d065ba7c944558336d7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8268ec947929f192559f28c6bf7d1eac" id="r_ga8268ec947929f192559f28c6bf7d1eac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga8268ec947929f192559f28c6bf7d1eac">TIM6_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x1000UL)</td></tr>
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<tr class="separator:ga8268ec947929f192559f28c6bf7d1eac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ebf54364c6a2be6eb19ded6b18b6387" id="r_ga0ebf54364c6a2be6eb19ded6b18b6387"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga0ebf54364c6a2be6eb19ded6b18b6387">TIM7_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x1400UL)</td></tr>
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<tr class="separator:ga0ebf54364c6a2be6eb19ded6b18b6387"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33dea32fadbaecea161c2ef7927992fd" id="r_ga33dea32fadbaecea161c2ef7927992fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga33dea32fadbaecea161c2ef7927992fd">TIM12_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x1800UL)</td></tr>
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<tr class="separator:ga33dea32fadbaecea161c2ef7927992fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad20f79948e9359125a40bbf6ed063590" id="r_gad20f79948e9359125a40bbf6ed063590"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad20f79948e9359125a40bbf6ed063590">TIM13_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x1C00UL)</td></tr>
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<tr class="separator:gad20f79948e9359125a40bbf6ed063590"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga862855347d6e1d92730dfe17ee8e90b8" id="r_ga862855347d6e1d92730dfe17ee8e90b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga862855347d6e1d92730dfe17ee8e90b8">TIM14_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x2000UL)</td></tr>
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<tr class="separator:ga862855347d6e1d92730dfe17ee8e90b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4265e665d56225412e57a61d87417022" id="r_ga4265e665d56225412e57a61d87417022"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga4265e665d56225412e57a61d87417022">RTC_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x2800UL)</td></tr>
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<tr class="separator:ga4265e665d56225412e57a61d87417022"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a5bf4728ab93dea5b569f5b972cbe62" id="r_ga9a5bf4728ab93dea5b569f5b972cbe62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga9a5bf4728ab93dea5b569f5b972cbe62">WWDG_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x2C00UL)</td></tr>
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<tr class="separator:ga9a5bf4728ab93dea5b569f5b972cbe62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8543ee4997296af5536b007cd4748f55" id="r_ga8543ee4997296af5536b007cd4748f55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga8543ee4997296af5536b007cd4748f55">IWDG_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x3000UL)</td></tr>
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<tr class="separator:ga8543ee4997296af5536b007cd4748f55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5f7b241ed5b756decd835300c9e7bc9" id="r_gaa5f7b241ed5b756decd835300c9e7bc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaa5f7b241ed5b756decd835300c9e7bc9">I2S2ext_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x3400UL)</td></tr>
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<tr class="separator:gaa5f7b241ed5b756decd835300c9e7bc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3e357b4c25106ed375fb1affab6bb86" id="r_gac3e357b4c25106ed375fb1affab6bb86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gac3e357b4c25106ed375fb1affab6bb86">SPI2_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x3800UL)</td></tr>
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<tr class="separator:gac3e357b4c25106ed375fb1affab6bb86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae634fe8faa6922690e90fbec2fc86162" id="r_gae634fe8faa6922690e90fbec2fc86162"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gae634fe8faa6922690e90fbec2fc86162">SPI3_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x3C00UL)</td></tr>
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<tr class="separator:gae634fe8faa6922690e90fbec2fc86162"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89b61d6e6b09e94f3fccb7bef34e0263" id="r_ga89b61d6e6b09e94f3fccb7bef34e0263"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga89b61d6e6b09e94f3fccb7bef34e0263">I2S3ext_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x4000UL)</td></tr>
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<tr class="separator:ga89b61d6e6b09e94f3fccb7bef34e0263"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade83162a04bca0b15b39018a8e8ec090" id="r_gade83162a04bca0b15b39018a8e8ec090"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gade83162a04bca0b15b39018a8e8ec090">USART2_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x4400UL)</td></tr>
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<tr class="separator:gade83162a04bca0b15b39018a8e8ec090"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe0d6539ac0026d598274ee7f45b0251" id="r_gabe0d6539ac0026d598274ee7f45b0251"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gabe0d6539ac0026d598274ee7f45b0251">USART3_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x4800UL)</td></tr>
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<tr class="separator:gabe0d6539ac0026d598274ee7f45b0251"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94d92270bf587ccdc3a37a5bb5d20467" id="r_ga94d92270bf587ccdc3a37a5bb5d20467"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga94d92270bf587ccdc3a37a5bb5d20467">UART4_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x4C00UL)</td></tr>
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<tr class="separator:ga94d92270bf587ccdc3a37a5bb5d20467"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa155689c0e206e6994951dc3cf31052a" id="r_gaa155689c0e206e6994951dc3cf31052a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaa155689c0e206e6994951dc3cf31052a">UART5_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x5000UL)</td></tr>
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<tr class="separator:gaa155689c0e206e6994951dc3cf31052a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd72dbffb1738ca87c838545c4eb85a3" id="r_gacd72dbffb1738ca87c838545c4eb85a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gacd72dbffb1738ca87c838545c4eb85a3">I2C1_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x5400UL)</td></tr>
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<tr class="separator:gacd72dbffb1738ca87c838545c4eb85a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04bda70f25c795fb79f163b633ad4a5d" id="r_ga04bda70f25c795fb79f163b633ad4a5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga04bda70f25c795fb79f163b633ad4a5d">I2C2_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x5800UL)</td></tr>
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<tr class="separator:ga04bda70f25c795fb79f163b633ad4a5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e8b9198748235a1729e1e8f8f24983b" id="r_ga4e8b9198748235a1729e1e8f8f24983b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga4e8b9198748235a1729e1e8f8f24983b">I2C3_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x5C00UL)</td></tr>
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<tr class="separator:ga4e8b9198748235a1729e1e8f8f24983b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8e45ea6c032d9fce1b0516fff9d8eaa" id="r_gad8e45ea6c032d9fce1b0516fff9d8eaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad8e45ea6c032d9fce1b0516fff9d8eaa">CAN1_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x6400UL)</td></tr>
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<tr class="separator:gad8e45ea6c032d9fce1b0516fff9d8eaa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7b8267b0d439f8f3e82f86be4b9fba1" id="r_gaf7b8267b0d439f8f3e82f86be4b9fba1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaf7b8267b0d439f8f3e82f86be4b9fba1">CAN2_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x6800UL)</td></tr>
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<tr class="separator:gaf7b8267b0d439f8f3e82f86be4b9fba1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac691ec23dace8b7a649a25acb110217a" id="r_gac691ec23dace8b7a649a25acb110217a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gac691ec23dace8b7a649a25acb110217a">PWR_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x7000UL)</td></tr>
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<tr class="separator:gac691ec23dace8b7a649a25acb110217a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad18d0b914c7f68cecbee1a2d23a67d38" id="r_gad18d0b914c7f68cecbee1a2d23a67d38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad18d0b914c7f68cecbee1a2d23a67d38">DAC_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb">APB1PERIPH_BASE</a> + 0x7400UL)</td></tr>
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<tr class="separator:gad18d0b914c7f68cecbee1a2d23a67d38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8aa324ca5011b8173ab16585ed7324a" id="r_gaf8aa324ca5011b8173ab16585ed7324a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaf8aa324ca5011b8173ab16585ed7324a">TIM1_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x0000UL)</td></tr>
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<tr class="separator:gaf8aa324ca5011b8173ab16585ed7324a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b72f698b7a048a6f9fcfe2efe5bc1db" id="r_ga5b72f698b7a048a6f9fcfe2efe5bc1db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga5b72f698b7a048a6f9fcfe2efe5bc1db">TIM8_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x0400UL)</td></tr>
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<tr class="separator:ga5b72f698b7a048a6f9fcfe2efe5bc1db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86162ab3f740db9026c1320d46938b4d" id="r_ga86162ab3f740db9026c1320d46938b4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga86162ab3f740db9026c1320d46938b4d">USART1_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x1000UL)</td></tr>
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<tr class="separator:ga86162ab3f740db9026c1320d46938b4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade4d3907fd0387ee832f426f52d568bb" id="r_gade4d3907fd0387ee832f426f52d568bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gade4d3907fd0387ee832f426f52d568bb">USART6_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x1400UL)</td></tr>
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<tr class="separator:gade4d3907fd0387ee832f426f52d568bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga695c9a2f892363a1c942405c8d351b91" id="r_ga695c9a2f892363a1c942405c8d351b91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga695c9a2f892363a1c942405c8d351b91">ADC1_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x2000UL)</td></tr>
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<tr class="separator:ga695c9a2f892363a1c942405c8d351b91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6544abc57f9759f610eee09a02442ae6" id="r_ga6544abc57f9759f610eee09a02442ae6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga6544abc57f9759f610eee09a02442ae6">ADC2_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x2100UL)</td></tr>
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<tr class="separator:ga6544abc57f9759f610eee09a02442ae6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca766f86c8e0b00a8e2b0224dcbb4c82" id="r_gaca766f86c8e0b00a8e2b0224dcbb4c82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaca766f86c8e0b00a8e2b0224dcbb4c82">ADC3_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x2200UL)</td></tr>
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<tr class="separator:gaca766f86c8e0b00a8e2b0224dcbb4c82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58b9980508ab28022e3be7edc4eda72e" id="r_ga58b9980508ab28022e3be7edc4eda72e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga58b9980508ab28022e3be7edc4eda72e">ADC123_COMMON_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x2300UL)</td></tr>
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<tr class="separator:ga58b9980508ab28022e3be7edc4eda72e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad06cb9e5985bd216a376f26f22303cd6" id="r_gad06cb9e5985bd216a376f26f22303cd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad06cb9e5985bd216a376f26f22303cd6">ADC_BASE</a>   <a class="el" href="group___peripheral__memory__map.html#ga58b9980508ab28022e3be7edc4eda72e">ADC123_COMMON_BASE</a></td></tr>
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<tr class="memitem:ga95dd0abbc6767893b4b02935fa846f52" id="r_ga95dd0abbc6767893b4b02935fa846f52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga95dd0abbc6767893b4b02935fa846f52">SDIO_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x2C00UL)</td></tr>
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<tr class="separator:ga95dd0abbc6767893b4b02935fa846f52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50cd8b47929f18b05efbd0f41253bf8d" id="r_ga50cd8b47929f18b05efbd0f41253bf8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga50cd8b47929f18b05efbd0f41253bf8d">SPI1_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x3000UL)</td></tr>
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<tr class="separator:ga50cd8b47929f18b05efbd0f41253bf8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62246020bf3b34b6a4d8d0e84ec79d3d" id="r_ga62246020bf3b34b6a4d8d0e84ec79d3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga62246020bf3b34b6a4d8d0e84ec79d3d">SYSCFG_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x3800UL)</td></tr>
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<tr class="separator:ga62246020bf3b34b6a4d8d0e84ec79d3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87371508b3bcdcd98cd1ec629be29061" id="r_ga87371508b3bcdcd98cd1ec629be29061"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga87371508b3bcdcd98cd1ec629be29061">EXTI_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x3C00UL)</td></tr>
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<tr class="separator:ga87371508b3bcdcd98cd1ec629be29061"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92ae902be7902560939223dd765ece08" id="r_ga92ae902be7902560939223dd765ece08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga92ae902be7902560939223dd765ece08">TIM9_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x4000UL)</td></tr>
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<tr class="separator:ga92ae902be7902560939223dd765ece08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3eff32f3801db31fb4b61d5618cad54a" id="r_ga3eff32f3801db31fb4b61d5618cad54a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga3eff32f3801db31fb4b61d5618cad54a">TIM10_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x4400UL)</td></tr>
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<tr class="separator:ga3eff32f3801db31fb4b61d5618cad54a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a4a06bb84c703084f0509e105ffaf1d" id="r_ga3a4a06bb84c703084f0509e105ffaf1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga3a4a06bb84c703084f0509e105ffaf1d">TIM11_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb">APB2PERIPH_BASE</a> + 0x4800UL)</td></tr>
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<tr class="separator:ga3a4a06bb84c703084f0509e105ffaf1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7723846cc5db8e43a44d78cf21f6efa" id="r_gad7723846cc5db8e43a44d78cf21f6efa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad7723846cc5db8e43a44d78cf21f6efa">GPIOA_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x0000UL)</td></tr>
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<tr class="separator:gad7723846cc5db8e43a44d78cf21f6efa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac944a89eb789000ece920c0f89cb6a68" id="r_gac944a89eb789000ece920c0f89cb6a68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gac944a89eb789000ece920c0f89cb6a68">GPIOB_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x0400UL)</td></tr>
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<tr class="separator:gac944a89eb789000ece920c0f89cb6a68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26f267dc35338eef219544c51f1e6b3f" id="r_ga26f267dc35338eef219544c51f1e6b3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga26f267dc35338eef219544c51f1e6b3f">GPIOC_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x0800UL)</td></tr>
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<tr class="separator:ga26f267dc35338eef219544c51f1e6b3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a93ab27129f04064089616910c296ec" id="r_ga1a93ab27129f04064089616910c296ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga1a93ab27129f04064089616910c296ec">GPIOD_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x0C00UL)</td></tr>
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<tr class="separator:ga1a93ab27129f04064089616910c296ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab487b1983d936c4fee3e9e88b95aad9d" id="r_gab487b1983d936c4fee3e9e88b95aad9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gab487b1983d936c4fee3e9e88b95aad9d">GPIOE_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x1000UL)</td></tr>
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<tr class="separator:gab487b1983d936c4fee3e9e88b95aad9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f9a3f4223a1a784af464a114978d26e" id="r_ga7f9a3f4223a1a784af464a114978d26e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga7f9a3f4223a1a784af464a114978d26e">GPIOF_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x1400UL)</td></tr>
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<tr class="separator:ga7f9a3f4223a1a784af464a114978d26e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d8ca4020f2e8c00bde974e8e7c13cfe" id="r_ga5d8ca4020f2e8c00bde974e8e7c13cfe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga5d8ca4020f2e8c00bde974e8e7c13cfe">GPIOG_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x1800UL)</td></tr>
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<tr class="separator:ga5d8ca4020f2e8c00bde974e8e7c13cfe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee4716389f3a1c727495375b76645608" id="r_gaee4716389f3a1c727495375b76645608"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaee4716389f3a1c727495375b76645608">GPIOH_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x1C00UL)</td></tr>
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<tr class="separator:gaee4716389f3a1c727495375b76645608"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50acf918c2e1c4597d5ccfe25eb3ad3d" id="r_ga50acf918c2e1c4597d5ccfe25eb3ad3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga50acf918c2e1c4597d5ccfe25eb3ad3d">GPIOI_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x2000UL)</td></tr>
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<tr class="separator:ga50acf918c2e1c4597d5ccfe25eb3ad3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga656a447589e785594cbf2f45c835ad7e" id="r_ga656a447589e785594cbf2f45c835ad7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga656a447589e785594cbf2f45c835ad7e">CRC_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x3000UL)</td></tr>
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<tr class="separator:ga656a447589e785594cbf2f45c835ad7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e681b03f364532055d88f63fec0d99d" id="r_ga0e681b03f364532055d88f63fec0d99d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga0e681b03f364532055d88f63fec0d99d">RCC_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x3800UL)</td></tr>
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<tr class="separator:ga0e681b03f364532055d88f63fec0d99d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e21f4845015730c5731763169ec0e9b" id="r_ga8e21f4845015730c5731763169ec0e9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga8e21f4845015730c5731763169ec0e9b">FLASH_R_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x3C00UL)</td></tr>
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<tr class="separator:ga8e21f4845015730c5731763169ec0e9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2d8a917a0e4ea99a22ac6ebf279bc72" id="r_gab2d8a917a0e4ea99a22ac6ebf279bc72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72">DMA1_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x6000UL)</td></tr>
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<tr class="separator:gab2d8a917a0e4ea99a22ac6ebf279bc72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d3c52aa35dcc68f78b704dfde57ba95" id="r_ga0d3c52aa35dcc68f78b704dfde57ba95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga0d3c52aa35dcc68f78b704dfde57ba95">DMA1_Stream0_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72">DMA1_BASE</a> + 0x010UL)</td></tr>
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<tr class="separator:ga0d3c52aa35dcc68f78b704dfde57ba95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b4152cef577e37eccc9311d8bdbf3c2" id="r_ga5b4152cef577e37eccc9311d8bdbf3c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga5b4152cef577e37eccc9311d8bdbf3c2">DMA1_Stream1_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72">DMA1_BASE</a> + 0x028UL)</td></tr>
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<tr class="separator:ga5b4152cef577e37eccc9311d8bdbf3c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48a551ee91d3f07dd74347fdb35c703d" id="r_ga48a551ee91d3f07dd74347fdb35c703d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga48a551ee91d3f07dd74347fdb35c703d">DMA1_Stream2_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72">DMA1_BASE</a> + 0x040UL)</td></tr>
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<tr class="separator:ga48a551ee91d3f07dd74347fdb35c703d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac51deb54ff7cfe1290dfcf517ae67127" id="r_gac51deb54ff7cfe1290dfcf517ae67127"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gac51deb54ff7cfe1290dfcf517ae67127">DMA1_Stream3_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72">DMA1_BASE</a> + 0x058UL)</td></tr>
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<tr class="separator:gac51deb54ff7cfe1290dfcf517ae67127"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga757a3c0d866c0fe68c6176156065a26b" id="r_ga757a3c0d866c0fe68c6176156065a26b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga757a3c0d866c0fe68c6176156065a26b">DMA1_Stream4_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72">DMA1_BASE</a> + 0x070UL)</td></tr>
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<tr class="separator:ga757a3c0d866c0fe68c6176156065a26b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ded7bed8969fe2e2d616e7f90eb7654" id="r_ga0ded7bed8969fe2e2d616e7f90eb7654"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga0ded7bed8969fe2e2d616e7f90eb7654">DMA1_Stream5_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72">DMA1_BASE</a> + 0x088UL)</td></tr>
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<tr class="separator:ga0ded7bed8969fe2e2d616e7f90eb7654"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58998ddc40adb6361704d6c9dad08125" id="r_ga58998ddc40adb6361704d6c9dad08125"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga58998ddc40adb6361704d6c9dad08125">DMA1_Stream6_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72">DMA1_BASE</a> + 0x0A0UL)</td></tr>
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<tr class="separator:ga58998ddc40adb6361704d6c9dad08125"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82186dd6d3f60995d428b34c041919d7" id="r_ga82186dd6d3f60995d428b34c041919d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga82186dd6d3f60995d428b34c041919d7">DMA1_Stream7_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72">DMA1_BASE</a> + 0x0B8UL)</td></tr>
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<tr class="separator:ga82186dd6d3f60995d428b34c041919d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab72a9ae145053ee13d1d491fb5c1df64" id="r_gab72a9ae145053ee13d1d491fb5c1df64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64">DMA2_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x6400UL)</td></tr>
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<tr class="separator:gab72a9ae145053ee13d1d491fb5c1df64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4c67b24726ba6b94d03adb351bcec4d" id="r_gac4c67b24726ba6b94d03adb351bcec4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gac4c67b24726ba6b94d03adb351bcec4d">DMA2_Stream0_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64">DMA2_BASE</a> + 0x010UL)</td></tr>
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<tr class="memitem:ga35512bdc3f5e9df4557c2fbe7935d0b1" id="r_ga35512bdc3f5e9df4557c2fbe7935d0b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga35512bdc3f5e9df4557c2fbe7935d0b1">DMA2_Stream1_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64">DMA2_BASE</a> + 0x028UL)</td></tr>
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<tr class="memitem:gaed33a06f08188466f2ede06160984e9a" id="r_gaed33a06f08188466f2ede06160984e9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaed33a06f08188466f2ede06160984e9a">DMA2_Stream2_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64">DMA2_BASE</a> + 0x040UL)</td></tr>
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<tr class="memitem:gaf3a9480e08c6ae94f4482e0cdaebdd17" id="r_gaf3a9480e08c6ae94f4482e0cdaebdd17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaf3a9480e08c6ae94f4482e0cdaebdd17">DMA2_Stream3_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64">DMA2_BASE</a> + 0x058UL)</td></tr>
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<tr class="separator:gaf3a9480e08c6ae94f4482e0cdaebdd17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1e67740e6301233473f64638145dd1f" id="r_gad1e67740e6301233473f64638145dd1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad1e67740e6301233473f64638145dd1f">DMA2_Stream4_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64">DMA2_BASE</a> + 0x070UL)</td></tr>
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<tr class="memitem:gaed1460fdc407b6decfbffccb0260d0af" id="r_gaed1460fdc407b6decfbffccb0260d0af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaed1460fdc407b6decfbffccb0260d0af">DMA2_Stream5_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64">DMA2_BASE</a> + 0x088UL)</td></tr>
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<tr class="separator:gaed1460fdc407b6decfbffccb0260d0af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e81174c96fd204fa7c82c815e85c8e6" id="r_ga5e81174c96fd204fa7c82c815e85c8e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga5e81174c96fd204fa7c82c815e85c8e6">DMA2_Stream6_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64">DMA2_BASE</a> + 0x0A0UL)</td></tr>
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<tr class="separator:ga5e81174c96fd204fa7c82c815e85c8e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9faa708ad2440d24eb1064cba9bb06d" id="r_gaa9faa708ad2440d24eb1064cba9bb06d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaa9faa708ad2440d24eb1064cba9bb06d">DMA2_Stream7_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64">DMA2_BASE</a> + 0x0B8UL)</td></tr>
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<tr class="separator:gaa9faa708ad2440d24eb1064cba9bb06d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad965a7b1106ece575ed3da10c45c65cc" id="r_gad965a7b1106ece575ed3da10c45c65cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad965a7b1106ece575ed3da10c45c65cc">ETH_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4">AHB1PERIPH_BASE</a> + 0x8000UL)</td></tr>
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<tr class="separator:gad965a7b1106ece575ed3da10c45c65cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cf7005808feb61bff1fee01e50a711a" id="r_ga3cf7005808feb61bff1fee01e50a711a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga3cf7005808feb61bff1fee01e50a711a">ETH_MAC_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gad965a7b1106ece575ed3da10c45c65cc">ETH_BASE</a>)</td></tr>
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<tr class="separator:ga3cf7005808feb61bff1fee01e50a711a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4946f2b3b03f7998343ac1778fbcf725" id="r_ga4946f2b3b03f7998343ac1778fbcf725"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga4946f2b3b03f7998343ac1778fbcf725">ETH_MMC_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gad965a7b1106ece575ed3da10c45c65cc">ETH_BASE</a> + 0x0100UL)</td></tr>
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<tr class="separator:ga4946f2b3b03f7998343ac1778fbcf725"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0f60b922aeb7275c785cbaa8f94ecf0" id="r_gaa0f60b922aeb7275c785cbaa8f94ecf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaa0f60b922aeb7275c785cbaa8f94ecf0">ETH_PTP_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gad965a7b1106ece575ed3da10c45c65cc">ETH_BASE</a> + 0x0700UL)</td></tr>
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<tr class="separator:gaa0f60b922aeb7275c785cbaa8f94ecf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace2114e1b37c1ba88d60f3e831b67e93" id="r_gace2114e1b37c1ba88d60f3e831b67e93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gace2114e1b37c1ba88d60f3e831b67e93">ETH_DMA_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gad965a7b1106ece575ed3da10c45c65cc">ETH_BASE</a> + 0x1000UL)</td></tr>
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<tr class="separator:gace2114e1b37c1ba88d60f3e831b67e93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55b794507e021135486de57129a2505c" id="r_ga55b794507e021135486de57129a2505c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga55b794507e021135486de57129a2505c">DCMI_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gaeedaa71d22a1948492365e2cd26cfd46">AHB2PERIPH_BASE</a> + 0x50000UL)</td></tr>
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<tr class="separator:ga55b794507e021135486de57129a2505c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab92662976cfe62457141e5b4f83d541c" id="r_gab92662976cfe62457141e5b4f83d541c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gab92662976cfe62457141e5b4f83d541c">RNG_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gaeedaa71d22a1948492365e2cd26cfd46">AHB2PERIPH_BASE</a> + 0x60800UL)</td></tr>
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<tr class="separator:gab92662976cfe62457141e5b4f83d541c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad196fe6f5e4041b201d14f43508c06d2" id="r_gad196fe6f5e4041b201d14f43508c06d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad196fe6f5e4041b201d14f43508c06d2">FSMC_Bank1_R_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gaddf0e199dccba83272b20c9fb4d3aaed">FSMC_R_BASE</a> + 0x0000UL)</td></tr>
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<tr class="separator:gad196fe6f5e4041b201d14f43508c06d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea182589c84aee30b7f735474d8774e2" id="r_gaea182589c84aee30b7f735474d8774e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaea182589c84aee30b7f735474d8774e2">FSMC_Bank1E_R_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gaddf0e199dccba83272b20c9fb4d3aaed">FSMC_R_BASE</a> + 0x0104UL)</td></tr>
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<tr class="separator:gaea182589c84aee30b7f735474d8774e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga851707a200f63e03c336073706fdce1d" id="r_ga851707a200f63e03c336073706fdce1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga851707a200f63e03c336073706fdce1d">FSMC_Bank2_3_R_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gaddf0e199dccba83272b20c9fb4d3aaed">FSMC_R_BASE</a> + 0x0060UL)</td></tr>
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<tr class="separator:ga851707a200f63e03c336073706fdce1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9e5417133160b0bdd0498d982acec19" id="r_gaf9e5417133160b0bdd0498d982acec19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaf9e5417133160b0bdd0498d982acec19">FSMC_Bank4_R_BASE</a>   (<a class="el" href="group___peripheral__memory__map.html#gaddf0e199dccba83272b20c9fb4d3aaed">FSMC_R_BASE</a> + 0x00A0UL)</td></tr>
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<tr class="separator:gaf9e5417133160b0bdd0498d982acec19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4adaf4fd82ccc3a538f1f27a70cdbbef" id="r_ga4adaf4fd82ccc3a538f1f27a70cdbbef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga4adaf4fd82ccc3a538f1f27a70cdbbef">DBGMCU_BASE</a>   (&<a class="el" href="stm32f4xx__matlab__conf_8c.html#a85a080726cb1ade56443b458fc49404b">DEBUG_MCU</a>)</td></tr>
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<tr class="separator:ga4adaf4fd82ccc3a538f1f27a70cdbbef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa405d2ebfd7e9394237b6639f16a5409" id="r_gaa405d2ebfd7e9394237b6639f16a5409"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaa405d2ebfd7e9394237b6639f16a5409">USB_OTG_HS_PERIPH_BASE</a>   0x40040000UL</td></tr>
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<tr class="separator:gaa405d2ebfd7e9394237b6639f16a5409"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa86d4c80849a74938924e73937b904e7" id="r_gaa86d4c80849a74938924e73937b904e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaa86d4c80849a74938924e73937b904e7">USB_OTG_FS_PERIPH_BASE</a>   0x50000000UL</td></tr>
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<tr class="separator:gaa86d4c80849a74938924e73937b904e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga044aa4388e72d9d47a03f387fb8926fb" id="r_ga044aa4388e72d9d47a03f387fb8926fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga044aa4388e72d9d47a03f387fb8926fb">USB_OTG_GLOBAL_BASE</a>   0x000UL</td></tr>
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<tr class="separator:ga044aa4388e72d9d47a03f387fb8926fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d74a337597a77b1fca978202b519a18" id="r_ga4d74a337597a77b1fca978202b519a18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga4d74a337597a77b1fca978202b519a18">USB_OTG_DEVICE_BASE</a>   0x800UL</td></tr>
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<tr class="separator:ga4d74a337597a77b1fca978202b519a18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8f69041452615aeb3948600e3882246" id="r_gad8f69041452615aeb3948600e3882246"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gad8f69041452615aeb3948600e3882246">USB_OTG_IN_ENDPOINT_BASE</a>   0x900UL</td></tr>
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<tr class="separator:gad8f69041452615aeb3948600e3882246"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0e972b8f028ecf44a652029efbd4642" id="r_gaf0e972b8f028ecf44a652029efbd4642"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaf0e972b8f028ecf44a652029efbd4642">USB_OTG_OUT_ENDPOINT_BASE</a>   0xB00UL</td></tr>
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<tr class="separator:gaf0e972b8f028ecf44a652029efbd4642"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6fdb7429ad88e2d69440d6ecc4f4199e" id="r_ga6fdb7429ad88e2d69440d6ecc4f4199e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga6fdb7429ad88e2d69440d6ecc4f4199e">USB_OTG_EP_REG_SIZE</a>   0x20UL</td></tr>
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<tr class="separator:ga6fdb7429ad88e2d69440d6ecc4f4199e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bb2dd6c82eefd8587b6146ba36ae071" id="r_ga3bb2dd6c82eefd8587b6146ba36ae071"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga3bb2dd6c82eefd8587b6146ba36ae071">USB_OTG_HOST_BASE</a>   0x400UL</td></tr>
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<tr class="separator:ga3bb2dd6c82eefd8587b6146ba36ae071"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42f433cb79ca69f09972e690fda6737a" id="r_ga42f433cb79ca69f09972e690fda6737a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga42f433cb79ca69f09972e690fda6737a">USB_OTG_HOST_PORT_BASE</a>   0x440UL</td></tr>
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<tr class="separator:ga42f433cb79ca69f09972e690fda6737a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga942c8c5241b80fbcf638fea0fa18bebd" id="r_ga942c8c5241b80fbcf638fea0fa18bebd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga942c8c5241b80fbcf638fea0fa18bebd">USB_OTG_HOST_CHANNEL_BASE</a>   0x500UL</td></tr>
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<tr class="separator:ga942c8c5241b80fbcf638fea0fa18bebd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga266cb1dbb50faf447f9c15d2ee93a522" id="r_ga266cb1dbb50faf447f9c15d2ee93a522"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga266cb1dbb50faf447f9c15d2ee93a522">USB_OTG_HOST_CHANNEL_SIZE</a>   0x20UL</td></tr>
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<tr class="separator:ga266cb1dbb50faf447f9c15d2ee93a522"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9766975aca084c257730879568bc7cf" id="r_gaa9766975aca084c257730879568bc7cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaa9766975aca084c257730879568bc7cf">USB_OTG_PCGCCTL_BASE</a>   0xE00UL</td></tr>
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<tr class="separator:gaa9766975aca084c257730879568bc7cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace340350802904868673f0e839c4fa04" id="r_gace340350802904868673f0e839c4fa04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gace340350802904868673f0e839c4fa04">USB_OTG_FIFO_BASE</a>   0x1000UL</td></tr>
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<tr class="separator:gace340350802904868673f0e839c4fa04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8781c4b2406c740d9fe540737a6a0188" id="r_ga8781c4b2406c740d9fe540737a6a0188"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga8781c4b2406c740d9fe540737a6a0188">USB_OTG_FIFO_SIZE</a>   0x1000UL</td></tr>
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<tr class="separator:ga8781c4b2406c740d9fe540737a6a0188"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga664eda42b83c919b153b07b23348be67" id="r_ga664eda42b83c919b153b07b23348be67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga664eda42b83c919b153b07b23348be67">UID_BASE</a>   0x1FFF7A10UL</td></tr>
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<tr class="separator:ga664eda42b83c919b153b07b23348be67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga776d985f2d4d40b588ef6ca9d573af78" id="r_ga776d985f2d4d40b588ef6ca9d573af78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga776d985f2d4d40b588ef6ca9d573af78">FLASHSIZE_BASE</a>   0x1FFF7A22UL</td></tr>
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<tr class="memitem:ga88fc8a2912bd1ac72c6eddb456f0b096" id="r_ga88fc8a2912bd1ac72c6eddb456f0b096"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga88fc8a2912bd1ac72c6eddb456f0b096">PACKAGE_BASE</a>   0x1FFF7BF0UL</td></tr>
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<tr class="memitem:ga3cfac9f2e43673f790f8668d48b4b92b" id="r_ga3cfac9f2e43673f790f8668d48b4b92b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga3cfac9f2e43673f790f8668d48b4b92b">TIM2</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga00d0fe6ad532ab32f0f81cafca8d3aa5">TIM2_BASE</a>)</td></tr>
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<tr class="memitem:ga61ee4c391385607d7af432b63905fcc9" id="r_ga61ee4c391385607d7af432b63905fcc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga61ee4c391385607d7af432b63905fcc9">TIM3</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaf0c34a518f87e1e505cd2332e989564a">TIM3_BASE</a>)</td></tr>
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<tr class="memitem:ga91a09bad8bdc7a1cb3d85cf49c94c8ec" id="r_ga91a09bad8bdc7a1cb3d85cf49c94c8ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga91a09bad8bdc7a1cb3d85cf49c94c8ec">TIM4</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga56e2d44b0002f316527b8913866a370d">TIM4_BASE</a>)</td></tr>
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<tr class="memitem:ga5125ff6a23a2ed66e2e19bd196128c14" id="r_ga5125ff6a23a2ed66e2e19bd196128c14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga5125ff6a23a2ed66e2e19bd196128c14">TIM5</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga3e1671477190d065ba7c944558336d7e">TIM5_BASE</a>)</td></tr>
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<tr class="memitem:gac7b4ed55f9201b498b38c962cca97314" id="r_gac7b4ed55f9201b498b38c962cca97314"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gac7b4ed55f9201b498b38c962cca97314">TIM6</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga8268ec947929f192559f28c6bf7d1eac">TIM6_BASE</a>)</td></tr>
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<tr class="memitem:ga49267c49946fd61db6af8b49bcf16394" id="r_ga49267c49946fd61db6af8b49bcf16394"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga49267c49946fd61db6af8b49bcf16394">TIM7</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga0ebf54364c6a2be6eb19ded6b18b6387">TIM7_BASE</a>)</td></tr>
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<tr class="memitem:ga2397f8a0f8e7aa10cf8e8c049e431e53" id="r_ga2397f8a0f8e7aa10cf8e8c049e431e53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga2397f8a0f8e7aa10cf8e8c049e431e53">TIM12</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga33dea32fadbaecea161c2ef7927992fd">TIM12_BASE</a>)</td></tr>
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<tr class="memitem:ga5a959a833074d59bf6cc7fb437c65b18" id="r_ga5a959a833074d59bf6cc7fb437c65b18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga5a959a833074d59bf6cc7fb437c65b18">TIM13</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gad20f79948e9359125a40bbf6ed063590">TIM13_BASE</a>)</td></tr>
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<tr class="memitem:ga2dd30f46fad69dd73e1d8941a43daffe" id="r_ga2dd30f46fad69dd73e1d8941a43daffe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga2dd30f46fad69dd73e1d8941a43daffe">TIM14</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga862855347d6e1d92730dfe17ee8e90b8">TIM14_BASE</a>)</td></tr>
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<tr class="memitem:ga5359a088f5d8b20ce74d920e46059304" id="r_ga5359a088f5d8b20ce74d920e46059304"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga5359a088f5d8b20ce74d920e46059304">RTC</a>   ((<a class="el" href="struct_r_t_c___type_def.html">RTC_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga4265e665d56225412e57a61d87417022">RTC_BASE</a>)</td></tr>
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<tr class="memitem:ga9821fd01757986612ddb8982e2fe27f1" id="r_ga9821fd01757986612ddb8982e2fe27f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga9821fd01757986612ddb8982e2fe27f1">WWDG</a>   ((<a class="el" href="struct_w_w_d_g___type_def.html">WWDG_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga9a5bf4728ab93dea5b569f5b972cbe62">WWDG_BASE</a>)</td></tr>
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<tr class="memitem:gad16b79dd94ee85d261d08a8ee94187e7" id="r_gad16b79dd94ee85d261d08a8ee94187e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gad16b79dd94ee85d261d08a8ee94187e7">IWDG</a>   ((<a class="el" href="struct_i_w_d_g___type_def.html">IWDG_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga8543ee4997296af5536b007cd4748f55">IWDG_BASE</a>)</td></tr>
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<tr class="memitem:ga9efe6de71871a01dd38abcb229f30c02" id="r_ga9efe6de71871a01dd38abcb229f30c02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga9efe6de71871a01dd38abcb229f30c02">I2S2ext</a>   ((<a class="el" href="struct_s_p_i___type_def.html">SPI_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaa5f7b241ed5b756decd835300c9e7bc9">I2S2ext_BASE</a>)</td></tr>
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<tr class="memitem:gaf2c3d8ce359dcfbb2261e07ed42af72b" id="r_gaf2c3d8ce359dcfbb2261e07ed42af72b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gaf2c3d8ce359dcfbb2261e07ed42af72b">SPI2</a>   ((<a class="el" href="struct_s_p_i___type_def.html">SPI_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gac3e357b4c25106ed375fb1affab6bb86">SPI2_BASE</a>)</td></tr>
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<tr class="memitem:gab2339cbf25502bf562b19208b1b257fc" id="r_gab2339cbf25502bf562b19208b1b257fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gab2339cbf25502bf562b19208b1b257fc">SPI3</a>   ((<a class="el" href="struct_s_p_i___type_def.html">SPI_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gae634fe8faa6922690e90fbec2fc86162">SPI3_BASE</a>)</td></tr>
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<tr class="memitem:ga15b3a03302ed53911099c5216da0b1cf" id="r_ga15b3a03302ed53911099c5216da0b1cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga15b3a03302ed53911099c5216da0b1cf">I2S3ext</a>   ((<a class="el" href="struct_s_p_i___type_def.html">SPI_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga89b61d6e6b09e94f3fccb7bef34e0263">I2S3ext_BASE</a>)</td></tr>
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<tr class="memitem:gaf114a9eab03ca08a6fb720e511595930" id="r_gaf114a9eab03ca08a6fb720e511595930"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gaf114a9eab03ca08a6fb720e511595930">USART2</a>   ((<a class="el" href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gade83162a04bca0b15b39018a8e8ec090">USART2_BASE</a>)</td></tr>
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<tr class="memitem:ga2350115553c1fe0a7bc14e6a7ec6a225" id="r_ga2350115553c1fe0a7bc14e6a7ec6a225"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga2350115553c1fe0a7bc14e6a7ec6a225">USART3</a>   ((<a class="el" href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gabe0d6539ac0026d598274ee7f45b0251">USART3_BASE</a>)</td></tr>
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<tr class="memitem:ga7c035f6f443c999fc043b2b7fb598800" id="r_ga7c035f6f443c999fc043b2b7fb598800"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga7c035f6f443c999fc043b2b7fb598800">UART4</a>   ((<a class="el" href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga94d92270bf587ccdc3a37a5bb5d20467">UART4_BASE</a>)</td></tr>
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<tr class="memitem:ga9274e37cf5e8a174fc5dd627b98ec0fe" id="r_ga9274e37cf5e8a174fc5dd627b98ec0fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga9274e37cf5e8a174fc5dd627b98ec0fe">UART5</a>   ((<a class="el" href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaa155689c0e206e6994951dc3cf31052a">UART5_BASE</a>)</td></tr>
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<tr class="memitem:gab45d257574da6fe1f091cc45b7eda6cc" id="r_gab45d257574da6fe1f091cc45b7eda6cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gab45d257574da6fe1f091cc45b7eda6cc">I2C1</a>   ((<a class="el" href="struct_i2_c___type_def.html">I2C_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gacd72dbffb1738ca87c838545c4eb85a3">I2C1_BASE</a>)</td></tr>
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<tr class="memitem:gafa60ac20c1921ef1002083bb3e1f5d16" id="r_gafa60ac20c1921ef1002083bb3e1f5d16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gafa60ac20c1921ef1002083bb3e1f5d16">I2C2</a>   ((<a class="el" href="struct_i2_c___type_def.html">I2C_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga04bda70f25c795fb79f163b633ad4a5d">I2C2_BASE</a>)</td></tr>
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<tr class="memitem:ga1489b37ed2bca9d9c659119590583bda" id="r_ga1489b37ed2bca9d9c659119590583bda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga1489b37ed2bca9d9c659119590583bda">I2C3</a>   ((<a class="el" href="struct_i2_c___type_def.html">I2C_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga4e8b9198748235a1729e1e8f8f24983b">I2C3_BASE</a>)</td></tr>
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<tr class="memitem:ga4964ecb6a5c689aaf8ee2832b8093aac" id="r_ga4964ecb6a5c689aaf8ee2832b8093aac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga4964ecb6a5c689aaf8ee2832b8093aac">CAN1</a>   ((<a class="el" href="struct_c_a_n___type_def.html">CAN_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gad8e45ea6c032d9fce1b0516fff9d8eaa">CAN1_BASE</a>)</td></tr>
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<tr class="memitem:gac5e4c86ed487dc91418b156e24808033" id="r_gac5e4c86ed487dc91418b156e24808033"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gac5e4c86ed487dc91418b156e24808033">CAN2</a>   ((<a class="el" href="struct_c_a_n___type_def.html">CAN_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaf7b8267b0d439f8f3e82f86be4b9fba1">CAN2_BASE</a>)</td></tr>
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<tr class="memitem:ga04651c526497822a859942b928e57f8e" id="r_ga04651c526497822a859942b928e57f8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga04651c526497822a859942b928e57f8e">PWR</a>   ((<a class="el" href="struct_p_w_r___type_def.html">PWR_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gac691ec23dace8b7a649a25acb110217a">PWR_BASE</a>)</td></tr>
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<tr class="memitem:gaffb5ff8779fa698f3c7165a617d56e4f" id="r_gaffb5ff8779fa698f3c7165a617d56e4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gaffb5ff8779fa698f3c7165a617d56e4f">DAC1</a>   ((<a class="el" href="struct_d_a_c___type_def.html">DAC_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gad18d0b914c7f68cecbee1a2d23a67d38">DAC_BASE</a>)</td></tr>
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<tr class="memitem:ga4aa2a4ab86ce00c23035e5cee2e7fc7e" id="r_ga4aa2a4ab86ce00c23035e5cee2e7fc7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga4aa2a4ab86ce00c23035e5cee2e7fc7e">DAC</a>   ((<a class="el" href="struct_d_a_c___type_def.html">DAC_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gad18d0b914c7f68cecbee1a2d23a67d38">DAC_BASE</a>) /* Kept for legacy purpose */</td></tr>
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<tr class="memitem:ga2e87451fea8dc9380056d3cfc5ed81fb" id="r_ga2e87451fea8dc9380056d3cfc5ed81fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga2e87451fea8dc9380056d3cfc5ed81fb">TIM1</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaf8aa324ca5011b8173ab16585ed7324a">TIM1_BASE</a>)</td></tr>
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<tr class="memitem:ga9a3660400b17735e91331f256095810e" id="r_ga9a3660400b17735e91331f256095810e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga9a3660400b17735e91331f256095810e">TIM8</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga5b72f698b7a048a6f9fcfe2efe5bc1db">TIM8_BASE</a>)</td></tr>
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<tr class="memitem:ga92871691058ff7ccffd7635930cb08da" id="r_ga92871691058ff7ccffd7635930cb08da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga92871691058ff7ccffd7635930cb08da">USART1</a>   ((<a class="el" href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga86162ab3f740db9026c1320d46938b4d">USART1_BASE</a>)</td></tr>
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<tr class="memitem:ga2dab39a19ce3dd05fe360dcbb7b5dc84" id="r_ga2dab39a19ce3dd05fe360dcbb7b5dc84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga2dab39a19ce3dd05fe360dcbb7b5dc84">USART6</a>   ((<a class="el" href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gade4d3907fd0387ee832f426f52d568bb">USART6_BASE</a>)</td></tr>
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<tr class="memitem:ga90d2d5c526ce5c0a551f533eccbee71a" id="r_ga90d2d5c526ce5c0a551f533eccbee71a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga90d2d5c526ce5c0a551f533eccbee71a">ADC1</a>   ((<a class="el" href="struct_a_d_c___type_def.html">ADC_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga695c9a2f892363a1c942405c8d351b91">ADC1_BASE</a>)</td></tr>
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<tr class="memitem:gac5503ae96c26b4475226f96715a1bf1e" id="r_gac5503ae96c26b4475226f96715a1bf1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gac5503ae96c26b4475226f96715a1bf1e">ADC2</a>   ((<a class="el" href="struct_a_d_c___type_def.html">ADC_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga6544abc57f9759f610eee09a02442ae6">ADC2_BASE</a>)</td></tr>
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<tr class="memitem:gae917784606daf6b04c9b7b96b40c2f74" id="r_gae917784606daf6b04c9b7b96b40c2f74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gae917784606daf6b04c9b7b96b40c2f74">ADC3</a>   ((<a class="el" href="struct_a_d_c___type_def.html">ADC_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaca766f86c8e0b00a8e2b0224dcbb4c82">ADC3_BASE</a>)</td></tr>
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<tr class="memitem:ga813de18391e45c0854aafd470c2d547f" id="r_ga813de18391e45c0854aafd470c2d547f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga813de18391e45c0854aafd470c2d547f">ADC123_COMMON</a>   ((<a class="el" href="struct_a_d_c___common___type_def.html">ADC_Common_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga58b9980508ab28022e3be7edc4eda72e">ADC123_COMMON_BASE</a>)</td></tr>
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<tr class="memitem:ga54d148b91f3d356713f7e367a2243bea" id="r_ga54d148b91f3d356713f7e367a2243bea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga54d148b91f3d356713f7e367a2243bea">ADC</a>   <a class="el" href="group___peripheral__declaration.html#ga813de18391e45c0854aafd470c2d547f">ADC123_COMMON</a></td></tr>
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<tr class="memitem:ga8149aa2760fffac16bc75216d5fd9331" id="r_ga8149aa2760fffac16bc75216d5fd9331"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga8149aa2760fffac16bc75216d5fd9331">SDIO</a>   ((<a class="el" href="struct_s_d_i_o___type_def.html">SDIO_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga95dd0abbc6767893b4b02935fa846f52">SDIO_BASE</a>)</td></tr>
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<tr class="memitem:gad483be344a28ac800be8f03654a9612f" id="r_gad483be344a28ac800be8f03654a9612f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gad483be344a28ac800be8f03654a9612f">SPI1</a>   ((<a class="el" href="struct_s_p_i___type_def.html">SPI_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga50cd8b47929f18b05efbd0f41253bf8d">SPI1_BASE</a>)</td></tr>
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<tr class="memitem:ga3c833fe1c486cb62250ccbca32899cb8" id="r_ga3c833fe1c486cb62250ccbca32899cb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga3c833fe1c486cb62250ccbca32899cb8">SYSCFG</a>   ((<a class="el" href="struct_s_y_s_c_f_g___type_def.html">SYSCFG_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga62246020bf3b34b6a4d8d0e84ec79d3d">SYSCFG_BASE</a>)</td></tr>
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<tr class="memitem:ga9189e770cd9b63dadd36683eb9843cac" id="r_ga9189e770cd9b63dadd36683eb9843cac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga9189e770cd9b63dadd36683eb9843cac">EXTI</a>   ((<a class="el" href="struct_e_x_t_i___type_def.html">EXTI_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga87371508b3bcdcd98cd1ec629be29061">EXTI_BASE</a>)</td></tr>
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<tr class="memitem:gaf52b4b4c36110a0addfa98059f54a50e" id="r_gaf52b4b4c36110a0addfa98059f54a50e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gaf52b4b4c36110a0addfa98059f54a50e">TIM9</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga92ae902be7902560939223dd765ece08">TIM9_BASE</a>)</td></tr>
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<tr class="memitem:ga46b2ad3f5f506f0f8df0d2ec3e767267" id="r_ga46b2ad3f5f506f0f8df0d2ec3e767267"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga46b2ad3f5f506f0f8df0d2ec3e767267">TIM10</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga3eff32f3801db31fb4b61d5618cad54a">TIM10_BASE</a>)</td></tr>
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<tr class="memitem:gacfd11ef966c7165f57e2cebe0abc71ad" id="r_gacfd11ef966c7165f57e2cebe0abc71ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gacfd11ef966c7165f57e2cebe0abc71ad">TIM11</a>   ((<a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga3a4a06bb84c703084f0509e105ffaf1d">TIM11_BASE</a>)</td></tr>
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<tr class="memitem:gac485358099728ddae050db37924dd6b7" id="r_gac485358099728ddae050db37924dd6b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gac485358099728ddae050db37924dd6b7">GPIOA</a>   ((<a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gad7723846cc5db8e43a44d78cf21f6efa">GPIOA_BASE</a>)</td></tr>
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<tr class="memitem:ga68b66ac73be4c836db878a42e1fea3cd" id="r_ga68b66ac73be4c836db878a42e1fea3cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga68b66ac73be4c836db878a42e1fea3cd">GPIOB</a>   ((<a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gac944a89eb789000ece920c0f89cb6a68">GPIOB_BASE</a>)</td></tr>
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<tr class="memitem:ga2dca03332d620196ba943bc2346eaa08" id="r_ga2dca03332d620196ba943bc2346eaa08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga2dca03332d620196ba943bc2346eaa08">GPIOC</a>   ((<a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga26f267dc35338eef219544c51f1e6b3f">GPIOC_BASE</a>)</td></tr>
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<tr class="memitem:ga7580b1a929ea9df59725ba9c18eba6ac" id="r_ga7580b1a929ea9df59725ba9c18eba6ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga7580b1a929ea9df59725ba9c18eba6ac">GPIOD</a>   ((<a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga1a93ab27129f04064089616910c296ec">GPIOD_BASE</a>)</td></tr>
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<tr class="memitem:gae04bdb5e8acc47cab1d0532e6b0d0763" id="r_gae04bdb5e8acc47cab1d0532e6b0d0763"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gae04bdb5e8acc47cab1d0532e6b0d0763">GPIOE</a>   ((<a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gab487b1983d936c4fee3e9e88b95aad9d">GPIOE_BASE</a>)</td></tr>
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<tr class="memitem:ga43c3022dede7c9db7a58d3c3409dbc8d" id="r_ga43c3022dede7c9db7a58d3c3409dbc8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga43c3022dede7c9db7a58d3c3409dbc8d">GPIOF</a>   ((<a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga7f9a3f4223a1a784af464a114978d26e">GPIOF_BASE</a>)</td></tr>
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<tr class="memitem:ga02a2a23a32f9b02166a8c64012842414" id="r_ga02a2a23a32f9b02166a8c64012842414"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga02a2a23a32f9b02166a8c64012842414">GPIOG</a>   ((<a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga5d8ca4020f2e8c00bde974e8e7c13cfe">GPIOG_BASE</a>)</td></tr>
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<tr class="memitem:gadeacbb43ae86c879945afe98c679b285" id="r_gadeacbb43ae86c879945afe98c679b285"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gadeacbb43ae86c879945afe98c679b285">GPIOH</a>   ((<a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaee4716389f3a1c727495375b76645608">GPIOH_BASE</a>)</td></tr>
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<tr class="memitem:gad15f13545ecdbbabfccf43d5997e5ade" id="r_gad15f13545ecdbbabfccf43d5997e5ade"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gad15f13545ecdbbabfccf43d5997e5ade">GPIOI</a>   ((<a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga50acf918c2e1c4597d5ccfe25eb3ad3d">GPIOI_BASE</a>)</td></tr>
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<tr class="memitem:ga4381bb54c2dbc34500521165aa7b89b1" id="r_ga4381bb54c2dbc34500521165aa7b89b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga4381bb54c2dbc34500521165aa7b89b1">CRC</a>   ((<a class="el" href="struct_c_r_c___type_def.html">CRC_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga656a447589e785594cbf2f45c835ad7e">CRC_BASE</a>)</td></tr>
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<tr class="memitem:ga74944438a086975793d26ae48d5882d4" id="r_ga74944438a086975793d26ae48d5882d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga74944438a086975793d26ae48d5882d4">RCC</a>   ((<a class="el" href="struct_r_c_c___type_def.html">RCC_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga0e681b03f364532055d88f63fec0d99d">RCC_BASE</a>)</td></tr>
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<tr class="memitem:ga844ea28ba1e0a5a0e497f16b61ea306b" id="r_ga844ea28ba1e0a5a0e497f16b61ea306b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga844ea28ba1e0a5a0e497f16b61ea306b">FLASH</a>   ((<a class="el" href="struct_f_l_a_s_h___type_def.html">FLASH_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga8e21f4845015730c5731763169ec0e9b">FLASH_R_BASE</a>)</td></tr>
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<tr class="memitem:gacc16d2a5937f7585320a98f7f6b578f9" id="r_gacc16d2a5937f7585320a98f7f6b578f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gacc16d2a5937f7585320a98f7f6b578f9">DMA1</a>   ((<a class="el" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72">DMA1_BASE</a>)</td></tr>
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<tr class="memitem:ga61247dd5d594289c404dd8774202dfd8" id="r_ga61247dd5d594289c404dd8774202dfd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga61247dd5d594289c404dd8774202dfd8">DMA1_Stream0</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga0d3c52aa35dcc68f78b704dfde57ba95">DMA1_Stream0_BASE</a>)</td></tr>
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<tr class="memitem:gaf7d82f110f19982d483eebc465d222b2" id="r_gaf7d82f110f19982d483eebc465d222b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gaf7d82f110f19982d483eebc465d222b2">DMA1_Stream1</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga5b4152cef577e37eccc9311d8bdbf3c2">DMA1_Stream1_BASE</a>)</td></tr>
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<tr class="memitem:gad0e2140b8eeec3594035f1a7bf2a7250" id="r_gad0e2140b8eeec3594035f1a7bf2a7250"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gad0e2140b8eeec3594035f1a7bf2a7250">DMA1_Stream2</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga48a551ee91d3f07dd74347fdb35c703d">DMA1_Stream2_BASE</a>)</td></tr>
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<tr class="memitem:ga96ac1af7a92469fe86a9fbdec091f25d" id="r_ga96ac1af7a92469fe86a9fbdec091f25d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga96ac1af7a92469fe86a9fbdec091f25d">DMA1_Stream3</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gac51deb54ff7cfe1290dfcf517ae67127">DMA1_Stream3_BASE</a>)</td></tr>
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<tr class="memitem:ga87df45f4b82e0b3a8c1b17f1a77aecdb" id="r_ga87df45f4b82e0b3a8c1b17f1a77aecdb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga87df45f4b82e0b3a8c1b17f1a77aecdb">DMA1_Stream4</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga757a3c0d866c0fe68c6176156065a26b">DMA1_Stream4_BASE</a>)</td></tr>
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<tr class="memitem:gac3abc20f80e25c19b02104ad34eae652" id="r_gac3abc20f80e25c19b02104ad34eae652"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gac3abc20f80e25c19b02104ad34eae652">DMA1_Stream5</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga0ded7bed8969fe2e2d616e7f90eb7654">DMA1_Stream5_BASE</a>)</td></tr>
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<tr class="memitem:gac95127480470900755953f1cfe68567d" id="r_gac95127480470900755953f1cfe68567d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gac95127480470900755953f1cfe68567d">DMA1_Stream6</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga58998ddc40adb6361704d6c9dad08125">DMA1_Stream6_BASE</a>)</td></tr>
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<tr class="memitem:ga8ecdeaf43d0f4207dab1fdb4d7bf8d26" id="r_ga8ecdeaf43d0f4207dab1fdb4d7bf8d26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga8ecdeaf43d0f4207dab1fdb4d7bf8d26">DMA1_Stream7</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga82186dd6d3f60995d428b34c041919d7">DMA1_Stream7_BASE</a>)</td></tr>
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<tr class="memitem:ga506520140eec1708bc7570c49bdf972d" id="r_ga506520140eec1708bc7570c49bdf972d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga506520140eec1708bc7570c49bdf972d">DMA2</a>   ((<a class="el" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64">DMA2_BASE</a>)</td></tr>
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<tr class="memitem:ga3a2efe5fd7a7a79be3b08a1670bbd016" id="r_ga3a2efe5fd7a7a79be3b08a1670bbd016"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga3a2efe5fd7a7a79be3b08a1670bbd016">DMA2_Stream0</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gac4c67b24726ba6b94d03adb351bcec4d">DMA2_Stream0_BASE</a>)</td></tr>
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<tr class="memitem:gae96f15d34d3c41c16fce69bc2878151a" id="r_gae96f15d34d3c41c16fce69bc2878151a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gae96f15d34d3c41c16fce69bc2878151a">DMA2_Stream1</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga35512bdc3f5e9df4557c2fbe7935d0b1">DMA2_Stream1_BASE</a>)</td></tr>
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<tr class="memitem:ga71bb410664b861ff0520f08976e24ee1" id="r_ga71bb410664b861ff0520f08976e24ee1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga71bb410664b861ff0520f08976e24ee1">DMA2_Stream2</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaed33a06f08188466f2ede06160984e9a">DMA2_Stream2_BASE</a>)</td></tr>
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<tr class="memitem:gaa6ead6a5ca6b8df70b5505aaeec6fd2e" id="r_gaa6ead6a5ca6b8df70b5505aaeec6fd2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gaa6ead6a5ca6b8df70b5505aaeec6fd2e">DMA2_Stream3</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaf3a9480e08c6ae94f4482e0cdaebdd17">DMA2_Stream3_BASE</a>)</td></tr>
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<tr class="memitem:gae32674772021620800275dd3b6d62c2f" id="r_gae32674772021620800275dd3b6d62c2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gae32674772021620800275dd3b6d62c2f">DMA2_Stream4</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gad1e67740e6301233473f64638145dd1f">DMA2_Stream4_BASE</a>)</td></tr>
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<tr class="memitem:gac40f58718761251875b5a897287efd83" id="r_gac40f58718761251875b5a897287efd83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gac40f58718761251875b5a897287efd83">DMA2_Stream5</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaed1460fdc407b6decfbffccb0260d0af">DMA2_Stream5_BASE</a>)</td></tr>
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<tr class="memitem:ga11a00b283e0911cd427e277e5a314ccc" id="r_ga11a00b283e0911cd427e277e5a314ccc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga11a00b283e0911cd427e277e5a314ccc">DMA2_Stream6</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga5e81174c96fd204fa7c82c815e85c8e6">DMA2_Stream6_BASE</a>)</td></tr>
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<tr class="memitem:gacc135dbca0eca67d5aa0abc555f053ce" id="r_gacc135dbca0eca67d5aa0abc555f053ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#gacc135dbca0eca67d5aa0abc555f053ce">DMA2_Stream7</a>   ((<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaa9faa708ad2440d24eb1064cba9bb06d">DMA2_Stream7_BASE</a>)</td></tr>
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<tr class="memitem:ga3a3f60de4318afbd0b3318e7a416aadc" id="r_ga3a3f60de4318afbd0b3318e7a416aadc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga3a3f60de4318afbd0b3318e7a416aadc">ETH</a>   ((<a class="el" href="struct_e_t_h___type_def.html">ETH_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gad965a7b1106ece575ed3da10c45c65cc">ETH_BASE</a>)</td></tr>
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<tr class="memitem:ga049d9f61cb078d642e68f3c22bb6d90c" id="r_ga049d9f61cb078d642e68f3c22bb6d90c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga049d9f61cb078d642e68f3c22bb6d90c">DCMI</a>   ((<a class="el" href="struct_d_c_m_i___type_def.html">DCMI_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga55b794507e021135486de57129a2505c">DCMI_BASE</a>)</td></tr>
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<tr class="memitem:ga5b0885b8b55bbc13691092b704d9309f" id="r_ga5b0885b8b55bbc13691092b704d9309f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga5b0885b8b55bbc13691092b704d9309f">RNG</a>   ((<a class="el" href="struct_r_n_g___type_def.html">RNG_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gab92662976cfe62457141e5b4f83d541c">RNG_BASE</a>)</td></tr>
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<tr class="memitem:ga2a759bad07fe730c99f9e1490e646220" id="r_ga2a759bad07fe730c99f9e1490e646220"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga2a759bad07fe730c99f9e1490e646220">FSMC_Bank1</a>   ((<a class="el" href="struct_f_s_m_c___bank1___type_def.html">FSMC_Bank1_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gad196fe6f5e4041b201d14f43508c06d2">FSMC_Bank1_R_BASE</a>)</td></tr>
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<tr class="memitem:ga422986101f42a8811ae89ac69deb2759" id="r_ga422986101f42a8811ae89ac69deb2759"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga422986101f42a8811ae89ac69deb2759">FSMC_Bank1E</a>   ((<a class="el" href="struct_f_s_m_c___bank1_e___type_def.html">FSMC_Bank1E_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaea182589c84aee30b7f735474d8774e2">FSMC_Bank1E_R_BASE</a>)</td></tr>
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<tr class="memitem:ga37d7365ac249959b103d7b91d74e776d" id="r_ga37d7365ac249959b103d7b91d74e776d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga37d7365ac249959b103d7b91d74e776d">FSMC_Bank2_3</a>   ((<a class="el" href="struct_f_s_m_c___bank2__3___type_def.html">FSMC_Bank2_3_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga851707a200f63e03c336073706fdce1d">FSMC_Bank2_3_R_BASE</a>)</td></tr>
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<tr class="memitem:ga5aa00e4ac522693c6a21bc23ef5a96df" id="r_ga5aa00e4ac522693c6a21bc23ef5a96df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga5aa00e4ac522693c6a21bc23ef5a96df">FSMC_Bank4</a>   ((<a class="el" href="struct_f_s_m_c___bank4___type_def.html">FSMC_Bank4_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaf9e5417133160b0bdd0498d982acec19">FSMC_Bank4_R_BASE</a>)</td></tr>
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<tr class="memitem:ga92ec6d9ec2251fda7d4ce09748cd74b4" id="r_ga92ec6d9ec2251fda7d4ce09748cd74b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga92ec6d9ec2251fda7d4ce09748cd74b4">DBGMCU</a>   ((<a class="el" href="struct_d_b_g_m_c_u___type_def.html">DBGMCU_TypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#ga4adaf4fd82ccc3a538f1f27a70cdbbef">DBGMCU_BASE</a>)</td></tr>
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<tr class="memitem:ga9ebb053ee138fb47cdfede0e3371123d" id="r_ga9ebb053ee138fb47cdfede0e3371123d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga9ebb053ee138fb47cdfede0e3371123d">USB_OTG_FS</a>   ((<a class="el" href="struct_u_s_b___o_t_g___global_type_def.html">USB_OTG_GlobalTypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaa86d4c80849a74938924e73937b904e7">USB_OTG_FS_PERIPH_BASE</a>)</td></tr>
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<tr class="memitem:ga820f5f7cb0a7af72a2444a1903fd83bc" id="r_ga820f5f7cb0a7af72a2444a1903fd83bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__declaration.html#ga820f5f7cb0a7af72a2444a1903fd83bc">USB_OTG_HS</a>   ((<a class="el" href="struct_u_s_b___o_t_g___global_type_def.html">USB_OTG_GlobalTypeDef</a> *) <a class="el" href="group___peripheral__memory__map.html#gaa405d2ebfd7e9394237b6639f16a5409">USB_OTG_HS_PERIPH_BASE</a>)</td></tr>
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<tr class="memitem:gab9ea77371b070034ca2a56381a7e9de7" id="r_gab9ea77371b070034ca2a56381a7e9de7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___hardware___constant___definition.html#gab9ea77371b070034ca2a56381a7e9de7">LSI_STARTUP_TIME</a>   40U</td></tr>
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<tr class="memitem:ga4e2d417bccd8d576e16729c3e5a25cb8" id="r_ga4e2d417bccd8d576e16729c3e5a25cb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e2d417bccd8d576e16729c3e5a25cb8">ADC_MULTIMODE_SUPPORT</a></td></tr>
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<tr class="memitem:gaa1c2e0f2c5f57df27447e2c4055d1a3b" id="r_gaa1c2e0f2c5f57df27447e2c4055d1a3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1c2e0f2c5f57df27447e2c4055d1a3b">ADC_SR_AWD_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gad1f5cef448ce47b4bf2e3d71ed7debf3" id="r_gad1f5cef448ce47b4bf2e3d71ed7debf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1f5cef448ce47b4bf2e3d71ed7debf3">ADC_SR_AWD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1c2e0f2c5f57df27447e2c4055d1a3b">ADC_SR_AWD_Pos</a>)</td></tr>
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<tr class="memitem:ga8b7f27694281e4cad956da567e5583b2" id="r_ga8b7f27694281e4cad956da567e5583b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b7f27694281e4cad956da567e5583b2">ADC_SR_AWD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad1f5cef448ce47b4bf2e3d71ed7debf3">ADC_SR_AWD_Msk</a></td></tr>
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<tr class="memitem:ga4a468d077f5722ce97ae2d5d907b6fc5" id="r_ga4a468d077f5722ce97ae2d5d907b6fc5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a468d077f5722ce97ae2d5d907b6fc5">ADC_SR_EOC_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga4a468d077f5722ce97ae2d5d907b6fc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga370d791b736d2b691df00221dbd3041a" id="r_ga370d791b736d2b691df00221dbd3041a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga370d791b736d2b691df00221dbd3041a">ADC_SR_EOC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a468d077f5722ce97ae2d5d907b6fc5">ADC_SR_EOC_Pos</a>)</td></tr>
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<tr class="separator:ga370d791b736d2b691df00221dbd3041a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3dc295c5253743aeb2cda582953b7b53" id="r_ga3dc295c5253743aeb2cda582953b7b53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3dc295c5253743aeb2cda582953b7b53">ADC_SR_EOC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga370d791b736d2b691df00221dbd3041a">ADC_SR_EOC_Msk</a></td></tr>
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<tr class="separator:ga3dc295c5253743aeb2cda582953b7b53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf45ea3ec6ba328fe2eb3d57cc061fcf6" id="r_gaf45ea3ec6ba328fe2eb3d57cc061fcf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf45ea3ec6ba328fe2eb3d57cc061fcf6">ADC_SR_JEOC_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaf45ea3ec6ba328fe2eb3d57cc061fcf6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e5d245721d37e76b53660c9d2094000" id="r_ga2e5d245721d37e76b53660c9d2094000"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e5d245721d37e76b53660c9d2094000">ADC_SR_JEOC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf45ea3ec6ba328fe2eb3d57cc061fcf6">ADC_SR_JEOC_Pos</a>)</td></tr>
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<tr class="separator:ga2e5d245721d37e76b53660c9d2094000"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc9f07589bb1a4e398781df372389b56" id="r_gabc9f07589bb1a4e398781df372389b56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc9f07589bb1a4e398781df372389b56">ADC_SR_JEOC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e5d245721d37e76b53660c9d2094000">ADC_SR_JEOC_Msk</a></td></tr>
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<tr class="separator:gabc9f07589bb1a4e398781df372389b56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66b7ea4bf6dc5c2b0406d52f5c728716" id="r_ga66b7ea4bf6dc5c2b0406d52f5c728716"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66b7ea4bf6dc5c2b0406d52f5c728716">ADC_SR_JSTRT_Pos</a>   (3U)</td></tr>
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<tr class="memitem:ga72dec61b0a9eaf8380b4ba19e8bd3750" id="r_ga72dec61b0a9eaf8380b4ba19e8bd3750"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72dec61b0a9eaf8380b4ba19e8bd3750">ADC_SR_JSTRT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66b7ea4bf6dc5c2b0406d52f5c728716">ADC_SR_JSTRT_Pos</a>)</td></tr>
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<tr class="separator:ga72dec61b0a9eaf8380b4ba19e8bd3750"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7340a01ffec051c06e80a037eee58a14" id="r_ga7340a01ffec051c06e80a037eee58a14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7340a01ffec051c06e80a037eee58a14">ADC_SR_JSTRT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga72dec61b0a9eaf8380b4ba19e8bd3750">ADC_SR_JSTRT_Msk</a></td></tr>
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<tr class="memitem:ga21a6327becffbd34525a0960e7be990e" id="r_ga21a6327becffbd34525a0960e7be990e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21a6327becffbd34525a0960e7be990e">ADC_SR_STRT_Pos</a>   (4U)</td></tr>
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<tr class="memitem:gaabffe4cd9e85d28f2e29d16acf305c48" id="r_gaabffe4cd9e85d28f2e29d16acf305c48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabffe4cd9e85d28f2e29d16acf305c48">ADC_SR_STRT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21a6327becffbd34525a0960e7be990e">ADC_SR_STRT_Pos</a>)</td></tr>
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<tr class="separator:gaabffe4cd9e85d28f2e29d16acf305c48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45eb11ad986d8220cde9fa47a91ed222" id="r_ga45eb11ad986d8220cde9fa47a91ed222"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45eb11ad986d8220cde9fa47a91ed222">ADC_SR_STRT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaabffe4cd9e85d28f2e29d16acf305c48">ADC_SR_STRT_Msk</a></td></tr>
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<tr class="memitem:ga50c7432adead5e587179e4c67713f193" id="r_ga50c7432adead5e587179e4c67713f193"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50c7432adead5e587179e4c67713f193">ADC_SR_OVR_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga50c7432adead5e587179e4c67713f193"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f963f57c46a01cd982b88b3a71574eb" id="r_ga3f963f57c46a01cd982b88b3a71574eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f963f57c46a01cd982b88b3a71574eb">ADC_SR_OVR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga50c7432adead5e587179e4c67713f193">ADC_SR_OVR_Pos</a>)</td></tr>
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<tr class="separator:ga3f963f57c46a01cd982b88b3a71574eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e5211d5e3e53cdedf4d9d6fe4ce2a45" id="r_ga1e5211d5e3e53cdedf4d9d6fe4ce2a45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5211d5e3e53cdedf4d9d6fe4ce2a45">ADC_SR_OVR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f963f57c46a01cd982b88b3a71574eb">ADC_SR_OVR_Msk</a></td></tr>
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<tr class="separator:ga1e5211d5e3e53cdedf4d9d6fe4ce2a45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga593a52bc26648e0eceef061f5a8c32e0" id="r_ga593a52bc26648e0eceef061f5a8c32e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga593a52bc26648e0eceef061f5a8c32e0">ADC_CR1_AWDCH_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga593a52bc26648e0eceef061f5a8c32e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cc3a347eb0150e7f476f67df64e2276" id="r_ga0cc3a347eb0150e7f476f67df64e2276"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cc3a347eb0150e7f476f67df64e2276">ADC_CR1_AWDCH_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga593a52bc26648e0eceef061f5a8c32e0">ADC_CR1_AWDCH_Pos</a>)</td></tr>
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<tr class="memitem:gad8bb755c7059bb2d4f5e2e999d2a2677" id="r_gad8bb755c7059bb2d4f5e2e999d2a2677"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8bb755c7059bb2d4f5e2e999d2a2677">ADC_CR1_AWDCH</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cc3a347eb0150e7f476f67df64e2276">ADC_CR1_AWDCH_Msk</a></td></tr>
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<tr class="separator:gad8bb755c7059bb2d4f5e2e999d2a2677"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18725d77c35c173cdb5bdab658d9dace" id="r_ga18725d77c35c173cdb5bdab658d9dace"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18725d77c35c173cdb5bdab658d9dace">ADC_CR1_AWDCH_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga593a52bc26648e0eceef061f5a8c32e0">ADC_CR1_AWDCH_Pos</a>)</td></tr>
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<tr class="separator:ga18725d77c35c173cdb5bdab658d9dace"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcd37244d74db7c9a34a4f08b94301ae" id="r_gafcd37244d74db7c9a34a4f08b94301ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcd37244d74db7c9a34a4f08b94301ae">ADC_CR1_AWDCH_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga593a52bc26648e0eceef061f5a8c32e0">ADC_CR1_AWDCH_Pos</a>)</td></tr>
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<tr class="separator:gafcd37244d74db7c9a34a4f08b94301ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga625eebdc95937325cad90a151853f5a0" id="r_ga625eebdc95937325cad90a151853f5a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga625eebdc95937325cad90a151853f5a0">ADC_CR1_AWDCH_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga593a52bc26648e0eceef061f5a8c32e0">ADC_CR1_AWDCH_Pos</a>)</td></tr>
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<tr class="memitem:gafb768d4aafbabc114d4650cf962392ec" id="r_gafb768d4aafbabc114d4650cf962392ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb768d4aafbabc114d4650cf962392ec">ADC_CR1_AWDCH_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga593a52bc26648e0eceef061f5a8c32e0">ADC_CR1_AWDCH_Pos</a>)</td></tr>
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<tr class="separator:gafb768d4aafbabc114d4650cf962392ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf37f3c0d7c72192803d0772e076cf8ee" id="r_gaf37f3c0d7c72192803d0772e076cf8ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf37f3c0d7c72192803d0772e076cf8ee">ADC_CR1_AWDCH_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga593a52bc26648e0eceef061f5a8c32e0">ADC_CR1_AWDCH_Pos</a>)</td></tr>
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<tr class="separator:gaf37f3c0d7c72192803d0772e076cf8ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac14738c525ee769e8971601f631ef594" id="r_gac14738c525ee769e8971601f631ef594"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac14738c525ee769e8971601f631ef594">ADC_CR1_EOCIE_Pos</a>   (5U)</td></tr>
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<tr class="separator:gac14738c525ee769e8971601f631ef594"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4cb8db4061b4ebb927dbf6bef84e9ae0" id="r_ga4cb8db4061b4ebb927dbf6bef84e9ae0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4cb8db4061b4ebb927dbf6bef84e9ae0">ADC_CR1_EOCIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac14738c525ee769e8971601f631ef594">ADC_CR1_EOCIE_Pos</a>)</td></tr>
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<tr class="separator:ga4cb8db4061b4ebb927dbf6bef84e9ae0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa39fee2e812a7ca45998cccf32e90aea" id="r_gaa39fee2e812a7ca45998cccf32e90aea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa39fee2e812a7ca45998cccf32e90aea">ADC_CR1_EOCIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4cb8db4061b4ebb927dbf6bef84e9ae0">ADC_CR1_EOCIE_Msk</a></td></tr>
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<tr class="separator:gaa39fee2e812a7ca45998cccf32e90aea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga553aa50487015ce07880bd3c62887698" id="r_ga553aa50487015ce07880bd3c62887698"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga553aa50487015ce07880bd3c62887698">ADC_CR1_AWDIE_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga553aa50487015ce07880bd3c62887698"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34c5eb25f1b9dc807fabc06c90fe9df6" id="r_ga34c5eb25f1b9dc807fabc06c90fe9df6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34c5eb25f1b9dc807fabc06c90fe9df6">ADC_CR1_AWDIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga553aa50487015ce07880bd3c62887698">ADC_CR1_AWDIE_Pos</a>)</td></tr>
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<tr class="separator:ga34c5eb25f1b9dc807fabc06c90fe9df6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd44f86b189696d5a3780342516de722" id="r_gacd44f86b189696d5a3780342516de722"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd44f86b189696d5a3780342516de722">ADC_CR1_AWDIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34c5eb25f1b9dc807fabc06c90fe9df6">ADC_CR1_AWDIE_Msk</a></td></tr>
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<tr class="separator:gacd44f86b189696d5a3780342516de722"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89dc37165238a2b3a31bad4bf2241b12" id="r_ga89dc37165238a2b3a31bad4bf2241b12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89dc37165238a2b3a31bad4bf2241b12">ADC_CR1_JEOCIE_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga89dc37165238a2b3a31bad4bf2241b12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c41e259f643939c71619ce4f743554a" id="r_ga4c41e259f643939c71619ce4f743554a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c41e259f643939c71619ce4f743554a">ADC_CR1_JEOCIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga89dc37165238a2b3a31bad4bf2241b12">ADC_CR1_JEOCIE_Pos</a>)</td></tr>
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<tr class="separator:ga4c41e259f643939c71619ce4f743554a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c46fc1dc6c63acf88821f46a8f6d5e7" id="r_ga5c46fc1dc6c63acf88821f46a8f6d5e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c46fc1dc6c63acf88821f46a8f6d5e7">ADC_CR1_JEOCIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c41e259f643939c71619ce4f743554a">ADC_CR1_JEOCIE_Msk</a></td></tr>
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<tr class="separator:ga5c46fc1dc6c63acf88821f46a8f6d5e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dcc7aec82792bc0439ebf0eaa871d5c" id="r_ga4dcc7aec82792bc0439ebf0eaa871d5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dcc7aec82792bc0439ebf0eaa871d5c">ADC_CR1_SCAN_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga4dcc7aec82792bc0439ebf0eaa871d5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ae87fc99e54856233fe19c05947821d" id="r_ga3ae87fc99e54856233fe19c05947821d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ae87fc99e54856233fe19c05947821d">ADC_CR1_SCAN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4dcc7aec82792bc0439ebf0eaa871d5c">ADC_CR1_SCAN_Pos</a>)</td></tr>
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<tr class="separator:ga3ae87fc99e54856233fe19c05947821d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaeab75ece0c73dd97e8f21911ed22d06" id="r_gaaeab75ece0c73dd97e8f21911ed22d06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaeab75ece0c73dd97e8f21911ed22d06">ADC_CR1_SCAN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ae87fc99e54856233fe19c05947821d">ADC_CR1_SCAN_Msk</a></td></tr>
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<tr class="separator:gaaeab75ece0c73dd97e8f21911ed22d06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cc219fd4025d88bd77dfb2824e4a42b" id="r_ga1cc219fd4025d88bd77dfb2824e4a42b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc219fd4025d88bd77dfb2824e4a42b">ADC_CR1_AWDSGL_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga1cc219fd4025d88bd77dfb2824e4a42b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a58382bba04769e4baef8f36390f648" id="r_ga2a58382bba04769e4baef8f36390f648"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a58382bba04769e4baef8f36390f648">ADC_CR1_AWDSGL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc219fd4025d88bd77dfb2824e4a42b">ADC_CR1_AWDSGL_Pos</a>)</td></tr>
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<tr class="separator:ga2a58382bba04769e4baef8f36390f648"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c9fc31f19c04033dfa98e982519c451" id="r_ga5c9fc31f19c04033dfa98e982519c451"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c9fc31f19c04033dfa98e982519c451">ADC_CR1_AWDSGL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a58382bba04769e4baef8f36390f648">ADC_CR1_AWDSGL_Msk</a></td></tr>
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<tr class="separator:ga5c9fc31f19c04033dfa98e982519c451"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac65ab808d9f67501a3e032f6e093baa7" id="r_gac65ab808d9f67501a3e032f6e093baa7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac65ab808d9f67501a3e032f6e093baa7">ADC_CR1_JAUTO_Pos</a>   (10U)</td></tr>
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<tr class="separator:gac65ab808d9f67501a3e032f6e093baa7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cfa0d38cd6dfd5ed09673558ccadacf" id="r_ga7cfa0d38cd6dfd5ed09673558ccadacf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cfa0d38cd6dfd5ed09673558ccadacf">ADC_CR1_JAUTO_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac65ab808d9f67501a3e032f6e093baa7">ADC_CR1_JAUTO_Pos</a>)</td></tr>
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<tr class="separator:ga7cfa0d38cd6dfd5ed09673558ccadacf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6353cb0d564410358b3a086dd0241f8c" id="r_ga6353cb0d564410358b3a086dd0241f8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6353cb0d564410358b3a086dd0241f8c">ADC_CR1_JAUTO</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cfa0d38cd6dfd5ed09673558ccadacf">ADC_CR1_JAUTO_Msk</a></td></tr>
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<tr class="separator:ga6353cb0d564410358b3a086dd0241f8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga394271f323587db3ea21731046b69004" id="r_ga394271f323587db3ea21731046b69004"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga394271f323587db3ea21731046b69004">ADC_CR1_DISCEN_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga394271f323587db3ea21731046b69004"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad69e1c5ba0421fe9b33109a3789be1a5" id="r_gad69e1c5ba0421fe9b33109a3789be1a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad69e1c5ba0421fe9b33109a3789be1a5">ADC_CR1_DISCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga394271f323587db3ea21731046b69004">ADC_CR1_DISCEN_Pos</a>)</td></tr>
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<tr class="separator:gad69e1c5ba0421fe9b33109a3789be1a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd690297fc73fca40d797f4c90800b9a" id="r_gabd690297fc73fca40d797f4c90800b9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd690297fc73fca40d797f4c90800b9a">ADC_CR1_DISCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad69e1c5ba0421fe9b33109a3789be1a5">ADC_CR1_DISCEN_Msk</a></td></tr>
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<tr class="separator:gabd690297fc73fca40d797f4c90800b9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2e2019ed8fe62389fe06843f9bbc265" id="r_gad2e2019ed8fe62389fe06843f9bbc265"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2e2019ed8fe62389fe06843f9bbc265">ADC_CR1_JDISCEN_Pos</a>   (12U)</td></tr>
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<tr class="separator:gad2e2019ed8fe62389fe06843f9bbc265"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae5059f8684f70119fff571d8c79bbaf" id="r_gaae5059f8684f70119fff571d8c79bbaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae5059f8684f70119fff571d8c79bbaf">ADC_CR1_JDISCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2e2019ed8fe62389fe06843f9bbc265">ADC_CR1_JDISCEN_Pos</a>)</td></tr>
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<tr class="separator:gaae5059f8684f70119fff571d8c79bbaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd06a2840346bf45ff335707db0b6e30" id="r_gacd06a2840346bf45ff335707db0b6e30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd06a2840346bf45ff335707db0b6e30">ADC_CR1_JDISCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae5059f8684f70119fff571d8c79bbaf">ADC_CR1_JDISCEN_Msk</a></td></tr>
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<tr class="separator:gacd06a2840346bf45ff335707db0b6e30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga418d84715b6f383cea1ca241d0c76194" id="r_ga418d84715b6f383cea1ca241d0c76194"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga418d84715b6f383cea1ca241d0c76194">ADC_CR1_DISCNUM_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga418d84715b6f383cea1ca241d0c76194"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafee42b4ef0f4cb5b0ab45fc78f3e27f9" id="r_gafee42b4ef0f4cb5b0ab45fc78f3e27f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafee42b4ef0f4cb5b0ab45fc78f3e27f9">ADC_CR1_DISCNUM_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga418d84715b6f383cea1ca241d0c76194">ADC_CR1_DISCNUM_Pos</a>)</td></tr>
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<tr class="separator:gafee42b4ef0f4cb5b0ab45fc78f3e27f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeaa416a291023449ae82e7ef39844075" id="r_gaeaa416a291023449ae82e7ef39844075"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeaa416a291023449ae82e7ef39844075">ADC_CR1_DISCNUM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafee42b4ef0f4cb5b0ab45fc78f3e27f9">ADC_CR1_DISCNUM_Msk</a></td></tr>
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<tr class="separator:gaeaa416a291023449ae82e7ef39844075"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59ff81db7def261f0e84d5dbb6cca1ce" id="r_ga59ff81db7def261f0e84d5dbb6cca1ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59ff81db7def261f0e84d5dbb6cca1ce">ADC_CR1_DISCNUM_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga418d84715b6f383cea1ca241d0c76194">ADC_CR1_DISCNUM_Pos</a>)</td></tr>
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<tr class="memitem:ga39940d3611126052f4f748934c629ebf" id="r_ga39940d3611126052f4f748934c629ebf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39940d3611126052f4f748934c629ebf">ADC_CR1_DISCNUM_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga418d84715b6f383cea1ca241d0c76194">ADC_CR1_DISCNUM_Pos</a>)</td></tr>
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<tr class="separator:ga39940d3611126052f4f748934c629ebf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab73d5fdf276f5ef3965afdda78ac9e1e" id="r_gab73d5fdf276f5ef3965afdda78ac9e1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab73d5fdf276f5ef3965afdda78ac9e1e">ADC_CR1_DISCNUM_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga418d84715b6f383cea1ca241d0c76194">ADC_CR1_DISCNUM_Pos</a>)</td></tr>
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<tr class="separator:gab73d5fdf276f5ef3965afdda78ac9e1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78cb5899a747da3e5013ad44934b5c7d" id="r_ga78cb5899a747da3e5013ad44934b5c7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78cb5899a747da3e5013ad44934b5c7d">ADC_CR1_JAWDEN_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga78cb5899a747da3e5013ad44934b5c7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29a30d56ef1ba75b52db631e367b13bb" id="r_ga29a30d56ef1ba75b52db631e367b13bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29a30d56ef1ba75b52db631e367b13bb">ADC_CR1_JAWDEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78cb5899a747da3e5013ad44934b5c7d">ADC_CR1_JAWDEN_Pos</a>)</td></tr>
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<tr class="separator:ga29a30d56ef1ba75b52db631e367b13bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4886de74bcd3a1e545094089f76fd0b3" id="r_ga4886de74bcd3a1e545094089f76fd0b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4886de74bcd3a1e545094089f76fd0b3">ADC_CR1_JAWDEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga29a30d56ef1ba75b52db631e367b13bb">ADC_CR1_JAWDEN_Msk</a></td></tr>
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<tr class="separator:ga4886de74bcd3a1e545094089f76fd0b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4078327f9219b87d0627ad53f27e25a" id="r_gaf4078327f9219b87d0627ad53f27e25a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4078327f9219b87d0627ad53f27e25a">ADC_CR1_AWDEN_Pos</a>   (23U)</td></tr>
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<tr class="separator:gaf4078327f9219b87d0627ad53f27e25a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga815cfd0e3ad3eed4424caf312550da16" id="r_ga815cfd0e3ad3eed4424caf312550da16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga815cfd0e3ad3eed4424caf312550da16">ADC_CR1_AWDEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4078327f9219b87d0627ad53f27e25a">ADC_CR1_AWDEN_Pos</a>)</td></tr>
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<tr class="separator:ga815cfd0e3ad3eed4424caf312550da16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e006d43fcb9fe1306745c95a1bdd651" id="r_ga6e006d43fcb9fe1306745c95a1bdd651"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e006d43fcb9fe1306745c95a1bdd651">ADC_CR1_AWDEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga815cfd0e3ad3eed4424caf312550da16">ADC_CR1_AWDEN_Msk</a></td></tr>
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<tr class="separator:ga6e006d43fcb9fe1306745c95a1bdd651"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacae7156287b4fc60bc71114529b7b868" id="r_gacae7156287b4fc60bc71114529b7b868"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacae7156287b4fc60bc71114529b7b868">ADC_CR1_RES_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga5645a309568931b9f783dbca969ff487" id="r_ga5645a309568931b9f783dbca969ff487"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5645a309568931b9f783dbca969ff487">ADC_CR1_RES_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacae7156287b4fc60bc71114529b7b868">ADC_CR1_RES_Pos</a>)</td></tr>
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<tr class="memitem:ga71e4a4c233895a2e7b6dd3ca6ca849e5" id="r_ga71e4a4c233895a2e7b6dd3ca6ca849e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71e4a4c233895a2e7b6dd3ca6ca849e5">ADC_CR1_RES</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5645a309568931b9f783dbca969ff487">ADC_CR1_RES_Msk</a></td></tr>
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<tr class="memitem:gacfc432ddbd2140a92d877f6d9dc52417" id="r_gacfc432ddbd2140a92d877f6d9dc52417"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfc432ddbd2140a92d877f6d9dc52417">ADC_CR1_RES_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacae7156287b4fc60bc71114529b7b868">ADC_CR1_RES_Pos</a>)</td></tr>
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<tr class="memitem:ga674904864f540043692a5b5ead9fae10" id="r_ga674904864f540043692a5b5ead9fae10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga674904864f540043692a5b5ead9fae10">ADC_CR1_RES_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacae7156287b4fc60bc71114529b7b868">ADC_CR1_RES_Pos</a>)</td></tr>
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<tr class="memitem:ga0c72d6e0c41f98ea9b378d8455de2f13" id="r_ga0c72d6e0c41f98ea9b378d8455de2f13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c72d6e0c41f98ea9b378d8455de2f13">ADC_CR1_OVRIE_Pos</a>   (26U)</td></tr>
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<tr class="memitem:gada4ec8e732a43f37a4568049593aa146" id="r_gada4ec8e732a43f37a4568049593aa146"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada4ec8e732a43f37a4568049593aa146">ADC_CR1_OVRIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c72d6e0c41f98ea9b378d8455de2f13">ADC_CR1_OVRIE_Pos</a>)</td></tr>
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<tr class="separator:gada4ec8e732a43f37a4568049593aa146"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa892fda7c204bf18a33a059f28be0fba" id="r_gaa892fda7c204bf18a33a059f28be0fba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa892fda7c204bf18a33a059f28be0fba">ADC_CR1_OVRIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada4ec8e732a43f37a4568049593aa146">ADC_CR1_OVRIE_Msk</a></td></tr>
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<tr class="separator:gaa892fda7c204bf18a33a059f28be0fba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga234ecbd845e8f7b48fab4b3f1e12e788" id="r_ga234ecbd845e8f7b48fab4b3f1e12e788"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga234ecbd845e8f7b48fab4b3f1e12e788">ADC_CR2_ADON_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga234ecbd845e8f7b48fab4b3f1e12e788"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga523c9c51b9eefe42cc33dec9dbcd7091" id="r_ga523c9c51b9eefe42cc33dec9dbcd7091"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga523c9c51b9eefe42cc33dec9dbcd7091">ADC_CR2_ADON_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga234ecbd845e8f7b48fab4b3f1e12e788">ADC_CR2_ADON_Pos</a>)</td></tr>
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<tr class="separator:ga523c9c51b9eefe42cc33dec9dbcd7091"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89b646f092b052d8488d2016f6290f0e" id="r_ga89b646f092b052d8488d2016f6290f0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89b646f092b052d8488d2016f6290f0e">ADC_CR2_ADON</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga523c9c51b9eefe42cc33dec9dbcd7091">ADC_CR2_ADON_Msk</a></td></tr>
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<tr class="separator:ga89b646f092b052d8488d2016f6290f0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4401869d89774c7f187aa72c3f9fae2" id="r_gab4401869d89774c7f187aa72c3f9fae2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4401869d89774c7f187aa72c3f9fae2">ADC_CR2_CONT_Pos</a>   (1U)</td></tr>
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<tr class="separator:gab4401869d89774c7f187aa72c3f9fae2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69a1c4bf40a36bd05804f1083f745914" id="r_ga69a1c4bf40a36bd05804f1083f745914"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69a1c4bf40a36bd05804f1083f745914">ADC_CR2_CONT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab4401869d89774c7f187aa72c3f9fae2">ADC_CR2_CONT_Pos</a>)</td></tr>
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<tr class="separator:ga69a1c4bf40a36bd05804f1083f745914"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49bb71a868c9d88a0f7bbe48918b2140" id="r_ga49bb71a868c9d88a0f7bbe48918b2140"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49bb71a868c9d88a0f7bbe48918b2140">ADC_CR2_CONT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga69a1c4bf40a36bd05804f1083f745914">ADC_CR2_CONT_Msk</a></td></tr>
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<tr class="separator:ga49bb71a868c9d88a0f7bbe48918b2140"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8edaebc5ec9c7cf465e7810189052ffd" id="r_ga8edaebc5ec9c7cf465e7810189052ffd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8edaebc5ec9c7cf465e7810189052ffd">ADC_CR2_DMA_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga8edaebc5ec9c7cf465e7810189052ffd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9bfa1dd15f4531ef79131a4a2810342" id="r_gad9bfa1dd15f4531ef79131a4a2810342"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9bfa1dd15f4531ef79131a4a2810342">ADC_CR2_DMA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8edaebc5ec9c7cf465e7810189052ffd">ADC_CR2_DMA_Pos</a>)</td></tr>
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<tr class="separator:gad9bfa1dd15f4531ef79131a4a2810342"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga017309ac4b532bc8c607388f4e2cbbec" id="r_ga017309ac4b532bc8c607388f4e2cbbec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga017309ac4b532bc8c607388f4e2cbbec">ADC_CR2_DMA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad9bfa1dd15f4531ef79131a4a2810342">ADC_CR2_DMA_Msk</a></td></tr>
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<tr class="memitem:ga25e88283dda37ac8153f8f2d5aa8fd4b" id="r_ga25e88283dda37ac8153f8f2d5aa8fd4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25e88283dda37ac8153f8f2d5aa8fd4b">ADC_CR2_DDS_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga25e88283dda37ac8153f8f2d5aa8fd4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96fbc51781aa1e2cb18d72ac67e748fe" id="r_ga96fbc51781aa1e2cb18d72ac67e748fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96fbc51781aa1e2cb18d72ac67e748fe">ADC_CR2_DDS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25e88283dda37ac8153f8f2d5aa8fd4b">ADC_CR2_DDS_Pos</a>)</td></tr>
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<tr class="separator:ga96fbc51781aa1e2cb18d72ac67e748fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d7d75f0c4c8fa190fbf9f86fbe6dfc8" id="r_ga0d7d75f0c4c8fa190fbf9f86fbe6dfc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d7d75f0c4c8fa190fbf9f86fbe6dfc8">ADC_CR2_DDS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga96fbc51781aa1e2cb18d72ac67e748fe">ADC_CR2_DDS_Msk</a></td></tr>
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<tr class="separator:ga0d7d75f0c4c8fa190fbf9f86fbe6dfc8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga375e2be253b645381365c90ae8c4cb1f" id="r_ga375e2be253b645381365c90ae8c4cb1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga375e2be253b645381365c90ae8c4cb1f">ADC_CR2_EOCS_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga375e2be253b645381365c90ae8c4cb1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacee54d4669ca3fd1c2e760cbe1a0dcbd" id="r_gacee54d4669ca3fd1c2e760cbe1a0dcbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacee54d4669ca3fd1c2e760cbe1a0dcbd">ADC_CR2_EOCS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga375e2be253b645381365c90ae8c4cb1f">ADC_CR2_EOCS_Pos</a>)</td></tr>
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<tr class="separator:gacee54d4669ca3fd1c2e760cbe1a0dcbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9dac2004ab20295e04012060ab24aeb" id="r_gaf9dac2004ab20295e04012060ab24aeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9dac2004ab20295e04012060ab24aeb">ADC_CR2_EOCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacee54d4669ca3fd1c2e760cbe1a0dcbd">ADC_CR2_EOCS_Msk</a></td></tr>
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<tr class="separator:gaf9dac2004ab20295e04012060ab24aeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6422927e869ce87e289e796dcf0067c2" id="r_ga6422927e869ce87e289e796dcf0067c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6422927e869ce87e289e796dcf0067c2">ADC_CR2_ALIGN_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga6422927e869ce87e289e796dcf0067c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada0bca3543546c0f5c893a4a99a4ddcc" id="r_gada0bca3543546c0f5c893a4a99a4ddcc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada0bca3543546c0f5c893a4a99a4ddcc">ADC_CR2_ALIGN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6422927e869ce87e289e796dcf0067c2">ADC_CR2_ALIGN_Pos</a>)</td></tr>
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<tr class="separator:gada0bca3543546c0f5c893a4a99a4ddcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5950b5a7438a447584f6dd86c343362" id="r_gaf5950b5a7438a447584f6dd86c343362"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5950b5a7438a447584f6dd86c343362">ADC_CR2_ALIGN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada0bca3543546c0f5c893a4a99a4ddcc">ADC_CR2_ALIGN_Msk</a></td></tr>
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<tr class="separator:gaf5950b5a7438a447584f6dd86c343362"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d64811b8292d3145622b767f859e3b0" id="r_ga6d64811b8292d3145622b767f859e3b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d64811b8292d3145622b767f859e3b0">ADC_CR2_JEXTSEL_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga6d64811b8292d3145622b767f859e3b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57147ca3b182775bc6708bd7edad0a8d" id="r_ga57147ca3b182775bc6708bd7edad0a8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57147ca3b182775bc6708bd7edad0a8d">ADC_CR2_JEXTSEL_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d64811b8292d3145622b767f859e3b0">ADC_CR2_JEXTSEL_Pos</a>)</td></tr>
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<tr class="separator:ga57147ca3b182775bc6708bd7edad0a8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab3aa5d0e2a4b77960ec8f3b425a3eac" id="r_gaab3aa5d0e2a4b77960ec8f3b425a3eac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab3aa5d0e2a4b77960ec8f3b425a3eac">ADC_CR2_JEXTSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57147ca3b182775bc6708bd7edad0a8d">ADC_CR2_JEXTSEL_Msk</a></td></tr>
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<tr class="separator:gaab3aa5d0e2a4b77960ec8f3b425a3eac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa70c1f30e2101e2177ce564440203ba3" id="r_gaa70c1f30e2101e2177ce564440203ba3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa70c1f30e2101e2177ce564440203ba3">ADC_CR2_JEXTSEL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d64811b8292d3145622b767f859e3b0">ADC_CR2_JEXTSEL_Pos</a>)</td></tr>
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<tr class="separator:gaa70c1f30e2101e2177ce564440203ba3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99fa4a240d34ce231d6d0543bac7fd9b" id="r_ga99fa4a240d34ce231d6d0543bac7fd9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99fa4a240d34ce231d6d0543bac7fd9b">ADC_CR2_JEXTSEL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d64811b8292d3145622b767f859e3b0">ADC_CR2_JEXTSEL_Pos</a>)</td></tr>
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<tr class="separator:ga99fa4a240d34ce231d6d0543bac7fd9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga571bb97f950181fedbc0d4756482713d" id="r_ga571bb97f950181fedbc0d4756482713d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga571bb97f950181fedbc0d4756482713d">ADC_CR2_JEXTSEL_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d64811b8292d3145622b767f859e3b0">ADC_CR2_JEXTSEL_Pos</a>)</td></tr>
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<tr class="separator:ga571bb97f950181fedbc0d4756482713d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae34f5dda7a153ffd927c9cd38999f822" id="r_gae34f5dda7a153ffd927c9cd38999f822"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae34f5dda7a153ffd927c9cd38999f822">ADC_CR2_JEXTSEL_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d64811b8292d3145622b767f859e3b0">ADC_CR2_JEXTSEL_Pos</a>)</td></tr>
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<tr class="separator:gae34f5dda7a153ffd927c9cd38999f822"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf91b9e9943eb12821746a1fe4a68988" id="r_gacf91b9e9943eb12821746a1fe4a68988"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf91b9e9943eb12821746a1fe4a68988">ADC_CR2_JEXTEN_Pos</a>   (20U)</td></tr>
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<tr class="separator:gacf91b9e9943eb12821746a1fe4a68988"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac444a034ccfbea8f0a0a1b3a40abb600" id="r_gac444a034ccfbea8f0a0a1b3a40abb600"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac444a034ccfbea8f0a0a1b3a40abb600">ADC_CR2_JEXTEN_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf91b9e9943eb12821746a1fe4a68988">ADC_CR2_JEXTEN_Pos</a>)</td></tr>
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<tr class="separator:gac444a034ccfbea8f0a0a1b3a40abb600"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07330f702208792faca3a563dc4fd9c6" id="r_ga07330f702208792faca3a563dc4fd9c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07330f702208792faca3a563dc4fd9c6">ADC_CR2_JEXTEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac444a034ccfbea8f0a0a1b3a40abb600">ADC_CR2_JEXTEN_Msk</a></td></tr>
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<tr class="memitem:ga0b3c99510de210ff3137ff8de328889b" id="r_ga0b3c99510de210ff3137ff8de328889b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b3c99510de210ff3137ff8de328889b">ADC_CR2_JEXTEN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf91b9e9943eb12821746a1fe4a68988">ADC_CR2_JEXTEN_Pos</a>)</td></tr>
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<tr class="memitem:ga949c70fdf36a32a6afcbf44fec123832" id="r_ga949c70fdf36a32a6afcbf44fec123832"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga949c70fdf36a32a6afcbf44fec123832">ADC_CR2_JEXTEN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf91b9e9943eb12821746a1fe4a68988">ADC_CR2_JEXTEN_Pos</a>)</td></tr>
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<tr class="memitem:ga3c5de0a53e5697dcb16759a12c47c7a4" id="r_ga3c5de0a53e5697dcb16759a12c47c7a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c5de0a53e5697dcb16759a12c47c7a4">ADC_CR2_JSWSTART_Pos</a>   (22U)</td></tr>
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<tr class="memitem:gac1555cd00a88accf874a2bda2c0ac8d4" id="r_gac1555cd00a88accf874a2bda2c0ac8d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1555cd00a88accf874a2bda2c0ac8d4">ADC_CR2_JSWSTART_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c5de0a53e5697dcb16759a12c47c7a4">ADC_CR2_JSWSTART_Pos</a>)</td></tr>
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<tr class="memitem:gac12fe8a6cc24eef2ed2e1f1525855678" id="r_gac12fe8a6cc24eef2ed2e1f1525855678"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac12fe8a6cc24eef2ed2e1f1525855678">ADC_CR2_JSWSTART</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac1555cd00a88accf874a2bda2c0ac8d4">ADC_CR2_JSWSTART_Msk</a></td></tr>
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<tr class="separator:gac12fe8a6cc24eef2ed2e1f1525855678"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98246071e8135d0b92366024e474511c" id="r_ga98246071e8135d0b92366024e474511c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98246071e8135d0b92366024e474511c">ADC_CR2_EXTSEL_Pos</a>   (24U)</td></tr>
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<tr class="memitem:gaef4979d74537d34ce18573d072e33408" id="r_gaef4979d74537d34ce18573d072e33408"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef4979d74537d34ce18573d072e33408">ADC_CR2_EXTSEL_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98246071e8135d0b92366024e474511c">ADC_CR2_EXTSEL_Pos</a>)</td></tr>
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<tr class="memitem:ga6d1054d6cd017e305cf6e8a864ce96c8" id="r_ga6d1054d6cd017e305cf6e8a864ce96c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d1054d6cd017e305cf6e8a864ce96c8">ADC_CR2_EXTSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaef4979d74537d34ce18573d072e33408">ADC_CR2_EXTSEL_Msk</a></td></tr>
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<tr class="memitem:ga9410c7fd93f6d0b157ede745ee269d7b" id="r_ga9410c7fd93f6d0b157ede745ee269d7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9410c7fd93f6d0b157ede745ee269d7b">ADC_CR2_EXTSEL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98246071e8135d0b92366024e474511c">ADC_CR2_EXTSEL_Pos</a>)</td></tr>
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<tr class="separator:ga9410c7fd93f6d0b157ede745ee269d7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a6725419743a8d01b4a223609952893" id="r_ga5a6725419743a8d01b4a223609952893"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a6725419743a8d01b4a223609952893">ADC_CR2_EXTSEL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98246071e8135d0b92366024e474511c">ADC_CR2_EXTSEL_Pos</a>)</td></tr>
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<tr class="memitem:ga5c2322988b5fff19d012d9179d412ad0" id="r_ga5c2322988b5fff19d012d9179d412ad0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c2322988b5fff19d012d9179d412ad0">ADC_CR2_EXTSEL_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98246071e8135d0b92366024e474511c">ADC_CR2_EXTSEL_Pos</a>)</td></tr>
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<tr class="memitem:ga387de6160834197888efa43e164c2db9" id="r_ga387de6160834197888efa43e164c2db9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga387de6160834197888efa43e164c2db9">ADC_CR2_EXTSEL_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98246071e8135d0b92366024e474511c">ADC_CR2_EXTSEL_Pos</a>)</td></tr>
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<tr class="separator:ga387de6160834197888efa43e164c2db9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga902a845718958f3db26c7d56e9c3a286" id="r_ga902a845718958f3db26c7d56e9c3a286"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga902a845718958f3db26c7d56e9c3a286">ADC_CR2_EXTEN_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga902a845718958f3db26c7d56e9c3a286"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac97138f7c2e3ecbb31756679589c9b62" id="r_gac97138f7c2e3ecbb31756679589c9b62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac97138f7c2e3ecbb31756679589c9b62">ADC_CR2_EXTEN_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga902a845718958f3db26c7d56e9c3a286">ADC_CR2_EXTEN_Pos</a>)</td></tr>
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<tr class="separator:gac97138f7c2e3ecbb31756679589c9b62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga574b4d8e90655d0432882d620e629234" id="r_ga574b4d8e90655d0432882d620e629234"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga574b4d8e90655d0432882d620e629234">ADC_CR2_EXTEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac97138f7c2e3ecbb31756679589c9b62">ADC_CR2_EXTEN_Msk</a></td></tr>
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<tr class="memitem:ga3519da0cc6fbd31444a16244c70232e6" id="r_ga3519da0cc6fbd31444a16244c70232e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3519da0cc6fbd31444a16244c70232e6">ADC_CR2_EXTEN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga902a845718958f3db26c7d56e9c3a286">ADC_CR2_EXTEN_Pos</a>)</td></tr>
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<tr class="memitem:ga17e37edddbb6ad791bffb350cca23d4d" id="r_ga17e37edddbb6ad791bffb350cca23d4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17e37edddbb6ad791bffb350cca23d4d">ADC_CR2_EXTEN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga902a845718958f3db26c7d56e9c3a286">ADC_CR2_EXTEN_Pos</a>)</td></tr>
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<tr class="separator:ga17e37edddbb6ad791bffb350cca23d4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf78afe48fe6fdadf00d3c37cfed860a7" id="r_gaf78afe48fe6fdadf00d3c37cfed860a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf78afe48fe6fdadf00d3c37cfed860a7">ADC_CR2_SWSTART_Pos</a>   (30U)</td></tr>
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<tr class="memitem:gaa5c16a177295208be4bed45f350c315e" id="r_gaa5c16a177295208be4bed45f350c315e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5c16a177295208be4bed45f350c315e">ADC_CR2_SWSTART_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf78afe48fe6fdadf00d3c37cfed860a7">ADC_CR2_SWSTART_Pos</a>)</td></tr>
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<tr class="memitem:ga5eae65bad1a6c975e1911eb5ba117468" id="r_ga5eae65bad1a6c975e1911eb5ba117468"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5eae65bad1a6c975e1911eb5ba117468">ADC_CR2_SWSTART</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5c16a177295208be4bed45f350c315e">ADC_CR2_SWSTART_Msk</a></td></tr>
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<tr class="memitem:gad2d3f858e16869682edb4fd672167f9e" id="r_gad2d3f858e16869682edb4fd672167f9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2d3f858e16869682edb4fd672167f9e">ADC_SMPR1_SMP10_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad2d3f858e16869682edb4fd672167f9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa436e3f99d6260a7c0d93c2c7b9e06e0" id="r_gaa436e3f99d6260a7c0d93c2c7b9e06e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa436e3f99d6260a7c0d93c2c7b9e06e0">ADC_SMPR1_SMP10_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2d3f858e16869682edb4fd672167f9e">ADC_SMPR1_SMP10_Pos</a>)</td></tr>
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<tr class="memitem:ga32242a2c2156a012a7343bcb43d490d0" id="r_ga32242a2c2156a012a7343bcb43d490d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32242a2c2156a012a7343bcb43d490d0">ADC_SMPR1_SMP10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa436e3f99d6260a7c0d93c2c7b9e06e0">ADC_SMPR1_SMP10_Msk</a></td></tr>
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<tr class="separator:ga32242a2c2156a012a7343bcb43d490d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a8996c53042759f01e966fb00351ebf" id="r_ga8a8996c53042759f01e966fb00351ebf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a8996c53042759f01e966fb00351ebf">ADC_SMPR1_SMP10_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2d3f858e16869682edb4fd672167f9e">ADC_SMPR1_SMP10_Pos</a>)</td></tr>
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<tr class="memitem:ga42b96f058436c8bdcfabe1e08c7edd61" id="r_ga42b96f058436c8bdcfabe1e08c7edd61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42b96f058436c8bdcfabe1e08c7edd61">ADC_SMPR1_SMP10_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2d3f858e16869682edb4fd672167f9e">ADC_SMPR1_SMP10_Pos</a>)</td></tr>
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<tr class="separator:ga42b96f058436c8bdcfabe1e08c7edd61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga289d89b4d92d7f685a8e44aeb9ddcded" id="r_ga289d89b4d92d7f685a8e44aeb9ddcded"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga289d89b4d92d7f685a8e44aeb9ddcded">ADC_SMPR1_SMP10_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2d3f858e16869682edb4fd672167f9e">ADC_SMPR1_SMP10_Pos</a>)</td></tr>
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<tr class="separator:ga289d89b4d92d7f685a8e44aeb9ddcded"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b0f3653aea6b1db3875f59d5c3bdc74" id="r_ga6b0f3653aea6b1db3875f59d5c3bdc74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b0f3653aea6b1db3875f59d5c3bdc74">ADC_SMPR1_SMP11_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga6b0f3653aea6b1db3875f59d5c3bdc74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bed6ca83db1864feb7eb926d8228c85" id="r_ga2bed6ca83db1864feb7eb926d8228c85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bed6ca83db1864feb7eb926d8228c85">ADC_SMPR1_SMP11_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b0f3653aea6b1db3875f59d5c3bdc74">ADC_SMPR1_SMP11_Pos</a>)</td></tr>
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<tr class="memitem:ga4c74d559f2a70a2e8c807b7bcaccd800" id="r_ga4c74d559f2a70a2e8c807b7bcaccd800"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c74d559f2a70a2e8c807b7bcaccd800">ADC_SMPR1_SMP11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2bed6ca83db1864feb7eb926d8228c85">ADC_SMPR1_SMP11_Msk</a></td></tr>
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<tr class="separator:ga4c74d559f2a70a2e8c807b7bcaccd800"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60780d613953f48a2dfc8debce72fb28" id="r_ga60780d613953f48a2dfc8debce72fb28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60780d613953f48a2dfc8debce72fb28">ADC_SMPR1_SMP11_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b0f3653aea6b1db3875f59d5c3bdc74">ADC_SMPR1_SMP11_Pos</a>)</td></tr>
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<tr class="memitem:gaa61e1dbafcae3e1c8eae4320a6e5ec5d" id="r_gaa61e1dbafcae3e1c8eae4320a6e5ec5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa61e1dbafcae3e1c8eae4320a6e5ec5d">ADC_SMPR1_SMP11_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b0f3653aea6b1db3875f59d5c3bdc74">ADC_SMPR1_SMP11_Pos</a>)</td></tr>
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<tr class="memitem:ga93a876a9a6d90cd30456433b7e38c3f2" id="r_ga93a876a9a6d90cd30456433b7e38c3f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93a876a9a6d90cd30456433b7e38c3f2">ADC_SMPR1_SMP11_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b0f3653aea6b1db3875f59d5c3bdc74">ADC_SMPR1_SMP11_Pos</a>)</td></tr>
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<tr class="memitem:gaeb6169f9cd1e9c488526140dcbf464c2" id="r_gaeb6169f9cd1e9c488526140dcbf464c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb6169f9cd1e9c488526140dcbf464c2">ADC_SMPR1_SMP12_Pos</a>   (6U)</td></tr>
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<tr class="memitem:gae18d279a21d7ce940d6969500a25a13b" id="r_gae18d279a21d7ce940d6969500a25a13b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae18d279a21d7ce940d6969500a25a13b">ADC_SMPR1_SMP12_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb6169f9cd1e9c488526140dcbf464c2">ADC_SMPR1_SMP12_Pos</a>)</td></tr>
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<tr class="memitem:ga433b5a7d944666fb7abed3b107c352fc" id="r_ga433b5a7d944666fb7abed3b107c352fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga433b5a7d944666fb7abed3b107c352fc">ADC_SMPR1_SMP12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae18d279a21d7ce940d6969500a25a13b">ADC_SMPR1_SMP12_Msk</a></td></tr>
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<tr class="memitem:gaaaac6ae97c00276d7472bc92a9edd6e2" id="r_gaaaac6ae97c00276d7472bc92a9edd6e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaaac6ae97c00276d7472bc92a9edd6e2">ADC_SMPR1_SMP12_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb6169f9cd1e9c488526140dcbf464c2">ADC_SMPR1_SMP12_Pos</a>)</td></tr>
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<tr class="memitem:ga6020f9d742e15650ad919aaccaf2ff6c" id="r_ga6020f9d742e15650ad919aaccaf2ff6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6020f9d742e15650ad919aaccaf2ff6c">ADC_SMPR1_SMP12_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb6169f9cd1e9c488526140dcbf464c2">ADC_SMPR1_SMP12_Pos</a>)</td></tr>
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<tr class="memitem:gadb59adb544d416e91ea0c12d4f39ccc9" id="r_gadb59adb544d416e91ea0c12d4f39ccc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb59adb544d416e91ea0c12d4f39ccc9">ADC_SMPR1_SMP12_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb6169f9cd1e9c488526140dcbf464c2">ADC_SMPR1_SMP12_Pos</a>)</td></tr>
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<tr class="memitem:ga9093533a0a301bae03822d9f8bfc7597" id="r_ga9093533a0a301bae03822d9f8bfc7597"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9093533a0a301bae03822d9f8bfc7597">ADC_SMPR1_SMP13_Pos</a>   (9U)</td></tr>
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<tr class="memitem:gaa0b2a1ff66bccc991c783ceca1d69cfd" id="r_gaa0b2a1ff66bccc991c783ceca1d69cfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0b2a1ff66bccc991c783ceca1d69cfd">ADC_SMPR1_SMP13_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9093533a0a301bae03822d9f8bfc7597">ADC_SMPR1_SMP13_Pos</a>)</td></tr>
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<tr class="memitem:ga2df120cd93a177ea17946a656259129e" id="r_ga2df120cd93a177ea17946a656259129e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2df120cd93a177ea17946a656259129e">ADC_SMPR1_SMP13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0b2a1ff66bccc991c783ceca1d69cfd">ADC_SMPR1_SMP13_Msk</a></td></tr>
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<tr class="memitem:ga49e7444d6cf630eccfd52fb4155bd553" id="r_ga49e7444d6cf630eccfd52fb4155bd553"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49e7444d6cf630eccfd52fb4155bd553">ADC_SMPR1_SMP13_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9093533a0a301bae03822d9f8bfc7597">ADC_SMPR1_SMP13_Pos</a>)</td></tr>
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<tr class="memitem:gad5d5ad9d8d08feaee18d1f2d8d6787a1" id="r_gad5d5ad9d8d08feaee18d1f2d8d6787a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5d5ad9d8d08feaee18d1f2d8d6787a1">ADC_SMPR1_SMP13_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9093533a0a301bae03822d9f8bfc7597">ADC_SMPR1_SMP13_Pos</a>)</td></tr>
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<tr class="memitem:gac4cd285d46485136deb6223377d0b17c" id="r_gac4cd285d46485136deb6223377d0b17c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4cd285d46485136deb6223377d0b17c">ADC_SMPR1_SMP13_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9093533a0a301bae03822d9f8bfc7597">ADC_SMPR1_SMP13_Pos</a>)</td></tr>
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<tr class="memitem:ga2da550ca91822740c151e660e6725475" id="r_ga2da550ca91822740c151e660e6725475"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2da550ca91822740c151e660e6725475">ADC_SMPR1_SMP14_Pos</a>   (12U)</td></tr>
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<tr class="memitem:ga410946d711bfd8069e7eb95d6d83e832" id="r_ga410946d711bfd8069e7eb95d6d83e832"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga410946d711bfd8069e7eb95d6d83e832">ADC_SMPR1_SMP14_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2da550ca91822740c151e660e6725475">ADC_SMPR1_SMP14_Pos</a>)</td></tr>
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<tr class="separator:ga410946d711bfd8069e7eb95d6d83e832"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1574fc02a40f22fc751073e02ebb781" id="r_gab1574fc02a40f22fc751073e02ebb781"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1574fc02a40f22fc751073e02ebb781">ADC_SMPR1_SMP14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga410946d711bfd8069e7eb95d6d83e832">ADC_SMPR1_SMP14_Msk</a></td></tr>
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<tr class="memitem:ga9243898272b1d27018c971eecfa57f78" id="r_ga9243898272b1d27018c971eecfa57f78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9243898272b1d27018c971eecfa57f78">ADC_SMPR1_SMP14_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2da550ca91822740c151e660e6725475">ADC_SMPR1_SMP14_Pos</a>)</td></tr>
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<tr class="memitem:ga1016b8ca359247491a2a0a5d77aa1c22" id="r_ga1016b8ca359247491a2a0a5d77aa1c22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1016b8ca359247491a2a0a5d77aa1c22">ADC_SMPR1_SMP14_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2da550ca91822740c151e660e6725475">ADC_SMPR1_SMP14_Pos</a>)</td></tr>
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<tr class="memitem:ga8e658a8b72bac244bf919a874690e49e" id="r_ga8e658a8b72bac244bf919a874690e49e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e658a8b72bac244bf919a874690e49e">ADC_SMPR1_SMP14_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2da550ca91822740c151e660e6725475">ADC_SMPR1_SMP14_Pos</a>)</td></tr>
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<tr class="memitem:gaf4a9dac15edbf7dbc2fa521e57cd0929" id="r_gaf4a9dac15edbf7dbc2fa521e57cd0929"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4a9dac15edbf7dbc2fa521e57cd0929">ADC_SMPR1_SMP15_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga2bd307278f68d42fad28c9a549cee495" id="r_ga2bd307278f68d42fad28c9a549cee495"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bd307278f68d42fad28c9a549cee495">ADC_SMPR1_SMP15_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4a9dac15edbf7dbc2fa521e57cd0929">ADC_SMPR1_SMP15_Pos</a>)</td></tr>
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<tr class="memitem:ga5ae0043ad863f7710834217bc82c8ecf" id="r_ga5ae0043ad863f7710834217bc82c8ecf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ae0043ad863f7710834217bc82c8ecf">ADC_SMPR1_SMP15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2bd307278f68d42fad28c9a549cee495">ADC_SMPR1_SMP15_Msk</a></td></tr>
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<tr class="memitem:gac5f8e555f5ece2ee632dd9d6c60d9584" id="r_gac5f8e555f5ece2ee632dd9d6c60d9584"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5f8e555f5ece2ee632dd9d6c60d9584">ADC_SMPR1_SMP15_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4a9dac15edbf7dbc2fa521e57cd0929">ADC_SMPR1_SMP15_Pos</a>)</td></tr>
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<tr class="memitem:gab978e10b7dcfe6c1b88dd4fef50498ac" id="r_gab978e10b7dcfe6c1b88dd4fef50498ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab978e10b7dcfe6c1b88dd4fef50498ac">ADC_SMPR1_SMP15_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4a9dac15edbf7dbc2fa521e57cd0929">ADC_SMPR1_SMP15_Pos</a>)</td></tr>
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<tr class="memitem:ga045285e1c5ab9ae570e37fe627b0e117" id="r_ga045285e1c5ab9ae570e37fe627b0e117"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga045285e1c5ab9ae570e37fe627b0e117">ADC_SMPR1_SMP15_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4a9dac15edbf7dbc2fa521e57cd0929">ADC_SMPR1_SMP15_Pos</a>)</td></tr>
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<tr class="memitem:gad299a50233bbf403f796758fbce28a27" id="r_gad299a50233bbf403f796758fbce28a27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad299a50233bbf403f796758fbce28a27">ADC_SMPR1_SMP16_Pos</a>   (18U)</td></tr>
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<tr class="memitem:gabbf22b25f0b78dab59b1f8d2e1bbceeb" id="r_gabbf22b25f0b78dab59b1f8d2e1bbceeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbf22b25f0b78dab59b1f8d2e1bbceeb">ADC_SMPR1_SMP16_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad299a50233bbf403f796758fbce28a27">ADC_SMPR1_SMP16_Pos</a>)</td></tr>
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<tr class="memitem:ga2925d05347e46e9c6a970214fa76bbec" id="r_ga2925d05347e46e9c6a970214fa76bbec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2925d05347e46e9c6a970214fa76bbec">ADC_SMPR1_SMP16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabbf22b25f0b78dab59b1f8d2e1bbceeb">ADC_SMPR1_SMP16_Msk</a></td></tr>
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<tr class="memitem:gae1a7d0ef695bd2017bcda3949f0134be" id="r_gae1a7d0ef695bd2017bcda3949f0134be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1a7d0ef695bd2017bcda3949f0134be">ADC_SMPR1_SMP16_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad299a50233bbf403f796758fbce28a27">ADC_SMPR1_SMP16_Pos</a>)</td></tr>
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<tr class="memitem:ga793ff2f46f51e1d485a9bd728687bf15" id="r_ga793ff2f46f51e1d485a9bd728687bf15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga793ff2f46f51e1d485a9bd728687bf15">ADC_SMPR1_SMP16_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad299a50233bbf403f796758fbce28a27">ADC_SMPR1_SMP16_Pos</a>)</td></tr>
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<tr class="memitem:gade321fdbf74f830e54951ccfca285686" id="r_gade321fdbf74f830e54951ccfca285686"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade321fdbf74f830e54951ccfca285686">ADC_SMPR1_SMP16_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad299a50233bbf403f796758fbce28a27">ADC_SMPR1_SMP16_Pos</a>)</td></tr>
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<tr class="memitem:ga5f0af7a5db877331daa8770222909d4d" id="r_ga5f0af7a5db877331daa8770222909d4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f0af7a5db877331daa8770222909d4d">ADC_SMPR1_SMP17_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga5f0af7a5db877331daa8770222909d4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9ca754667b1437b01fb0da560d36e10" id="r_gac9ca754667b1437b01fb0da560d36e10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9ca754667b1437b01fb0da560d36e10">ADC_SMPR1_SMP17_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f0af7a5db877331daa8770222909d4d">ADC_SMPR1_SMP17_Pos</a>)</td></tr>
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<tr class="memitem:ga9867370ecef7b99c32b8ecb44ad9e581" id="r_ga9867370ecef7b99c32b8ecb44ad9e581"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9867370ecef7b99c32b8ecb44ad9e581">ADC_SMPR1_SMP17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9ca754667b1437b01fb0da560d36e10">ADC_SMPR1_SMP17_Msk</a></td></tr>
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<tr class="separator:ga9867370ecef7b99c32b8ecb44ad9e581"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42b004d74f288cb191bfc6a327f94480" id="r_ga42b004d74f288cb191bfc6a327f94480"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42b004d74f288cb191bfc6a327f94480">ADC_SMPR1_SMP17_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f0af7a5db877331daa8770222909d4d">ADC_SMPR1_SMP17_Pos</a>)</td></tr>
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<tr class="memitem:ga3ac4c21586d6a353c208a5175906ecc1" id="r_ga3ac4c21586d6a353c208a5175906ecc1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ac4c21586d6a353c208a5175906ecc1">ADC_SMPR1_SMP17_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f0af7a5db877331daa8770222909d4d">ADC_SMPR1_SMP17_Pos</a>)</td></tr>
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<tr class="memitem:gac81ceec799a7da2def4f33339bd5e273" id="r_gac81ceec799a7da2def4f33339bd5e273"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac81ceec799a7da2def4f33339bd5e273">ADC_SMPR1_SMP17_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f0af7a5db877331daa8770222909d4d">ADC_SMPR1_SMP17_Pos</a>)</td></tr>
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<tr class="memitem:ga6d49003824f10f93348569e720865899" id="r_ga6d49003824f10f93348569e720865899"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d49003824f10f93348569e720865899">ADC_SMPR1_SMP18_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga4c670627d1f5c73fae79914ba1f04475" id="r_ga4c670627d1f5c73fae79914ba1f04475"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c670627d1f5c73fae79914ba1f04475">ADC_SMPR1_SMP18_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d49003824f10f93348569e720865899">ADC_SMPR1_SMP18_Pos</a>)</td></tr>
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<tr class="separator:ga4c670627d1f5c73fae79914ba1f04475"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3c7d84a92899d950de236fe9d14df2c" id="r_gac3c7d84a92899d950de236fe9d14df2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3c7d84a92899d950de236fe9d14df2c">ADC_SMPR1_SMP18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c670627d1f5c73fae79914ba1f04475">ADC_SMPR1_SMP18_Msk</a></td></tr>
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<tr class="memitem:ga6862168bb7688638764defc72120716b" id="r_ga6862168bb7688638764defc72120716b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6862168bb7688638764defc72120716b">ADC_SMPR1_SMP18_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d49003824f10f93348569e720865899">ADC_SMPR1_SMP18_Pos</a>)</td></tr>
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<tr class="memitem:ga72a01c59a0a785b18235641b36735090" id="r_ga72a01c59a0a785b18235641b36735090"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72a01c59a0a785b18235641b36735090">ADC_SMPR1_SMP18_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d49003824f10f93348569e720865899">ADC_SMPR1_SMP18_Pos</a>)</td></tr>
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<tr class="memitem:gaec1addc9c417b4b7693768817b058059" id="r_gaec1addc9c417b4b7693768817b058059"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec1addc9c417b4b7693768817b058059">ADC_SMPR1_SMP18_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d49003824f10f93348569e720865899">ADC_SMPR1_SMP18_Pos</a>)</td></tr>
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<tr class="separator:gaec1addc9c417b4b7693768817b058059"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8509ff53fa9599b3e2756b0029701a12" id="r_ga8509ff53fa9599b3e2756b0029701a12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8509ff53fa9599b3e2756b0029701a12">ADC_SMPR2_SMP0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8509ff53fa9599b3e2756b0029701a12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa46fc7c440c9969355b4fd542b9a6447" id="r_gaa46fc7c440c9969355b4fd542b9a6447"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa46fc7c440c9969355b4fd542b9a6447">ADC_SMPR2_SMP0_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8509ff53fa9599b3e2756b0029701a12">ADC_SMPR2_SMP0_Pos</a>)</td></tr>
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<tr class="separator:gaa46fc7c440c9969355b4fd542b9a6447"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a13b3c652e5759e2d8bc7e38889bc5e" id="r_ga5a13b3c652e5759e2d8bc7e38889bc5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a13b3c652e5759e2d8bc7e38889bc5e">ADC_SMPR2_SMP0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa46fc7c440c9969355b4fd542b9a6447">ADC_SMPR2_SMP0_Msk</a></td></tr>
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<tr class="separator:ga5a13b3c652e5759e2d8bc7e38889bc5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bde59fce56980a59a3dfdb0da7ebe0c" id="r_ga1bde59fce56980a59a3dfdb0da7ebe0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bde59fce56980a59a3dfdb0da7ebe0c">ADC_SMPR2_SMP0_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8509ff53fa9599b3e2756b0029701a12">ADC_SMPR2_SMP0_Pos</a>)</td></tr>
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<tr class="memitem:ga1d5b6e025d8e70767914c144793b93e6" id="r_ga1d5b6e025d8e70767914c144793b93e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d5b6e025d8e70767914c144793b93e6">ADC_SMPR2_SMP0_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8509ff53fa9599b3e2756b0029701a12">ADC_SMPR2_SMP0_Pos</a>)</td></tr>
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<tr class="separator:ga1d5b6e025d8e70767914c144793b93e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga361de56c56c45834fc837df349f155dc" id="r_ga361de56c56c45834fc837df349f155dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga361de56c56c45834fc837df349f155dc">ADC_SMPR2_SMP0_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8509ff53fa9599b3e2756b0029701a12">ADC_SMPR2_SMP0_Pos</a>)</td></tr>
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<tr class="separator:ga361de56c56c45834fc837df349f155dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a7d6076724526beda6cb481eb3ea5e7" id="r_ga3a7d6076724526beda6cb481eb3ea5e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a7d6076724526beda6cb481eb3ea5e7">ADC_SMPR2_SMP1_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga3a7d6076724526beda6cb481eb3ea5e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39b8904a2aa672a622471712507c39c7" id="r_ga39b8904a2aa672a622471712507c39c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39b8904a2aa672a622471712507c39c7">ADC_SMPR2_SMP1_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a7d6076724526beda6cb481eb3ea5e7">ADC_SMPR2_SMP1_Pos</a>)</td></tr>
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<tr class="separator:ga39b8904a2aa672a622471712507c39c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b85dd0b1708cdf1bf403b07ad51da36" id="r_ga5b85dd0b1708cdf1bf403b07ad51da36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b85dd0b1708cdf1bf403b07ad51da36">ADC_SMPR2_SMP1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga39b8904a2aa672a622471712507c39c7">ADC_SMPR2_SMP1_Msk</a></td></tr>
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<tr class="separator:ga5b85dd0b1708cdf1bf403b07ad51da36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa99de1a2d2bbe8921353114d03cb7f6" id="r_gaaa99de1a2d2bbe8921353114d03cb7f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa99de1a2d2bbe8921353114d03cb7f6">ADC_SMPR2_SMP1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a7d6076724526beda6cb481eb3ea5e7">ADC_SMPR2_SMP1_Pos</a>)</td></tr>
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<tr class="memitem:gaf6ceb41e5e3cb6ae7da28070bc0b07d2" id="r_gaf6ceb41e5e3cb6ae7da28070bc0b07d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6ceb41e5e3cb6ae7da28070bc0b07d2">ADC_SMPR2_SMP1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a7d6076724526beda6cb481eb3ea5e7">ADC_SMPR2_SMP1_Pos</a>)</td></tr>
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<tr class="separator:gaf6ceb41e5e3cb6ae7da28070bc0b07d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b9efc8f9488d389301c4a6f9ef4427a" id="r_ga8b9efc8f9488d389301c4a6f9ef4427a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b9efc8f9488d389301c4a6f9ef4427a">ADC_SMPR2_SMP1_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a7d6076724526beda6cb481eb3ea5e7">ADC_SMPR2_SMP1_Pos</a>)</td></tr>
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<tr class="memitem:ga8f3716b7531126383d5f4f26c55b17a0" id="r_ga8f3716b7531126383d5f4f26c55b17a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f3716b7531126383d5f4f26c55b17a0">ADC_SMPR2_SMP2_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga8f3716b7531126383d5f4f26c55b17a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf47f3ef6dad5ad4ab6a70f7256cce7bf" id="r_gaf47f3ef6dad5ad4ab6a70f7256cce7bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf47f3ef6dad5ad4ab6a70f7256cce7bf">ADC_SMPR2_SMP2_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f3716b7531126383d5f4f26c55b17a0">ADC_SMPR2_SMP2_Pos</a>)</td></tr>
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<tr class="separator:gaf47f3ef6dad5ad4ab6a70f7256cce7bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea6e1e298372596bcdcdf93e763b3683" id="r_gaea6e1e298372596bcdcdf93e763b3683"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea6e1e298372596bcdcdf93e763b3683">ADC_SMPR2_SMP2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf47f3ef6dad5ad4ab6a70f7256cce7bf">ADC_SMPR2_SMP2_Msk</a></td></tr>
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<tr class="separator:gaea6e1e298372596bcdcdf93e763b3683"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97e2ac0d4d8afb3aa0b4c09c8fa1d018" id="r_ga97e2ac0d4d8afb3aa0b4c09c8fa1d018"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97e2ac0d4d8afb3aa0b4c09c8fa1d018">ADC_SMPR2_SMP2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f3716b7531126383d5f4f26c55b17a0">ADC_SMPR2_SMP2_Pos</a>)</td></tr>
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<tr class="separator:ga97e2ac0d4d8afb3aa0b4c09c8fa1d018"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83fe79e3e10b689a209dc5a724f89199" id="r_ga83fe79e3e10b689a209dc5a724f89199"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83fe79e3e10b689a209dc5a724f89199">ADC_SMPR2_SMP2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f3716b7531126383d5f4f26c55b17a0">ADC_SMPR2_SMP2_Pos</a>)</td></tr>
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<tr class="separator:ga83fe79e3e10b689a209dc5a724f89199"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad580d376e0a0bcb34183a6d6735b3122" id="r_gad580d376e0a0bcb34183a6d6735b3122"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad580d376e0a0bcb34183a6d6735b3122">ADC_SMPR2_SMP2_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f3716b7531126383d5f4f26c55b17a0">ADC_SMPR2_SMP2_Pos</a>)</td></tr>
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<tr class="memitem:ga46bbf950a5d9f629a48b7f9faebbcc55" id="r_ga46bbf950a5d9f629a48b7f9faebbcc55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46bbf950a5d9f629a48b7f9faebbcc55">ADC_SMPR2_SMP3_Pos</a>   (9U)</td></tr>
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<tr class="memitem:ga305cad42f0aae469c0f63a79de6bbf2a" id="r_ga305cad42f0aae469c0f63a79de6bbf2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga305cad42f0aae469c0f63a79de6bbf2a">ADC_SMPR2_SMP3_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46bbf950a5d9f629a48b7f9faebbcc55">ADC_SMPR2_SMP3_Pos</a>)</td></tr>
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<tr class="memitem:ga081c3d61e5311a11cb046d56630e1fd0" id="r_ga081c3d61e5311a11cb046d56630e1fd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga081c3d61e5311a11cb046d56630e1fd0">ADC_SMPR2_SMP3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga305cad42f0aae469c0f63a79de6bbf2a">ADC_SMPR2_SMP3_Msk</a></td></tr>
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<tr class="memitem:gaa1679a42f67ca4b9b9496dd6000fec01" id="r_gaa1679a42f67ca4b9b9496dd6000fec01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1679a42f67ca4b9b9496dd6000fec01">ADC_SMPR2_SMP3_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46bbf950a5d9f629a48b7f9faebbcc55">ADC_SMPR2_SMP3_Pos</a>)</td></tr>
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<tr class="memitem:ga1bf92b0a67dcec9b3c325d58e7e517b0" id="r_ga1bf92b0a67dcec9b3c325d58e7e517b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bf92b0a67dcec9b3c325d58e7e517b0">ADC_SMPR2_SMP3_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46bbf950a5d9f629a48b7f9faebbcc55">ADC_SMPR2_SMP3_Pos</a>)</td></tr>
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<tr class="memitem:ga40682268fa8534bd369eb64a329bdf46" id="r_ga40682268fa8534bd369eb64a329bdf46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40682268fa8534bd369eb64a329bdf46">ADC_SMPR2_SMP3_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46bbf950a5d9f629a48b7f9faebbcc55">ADC_SMPR2_SMP3_Pos</a>)</td></tr>
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<tr class="memitem:gad8fe44c9dc72211b7255b4355462f680" id="r_gad8fe44c9dc72211b7255b4355462f680"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8fe44c9dc72211b7255b4355462f680">ADC_SMPR2_SMP4_Pos</a>   (12U)</td></tr>
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<tr class="memitem:ga41d006fba68f1e84ff3bd0ec21f61233" id="r_ga41d006fba68f1e84ff3bd0ec21f61233"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41d006fba68f1e84ff3bd0ec21f61233">ADC_SMPR2_SMP4_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad8fe44c9dc72211b7255b4355462f680">ADC_SMPR2_SMP4_Pos</a>)</td></tr>
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<tr class="memitem:gaeab838fcf0aace87b2163b96d208bb64" id="r_gaeab838fcf0aace87b2163b96d208bb64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeab838fcf0aace87b2163b96d208bb64">ADC_SMPR2_SMP4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga41d006fba68f1e84ff3bd0ec21f61233">ADC_SMPR2_SMP4_Msk</a></td></tr>
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<tr class="memitem:gae4123bce64dc4f1831f992b09d6db4f2" id="r_gae4123bce64dc4f1831f992b09d6db4f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4123bce64dc4f1831f992b09d6db4f2">ADC_SMPR2_SMP4_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad8fe44c9dc72211b7255b4355462f680">ADC_SMPR2_SMP4_Pos</a>)</td></tr>
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<tr class="memitem:gad3edf57b459804d17d5a588dd446c763" id="r_gad3edf57b459804d17d5a588dd446c763"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3edf57b459804d17d5a588dd446c763">ADC_SMPR2_SMP4_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad8fe44c9dc72211b7255b4355462f680">ADC_SMPR2_SMP4_Pos</a>)</td></tr>
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<tr class="memitem:gac2a2fd74311c4ffcaed4a8d1a3be2245" id="r_gac2a2fd74311c4ffcaed4a8d1a3be2245"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2a2fd74311c4ffcaed4a8d1a3be2245">ADC_SMPR2_SMP4_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad8fe44c9dc72211b7255b4355462f680">ADC_SMPR2_SMP4_Pos</a>)</td></tr>
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<tr class="memitem:gafdd88f74dea228c26eeb5bcbd9513012" id="r_gafdd88f74dea228c26eeb5bcbd9513012"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdd88f74dea228c26eeb5bcbd9513012">ADC_SMPR2_SMP5_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga9b8b4a18f347d72459aa84fd6a2629a8" id="r_ga9b8b4a18f347d72459aa84fd6a2629a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b8b4a18f347d72459aa84fd6a2629a8">ADC_SMPR2_SMP5_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafdd88f74dea228c26eeb5bcbd9513012">ADC_SMPR2_SMP5_Pos</a>)</td></tr>
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<tr class="memitem:ga9500281fa740994b9cfa6a7df8227849" id="r_ga9500281fa740994b9cfa6a7df8227849"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9500281fa740994b9cfa6a7df8227849">ADC_SMPR2_SMP5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b8b4a18f347d72459aa84fd6a2629a8">ADC_SMPR2_SMP5_Msk</a></td></tr>
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<tr class="memitem:ga22dd2b1695a4e7a4b1d4ec2b8e244ffc" id="r_ga22dd2b1695a4e7a4b1d4ec2b8e244ffc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22dd2b1695a4e7a4b1d4ec2b8e244ffc">ADC_SMPR2_SMP5_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafdd88f74dea228c26eeb5bcbd9513012">ADC_SMPR2_SMP5_Pos</a>)</td></tr>
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<tr class="memitem:gab4de4f6c62646be62d0710dc46eb5e88" id="r_gab4de4f6c62646be62d0710dc46eb5e88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4de4f6c62646be62d0710dc46eb5e88">ADC_SMPR2_SMP5_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafdd88f74dea228c26eeb5bcbd9513012">ADC_SMPR2_SMP5_Pos</a>)</td></tr>
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<tr class="memitem:ga6c19081d82f2c6478c6aefc207778e1e" id="r_ga6c19081d82f2c6478c6aefc207778e1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c19081d82f2c6478c6aefc207778e1e">ADC_SMPR2_SMP5_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafdd88f74dea228c26eeb5bcbd9513012">ADC_SMPR2_SMP5_Pos</a>)</td></tr>
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<tr class="memitem:gac7ad6181795d9407c499d6c5d87c7056" id="r_gac7ad6181795d9407c499d6c5d87c7056"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7ad6181795d9407c499d6c5d87c7056">ADC_SMPR2_SMP6_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga63b337299939afb7336f2579bd3a727c" id="r_ga63b337299939afb7336f2579bd3a727c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63b337299939afb7336f2579bd3a727c">ADC_SMPR2_SMP6_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac7ad6181795d9407c499d6c5d87c7056">ADC_SMPR2_SMP6_Pos</a>)</td></tr>
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<tr class="memitem:ga64cd99c27d07298913541dbdc31aa8ae" id="r_ga64cd99c27d07298913541dbdc31aa8ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64cd99c27d07298913541dbdc31aa8ae">ADC_SMPR2_SMP6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63b337299939afb7336f2579bd3a727c">ADC_SMPR2_SMP6_Msk</a></td></tr>
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<tr class="memitem:gadbebc0a7f368e5846408d768603d9b44" id="r_gadbebc0a7f368e5846408d768603d9b44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbebc0a7f368e5846408d768603d9b44">ADC_SMPR2_SMP6_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac7ad6181795d9407c499d6c5d87c7056">ADC_SMPR2_SMP6_Pos</a>)</td></tr>
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<tr class="memitem:ga27f59166864f7cd0a5e8e6b4450e72d3" id="r_ga27f59166864f7cd0a5e8e6b4450e72d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27f59166864f7cd0a5e8e6b4450e72d3">ADC_SMPR2_SMP6_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac7ad6181795d9407c499d6c5d87c7056">ADC_SMPR2_SMP6_Pos</a>)</td></tr>
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<tr class="memitem:ga4139fac7e8ba3e604e35ba906880f909" id="r_ga4139fac7e8ba3e604e35ba906880f909"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4139fac7e8ba3e604e35ba906880f909">ADC_SMPR2_SMP6_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac7ad6181795d9407c499d6c5d87c7056">ADC_SMPR2_SMP6_Pos</a>)</td></tr>
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<tr class="memitem:gaeb68d22ee2b8a9a6238d08b3c5f0417c" id="r_gaeb68d22ee2b8a9a6238d08b3c5f0417c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb68d22ee2b8a9a6238d08b3c5f0417c">ADC_SMPR2_SMP7_Pos</a>   (21U)</td></tr>
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<tr class="memitem:ga8f8b7b73b7ac647dd48d114f683afc55" id="r_ga8f8b7b73b7ac647dd48d114f683afc55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f8b7b73b7ac647dd48d114f683afc55">ADC_SMPR2_SMP7_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb68d22ee2b8a9a6238d08b3c5f0417c">ADC_SMPR2_SMP7_Pos</a>)</td></tr>
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<tr class="memitem:ga6ec6ee971fc8b2d1890858df94a5c500" id="r_ga6ec6ee971fc8b2d1890858df94a5c500"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ec6ee971fc8b2d1890858df94a5c500">ADC_SMPR2_SMP7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f8b7b73b7ac647dd48d114f683afc55">ADC_SMPR2_SMP7_Msk</a></td></tr>
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<tr class="memitem:ga6f30003c59ab6c232d73aa446c77651a" id="r_ga6f30003c59ab6c232d73aa446c77651a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f30003c59ab6c232d73aa446c77651a">ADC_SMPR2_SMP7_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb68d22ee2b8a9a6238d08b3c5f0417c">ADC_SMPR2_SMP7_Pos</a>)</td></tr>
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<tr class="memitem:ga0c8708fc97082257b43fa4534c721068" id="r_ga0c8708fc97082257b43fa4534c721068"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c8708fc97082257b43fa4534c721068">ADC_SMPR2_SMP7_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb68d22ee2b8a9a6238d08b3c5f0417c">ADC_SMPR2_SMP7_Pos</a>)</td></tr>
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<tr class="memitem:ga2e42897bdc25951a73bac060a7a065ca" id="r_ga2e42897bdc25951a73bac060a7a065ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e42897bdc25951a73bac060a7a065ca">ADC_SMPR2_SMP7_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb68d22ee2b8a9a6238d08b3c5f0417c">ADC_SMPR2_SMP7_Pos</a>)</td></tr>
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<tr class="memitem:gab45620208290dbe572341227dd291c5d" id="r_gab45620208290dbe572341227dd291c5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab45620208290dbe572341227dd291c5d">ADC_SMPR2_SMP8_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga0390786a9cb491305c18fe615acfd13f" id="r_ga0390786a9cb491305c18fe615acfd13f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0390786a9cb491305c18fe615acfd13f">ADC_SMPR2_SMP8_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab45620208290dbe572341227dd291c5d">ADC_SMPR2_SMP8_Pos</a>)</td></tr>
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<tr class="memitem:ga0695c289e658b772070a7f29797e9cc3" id="r_ga0695c289e658b772070a7f29797e9cc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0695c289e658b772070a7f29797e9cc3">ADC_SMPR2_SMP8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0390786a9cb491305c18fe615acfd13f">ADC_SMPR2_SMP8_Msk</a></td></tr>
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<tr class="separator:ga0695c289e658b772070a7f29797e9cc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5f1d2290107eda2dfee33810779b0f6" id="r_gab5f1d2290107eda2dfee33810779b0f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5f1d2290107eda2dfee33810779b0f6">ADC_SMPR2_SMP8_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab45620208290dbe572341227dd291c5d">ADC_SMPR2_SMP8_Pos</a>)</td></tr>
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<tr class="separator:gab5f1d2290107eda2dfee33810779b0f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb9ce9d71f989bad0ed686caf4dd5250" id="r_gabb9ce9d71f989bad0ed686caf4dd5250"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb9ce9d71f989bad0ed686caf4dd5250">ADC_SMPR2_SMP8_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab45620208290dbe572341227dd291c5d">ADC_SMPR2_SMP8_Pos</a>)</td></tr>
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<tr class="memitem:ga3756c6141f55c60da0bcd4d599e7d60d" id="r_ga3756c6141f55c60da0bcd4d599e7d60d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3756c6141f55c60da0bcd4d599e7d60d">ADC_SMPR2_SMP8_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab45620208290dbe572341227dd291c5d">ADC_SMPR2_SMP8_Pos</a>)</td></tr>
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<tr class="separator:ga3756c6141f55c60da0bcd4d599e7d60d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39bc8143f781965172d5e6e023529abc" id="r_ga39bc8143f781965172d5e6e023529abc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39bc8143f781965172d5e6e023529abc">ADC_SMPR2_SMP9_Pos</a>   (27U)</td></tr>
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<tr class="memitem:ga1b124d3d088448db3cd97db242b125cf" id="r_ga1b124d3d088448db3cd97db242b125cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b124d3d088448db3cd97db242b125cf">ADC_SMPR2_SMP9_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga39bc8143f781965172d5e6e023529abc">ADC_SMPR2_SMP9_Pos</a>)</td></tr>
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<tr class="separator:ga1b124d3d088448db3cd97db242b125cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5348f83daaa38060702d7b9cfe2e4005" id="r_ga5348f83daaa38060702d7b9cfe2e4005"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5348f83daaa38060702d7b9cfe2e4005">ADC_SMPR2_SMP9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b124d3d088448db3cd97db242b125cf">ADC_SMPR2_SMP9_Msk</a></td></tr>
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<tr class="separator:ga5348f83daaa38060702d7b9cfe2e4005"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga892f18c89fbaafc74b7d67db74b41423" id="r_ga892f18c89fbaafc74b7d67db74b41423"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga892f18c89fbaafc74b7d67db74b41423">ADC_SMPR2_SMP9_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga39bc8143f781965172d5e6e023529abc">ADC_SMPR2_SMP9_Pos</a>)</td></tr>
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<tr class="separator:ga892f18c89fbaafc74b7d67db74b41423"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a6949e61c5845a7ff2331b64cb579bc" id="r_ga3a6949e61c5845a7ff2331b64cb579bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a6949e61c5845a7ff2331b64cb579bc">ADC_SMPR2_SMP9_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga39bc8143f781965172d5e6e023529abc">ADC_SMPR2_SMP9_Pos</a>)</td></tr>
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<tr class="separator:ga3a6949e61c5845a7ff2331b64cb579bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga070135017850599b1e19766c6aa31cd1" id="r_ga070135017850599b1e19766c6aa31cd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga070135017850599b1e19766c6aa31cd1">ADC_SMPR2_SMP9_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga39bc8143f781965172d5e6e023529abc">ADC_SMPR2_SMP9_Pos</a>)</td></tr>
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<tr class="memitem:ga593196324c441869e2b7629db926aafd" id="r_ga593196324c441869e2b7629db926aafd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga593196324c441869e2b7629db926aafd">ADC_JOFR1_JOFFSET1_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga4aeb01e5e14a55e3de62770ff3b3d0fd" id="r_ga4aeb01e5e14a55e3de62770ff3b3d0fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4aeb01e5e14a55e3de62770ff3b3d0fd">ADC_JOFR1_JOFFSET1_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga593196324c441869e2b7629db926aafd">ADC_JOFR1_JOFFSET1_Pos</a>)</td></tr>
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<tr class="separator:ga4aeb01e5e14a55e3de62770ff3b3d0fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad76f97130b391455094605a6c803026c" id="r_gad76f97130b391455094605a6c803026c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad76f97130b391455094605a6c803026c">ADC_JOFR1_JOFFSET1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4aeb01e5e14a55e3de62770ff3b3d0fd">ADC_JOFR1_JOFFSET1_Msk</a></td></tr>
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<tr class="separator:gad76f97130b391455094605a6c803026c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15e0dc116f3623901fdda1e743838334" id="r_ga15e0dc116f3623901fdda1e743838334"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15e0dc116f3623901fdda1e743838334">ADC_JOFR2_JOFFSET2_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga15e0dc116f3623901fdda1e743838334"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21ef3d2ed0de640e567ecefb4c902df4" id="r_ga21ef3d2ed0de640e567ecefb4c902df4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21ef3d2ed0de640e567ecefb4c902df4">ADC_JOFR2_JOFFSET2_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga15e0dc116f3623901fdda1e743838334">ADC_JOFR2_JOFFSET2_Pos</a>)</td></tr>
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<tr class="separator:ga21ef3d2ed0de640e567ecefb4c902df4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b15a9e9ce10303e233059c1de6d956c" id="r_ga1b15a9e9ce10303e233059c1de6d956c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b15a9e9ce10303e233059c1de6d956c">ADC_JOFR2_JOFFSET2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga21ef3d2ed0de640e567ecefb4c902df4">ADC_JOFR2_JOFFSET2_Msk</a></td></tr>
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<tr class="separator:ga1b15a9e9ce10303e233059c1de6d956c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad339e95766c1c4dd3ec3ef2fa5856f8b" id="r_gad339e95766c1c4dd3ec3ef2fa5856f8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad339e95766c1c4dd3ec3ef2fa5856f8b">ADC_JOFR3_JOFFSET3_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad339e95766c1c4dd3ec3ef2fa5856f8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e742777e82d2e3a58f789f7785fa530" id="r_ga8e742777e82d2e3a58f789f7785fa530"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e742777e82d2e3a58f789f7785fa530">ADC_JOFR3_JOFFSET3_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad339e95766c1c4dd3ec3ef2fa5856f8b">ADC_JOFR3_JOFFSET3_Pos</a>)</td></tr>
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<tr class="separator:ga8e742777e82d2e3a58f789f7785fa530"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga743e4c3a7cefc1a193146e77791c3985" id="r_ga743e4c3a7cefc1a193146e77791c3985"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga743e4c3a7cefc1a193146e77791c3985">ADC_JOFR3_JOFFSET3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e742777e82d2e3a58f789f7785fa530">ADC_JOFR3_JOFFSET3_Msk</a></td></tr>
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<tr class="separator:ga743e4c3a7cefc1a193146e77791c3985"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb1f1ccebbb9c41f3b6bae1f8c587618" id="r_gaeb1f1ccebbb9c41f3b6bae1f8c587618"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb1f1ccebbb9c41f3b6bae1f8c587618">ADC_JOFR4_JOFFSET4_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaeb1f1ccebbb9c41f3b6bae1f8c587618"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga983eba37929e630bc6bec3c1ab411db5" id="r_ga983eba37929e630bc6bec3c1ab411db5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga983eba37929e630bc6bec3c1ab411db5">ADC_JOFR4_JOFFSET4_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb1f1ccebbb9c41f3b6bae1f8c587618">ADC_JOFR4_JOFFSET4_Pos</a>)</td></tr>
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<tr class="separator:ga983eba37929e630bc6bec3c1ab411db5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada0937f2f6a64bd6b7531ad553471b8d" id="r_gada0937f2f6a64bd6b7531ad553471b8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada0937f2f6a64bd6b7531ad553471b8d">ADC_JOFR4_JOFFSET4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga983eba37929e630bc6bec3c1ab411db5">ADC_JOFR4_JOFFSET4_Msk</a></td></tr>
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<tr class="separator:gada0937f2f6a64bd6b7531ad553471b8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a635538ea4e4daa6b302e0d2d5c0932" id="r_ga4a635538ea4e4daa6b302e0d2d5c0932"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a635538ea4e4daa6b302e0d2d5c0932">ADC_HTR_HT_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4a635538ea4e4daa6b302e0d2d5c0932"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9097907041c9d3893ab46b359ade4b00" id="r_ga9097907041c9d3893ab46b359ade4b00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9097907041c9d3893ab46b359ade4b00">ADC_HTR_HT_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a635538ea4e4daa6b302e0d2d5c0932">ADC_HTR_HT_Pos</a>)</td></tr>
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<tr class="memitem:gad685f031174465e636ef75a5bd7b637d" id="r_gad685f031174465e636ef75a5bd7b637d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad685f031174465e636ef75a5bd7b637d">ADC_HTR_HT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9097907041c9d3893ab46b359ade4b00">ADC_HTR_HT_Msk</a></td></tr>
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<tr class="memitem:ga309e0c5c17cfe008132dbc95924ba0cd" id="r_ga309e0c5c17cfe008132dbc95924ba0cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga309e0c5c17cfe008132dbc95924ba0cd">ADC_LTR_LT_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga309e0c5c17cfe008132dbc95924ba0cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1c59cf6098c3ba86d00ff2eabbee680" id="r_gad1c59cf6098c3ba86d00ff2eabbee680"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1c59cf6098c3ba86d00ff2eabbee680">ADC_LTR_LT_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga309e0c5c17cfe008132dbc95924ba0cd">ADC_LTR_LT_Pos</a>)</td></tr>
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<tr class="separator:gad1c59cf6098c3ba86d00ff2eabbee680"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7ac18b970378acf726f04ae68232c24" id="r_gac7ac18b970378acf726f04ae68232c24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7ac18b970378acf726f04ae68232c24">ADC_LTR_LT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad1c59cf6098c3ba86d00ff2eabbee680">ADC_LTR_LT_Msk</a></td></tr>
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<tr class="memitem:ga881b03d9be116c006dab51c6c46aee4e" id="r_ga881b03d9be116c006dab51c6c46aee4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga881b03d9be116c006dab51c6c46aee4e">ADC_SQR1_SQ13_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga881b03d9be116c006dab51c6c46aee4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08e9c7dc59718bbfbf1a3db4eba22f86" id="r_ga08e9c7dc59718bbfbf1a3db4eba22f86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08e9c7dc59718bbfbf1a3db4eba22f86">ADC_SQR1_SQ13_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga881b03d9be116c006dab51c6c46aee4e">ADC_SQR1_SQ13_Pos</a>)</td></tr>
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<tr class="memitem:ga1ae1998c0dd11275958e7347a92852fc" id="r_ga1ae1998c0dd11275958e7347a92852fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ae1998c0dd11275958e7347a92852fc">ADC_SQR1_SQ13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga08e9c7dc59718bbfbf1a3db4eba22f86">ADC_SQR1_SQ13_Msk</a></td></tr>
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<tr class="memitem:ga40d24ddd458198e7731d5abf9d15fc08" id="r_ga40d24ddd458198e7731d5abf9d15fc08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40d24ddd458198e7731d5abf9d15fc08">ADC_SQR1_SQ13_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga881b03d9be116c006dab51c6c46aee4e">ADC_SQR1_SQ13_Pos</a>)</td></tr>
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<tr class="memitem:gaccdca8b0f3cab9f62ae2ffbb9c30546f" id="r_gaccdca8b0f3cab9f62ae2ffbb9c30546f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccdca8b0f3cab9f62ae2ffbb9c30546f">ADC_SQR1_SQ13_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga881b03d9be116c006dab51c6c46aee4e">ADC_SQR1_SQ13_Pos</a>)</td></tr>
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<tr class="memitem:ga37e8723bfdc43da0b86e40a49b78c9ad" id="r_ga37e8723bfdc43da0b86e40a49b78c9ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37e8723bfdc43da0b86e40a49b78c9ad">ADC_SQR1_SQ13_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga881b03d9be116c006dab51c6c46aee4e">ADC_SQR1_SQ13_Pos</a>)</td></tr>
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<tr class="memitem:ga412374f7ce1f62ee187c819391898778" id="r_ga412374f7ce1f62ee187c819391898778"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga412374f7ce1f62ee187c819391898778">ADC_SQR1_SQ13_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga881b03d9be116c006dab51c6c46aee4e">ADC_SQR1_SQ13_Pos</a>)</td></tr>
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<tr class="memitem:ga05ca5e303f844f512c9a9cb5df9a1028" id="r_ga05ca5e303f844f512c9a9cb5df9a1028"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05ca5e303f844f512c9a9cb5df9a1028">ADC_SQR1_SQ13_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga881b03d9be116c006dab51c6c46aee4e">ADC_SQR1_SQ13_Pos</a>)</td></tr>
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<tr class="memitem:ga6ca511d19962e09ad2294844874a00de" id="r_ga6ca511d19962e09ad2294844874a00de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ca511d19962e09ad2294844874a00de">ADC_SQR1_SQ14_Pos</a>   (5U)</td></tr>
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<tr class="memitem:gac16eaf610307245433e59aee05bfe254" id="r_gac16eaf610307245433e59aee05bfe254"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac16eaf610307245433e59aee05bfe254">ADC_SQR1_SQ14_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ca511d19962e09ad2294844874a00de">ADC_SQR1_SQ14_Pos</a>)</td></tr>
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<tr class="memitem:gab0251199146cb3d0d2c1c0608fbca585" id="r_gab0251199146cb3d0d2c1c0608fbca585"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0251199146cb3d0d2c1c0608fbca585">ADC_SQR1_SQ14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac16eaf610307245433e59aee05bfe254">ADC_SQR1_SQ14_Msk</a></td></tr>
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<tr class="memitem:gacde3a6d9e94aa1c2399e335911fd6212" id="r_gacde3a6d9e94aa1c2399e335911fd6212"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacde3a6d9e94aa1c2399e335911fd6212">ADC_SQR1_SQ14_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ca511d19962e09ad2294844874a00de">ADC_SQR1_SQ14_Pos</a>)</td></tr>
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<tr class="memitem:ga1bc61e4d3ea200e1fc3e9d621ebbd2b4" id="r_ga1bc61e4d3ea200e1fc3e9d621ebbd2b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc61e4d3ea200e1fc3e9d621ebbd2b4">ADC_SQR1_SQ14_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ca511d19962e09ad2294844874a00de">ADC_SQR1_SQ14_Pos</a>)</td></tr>
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<tr class="memitem:gaeea616e444521cd58c5d8d574c47ccf0" id="r_gaeea616e444521cd58c5d8d574c47ccf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeea616e444521cd58c5d8d574c47ccf0">ADC_SQR1_SQ14_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ca511d19962e09ad2294844874a00de">ADC_SQR1_SQ14_Pos</a>)</td></tr>
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<tr class="memitem:ga0e0c9439633fb5c67c8f2138c9d2efae" id="r_ga0e0c9439633fb5c67c8f2138c9d2efae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e0c9439633fb5c67c8f2138c9d2efae">ADC_SQR1_SQ14_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ca511d19962e09ad2294844874a00de">ADC_SQR1_SQ14_Pos</a>)</td></tr>
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<tr class="memitem:gaea22b4dd0fbb26d2a0babbc483778b0e" id="r_gaea22b4dd0fbb26d2a0babbc483778b0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea22b4dd0fbb26d2a0babbc483778b0e">ADC_SQR1_SQ14_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ca511d19962e09ad2294844874a00de">ADC_SQR1_SQ14_Pos</a>)</td></tr>
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<tr class="memitem:ga21eb97eeceffa9eb2cd4aea37af8b13f" id="r_ga21eb97eeceffa9eb2cd4aea37af8b13f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21eb97eeceffa9eb2cd4aea37af8b13f">ADC_SQR1_SQ15_Pos</a>   (10U)</td></tr>
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<tr class="memitem:ga2dcdc56b5476a5cbed60e74735574831" id="r_ga2dcdc56b5476a5cbed60e74735574831"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dcdc56b5476a5cbed60e74735574831">ADC_SQR1_SQ15_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21eb97eeceffa9eb2cd4aea37af8b13f">ADC_SQR1_SQ15_Pos</a>)</td></tr>
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<tr class="memitem:ga23222c591c6d926f7a741bc9346f1d8f" id="r_ga23222c591c6d926f7a741bc9346f1d8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23222c591c6d926f7a741bc9346f1d8f">ADC_SQR1_SQ15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2dcdc56b5476a5cbed60e74735574831">ADC_SQR1_SQ15_Msk</a></td></tr>
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<tr class="memitem:gacbfbc70f67ce1d8f227e17a7f19c123b" id="r_gacbfbc70f67ce1d8f227e17a7f19c123b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbfbc70f67ce1d8f227e17a7f19c123b">ADC_SQR1_SQ15_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21eb97eeceffa9eb2cd4aea37af8b13f">ADC_SQR1_SQ15_Pos</a>)</td></tr>
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<tr class="memitem:gac00e343ff0dd8f1f29e897148e3e070a" id="r_gac00e343ff0dd8f1f29e897148e3e070a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac00e343ff0dd8f1f29e897148e3e070a">ADC_SQR1_SQ15_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21eb97eeceffa9eb2cd4aea37af8b13f">ADC_SQR1_SQ15_Pos</a>)</td></tr>
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<tr class="memitem:gab63443b0c5a2eca60a8c9714f6f31c03" id="r_gab63443b0c5a2eca60a8c9714f6f31c03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab63443b0c5a2eca60a8c9714f6f31c03">ADC_SQR1_SQ15_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21eb97eeceffa9eb2cd4aea37af8b13f">ADC_SQR1_SQ15_Pos</a>)</td></tr>
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<tr class="memitem:gadf676d45ba227a2dc641b2afadfa7852" id="r_gadf676d45ba227a2dc641b2afadfa7852"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf676d45ba227a2dc641b2afadfa7852">ADC_SQR1_SQ15_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21eb97eeceffa9eb2cd4aea37af8b13f">ADC_SQR1_SQ15_Pos</a>)</td></tr>
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<tr class="memitem:ga7dbc07d0904f60abcc15827ccab1a8c2" id="r_ga7dbc07d0904f60abcc15827ccab1a8c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7dbc07d0904f60abcc15827ccab1a8c2">ADC_SQR1_SQ15_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21eb97eeceffa9eb2cd4aea37af8b13f">ADC_SQR1_SQ15_Pos</a>)</td></tr>
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<tr class="memitem:ga175666e476ceceebaa0f3267aeb6ea09" id="r_ga175666e476ceceebaa0f3267aeb6ea09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga175666e476ceceebaa0f3267aeb6ea09">ADC_SQR1_SQ16_Pos</a>   (15U)</td></tr>
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<tr class="memitem:gabddb795f3c7a42aba72d3961e19cc7fc" id="r_gabddb795f3c7a42aba72d3961e19cc7fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabddb795f3c7a42aba72d3961e19cc7fc">ADC_SQR1_SQ16_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga175666e476ceceebaa0f3267aeb6ea09">ADC_SQR1_SQ16_Pos</a>)</td></tr>
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<tr class="memitem:gafecb33099669a080cede6ce0236389e7" id="r_gafecb33099669a080cede6ce0236389e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafecb33099669a080cede6ce0236389e7">ADC_SQR1_SQ16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabddb795f3c7a42aba72d3961e19cc7fc">ADC_SQR1_SQ16_Msk</a></td></tr>
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<tr class="memitem:ga3404d0bf04b8561bf93455d968b77ea9" id="r_ga3404d0bf04b8561bf93455d968b77ea9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3404d0bf04b8561bf93455d968b77ea9">ADC_SQR1_SQ16_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga175666e476ceceebaa0f3267aeb6ea09">ADC_SQR1_SQ16_Pos</a>)</td></tr>
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<tr class="separator:ga3404d0bf04b8561bf93455d968b77ea9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ea6af777051f14be5cf166dd4ae69d1" id="r_ga7ea6af777051f14be5cf166dd4ae69d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ea6af777051f14be5cf166dd4ae69d1">ADC_SQR1_SQ16_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga175666e476ceceebaa0f3267aeb6ea09">ADC_SQR1_SQ16_Pos</a>)</td></tr>
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<tr class="memitem:gaf59e4a113346ac3daf6829c3321444f5" id="r_gaf59e4a113346ac3daf6829c3321444f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf59e4a113346ac3daf6829c3321444f5">ADC_SQR1_SQ16_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga175666e476ceceebaa0f3267aeb6ea09">ADC_SQR1_SQ16_Pos</a>)</td></tr>
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<tr class="memitem:ga6052517e5fcab3f58c42b59fb3ffee55" id="r_ga6052517e5fcab3f58c42b59fb3ffee55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6052517e5fcab3f58c42b59fb3ffee55">ADC_SQR1_SQ16_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga175666e476ceceebaa0f3267aeb6ea09">ADC_SQR1_SQ16_Pos</a>)</td></tr>
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<tr class="memitem:ga7af851b5898b4421958e7a100602c8cd" id="r_ga7af851b5898b4421958e7a100602c8cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7af851b5898b4421958e7a100602c8cd">ADC_SQR1_SQ16_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga175666e476ceceebaa0f3267aeb6ea09">ADC_SQR1_SQ16_Pos</a>)</td></tr>
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<tr class="memitem:ga58db108cdbc75716bedb45ba9fabe727" id="r_ga58db108cdbc75716bedb45ba9fabe727"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58db108cdbc75716bedb45ba9fabe727">ADC_SQR1_L_Pos</a>   (20U)</td></tr>
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<tr class="memitem:gac11490606e7ecc26985deed271f7ff57" id="r_gac11490606e7ecc26985deed271f7ff57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac11490606e7ecc26985deed271f7ff57">ADC_SQR1_L_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58db108cdbc75716bedb45ba9fabe727">ADC_SQR1_L_Pos</a>)</td></tr>
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<tr class="memitem:gae68a19a18d72f6d87c6f2b8cc8bfc6dc" id="r_gae68a19a18d72f6d87c6f2b8cc8bfc6dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae68a19a18d72f6d87c6f2b8cc8bfc6dc">ADC_SQR1_L</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac11490606e7ecc26985deed271f7ff57">ADC_SQR1_L_Msk</a></td></tr>
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<tr class="memitem:ga00ec56fbf232492ec12c954e27d03c6c" id="r_ga00ec56fbf232492ec12c954e27d03c6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00ec56fbf232492ec12c954e27d03c6c">ADC_SQR1_L_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58db108cdbc75716bedb45ba9fabe727">ADC_SQR1_L_Pos</a>)</td></tr>
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<tr class="memitem:ga52708c6570da08c295603e5b52461ecd" id="r_ga52708c6570da08c295603e5b52461ecd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52708c6570da08c295603e5b52461ecd">ADC_SQR1_L_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58db108cdbc75716bedb45ba9fabe727">ADC_SQR1_L_Pos</a>)</td></tr>
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<tr class="memitem:ga8b914eeb128157c4acf6f6b9a4be5558" id="r_ga8b914eeb128157c4acf6f6b9a4be5558"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b914eeb128157c4acf6f6b9a4be5558">ADC_SQR1_L_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58db108cdbc75716bedb45ba9fabe727">ADC_SQR1_L_Pos</a>)</td></tr>
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<tr class="memitem:gaffdd34daa55da53d18055417ae895c47" id="r_gaffdd34daa55da53d18055417ae895c47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffdd34daa55da53d18055417ae895c47">ADC_SQR1_L_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58db108cdbc75716bedb45ba9fabe727">ADC_SQR1_L_Pos</a>)</td></tr>
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<tr class="memitem:ga589d869844063982a6fc59daa2d49aee" id="r_ga589d869844063982a6fc59daa2d49aee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga589d869844063982a6fc59daa2d49aee">ADC_SQR2_SQ7_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gaee89c65015de91a4fc92b922bcef81fe" id="r_gaee89c65015de91a4fc92b922bcef81fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee89c65015de91a4fc92b922bcef81fe">ADC_SQR2_SQ7_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga589d869844063982a6fc59daa2d49aee">ADC_SQR2_SQ7_Pos</a>)</td></tr>
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<tr class="memitem:gaa9f66f702fc124040956117f20ef8df4" id="r_gaa9f66f702fc124040956117f20ef8df4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9f66f702fc124040956117f20ef8df4">ADC_SQR2_SQ7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaee89c65015de91a4fc92b922bcef81fe">ADC_SQR2_SQ7_Msk</a></td></tr>
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<tr class="memitem:ga12bbc822c10582a80f7e20a11038ce96" id="r_ga12bbc822c10582a80f7e20a11038ce96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12bbc822c10582a80f7e20a11038ce96">ADC_SQR2_SQ7_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga589d869844063982a6fc59daa2d49aee">ADC_SQR2_SQ7_Pos</a>)</td></tr>
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<tr class="memitem:ga3d0d7daf3b6db6ff4fa382495f6127c6" id="r_ga3d0d7daf3b6db6ff4fa382495f6127c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d0d7daf3b6db6ff4fa382495f6127c6">ADC_SQR2_SQ7_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga589d869844063982a6fc59daa2d49aee">ADC_SQR2_SQ7_Pos</a>)</td></tr>
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<tr class="memitem:ga74bda24f18a95261661a944cecf45a52" id="r_ga74bda24f18a95261661a944cecf45a52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74bda24f18a95261661a944cecf45a52">ADC_SQR2_SQ7_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga589d869844063982a6fc59daa2d49aee">ADC_SQR2_SQ7_Pos</a>)</td></tr>
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<tr class="memitem:ga2697675d008dda4e6a4905fc0f8d22af" id="r_ga2697675d008dda4e6a4905fc0f8d22af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2697675d008dda4e6a4905fc0f8d22af">ADC_SQR2_SQ7_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga589d869844063982a6fc59daa2d49aee">ADC_SQR2_SQ7_Pos</a>)</td></tr>
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<tr class="memitem:ga2c46dd0f30ef85094ca0cde2e8c00dac" id="r_ga2c46dd0f30ef85094ca0cde2e8c00dac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c46dd0f30ef85094ca0cde2e8c00dac">ADC_SQR2_SQ7_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga589d869844063982a6fc59daa2d49aee">ADC_SQR2_SQ7_Pos</a>)</td></tr>
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<tr class="memitem:gaab83e34058c7c593c58b4fc8f7d27084" id="r_gaab83e34058c7c593c58b4fc8f7d27084"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab83e34058c7c593c58b4fc8f7d27084">ADC_SQR2_SQ8_Pos</a>   (5U)</td></tr>
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<tr class="memitem:ga9152be162b9262d76b7a59b4c0f25956" id="r_ga9152be162b9262d76b7a59b4c0f25956"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9152be162b9262d76b7a59b4c0f25956">ADC_SQR2_SQ8_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab83e34058c7c593c58b4fc8f7d27084">ADC_SQR2_SQ8_Pos</a>)</td></tr>
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<tr class="memitem:ga308ec58a8d20dcb3a348c30c332a0a8e" id="r_ga308ec58a8d20dcb3a348c30c332a0a8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga308ec58a8d20dcb3a348c30c332a0a8e">ADC_SQR2_SQ8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9152be162b9262d76b7a59b4c0f25956">ADC_SQR2_SQ8_Msk</a></td></tr>
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<tr class="memitem:ga858717a28d6c26612ad4ced46863ba13" id="r_ga858717a28d6c26612ad4ced46863ba13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga858717a28d6c26612ad4ced46863ba13">ADC_SQR2_SQ8_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab83e34058c7c593c58b4fc8f7d27084">ADC_SQR2_SQ8_Pos</a>)</td></tr>
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<tr class="memitem:ga2d06168a43b4845409f2fb9193ee474a" id="r_ga2d06168a43b4845409f2fb9193ee474a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d06168a43b4845409f2fb9193ee474a">ADC_SQR2_SQ8_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab83e34058c7c593c58b4fc8f7d27084">ADC_SQR2_SQ8_Pos</a>)</td></tr>
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<tr class="memitem:gaa5eaea65d6719a8199639ec30bb8a07b" id="r_gaa5eaea65d6719a8199639ec30bb8a07b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5eaea65d6719a8199639ec30bb8a07b">ADC_SQR2_SQ8_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab83e34058c7c593c58b4fc8f7d27084">ADC_SQR2_SQ8_Pos</a>)</td></tr>
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<tr class="memitem:ga23e22da18926dd107adc69282a445412" id="r_ga23e22da18926dd107adc69282a445412"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23e22da18926dd107adc69282a445412">ADC_SQR2_SQ8_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab83e34058c7c593c58b4fc8f7d27084">ADC_SQR2_SQ8_Pos</a>)</td></tr>
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<tr class="memitem:gacadd092f31f37bb129065be175673c63" id="r_gacadd092f31f37bb129065be175673c63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacadd092f31f37bb129065be175673c63">ADC_SQR2_SQ8_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab83e34058c7c593c58b4fc8f7d27084">ADC_SQR2_SQ8_Pos</a>)</td></tr>
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<tr class="memitem:ga8585b815abcb076901d4f1a4c8d6c80b" id="r_ga8585b815abcb076901d4f1a4c8d6c80b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8585b815abcb076901d4f1a4c8d6c80b">ADC_SQR2_SQ9_Pos</a>   (10U)</td></tr>
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<tr class="memitem:ga03bc5dff92603b8e5dfe5ac87552f40a" id="r_ga03bc5dff92603b8e5dfe5ac87552f40a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03bc5dff92603b8e5dfe5ac87552f40a">ADC_SQR2_SQ9_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8585b815abcb076901d4f1a4c8d6c80b">ADC_SQR2_SQ9_Pos</a>)</td></tr>
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<tr class="memitem:gaf5d91ecfc3d40cc6b1960544e526eb91" id="r_gaf5d91ecfc3d40cc6b1960544e526eb91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5d91ecfc3d40cc6b1960544e526eb91">ADC_SQR2_SQ9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga03bc5dff92603b8e5dfe5ac87552f40a">ADC_SQR2_SQ9_Msk</a></td></tr>
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<tr class="memitem:gace032949b436d9af8a20ea10a349d55b" id="r_gace032949b436d9af8a20ea10a349d55b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace032949b436d9af8a20ea10a349d55b">ADC_SQR2_SQ9_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8585b815abcb076901d4f1a4c8d6c80b">ADC_SQR2_SQ9_Pos</a>)</td></tr>
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<tr class="memitem:ga5cf43f1c5de0e73d6159fabc3681b891" id="r_ga5cf43f1c5de0e73d6159fabc3681b891"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5cf43f1c5de0e73d6159fabc3681b891">ADC_SQR2_SQ9_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8585b815abcb076901d4f1a4c8d6c80b">ADC_SQR2_SQ9_Pos</a>)</td></tr>
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<tr class="separator:ga5cf43f1c5de0e73d6159fabc3681b891"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3389c07a9de242151ffa434908fee39d" id="r_ga3389c07a9de242151ffa434908fee39d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3389c07a9de242151ffa434908fee39d">ADC_SQR2_SQ9_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8585b815abcb076901d4f1a4c8d6c80b">ADC_SQR2_SQ9_Pos</a>)</td></tr>
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<tr class="memitem:ga13f30540b9f2d33640ea7d9652dc3c71" id="r_ga13f30540b9f2d33640ea7d9652dc3c71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13f30540b9f2d33640ea7d9652dc3c71">ADC_SQR2_SQ9_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8585b815abcb076901d4f1a4c8d6c80b">ADC_SQR2_SQ9_Pos</a>)</td></tr>
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<tr class="separator:ga13f30540b9f2d33640ea7d9652dc3c71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga910e5bda9852d49117b76b0d9f420ef2" id="r_ga910e5bda9852d49117b76b0d9f420ef2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga910e5bda9852d49117b76b0d9f420ef2">ADC_SQR2_SQ9_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8585b815abcb076901d4f1a4c8d6c80b">ADC_SQR2_SQ9_Pos</a>)</td></tr>
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<tr class="separator:ga910e5bda9852d49117b76b0d9f420ef2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48d10816801feffec06a224ee726a97e" id="r_ga48d10816801feffec06a224ee726a97e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48d10816801feffec06a224ee726a97e">ADC_SQR2_SQ10_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga8a438cb8cfa6116018759eca4d2c2fbb" id="r_ga8a438cb8cfa6116018759eca4d2c2fbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a438cb8cfa6116018759eca4d2c2fbb">ADC_SQR2_SQ10_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48d10816801feffec06a224ee726a97e">ADC_SQR2_SQ10_Pos</a>)</td></tr>
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<tr class="memitem:ga22e474b65f217ac21137b1d3f3cbb6bb" id="r_ga22e474b65f217ac21137b1d3f3cbb6bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22e474b65f217ac21137b1d3f3cbb6bb">ADC_SQR2_SQ10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a438cb8cfa6116018759eca4d2c2fbb">ADC_SQR2_SQ10_Msk</a></td></tr>
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<tr class="memitem:gab5a36056dbfce703d22387432ac12262" id="r_gab5a36056dbfce703d22387432ac12262"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5a36056dbfce703d22387432ac12262">ADC_SQR2_SQ10_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48d10816801feffec06a224ee726a97e">ADC_SQR2_SQ10_Pos</a>)</td></tr>
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<tr class="memitem:ga09a1de734fe67156af26edf3b8a61044" id="r_ga09a1de734fe67156af26edf3b8a61044"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09a1de734fe67156af26edf3b8a61044">ADC_SQR2_SQ10_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48d10816801feffec06a224ee726a97e">ADC_SQR2_SQ10_Pos</a>)</td></tr>
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<tr class="memitem:ga3b1d6ad0a40e7171d40a964b361d1eb9" id="r_ga3b1d6ad0a40e7171d40a964b361d1eb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b1d6ad0a40e7171d40a964b361d1eb9">ADC_SQR2_SQ10_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48d10816801feffec06a224ee726a97e">ADC_SQR2_SQ10_Pos</a>)</td></tr>
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<tr class="memitem:ga24d63e60eabad897aa9b19dbe56da71e" id="r_ga24d63e60eabad897aa9b19dbe56da71e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24d63e60eabad897aa9b19dbe56da71e">ADC_SQR2_SQ10_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48d10816801feffec06a224ee726a97e">ADC_SQR2_SQ10_Pos</a>)</td></tr>
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<tr class="memitem:ga7df899f74116e6cb3205af2767840cfb" id="r_ga7df899f74116e6cb3205af2767840cfb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7df899f74116e6cb3205af2767840cfb">ADC_SQR2_SQ10_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48d10816801feffec06a224ee726a97e">ADC_SQR2_SQ10_Pos</a>)</td></tr>
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<tr class="memitem:ga6148bba86967003cb581b42e6eaa29e5" id="r_ga6148bba86967003cb581b42e6eaa29e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6148bba86967003cb581b42e6eaa29e5">ADC_SQR2_SQ11_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga0f72a350259ac99fdcda7a97eb6fe2a8" id="r_ga0f72a350259ac99fdcda7a97eb6fe2a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f72a350259ac99fdcda7a97eb6fe2a8">ADC_SQR2_SQ11_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6148bba86967003cb581b42e6eaa29e5">ADC_SQR2_SQ11_Pos</a>)</td></tr>
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<tr class="memitem:ga7bf491b9c1542fb0d0b83fc96166362e" id="r_ga7bf491b9c1542fb0d0b83fc96166362e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7bf491b9c1542fb0d0b83fc96166362e">ADC_SQR2_SQ11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f72a350259ac99fdcda7a97eb6fe2a8">ADC_SQR2_SQ11_Msk</a></td></tr>
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<tr class="memitem:ga5bc91fec2ef468c5d39d19beda9ecd3e" id="r_ga5bc91fec2ef468c5d39d19beda9ecd3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bc91fec2ef468c5d39d19beda9ecd3e">ADC_SQR2_SQ11_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6148bba86967003cb581b42e6eaa29e5">ADC_SQR2_SQ11_Pos</a>)</td></tr>
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<tr class="memitem:ga3e142789d2bd0584480e923754544ff5" id="r_ga3e142789d2bd0584480e923754544ff5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e142789d2bd0584480e923754544ff5">ADC_SQR2_SQ11_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6148bba86967003cb581b42e6eaa29e5">ADC_SQR2_SQ11_Pos</a>)</td></tr>
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<tr class="memitem:gad6b844fe698c16437e91c9e05a367a4c" id="r_gad6b844fe698c16437e91c9e05a367a4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6b844fe698c16437e91c9e05a367a4c">ADC_SQR2_SQ11_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6148bba86967003cb581b42e6eaa29e5">ADC_SQR2_SQ11_Pos</a>)</td></tr>
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<tr class="memitem:ga1a8127191e3c48f4e0952bdb5e196225" id="r_ga1a8127191e3c48f4e0952bdb5e196225"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a8127191e3c48f4e0952bdb5e196225">ADC_SQR2_SQ11_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6148bba86967003cb581b42e6eaa29e5">ADC_SQR2_SQ11_Pos</a>)</td></tr>
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<tr class="memitem:ga5e8a39f645505ef84cb94bbc8d21b8e0" id="r_ga5e8a39f645505ef84cb94bbc8d21b8e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e8a39f645505ef84cb94bbc8d21b8e0">ADC_SQR2_SQ11_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6148bba86967003cb581b42e6eaa29e5">ADC_SQR2_SQ11_Pos</a>)</td></tr>
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<tr class="memitem:gac2490bed33c8e2523dd8fd0f48cf1ab4" id="r_gac2490bed33c8e2523dd8fd0f48cf1ab4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2490bed33c8e2523dd8fd0f48cf1ab4">ADC_SQR2_SQ12_Pos</a>   (25U)</td></tr>
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<tr class="memitem:ga3a8e8248a0fe8bbf43de3e6f06984a85" id="r_ga3a8e8248a0fe8bbf43de3e6f06984a85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a8e8248a0fe8bbf43de3e6f06984a85">ADC_SQR2_SQ12_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2490bed33c8e2523dd8fd0f48cf1ab4">ADC_SQR2_SQ12_Pos</a>)</td></tr>
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<tr class="memitem:ga8731660b1710e63d5423cd31c11be184" id="r_ga8731660b1710e63d5423cd31c11be184"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8731660b1710e63d5423cd31c11be184">ADC_SQR2_SQ12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a8e8248a0fe8bbf43de3e6f06984a85">ADC_SQR2_SQ12_Msk</a></td></tr>
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<tr class="memitem:ga5b2da909e54f8f6f61bf2bd2cd3e93e0" id="r_ga5b2da909e54f8f6f61bf2bd2cd3e93e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b2da909e54f8f6f61bf2bd2cd3e93e0">ADC_SQR2_SQ12_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2490bed33c8e2523dd8fd0f48cf1ab4">ADC_SQR2_SQ12_Pos</a>)</td></tr>
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<tr class="memitem:gab5930c4a07d594aa23bc868526b42601" id="r_gab5930c4a07d594aa23bc868526b42601"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5930c4a07d594aa23bc868526b42601">ADC_SQR2_SQ12_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2490bed33c8e2523dd8fd0f48cf1ab4">ADC_SQR2_SQ12_Pos</a>)</td></tr>
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<tr class="memitem:ga377805a21e7da2a66a3913a77bcc1e66" id="r_ga377805a21e7da2a66a3913a77bcc1e66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga377805a21e7da2a66a3913a77bcc1e66">ADC_SQR2_SQ12_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2490bed33c8e2523dd8fd0f48cf1ab4">ADC_SQR2_SQ12_Pos</a>)</td></tr>
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<tr class="memitem:ga2e3b45cac9aeb68d33b31a0914692857" id="r_ga2e3b45cac9aeb68d33b31a0914692857"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e3b45cac9aeb68d33b31a0914692857">ADC_SQR2_SQ12_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2490bed33c8e2523dd8fd0f48cf1ab4">ADC_SQR2_SQ12_Pos</a>)</td></tr>
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<tr class="memitem:ga6043d31a6cb9bd7c1542c3d41eb296c7" id="r_ga6043d31a6cb9bd7c1542c3d41eb296c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6043d31a6cb9bd7c1542c3d41eb296c7">ADC_SQR2_SQ12_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2490bed33c8e2523dd8fd0f48cf1ab4">ADC_SQR2_SQ12_Pos</a>)</td></tr>
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<tr class="memitem:gac825474ea3bcec005557a9fe47526a4f" id="r_gac825474ea3bcec005557a9fe47526a4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac825474ea3bcec005557a9fe47526a4f">ADC_SQR3_SQ1_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga158e02c01bc2ee902ff9d4ca8c767184" id="r_ga158e02c01bc2ee902ff9d4ca8c767184"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga158e02c01bc2ee902ff9d4ca8c767184">ADC_SQR3_SQ1_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac825474ea3bcec005557a9fe47526a4f">ADC_SQR3_SQ1_Pos</a>)</td></tr>
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<tr class="memitem:ga52491114e8394648559004f3bae718d9" id="r_ga52491114e8394648559004f3bae718d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52491114e8394648559004f3bae718d9">ADC_SQR3_SQ1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga158e02c01bc2ee902ff9d4ca8c767184">ADC_SQR3_SQ1_Msk</a></td></tr>
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<tr class="memitem:ga53d3bb1c8bb48c7bcb0f7409db69f7b4" id="r_ga53d3bb1c8bb48c7bcb0f7409db69f7b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53d3bb1c8bb48c7bcb0f7409db69f7b4">ADC_SQR3_SQ1_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac825474ea3bcec005557a9fe47526a4f">ADC_SQR3_SQ1_Pos</a>)</td></tr>
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<tr class="memitem:gaddb9af3a3b23a103fbc34c4f422fd2af" id="r_gaddb9af3a3b23a103fbc34c4f422fd2af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddb9af3a3b23a103fbc34c4f422fd2af">ADC_SQR3_SQ1_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac825474ea3bcec005557a9fe47526a4f">ADC_SQR3_SQ1_Pos</a>)</td></tr>
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<tr class="memitem:gadf591f43a15c0c2c5afae2598b8f2afc" id="r_gadf591f43a15c0c2c5afae2598b8f2afc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf591f43a15c0c2c5afae2598b8f2afc">ADC_SQR3_SQ1_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac825474ea3bcec005557a9fe47526a4f">ADC_SQR3_SQ1_Pos</a>)</td></tr>
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<tr class="memitem:ga05cfde0ef0e6a8dd6311f5cd7a806556" id="r_ga05cfde0ef0e6a8dd6311f5cd7a806556"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05cfde0ef0e6a8dd6311f5cd7a806556">ADC_SQR3_SQ1_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac825474ea3bcec005557a9fe47526a4f">ADC_SQR3_SQ1_Pos</a>)</td></tr>
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<tr class="memitem:ga9981512f99a6c41ce107a9428d9cfdd0" id="r_ga9981512f99a6c41ce107a9428d9cfdd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9981512f99a6c41ce107a9428d9cfdd0">ADC_SQR3_SQ1_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac825474ea3bcec005557a9fe47526a4f">ADC_SQR3_SQ1_Pos</a>)</td></tr>
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<tr class="memitem:ga92d0269f674151ea3e8e38760675099c" id="r_ga92d0269f674151ea3e8e38760675099c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92d0269f674151ea3e8e38760675099c">ADC_SQR3_SQ2_Pos</a>   (5U)</td></tr>
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<tr class="memitem:ga1e5a7d30b953796355d6e134aefa7fc3" id="r_ga1e5a7d30b953796355d6e134aefa7fc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5a7d30b953796355d6e134aefa7fc3">ADC_SQR3_SQ2_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92d0269f674151ea3e8e38760675099c">ADC_SQR3_SQ2_Pos</a>)</td></tr>
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<tr class="memitem:ga60637fb25c099f8da72a8a36211f7a8c" id="r_ga60637fb25c099f8da72a8a36211f7a8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60637fb25c099f8da72a8a36211f7a8c">ADC_SQR3_SQ2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5a7d30b953796355d6e134aefa7fc3">ADC_SQR3_SQ2_Msk</a></td></tr>
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<tr class="memitem:gaede0302eb64f023913c7a9e588d77937" id="r_gaede0302eb64f023913c7a9e588d77937"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaede0302eb64f023913c7a9e588d77937">ADC_SQR3_SQ2_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92d0269f674151ea3e8e38760675099c">ADC_SQR3_SQ2_Pos</a>)</td></tr>
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<tr class="memitem:ga158ab7429a864634a46c81fdb51d7508" id="r_ga158ab7429a864634a46c81fdb51d7508"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga158ab7429a864634a46c81fdb51d7508">ADC_SQR3_SQ2_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92d0269f674151ea3e8e38760675099c">ADC_SQR3_SQ2_Pos</a>)</td></tr>
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<tr class="memitem:gae729e21d590271c59c0d653300d5581c" id="r_gae729e21d590271c59c0d653300d5581c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae729e21d590271c59c0d653300d5581c">ADC_SQR3_SQ2_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92d0269f674151ea3e8e38760675099c">ADC_SQR3_SQ2_Pos</a>)</td></tr>
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<tr class="memitem:gaf65c33275178a8777fa8fed8a01f7389" id="r_gaf65c33275178a8777fa8fed8a01f7389"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf65c33275178a8777fa8fed8a01f7389">ADC_SQR3_SQ2_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92d0269f674151ea3e8e38760675099c">ADC_SQR3_SQ2_Pos</a>)</td></tr>
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<tr class="memitem:ga990aeb689b7cc8f0bebb3dd6af7b27a6" id="r_ga990aeb689b7cc8f0bebb3dd6af7b27a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga990aeb689b7cc8f0bebb3dd6af7b27a6">ADC_SQR3_SQ2_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92d0269f674151ea3e8e38760675099c">ADC_SQR3_SQ2_Pos</a>)</td></tr>
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<tr class="memitem:ga70ca80250d365fa475d9afed6d03ca8b" id="r_ga70ca80250d365fa475d9afed6d03ca8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70ca80250d365fa475d9afed6d03ca8b">ADC_SQR3_SQ3_Pos</a>   (10U)</td></tr>
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<tr class="memitem:gaea87ead7a01cad5a05b3212eb1b5ce35" id="r_gaea87ead7a01cad5a05b3212eb1b5ce35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea87ead7a01cad5a05b3212eb1b5ce35">ADC_SQR3_SQ3_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70ca80250d365fa475d9afed6d03ca8b">ADC_SQR3_SQ3_Pos</a>)</td></tr>
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<tr class="memitem:ga601f21b7c1e571fb8c5ff310aca021e1" id="r_ga601f21b7c1e571fb8c5ff310aca021e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga601f21b7c1e571fb8c5ff310aca021e1">ADC_SQR3_SQ3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaea87ead7a01cad5a05b3212eb1b5ce35">ADC_SQR3_SQ3_Msk</a></td></tr>
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<tr class="memitem:ga7fd2c154b5852cb08ce60b4adfa36313" id="r_ga7fd2c154b5852cb08ce60b4adfa36313"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fd2c154b5852cb08ce60b4adfa36313">ADC_SQR3_SQ3_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70ca80250d365fa475d9afed6d03ca8b">ADC_SQR3_SQ3_Pos</a>)</td></tr>
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<tr class="memitem:ga214580377dd3a424ad819f14f6b025d4" id="r_ga214580377dd3a424ad819f14f6b025d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga214580377dd3a424ad819f14f6b025d4">ADC_SQR3_SQ3_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70ca80250d365fa475d9afed6d03ca8b">ADC_SQR3_SQ3_Pos</a>)</td></tr>
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<tr class="memitem:gabae2353b109c9cda2a176ea1f44db4fe" id="r_gabae2353b109c9cda2a176ea1f44db4fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabae2353b109c9cda2a176ea1f44db4fe">ADC_SQR3_SQ3_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70ca80250d365fa475d9afed6d03ca8b">ADC_SQR3_SQ3_Pos</a>)</td></tr>
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<tr class="memitem:ga7d2f00d3372bd1d64bf4eb2271277ab0" id="r_ga7d2f00d3372bd1d64bf4eb2271277ab0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d2f00d3372bd1d64bf4eb2271277ab0">ADC_SQR3_SQ3_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70ca80250d365fa475d9afed6d03ca8b">ADC_SQR3_SQ3_Pos</a>)</td></tr>
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<tr class="memitem:ga5279e505b1a59b223f30e5be139d5042" id="r_ga5279e505b1a59b223f30e5be139d5042"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5279e505b1a59b223f30e5be139d5042">ADC_SQR3_SQ3_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70ca80250d365fa475d9afed6d03ca8b">ADC_SQR3_SQ3_Pos</a>)</td></tr>
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<tr class="memitem:ga01430f2ace37e28c2c79a923632d094a" id="r_ga01430f2ace37e28c2c79a923632d094a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01430f2ace37e28c2c79a923632d094a">ADC_SQR3_SQ4_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga2f6ee00d27c507e9b088b1f6b825ab55" id="r_ga2f6ee00d27c507e9b088b1f6b825ab55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f6ee00d27c507e9b088b1f6b825ab55">ADC_SQR3_SQ4_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01430f2ace37e28c2c79a923632d094a">ADC_SQR3_SQ4_Pos</a>)</td></tr>
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<tr class="memitem:ga3fc43f70bb3c67c639678b91d852390b" id="r_ga3fc43f70bb3c67c639678b91d852390b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3fc43f70bb3c67c639678b91d852390b">ADC_SQR3_SQ4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f6ee00d27c507e9b088b1f6b825ab55">ADC_SQR3_SQ4_Msk</a></td></tr>
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<tr class="memitem:gab2a501b20cf758a7353efcb3f95a3a93" id="r_gab2a501b20cf758a7353efcb3f95a3a93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2a501b20cf758a7353efcb3f95a3a93">ADC_SQR3_SQ4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01430f2ace37e28c2c79a923632d094a">ADC_SQR3_SQ4_Pos</a>)</td></tr>
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<tr class="memitem:gaffafa27fd561e4c7d419e3f665d80f2c" id="r_gaffafa27fd561e4c7d419e3f665d80f2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffafa27fd561e4c7d419e3f665d80f2c">ADC_SQR3_SQ4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01430f2ace37e28c2c79a923632d094a">ADC_SQR3_SQ4_Pos</a>)</td></tr>
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<tr class="memitem:gad0251fa70e400ee74f442d8fba2b1afb" id="r_gad0251fa70e400ee74f442d8fba2b1afb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0251fa70e400ee74f442d8fba2b1afb">ADC_SQR3_SQ4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01430f2ace37e28c2c79a923632d094a">ADC_SQR3_SQ4_Pos</a>)</td></tr>
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<tr class="memitem:ga3dc48c3c6b304517261486d8a63637ae" id="r_ga3dc48c3c6b304517261486d8a63637ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3dc48c3c6b304517261486d8a63637ae">ADC_SQR3_SQ4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01430f2ace37e28c2c79a923632d094a">ADC_SQR3_SQ4_Pos</a>)</td></tr>
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<tr class="memitem:gafe23b9e640df96ca84eab4b6b4f44083" id="r_gafe23b9e640df96ca84eab4b6b4f44083"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe23b9e640df96ca84eab4b6b4f44083">ADC_SQR3_SQ4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01430f2ace37e28c2c79a923632d094a">ADC_SQR3_SQ4_Pos</a>)</td></tr>
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<tr class="memitem:ga834a04bad696f9b1a363e828441e5d6a" id="r_ga834a04bad696f9b1a363e828441e5d6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga834a04bad696f9b1a363e828441e5d6a">ADC_SQR3_SQ5_Pos</a>   (20U)</td></tr>
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<tr class="memitem:gaade1e4985264c9bc583a6803cc54e7cf" id="r_gaade1e4985264c9bc583a6803cc54e7cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaade1e4985264c9bc583a6803cc54e7cf">ADC_SQR3_SQ5_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga834a04bad696f9b1a363e828441e5d6a">ADC_SQR3_SQ5_Pos</a>)</td></tr>
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<tr class="memitem:gaae841d68049442e4568b86322ed4be6f" id="r_gaae841d68049442e4568b86322ed4be6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae841d68049442e4568b86322ed4be6f">ADC_SQR3_SQ5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaade1e4985264c9bc583a6803cc54e7cf">ADC_SQR3_SQ5_Msk</a></td></tr>
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<tr class="memitem:gaa1de9fc24755b715c700c6442f4a396b" id="r_gaa1de9fc24755b715c700c6442f4a396b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1de9fc24755b715c700c6442f4a396b">ADC_SQR3_SQ5_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga834a04bad696f9b1a363e828441e5d6a">ADC_SQR3_SQ5_Pos</a>)</td></tr>
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<tr class="memitem:ga3f704feb58eecb39bc7f199577064172" id="r_ga3f704feb58eecb39bc7f199577064172"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f704feb58eecb39bc7f199577064172">ADC_SQR3_SQ5_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga834a04bad696f9b1a363e828441e5d6a">ADC_SQR3_SQ5_Pos</a>)</td></tr>
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<tr class="memitem:ga88a7994f637a75d105cc5975b154c373" id="r_ga88a7994f637a75d105cc5975b154c373"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88a7994f637a75d105cc5975b154c373">ADC_SQR3_SQ5_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga834a04bad696f9b1a363e828441e5d6a">ADC_SQR3_SQ5_Pos</a>)</td></tr>
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<tr class="memitem:ga31c6fce8f01e75c68124124061f67f0e" id="r_ga31c6fce8f01e75c68124124061f67f0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31c6fce8f01e75c68124124061f67f0e">ADC_SQR3_SQ5_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga834a04bad696f9b1a363e828441e5d6a">ADC_SQR3_SQ5_Pos</a>)</td></tr>
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<tr class="memitem:ga6b0cad694c068ea8874b6504bd6ae885" id="r_ga6b0cad694c068ea8874b6504bd6ae885"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b0cad694c068ea8874b6504bd6ae885">ADC_SQR3_SQ5_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga834a04bad696f9b1a363e828441e5d6a">ADC_SQR3_SQ5_Pos</a>)</td></tr>
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<tr class="memitem:ga972ec9142a3fdc4969c91b9743372a9c" id="r_ga972ec9142a3fdc4969c91b9743372a9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga972ec9142a3fdc4969c91b9743372a9c">ADC_SQR3_SQ6_Pos</a>   (25U)</td></tr>
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<tr class="memitem:gab01b48333516c485500fcf186f861bf3" id="r_gab01b48333516c485500fcf186f861bf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab01b48333516c485500fcf186f861bf3">ADC_SQR3_SQ6_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga972ec9142a3fdc4969c91b9743372a9c">ADC_SQR3_SQ6_Pos</a>)</td></tr>
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<tr class="memitem:ga723792274b16b342d16d6a02fce74ba6" id="r_ga723792274b16b342d16d6a02fce74ba6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga723792274b16b342d16d6a02fce74ba6">ADC_SQR3_SQ6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab01b48333516c485500fcf186f861bf3">ADC_SQR3_SQ6_Msk</a></td></tr>
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<tr class="memitem:ga91b8b5293abd0601c543c13a0b53b335" id="r_ga91b8b5293abd0601c543c13a0b53b335"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91b8b5293abd0601c543c13a0b53b335">ADC_SQR3_SQ6_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga972ec9142a3fdc4969c91b9743372a9c">ADC_SQR3_SQ6_Pos</a>)</td></tr>
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<tr class="memitem:gab29847362a613b43eeeda6db758d781e" id="r_gab29847362a613b43eeeda6db758d781e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab29847362a613b43eeeda6db758d781e">ADC_SQR3_SQ6_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga972ec9142a3fdc4969c91b9743372a9c">ADC_SQR3_SQ6_Pos</a>)</td></tr>
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<tr class="memitem:gaa92c8ea1bfb42ed80622770ae2dc41ab" id="r_gaa92c8ea1bfb42ed80622770ae2dc41ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa92c8ea1bfb42ed80622770ae2dc41ab">ADC_SQR3_SQ6_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga972ec9142a3fdc4969c91b9743372a9c">ADC_SQR3_SQ6_Pos</a>)</td></tr>
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<tr class="memitem:gaed2d7edb11fb84b02c175acff305a922" id="r_gaed2d7edb11fb84b02c175acff305a922"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed2d7edb11fb84b02c175acff305a922">ADC_SQR3_SQ6_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga972ec9142a3fdc4969c91b9743372a9c">ADC_SQR3_SQ6_Pos</a>)</td></tr>
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<tr class="memitem:ga78f9e51811549a6797ecfe1468def4ff" id="r_ga78f9e51811549a6797ecfe1468def4ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78f9e51811549a6797ecfe1468def4ff">ADC_SQR3_SQ6_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga972ec9142a3fdc4969c91b9743372a9c">ADC_SQR3_SQ6_Pos</a>)</td></tr>
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<tr class="memitem:gab9c01f684cb7d1dc5db5d91d29706d1e" id="r_gab9c01f684cb7d1dc5db5d91d29706d1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9c01f684cb7d1dc5db5d91d29706d1e">ADC_JSQR_JSQ1_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab9c01f684cb7d1dc5db5d91d29706d1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d51f520a176b598792f5019ef4e1f7e" id="r_ga3d51f520a176b598792f5019ef4e1f7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d51f520a176b598792f5019ef4e1f7e">ADC_JSQR_JSQ1_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9c01f684cb7d1dc5db5d91d29706d1e">ADC_JSQR_JSQ1_Pos</a>)</td></tr>
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<tr class="separator:ga3d51f520a176b598792f5019ef4e1f7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7fa15dfe51b084b36cb5df2fbf44bb2" id="r_gad7fa15dfe51b084b36cb5df2fbf44bb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7fa15dfe51b084b36cb5df2fbf44bb2">ADC_JSQR_JSQ1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d51f520a176b598792f5019ef4e1f7e">ADC_JSQR_JSQ1_Msk</a></td></tr>
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<tr class="separator:gad7fa15dfe51b084b36cb5df2fbf44bb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3ea38b080462c4571524b5fcbfed292" id="r_gaf3ea38b080462c4571524b5fcbfed292"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3ea38b080462c4571524b5fcbfed292">ADC_JSQR_JSQ1_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9c01f684cb7d1dc5db5d91d29706d1e">ADC_JSQR_JSQ1_Pos</a>)</td></tr>
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<tr class="separator:gaf3ea38b080462c4571524b5fcbfed292"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabae36d7655fb1dce11e60ffa8e57b509" id="r_gabae36d7655fb1dce11e60ffa8e57b509"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabae36d7655fb1dce11e60ffa8e57b509">ADC_JSQR_JSQ1_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9c01f684cb7d1dc5db5d91d29706d1e">ADC_JSQR_JSQ1_Pos</a>)</td></tr>
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<tr class="separator:gabae36d7655fb1dce11e60ffa8e57b509"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3e7a96d33f640444b40b70e9ee28671" id="r_gad3e7a96d33f640444b40b70e9ee28671"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3e7a96d33f640444b40b70e9ee28671">ADC_JSQR_JSQ1_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9c01f684cb7d1dc5db5d91d29706d1e">ADC_JSQR_JSQ1_Pos</a>)</td></tr>
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<tr class="separator:gad3e7a96d33f640444b40b70e9ee28671"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6066a6aef47f317a5df0c9bbf59121fb" id="r_ga6066a6aef47f317a5df0c9bbf59121fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6066a6aef47f317a5df0c9bbf59121fb">ADC_JSQR_JSQ1_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9c01f684cb7d1dc5db5d91d29706d1e">ADC_JSQR_JSQ1_Pos</a>)</td></tr>
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<tr class="separator:ga6066a6aef47f317a5df0c9bbf59121fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2c4baf98380a477cebb01be3e8f0594" id="r_gaf2c4baf98380a477cebb01be3e8f0594"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2c4baf98380a477cebb01be3e8f0594">ADC_JSQR_JSQ1_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9c01f684cb7d1dc5db5d91d29706d1e">ADC_JSQR_JSQ1_Pos</a>)</td></tr>
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<tr class="separator:gaf2c4baf98380a477cebb01be3e8f0594"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga086dad3b0d75e5a34736717f639f54bc" id="r_ga086dad3b0d75e5a34736717f639f54bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga086dad3b0d75e5a34736717f639f54bc">ADC_JSQR_JSQ2_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga086dad3b0d75e5a34736717f639f54bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1fb22b426f041225a2383fbb9a014c74" id="r_ga1fb22b426f041225a2383fbb9a014c74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fb22b426f041225a2383fbb9a014c74">ADC_JSQR_JSQ2_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga086dad3b0d75e5a34736717f639f54bc">ADC_JSQR_JSQ2_Pos</a>)</td></tr>
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<tr class="separator:ga1fb22b426f041225a2383fbb9a014c74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e8446a5857e5379cff8cadf822e15d4" id="r_ga3e8446a5857e5379cff8cadf822e15d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e8446a5857e5379cff8cadf822e15d4">ADC_JSQR_JSQ2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fb22b426f041225a2383fbb9a014c74">ADC_JSQR_JSQ2_Msk</a></td></tr>
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<tr class="separator:ga3e8446a5857e5379cff8cadf822e15d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabf0889d056b56e4a113142b3694166d" id="r_gaabf0889d056b56e4a113142b3694166d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabf0889d056b56e4a113142b3694166d">ADC_JSQR_JSQ2_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga086dad3b0d75e5a34736717f639f54bc">ADC_JSQR_JSQ2_Pos</a>)</td></tr>
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<tr class="memitem:ga048f97e9e332adb21eca27b647af1378" id="r_ga048f97e9e332adb21eca27b647af1378"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga048f97e9e332adb21eca27b647af1378">ADC_JSQR_JSQ2_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga086dad3b0d75e5a34736717f639f54bc">ADC_JSQR_JSQ2_Pos</a>)</td></tr>
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<tr class="separator:ga048f97e9e332adb21eca27b647af1378"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18bee187ed94e73b16eeea7501394581" id="r_ga18bee187ed94e73b16eeea7501394581"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18bee187ed94e73b16eeea7501394581">ADC_JSQR_JSQ2_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga086dad3b0d75e5a34736717f639f54bc">ADC_JSQR_JSQ2_Pos</a>)</td></tr>
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<tr class="memitem:ga78b031d11b56e49b2c28c1a79136b48a" id="r_ga78b031d11b56e49b2c28c1a79136b48a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78b031d11b56e49b2c28c1a79136b48a">ADC_JSQR_JSQ2_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga086dad3b0d75e5a34736717f639f54bc">ADC_JSQR_JSQ2_Pos</a>)</td></tr>
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<tr class="separator:ga78b031d11b56e49b2c28c1a79136b48a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga064d6ccde30a22430c658b8efc431e59" id="r_ga064d6ccde30a22430c658b8efc431e59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga064d6ccde30a22430c658b8efc431e59">ADC_JSQR_JSQ2_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga086dad3b0d75e5a34736717f639f54bc">ADC_JSQR_JSQ2_Pos</a>)</td></tr>
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<tr class="separator:ga064d6ccde30a22430c658b8efc431e59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9af86c6e6cd2d134f389580a03449e9e" id="r_ga9af86c6e6cd2d134f389580a03449e9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9af86c6e6cd2d134f389580a03449e9e">ADC_JSQR_JSQ3_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga9af86c6e6cd2d134f389580a03449e9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b87c9c110f68556c6d266cd9808165b" id="r_ga4b87c9c110f68556c6d266cd9808165b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b87c9c110f68556c6d266cd9808165b">ADC_JSQR_JSQ3_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9af86c6e6cd2d134f389580a03449e9e">ADC_JSQR_JSQ3_Pos</a>)</td></tr>
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<tr class="separator:ga4b87c9c110f68556c6d266cd9808165b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2fbdc1b854a54c4288402c2d3a7fca9" id="r_gae2fbdc1b854a54c4288402c2d3a7fca9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2fbdc1b854a54c4288402c2d3a7fca9">ADC_JSQR_JSQ3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b87c9c110f68556c6d266cd9808165b">ADC_JSQR_JSQ3_Msk</a></td></tr>
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<tr class="separator:gae2fbdc1b854a54c4288402c2d3a7fca9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12fbc27c3543f23125f632dfa60fdc98" id="r_ga12fbc27c3543f23125f632dfa60fdc98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12fbc27c3543f23125f632dfa60fdc98">ADC_JSQR_JSQ3_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9af86c6e6cd2d134f389580a03449e9e">ADC_JSQR_JSQ3_Pos</a>)</td></tr>
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<tr class="separator:ga12fbc27c3543f23125f632dfa60fdc98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga169ec7d371e3ee897b73c3ad84b6ed32" id="r_ga169ec7d371e3ee897b73c3ad84b6ed32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga169ec7d371e3ee897b73c3ad84b6ed32">ADC_JSQR_JSQ3_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9af86c6e6cd2d134f389580a03449e9e">ADC_JSQR_JSQ3_Pos</a>)</td></tr>
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<tr class="separator:ga169ec7d371e3ee897b73c3ad84b6ed32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga693542d5a536304f364476589ba0bec9" id="r_ga693542d5a536304f364476589ba0bec9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga693542d5a536304f364476589ba0bec9">ADC_JSQR_JSQ3_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9af86c6e6cd2d134f389580a03449e9e">ADC_JSQR_JSQ3_Pos</a>)</td></tr>
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<tr class="memitem:ga139ddd01c0faf219dca844477453149e" id="r_ga139ddd01c0faf219dca844477453149e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga139ddd01c0faf219dca844477453149e">ADC_JSQR_JSQ3_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9af86c6e6cd2d134f389580a03449e9e">ADC_JSQR_JSQ3_Pos</a>)</td></tr>
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<tr class="memitem:gac1452b8cf4acc90fb522d90751043aac" id="r_gac1452b8cf4acc90fb522d90751043aac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1452b8cf4acc90fb522d90751043aac">ADC_JSQR_JSQ3_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9af86c6e6cd2d134f389580a03449e9e">ADC_JSQR_JSQ3_Pos</a>)</td></tr>
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<tr class="memitem:ga24746201bf3845f70dc4e442d61d470a" id="r_ga24746201bf3845f70dc4e442d61d470a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24746201bf3845f70dc4e442d61d470a">ADC_JSQR_JSQ4_Pos</a>   (15U)</td></tr>
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<tr class="memitem:gaa3c43ea620dd89338b58bf89feab30fd" id="r_gaa3c43ea620dd89338b58bf89feab30fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3c43ea620dd89338b58bf89feab30fd">ADC_JSQR_JSQ4_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24746201bf3845f70dc4e442d61d470a">ADC_JSQR_JSQ4_Pos</a>)</td></tr>
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<tr class="memitem:ga39a279051ef198ee34cad73743b996f4" id="r_ga39a279051ef198ee34cad73743b996f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39a279051ef198ee34cad73743b996f4">ADC_JSQR_JSQ4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3c43ea620dd89338b58bf89feab30fd">ADC_JSQR_JSQ4_Msk</a></td></tr>
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<tr class="separator:ga39a279051ef198ee34cad73743b996f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13e250d329673c02f7a0d24d25e83649" id="r_ga13e250d329673c02f7a0d24d25e83649"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13e250d329673c02f7a0d24d25e83649">ADC_JSQR_JSQ4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24746201bf3845f70dc4e442d61d470a">ADC_JSQR_JSQ4_Pos</a>)</td></tr>
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<tr class="separator:ga13e250d329673c02f7a0d24d25e83649"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30dad81d708c35136e2da4e96cfe07b7" id="r_ga30dad81d708c35136e2da4e96cfe07b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30dad81d708c35136e2da4e96cfe07b7">ADC_JSQR_JSQ4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24746201bf3845f70dc4e442d61d470a">ADC_JSQR_JSQ4_Pos</a>)</td></tr>
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<tr class="separator:ga30dad81d708c35136e2da4e96cfe07b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ceab97acb95b31cb7448c9da38fc11a" id="r_ga6ceab97acb95b31cb7448c9da38fc11a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ceab97acb95b31cb7448c9da38fc11a">ADC_JSQR_JSQ4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24746201bf3845f70dc4e442d61d470a">ADC_JSQR_JSQ4_Pos</a>)</td></tr>
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<tr class="separator:ga6ceab97acb95b31cb7448c9da38fc11a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52f6571e7efed6a0f72df19c66d3c917" id="r_ga52f6571e7efed6a0f72df19c66d3c917"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52f6571e7efed6a0f72df19c66d3c917">ADC_JSQR_JSQ4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24746201bf3845f70dc4e442d61d470a">ADC_JSQR_JSQ4_Pos</a>)</td></tr>
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<tr class="separator:ga52f6571e7efed6a0f72df19c66d3c917"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaede3a17ef541039943d9dcd85df223ca" id="r_gaede3a17ef541039943d9dcd85df223ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaede3a17ef541039943d9dcd85df223ca">ADC_JSQR_JSQ4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24746201bf3845f70dc4e442d61d470a">ADC_JSQR_JSQ4_Pos</a>)</td></tr>
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<tr class="memitem:gab1dd38cefe9e4ca58d8535c9b2386cb1" id="r_gab1dd38cefe9e4ca58d8535c9b2386cb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1dd38cefe9e4ca58d8535c9b2386cb1">ADC_JSQR_JL_Pos</a>   (20U)</td></tr>
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<tr class="separator:gab1dd38cefe9e4ca58d8535c9b2386cb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11fbbdaa929d9ecf3054aaaed0285b05" id="r_ga11fbbdaa929d9ecf3054aaaed0285b05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11fbbdaa929d9ecf3054aaaed0285b05">ADC_JSQR_JL_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab1dd38cefe9e4ca58d8535c9b2386cb1">ADC_JSQR_JL_Pos</a>)</td></tr>
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<tr class="separator:ga11fbbdaa929d9ecf3054aaaed0285b05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa624d1fe34014b88873e2dfa91f79232" id="r_gaa624d1fe34014b88873e2dfa91f79232"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa624d1fe34014b88873e2dfa91f79232">ADC_JSQR_JL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga11fbbdaa929d9ecf3054aaaed0285b05">ADC_JSQR_JL_Msk</a></td></tr>
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<tr class="separator:gaa624d1fe34014b88873e2dfa91f79232"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga117a6719241f20dbd765bc34f9ffcd58" id="r_ga117a6719241f20dbd765bc34f9ffcd58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga117a6719241f20dbd765bc34f9ffcd58">ADC_JSQR_JL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab1dd38cefe9e4ca58d8535c9b2386cb1">ADC_JSQR_JL_Pos</a>)</td></tr>
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<tr class="memitem:ga1f82ef3b6e6350b9e52e622daeaa3e6e" id="r_ga1f82ef3b6e6350b9e52e622daeaa3e6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f82ef3b6e6350b9e52e622daeaa3e6e">ADC_JSQR_JL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab1dd38cefe9e4ca58d8535c9b2386cb1">ADC_JSQR_JL_Pos</a>)</td></tr>
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<tr class="separator:ga1f82ef3b6e6350b9e52e622daeaa3e6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb0c0f7960a790d485b1ae99aed0e8c7" id="r_gadb0c0f7960a790d485b1ae99aed0e8c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb0c0f7960a790d485b1ae99aed0e8c7">ADC_JDR1_JDATA_Pos</a>   (0U)</td></tr>
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<tr class="separator:gadb0c0f7960a790d485b1ae99aed0e8c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6440d03419f23870bf5bf1a38a57c79d" id="r_ga6440d03419f23870bf5bf1a38a57c79d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6440d03419f23870bf5bf1a38a57c79d">ADC_JDR1_JDATA_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb0c0f7960a790d485b1ae99aed0e8c7">ADC_JDR1_JDATA_Pos</a>)</td></tr>
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<tr class="separator:ga6440d03419f23870bf5bf1a38a57c79d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad02fcd8fd97b2f7d70a5a04fed60b558" id="r_gad02fcd8fd97b2f7d70a5a04fed60b558"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad02fcd8fd97b2f7d70a5a04fed60b558">ADC_JDR1_JDATA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6440d03419f23870bf5bf1a38a57c79d">ADC_JDR1_JDATA_Msk</a></td></tr>
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<tr class="separator:gad02fcd8fd97b2f7d70a5a04fed60b558"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e02f5dbe30f9da55c112634b5636b3d" id="r_ga2e02f5dbe30f9da55c112634b5636b3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e02f5dbe30f9da55c112634b5636b3d">ADC_JDR2_JDATA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2e02f5dbe30f9da55c112634b5636b3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0ff8b95da1c11baf16aa35dd8672670" id="r_gad0ff8b95da1c11baf16aa35dd8672670"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0ff8b95da1c11baf16aa35dd8672670">ADC_JDR2_JDATA_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e02f5dbe30f9da55c112634b5636b3d">ADC_JDR2_JDATA_Pos</a>)</td></tr>
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<tr class="separator:gad0ff8b95da1c11baf16aa35dd8672670"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fbd8801b9c60269ca477062985a08e8" id="r_ga9fbd8801b9c60269ca477062985a08e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fbd8801b9c60269ca477062985a08e8">ADC_JDR2_JDATA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad0ff8b95da1c11baf16aa35dd8672670">ADC_JDR2_JDATA_Msk</a></td></tr>
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<tr class="separator:ga9fbd8801b9c60269ca477062985a08e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga382b9639cc85f4dc0c4603b83e4e3246" id="r_ga382b9639cc85f4dc0c4603b83e4e3246"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga382b9639cc85f4dc0c4603b83e4e3246">ADC_JDR3_JDATA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga382b9639cc85f4dc0c4603b83e4e3246"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee0994ddf4fa21f7e6cedc0c3d599683" id="r_gaee0994ddf4fa21f7e6cedc0c3d599683"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee0994ddf4fa21f7e6cedc0c3d599683">ADC_JDR3_JDATA_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga382b9639cc85f4dc0c4603b83e4e3246">ADC_JDR3_JDATA_Pos</a>)</td></tr>
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<tr class="separator:gaee0994ddf4fa21f7e6cedc0c3d599683"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae84e9e5928bb9ed1aef6c83089fb5ef" id="r_gaae84e9e5928bb9ed1aef6c83089fb5ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae84e9e5928bb9ed1aef6c83089fb5ef">ADC_JDR3_JDATA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaee0994ddf4fa21f7e6cedc0c3d599683">ADC_JDR3_JDATA_Msk</a></td></tr>
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<tr class="separator:gaae84e9e5928bb9ed1aef6c83089fb5ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa993f3df2df14e7be95b96543bd4873f" id="r_gaa993f3df2df14e7be95b96543bd4873f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa993f3df2df14e7be95b96543bd4873f">ADC_JDR4_JDATA_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa993f3df2df14e7be95b96543bd4873f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad42adbc5ae1c70cdc1926642fcc2baef" id="r_gad42adbc5ae1c70cdc1926642fcc2baef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad42adbc5ae1c70cdc1926642fcc2baef">ADC_JDR4_JDATA_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa993f3df2df14e7be95b96543bd4873f">ADC_JDR4_JDATA_Pos</a>)</td></tr>
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<tr class="separator:gad42adbc5ae1c70cdc1926642fcc2baef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48d8fafdad1fb1bb0f761fd833e7b0c1" id="r_ga48d8fafdad1fb1bb0f761fd833e7b0c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48d8fafdad1fb1bb0f761fd833e7b0c1">ADC_JDR4_JDATA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad42adbc5ae1c70cdc1926642fcc2baef">ADC_JDR4_JDATA_Msk</a></td></tr>
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<tr class="separator:ga48d8fafdad1fb1bb0f761fd833e7b0c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84a231db4b53876ee3823b0ea3c92a06" id="r_ga84a231db4b53876ee3823b0ea3c92a06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84a231db4b53876ee3823b0ea3c92a06">ADC_DR_DATA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga84a231db4b53876ee3823b0ea3c92a06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85ec9cca38cafd77f3d56fdf80f84eb7" id="r_ga85ec9cca38cafd77f3d56fdf80f84eb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85ec9cca38cafd77f3d56fdf80f84eb7">ADC_DR_DATA_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84a231db4b53876ee3823b0ea3c92a06">ADC_DR_DATA_Pos</a>)</td></tr>
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<tr class="memitem:gada596183c4087696c486546e88176038" id="r_gada596183c4087696c486546e88176038"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada596183c4087696c486546e88176038">ADC_DR_DATA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga85ec9cca38cafd77f3d56fdf80f84eb7">ADC_DR_DATA_Msk</a></td></tr>
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<tr class="memitem:gad6fdf317d06706f2a57b4aca8334eb37" id="r_gad6fdf317d06706f2a57b4aca8334eb37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6fdf317d06706f2a57b4aca8334eb37">ADC_DR_ADC2DATA_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga86da874944121326b9f268295d8ce9b9" id="r_ga86da874944121326b9f268295d8ce9b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86da874944121326b9f268295d8ce9b9">ADC_DR_ADC2DATA_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad6fdf317d06706f2a57b4aca8334eb37">ADC_DR_ADC2DATA_Pos</a>)</td></tr>
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<tr class="memitem:ga67c396288ac97bfab2d37017bd536b98" id="r_ga67c396288ac97bfab2d37017bd536b98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67c396288ac97bfab2d37017bd536b98">ADC_DR_ADC2DATA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86da874944121326b9f268295d8ce9b9">ADC_DR_ADC2DATA_Msk</a></td></tr>
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<tr class="memitem:gaabf05dcdb9f298564bf23c2c012e0471" id="r_gaabf05dcdb9f298564bf23c2c012e0471"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabf05dcdb9f298564bf23c2c012e0471">ADC_CSR_AWD1_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaabf05dcdb9f298564bf23c2c012e0471"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fc1dc3f69bc55d0dc278a8cfe172200" id="r_ga8fc1dc3f69bc55d0dc278a8cfe172200"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fc1dc3f69bc55d0dc278a8cfe172200">ADC_CSR_AWD1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaabf05dcdb9f298564bf23c2c012e0471">ADC_CSR_AWD1_Pos</a>)</td></tr>
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<tr class="separator:ga8fc1dc3f69bc55d0dc278a8cfe172200"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e640f7443f14d01a37e29cff004223f" id="r_ga3e640f7443f14d01a37e29cff004223f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e640f7443f14d01a37e29cff004223f">ADC_CSR_AWD1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fc1dc3f69bc55d0dc278a8cfe172200">ADC_CSR_AWD1_Msk</a></td></tr>
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<tr class="separator:ga3e640f7443f14d01a37e29cff004223f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga193522f6fdf87c39545d2697f3650547" id="r_ga193522f6fdf87c39545d2697f3650547"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga193522f6fdf87c39545d2697f3650547">ADC_CSR_EOC1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga193522f6fdf87c39545d2697f3650547"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacaca4cc88bbeca3aee454610c500d2fc" id="r_gacaca4cc88bbeca3aee454610c500d2fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacaca4cc88bbeca3aee454610c500d2fc">ADC_CSR_EOC1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga193522f6fdf87c39545d2697f3650547">ADC_CSR_EOC1_Pos</a>)</td></tr>
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<tr class="separator:gacaca4cc88bbeca3aee454610c500d2fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga715bcb019d713187aacd46f4482fa5f9" id="r_ga715bcb019d713187aacd46f4482fa5f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga715bcb019d713187aacd46f4482fa5f9">ADC_CSR_EOC1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacaca4cc88bbeca3aee454610c500d2fc">ADC_CSR_EOC1_Msk</a></td></tr>
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<tr class="separator:ga715bcb019d713187aacd46f4482fa5f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabff4c4fa606c1a8c035b453d95da53fd" id="r_gabff4c4fa606c1a8c035b453d95da53fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabff4c4fa606c1a8c035b453d95da53fd">ADC_CSR_JEOC1_Pos</a>   (2U)</td></tr>
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<tr class="separator:gabff4c4fa606c1a8c035b453d95da53fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga954441bd559cdbe9da94c7ff0172c859" id="r_ga954441bd559cdbe9da94c7ff0172c859"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga954441bd559cdbe9da94c7ff0172c859">ADC_CSR_JEOC1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabff4c4fa606c1a8c035b453d95da53fd">ADC_CSR_JEOC1_Pos</a>)</td></tr>
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<tr class="separator:ga954441bd559cdbe9da94c7ff0172c859"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a8a134d8b946f3549390294ef94b8d6" id="r_ga1a8a134d8b946f3549390294ef94b8d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a8a134d8b946f3549390294ef94b8d6">ADC_CSR_JEOC1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga954441bd559cdbe9da94c7ff0172c859">ADC_CSR_JEOC1_Msk</a></td></tr>
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<tr class="separator:ga1a8a134d8b946f3549390294ef94b8d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa094512686f5c37d85ec4c41b9fe1d21" id="r_gaa094512686f5c37d85ec4c41b9fe1d21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa094512686f5c37d85ec4c41b9fe1d21">ADC_CSR_JSTRT1_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaa094512686f5c37d85ec4c41b9fe1d21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e0c41a114f966849054e2e43ee9b115" id="r_ga6e0c41a114f966849054e2e43ee9b115"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e0c41a114f966849054e2e43ee9b115">ADC_CSR_JSTRT1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa094512686f5c37d85ec4c41b9fe1d21">ADC_CSR_JSTRT1_Pos</a>)</td></tr>
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<tr class="separator:ga6e0c41a114f966849054e2e43ee9b115"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f1e6578b14d71c6d972c6d6f6d48eaa" id="r_ga3f1e6578b14d71c6d972c6d6f6d48eaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1e6578b14d71c6d972c6d6f6d48eaa">ADC_CSR_JSTRT1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e0c41a114f966849054e2e43ee9b115">ADC_CSR_JSTRT1_Msk</a></td></tr>
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<tr class="separator:ga3f1e6578b14d71c6d972c6d6f6d48eaa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga186066448c230ab12a99cd67a22aaea5" id="r_ga186066448c230ab12a99cd67a22aaea5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga186066448c230ab12a99cd67a22aaea5">ADC_CSR_STRT1_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga186066448c230ab12a99cd67a22aaea5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d9691131e58b26068e792ad4b458bd6" id="r_ga1d9691131e58b26068e792ad4b458bd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d9691131e58b26068e792ad4b458bd6">ADC_CSR_STRT1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga186066448c230ab12a99cd67a22aaea5">ADC_CSR_STRT1_Pos</a>)</td></tr>
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<tr class="separator:ga1d9691131e58b26068e792ad4b458bd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78ff468cfaa299ef62ab7b8b9910e142" id="r_ga78ff468cfaa299ef62ab7b8b9910e142"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78ff468cfaa299ef62ab7b8b9910e142">ADC_CSR_STRT1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d9691131e58b26068e792ad4b458bd6">ADC_CSR_STRT1_Msk</a></td></tr>
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<tr class="separator:ga78ff468cfaa299ef62ab7b8b9910e142"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94e77ef740b6a1dccec74746261be4f1" id="r_ga94e77ef740b6a1dccec74746261be4f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94e77ef740b6a1dccec74746261be4f1">ADC_CSR_OVR1_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga94e77ef740b6a1dccec74746261be4f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ab0daf58c1ac552862c36465fc864cc" id="r_ga7ab0daf58c1ac552862c36465fc864cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ab0daf58c1ac552862c36465fc864cc">ADC_CSR_OVR1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga94e77ef740b6a1dccec74746261be4f1">ADC_CSR_OVR1_Pos</a>)</td></tr>
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<tr class="separator:ga7ab0daf58c1ac552862c36465fc864cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52c109fe013835222183c22b26d6edec" id="r_ga52c109fe013835222183c22b26d6edec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52c109fe013835222183c22b26d6edec">ADC_CSR_OVR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ab0daf58c1ac552862c36465fc864cc">ADC_CSR_OVR1_Msk</a></td></tr>
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<tr class="separator:ga52c109fe013835222183c22b26d6edec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f64205df755a2aef86ebb9f9cbe912f" id="r_ga2f64205df755a2aef86ebb9f9cbe912f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f64205df755a2aef86ebb9f9cbe912f">ADC_CSR_AWD2_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga2f64205df755a2aef86ebb9f9cbe912f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf07d606cd2ac81d17e0a9cf425261d33" id="r_gaf07d606cd2ac81d17e0a9cf425261d33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf07d606cd2ac81d17e0a9cf425261d33">ADC_CSR_AWD2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f64205df755a2aef86ebb9f9cbe912f">ADC_CSR_AWD2_Pos</a>)</td></tr>
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<tr class="separator:gaf07d606cd2ac81d17e0a9cf425261d33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80d8090a99ec65807ed831fea0d5524c" id="r_ga80d8090a99ec65807ed831fea0d5524c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80d8090a99ec65807ed831fea0d5524c">ADC_CSR_AWD2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf07d606cd2ac81d17e0a9cf425261d33">ADC_CSR_AWD2_Msk</a></td></tr>
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<tr class="separator:ga80d8090a99ec65807ed831fea0d5524c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c366fb2cc8fe08c701b8b8f5babe5f8" id="r_ga4c366fb2cc8fe08c701b8b8f5babe5f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c366fb2cc8fe08c701b8b8f5babe5f8">ADC_CSR_EOC2_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga4c366fb2cc8fe08c701b8b8f5babe5f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d50d5f274525ebcca937eac9f52d2d1" id="r_ga8d50d5f274525ebcca937eac9f52d2d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d50d5f274525ebcca937eac9f52d2d1">ADC_CSR_EOC2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c366fb2cc8fe08c701b8b8f5babe5f8">ADC_CSR_EOC2_Pos</a>)</td></tr>
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<tr class="separator:ga8d50d5f274525ebcca937eac9f52d2d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga411d79254769bbb4eeb14964abad497a" id="r_ga411d79254769bbb4eeb14964abad497a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga411d79254769bbb4eeb14964abad497a">ADC_CSR_EOC2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d50d5f274525ebcca937eac9f52d2d1">ADC_CSR_EOC2_Msk</a></td></tr>
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<tr class="separator:ga411d79254769bbb4eeb14964abad497a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5615f8b2030741d5188cb255da51a409" id="r_ga5615f8b2030741d5188cb255da51a409"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5615f8b2030741d5188cb255da51a409">ADC_CSR_JEOC2_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga5615f8b2030741d5188cb255da51a409"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a92cfaa1c1cf45b621a52cdea84dfb4" id="r_ga8a92cfaa1c1cf45b621a52cdea84dfb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a92cfaa1c1cf45b621a52cdea84dfb4">ADC_CSR_JEOC2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5615f8b2030741d5188cb255da51a409">ADC_CSR_JEOC2_Pos</a>)</td></tr>
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<tr class="separator:ga8a92cfaa1c1cf45b621a52cdea84dfb4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf24dbb77fadc6f928b8e38199a08abc7" id="r_gaf24dbb77fadc6f928b8e38199a08abc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf24dbb77fadc6f928b8e38199a08abc7">ADC_CSR_JEOC2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a92cfaa1c1cf45b621a52cdea84dfb4">ADC_CSR_JEOC2_Msk</a></td></tr>
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<tr class="separator:gaf24dbb77fadc6f928b8e38199a08abc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7624f0eb95cc1a44180577d68273a13" id="r_gaa7624f0eb95cc1a44180577d68273a13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7624f0eb95cc1a44180577d68273a13">ADC_CSR_JSTRT2_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaa7624f0eb95cc1a44180577d68273a13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f6fcf838fd219679c57c9b87eba1444" id="r_ga1f6fcf838fd219679c57c9b87eba1444"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f6fcf838fd219679c57c9b87eba1444">ADC_CSR_JSTRT2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7624f0eb95cc1a44180577d68273a13">ADC_CSR_JSTRT2_Pos</a>)</td></tr>
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<tr class="separator:ga1f6fcf838fd219679c57c9b87eba1444"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ca65d6d580299518fb7491e1cebac1d" id="r_ga0ca65d6d580299518fb7491e1cebac1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ca65d6d580299518fb7491e1cebac1d">ADC_CSR_JSTRT2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f6fcf838fd219679c57c9b87eba1444">ADC_CSR_JSTRT2_Msk</a></td></tr>
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<tr class="separator:ga0ca65d6d580299518fb7491e1cebac1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf06d7d8b3b81c9fca7b92449c039a859" id="r_gaf06d7d8b3b81c9fca7b92449c039a859"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf06d7d8b3b81c9fca7b92449c039a859">ADC_CSR_STRT2_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaf06d7d8b3b81c9fca7b92449c039a859"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae765e2672e081170cb86dc14096b2c9d" id="r_gae765e2672e081170cb86dc14096b2c9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae765e2672e081170cb86dc14096b2c9d">ADC_CSR_STRT2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf06d7d8b3b81c9fca7b92449c039a859">ADC_CSR_STRT2_Pos</a>)</td></tr>
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<tr class="separator:gae765e2672e081170cb86dc14096b2c9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9e79005049b17d08c28aeca86677655" id="r_gac9e79005049b17d08c28aeca86677655"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9e79005049b17d08c28aeca86677655">ADC_CSR_STRT2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae765e2672e081170cb86dc14096b2c9d">ADC_CSR_STRT2_Msk</a></td></tr>
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<tr class="memitem:ga6ad98b43be125be93ecac83e636b9b30" id="r_ga6ad98b43be125be93ecac83e636b9b30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad98b43be125be93ecac83e636b9b30">ADC_CSR_OVR2_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga592e0a5440edb75e0af2cbb8f8e9f4ca" id="r_ga592e0a5440edb75e0af2cbb8f8e9f4ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga592e0a5440edb75e0af2cbb8f8e9f4ca">ADC_CSR_OVR2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad98b43be125be93ecac83e636b9b30">ADC_CSR_OVR2_Pos</a>)</td></tr>
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<tr class="memitem:ga3b0e80da58202660466f6916c0bbb9da" id="r_ga3b0e80da58202660466f6916c0bbb9da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b0e80da58202660466f6916c0bbb9da">ADC_CSR_OVR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga592e0a5440edb75e0af2cbb8f8e9f4ca">ADC_CSR_OVR2_Msk</a></td></tr>
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<tr class="memitem:ga0cc0cb58fe0e65bf12a871cd5b4f5a3a" id="r_ga0cc0cb58fe0e65bf12a871cd5b4f5a3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cc0cb58fe0e65bf12a871cd5b4f5a3a">ADC_CSR_AWD3_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga0cc0cb58fe0e65bf12a871cd5b4f5a3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab466d762c126698b9be1d851411e13b9" id="r_gab466d762c126698b9be1d851411e13b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab466d762c126698b9be1d851411e13b9">ADC_CSR_AWD3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cc0cb58fe0e65bf12a871cd5b4f5a3a">ADC_CSR_AWD3_Pos</a>)</td></tr>
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<tr class="memitem:gad8883de33c5a7b30c611db11340fec6d" id="r_gad8883de33c5a7b30c611db11340fec6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8883de33c5a7b30c611db11340fec6d">ADC_CSR_AWD3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab466d762c126698b9be1d851411e13b9">ADC_CSR_AWD3_Msk</a></td></tr>
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<tr class="separator:gad8883de33c5a7b30c611db11340fec6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17e2ab7d373bb1befc8891719de8c437" id="r_ga17e2ab7d373bb1befc8891719de8c437"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17e2ab7d373bb1befc8891719de8c437">ADC_CSR_EOC3_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga17e2ab7d373bb1befc8891719de8c437"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga337e83ffa1ec72fe00ab4b9c889a5acd" id="r_ga337e83ffa1ec72fe00ab4b9c889a5acd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga337e83ffa1ec72fe00ab4b9c889a5acd">ADC_CSR_EOC3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17e2ab7d373bb1befc8891719de8c437">ADC_CSR_EOC3_Pos</a>)</td></tr>
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<tr class="separator:ga337e83ffa1ec72fe00ab4b9c889a5acd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a94c410343ba459146b2bb17833a795" id="r_ga4a94c410343ba459146b2bb17833a795"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a94c410343ba459146b2bb17833a795">ADC_CSR_EOC3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga337e83ffa1ec72fe00ab4b9c889a5acd">ADC_CSR_EOC3_Msk</a></td></tr>
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<tr class="separator:ga4a94c410343ba459146b2bb17833a795"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d7e8c14892467a1d198b169c3c0bb78" id="r_ga6d7e8c14892467a1d198b169c3c0bb78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d7e8c14892467a1d198b169c3c0bb78">ADC_CSR_JEOC3_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga6d7e8c14892467a1d198b169c3c0bb78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48e83374e0184b6a6ba6f3216d0d2ecc" id="r_ga48e83374e0184b6a6ba6f3216d0d2ecc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48e83374e0184b6a6ba6f3216d0d2ecc">ADC_CSR_JEOC3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d7e8c14892467a1d198b169c3c0bb78">ADC_CSR_JEOC3_Pos</a>)</td></tr>
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<tr class="memitem:gae7d3c36f449ef1ee9ee20c5686b4e974" id="r_gae7d3c36f449ef1ee9ee20c5686b4e974"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7d3c36f449ef1ee9ee20c5686b4e974">ADC_CSR_JEOC3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga48e83374e0184b6a6ba6f3216d0d2ecc">ADC_CSR_JEOC3_Msk</a></td></tr>
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<tr class="separator:gae7d3c36f449ef1ee9ee20c5686b4e974"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e64575250e915936cf02785b3068c95" id="r_ga6e64575250e915936cf02785b3068c95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e64575250e915936cf02785b3068c95">ADC_CSR_JSTRT3_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga6e64575250e915936cf02785b3068c95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa137f40aeea09749a280b436c560a8e6" id="r_gaa137f40aeea09749a280b436c560a8e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa137f40aeea09749a280b436c560a8e6">ADC_CSR_JSTRT3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e64575250e915936cf02785b3068c95">ADC_CSR_JSTRT3_Pos</a>)</td></tr>
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<tr class="memitem:ga94140d21b4c83d9f401cc459a7ec6060" id="r_ga94140d21b4c83d9f401cc459a7ec6060"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94140d21b4c83d9f401cc459a7ec6060">ADC_CSR_JSTRT3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa137f40aeea09749a280b436c560a8e6">ADC_CSR_JSTRT3_Msk</a></td></tr>
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<tr class="separator:ga94140d21b4c83d9f401cc459a7ec6060"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f2699ef95e89fb1803e46d4670ce1f2" id="r_ga1f2699ef95e89fb1803e46d4670ce1f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f2699ef95e89fb1803e46d4670ce1f2">ADC_CSR_STRT3_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga1f2699ef95e89fb1803e46d4670ce1f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga774dbbb3929e4d525c6fce448459a711" id="r_ga774dbbb3929e4d525c6fce448459a711"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga774dbbb3929e4d525c6fce448459a711">ADC_CSR_STRT3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f2699ef95e89fb1803e46d4670ce1f2">ADC_CSR_STRT3_Pos</a>)</td></tr>
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<tr class="separator:ga774dbbb3929e4d525c6fce448459a711"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13ca665cc575b64588475723f5289d4a" id="r_ga13ca665cc575b64588475723f5289d4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13ca665cc575b64588475723f5289d4a">ADC_CSR_STRT3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga774dbbb3929e4d525c6fce448459a711">ADC_CSR_STRT3_Msk</a></td></tr>
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<tr class="memitem:gab46fd70aefec77d01f6fba4d19d677b6" id="r_gab46fd70aefec77d01f6fba4d19d677b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab46fd70aefec77d01f6fba4d19d677b6">ADC_CSR_OVR3_Pos</a>   (21U)</td></tr>
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<tr class="separator:gab46fd70aefec77d01f6fba4d19d677b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef6f4ccc5a845954e07699858b868c9b" id="r_gaef6f4ccc5a845954e07699858b868c9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef6f4ccc5a845954e07699858b868c9b">ADC_CSR_OVR3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab46fd70aefec77d01f6fba4d19d677b6">ADC_CSR_OVR3_Pos</a>)</td></tr>
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<tr class="separator:gaef6f4ccc5a845954e07699858b868c9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab76495b35a2bc7fc5f1b51ab1ee92384" id="r_gab76495b35a2bc7fc5f1b51ab1ee92384"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab76495b35a2bc7fc5f1b51ab1ee92384">ADC_CSR_OVR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaef6f4ccc5a845954e07699858b868c9b">ADC_CSR_OVR3_Msk</a></td></tr>
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<tr class="memitem:ga321ed2ccdf98d3a3307947056a8c401a" id="r_ga321ed2ccdf98d3a3307947056a8c401a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga321ed2ccdf98d3a3307947056a8c401a">ADC_CSR_DOVR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga52c109fe013835222183c22b26d6edec">ADC_CSR_OVR1</a></td></tr>
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<tr class="memitem:ga00e2a30df5568b5663e9f016743b3a35" id="r_ga00e2a30df5568b5663e9f016743b3a35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00e2a30df5568b5663e9f016743b3a35">ADC_CSR_DOVR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b0e80da58202660466f6916c0bbb9da">ADC_CSR_OVR2</a></td></tr>
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<tr class="memitem:ga396513974cf26f2a4aa0f36e755e227c" id="r_ga396513974cf26f2a4aa0f36e755e227c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga396513974cf26f2a4aa0f36e755e227c">ADC_CSR_DOVR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab76495b35a2bc7fc5f1b51ab1ee92384">ADC_CSR_OVR3</a></td></tr>
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<tr class="separator:ga396513974cf26f2a4aa0f36e755e227c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f9e95bcdc01cb070e8b42441839b517" id="r_ga9f9e95bcdc01cb070e8b42441839b517"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f9e95bcdc01cb070e8b42441839b517">ADC_CCR_MULTI_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga9f9e95bcdc01cb070e8b42441839b517"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga535eaa79d3a77403b2e0981641f10f81" id="r_ga535eaa79d3a77403b2e0981641f10f81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga535eaa79d3a77403b2e0981641f10f81">ADC_CCR_MULTI_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f9e95bcdc01cb070e8b42441839b517">ADC_CCR_MULTI_Pos</a>)</td></tr>
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<tr class="separator:ga535eaa79d3a77403b2e0981641f10f81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf70ab04667c7c7da0f29c0e5a6c48e68" id="r_gaf70ab04667c7c7da0f29c0e5a6c48e68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf70ab04667c7c7da0f29c0e5a6c48e68">ADC_CCR_MULTI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga535eaa79d3a77403b2e0981641f10f81">ADC_CCR_MULTI_Msk</a></td></tr>
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<tr class="memitem:gae4e7104ce01e3a79b8f6138d87dc3684" id="r_gae4e7104ce01e3a79b8f6138d87dc3684"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4e7104ce01e3a79b8f6138d87dc3684">ADC_CCR_MULTI_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f9e95bcdc01cb070e8b42441839b517">ADC_CCR_MULTI_Pos</a>)</td></tr>
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<tr class="separator:gae4e7104ce01e3a79b8f6138d87dc3684"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8781dec7f076b475b85f8470aee94d06" id="r_ga8781dec7f076b475b85f8470aee94d06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8781dec7f076b475b85f8470aee94d06">ADC_CCR_MULTI_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f9e95bcdc01cb070e8b42441839b517">ADC_CCR_MULTI_Pos</a>)</td></tr>
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<tr class="memitem:gae6a5be6cff1227431b8d54dffcc1ce88" id="r_gae6a5be6cff1227431b8d54dffcc1ce88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6a5be6cff1227431b8d54dffcc1ce88">ADC_CCR_MULTI_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f9e95bcdc01cb070e8b42441839b517">ADC_CCR_MULTI_Pos</a>)</td></tr>
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<tr class="separator:gae6a5be6cff1227431b8d54dffcc1ce88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae55be7b911b4c0272543f98a0dba5f20" id="r_gae55be7b911b4c0272543f98a0dba5f20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae55be7b911b4c0272543f98a0dba5f20">ADC_CCR_MULTI_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f9e95bcdc01cb070e8b42441839b517">ADC_CCR_MULTI_Pos</a>)</td></tr>
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<tr class="separator:gae55be7b911b4c0272543f98a0dba5f20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5087b3cb0d4570b80b3138c277bcbf6c" id="r_ga5087b3cb0d4570b80b3138c277bcbf6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5087b3cb0d4570b80b3138c277bcbf6c">ADC_CCR_MULTI_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f9e95bcdc01cb070e8b42441839b517">ADC_CCR_MULTI_Pos</a>)</td></tr>
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<tr class="memitem:ga702c581a6341f08b3198cd41b0cb69a3" id="r_ga702c581a6341f08b3198cd41b0cb69a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga702c581a6341f08b3198cd41b0cb69a3">ADC_CCR_DELAY_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga7c1c63139684661c857ece4937a72415" id="r_ga7c1c63139684661c857ece4937a72415"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c1c63139684661c857ece4937a72415">ADC_CCR_DELAY_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702c581a6341f08b3198cd41b0cb69a3">ADC_CCR_DELAY_Pos</a>)</td></tr>
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<tr class="memitem:ga9c13aa04949ed520cf92613d3a619198" id="r_ga9c13aa04949ed520cf92613d3a619198"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c13aa04949ed520cf92613d3a619198">ADC_CCR_DELAY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c1c63139684661c857ece4937a72415">ADC_CCR_DELAY_Msk</a></td></tr>
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<tr class="memitem:ga22b71e9df8b1fca93802ad602341eb0b" id="r_ga22b71e9df8b1fca93802ad602341eb0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22b71e9df8b1fca93802ad602341eb0b">ADC_CCR_DELAY_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702c581a6341f08b3198cd41b0cb69a3">ADC_CCR_DELAY_Pos</a>)</td></tr>
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<tr class="memitem:ga6d0d5785cb6c75e700517e88af188573" id="r_ga6d0d5785cb6c75e700517e88af188573"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d0d5785cb6c75e700517e88af188573">ADC_CCR_DELAY_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702c581a6341f08b3198cd41b0cb69a3">ADC_CCR_DELAY_Pos</a>)</td></tr>
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<tr class="memitem:ga17f85cbda5dcf9a392a29befb73c6ceb" id="r_ga17f85cbda5dcf9a392a29befb73c6ceb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17f85cbda5dcf9a392a29befb73c6ceb">ADC_CCR_DELAY_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702c581a6341f08b3198cd41b0cb69a3">ADC_CCR_DELAY_Pos</a>)</td></tr>
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<tr class="memitem:gae0216de7d6fcfa507c9aa1400972d862" id="r_gae0216de7d6fcfa507c9aa1400972d862"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0216de7d6fcfa507c9aa1400972d862">ADC_CCR_DELAY_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702c581a6341f08b3198cd41b0cb69a3">ADC_CCR_DELAY_Pos</a>)</td></tr>
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<tr class="memitem:ga27c6d297e452d728c075a6f9b953d0a5" id="r_ga27c6d297e452d728c075a6f9b953d0a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27c6d297e452d728c075a6f9b953d0a5">ADC_CCR_DDS_Pos</a>   (13U)</td></tr>
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<tr class="memitem:gad41720d885d32a33cb04782a2a2a74f9" id="r_gad41720d885d32a33cb04782a2a2a74f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad41720d885d32a33cb04782a2a2a74f9">ADC_CCR_DDS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27c6d297e452d728c075a6f9b953d0a5">ADC_CCR_DDS_Pos</a>)</td></tr>
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<tr class="memitem:ga7e745513bbc2e5e5a76ae999d5d535af" id="r_ga7e745513bbc2e5e5a76ae999d5d535af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e745513bbc2e5e5a76ae999d5d535af">ADC_CCR_DDS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad41720d885d32a33cb04782a2a2a74f9">ADC_CCR_DDS_Msk</a></td></tr>
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<tr class="memitem:ga2cdf117dd6f678b5d2121253b4e452c6" id="r_ga2cdf117dd6f678b5d2121253b4e452c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdf117dd6f678b5d2121253b4e452c6">ADC_CCR_DMA_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gab7933afb88d395724816248ec8fa9b76" id="r_gab7933afb88d395724816248ec8fa9b76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7933afb88d395724816248ec8fa9b76">ADC_CCR_DMA_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdf117dd6f678b5d2121253b4e452c6">ADC_CCR_DMA_Pos</a>)</td></tr>
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<tr class="memitem:ga9e346b21afcaeced784e6c80b3aa1fb4" id="r_ga9e346b21afcaeced784e6c80b3aa1fb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e346b21afcaeced784e6c80b3aa1fb4">ADC_CCR_DMA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab7933afb88d395724816248ec8fa9b76">ADC_CCR_DMA_Msk</a></td></tr>
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<tr class="memitem:ga3a42ee6ec5115244aef8f60d35abcc47" id="r_ga3a42ee6ec5115244aef8f60d35abcc47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a42ee6ec5115244aef8f60d35abcc47">ADC_CCR_DMA_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdf117dd6f678b5d2121253b4e452c6">ADC_CCR_DMA_Pos</a>)</td></tr>
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<tr class="memitem:gacdc9d29cafdd54e5c0dd752c358e1bc8" id="r_gacdc9d29cafdd54e5c0dd752c358e1bc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdc9d29cafdd54e5c0dd752c358e1bc8">ADC_CCR_DMA_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdf117dd6f678b5d2121253b4e452c6">ADC_CCR_DMA_Pos</a>)</td></tr>
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<tr class="memitem:gafceea99dc2287c360b275732f9862bca" id="r_gafceea99dc2287c360b275732f9862bca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafceea99dc2287c360b275732f9862bca">ADC_CCR_ADCPRE_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga2458ab94917987a44a275e1ed886e825" id="r_ga2458ab94917987a44a275e1ed886e825"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2458ab94917987a44a275e1ed886e825">ADC_CCR_ADCPRE_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafceea99dc2287c360b275732f9862bca">ADC_CCR_ADCPRE_Pos</a>)</td></tr>
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<tr class="memitem:ga3a2ee019aef4c64fffc72141f7aaab2c" id="r_ga3a2ee019aef4c64fffc72141f7aaab2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a2ee019aef4c64fffc72141f7aaab2c">ADC_CCR_ADCPRE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2458ab94917987a44a275e1ed886e825">ADC_CCR_ADCPRE_Msk</a></td></tr>
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<tr class="memitem:gaf3108cc8fb81f6efd1e93fa5f82ac313" id="r_gaf3108cc8fb81f6efd1e93fa5f82ac313"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3108cc8fb81f6efd1e93fa5f82ac313">ADC_CCR_ADCPRE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafceea99dc2287c360b275732f9862bca">ADC_CCR_ADCPRE_Pos</a>)</td></tr>
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<tr class="memitem:gafa090830d2d359db04f365d46c6644d5" id="r_gafa090830d2d359db04f365d46c6644d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa090830d2d359db04f365d46c6644d5">ADC_CCR_ADCPRE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafceea99dc2287c360b275732f9862bca">ADC_CCR_ADCPRE_Pos</a>)</td></tr>
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<tr class="memitem:ga8ece9c9847db39ff9782d07ed5104bbf" id="r_ga8ece9c9847db39ff9782d07ed5104bbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ece9c9847db39ff9782d07ed5104bbf">ADC_CCR_VBATE_Pos</a>   (22U)</td></tr>
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<tr class="memitem:gac3d86d837c7c40d14882728116a3722b" id="r_gac3d86d837c7c40d14882728116a3722b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3d86d837c7c40d14882728116a3722b">ADC_CCR_VBATE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ece9c9847db39ff9782d07ed5104bbf">ADC_CCR_VBATE_Pos</a>)</td></tr>
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<tr class="separator:gac3d86d837c7c40d14882728116a3722b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga519645e42dcf6b19af9c05dc40300abb" id="r_ga519645e42dcf6b19af9c05dc40300abb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga519645e42dcf6b19af9c05dc40300abb">ADC_CCR_VBATE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac3d86d837c7c40d14882728116a3722b">ADC_CCR_VBATE_Msk</a></td></tr>
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<tr class="memitem:ga9741df391649af046f8310352ca3b3be" id="r_ga9741df391649af046f8310352ca3b3be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9741df391649af046f8310352ca3b3be">ADC_CCR_TSVREFE_Pos</a>   (23U)</td></tr>
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<tr class="memitem:ga5e1a3df0d33a0c78197ad8c161c22a7a" id="r_ga5e1a3df0d33a0c78197ad8c161c22a7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e1a3df0d33a0c78197ad8c161c22a7a">ADC_CCR_TSVREFE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9741df391649af046f8310352ca3b3be">ADC_CCR_TSVREFE_Pos</a>)</td></tr>
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<tr class="separator:ga5e1a3df0d33a0c78197ad8c161c22a7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc020d85a8740491ce3f218a0706f1dc" id="r_gafc020d85a8740491ce3f218a0706f1dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc020d85a8740491ce3f218a0706f1dc">ADC_CCR_TSVREFE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e1a3df0d33a0c78197ad8c161c22a7a">ADC_CCR_TSVREFE_Msk</a></td></tr>
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<tr class="memitem:gaa14929dd3fe8ae466d2ad41c395ca2c1" id="r_gaa14929dd3fe8ae466d2ad41c395ca2c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa14929dd3fe8ae466d2ad41c395ca2c1">ADC_CDR_DATA1_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gadb4c80caea7b29ec5b2b863e84288cf1" id="r_gadb4c80caea7b29ec5b2b863e84288cf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb4c80caea7b29ec5b2b863e84288cf1">ADC_CDR_DATA1_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa14929dd3fe8ae466d2ad41c395ca2c1">ADC_CDR_DATA1_Pos</a>)</td></tr>
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<tr class="memitem:ga6d7a0a18c77816c45c5682c3884e3d56" id="r_ga6d7a0a18c77816c45c5682c3884e3d56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d7a0a18c77816c45c5682c3884e3d56">ADC_CDR_DATA1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadb4c80caea7b29ec5b2b863e84288cf1">ADC_CDR_DATA1_Msk</a></td></tr>
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<tr class="memitem:gab562b2adbf577b621d81758fa806e5fc" id="r_gab562b2adbf577b621d81758fa806e5fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab562b2adbf577b621d81758fa806e5fc">ADC_CDR_DATA2_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga2e8ac90ba8958b4d858c24e2896f7733" id="r_ga2e8ac90ba8958b4d858c24e2896f7733"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e8ac90ba8958b4d858c24e2896f7733">ADC_CDR_DATA2_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab562b2adbf577b621d81758fa806e5fc">ADC_CDR_DATA2_Pos</a>)</td></tr>
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<tr class="memitem:ga55f0776b9bf2612c194c1ab478d8a371" id="r_ga55f0776b9bf2612c194c1ab478d8a371"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55f0776b9bf2612c194c1ab478d8a371">ADC_CDR_DATA2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e8ac90ba8958b4d858c24e2896f7733">ADC_CDR_DATA2_Msk</a></td></tr>
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<tr class="memitem:ga588fd6c0f172ca0e7683bb54034564fe" id="r_ga588fd6c0f172ca0e7683bb54034564fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga588fd6c0f172ca0e7683bb54034564fe">ADC_CDR_RDATA_MST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d7a0a18c77816c45c5682c3884e3d56">ADC_CDR_DATA1</a></td></tr>
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<tr class="memitem:gad582026e4b62991d8281b51494902a33" id="r_gad582026e4b62991d8281b51494902a33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad582026e4b62991d8281b51494902a33">ADC_CDR_RDATA_SLV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga55f0776b9bf2612c194c1ab478d8a371">ADC_CDR_DATA2</a></td></tr>
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<tr class="memitem:ga5bcdd01eb82046959b22b3d254073c22" id="r_ga5bcdd01eb82046959b22b3d254073c22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bcdd01eb82046959b22b3d254073c22">CAN_MCR_INRQ_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5bcdd01eb82046959b22b3d254073c22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7afc4335014982a4cfac31de0cdbebc" id="r_gaf7afc4335014982a4cfac31de0cdbebc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7afc4335014982a4cfac31de0cdbebc">CAN_MCR_INRQ_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bcdd01eb82046959b22b3d254073c22">CAN_MCR_INRQ_Pos</a>)</td></tr>
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<tr class="separator:gaf7afc4335014982a4cfac31de0cdbebc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cf12be5661908dbe38aa14cd4c3a356" id="r_ga0cf12be5661908dbe38aa14cd4c3a356"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cf12be5661908dbe38aa14cd4c3a356">CAN_MCR_INRQ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7afc4335014982a4cfac31de0cdbebc">CAN_MCR_INRQ_Msk</a></td></tr>
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<tr class="separator:ga0cf12be5661908dbe38aa14cd4c3a356"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60009c948dbdf525fb2fc932d988c245" id="r_ga60009c948dbdf525fb2fc932d988c245"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60009c948dbdf525fb2fc932d988c245">CAN_MCR_SLEEP_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga60009c948dbdf525fb2fc932d988c245"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4181676e5d50d29f09805be441efc9b" id="r_gac4181676e5d50d29f09805be441efc9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4181676e5d50d29f09805be441efc9b">CAN_MCR_SLEEP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga60009c948dbdf525fb2fc932d988c245">CAN_MCR_SLEEP_Pos</a>)</td></tr>
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<tr class="separator:gac4181676e5d50d29f09805be441efc9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf9602dfb2f95b481b6e642b95991176" id="r_gadf9602dfb2f95b481b6e642b95991176"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf9602dfb2f95b481b6e642b95991176">CAN_MCR_SLEEP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4181676e5d50d29f09805be441efc9b">CAN_MCR_SLEEP_Msk</a></td></tr>
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<tr class="separator:gadf9602dfb2f95b481b6e642b95991176"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80233affcdda60458e98647fe1416f85" id="r_ga80233affcdda60458e98647fe1416f85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80233affcdda60458e98647fe1416f85">CAN_MCR_TXFP_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga80233affcdda60458e98647fe1416f85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc1c0efc56b72fa75b6e25d773ada7d2" id="r_gacc1c0efc56b72fa75b6e25d773ada7d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc1c0efc56b72fa75b6e25d773ada7d2">CAN_MCR_TXFP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80233affcdda60458e98647fe1416f85">CAN_MCR_TXFP_Pos</a>)</td></tr>
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<tr class="separator:gacc1c0efc56b72fa75b6e25d773ada7d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35e7e66f9cd8cb6efa6a80367d2294a9" id="r_ga35e7e66f9cd8cb6efa6a80367d2294a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35e7e66f9cd8cb6efa6a80367d2294a9">CAN_MCR_TXFP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacc1c0efc56b72fa75b6e25d773ada7d2">CAN_MCR_TXFP_Msk</a></td></tr>
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<tr class="separator:ga35e7e66f9cd8cb6efa6a80367d2294a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf728107056b7bc1dbab277967ad255bc" id="r_gaf728107056b7bc1dbab277967ad255bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf728107056b7bc1dbab277967ad255bc">CAN_MCR_RFLM_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaf728107056b7bc1dbab277967ad255bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ff5789ccbdf18976ec76ab44cd798e0" id="r_ga5ff5789ccbdf18976ec76ab44cd798e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ff5789ccbdf18976ec76ab44cd798e0">CAN_MCR_RFLM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf728107056b7bc1dbab277967ad255bc">CAN_MCR_RFLM_Pos</a>)</td></tr>
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<tr class="separator:ga5ff5789ccbdf18976ec76ab44cd798e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga501125ff257a7d02c35a0d6dcbaa2ba8" id="r_ga501125ff257a7d02c35a0d6dcbaa2ba8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga501125ff257a7d02c35a0d6dcbaa2ba8">CAN_MCR_RFLM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ff5789ccbdf18976ec76ab44cd798e0">CAN_MCR_RFLM_Msk</a></td></tr>
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<tr class="separator:ga501125ff257a7d02c35a0d6dcbaa2ba8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa15d8c6ceddacbfdcfe732d9bcb0cd50" id="r_gaa15d8c6ceddacbfdcfe732d9bcb0cd50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa15d8c6ceddacbfdcfe732d9bcb0cd50">CAN_MCR_NART_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaa15d8c6ceddacbfdcfe732d9bcb0cd50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f03d5006b20e144bec0f3739345bc60" id="r_ga4f03d5006b20e144bec0f3739345bc60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f03d5006b20e144bec0f3739345bc60">CAN_MCR_NART_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa15d8c6ceddacbfdcfe732d9bcb0cd50">CAN_MCR_NART_Pos</a>)</td></tr>
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<tr class="separator:ga4f03d5006b20e144bec0f3739345bc60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2774f04e286942d36a5b6135c8028049" id="r_ga2774f04e286942d36a5b6135c8028049"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2774f04e286942d36a5b6135c8028049">CAN_MCR_NART</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f03d5006b20e144bec0f3739345bc60">CAN_MCR_NART_Msk</a></td></tr>
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<tr class="separator:ga2774f04e286942d36a5b6135c8028049"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga191178a51ef5243b2ecf547aeb1d5eb9" id="r_ga191178a51ef5243b2ecf547aeb1d5eb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga191178a51ef5243b2ecf547aeb1d5eb9">CAN_MCR_AWUM_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga191178a51ef5243b2ecf547aeb1d5eb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a62120fa01d4bb366f02555ddd6a0d4" id="r_ga5a62120fa01d4bb366f02555ddd6a0d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a62120fa01d4bb366f02555ddd6a0d4">CAN_MCR_AWUM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga191178a51ef5243b2ecf547aeb1d5eb9">CAN_MCR_AWUM_Pos</a>)</td></tr>
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<tr class="separator:ga5a62120fa01d4bb366f02555ddd6a0d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2745f1a565c3f2ec5b16612d1fd66e0" id="r_gaa2745f1a565c3f2ec5b16612d1fd66e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2745f1a565c3f2ec5b16612d1fd66e0">CAN_MCR_AWUM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a62120fa01d4bb366f02555ddd6a0d4">CAN_MCR_AWUM_Msk</a></td></tr>
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<tr class="separator:gaa2745f1a565c3f2ec5b16612d1fd66e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cc28c00c9766a53c2ba8c0d42feba92" id="r_ga1cc28c00c9766a53c2ba8c0d42feba92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc28c00c9766a53c2ba8c0d42feba92">CAN_MCR_ABOM_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga1cc28c00c9766a53c2ba8c0d42feba92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb5d923de1437f1c441b540c74c6ebd9" id="r_gaeb5d923de1437f1c441b540c74c6ebd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb5d923de1437f1c441b540c74c6ebd9">CAN_MCR_ABOM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc28c00c9766a53c2ba8c0d42feba92">CAN_MCR_ABOM_Pos</a>)</td></tr>
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<tr class="separator:gaeb5d923de1437f1c441b540c74c6ebd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7aff5c0a3ead7f937849ab66eba7490" id="r_gad7aff5c0a3ead7f937849ab66eba7490"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7aff5c0a3ead7f937849ab66eba7490">CAN_MCR_ABOM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb5d923de1437f1c441b540c74c6ebd9">CAN_MCR_ABOM_Msk</a></td></tr>
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<tr class="separator:gad7aff5c0a3ead7f937849ab66eba7490"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16b15e96f1e4a0203c3974949c2e54a2" id="r_ga16b15e96f1e4a0203c3974949c2e54a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16b15e96f1e4a0203c3974949c2e54a2">CAN_MCR_TTCM_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga16b15e96f1e4a0203c3974949c2e54a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a53a37c946b05dbafc5b7392d5163a3" id="r_ga2a53a37c946b05dbafc5b7392d5163a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a53a37c946b05dbafc5b7392d5163a3">CAN_MCR_TTCM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16b15e96f1e4a0203c3974949c2e54a2">CAN_MCR_TTCM_Pos</a>)</td></tr>
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<tr class="separator:ga2a53a37c946b05dbafc5b7392d5163a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32b2eda9cad8a969c5d2349bd1d853bb" id="r_ga32b2eda9cad8a969c5d2349bd1d853bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32b2eda9cad8a969c5d2349bd1d853bb">CAN_MCR_TTCM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a53a37c946b05dbafc5b7392d5163a3">CAN_MCR_TTCM_Msk</a></td></tr>
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<tr class="separator:ga32b2eda9cad8a969c5d2349bd1d853bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21598a34f72464c29fccedd71b51d519" id="r_ga21598a34f72464c29fccedd71b51d519"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21598a34f72464c29fccedd71b51d519">CAN_MCR_RESET_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga21598a34f72464c29fccedd71b51d519"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa6c92ebbf496383e92f30301169b1b7" id="r_gafa6c92ebbf496383e92f30301169b1b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa6c92ebbf496383e92f30301169b1b7">CAN_MCR_RESET_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21598a34f72464c29fccedd71b51d519">CAN_MCR_RESET_Pos</a>)</td></tr>
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<tr class="separator:gafa6c92ebbf496383e92f30301169b1b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga410fdbad37a9dbda508b8c437277e79f" id="r_ga410fdbad37a9dbda508b8c437277e79f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga410fdbad37a9dbda508b8c437277e79f">CAN_MCR_RESET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafa6c92ebbf496383e92f30301169b1b7">CAN_MCR_RESET_Msk</a></td></tr>
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<tr class="separator:ga410fdbad37a9dbda508b8c437277e79f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa32526e641ef7eed19b3b8db98befbd4" id="r_gaa32526e641ef7eed19b3b8db98befbd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa32526e641ef7eed19b3b8db98befbd4">CAN_MCR_DBF_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaa32526e641ef7eed19b3b8db98befbd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7284f1c36b5a1422050a8204ff673557" id="r_ga7284f1c36b5a1422050a8204ff673557"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7284f1c36b5a1422050a8204ff673557">CAN_MCR_DBF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa32526e641ef7eed19b3b8db98befbd4">CAN_MCR_DBF_Pos</a>)</td></tr>
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<tr class="separator:ga7284f1c36b5a1422050a8204ff673557"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf74445921cdd9df3e44b6b9ba8f67491" id="r_gaf74445921cdd9df3e44b6b9ba8f67491"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf74445921cdd9df3e44b6b9ba8f67491">CAN_MCR_DBF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7284f1c36b5a1422050a8204ff673557">CAN_MCR_DBF_Msk</a></td></tr>
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<tr class="separator:gaf74445921cdd9df3e44b6b9ba8f67491"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2a392cb8353ef23ff078a068ad8cdf9" id="r_gaf2a392cb8353ef23ff078a068ad8cdf9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2a392cb8353ef23ff078a068ad8cdf9">CAN_MSR_INAK_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf2a392cb8353ef23ff078a068ad8cdf9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac65998a2ace7015bb67d9a4a64e4fba5" id="r_gac65998a2ace7015bb67d9a4a64e4fba5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac65998a2ace7015bb67d9a4a64e4fba5">CAN_MSR_INAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2a392cb8353ef23ff078a068ad8cdf9">CAN_MSR_INAK_Pos</a>)</td></tr>
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<tr class="memitem:ga2871cee90ebecb760bab16e9c039b682" id="r_ga2871cee90ebecb760bab16e9c039b682"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2871cee90ebecb760bab16e9c039b682">CAN_MSR_INAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac65998a2ace7015bb67d9a4a64e4fba5">CAN_MSR_INAK_Msk</a></td></tr>
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<tr class="memitem:gac27c0590f11b2b5fb894a60a9700567c" id="r_gac27c0590f11b2b5fb894a60a9700567c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac27c0590f11b2b5fb894a60a9700567c">CAN_MSR_SLAK_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga81eeee3e575f4bd0cf494ad946b11a90" id="r_ga81eeee3e575f4bd0cf494ad946b11a90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81eeee3e575f4bd0cf494ad946b11a90">CAN_MSR_SLAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac27c0590f11b2b5fb894a60a9700567c">CAN_MSR_SLAK_Pos</a>)</td></tr>
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<tr class="memitem:gaf1611badb362f0fd9047af965509f074" id="r_gaf1611badb362f0fd9047af965509f074"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1611badb362f0fd9047af965509f074">CAN_MSR_SLAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga81eeee3e575f4bd0cf494ad946b11a90">CAN_MSR_SLAK_Msk</a></td></tr>
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<tr class="memitem:ga1ff8b9d234d0cd377443d4cc21ccd663" id="r_ga1ff8b9d234d0cd377443d4cc21ccd663"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ff8b9d234d0cd377443d4cc21ccd663">CAN_MSR_ERRI_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga1ff8b9d234d0cd377443d4cc21ccd663"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a189bb7f091383b4cbc858f14cf1dbc" id="r_ga8a189bb7f091383b4cbc858f14cf1dbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a189bb7f091383b4cbc858f14cf1dbc">CAN_MSR_ERRI_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ff8b9d234d0cd377443d4cc21ccd663">CAN_MSR_ERRI_Pos</a>)</td></tr>
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<tr class="separator:ga8a189bb7f091383b4cbc858f14cf1dbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c424768e9e963402f37cb95ae87a1ae" id="r_ga9c424768e9e963402f37cb95ae87a1ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c424768e9e963402f37cb95ae87a1ae">CAN_MSR_ERRI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a189bb7f091383b4cbc858f14cf1dbc">CAN_MSR_ERRI_Msk</a></td></tr>
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<tr class="separator:ga9c424768e9e963402f37cb95ae87a1ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga953a3a5616c5bff5392ff196772915d7" id="r_ga953a3a5616c5bff5392ff196772915d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga953a3a5616c5bff5392ff196772915d7">CAN_MSR_WKUI_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga953a3a5616c5bff5392ff196772915d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad3ddd5d76a1f1e9af5926464efff245" id="r_gaad3ddd5d76a1f1e9af5926464efff245"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad3ddd5d76a1f1e9af5926464efff245">CAN_MSR_WKUI_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga953a3a5616c5bff5392ff196772915d7">CAN_MSR_WKUI_Pos</a>)</td></tr>
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<tr class="separator:gaad3ddd5d76a1f1e9af5926464efff245"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f4c753b96d21c5001b39ad5b08519fc" id="r_ga0f4c753b96d21c5001b39ad5b08519fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f4c753b96d21c5001b39ad5b08519fc">CAN_MSR_WKUI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaad3ddd5d76a1f1e9af5926464efff245">CAN_MSR_WKUI_Msk</a></td></tr>
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<tr class="separator:ga0f4c753b96d21c5001b39ad5b08519fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5030b442fd7a20eb18897625d8d68078" id="r_ga5030b442fd7a20eb18897625d8d68078"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5030b442fd7a20eb18897625d8d68078">CAN_MSR_SLAKI_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga5030b442fd7a20eb18897625d8d68078"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5373a083dae43a5491e9bc91d9478dd5" id="r_ga5373a083dae43a5491e9bc91d9478dd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5373a083dae43a5491e9bc91d9478dd5">CAN_MSR_SLAKI_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5030b442fd7a20eb18897625d8d68078">CAN_MSR_SLAKI_Pos</a>)</td></tr>
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<tr class="separator:ga5373a083dae43a5491e9bc91d9478dd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47ab62ae123c791de27ad05dde5bee91" id="r_ga47ab62ae123c791de27ad05dde5bee91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47ab62ae123c791de27ad05dde5bee91">CAN_MSR_SLAKI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5373a083dae43a5491e9bc91d9478dd5">CAN_MSR_SLAKI_Msk</a></td></tr>
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<tr class="separator:ga47ab62ae123c791de27ad05dde5bee91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3d01c4e4a870b78aca2a679d1936095" id="r_gad3d01c4e4a870b78aca2a679d1936095"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3d01c4e4a870b78aca2a679d1936095">CAN_MSR_TXM_Pos</a>   (8U)</td></tr>
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<tr class="separator:gad3d01c4e4a870b78aca2a679d1936095"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ef1d9966b0022bbbeef87229714ec59" id="r_ga9ef1d9966b0022bbbeef87229714ec59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ef1d9966b0022bbbeef87229714ec59">CAN_MSR_TXM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad3d01c4e4a870b78aca2a679d1936095">CAN_MSR_TXM_Pos</a>)</td></tr>
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<tr class="separator:ga9ef1d9966b0022bbbeef87229714ec59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga651580d35b658e90ea831cb13b8a8988" id="r_ga651580d35b658e90ea831cb13b8a8988"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga651580d35b658e90ea831cb13b8a8988">CAN_MSR_TXM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ef1d9966b0022bbbeef87229714ec59">CAN_MSR_TXM_Msk</a></td></tr>
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<tr class="separator:ga651580d35b658e90ea831cb13b8a8988"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e954c04ec46d198ac7e9b88f46e9a93" id="r_ga9e954c04ec46d198ac7e9b88f46e9a93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e954c04ec46d198ac7e9b88f46e9a93">CAN_MSR_RXM_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga9e954c04ec46d198ac7e9b88f46e9a93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8eec1fe9e0ab8545330e597a28d9035d" id="r_ga8eec1fe9e0ab8545330e597a28d9035d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8eec1fe9e0ab8545330e597a28d9035d">CAN_MSR_RXM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e954c04ec46d198ac7e9b88f46e9a93">CAN_MSR_RXM_Pos</a>)</td></tr>
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<tr class="separator:ga8eec1fe9e0ab8545330e597a28d9035d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67f8e1140b0304930d5b4f2a041a7884" id="r_ga67f8e1140b0304930d5b4f2a041a7884"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67f8e1140b0304930d5b4f2a041a7884">CAN_MSR_RXM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8eec1fe9e0ab8545330e597a28d9035d">CAN_MSR_RXM_Msk</a></td></tr>
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<tr class="separator:ga67f8e1140b0304930d5b4f2a041a7884"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7ede877266831078649ab791547ba3e" id="r_gab7ede877266831078649ab791547ba3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7ede877266831078649ab791547ba3e">CAN_MSR_SAMP_Pos</a>   (10U)</td></tr>
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<tr class="separator:gab7ede877266831078649ab791547ba3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga092ef8e336f9e5bf5121d0a5c28606cb" id="r_ga092ef8e336f9e5bf5121d0a5c28606cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga092ef8e336f9e5bf5121d0a5c28606cb">CAN_MSR_SAMP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab7ede877266831078649ab791547ba3e">CAN_MSR_SAMP_Pos</a>)</td></tr>
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<tr class="separator:ga092ef8e336f9e5bf5121d0a5c28606cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf68038824bb78c4a5c4dee1730848f69" id="r_gaf68038824bb78c4a5c4dee1730848f69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf68038824bb78c4a5c4dee1730848f69">CAN_MSR_SAMP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga092ef8e336f9e5bf5121d0a5c28606cb">CAN_MSR_SAMP_Msk</a></td></tr>
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<tr class="separator:gaf68038824bb78c4a5c4dee1730848f69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef4c2abade47710dcb184a0f406eaf85" id="r_gaef4c2abade47710dcb184a0f406eaf85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef4c2abade47710dcb184a0f406eaf85">CAN_MSR_RX_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaef4c2abade47710dcb184a0f406eaf85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga453cbc8d18bbadf9be9ec9b7987f1dc4" id="r_ga453cbc8d18bbadf9be9ec9b7987f1dc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga453cbc8d18bbadf9be9ec9b7987f1dc4">CAN_MSR_RX_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef4c2abade47710dcb184a0f406eaf85">CAN_MSR_RX_Pos</a>)</td></tr>
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<tr class="separator:ga453cbc8d18bbadf9be9ec9b7987f1dc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6564a1d2f23f246053188a454264eb4b" id="r_ga6564a1d2f23f246053188a454264eb4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6564a1d2f23f246053188a454264eb4b">CAN_MSR_RX</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga453cbc8d18bbadf9be9ec9b7987f1dc4">CAN_MSR_RX_Msk</a></td></tr>
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<tr class="separator:ga6564a1d2f23f246053188a454264eb4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab31d05fd93767905fa9bde4b5d6143d4" id="r_gab31d05fd93767905fa9bde4b5d6143d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab31d05fd93767905fa9bde4b5d6143d4">CAN_TSR_RQCP0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab31d05fd93767905fa9bde4b5d6143d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d71df41ef791745448cbd0aaaad6e38" id="r_ga2d71df41ef791745448cbd0aaaad6e38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d71df41ef791745448cbd0aaaad6e38">CAN_TSR_RQCP0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab31d05fd93767905fa9bde4b5d6143d4">CAN_TSR_RQCP0_Pos</a>)</td></tr>
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<tr class="separator:ga2d71df41ef791745448cbd0aaaad6e38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a4809b8908618df57e6393cc7fe0f52" id="r_ga4a4809b8908618df57e6393cc7fe0f52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a4809b8908618df57e6393cc7fe0f52">CAN_TSR_RQCP0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d71df41ef791745448cbd0aaaad6e38">CAN_TSR_RQCP0_Msk</a></td></tr>
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<tr class="separator:ga4a4809b8908618df57e6393cc7fe0f52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83553d6d8a8baa6d29b9df2e97689281" id="r_ga83553d6d8a8baa6d29b9df2e97689281"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83553d6d8a8baa6d29b9df2e97689281">CAN_TSR_TXOK0_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga83553d6d8a8baa6d29b9df2e97689281"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13bd0e217ec398f9ac7c605b03eaa566" id="r_ga13bd0e217ec398f9ac7c605b03eaa566"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13bd0e217ec398f9ac7c605b03eaa566">CAN_TSR_TXOK0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83553d6d8a8baa6d29b9df2e97689281">CAN_TSR_TXOK0_Pos</a>)</td></tr>
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<tr class="separator:ga13bd0e217ec398f9ac7c605b03eaa566"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacedb237b31d29aef7f38475e9a6b297" id="r_gaacedb237b31d29aef7f38475e9a6b297"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacedb237b31d29aef7f38475e9a6b297">CAN_TSR_TXOK0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga13bd0e217ec398f9ac7c605b03eaa566">CAN_TSR_TXOK0_Msk</a></td></tr>
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<tr class="separator:gaacedb237b31d29aef7f38475e9a6b297"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91b96c96a75628fa3b50f792e68b2b27" id="r_ga91b96c96a75628fa3b50f792e68b2b27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91b96c96a75628fa3b50f792e68b2b27">CAN_TSR_ALST0_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga91b96c96a75628fa3b50f792e68b2b27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d2ee6ceab2eab0f30a108d406855c7e" id="r_ga9d2ee6ceab2eab0f30a108d406855c7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d2ee6ceab2eab0f30a108d406855c7e">CAN_TSR_ALST0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga91b96c96a75628fa3b50f792e68b2b27">CAN_TSR_ALST0_Pos</a>)</td></tr>
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<tr class="separator:ga9d2ee6ceab2eab0f30a108d406855c7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b94ea5001d70a26ec32d9dc6ff76e47" id="r_ga9b94ea5001d70a26ec32d9dc6ff76e47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b94ea5001d70a26ec32d9dc6ff76e47">CAN_TSR_ALST0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d2ee6ceab2eab0f30a108d406855c7e">CAN_TSR_ALST0_Msk</a></td></tr>
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<tr class="separator:ga9b94ea5001d70a26ec32d9dc6ff76e47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52966440e5d87a89726c19d62645a27c" id="r_ga52966440e5d87a89726c19d62645a27c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52966440e5d87a89726c19d62645a27c">CAN_TSR_TERR0_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga52966440e5d87a89726c19d62645a27c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58999cde45dd10f2f351be5cc8ec1a8b" id="r_ga58999cde45dd10f2f351be5cc8ec1a8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58999cde45dd10f2f351be5cc8ec1a8b">CAN_TSR_TERR0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52966440e5d87a89726c19d62645a27c">CAN_TSR_TERR0_Pos</a>)</td></tr>
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<tr class="separator:ga58999cde45dd10f2f351be5cc8ec1a8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga805d2dab5b1d4618492b1cf2a3f5e1e0" id="r_ga805d2dab5b1d4618492b1cf2a3f5e1e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga805d2dab5b1d4618492b1cf2a3f5e1e0">CAN_TSR_TERR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga58999cde45dd10f2f351be5cc8ec1a8b">CAN_TSR_TERR0_Msk</a></td></tr>
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<tr class="separator:ga805d2dab5b1d4618492b1cf2a3f5e1e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56679e8aea1650e19f2baf79b35be24f" id="r_ga56679e8aea1650e19f2baf79b35be24f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56679e8aea1650e19f2baf79b35be24f">CAN_TSR_ABRQ0_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga56679e8aea1650e19f2baf79b35be24f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa78f950ccfd5a5a906c03de00a311047" id="r_gaa78f950ccfd5a5a906c03de00a311047"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa78f950ccfd5a5a906c03de00a311047">CAN_TSR_ABRQ0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga56679e8aea1650e19f2baf79b35be24f">CAN_TSR_ABRQ0_Pos</a>)</td></tr>
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<tr class="separator:gaa78f950ccfd5a5a906c03de00a311047"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdac6b87a303b0d0ec9b0d94a54ae31f" id="r_gafdac6b87a303b0d0ec9b0d94a54ae31f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdac6b87a303b0d0ec9b0d94a54ae31f">CAN_TSR_ABRQ0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa78f950ccfd5a5a906c03de00a311047">CAN_TSR_ABRQ0_Msk</a></td></tr>
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<tr class="separator:gafdac6b87a303b0d0ec9b0d94a54ae31f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd31c6bc75f595b504cc521280752259" id="r_gabd31c6bc75f595b504cc521280752259"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd31c6bc75f595b504cc521280752259">CAN_TSR_RQCP1_Pos</a>   (8U)</td></tr>
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<tr class="separator:gabd31c6bc75f595b504cc521280752259"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27fdee112d3e6e2b5f6bad6c9d95cb2b" id="r_ga27fdee112d3e6e2b5f6bad6c9d95cb2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27fdee112d3e6e2b5f6bad6c9d95cb2b">CAN_TSR_RQCP1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabd31c6bc75f595b504cc521280752259">CAN_TSR_RQCP1_Pos</a>)</td></tr>
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<tr class="separator:ga27fdee112d3e6e2b5f6bad6c9d95cb2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd3118dec59c3a45d2f262b090699538" id="r_gabd3118dec59c3a45d2f262b090699538"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd3118dec59c3a45d2f262b090699538">CAN_TSR_RQCP1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga27fdee112d3e6e2b5f6bad6c9d95cb2b">CAN_TSR_RQCP1_Msk</a></td></tr>
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<tr class="separator:gabd3118dec59c3a45d2f262b090699538"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabf7c2bb1371409780b6aa677d30505d" id="r_gaabf7c2bb1371409780b6aa677d30505d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabf7c2bb1371409780b6aa677d30505d">CAN_TSR_TXOK1_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaabf7c2bb1371409780b6aa677d30505d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d08d43b83ebfa8f93c1ac842ccb1e31" id="r_ga5d08d43b83ebfa8f93c1ac842ccb1e31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d08d43b83ebfa8f93c1ac842ccb1e31">CAN_TSR_TXOK1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaabf7c2bb1371409780b6aa677d30505d">CAN_TSR_TXOK1_Pos</a>)</td></tr>
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<tr class="separator:ga5d08d43b83ebfa8f93c1ac842ccb1e31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea918e510c5471b1ac797350b7950151" id="r_gaea918e510c5471b1ac797350b7950151"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea918e510c5471b1ac797350b7950151">CAN_TSR_TXOK1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5d08d43b83ebfa8f93c1ac842ccb1e31">CAN_TSR_TXOK1_Msk</a></td></tr>
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<tr class="separator:gaea918e510c5471b1ac797350b7950151"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3647d7d831be09723b38baaf9011fe0" id="r_gad3647d7d831be09723b38baaf9011fe0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3647d7d831be09723b38baaf9011fe0">CAN_TSR_ALST1_Pos</a>   (10U)</td></tr>
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<tr class="separator:gad3647d7d831be09723b38baaf9011fe0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ffcef1919cf06d2874bff8879d69c23" id="r_ga9ffcef1919cf06d2874bff8879d69c23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ffcef1919cf06d2874bff8879d69c23">CAN_TSR_ALST1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad3647d7d831be09723b38baaf9011fe0">CAN_TSR_ALST1_Pos</a>)</td></tr>
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<tr class="memitem:ga7a34d996177f23148c9b4cd6b0a80529" id="r_ga7a34d996177f23148c9b4cd6b0a80529"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a34d996177f23148c9b4cd6b0a80529">CAN_TSR_ALST1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ffcef1919cf06d2874bff8879d69c23">CAN_TSR_ALST1_Msk</a></td></tr>
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<tr class="separator:ga7a34d996177f23148c9b4cd6b0a80529"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c91415cb60af76367c9c03ddb9d1791" id="r_ga0c91415cb60af76367c9c03ddb9d1791"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c91415cb60af76367c9c03ddb9d1791">CAN_TSR_TERR1_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga0c91415cb60af76367c9c03ddb9d1791"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cd5d4653c34defa63b29c42292358dd" id="r_ga5cd5d4653c34defa63b29c42292358dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5cd5d4653c34defa63b29c42292358dd">CAN_TSR_TERR1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c91415cb60af76367c9c03ddb9d1791">CAN_TSR_TERR1_Pos</a>)</td></tr>
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<tr class="separator:ga5cd5d4653c34defa63b29c42292358dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b01eca562bdb60e5416840fca47fff6" id="r_ga9b01eca562bdb60e5416840fca47fff6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b01eca562bdb60e5416840fca47fff6">CAN_TSR_TERR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cd5d4653c34defa63b29c42292358dd">CAN_TSR_TERR1_Msk</a></td></tr>
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<tr class="memitem:ga2254de573340c2b341cecb12bb6ead4e" id="r_ga2254de573340c2b341cecb12bb6ead4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2254de573340c2b341cecb12bb6ead4e">CAN_TSR_ABRQ1_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga2254de573340c2b341cecb12bb6ead4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadca8d9c91c9b53a361a07cea552fe847" id="r_gadca8d9c91c9b53a361a07cea552fe847"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadca8d9c91c9b53a361a07cea552fe847">CAN_TSR_ABRQ1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2254de573340c2b341cecb12bb6ead4e">CAN_TSR_ABRQ1_Pos</a>)</td></tr>
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<tr class="separator:gadca8d9c91c9b53a361a07cea552fe847"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c44a4e585b3ab1c37a6c2c28c90d6cd" id="r_ga4c44a4e585b3ab1c37a6c2c28c90d6cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c44a4e585b3ab1c37a6c2c28c90d6cd">CAN_TSR_ABRQ1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadca8d9c91c9b53a361a07cea552fe847">CAN_TSR_ABRQ1_Msk</a></td></tr>
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<tr class="memitem:gac32ff69b06375749e0a00c17c010f1fe" id="r_gac32ff69b06375749e0a00c17c010f1fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac32ff69b06375749e0a00c17c010f1fe">CAN_TSR_RQCP2_Pos</a>   (16U)</td></tr>
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<tr class="separator:gac32ff69b06375749e0a00c17c010f1fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8137af39f29d789c1794527149da1e70" id="r_ga8137af39f29d789c1794527149da1e70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8137af39f29d789c1794527149da1e70">CAN_TSR_RQCP2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac32ff69b06375749e0a00c17c010f1fe">CAN_TSR_RQCP2_Pos</a>)</td></tr>
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<tr class="memitem:ga3cf9e83cec96164f1dadf4e43411ebf0" id="r_ga3cf9e83cec96164f1dadf4e43411ebf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cf9e83cec96164f1dadf4e43411ebf0">CAN_TSR_RQCP2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8137af39f29d789c1794527149da1e70">CAN_TSR_RQCP2_Msk</a></td></tr>
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<tr class="separator:ga3cf9e83cec96164f1dadf4e43411ebf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c1c09375222011c0dba1bdb1cf56fd2" id="r_ga5c1c09375222011c0dba1bdb1cf56fd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c1c09375222011c0dba1bdb1cf56fd2">CAN_TSR_TXOK2_Pos</a>   (17U)</td></tr>
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<tr class="memitem:gab26c50058879d92619cbc4bef2e9d492" id="r_gab26c50058879d92619cbc4bef2e9d492"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab26c50058879d92619cbc4bef2e9d492">CAN_TSR_TXOK2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c1c09375222011c0dba1bdb1cf56fd2">CAN_TSR_TXOK2_Pos</a>)</td></tr>
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<tr class="separator:gab26c50058879d92619cbc4bef2e9d492"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga782c591bb204d751b470dd53a37d240e" id="r_ga782c591bb204d751b470dd53a37d240e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga782c591bb204d751b470dd53a37d240e">CAN_TSR_TXOK2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab26c50058879d92619cbc4bef2e9d492">CAN_TSR_TXOK2_Msk</a></td></tr>
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<tr class="memitem:ga435fe7e72dd93d43d2a3f1bd89a89c44" id="r_ga435fe7e72dd93d43d2a3f1bd89a89c44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga435fe7e72dd93d43d2a3f1bd89a89c44">CAN_TSR_ALST2_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga435fe7e72dd93d43d2a3f1bd89a89c44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5a24da79f81578dafc2126d5f731d4a" id="r_gac5a24da79f81578dafc2126d5f731d4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5a24da79f81578dafc2126d5f731d4a">CAN_TSR_ALST2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga435fe7e72dd93d43d2a3f1bd89a89c44">CAN_TSR_ALST2_Pos</a>)</td></tr>
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<tr class="memitem:ga75db1172038ebd72db1ed2fedc6108ff" id="r_ga75db1172038ebd72db1ed2fedc6108ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75db1172038ebd72db1ed2fedc6108ff">CAN_TSR_ALST2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac5a24da79f81578dafc2126d5f731d4a">CAN_TSR_ALST2_Msk</a></td></tr>
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<tr class="memitem:ga99b204977a683ed30b391720352e3260" id="r_ga99b204977a683ed30b391720352e3260"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99b204977a683ed30b391720352e3260">CAN_TSR_TERR2_Pos</a>   (19U)</td></tr>
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<tr class="memitem:gabd1cf1551625e3972c4942983a394acc" id="r_gabd1cf1551625e3972c4942983a394acc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd1cf1551625e3972c4942983a394acc">CAN_TSR_TERR2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga99b204977a683ed30b391720352e3260">CAN_TSR_TERR2_Pos</a>)</td></tr>
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<tr class="memitem:ga26a85626eb26bf99413ba80c676d0af8" id="r_ga26a85626eb26bf99413ba80c676d0af8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26a85626eb26bf99413ba80c676d0af8">CAN_TSR_TERR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd1cf1551625e3972c4942983a394acc">CAN_TSR_TERR2_Msk</a></td></tr>
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<tr class="memitem:ga5ad0f8e1da30d1f2b0c6713ae0cc2793" id="r_ga5ad0f8e1da30d1f2b0c6713ae0cc2793"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ad0f8e1da30d1f2b0c6713ae0cc2793">CAN_TSR_ABRQ2_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga5ad0f8e1da30d1f2b0c6713ae0cc2793"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafba8518081068f7375284a1e07873417" id="r_gafba8518081068f7375284a1e07873417"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafba8518081068f7375284a1e07873417">CAN_TSR_ABRQ2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ad0f8e1da30d1f2b0c6713ae0cc2793">CAN_TSR_ABRQ2_Pos</a>)</td></tr>
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<tr class="memitem:ga2a3b7e4be7cebb35ad66cb85b82901bb" id="r_ga2a3b7e4be7cebb35ad66cb85b82901bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a3b7e4be7cebb35ad66cb85b82901bb">CAN_TSR_ABRQ2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafba8518081068f7375284a1e07873417">CAN_TSR_ABRQ2_Msk</a></td></tr>
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<tr class="separator:ga2a3b7e4be7cebb35ad66cb85b82901bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca63bcf7a21cf13d7fcd42d49ee2a59f" id="r_gaca63bcf7a21cf13d7fcd42d49ee2a59f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca63bcf7a21cf13d7fcd42d49ee2a59f">CAN_TSR_CODE_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaca63bcf7a21cf13d7fcd42d49ee2a59f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13f9f007576f8a12578052bdbd224681" id="r_ga13f9f007576f8a12578052bdbd224681"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13f9f007576f8a12578052bdbd224681">CAN_TSR_CODE_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaca63bcf7a21cf13d7fcd42d49ee2a59f">CAN_TSR_CODE_Pos</a>)</td></tr>
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<tr class="memitem:gac00145ea43822f362f3d473bba62fa13" id="r_gac00145ea43822f362f3d473bba62fa13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac00145ea43822f362f3d473bba62fa13">CAN_TSR_CODE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga13f9f007576f8a12578052bdbd224681">CAN_TSR_CODE_Msk</a></td></tr>
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<tr class="memitem:ga4348cbdeed004189582a35db2ff12d74" id="r_ga4348cbdeed004189582a35db2ff12d74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4348cbdeed004189582a35db2ff12d74">CAN_TSR_TME_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga4348cbdeed004189582a35db2ff12d74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga635aef2e8090ae256c1251a3a1736965" id="r_ga635aef2e8090ae256c1251a3a1736965"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga635aef2e8090ae256c1251a3a1736965">CAN_TSR_TME_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4348cbdeed004189582a35db2ff12d74">CAN_TSR_TME_Pos</a>)</td></tr>
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<tr class="memitem:ga61ab11e97b42c5210109516e30af9b05" id="r_ga61ab11e97b42c5210109516e30af9b05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61ab11e97b42c5210109516e30af9b05">CAN_TSR_TME</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga635aef2e8090ae256c1251a3a1736965">CAN_TSR_TME_Msk</a></td></tr>
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<tr class="memitem:ga37b566e4628d2f032e393c1b86748f2c" id="r_ga37b566e4628d2f032e393c1b86748f2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37b566e4628d2f032e393c1b86748f2c">CAN_TSR_TME0_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga37b566e4628d2f032e393c1b86748f2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga440056199033e966155a795be606acdc" id="r_ga440056199033e966155a795be606acdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga440056199033e966155a795be606acdc">CAN_TSR_TME0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga37b566e4628d2f032e393c1b86748f2c">CAN_TSR_TME0_Pos</a>)</td></tr>
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<tr class="separator:ga440056199033e966155a795be606acdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7500e491fe82e67ed5d40759e8a50f0" id="r_gad7500e491fe82e67ed5d40759e8a50f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7500e491fe82e67ed5d40759e8a50f0">CAN_TSR_TME0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga440056199033e966155a795be606acdc">CAN_TSR_TME0_Msk</a></td></tr>
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<tr class="separator:gad7500e491fe82e67ed5d40759e8a50f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad799e75ed3dad61e73e34781df0f87f2" id="r_gad799e75ed3dad61e73e34781df0f87f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad799e75ed3dad61e73e34781df0f87f2">CAN_TSR_TME1_Pos</a>   (27U)</td></tr>
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<tr class="separator:gad799e75ed3dad61e73e34781df0f87f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39fa95bef47ce6b3631b924d25556454" id="r_ga39fa95bef47ce6b3631b924d25556454"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39fa95bef47ce6b3631b924d25556454">CAN_TSR_TME1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad799e75ed3dad61e73e34781df0f87f2">CAN_TSR_TME1_Pos</a>)</td></tr>
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<tr class="separator:ga39fa95bef47ce6b3631b924d25556454"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ba2b51def4b1683fd050e43045306ea" id="r_ga5ba2b51def4b1683fd050e43045306ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ba2b51def4b1683fd050e43045306ea">CAN_TSR_TME1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga39fa95bef47ce6b3631b924d25556454">CAN_TSR_TME1_Msk</a></td></tr>
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<tr class="memitem:ga1884d523a48ffedf27bb137b34ac6c78" id="r_ga1884d523a48ffedf27bb137b34ac6c78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1884d523a48ffedf27bb137b34ac6c78">CAN_TSR_TME2_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga1884d523a48ffedf27bb137b34ac6c78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4977ccde238489d3291b2fe91434c713" id="r_ga4977ccde238489d3291b2fe91434c713"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4977ccde238489d3291b2fe91434c713">CAN_TSR_TME2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1884d523a48ffedf27bb137b34ac6c78">CAN_TSR_TME2_Pos</a>)</td></tr>
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<tr class="memitem:gaf6523fac51d3aed2e36de4c2f07c2a21" id="r_gaf6523fac51d3aed2e36de4c2f07c2a21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6523fac51d3aed2e36de4c2f07c2a21">CAN_TSR_TME2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4977ccde238489d3291b2fe91434c713">CAN_TSR_TME2_Msk</a></td></tr>
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<tr class="memitem:ga702291f34c1368501b753d7af3d553fe" id="r_ga702291f34c1368501b753d7af3d553fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga702291f34c1368501b753d7af3d553fe">CAN_TSR_LOW_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga702291f34c1368501b753d7af3d553fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd34530d99bc8ff61a5e6ce04caf7d67" id="r_gacd34530d99bc8ff61a5e6ce04caf7d67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd34530d99bc8ff61a5e6ce04caf7d67">CAN_TSR_LOW_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702291f34c1368501b753d7af3d553fe">CAN_TSR_LOW_Pos</a>)</td></tr>
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<tr class="separator:gacd34530d99bc8ff61a5e6ce04caf7d67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96c6453caa447cc4a9961d6ee5dea74e" id="r_ga96c6453caa447cc4a9961d6ee5dea74e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96c6453caa447cc4a9961d6ee5dea74e">CAN_TSR_LOW</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacd34530d99bc8ff61a5e6ce04caf7d67">CAN_TSR_LOW_Msk</a></td></tr>
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<tr class="memitem:gaca4490d8d7d5ccfdf3200cf4be7d6641" id="r_gaca4490d8d7d5ccfdf3200cf4be7d6641"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca4490d8d7d5ccfdf3200cf4be7d6641">CAN_TSR_LOW0_Pos</a>   (29U)</td></tr>
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<tr class="separator:gaca4490d8d7d5ccfdf3200cf4be7d6641"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ae04ec8ef32d4f5aa583628114cb54e" id="r_ga0ae04ec8ef32d4f5aa583628114cb54e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ae04ec8ef32d4f5aa583628114cb54e">CAN_TSR_LOW0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaca4490d8d7d5ccfdf3200cf4be7d6641">CAN_TSR_LOW0_Pos</a>)</td></tr>
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<tr class="memitem:ga79ff582efea1d7be2d1de7a1fd1a2b65" id="r_ga79ff582efea1d7be2d1de7a1fd1a2b65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79ff582efea1d7be2d1de7a1fd1a2b65">CAN_TSR_LOW0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ae04ec8ef32d4f5aa583628114cb54e">CAN_TSR_LOW0_Msk</a></td></tr>
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<tr class="memitem:ga6cb85fb2c45304df1a329b7d2320c511" id="r_ga6cb85fb2c45304df1a329b7d2320c511"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cb85fb2c45304df1a329b7d2320c511">CAN_TSR_LOW1_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga6cb85fb2c45304df1a329b7d2320c511"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b5f0c70b09a3395c07d6b2287210b7d" id="r_ga4b5f0c70b09a3395c07d6b2287210b7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b5f0c70b09a3395c07d6b2287210b7d">CAN_TSR_LOW1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cb85fb2c45304df1a329b7d2320c511">CAN_TSR_LOW1_Pos</a>)</td></tr>
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<tr class="memitem:gac1e550c2e6a5f8425322f9943fd7c7ed" id="r_gac1e550c2e6a5f8425322f9943fd7c7ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1e550c2e6a5f8425322f9943fd7c7ed">CAN_TSR_LOW1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b5f0c70b09a3395c07d6b2287210b7d">CAN_TSR_LOW1_Msk</a></td></tr>
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<tr class="memitem:gaa822557268b20255c2be98727a357202" id="r_gaa822557268b20255c2be98727a357202"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa822557268b20255c2be98727a357202">CAN_TSR_LOW2_Pos</a>   (31U)</td></tr>
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<tr class="memitem:ga987f19b94125300653186bb50bb43ca6" id="r_ga987f19b94125300653186bb50bb43ca6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga987f19b94125300653186bb50bb43ca6">CAN_TSR_LOW2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa822557268b20255c2be98727a357202">CAN_TSR_LOW2_Pos</a>)</td></tr>
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<tr class="memitem:gadd1db2c2ce76b732fdb71df65fb8124f" id="r_gadd1db2c2ce76b732fdb71df65fb8124f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd1db2c2ce76b732fdb71df65fb8124f">CAN_TSR_LOW2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga987f19b94125300653186bb50bb43ca6">CAN_TSR_LOW2_Msk</a></td></tr>
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<tr class="memitem:gab868d2c9f9b9e52d7d3b3e8227b8e862" id="r_gab868d2c9f9b9e52d7d3b3e8227b8e862"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab868d2c9f9b9e52d7d3b3e8227b8e862">CAN_RF0R_FMP0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab868d2c9f9b9e52d7d3b3e8227b8e862"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad74fc3f4e266805779daf7f69194bd97" id="r_gad74fc3f4e266805779daf7f69194bd97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad74fc3f4e266805779daf7f69194bd97">CAN_RF0R_FMP0_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab868d2c9f9b9e52d7d3b3e8227b8e862">CAN_RF0R_FMP0_Pos</a>)</td></tr>
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<tr class="separator:gad74fc3f4e266805779daf7f69194bd97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e23f3d7947e58531524d77b5c4741cc" id="r_ga9e23f3d7947e58531524d77b5c4741cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e23f3d7947e58531524d77b5c4741cc">CAN_RF0R_FMP0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad74fc3f4e266805779daf7f69194bd97">CAN_RF0R_FMP0_Msk</a></td></tr>
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<tr class="separator:ga9e23f3d7947e58531524d77b5c4741cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab168d7bfdd89ac5e7654804ff6c16d3" id="r_gaab168d7bfdd89ac5e7654804ff6c16d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab168d7bfdd89ac5e7654804ff6c16d3">CAN_RF0R_FULL0_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaab168d7bfdd89ac5e7654804ff6c16d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27305e8a2d6f381b6d0ff05d6d0c74ba" id="r_ga27305e8a2d6f381b6d0ff05d6d0c74ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27305e8a2d6f381b6d0ff05d6d0c74ba">CAN_RF0R_FULL0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab168d7bfdd89ac5e7654804ff6c16d3">CAN_RF0R_FULL0_Pos</a>)</td></tr>
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<tr class="separator:ga27305e8a2d6f381b6d0ff05d6d0c74ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae934674f6e22a758e430f32cfc386d70" id="r_gae934674f6e22a758e430f32cfc386d70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae934674f6e22a758e430f32cfc386d70">CAN_RF0R_FULL0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga27305e8a2d6f381b6d0ff05d6d0c74ba">CAN_RF0R_FULL0_Msk</a></td></tr>
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<tr class="separator:gae934674f6e22a758e430f32cfc386d70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0aad54077e9896ec6f7599d126e54e1" id="r_gae0aad54077e9896ec6f7599d126e54e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0aad54077e9896ec6f7599d126e54e1">CAN_RF0R_FOVR0_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae0aad54077e9896ec6f7599d126e54e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0699f23293ca0bc417c7c1a343f53ba" id="r_gaa0699f23293ca0bc417c7c1a343f53ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0699f23293ca0bc417c7c1a343f53ba">CAN_RF0R_FOVR0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae0aad54077e9896ec6f7599d126e54e1">CAN_RF0R_FOVR0_Pos</a>)</td></tr>
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<tr class="separator:gaa0699f23293ca0bc417c7c1a343f53ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a3d15b3abab8199c16e26a3dffdc8b8" id="r_ga2a3d15b3abab8199c16e26a3dffdc8b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a3d15b3abab8199c16e26a3dffdc8b8">CAN_RF0R_FOVR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0699f23293ca0bc417c7c1a343f53ba">CAN_RF0R_FOVR0_Msk</a></td></tr>
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<tr class="separator:ga2a3d15b3abab8199c16e26a3dffdc8b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae75e432559ee49ae55397f529f199ad0" id="r_gae75e432559ee49ae55397f529f199ad0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae75e432559ee49ae55397f529f199ad0">CAN_RF0R_RFOM0_Pos</a>   (5U)</td></tr>
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<tr class="separator:gae75e432559ee49ae55397f529f199ad0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3c768b2f6a6c8b8b434991528110467" id="r_gae3c768b2f6a6c8b8b434991528110467"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3c768b2f6a6c8b8b434991528110467">CAN_RF0R_RFOM0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae75e432559ee49ae55397f529f199ad0">CAN_RF0R_RFOM0_Pos</a>)</td></tr>
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<tr class="separator:gae3c768b2f6a6c8b8b434991528110467"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74d2db4b9b7d52712e47557dcc61964d" id="r_ga74d2db4b9b7d52712e47557dcc61964d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74d2db4b9b7d52712e47557dcc61964d">CAN_RF0R_RFOM0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3c768b2f6a6c8b8b434991528110467">CAN_RF0R_RFOM0_Msk</a></td></tr>
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<tr class="separator:ga74d2db4b9b7d52712e47557dcc61964d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00fcf8bdc5087d5ff6d55c5206b346f3" id="r_ga00fcf8bdc5087d5ff6d55c5206b346f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00fcf8bdc5087d5ff6d55c5206b346f3">CAN_RF1R_FMP1_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga00fcf8bdc5087d5ff6d55c5206b346f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b08002573d35c943f136ab6c667f363" id="r_ga2b08002573d35c943f136ab6c667f363"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b08002573d35c943f136ab6c667f363">CAN_RF1R_FMP1_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga00fcf8bdc5087d5ff6d55c5206b346f3">CAN_RF1R_FMP1_Pos</a>)</td></tr>
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<tr class="separator:ga2b08002573d35c943f136ab6c667f363"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f9254d05043df6f21bf96234a03f72f" id="r_ga8f9254d05043df6f21bf96234a03f72f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f9254d05043df6f21bf96234a03f72f">CAN_RF1R_FMP1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b08002573d35c943f136ab6c667f363">CAN_RF1R_FMP1_Msk</a></td></tr>
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<tr class="separator:ga8f9254d05043df6f21bf96234a03f72f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc6bab0544e01fcd1bcf0487139f729e" id="r_gadc6bab0544e01fcd1bcf0487139f729e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc6bab0544e01fcd1bcf0487139f729e">CAN_RF1R_FULL1_Pos</a>   (3U)</td></tr>
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<tr class="separator:gadc6bab0544e01fcd1bcf0487139f729e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0ac244ab1c525913bfcc3d03b9ab06f" id="r_gae0ac244ab1c525913bfcc3d03b9ab06f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0ac244ab1c525913bfcc3d03b9ab06f">CAN_RF1R_FULL1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadc6bab0544e01fcd1bcf0487139f729e">CAN_RF1R_FULL1_Pos</a>)</td></tr>
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<tr class="separator:gae0ac244ab1c525913bfcc3d03b9ab06f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdaa12fe4d14254cc4a6a4de749a7d0a" id="r_gabdaa12fe4d14254cc4a6a4de749a7d0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdaa12fe4d14254cc4a6a4de749a7d0a">CAN_RF1R_FULL1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae0ac244ab1c525913bfcc3d03b9ab06f">CAN_RF1R_FULL1_Msk</a></td></tr>
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<tr class="separator:gabdaa12fe4d14254cc4a6a4de749a7d0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9faad05fc13813a198405bb5f064fb05" id="r_ga9faad05fc13813a198405bb5f064fb05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9faad05fc13813a198405bb5f064fb05">CAN_RF1R_FOVR1_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga9faad05fc13813a198405bb5f064fb05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacee8c5b572eb85447912dcbc62aac97c" id="r_gacee8c5b572eb85447912dcbc62aac97c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacee8c5b572eb85447912dcbc62aac97c">CAN_RF1R_FOVR1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9faad05fc13813a198405bb5f064fb05">CAN_RF1R_FOVR1_Pos</a>)</td></tr>
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<tr class="separator:gacee8c5b572eb85447912dcbc62aac97c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5eeaabd4db3825bc53d860aca8d7590" id="r_gab5eeaabd4db3825bc53d860aca8d7590"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5eeaabd4db3825bc53d860aca8d7590">CAN_RF1R_FOVR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacee8c5b572eb85447912dcbc62aac97c">CAN_RF1R_FOVR1_Msk</a></td></tr>
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<tr class="separator:gab5eeaabd4db3825bc53d860aca8d7590"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2e95cc6d93830acc8669871fff26939" id="r_gaa2e95cc6d93830acc8669871fff26939"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2e95cc6d93830acc8669871fff26939">CAN_RF1R_RFOM1_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaa2e95cc6d93830acc8669871fff26939"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec98a01deaf5464a0ba9052a028bf483" id="r_gaec98a01deaf5464a0ba9052a028bf483"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec98a01deaf5464a0ba9052a028bf483">CAN_RF1R_RFOM1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2e95cc6d93830acc8669871fff26939">CAN_RF1R_RFOM1_Pos</a>)</td></tr>
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<tr class="separator:gaec98a01deaf5464a0ba9052a028bf483"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6930f860de4a90e3344e63fbc209b9ab" id="r_ga6930f860de4a90e3344e63fbc209b9ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6930f860de4a90e3344e63fbc209b9ab">CAN_RF1R_RFOM1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec98a01deaf5464a0ba9052a028bf483">CAN_RF1R_RFOM1_Msk</a></td></tr>
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<tr class="separator:ga6930f860de4a90e3344e63fbc209b9ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea8fc846d9892de7b30d31bdf6b54edb" id="r_gaea8fc846d9892de7b30d31bdf6b54edb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea8fc846d9892de7b30d31bdf6b54edb">CAN_IER_TMEIE_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaea8fc846d9892de7b30d31bdf6b54edb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac38696874c8fbbd05b6413ac11746d6b" id="r_gac38696874c8fbbd05b6413ac11746d6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac38696874c8fbbd05b6413ac11746d6b">CAN_IER_TMEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea8fc846d9892de7b30d31bdf6b54edb">CAN_IER_TMEIE_Pos</a>)</td></tr>
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<tr class="separator:gac38696874c8fbbd05b6413ac11746d6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe027af7acd051f5a52db78608a36e26" id="r_gafe027af7acd051f5a52db78608a36e26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe027af7acd051f5a52db78608a36e26">CAN_IER_TMEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac38696874c8fbbd05b6413ac11746d6b">CAN_IER_TMEIE_Msk</a></td></tr>
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<tr class="separator:gafe027af7acd051f5a52db78608a36e26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3325defd7e318b63baa1f78b50394280" id="r_ga3325defd7e318b63baa1f78b50394280"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3325defd7e318b63baa1f78b50394280">CAN_IER_FMPIE0_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga3325defd7e318b63baa1f78b50394280"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6885c5945dc4db64d46aa83bd8367e83" id="r_ga6885c5945dc4db64d46aa83bd8367e83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6885c5945dc4db64d46aa83bd8367e83">CAN_IER_FMPIE0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3325defd7e318b63baa1f78b50394280">CAN_IER_FMPIE0_Pos</a>)</td></tr>
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<tr class="separator:ga6885c5945dc4db64d46aa83bd8367e83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59eecd1bb7d1d0e17422a26ae89cf39d" id="r_ga59eecd1bb7d1d0e17422a26ae89cf39d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59eecd1bb7d1d0e17422a26ae89cf39d">CAN_IER_FMPIE0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6885c5945dc4db64d46aa83bd8367e83">CAN_IER_FMPIE0_Msk</a></td></tr>
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<tr class="separator:ga59eecd1bb7d1d0e17422a26ae89cf39d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga411ce03315531b3f90698b7e9224b93a" id="r_ga411ce03315531b3f90698b7e9224b93a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga411ce03315531b3f90698b7e9224b93a">CAN_IER_FFIE0_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga411ce03315531b3f90698b7e9224b93a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8885a2f34117d17dfb78fb78fb18b7a7" id="r_ga8885a2f34117d17dfb78fb78fb18b7a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8885a2f34117d17dfb78fb78fb18b7a7">CAN_IER_FFIE0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga411ce03315531b3f90698b7e9224b93a">CAN_IER_FFIE0_Pos</a>)</td></tr>
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<tr class="separator:ga8885a2f34117d17dfb78fb78fb18b7a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf926ae29d98a8b72ef48f001fda07fc3" id="r_gaf926ae29d98a8b72ef48f001fda07fc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf926ae29d98a8b72ef48f001fda07fc3">CAN_IER_FFIE0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8885a2f34117d17dfb78fb78fb18b7a7">CAN_IER_FFIE0_Msk</a></td></tr>
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<tr class="separator:gaf926ae29d98a8b72ef48f001fda07fc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7cded06b69c3ab261928a1b48ece5f9" id="r_gab7cded06b69c3ab261928a1b48ece5f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7cded06b69c3ab261928a1b48ece5f9">CAN_IER_FOVIE0_Pos</a>   (3U)</td></tr>
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<tr class="separator:gab7cded06b69c3ab261928a1b48ece5f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7859520258dfc8c61eca8da04ff180f9" id="r_ga7859520258dfc8c61eca8da04ff180f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7859520258dfc8c61eca8da04ff180f9">CAN_IER_FOVIE0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab7cded06b69c3ab261928a1b48ece5f9">CAN_IER_FOVIE0_Pos</a>)</td></tr>
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<tr class="separator:ga7859520258dfc8c61eca8da04ff180f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c423699fdcd2ddddb3046a368505679" id="r_ga0c423699fdcd2ddddb3046a368505679"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c423699fdcd2ddddb3046a368505679">CAN_IER_FOVIE0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7859520258dfc8c61eca8da04ff180f9">CAN_IER_FOVIE0_Msk</a></td></tr>
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<tr class="separator:ga0c423699fdcd2ddddb3046a368505679"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b904e14bd25a2d2e155364c2ebb5c7e" id="r_ga8b904e14bd25a2d2e155364c2ebb5c7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b904e14bd25a2d2e155364c2ebb5c7e">CAN_IER_FMPIE1_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga8b904e14bd25a2d2e155364c2ebb5c7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac66a68cb8bc52e699f9d83673515c3b9" id="r_gac66a68cb8bc52e699f9d83673515c3b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac66a68cb8bc52e699f9d83673515c3b9">CAN_IER_FMPIE1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b904e14bd25a2d2e155364c2ebb5c7e">CAN_IER_FMPIE1_Pos</a>)</td></tr>
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<tr class="separator:gac66a68cb8bc52e699f9d83673515c3b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b8492d1b8ce13fead7869a0e4ef39ed" id="r_ga4b8492d1b8ce13fead7869a0e4ef39ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b8492d1b8ce13fead7869a0e4ef39ed">CAN_IER_FMPIE1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac66a68cb8bc52e699f9d83673515c3b9">CAN_IER_FMPIE1_Msk</a></td></tr>
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<tr class="separator:ga4b8492d1b8ce13fead7869a0e4ef39ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0c5e16c335ad2459a1726d123b8f720" id="r_gae0c5e16c335ad2459a1726d123b8f720"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0c5e16c335ad2459a1726d123b8f720">CAN_IER_FFIE1_Pos</a>   (5U)</td></tr>
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<tr class="separator:gae0c5e16c335ad2459a1726d123b8f720"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20cba05b98222a9ce8bf5b5804c78ead" id="r_ga20cba05b98222a9ce8bf5b5804c78ead"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20cba05b98222a9ce8bf5b5804c78ead">CAN_IER_FFIE1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae0c5e16c335ad2459a1726d123b8f720">CAN_IER_FFIE1_Pos</a>)</td></tr>
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<tr class="separator:ga20cba05b98222a9ce8bf5b5804c78ead"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5a7e9d13e8d96bef2ac1972520b1c4f" id="r_gaf5a7e9d13e8d96bef2ac1972520b1c4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5a7e9d13e8d96bef2ac1972520b1c4f">CAN_IER_FFIE1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga20cba05b98222a9ce8bf5b5804c78ead">CAN_IER_FFIE1_Msk</a></td></tr>
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<tr class="separator:gaf5a7e9d13e8d96bef2ac1972520b1c4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga210db948ed64aa24bc8176041966f934" id="r_ga210db948ed64aa24bc8176041966f934"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga210db948ed64aa24bc8176041966f934">CAN_IER_FOVIE1_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga210db948ed64aa24bc8176041966f934"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0256723529d4c2adf64c0f5b6da56e7a" id="r_ga0256723529d4c2adf64c0f5b6da56e7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0256723529d4c2adf64c0f5b6da56e7a">CAN_IER_FOVIE1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga210db948ed64aa24bc8176041966f934">CAN_IER_FOVIE1_Pos</a>)</td></tr>
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<tr class="separator:ga0256723529d4c2adf64c0f5b6da56e7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3734d9bf5cd08ff219b2d8c2f8300dbf" id="r_ga3734d9bf5cd08ff219b2d8c2f8300dbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3734d9bf5cd08ff219b2d8c2f8300dbf">CAN_IER_FOVIE1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0256723529d4c2adf64c0f5b6da56e7a">CAN_IER_FOVIE1_Msk</a></td></tr>
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<tr class="separator:ga3734d9bf5cd08ff219b2d8c2f8300dbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ed2cabb36a1f1b250a8d344896b1c9c" id="r_ga5ed2cabb36a1f1b250a8d344896b1c9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ed2cabb36a1f1b250a8d344896b1c9c">CAN_IER_EWGIE_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga5ed2cabb36a1f1b250a8d344896b1c9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac15046ca7a384201773a9dfeb03deabc" id="r_gac15046ca7a384201773a9dfeb03deabc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac15046ca7a384201773a9dfeb03deabc">CAN_IER_EWGIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ed2cabb36a1f1b250a8d344896b1c9c">CAN_IER_EWGIE_Pos</a>)</td></tr>
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<tr class="separator:gac15046ca7a384201773a9dfeb03deabc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa80103eca53d74a2b047f761336918e3" id="r_gaa80103eca53d74a2b047f761336918e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa80103eca53d74a2b047f761336918e3">CAN_IER_EWGIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac15046ca7a384201773a9dfeb03deabc">CAN_IER_EWGIE_Msk</a></td></tr>
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<tr class="separator:gaa80103eca53d74a2b047f761336918e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9f52eb0782253e0623c7bdd27823743" id="r_gad9f52eb0782253e0623c7bdd27823743"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9f52eb0782253e0623c7bdd27823743">CAN_IER_EPVIE_Pos</a>   (9U)</td></tr>
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<tr class="separator:gad9f52eb0782253e0623c7bdd27823743"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gababf833052c2a6ffbd6ce2aa5960a61b" id="r_gababf833052c2a6ffbd6ce2aa5960a61b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gababf833052c2a6ffbd6ce2aa5960a61b">CAN_IER_EPVIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9f52eb0782253e0623c7bdd27823743">CAN_IER_EPVIE_Pos</a>)</td></tr>
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<tr class="separator:gababf833052c2a6ffbd6ce2aa5960a61b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e3307992cabee858287305a64e5031b" id="r_ga9e3307992cabee858287305a64e5031b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e3307992cabee858287305a64e5031b">CAN_IER_EPVIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gababf833052c2a6ffbd6ce2aa5960a61b">CAN_IER_EPVIE_Msk</a></td></tr>
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<tr class="separator:ga9e3307992cabee858287305a64e5031b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa110152ba07d311efc4c513a0e39eb4" id="r_gafa110152ba07d311efc4c513a0e39eb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa110152ba07d311efc4c513a0e39eb4">CAN_IER_BOFIE_Pos</a>   (10U)</td></tr>
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<tr class="separator:gafa110152ba07d311efc4c513a0e39eb4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga748f02d794157dc9684f6c15096d4e75" id="r_ga748f02d794157dc9684f6c15096d4e75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga748f02d794157dc9684f6c15096d4e75">CAN_IER_BOFIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafa110152ba07d311efc4c513a0e39eb4">CAN_IER_BOFIE_Pos</a>)</td></tr>
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<tr class="separator:ga748f02d794157dc9684f6c15096d4e75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d953fd5b625af04f95f5414259769ef" id="r_ga7d953fd5b625af04f95f5414259769ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d953fd5b625af04f95f5414259769ef">CAN_IER_BOFIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga748f02d794157dc9684f6c15096d4e75">CAN_IER_BOFIE_Msk</a></td></tr>
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<tr class="separator:ga7d953fd5b625af04f95f5414259769ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ccd7e2e333c2dae013674b5bac0ecbc" id="r_ga4ccd7e2e333c2dae013674b5bac0ecbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ccd7e2e333c2dae013674b5bac0ecbc">CAN_IER_LECIE_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga4ccd7e2e333c2dae013674b5bac0ecbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga386f61a3f7ef21600969ef0c936e255c" id="r_ga386f61a3f7ef21600969ef0c936e255c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga386f61a3f7ef21600969ef0c936e255c">CAN_IER_LECIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ccd7e2e333c2dae013674b5bac0ecbc">CAN_IER_LECIE_Pos</a>)</td></tr>
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<tr class="separator:ga386f61a3f7ef21600969ef0c936e255c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81514ecf1b6596e9930906779c4bdf39" id="r_ga81514ecf1b6596e9930906779c4bdf39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81514ecf1b6596e9930906779c4bdf39">CAN_IER_LECIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga386f61a3f7ef21600969ef0c936e255c">CAN_IER_LECIE_Msk</a></td></tr>
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<tr class="separator:ga81514ecf1b6596e9930906779c4bdf39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5a98a5d7ea27cfd207b83364fb3b8e2" id="r_gaf5a98a5d7ea27cfd207b83364fb3b8e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5a98a5d7ea27cfd207b83364fb3b8e2">CAN_IER_ERRIE_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaf5a98a5d7ea27cfd207b83364fb3b8e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3df7133242e3ff1636bb946649faa8d0" id="r_ga3df7133242e3ff1636bb946649faa8d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3df7133242e3ff1636bb946649faa8d0">CAN_IER_ERRIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5a98a5d7ea27cfd207b83364fb3b8e2">CAN_IER_ERRIE_Pos</a>)</td></tr>
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<tr class="separator:ga3df7133242e3ff1636bb946649faa8d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga962968c3ee1f70c714a5b12442369d9a" id="r_ga962968c3ee1f70c714a5b12442369d9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga962968c3ee1f70c714a5b12442369d9a">CAN_IER_ERRIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3df7133242e3ff1636bb946649faa8d0">CAN_IER_ERRIE_Msk</a></td></tr>
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<tr class="separator:ga962968c3ee1f70c714a5b12442369d9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf233f7c7c686ed81c4bc295143eb3a4b" id="r_gaf233f7c7c686ed81c4bc295143eb3a4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf233f7c7c686ed81c4bc295143eb3a4b">CAN_IER_WKUIE_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaf233f7c7c686ed81c4bc295143eb3a4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga181d122c65769851c2cc82f4bd764d80" id="r_ga181d122c65769851c2cc82f4bd764d80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga181d122c65769851c2cc82f4bd764d80">CAN_IER_WKUIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf233f7c7c686ed81c4bc295143eb3a4b">CAN_IER_WKUIE_Pos</a>)</td></tr>
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<tr class="separator:ga181d122c65769851c2cc82f4bd764d80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37f3438e80288c1791de27042df9838e" id="r_ga37f3438e80288c1791de27042df9838e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37f3438e80288c1791de27042df9838e">CAN_IER_WKUIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga181d122c65769851c2cc82f4bd764d80">CAN_IER_WKUIE_Msk</a></td></tr>
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<tr class="separator:ga37f3438e80288c1791de27042df9838e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa7b49f18204d00911b39f940b63e0f3" id="r_gafa7b49f18204d00911b39f940b63e0f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa7b49f18204d00911b39f940b63e0f3">CAN_IER_SLKIE_Pos</a>   (17U)</td></tr>
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<tr class="separator:gafa7b49f18204d00911b39f940b63e0f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf34b93be0df4cfdaad8dbb99f4fa1bc7" id="r_gaf34b93be0df4cfdaad8dbb99f4fa1bc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf34b93be0df4cfdaad8dbb99f4fa1bc7">CAN_IER_SLKIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafa7b49f18204d00911b39f940b63e0f3">CAN_IER_SLKIE_Pos</a>)</td></tr>
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<tr class="memitem:ga82389b79f21410f5d5f6bef38d192812" id="r_ga82389b79f21410f5d5f6bef38d192812"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82389b79f21410f5d5f6bef38d192812">CAN_IER_SLKIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf34b93be0df4cfdaad8dbb99f4fa1bc7">CAN_IER_SLKIE_Msk</a></td></tr>
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<tr class="memitem:ga5ed2cabb36a1f1b250a8d344896b1c9c" id="r_ga5ed2cabb36a1f1b250a8d344896b1c9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ed2cabb36a1f1b250a8d344896b1c9c">CAN_IER_EWGIE_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gaecadeaf7d9cadf19529cab6314ccc5e6" id="r_gaecadeaf7d9cadf19529cab6314ccc5e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecadeaf7d9cadf19529cab6314ccc5e6">CAN_ESR_EWGF_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gaace0e3b331bea3a3f35a3bdf88a40b86" id="r_gaace0e3b331bea3a3f35a3bdf88a40b86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaace0e3b331bea3a3f35a3bdf88a40b86">CAN_ESR_EWGF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaecadeaf7d9cadf19529cab6314ccc5e6">CAN_ESR_EWGF_Pos</a>)</td></tr>
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<tr class="memitem:ga2c0c02829fb41ac2a1b1852c19931de8" id="r_ga2c0c02829fb41ac2a1b1852c19931de8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c0c02829fb41ac2a1b1852c19931de8">CAN_ESR_EWGF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaace0e3b331bea3a3f35a3bdf88a40b86">CAN_ESR_EWGF_Msk</a></td></tr>
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<tr class="memitem:ga6c53494946cb6ee312e947da2e4329b6" id="r_ga6c53494946cb6ee312e947da2e4329b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c53494946cb6ee312e947da2e4329b6">CAN_ESR_EPVF_Pos</a>   (1U)</td></tr>
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<tr class="memitem:gab80e2d629b9aaf329dee50e9e4ee4a3e" id="r_gab80e2d629b9aaf329dee50e9e4ee4a3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab80e2d629b9aaf329dee50e9e4ee4a3e">CAN_ESR_EPVF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c53494946cb6ee312e947da2e4329b6">CAN_ESR_EPVF_Pos</a>)</td></tr>
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<tr class="memitem:ga633c961d528cbf8093b0e05e92225ff0" id="r_ga633c961d528cbf8093b0e05e92225ff0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga633c961d528cbf8093b0e05e92225ff0">CAN_ESR_EPVF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab80e2d629b9aaf329dee50e9e4ee4a3e">CAN_ESR_EPVF_Msk</a></td></tr>
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<tr class="memitem:gabe022d4e68fb0eca8278904fcfe3c783" id="r_gabe022d4e68fb0eca8278904fcfe3c783"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe022d4e68fb0eca8278904fcfe3c783">CAN_ESR_BOFF_Pos</a>   (2U)</td></tr>
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<tr class="memitem:gaa6607245f6b97f83691b9f9d9a3cf592" id="r_gaa6607245f6b97f83691b9f9d9a3cf592"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6607245f6b97f83691b9f9d9a3cf592">CAN_ESR_BOFF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabe022d4e68fb0eca8278904fcfe3c783">CAN_ESR_BOFF_Pos</a>)</td></tr>
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<tr class="memitem:ga619d49f67f1835a7efc457205fea1225" id="r_ga619d49f67f1835a7efc457205fea1225"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga619d49f67f1835a7efc457205fea1225">CAN_ESR_BOFF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6607245f6b97f83691b9f9d9a3cf592">CAN_ESR_BOFF_Msk</a></td></tr>
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<tr class="memitem:ga0d2dfedaf48ce2f4787afd43cad691bf" id="r_ga0d2dfedaf48ce2f4787afd43cad691bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d2dfedaf48ce2f4787afd43cad691bf">CAN_ESR_LEC_Pos</a>   (4U)</td></tr>
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<tr class="memitem:gad88ad0a905fbbe60fa2900f2cec42f5c" id="r_gad88ad0a905fbbe60fa2900f2cec42f5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad88ad0a905fbbe60fa2900f2cec42f5c">CAN_ESR_LEC_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d2dfedaf48ce2f4787afd43cad691bf">CAN_ESR_LEC_Pos</a>)</td></tr>
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<tr class="memitem:gab9f86741dd89034900e300499ae2272e" id="r_gab9f86741dd89034900e300499ae2272e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9f86741dd89034900e300499ae2272e">CAN_ESR_LEC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad88ad0a905fbbe60fa2900f2cec42f5c">CAN_ESR_LEC_Msk</a></td></tr>
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<tr class="memitem:ga054ebb41578d890d4d9dffb4828f02e7" id="r_ga054ebb41578d890d4d9dffb4828f02e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga054ebb41578d890d4d9dffb4828f02e7">CAN_ESR_LEC_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d2dfedaf48ce2f4787afd43cad691bf">CAN_ESR_LEC_Pos</a>)</td></tr>
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<tr class="memitem:gae570e9ba39dbe11808db929392250cf4" id="r_gae570e9ba39dbe11808db929392250cf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae570e9ba39dbe11808db929392250cf4">CAN_ESR_LEC_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d2dfedaf48ce2f4787afd43cad691bf">CAN_ESR_LEC_Pos</a>)</td></tr>
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<tr class="memitem:ga4998e7bfd002999413c68107911c6e8c" id="r_ga4998e7bfd002999413c68107911c6e8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4998e7bfd002999413c68107911c6e8c">CAN_ESR_LEC_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d2dfedaf48ce2f4787afd43cad691bf">CAN_ESR_LEC_Pos</a>)</td></tr>
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<tr class="separator:ga4998e7bfd002999413c68107911c6e8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11fde56e8a41fc98f69d84636121a361" id="r_ga11fde56e8a41fc98f69d84636121a361"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11fde56e8a41fc98f69d84636121a361">CAN_ESR_TEC_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga56c7759712292904bf0d15c2d968bbad" id="r_ga56c7759712292904bf0d15c2d968bbad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56c7759712292904bf0d15c2d968bbad">CAN_ESR_TEC_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11fde56e8a41fc98f69d84636121a361">CAN_ESR_TEC_Pos</a>)</td></tr>
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<tr class="memitem:gae3de2080f48cc851c20d920acfd1737d" id="r_gae3de2080f48cc851c20d920acfd1737d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3de2080f48cc851c20d920acfd1737d">CAN_ESR_TEC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga56c7759712292904bf0d15c2d968bbad">CAN_ESR_TEC_Msk</a></td></tr>
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<tr class="memitem:ga804f28bce21721cd4e9fcabf772f0f9d" id="r_ga804f28bce21721cd4e9fcabf772f0f9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga804f28bce21721cd4e9fcabf772f0f9d">CAN_ESR_REC_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga804f28bce21721cd4e9fcabf772f0f9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0143dc7eea1099168ef7fef24192949e" id="r_ga0143dc7eea1099168ef7fef24192949e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0143dc7eea1099168ef7fef24192949e">CAN_ESR_REC_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga804f28bce21721cd4e9fcabf772f0f9d">CAN_ESR_REC_Pos</a>)</td></tr>
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<tr class="memitem:ga0df5b2ea3f419182e9bd885f55ee5dc9" id="r_ga0df5b2ea3f419182e9bd885f55ee5dc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0df5b2ea3f419182e9bd885f55ee5dc9">CAN_ESR_REC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0143dc7eea1099168ef7fef24192949e">CAN_ESR_REC_Msk</a></td></tr>
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<tr class="memitem:gac3a0f2dc6767c5297f2f3475fdea8bef" id="r_gac3a0f2dc6767c5297f2f3475fdea8bef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3a0f2dc6767c5297f2f3475fdea8bef">CAN_BTR_BRP_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac3a0f2dc6767c5297f2f3475fdea8bef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad530ac34faa377b770d56624f009934d" id="r_gad530ac34faa377b770d56624f009934d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad530ac34faa377b770d56624f009934d">CAN_BTR_BRP_Msk</a>   (0x3FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3a0f2dc6767c5297f2f3475fdea8bef">CAN_BTR_BRP_Pos</a>)</td></tr>
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<tr class="memitem:ga96a5522b4c06551856f7185bdd448b02" id="r_ga96a5522b4c06551856f7185bdd448b02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96a5522b4c06551856f7185bdd448b02">CAN_BTR_BRP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad530ac34faa377b770d56624f009934d">CAN_BTR_BRP_Msk</a></td></tr>
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<tr class="separator:ga96a5522b4c06551856f7185bdd448b02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac00e3a010662ce93bd9e67f340bd2646" id="r_gac00e3a010662ce93bd9e67f340bd2646"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac00e3a010662ce93bd9e67f340bd2646">CAN_BTR_TS1_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gaf97266c03c918c7ff4a0d90b9f80b4f2" id="r_gaf97266c03c918c7ff4a0d90b9f80b4f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf97266c03c918c7ff4a0d90b9f80b4f2">CAN_BTR_TS1_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac00e3a010662ce93bd9e67f340bd2646">CAN_BTR_TS1_Pos</a>)</td></tr>
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<tr class="memitem:ga4d7ae8f06f8fbbf5dcfbbbb887057be9" id="r_ga4d7ae8f06f8fbbf5dcfbbbb887057be9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d7ae8f06f8fbbf5dcfbbbb887057be9">CAN_BTR_TS1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf97266c03c918c7ff4a0d90b9f80b4f2">CAN_BTR_TS1_Msk</a></td></tr>
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<tr class="separator:ga4d7ae8f06f8fbbf5dcfbbbb887057be9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga164ffd2240a76982894ce41143a12d82" id="r_ga164ffd2240a76982894ce41143a12d82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga164ffd2240a76982894ce41143a12d82">CAN_BTR_TS1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac00e3a010662ce93bd9e67f340bd2646">CAN_BTR_TS1_Pos</a>)</td></tr>
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<tr class="memitem:gae4365204ebb29eb5595027a4ee9c5f0d" id="r_gae4365204ebb29eb5595027a4ee9c5f0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4365204ebb29eb5595027a4ee9c5f0d">CAN_BTR_TS1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac00e3a010662ce93bd9e67f340bd2646">CAN_BTR_TS1_Pos</a>)</td></tr>
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<tr class="memitem:ga43dc43f11ee173cf07f77aa6e41f1275" id="r_ga43dc43f11ee173cf07f77aa6e41f1275"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43dc43f11ee173cf07f77aa6e41f1275">CAN_BTR_TS1_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac00e3a010662ce93bd9e67f340bd2646">CAN_BTR_TS1_Pos</a>)</td></tr>
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<tr class="memitem:ga7a5cd639329fe3eef8cde846247a4be9" id="r_ga7a5cd639329fe3eef8cde846247a4be9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a5cd639329fe3eef8cde846247a4be9">CAN_BTR_TS1_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac00e3a010662ce93bd9e67f340bd2646">CAN_BTR_TS1_Pos</a>)</td></tr>
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<tr class="memitem:gac80e236530969bf1f520e8e0dd7b7e79" id="r_gac80e236530969bf1f520e8e0dd7b7e79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac80e236530969bf1f520e8e0dd7b7e79">CAN_BTR_TS2_Pos</a>   (20U)</td></tr>
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<tr class="separator:gac80e236530969bf1f520e8e0dd7b7e79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7c657a3c97363915a9d739defa0f516" id="r_gaf7c657a3c97363915a9d739defa0f516"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7c657a3c97363915a9d739defa0f516">CAN_BTR_TS2_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac80e236530969bf1f520e8e0dd7b7e79">CAN_BTR_TS2_Pos</a>)</td></tr>
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<tr class="separator:gaf7c657a3c97363915a9d739defa0f516"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac006aa2ab26c50227ccaa18e0a79bff3" id="r_gac006aa2ab26c50227ccaa18e0a79bff3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac006aa2ab26c50227ccaa18e0a79bff3">CAN_BTR_TS2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7c657a3c97363915a9d739defa0f516">CAN_BTR_TS2_Msk</a></td></tr>
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<tr class="separator:gac006aa2ab26c50227ccaa18e0a79bff3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee307fe50e8d3cfdc9513da803808880" id="r_gaee307fe50e8d3cfdc9513da803808880"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee307fe50e8d3cfdc9513da803808880">CAN_BTR_TS2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac80e236530969bf1f520e8e0dd7b7e79">CAN_BTR_TS2_Pos</a>)</td></tr>
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<tr class="memitem:ga33265730e1d25198d9fb4347bdce8019" id="r_ga33265730e1d25198d9fb4347bdce8019"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33265730e1d25198d9fb4347bdce8019">CAN_BTR_TS2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac80e236530969bf1f520e8e0dd7b7e79">CAN_BTR_TS2_Pos</a>)</td></tr>
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<tr class="separator:ga33265730e1d25198d9fb4347bdce8019"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac4720d91283fc1fc74c1f0baaa8a3da" id="r_gaac4720d91283fc1fc74c1f0baaa8a3da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac4720d91283fc1fc74c1f0baaa8a3da">CAN_BTR_TS2_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac80e236530969bf1f520e8e0dd7b7e79">CAN_BTR_TS2_Pos</a>)</td></tr>
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<tr class="separator:gaac4720d91283fc1fc74c1f0baaa8a3da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cc4270d185b17bd0ce09ebb14c30121" id="r_ga6cc4270d185b17bd0ce09ebb14c30121"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cc4270d185b17bd0ce09ebb14c30121">CAN_BTR_SJW_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga6cc4270d185b17bd0ce09ebb14c30121"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaddf7f2fb84354e7e4756bdc25569d6cc" id="r_gaddf7f2fb84354e7e4756bdc25569d6cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddf7f2fb84354e7e4756bdc25569d6cc">CAN_BTR_SJW_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cc4270d185b17bd0ce09ebb14c30121">CAN_BTR_SJW_Pos</a>)</td></tr>
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<tr class="separator:gaddf7f2fb84354e7e4756bdc25569d6cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04c8b91ddacdcbb779bae42398c94cf2" id="r_ga04c8b91ddacdcbb779bae42398c94cf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04c8b91ddacdcbb779bae42398c94cf2">CAN_BTR_SJW</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaddf7f2fb84354e7e4756bdc25569d6cc">CAN_BTR_SJW_Msk</a></td></tr>
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<tr class="separator:ga04c8b91ddacdcbb779bae42398c94cf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08ae9e8258ef5c241733f6d58eb2a4e4" id="r_ga08ae9e8258ef5c241733f6d58eb2a4e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08ae9e8258ef5c241733f6d58eb2a4e4">CAN_BTR_SJW_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cc4270d185b17bd0ce09ebb14c30121">CAN_BTR_SJW_Pos</a>)</td></tr>
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<tr class="separator:ga08ae9e8258ef5c241733f6d58eb2a4e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8178f0abe0f854f4503ded1ad1adb531" id="r_ga8178f0abe0f854f4503ded1ad1adb531"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8178f0abe0f854f4503ded1ad1adb531">CAN_BTR_SJW_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cc4270d185b17bd0ce09ebb14c30121">CAN_BTR_SJW_Pos</a>)</td></tr>
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<tr class="separator:ga8178f0abe0f854f4503ded1ad1adb531"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d6dac3caae5bf3f69716d7417e920d7" id="r_ga4d6dac3caae5bf3f69716d7417e920d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d6dac3caae5bf3f69716d7417e920d7">CAN_BTR_LBKM_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga4d6dac3caae5bf3f69716d7417e920d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa32a82ff55c8008f4c0a1e16c0492d6c" id="r_gaa32a82ff55c8008f4c0a1e16c0492d6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa32a82ff55c8008f4c0a1e16c0492d6c">CAN_BTR_LBKM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d6dac3caae5bf3f69716d7417e920d7">CAN_BTR_LBKM_Pos</a>)</td></tr>
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<tr class="separator:gaa32a82ff55c8008f4c0a1e16c0492d6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6c0a81d8dcde61a1f2772232f5343b8" id="r_gac6c0a81d8dcde61a1f2772232f5343b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6c0a81d8dcde61a1f2772232f5343b8">CAN_BTR_LBKM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa32a82ff55c8008f4c0a1e16c0492d6c">CAN_BTR_LBKM_Msk</a></td></tr>
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<tr class="separator:gac6c0a81d8dcde61a1f2772232f5343b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac19407ed54b60ae709840db37855a0a4" id="r_gac19407ed54b60ae709840db37855a0a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac19407ed54b60ae709840db37855a0a4">CAN_BTR_SILM_Pos</a>   (31U)</td></tr>
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<tr class="separator:gac19407ed54b60ae709840db37855a0a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a7f4e5e22b9959994c790ac9c7f03d3" id="r_ga8a7f4e5e22b9959994c790ac9c7f03d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a7f4e5e22b9959994c790ac9c7f03d3">CAN_BTR_SILM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac19407ed54b60ae709840db37855a0a4">CAN_BTR_SILM_Pos</a>)</td></tr>
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<tr class="separator:ga8a7f4e5e22b9959994c790ac9c7f03d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa36bc23e833190cbee9b8cf5cf49159d" id="r_gaa36bc23e833190cbee9b8cf5cf49159d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa36bc23e833190cbee9b8cf5cf49159d">CAN_BTR_SILM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a7f4e5e22b9959994c790ac9c7f03d3">CAN_BTR_SILM_Msk</a></td></tr>
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<tr class="separator:gaa36bc23e833190cbee9b8cf5cf49159d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga255ce6dd558937c9b33efa43d01b7029" id="r_ga255ce6dd558937c9b33efa43d01b7029"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga255ce6dd558937c9b33efa43d01b7029">CAN_TI0R_TXRQ_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga255ce6dd558937c9b33efa43d01b7029"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53cf2d76df5b85e7363ca6fb45e71c4a" id="r_ga53cf2d76df5b85e7363ca6fb45e71c4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53cf2d76df5b85e7363ca6fb45e71c4a">CAN_TI0R_TXRQ_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga255ce6dd558937c9b33efa43d01b7029">CAN_TI0R_TXRQ_Pos</a>)</td></tr>
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<tr class="separator:ga53cf2d76df5b85e7363ca6fb45e71c4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b79cbb7ebb7f3419aa6ac04bd76899a" id="r_ga7b79cbb7ebb7f3419aa6ac04bd76899a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b79cbb7ebb7f3419aa6ac04bd76899a">CAN_TI0R_TXRQ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga53cf2d76df5b85e7363ca6fb45e71c4a">CAN_TI0R_TXRQ_Msk</a></td></tr>
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<tr class="separator:ga7b79cbb7ebb7f3419aa6ac04bd76899a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98b5217c83959ca007cb09ba59f1c182" id="r_ga98b5217c83959ca007cb09ba59f1c182"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98b5217c83959ca007cb09ba59f1c182">CAN_TI0R_RTR_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga98b5217c83959ca007cb09ba59f1c182"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab713759c47fadc25119dd265c413f771" id="r_gab713759c47fadc25119dd265c413f771"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab713759c47fadc25119dd265c413f771">CAN_TI0R_RTR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98b5217c83959ca007cb09ba59f1c182">CAN_TI0R_RTR_Pos</a>)</td></tr>
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<tr class="separator:gab713759c47fadc25119dd265c413f771"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5556f2ceb5b71b8afa76a18a31cbb6a" id="r_gad5556f2ceb5b71b8afa76a18a31cbb6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5556f2ceb5b71b8afa76a18a31cbb6a">CAN_TI0R_RTR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab713759c47fadc25119dd265c413f771">CAN_TI0R_RTR_Msk</a></td></tr>
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<tr class="separator:gad5556f2ceb5b71b8afa76a18a31cbb6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10b3ea5dc6c4d2f6d3925debfc2ba267" id="r_ga10b3ea5dc6c4d2f6d3925debfc2ba267"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10b3ea5dc6c4d2f6d3925debfc2ba267">CAN_TI0R_IDE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga10b3ea5dc6c4d2f6d3925debfc2ba267"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga080d97de6d25618d06b2d0a453c692b6" id="r_ga080d97de6d25618d06b2d0a453c692b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga080d97de6d25618d06b2d0a453c692b6">CAN_TI0R_IDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga10b3ea5dc6c4d2f6d3925debfc2ba267">CAN_TI0R_IDE_Pos</a>)</td></tr>
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<tr class="separator:ga080d97de6d25618d06b2d0a453c692b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06f761a877f8ad39f878284f69119c0b" id="r_ga06f761a877f8ad39f878284f69119c0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06f761a877f8ad39f878284f69119c0b">CAN_TI0R_IDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga080d97de6d25618d06b2d0a453c692b6">CAN_TI0R_IDE_Msk</a></td></tr>
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<tr class="separator:ga06f761a877f8ad39f878284f69119c0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4e738c64e396face3bbc9c5011e6b0e" id="r_gae4e738c64e396face3bbc9c5011e6b0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4e738c64e396face3bbc9c5011e6b0e">CAN_TI0R_EXID_Pos</a>   (3U)</td></tr>
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<tr class="separator:gae4e738c64e396face3bbc9c5011e6b0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2138165e39efac11d31381e1d7c72bfa" id="r_ga2138165e39efac11d31381e1d7c72bfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2138165e39efac11d31381e1d7c72bfa">CAN_TI0R_EXID_Msk</a>   (0x3FFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4e738c64e396face3bbc9c5011e6b0e">CAN_TI0R_EXID_Pos</a>)</td></tr>
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<tr class="separator:ga2138165e39efac11d31381e1d7c72bfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga894df6ad0d2976fe643dcb77052672f5" id="r_ga894df6ad0d2976fe643dcb77052672f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga894df6ad0d2976fe643dcb77052672f5">CAN_TI0R_EXID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2138165e39efac11d31381e1d7c72bfa">CAN_TI0R_EXID_Msk</a></td></tr>
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<tr class="separator:ga894df6ad0d2976fe643dcb77052672f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9e827ddbaa36f5651329cc61375221f" id="r_gab9e827ddbaa36f5651329cc61375221f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9e827ddbaa36f5651329cc61375221f">CAN_TI0R_STID_Pos</a>   (21U)</td></tr>
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<tr class="separator:gab9e827ddbaa36f5651329cc61375221f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4b180d9e1ecf00b104d18670496a8db" id="r_gad4b180d9e1ecf00b104d18670496a8db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4b180d9e1ecf00b104d18670496a8db">CAN_TI0R_STID_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9e827ddbaa36f5651329cc61375221f">CAN_TI0R_STID_Pos</a>)</td></tr>
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<tr class="separator:gad4b180d9e1ecf00b104d18670496a8db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d3b5882e1f9f76f5cfebffb5bc2f717" id="r_ga4d3b5882e1f9f76f5cfebffb5bc2f717"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d3b5882e1f9f76f5cfebffb5bc2f717">CAN_TI0R_STID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad4b180d9e1ecf00b104d18670496a8db">CAN_TI0R_STID_Msk</a></td></tr>
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<tr class="memitem:ga4ba7824b92498610f685f712c1075702" id="r_ga4ba7824b92498610f685f712c1075702"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ba7824b92498610f685f712c1075702">CAN_TDT0R_DLC_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga06a3a47edaaf175482a18feccbce3a61" id="r_ga06a3a47edaaf175482a18feccbce3a61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06a3a47edaaf175482a18feccbce3a61">CAN_TDT0R_DLC_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ba7824b92498610f685f712c1075702">CAN_TDT0R_DLC_Pos</a>)</td></tr>
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<tr class="memitem:gacf812eaee11f12863773b3f8e95ae6e2" id="r_gacf812eaee11f12863773b3f8e95ae6e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf812eaee11f12863773b3f8e95ae6e2">CAN_TDT0R_DLC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06a3a47edaaf175482a18feccbce3a61">CAN_TDT0R_DLC_Msk</a></td></tr>
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<tr class="separator:gacf812eaee11f12863773b3f8e95ae6e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac770efaeca5e93c9dbde1fa508ab79aa" id="r_gac770efaeca5e93c9dbde1fa508ab79aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac770efaeca5e93c9dbde1fa508ab79aa">CAN_TDT0R_TGT_Pos</a>   (8U)</td></tr>
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<tr class="separator:gac770efaeca5e93c9dbde1fa508ab79aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga394785c0a3d16b48d7bbcc524d2821a3" id="r_ga394785c0a3d16b48d7bbcc524d2821a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga394785c0a3d16b48d7bbcc524d2821a3">CAN_TDT0R_TGT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac770efaeca5e93c9dbde1fa508ab79aa">CAN_TDT0R_TGT_Pos</a>)</td></tr>
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<tr class="separator:ga394785c0a3d16b48d7bbcc524d2821a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2d329960b527a62fab099a084bfa906" id="r_gad2d329960b527a62fab099a084bfa906"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2d329960b527a62fab099a084bfa906">CAN_TDT0R_TGT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga394785c0a3d16b48d7bbcc524d2821a3">CAN_TDT0R_TGT_Msk</a></td></tr>
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<tr class="separator:gad2d329960b527a62fab099a084bfa906"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ffd9f8d93bb7f96dfc8f2b202986ec5" id="r_ga5ffd9f8d93bb7f96dfc8f2b202986ec5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ffd9f8d93bb7f96dfc8f2b202986ec5">CAN_TDT0R_TIME_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga544adf091e79aa36d9d7a6e47bafcb41" id="r_ga544adf091e79aa36d9d7a6e47bafcb41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga544adf091e79aa36d9d7a6e47bafcb41">CAN_TDT0R_TIME_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ffd9f8d93bb7f96dfc8f2b202986ec5">CAN_TDT0R_TIME_Pos</a>)</td></tr>
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<tr class="separator:ga544adf091e79aa36d9d7a6e47bafcb41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga104ba91151bf88edd44593b1690b879a" id="r_ga104ba91151bf88edd44593b1690b879a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga104ba91151bf88edd44593b1690b879a">CAN_TDT0R_TIME</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga544adf091e79aa36d9d7a6e47bafcb41">CAN_TDT0R_TIME_Msk</a></td></tr>
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<tr class="separator:ga104ba91151bf88edd44593b1690b879a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2dfd1e20e5283d40302140066d527d3" id="r_gae2dfd1e20e5283d40302140066d527d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2dfd1e20e5283d40302140066d527d3">CAN_TDL0R_DATA0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae2dfd1e20e5283d40302140066d527d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21c0f147ab22439d7677e400651302c4" id="r_ga21c0f147ab22439d7677e400651302c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21c0f147ab22439d7677e400651302c4">CAN_TDL0R_DATA0_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae2dfd1e20e5283d40302140066d527d3">CAN_TDL0R_DATA0_Pos</a>)</td></tr>
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<tr class="separator:ga21c0f147ab22439d7677e400651302c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadec3350607b41410ddb6e00a71a4384e" id="r_gadec3350607b41410ddb6e00a71a4384e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadec3350607b41410ddb6e00a71a4384e">CAN_TDL0R_DATA0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga21c0f147ab22439d7677e400651302c4">CAN_TDL0R_DATA0_Msk</a></td></tr>
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<tr class="separator:gadec3350607b41410ddb6e00a71a4384e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ebdc896d4816e5d5eee1c1700c7fb25" id="r_ga1ebdc896d4816e5d5eee1c1700c7fb25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ebdc896d4816e5d5eee1c1700c7fb25">CAN_TDL0R_DATA1_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga1ebdc896d4816e5d5eee1c1700c7fb25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae03b879d3e573023038e211ea211ae9f" id="r_gae03b879d3e573023038e211ea211ae9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae03b879d3e573023038e211ea211ae9f">CAN_TDL0R_DATA1_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ebdc896d4816e5d5eee1c1700c7fb25">CAN_TDL0R_DATA1_Pos</a>)</td></tr>
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<tr class="separator:gae03b879d3e573023038e211ea211ae9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cd20d218027e7432178c67414475830" id="r_ga1cd20d218027e7432178c67414475830"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cd20d218027e7432178c67414475830">CAN_TDL0R_DATA1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae03b879d3e573023038e211ea211ae9f">CAN_TDL0R_DATA1_Msk</a></td></tr>
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<tr class="memitem:gad46a5808e83c8ce1c6c2da8c3ee2898d" id="r_gad46a5808e83c8ce1c6c2da8c3ee2898d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad46a5808e83c8ce1c6c2da8c3ee2898d">CAN_TDL0R_DATA2_Pos</a>   (16U)</td></tr>
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<tr class="separator:gad46a5808e83c8ce1c6c2da8c3ee2898d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcc788dc5db08c074c7026e60d3af7cb" id="r_gadcc788dc5db08c074c7026e60d3af7cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcc788dc5db08c074c7026e60d3af7cb">CAN_TDL0R_DATA2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad46a5808e83c8ce1c6c2da8c3ee2898d">CAN_TDL0R_DATA2_Pos</a>)</td></tr>
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<tr class="separator:gadcc788dc5db08c074c7026e60d3af7cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa04384f0a7c5026c91a33a005c755d68" id="r_gaa04384f0a7c5026c91a33a005c755d68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa04384f0a7c5026c91a33a005c755d68">CAN_TDL0R_DATA2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadcc788dc5db08c074c7026e60d3af7cb">CAN_TDL0R_DATA2_Msk</a></td></tr>
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<tr class="separator:gaa04384f0a7c5026c91a33a005c755d68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66d8189fd904326f4be09972047fda59" id="r_ga66d8189fd904326f4be09972047fda59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66d8189fd904326f4be09972047fda59">CAN_TDL0R_DATA3_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga66d8189fd904326f4be09972047fda59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga782c6f20d550a56c15fe265a75105255" id="r_ga782c6f20d550a56c15fe265a75105255"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga782c6f20d550a56c15fe265a75105255">CAN_TDL0R_DATA3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d8189fd904326f4be09972047fda59">CAN_TDL0R_DATA3_Pos</a>)</td></tr>
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<tr class="separator:ga782c6f20d550a56c15fe265a75105255"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga283a1bfa52851ea4ee45f45817985752" id="r_ga283a1bfa52851ea4ee45f45817985752"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga283a1bfa52851ea4ee45f45817985752">CAN_TDL0R_DATA3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga782c6f20d550a56c15fe265a75105255">CAN_TDL0R_DATA3_Msk</a></td></tr>
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<tr class="separator:ga283a1bfa52851ea4ee45f45817985752"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67239c62f07e5a4d0f348f9595d4fb0e" id="r_ga67239c62f07e5a4d0f348f9595d4fb0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67239c62f07e5a4d0f348f9595d4fb0e">CAN_TDH0R_DATA4_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga67239c62f07e5a4d0f348f9595d4fb0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2389e6393c4c90eac09ecadd67e77203" id="r_ga2389e6393c4c90eac09ecadd67e77203"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2389e6393c4c90eac09ecadd67e77203">CAN_TDH0R_DATA4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67239c62f07e5a4d0f348f9595d4fb0e">CAN_TDH0R_DATA4_Pos</a>)</td></tr>
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<tr class="separator:ga2389e6393c4c90eac09ecadd67e77203"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0114ae75b33f978ca7825f7bcd836982" id="r_ga0114ae75b33f978ca7825f7bcd836982"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0114ae75b33f978ca7825f7bcd836982">CAN_TDH0R_DATA4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2389e6393c4c90eac09ecadd67e77203">CAN_TDH0R_DATA4_Msk</a></td></tr>
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<tr class="separator:ga0114ae75b33f978ca7825f7bcd836982"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac19fa11ce4c6d4c00690d453a3b42354" id="r_gac19fa11ce4c6d4c00690d453a3b42354"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac19fa11ce4c6d4c00690d453a3b42354">CAN_TDH0R_DATA5_Pos</a>   (8U)</td></tr>
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<tr class="separator:gac19fa11ce4c6d4c00690d453a3b42354"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadeaa64cd95a54957ee402f9edbd62411" id="r_gadeaa64cd95a54957ee402f9edbd62411"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadeaa64cd95a54957ee402f9edbd62411">CAN_TDH0R_DATA5_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac19fa11ce4c6d4c00690d453a3b42354">CAN_TDH0R_DATA5_Pos</a>)</td></tr>
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<tr class="separator:gadeaa64cd95a54957ee402f9edbd62411"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5b6a0742ac1bcd5ef0408cb0f92ef75" id="r_gaf5b6a0742ac1bcd5ef0408cb0f92ef75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5b6a0742ac1bcd5ef0408cb0f92ef75">CAN_TDH0R_DATA5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadeaa64cd95a54957ee402f9edbd62411">CAN_TDH0R_DATA5_Msk</a></td></tr>
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<tr class="separator:gaf5b6a0742ac1bcd5ef0408cb0f92ef75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19b1609d2ed4f6b59e9b175e022123b5" id="r_ga19b1609d2ed4f6b59e9b175e022123b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19b1609d2ed4f6b59e9b175e022123b5">CAN_TDH0R_DATA6_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga19b1609d2ed4f6b59e9b175e022123b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80deb2e84b16aa300ba4b6dad03ced70" id="r_ga80deb2e84b16aa300ba4b6dad03ced70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80deb2e84b16aa300ba4b6dad03ced70">CAN_TDH0R_DATA6_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga19b1609d2ed4f6b59e9b175e022123b5">CAN_TDH0R_DATA6_Pos</a>)</td></tr>
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<tr class="separator:ga80deb2e84b16aa300ba4b6dad03ced70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8ea7090da55c7cc9993235efa1c4a02" id="r_gac8ea7090da55c7cc9993235efa1c4a02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8ea7090da55c7cc9993235efa1c4a02">CAN_TDH0R_DATA6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga80deb2e84b16aa300ba4b6dad03ced70">CAN_TDH0R_DATA6_Msk</a></td></tr>
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<tr class="separator:gac8ea7090da55c7cc9993235efa1c4a02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed76c2a3e8d2946eeed952bb2ff20e94" id="r_gaed76c2a3e8d2946eeed952bb2ff20e94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed76c2a3e8d2946eeed952bb2ff20e94">CAN_TDH0R_DATA7_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaed76c2a3e8d2946eeed952bb2ff20e94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad14d21df0b2b694450b769b900c1161e" id="r_gad14d21df0b2b694450b769b900c1161e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad14d21df0b2b694450b769b900c1161e">CAN_TDH0R_DATA7_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed76c2a3e8d2946eeed952bb2ff20e94">CAN_TDH0R_DATA7_Pos</a>)</td></tr>
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<tr class="memitem:ga6021a4045fbfd71817bf9aec6cbc731c" id="r_ga6021a4045fbfd71817bf9aec6cbc731c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6021a4045fbfd71817bf9aec6cbc731c">CAN_TDH0R_DATA7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad14d21df0b2b694450b769b900c1161e">CAN_TDH0R_DATA7_Msk</a></td></tr>
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<tr class="separator:ga6021a4045fbfd71817bf9aec6cbc731c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab1e199d262fd92f1702125a8e8f5b49" id="r_gaab1e199d262fd92f1702125a8e8f5b49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab1e199d262fd92f1702125a8e8f5b49">CAN_TI1R_TXRQ_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaab1e199d262fd92f1702125a8e8f5b49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89f8f9283cb55ff6427db96afb6ad799" id="r_ga89f8f9283cb55ff6427db96afb6ad799"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89f8f9283cb55ff6427db96afb6ad799">CAN_TI1R_TXRQ_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab1e199d262fd92f1702125a8e8f5b49">CAN_TI1R_TXRQ_Pos</a>)</td></tr>
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<tr class="separator:ga89f8f9283cb55ff6427db96afb6ad799"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0adf4a08415673753fafedf463f93bee" id="r_ga0adf4a08415673753fafedf463f93bee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0adf4a08415673753fafedf463f93bee">CAN_TI1R_TXRQ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga89f8f9283cb55ff6427db96afb6ad799">CAN_TI1R_TXRQ_Msk</a></td></tr>
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<tr class="separator:ga0adf4a08415673753fafedf463f93bee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35a4cc56a2487c645c3b318bfba5e8ca" id="r_ga35a4cc56a2487c645c3b318bfba5e8ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35a4cc56a2487c645c3b318bfba5e8ca">CAN_TI1R_RTR_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga35a4cc56a2487c645c3b318bfba5e8ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f27bd0f65fe4d7afe69a92c28bef94e" id="r_ga2f27bd0f65fe4d7afe69a92c28bef94e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f27bd0f65fe4d7afe69a92c28bef94e">CAN_TI1R_RTR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga35a4cc56a2487c645c3b318bfba5e8ca">CAN_TI1R_RTR_Pos</a>)</td></tr>
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<tr class="separator:ga2f27bd0f65fe4d7afe69a92c28bef94e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga476cde56b1a2a13cde8477d5178ba34b" id="r_ga476cde56b1a2a13cde8477d5178ba34b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga476cde56b1a2a13cde8477d5178ba34b">CAN_TI1R_RTR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f27bd0f65fe4d7afe69a92c28bef94e">CAN_TI1R_RTR_Msk</a></td></tr>
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<tr class="separator:ga476cde56b1a2a13cde8477d5178ba34b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga176b1ffea4ad6af7a07044e30d9a210e" id="r_ga176b1ffea4ad6af7a07044e30d9a210e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga176b1ffea4ad6af7a07044e30d9a210e">CAN_TI1R_IDE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga176b1ffea4ad6af7a07044e30d9a210e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20f905ac8ef34db338cd9b9e94ea7216" id="r_ga20f905ac8ef34db338cd9b9e94ea7216"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20f905ac8ef34db338cd9b9e94ea7216">CAN_TI1R_IDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga176b1ffea4ad6af7a07044e30d9a210e">CAN_TI1R_IDE_Pos</a>)</td></tr>
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<tr class="separator:ga20f905ac8ef34db338cd9b9e94ea7216"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f338f3e295b7b512ed865b3f9a8d6de" id="r_ga8f338f3e295b7b512ed865b3f9a8d6de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f338f3e295b7b512ed865b3f9a8d6de">CAN_TI1R_IDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga20f905ac8ef34db338cd9b9e94ea7216">CAN_TI1R_IDE_Msk</a></td></tr>
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<tr class="separator:ga8f338f3e295b7b512ed865b3f9a8d6de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab927997e1cb30013ce0c58a974a1ea55" id="r_gab927997e1cb30013ce0c58a974a1ea55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab927997e1cb30013ce0c58a974a1ea55">CAN_TI1R_EXID_Pos</a>   (3U)</td></tr>
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<tr class="separator:gab927997e1cb30013ce0c58a974a1ea55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ba8b24afd72b47c403129c09a6f295f" id="r_ga8ba8b24afd72b47c403129c09a6f295f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ba8b24afd72b47c403129c09a6f295f">CAN_TI1R_EXID_Msk</a>   (0x3FFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab927997e1cb30013ce0c58a974a1ea55">CAN_TI1R_EXID_Pos</a>)</td></tr>
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<tr class="separator:ga8ba8b24afd72b47c403129c09a6f295f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c660943fa3c70c4974c2dacd3e4ca2e" id="r_ga6c660943fa3c70c4974c2dacd3e4ca2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c660943fa3c70c4974c2dacd3e4ca2e">CAN_TI1R_EXID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ba8b24afd72b47c403129c09a6f295f">CAN_TI1R_EXID_Msk</a></td></tr>
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<tr class="separator:ga6c660943fa3c70c4974c2dacd3e4ca2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a5e1691eb28536f2773609a195e4cbf" id="r_ga2a5e1691eb28536f2773609a195e4cbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5e1691eb28536f2773609a195e4cbf">CAN_TI1R_STID_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga2a5e1691eb28536f2773609a195e4cbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2fb9bb620f8051f9059d78eb2fd09cd9" id="r_ga2fb9bb620f8051f9059d78eb2fd09cd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fb9bb620f8051f9059d78eb2fd09cd9">CAN_TI1R_STID_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5e1691eb28536f2773609a195e4cbf">CAN_TI1R_STID_Pos</a>)</td></tr>
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<tr class="separator:ga2fb9bb620f8051f9059d78eb2fd09cd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga842071768c2f8f5eae11a764a77dd0dd" id="r_ga842071768c2f8f5eae11a764a77dd0dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga842071768c2f8f5eae11a764a77dd0dd">CAN_TI1R_STID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2fb9bb620f8051f9059d78eb2fd09cd9">CAN_TI1R_STID_Msk</a></td></tr>
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<tr class="separator:ga842071768c2f8f5eae11a764a77dd0dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b088fcd5a224ff04b87ca90fe4ad93a" id="r_ga5b088fcd5a224ff04b87ca90fe4ad93a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b088fcd5a224ff04b87ca90fe4ad93a">CAN_TDT1R_DLC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5b088fcd5a224ff04b87ca90fe4ad93a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78cb2a08e7abfd8105acee53c2fe6957" id="r_ga78cb2a08e7abfd8105acee53c2fe6957"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78cb2a08e7abfd8105acee53c2fe6957">CAN_TDT1R_DLC_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b088fcd5a224ff04b87ca90fe4ad93a">CAN_TDT1R_DLC_Pos</a>)</td></tr>
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<tr class="separator:ga78cb2a08e7abfd8105acee53c2fe6957"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68ef8b6cb43a80d29c5fc318a67acd3b" id="r_ga68ef8b6cb43a80d29c5fc318a67acd3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68ef8b6cb43a80d29c5fc318a67acd3b">CAN_TDT1R_DLC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga78cb2a08e7abfd8105acee53c2fe6957">CAN_TDT1R_DLC_Msk</a></td></tr>
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<tr class="separator:ga68ef8b6cb43a80d29c5fc318a67acd3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf17aa4d8323302bc493c93d38be34b60" id="r_gaf17aa4d8323302bc493c93d38be34b60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf17aa4d8323302bc493c93d38be34b60">CAN_TDT1R_TGT_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaf17aa4d8323302bc493c93d38be34b60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36274682f7c568c18db742816468f08d" id="r_ga36274682f7c568c18db742816468f08d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36274682f7c568c18db742816468f08d">CAN_TDT1R_TGT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf17aa4d8323302bc493c93d38be34b60">CAN_TDT1R_TGT_Pos</a>)</td></tr>
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<tr class="separator:ga36274682f7c568c18db742816468f08d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35757787e6481553885fdf4fd2738c4b" id="r_ga35757787e6481553885fdf4fd2738c4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35757787e6481553885fdf4fd2738c4b">CAN_TDT1R_TGT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36274682f7c568c18db742816468f08d">CAN_TDT1R_TGT_Msk</a></td></tr>
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<tr class="separator:ga35757787e6481553885fdf4fd2738c4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37df5b75c3aedc37c37f308d32b178b6" id="r_ga37df5b75c3aedc37c37f308d32b178b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37df5b75c3aedc37c37f308d32b178b6">CAN_TDT1R_TIME_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga37df5b75c3aedc37c37f308d32b178b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96a341aceed7cefa4f144685b047b5aa" id="r_ga96a341aceed7cefa4f144685b047b5aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96a341aceed7cefa4f144685b047b5aa">CAN_TDT1R_TIME_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga37df5b75c3aedc37c37f308d32b178b6">CAN_TDT1R_TIME_Pos</a>)</td></tr>
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<tr class="separator:ga96a341aceed7cefa4f144685b047b5aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad28ac334a59a6679c362611d65666910" id="r_gad28ac334a59a6679c362611d65666910"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad28ac334a59a6679c362611d65666910">CAN_TDT1R_TIME</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga96a341aceed7cefa4f144685b047b5aa">CAN_TDT1R_TIME_Msk</a></td></tr>
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<tr class="separator:gad28ac334a59a6679c362611d65666910"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a9794992e11c29ba12088b41a9215cd" id="r_ga4a9794992e11c29ba12088b41a9215cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a9794992e11c29ba12088b41a9215cd">CAN_TDL1R_DATA0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4a9794992e11c29ba12088b41a9215cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16520ea88ace96a458b0818d3e4d5cf2" id="r_ga16520ea88ace96a458b0818d3e4d5cf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16520ea88ace96a458b0818d3e4d5cf2">CAN_TDL1R_DATA0_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a9794992e11c29ba12088b41a9215cd">CAN_TDL1R_DATA0_Pos</a>)</td></tr>
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<tr class="separator:ga16520ea88ace96a458b0818d3e4d5cf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21abc05257bcdfa47fc824b4d806a105" id="r_ga21abc05257bcdfa47fc824b4d806a105"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21abc05257bcdfa47fc824b4d806a105">CAN_TDL1R_DATA0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga16520ea88ace96a458b0818d3e4d5cf2">CAN_TDL1R_DATA0_Msk</a></td></tr>
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<tr class="separator:ga21abc05257bcdfa47fc824b4d806a105"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15870798808b9bf8e3b389d99f8205bd" id="r_ga15870798808b9bf8e3b389d99f8205bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15870798808b9bf8e3b389d99f8205bd">CAN_TDL1R_DATA1_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga15870798808b9bf8e3b389d99f8205bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22d121d05d7faac3231ab8b0cc3fd4e2" id="r_ga22d121d05d7faac3231ab8b0cc3fd4e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22d121d05d7faac3231ab8b0cc3fd4e2">CAN_TDL1R_DATA1_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga15870798808b9bf8e3b389d99f8205bd">CAN_TDL1R_DATA1_Pos</a>)</td></tr>
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<tr class="separator:ga22d121d05d7faac3231ab8b0cc3fd4e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bf459dee1be706b38141722be67e4ab" id="r_ga0bf459dee1be706b38141722be67e4ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bf459dee1be706b38141722be67e4ab">CAN_TDL1R_DATA1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga22d121d05d7faac3231ab8b0cc3fd4e2">CAN_TDL1R_DATA1_Msk</a></td></tr>
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<tr class="separator:ga0bf459dee1be706b38141722be67e4ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga822b0dd09688ddb0241506b3657d3e76" id="r_ga822b0dd09688ddb0241506b3657d3e76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga822b0dd09688ddb0241506b3657d3e76">CAN_TDL1R_DATA2_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga822b0dd09688ddb0241506b3657d3e76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06359cf64606bd479a4a5e074c5e70ac" id="r_ga06359cf64606bd479a4a5e074c5e70ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06359cf64606bd479a4a5e074c5e70ac">CAN_TDL1R_DATA2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga822b0dd09688ddb0241506b3657d3e76">CAN_TDL1R_DATA2_Pos</a>)</td></tr>
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<tr class="separator:ga06359cf64606bd479a4a5e074c5e70ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb92a65c225432fab0daa30808d5065c" id="r_gaeb92a65c225432fab0daa30808d5065c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb92a65c225432fab0daa30808d5065c">CAN_TDL1R_DATA2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06359cf64606bd479a4a5e074c5e70ac">CAN_TDL1R_DATA2_Msk</a></td></tr>
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<tr class="separator:gaeb92a65c225432fab0daa30808d5065c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26002007d5645d59e1de29fecb91c906" id="r_ga26002007d5645d59e1de29fecb91c906"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26002007d5645d59e1de29fecb91c906">CAN_TDL1R_DATA3_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga17d98be9066ebe1cf701052043be89bc" id="r_ga17d98be9066ebe1cf701052043be89bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17d98be9066ebe1cf701052043be89bc">CAN_TDL1R_DATA3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga26002007d5645d59e1de29fecb91c906">CAN_TDL1R_DATA3_Pos</a>)</td></tr>
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<tr class="separator:ga17d98be9066ebe1cf701052043be89bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga482506faa59360c6a48aa9bc55a024c4" id="r_ga482506faa59360c6a48aa9bc55a024c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga482506faa59360c6a48aa9bc55a024c4">CAN_TDL1R_DATA3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga17d98be9066ebe1cf701052043be89bc">CAN_TDL1R_DATA3_Msk</a></td></tr>
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<tr class="separator:ga482506faa59360c6a48aa9bc55a024c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4acd3f2aaf9f8a62bc486733feb4fba8" id="r_ga4acd3f2aaf9f8a62bc486733feb4fba8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4acd3f2aaf9f8a62bc486733feb4fba8">CAN_TDH1R_DATA4_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4acd3f2aaf9f8a62bc486733feb4fba8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44d94c7419786e7bba7ec0a1b35395cb" id="r_ga44d94c7419786e7bba7ec0a1b35395cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44d94c7419786e7bba7ec0a1b35395cb">CAN_TDH1R_DATA4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4acd3f2aaf9f8a62bc486733feb4fba8">CAN_TDH1R_DATA4_Pos</a>)</td></tr>
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<tr class="separator:ga44d94c7419786e7bba7ec0a1b35395cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41c3f19eea0d63211f643833da984c90" id="r_ga41c3f19eea0d63211f643833da984c90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41c3f19eea0d63211f643833da984c90">CAN_TDH1R_DATA4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44d94c7419786e7bba7ec0a1b35395cb">CAN_TDH1R_DATA4_Msk</a></td></tr>
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<tr class="separator:ga41c3f19eea0d63211f643833da984c90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f2050d91710f0b977d984e164067f9f" id="r_ga7f2050d91710f0b977d984e164067f9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f2050d91710f0b977d984e164067f9f">CAN_TDH1R_DATA5_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga7f2050d91710f0b977d984e164067f9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa946d8a10e5f952a5c4eda78228042af" id="r_gaa946d8a10e5f952a5c4eda78228042af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa946d8a10e5f952a5c4eda78228042af">CAN_TDH1R_DATA5_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f2050d91710f0b977d984e164067f9f">CAN_TDH1R_DATA5_Pos</a>)</td></tr>
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<tr class="separator:gaa946d8a10e5f952a5c4eda78228042af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35cbe73d2ce87b6aaf19510818610d16" id="r_ga35cbe73d2ce87b6aaf19510818610d16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35cbe73d2ce87b6aaf19510818610d16">CAN_TDH1R_DATA5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa946d8a10e5f952a5c4eda78228042af">CAN_TDH1R_DATA5_Msk</a></td></tr>
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<tr class="separator:ga35cbe73d2ce87b6aaf19510818610d16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f3a0e5d886a7db9accd6e2d1316174f" id="r_ga8f3a0e5d886a7db9accd6e2d1316174f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f3a0e5d886a7db9accd6e2d1316174f">CAN_TDH1R_DATA6_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga8f3a0e5d886a7db9accd6e2d1316174f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff0a58abbdfa5e21213dbc2f82935250" id="r_gaff0a58abbdfa5e21213dbc2f82935250"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff0a58abbdfa5e21213dbc2f82935250">CAN_TDH1R_DATA6_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f3a0e5d886a7db9accd6e2d1316174f">CAN_TDH1R_DATA6_Pos</a>)</td></tr>
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<tr class="separator:gaff0a58abbdfa5e21213dbc2f82935250"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b731ca095cbad8e56ba4147c14d7128" id="r_ga1b731ca095cbad8e56ba4147c14d7128"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b731ca095cbad8e56ba4147c14d7128">CAN_TDH1R_DATA6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaff0a58abbdfa5e21213dbc2f82935250">CAN_TDH1R_DATA6_Msk</a></td></tr>
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<tr class="separator:ga1b731ca095cbad8e56ba4147c14d7128"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae01db20e595c85191c3abd91a1f74717" id="r_gae01db20e595c85191c3abd91a1f74717"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae01db20e595c85191c3abd91a1f74717">CAN_TDH1R_DATA7_Pos</a>   (24U)</td></tr>
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<tr class="separator:gae01db20e595c85191c3abd91a1f74717"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga625d5b8e464b8dfc789e4191f55444cf" id="r_ga625d5b8e464b8dfc789e4191f55444cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga625d5b8e464b8dfc789e4191f55444cf">CAN_TDH1R_DATA7_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae01db20e595c85191c3abd91a1f74717">CAN_TDH1R_DATA7_Pos</a>)</td></tr>
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<tr class="separator:ga625d5b8e464b8dfc789e4191f55444cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec56ce4aba46e836d44e2c034a9ed817" id="r_gaec56ce4aba46e836d44e2c034a9ed817"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec56ce4aba46e836d44e2c034a9ed817">CAN_TDH1R_DATA7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga625d5b8e464b8dfc789e4191f55444cf">CAN_TDH1R_DATA7_Msk</a></td></tr>
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<tr class="separator:gaec56ce4aba46e836d44e2c034a9ed817"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fa18e2cbbb88117b1b6272c0c1ffea4" id="r_ga5fa18e2cbbb88117b1b6272c0c1ffea4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fa18e2cbbb88117b1b6272c0c1ffea4">CAN_TI2R_TXRQ_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5fa18e2cbbb88117b1b6272c0c1ffea4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76f8681c59cc25db5a1089ecfc20a2ce" id="r_ga76f8681c59cc25db5a1089ecfc20a2ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76f8681c59cc25db5a1089ecfc20a2ce">CAN_TI2R_TXRQ_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fa18e2cbbb88117b1b6272c0c1ffea4">CAN_TI2R_TXRQ_Pos</a>)</td></tr>
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<tr class="separator:ga76f8681c59cc25db5a1089ecfc20a2ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4edd8438a684e353c497f80cb37365f" id="r_gab4edd8438a684e353c497f80cb37365f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4edd8438a684e353c497f80cb37365f">CAN_TI2R_TXRQ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga76f8681c59cc25db5a1089ecfc20a2ce">CAN_TI2R_TXRQ_Msk</a></td></tr>
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<tr class="separator:gab4edd8438a684e353c497f80cb37365f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ac8d95e007f7ca50f787eac4e08aa1e" id="r_ga7ac8d95e007f7ca50f787eac4e08aa1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac8d95e007f7ca50f787eac4e08aa1e">CAN_TI2R_RTR_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga7ac8d95e007f7ca50f787eac4e08aa1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe417e434f32c25426c52b68fb763c9f" id="r_gafe417e434f32c25426c52b68fb763c9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe417e434f32c25426c52b68fb763c9f">CAN_TI2R_RTR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac8d95e007f7ca50f787eac4e08aa1e">CAN_TI2R_RTR_Pos</a>)</td></tr>
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<tr class="separator:gafe417e434f32c25426c52b68fb763c9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga980cfab3daebb05da35b6166a051385d" id="r_ga980cfab3daebb05da35b6166a051385d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga980cfab3daebb05da35b6166a051385d">CAN_TI2R_RTR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafe417e434f32c25426c52b68fb763c9f">CAN_TI2R_RTR_Msk</a></td></tr>
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<tr class="separator:ga980cfab3daebb05da35b6166a051385d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade77331f4ecfa76912b1a1b439583b61" id="r_gade77331f4ecfa76912b1a1b439583b61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade77331f4ecfa76912b1a1b439583b61">CAN_TI2R_IDE_Pos</a>   (2U)</td></tr>
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<tr class="separator:gade77331f4ecfa76912b1a1b439583b61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5048adf1f603ea5d5170f3f9bcb92b4" id="r_gab5048adf1f603ea5d5170f3f9bcb92b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5048adf1f603ea5d5170f3f9bcb92b4">CAN_TI2R_IDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade77331f4ecfa76912b1a1b439583b61">CAN_TI2R_IDE_Pos</a>)</td></tr>
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<tr class="separator:gab5048adf1f603ea5d5170f3f9bcb92b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1d888a2225c77452f73bf66fb0e1b78" id="r_gac1d888a2225c77452f73bf66fb0e1b78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1d888a2225c77452f73bf66fb0e1b78">CAN_TI2R_IDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab5048adf1f603ea5d5170f3f9bcb92b4">CAN_TI2R_IDE_Msk</a></td></tr>
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<tr class="separator:gac1d888a2225c77452f73bf66fb0e1b78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd2af643048de0df22426f9066d19223" id="r_gafd2af643048de0df22426f9066d19223"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd2af643048de0df22426f9066d19223">CAN_TI2R_EXID_Pos</a>   (3U)</td></tr>
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<tr class="separator:gafd2af643048de0df22426f9066d19223"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade10da0694545f61f922cc3679f719d1" id="r_gade10da0694545f61f922cc3679f719d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade10da0694545f61f922cc3679f719d1">CAN_TI2R_EXID_Msk</a>   (0x3FFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafd2af643048de0df22426f9066d19223">CAN_TI2R_EXID_Pos</a>)</td></tr>
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<tr class="separator:gade10da0694545f61f922cc3679f719d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae62678bd1dc39aae5a153e9c9b3c3f3b" id="r_gae62678bd1dc39aae5a153e9c9b3c3f3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae62678bd1dc39aae5a153e9c9b3c3f3b">CAN_TI2R_EXID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gade10da0694545f61f922cc3679f719d1">CAN_TI2R_EXID_Msk</a></td></tr>
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<tr class="separator:gae62678bd1dc39aae5a153e9c9b3c3f3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2fa5a1ec336dd0151f1027aa25379708" id="r_ga2fa5a1ec336dd0151f1027aa25379708"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fa5a1ec336dd0151f1027aa25379708">CAN_TI2R_STID_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga2fa5a1ec336dd0151f1027aa25379708"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78165cdc898ec9184cf14df3d1940a46" id="r_ga78165cdc898ec9184cf14df3d1940a46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78165cdc898ec9184cf14df3d1940a46">CAN_TI2R_STID_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2fa5a1ec336dd0151f1027aa25379708">CAN_TI2R_STID_Pos</a>)</td></tr>
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<tr class="separator:ga78165cdc898ec9184cf14df3d1940a46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41c8bd734dd29caa40d34ced3981443a" id="r_ga41c8bd734dd29caa40d34ced3981443a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41c8bd734dd29caa40d34ced3981443a">CAN_TI2R_STID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga78165cdc898ec9184cf14df3d1940a46">CAN_TI2R_STID_Msk</a></td></tr>
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<tr class="separator:ga41c8bd734dd29caa40d34ced3981443a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45143135ab0f9c01d85cca11d7949b26" id="r_ga45143135ab0f9c01d85cca11d7949b26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45143135ab0f9c01d85cca11d7949b26">CAN_TDT2R_DLC_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga63e75710f89ae715962fd2e2c5465edb" id="r_ga63e75710f89ae715962fd2e2c5465edb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63e75710f89ae715962fd2e2c5465edb">CAN_TDT2R_DLC_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga45143135ab0f9c01d85cca11d7949b26">CAN_TDT2R_DLC_Pos</a>)</td></tr>
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<tr class="memitem:ga52898eb9fa3bcf0b8086220971af49f5" id="r_ga52898eb9fa3bcf0b8086220971af49f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52898eb9fa3bcf0b8086220971af49f5">CAN_TDT2R_DLC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63e75710f89ae715962fd2e2c5465edb">CAN_TDT2R_DLC_Msk</a></td></tr>
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<tr class="memitem:gaa9e5a3e9a2526007920e8a255b7e1c3a" id="r_gaa9e5a3e9a2526007920e8a255b7e1c3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9e5a3e9a2526007920e8a255b7e1c3a">CAN_TDT2R_TGT_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga01d388232664bf958d0396c19e39c815" id="r_ga01d388232664bf958d0396c19e39c815"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01d388232664bf958d0396c19e39c815">CAN_TDT2R_TGT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9e5a3e9a2526007920e8a255b7e1c3a">CAN_TDT2R_TGT_Pos</a>)</td></tr>
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<tr class="memitem:ga4c51b43d309b56e8a64724ef1517033e" id="r_ga4c51b43d309b56e8a64724ef1517033e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c51b43d309b56e8a64724ef1517033e">CAN_TDT2R_TGT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga01d388232664bf958d0396c19e39c815">CAN_TDT2R_TGT_Msk</a></td></tr>
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<tr class="memitem:gaceba646b9f79f648862f0ec8cf1e6a85" id="r_gaceba646b9f79f648862f0ec8cf1e6a85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaceba646b9f79f648862f0ec8cf1e6a85">CAN_TDT2R_TIME_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga9585327a9b756069b9a3ee0727e35f19" id="r_ga9585327a9b756069b9a3ee0727e35f19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9585327a9b756069b9a3ee0727e35f19">CAN_TDT2R_TIME_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaceba646b9f79f648862f0ec8cf1e6a85">CAN_TDT2R_TIME_Pos</a>)</td></tr>
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<tr class="memitem:ga508aea584f7c81700b485916a13431fa" id="r_ga508aea584f7c81700b485916a13431fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga508aea584f7c81700b485916a13431fa">CAN_TDT2R_TIME</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9585327a9b756069b9a3ee0727e35f19">CAN_TDT2R_TIME_Msk</a></td></tr>
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<tr class="memitem:ga3e9d0286857aaf4744cae03ce9379b74" id="r_ga3e9d0286857aaf4744cae03ce9379b74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e9d0286857aaf4744cae03ce9379b74">CAN_TDL2R_DATA0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3e9d0286857aaf4744cae03ce9379b74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9d44c13085429bc76007fa3aff31964" id="r_gad9d44c13085429bc76007fa3aff31964"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9d44c13085429bc76007fa3aff31964">CAN_TDL2R_DATA0_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e9d0286857aaf4744cae03ce9379b74">CAN_TDL2R_DATA0_Pos</a>)</td></tr>
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<tr class="memitem:ga7a9852d0f6058c19f0e678228ea14a21" id="r_ga7a9852d0f6058c19f0e678228ea14a21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a9852d0f6058c19f0e678228ea14a21">CAN_TDL2R_DATA0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad9d44c13085429bc76007fa3aff31964">CAN_TDL2R_DATA0_Msk</a></td></tr>
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<tr class="memitem:ga58e2da210f0a94f67e20d4c6179034c6" id="r_ga58e2da210f0a94f67e20d4c6179034c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58e2da210f0a94f67e20d4c6179034c6">CAN_TDL2R_DATA1_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gac9e6c39a9c27791be19e6cde5f8c45c7" id="r_gac9e6c39a9c27791be19e6cde5f8c45c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9e6c39a9c27791be19e6cde5f8c45c7">CAN_TDL2R_DATA1_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58e2da210f0a94f67e20d4c6179034c6">CAN_TDL2R_DATA1_Pos</a>)</td></tr>
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<tr class="memitem:gad5be1bcda68f562be669184b30727be1" id="r_gad5be1bcda68f562be669184b30727be1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5be1bcda68f562be669184b30727be1">CAN_TDL2R_DATA1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9e6c39a9c27791be19e6cde5f8c45c7">CAN_TDL2R_DATA1_Msk</a></td></tr>
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<tr class="memitem:ga0d7a1f37d86fae4a8efd1beb1322a4de" id="r_ga0d7a1f37d86fae4a8efd1beb1322a4de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d7a1f37d86fae4a8efd1beb1322a4de">CAN_TDL2R_DATA2_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga0d7a1f37d86fae4a8efd1beb1322a4de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dae494d814d7c4c5785066ffc203f11" id="r_ga4dae494d814d7c4c5785066ffc203f11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dae494d814d7c4c5785066ffc203f11">CAN_TDL2R_DATA2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d7a1f37d86fae4a8efd1beb1322a4de">CAN_TDL2R_DATA2_Pos</a>)</td></tr>
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<tr class="separator:ga4dae494d814d7c4c5785066ffc203f11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62cd5e7f3e98fe5b247998d39ebdd6fb" id="r_ga62cd5e7f3e98fe5b247998d39ebdd6fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62cd5e7f3e98fe5b247998d39ebdd6fb">CAN_TDL2R_DATA2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4dae494d814d7c4c5785066ffc203f11">CAN_TDL2R_DATA2_Msk</a></td></tr>
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<tr class="separator:ga62cd5e7f3e98fe5b247998d39ebdd6fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b77eb2ec1d44ecd49eae21f5d238a32" id="r_ga7b77eb2ec1d44ecd49eae21f5d238a32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b77eb2ec1d44ecd49eae21f5d238a32">CAN_TDL2R_DATA3_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga7b77eb2ec1d44ecd49eae21f5d238a32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9551d67aa378b224e317e4f298ccd195" id="r_ga9551d67aa378b224e317e4f298ccd195"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9551d67aa378b224e317e4f298ccd195">CAN_TDL2R_DATA3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b77eb2ec1d44ecd49eae21f5d238a32">CAN_TDL2R_DATA3_Pos</a>)</td></tr>
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<tr class="memitem:ga3d76ed3982f13fb34a54d62f0caa3fa2" id="r_ga3d76ed3982f13fb34a54d62f0caa3fa2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d76ed3982f13fb34a54d62f0caa3fa2">CAN_TDL2R_DATA3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9551d67aa378b224e317e4f298ccd195">CAN_TDL2R_DATA3_Msk</a></td></tr>
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<tr class="memitem:ga61800b82cf4fd9229d91e7f9e3ac7158" id="r_ga61800b82cf4fd9229d91e7f9e3ac7158"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61800b82cf4fd9229d91e7f9e3ac7158">CAN_TDH2R_DATA4_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga61800b82cf4fd9229d91e7f9e3ac7158"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae061c8ed2699c7a7be546e5825946c60" id="r_gae061c8ed2699c7a7be546e5825946c60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae061c8ed2699c7a7be546e5825946c60">CAN_TDH2R_DATA4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61800b82cf4fd9229d91e7f9e3ac7158">CAN_TDH2R_DATA4_Pos</a>)</td></tr>
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<tr class="memitem:ga23a93a13da2f302ecd2f0c462065428d" id="r_ga23a93a13da2f302ecd2f0c462065428d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23a93a13da2f302ecd2f0c462065428d">CAN_TDH2R_DATA4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae061c8ed2699c7a7be546e5825946c60">CAN_TDH2R_DATA4_Msk</a></td></tr>
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<tr class="separator:ga23a93a13da2f302ecd2f0c462065428d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd401f60132154e0d004d262ba48e862" id="r_gabd401f60132154e0d004d262ba48e862"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd401f60132154e0d004d262ba48e862">CAN_TDH2R_DATA5_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gaf5ace2c6eb67c621bf571e285b76b007" id="r_gaf5ace2c6eb67c621bf571e285b76b007"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5ace2c6eb67c621bf571e285b76b007">CAN_TDH2R_DATA5_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabd401f60132154e0d004d262ba48e862">CAN_TDH2R_DATA5_Pos</a>)</td></tr>
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<tr class="memitem:gab9f372328c8d1e4fe2503d45aed50fb6" id="r_gab9f372328c8d1e4fe2503d45aed50fb6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9f372328c8d1e4fe2503d45aed50fb6">CAN_TDH2R_DATA5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5ace2c6eb67c621bf571e285b76b007">CAN_TDH2R_DATA5_Msk</a></td></tr>
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<tr class="separator:gab9f372328c8d1e4fe2503d45aed50fb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf512e0c618635a2b56048d1712930843" id="r_gaf512e0c618635a2b56048d1712930843"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf512e0c618635a2b56048d1712930843">CAN_TDH2R_DATA6_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga621fec630f1758b3f11a2e52e62fa970" id="r_ga621fec630f1758b3f11a2e52e62fa970"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga621fec630f1758b3f11a2e52e62fa970">CAN_TDH2R_DATA6_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf512e0c618635a2b56048d1712930843">CAN_TDH2R_DATA6_Pos</a>)</td></tr>
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<tr class="separator:ga621fec630f1758b3f11a2e52e62fa970"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae96248bcf102a3c6f39f72cdcf8e4fe5" id="r_gae96248bcf102a3c6f39f72cdcf8e4fe5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae96248bcf102a3c6f39f72cdcf8e4fe5">CAN_TDH2R_DATA6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga621fec630f1758b3f11a2e52e62fa970">CAN_TDH2R_DATA6_Msk</a></td></tr>
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<tr class="separator:gae96248bcf102a3c6f39f72cdcf8e4fe5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57346e5378ab4dbab77f4f84d5a1e780" id="r_ga57346e5378ab4dbab77f4f84d5a1e780"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57346e5378ab4dbab77f4f84d5a1e780">CAN_TDH2R_DATA7_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga57346e5378ab4dbab77f4f84d5a1e780"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee62fccda69811932555a125bce78606" id="r_gaee62fccda69811932555a125bce78606"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee62fccda69811932555a125bce78606">CAN_TDH2R_DATA7_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57346e5378ab4dbab77f4f84d5a1e780">CAN_TDH2R_DATA7_Pos</a>)</td></tr>
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<tr class="memitem:ga895341b943e4b01938857b84a0b0dbda" id="r_ga895341b943e4b01938857b84a0b0dbda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga895341b943e4b01938857b84a0b0dbda">CAN_TDH2R_DATA7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaee62fccda69811932555a125bce78606">CAN_TDH2R_DATA7_Msk</a></td></tr>
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<tr class="memitem:ga1534235598ebdacd295d6e248ca1732f" id="r_ga1534235598ebdacd295d6e248ca1732f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1534235598ebdacd295d6e248ca1732f">CAN_RI0R_RTR_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga1534235598ebdacd295d6e248ca1732f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga833387b84a95443455bffb4a6390b7b9" id="r_ga833387b84a95443455bffb4a6390b7b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga833387b84a95443455bffb4a6390b7b9">CAN_RI0R_RTR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1534235598ebdacd295d6e248ca1732f">CAN_RI0R_RTR_Pos</a>)</td></tr>
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<tr class="separator:ga833387b84a95443455bffb4a6390b7b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41f4780b822a42834bf1927eb92b4fba" id="r_ga41f4780b822a42834bf1927eb92b4fba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41f4780b822a42834bf1927eb92b4fba">CAN_RI0R_RTR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga833387b84a95443455bffb4a6390b7b9">CAN_RI0R_RTR_Msk</a></td></tr>
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<tr class="separator:ga41f4780b822a42834bf1927eb92b4fba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1f9c6a0d27ac2f4c05fa3d0f6aab88b" id="r_gad1f9c6a0d27ac2f4c05fa3d0f6aab88b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1f9c6a0d27ac2f4c05fa3d0f6aab88b">CAN_RI0R_IDE_Pos</a>   (2U)</td></tr>
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<tr class="separator:gad1f9c6a0d27ac2f4c05fa3d0f6aab88b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80f4b044d79d1e751d54a604b637c26c" id="r_ga80f4b044d79d1e751d54a604b637c26c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80f4b044d79d1e751d54a604b637c26c">CAN_RI0R_IDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad1f9c6a0d27ac2f4c05fa3d0f6aab88b">CAN_RI0R_IDE_Pos</a>)</td></tr>
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<tr class="separator:ga80f4b044d79d1e751d54a604b637c26c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga688074182caafff289c921548bc9afca" id="r_ga688074182caafff289c921548bc9afca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga688074182caafff289c921548bc9afca">CAN_RI0R_IDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga80f4b044d79d1e751d54a604b637c26c">CAN_RI0R_IDE_Msk</a></td></tr>
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<tr class="separator:ga688074182caafff289c921548bc9afca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga782a6732674fa4ee7b2581709d2a45b7" id="r_ga782a6732674fa4ee7b2581709d2a45b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga782a6732674fa4ee7b2581709d2a45b7">CAN_RI0R_EXID_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga782a6732674fa4ee7b2581709d2a45b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf95ca68eadd026273958ef22678dc37" id="r_gacf95ca68eadd026273958ef22678dc37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf95ca68eadd026273958ef22678dc37">CAN_RI0R_EXID_Msk</a>   (0x3FFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga782a6732674fa4ee7b2581709d2a45b7">CAN_RI0R_EXID_Pos</a>)</td></tr>
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<tr class="separator:gacf95ca68eadd026273958ef22678dc37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d81487e8b340810e3193cd8f1386240" id="r_ga4d81487e8b340810e3193cd8f1386240"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d81487e8b340810e3193cd8f1386240">CAN_RI0R_EXID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacf95ca68eadd026273958ef22678dc37">CAN_RI0R_EXID_Msk</a></td></tr>
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<tr class="separator:ga4d81487e8b340810e3193cd8f1386240"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac72774c622ac99f08cc1f7e2814be168" id="r_gac72774c622ac99f08cc1f7e2814be168"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac72774c622ac99f08cc1f7e2814be168">CAN_RI0R_STID_Pos</a>   (21U)</td></tr>
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<tr class="separator:gac72774c622ac99f08cc1f7e2814be168"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02a63ecf925c0930d317bdbf439e9486" id="r_ga02a63ecf925c0930d317bdbf439e9486"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02a63ecf925c0930d317bdbf439e9486">CAN_RI0R_STID_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac72774c622ac99f08cc1f7e2814be168">CAN_RI0R_STID_Pos</a>)</td></tr>
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<tr class="separator:ga02a63ecf925c0930d317bdbf439e9486"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga101aa355c83b8c7d068f02b7dcc5b98f" id="r_ga101aa355c83b8c7d068f02b7dcc5b98f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga101aa355c83b8c7d068f02b7dcc5b98f">CAN_RI0R_STID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga02a63ecf925c0930d317bdbf439e9486">CAN_RI0R_STID_Msk</a></td></tr>
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<tr class="separator:ga101aa355c83b8c7d068f02b7dcc5b98f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabcb714f10d7dba636a67e79c0473dbf9" id="r_gabcb714f10d7dba636a67e79c0473dbf9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabcb714f10d7dba636a67e79c0473dbf9">CAN_RDT0R_DLC_Pos</a>   (0U)</td></tr>
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<tr class="separator:gabcb714f10d7dba636a67e79c0473dbf9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace43bd7d7388fd3cf4c33142d62ef541" id="r_gace43bd7d7388fd3cf4c33142d62ef541"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace43bd7d7388fd3cf4c33142d62ef541">CAN_RDT0R_DLC_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabcb714f10d7dba636a67e79c0473dbf9">CAN_RDT0R_DLC_Pos</a>)</td></tr>
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<tr class="separator:gace43bd7d7388fd3cf4c33142d62ef541"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17ca0af4afd89e6a1c43ffd1430359b7" id="r_ga17ca0af4afd89e6a1c43ffd1430359b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17ca0af4afd89e6a1c43ffd1430359b7">CAN_RDT0R_DLC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gace43bd7d7388fd3cf4c33142d62ef541">CAN_RDT0R_DLC_Msk</a></td></tr>
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<tr class="separator:ga17ca0af4afd89e6a1c43ffd1430359b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6076b1e14b5a81a0a25e4e8973a28477" id="r_ga6076b1e14b5a81a0a25e4e8973a28477"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6076b1e14b5a81a0a25e4e8973a28477">CAN_RDT0R_FMI_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga6076b1e14b5a81a0a25e4e8973a28477"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bafb8a31e8370f9d068a1acfe30e222" id="r_ga9bafb8a31e8370f9d068a1acfe30e222"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bafb8a31e8370f9d068a1acfe30e222">CAN_RDT0R_FMI_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6076b1e14b5a81a0a25e4e8973a28477">CAN_RDT0R_FMI_Pos</a>)</td></tr>
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<tr class="separator:ga9bafb8a31e8370f9d068a1acfe30e222"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5081739b6e21e033b95e68af9331a6d1" id="r_ga5081739b6e21e033b95e68af9331a6d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5081739b6e21e033b95e68af9331a6d1">CAN_RDT0R_FMI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9bafb8a31e8370f9d068a1acfe30e222">CAN_RDT0R_FMI_Msk</a></td></tr>
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<tr class="separator:ga5081739b6e21e033b95e68af9331a6d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44d89e7d66e3f4c953cbaeb271a30ada" id="r_ga44d89e7d66e3f4c953cbaeb271a30ada"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44d89e7d66e3f4c953cbaeb271a30ada">CAN_RDT0R_TIME_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga44d89e7d66e3f4c953cbaeb271a30ada"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcf8581ecb0c6b9bf464155b93f1003a" id="r_gafcf8581ecb0c6b9bf464155b93f1003a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcf8581ecb0c6b9bf464155b93f1003a">CAN_RDT0R_TIME_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga44d89e7d66e3f4c953cbaeb271a30ada">CAN_RDT0R_TIME_Pos</a>)</td></tr>
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<tr class="separator:gafcf8581ecb0c6b9bf464155b93f1003a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae20b7a72690033591eeda7a511ac4a2e" id="r_gae20b7a72690033591eeda7a511ac4a2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae20b7a72690033591eeda7a511ac4a2e">CAN_RDT0R_TIME</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafcf8581ecb0c6b9bf464155b93f1003a">CAN_RDT0R_TIME_Msk</a></td></tr>
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<tr class="separator:gae20b7a72690033591eeda7a511ac4a2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd7172931b3e1d8cf3daba5edfdd42c4" id="r_gadd7172931b3e1d8cf3daba5edfdd42c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd7172931b3e1d8cf3daba5edfdd42c4">CAN_RDL0R_DATA0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gadd7172931b3e1d8cf3daba5edfdd42c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15f91b45288700ef7858e998d598ea21" id="r_ga15f91b45288700ef7858e998d598ea21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15f91b45288700ef7858e998d598ea21">CAN_RDL0R_DATA0_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadd7172931b3e1d8cf3daba5edfdd42c4">CAN_RDL0R_DATA0_Pos</a>)</td></tr>
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<tr class="separator:ga15f91b45288700ef7858e998d598ea21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44313106efc3a5a65633168a2ad1928d" id="r_ga44313106efc3a5a65633168a2ad1928d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44313106efc3a5a65633168a2ad1928d">CAN_RDL0R_DATA0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga15f91b45288700ef7858e998d598ea21">CAN_RDL0R_DATA0_Msk</a></td></tr>
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<tr class="separator:ga44313106efc3a5a65633168a2ad1928d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab942d411c058da0f504d49adabdf7f11" id="r_gab942d411c058da0f504d49adabdf7f11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab942d411c058da0f504d49adabdf7f11">CAN_RDL0R_DATA1_Pos</a>   (8U)</td></tr>
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<tr class="separator:gab942d411c058da0f504d49adabdf7f11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86f144804d9b849f9bf589f9d0d53b4c" id="r_ga86f144804d9b849f9bf589f9d0d53b4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86f144804d9b849f9bf589f9d0d53b4c">CAN_RDL0R_DATA1_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab942d411c058da0f504d49adabdf7f11">CAN_RDL0R_DATA1_Pos</a>)</td></tr>
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<tr class="separator:ga86f144804d9b849f9bf589f9d0d53b4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73d4025ce501af78db93761e8b8c3b9e" id="r_ga73d4025ce501af78db93761e8b8c3b9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73d4025ce501af78db93761e8b8c3b9e">CAN_RDL0R_DATA1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86f144804d9b849f9bf589f9d0d53b4c">CAN_RDL0R_DATA1_Msk</a></td></tr>
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<tr class="separator:ga73d4025ce501af78db93761e8b8c3b9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe0336c208a9884936f3527688c349de" id="r_gafe0336c208a9884936f3527688c349de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe0336c208a9884936f3527688c349de">CAN_RDL0R_DATA2_Pos</a>   (16U)</td></tr>
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<tr class="separator:gafe0336c208a9884936f3527688c349de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75e00e47c6f9bab7a6602af43e7d9d4d" id="r_ga75e00e47c6f9bab7a6602af43e7d9d4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75e00e47c6f9bab7a6602af43e7d9d4d">CAN_RDL0R_DATA2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafe0336c208a9884936f3527688c349de">CAN_RDL0R_DATA2_Pos</a>)</td></tr>
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<tr class="separator:ga75e00e47c6f9bab7a6602af43e7d9d4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52b3c31ad72881e11a4d3cae073a0df8" id="r_ga52b3c31ad72881e11a4d3cae073a0df8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52b3c31ad72881e11a4d3cae073a0df8">CAN_RDL0R_DATA2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga75e00e47c6f9bab7a6602af43e7d9d4d">CAN_RDL0R_DATA2_Msk</a></td></tr>
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<tr class="separator:ga52b3c31ad72881e11a4d3cae073a0df8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga839a3d98930a4ab823b30dc7ac805e9a" id="r_ga839a3d98930a4ab823b30dc7ac805e9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga839a3d98930a4ab823b30dc7ac805e9a">CAN_RDL0R_DATA3_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga839a3d98930a4ab823b30dc7ac805e9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0b46bd6794046d7c70d8db43a5c5524" id="r_gaa0b46bd6794046d7c70d8db43a5c5524"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0b46bd6794046d7c70d8db43a5c5524">CAN_RDL0R_DATA3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga839a3d98930a4ab823b30dc7ac805e9a">CAN_RDL0R_DATA3_Pos</a>)</td></tr>
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<tr class="separator:gaa0b46bd6794046d7c70d8db43a5c5524"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad637a53ae780998f95f2bb570d5cd05a" id="r_gad637a53ae780998f95f2bb570d5cd05a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad637a53ae780998f95f2bb570d5cd05a">CAN_RDL0R_DATA3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0b46bd6794046d7c70d8db43a5c5524">CAN_RDL0R_DATA3_Msk</a></td></tr>
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<tr class="separator:gad637a53ae780998f95f2bb570d5cd05a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cb8238c1f77ff904290afdc572b31bc" id="r_ga3cb8238c1f77ff904290afdc572b31bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cb8238c1f77ff904290afdc572b31bc">CAN_RDH0R_DATA4_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3cb8238c1f77ff904290afdc572b31bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga043ce7187baa93bc909445ec56a283b1" id="r_ga043ce7187baa93bc909445ec56a283b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga043ce7187baa93bc909445ec56a283b1">CAN_RDH0R_DATA4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cb8238c1f77ff904290afdc572b31bc">CAN_RDH0R_DATA4_Pos</a>)</td></tr>
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<tr class="separator:ga043ce7187baa93bc909445ec56a283b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dc7309c31cda93d05bb1fe1c923646c" id="r_ga4dc7309c31cda93d05bb1fe1c923646c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dc7309c31cda93d05bb1fe1c923646c">CAN_RDH0R_DATA4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga043ce7187baa93bc909445ec56a283b1">CAN_RDH0R_DATA4_Msk</a></td></tr>
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<tr class="separator:ga4dc7309c31cda93d05bb1fe1c923646c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafeef959f9d8913e402c9a08f964da52f" id="r_gafeef959f9d8913e402c9a08f964da52f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafeef959f9d8913e402c9a08f964da52f">CAN_RDH0R_DATA5_Pos</a>   (8U)</td></tr>
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<tr class="separator:gafeef959f9d8913e402c9a08f964da52f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a76bc6ca34c282e8d5e6d80de4d2ae6" id="r_ga1a76bc6ca34c282e8d5e6d80de4d2ae6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a76bc6ca34c282e8d5e6d80de4d2ae6">CAN_RDH0R_DATA5_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafeef959f9d8913e402c9a08f964da52f">CAN_RDH0R_DATA5_Pos</a>)</td></tr>
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<tr class="separator:ga1a76bc6ca34c282e8d5e6d80de4d2ae6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga577eba5ab3a66283f5c0837e91f1776a" id="r_ga577eba5ab3a66283f5c0837e91f1776a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga577eba5ab3a66283f5c0837e91f1776a">CAN_RDH0R_DATA5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a76bc6ca34c282e8d5e6d80de4d2ae6">CAN_RDH0R_DATA5_Msk</a></td></tr>
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<tr class="separator:ga577eba5ab3a66283f5c0837e91f1776a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e54ca30453b2103004ca2b87da2e052" id="r_ga0e54ca30453b2103004ca2b87da2e052"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e54ca30453b2103004ca2b87da2e052">CAN_RDH0R_DATA6_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga0e54ca30453b2103004ca2b87da2e052"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ea6c132f074602725c9d14d4a66826c" id="r_ga5ea6c132f074602725c9d14d4a66826c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ea6c132f074602725c9d14d4a66826c">CAN_RDH0R_DATA6_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e54ca30453b2103004ca2b87da2e052">CAN_RDH0R_DATA6_Pos</a>)</td></tr>
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<tr class="separator:ga5ea6c132f074602725c9d14d4a66826c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27a0bd49dc24e59b776ad5a00aabb97b" id="r_ga27a0bd49dc24e59b776ad5a00aabb97b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27a0bd49dc24e59b776ad5a00aabb97b">CAN_RDH0R_DATA6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ea6c132f074602725c9d14d4a66826c">CAN_RDH0R_DATA6_Msk</a></td></tr>
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<tr class="separator:ga27a0bd49dc24e59b776ad5a00aabb97b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga676e501253a8d78d74a13f9dbc87d222" id="r_ga676e501253a8d78d74a13f9dbc87d222"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga676e501253a8d78d74a13f9dbc87d222">CAN_RDH0R_DATA7_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga676e501253a8d78d74a13f9dbc87d222"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga167fa92520367130afbb5e929ff8b542" id="r_ga167fa92520367130afbb5e929ff8b542"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga167fa92520367130afbb5e929ff8b542">CAN_RDH0R_DATA7_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga676e501253a8d78d74a13f9dbc87d222">CAN_RDH0R_DATA7_Pos</a>)</td></tr>
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<tr class="separator:ga167fa92520367130afbb5e929ff8b542"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga243b8a3632812b2f8c7b447ed635ce5f" id="r_ga243b8a3632812b2f8c7b447ed635ce5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga243b8a3632812b2f8c7b447ed635ce5f">CAN_RDH0R_DATA7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga167fa92520367130afbb5e929ff8b542">CAN_RDH0R_DATA7_Msk</a></td></tr>
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<tr class="separator:ga243b8a3632812b2f8c7b447ed635ce5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga726ed3ef9d26e53ea346a23731e0e967" id="r_ga726ed3ef9d26e53ea346a23731e0e967"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga726ed3ef9d26e53ea346a23731e0e967">CAN_RI1R_RTR_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga726ed3ef9d26e53ea346a23731e0e967"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e9658541637a4332c1ccf67b34a8fb9" id="r_ga2e9658541637a4332c1ccf67b34a8fb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e9658541637a4332c1ccf67b34a8fb9">CAN_RI1R_RTR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga726ed3ef9d26e53ea346a23731e0e967">CAN_RI1R_RTR_Pos</a>)</td></tr>
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<tr class="separator:ga2e9658541637a4332c1ccf67b34a8fb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbd0ecd9579a339bffb95ea3b7c9f1e8" id="r_gafbd0ecd9579a339bffb95ea3b7c9f1e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbd0ecd9579a339bffb95ea3b7c9f1e8">CAN_RI1R_RTR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e9658541637a4332c1ccf67b34a8fb9">CAN_RI1R_RTR_Msk</a></td></tr>
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<tr class="separator:gafbd0ecd9579a339bffb95ea3b7c9f1e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0367ce97761605b4cdc45b529f791417" id="r_ga0367ce97761605b4cdc45b529f791417"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0367ce97761605b4cdc45b529f791417">CAN_RI1R_IDE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga0367ce97761605b4cdc45b529f791417"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68b6e874a467bca60ef46e3ffb30f098" id="r_ga68b6e874a467bca60ef46e3ffb30f098"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68b6e874a467bca60ef46e3ffb30f098">CAN_RI1R_IDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0367ce97761605b4cdc45b529f791417">CAN_RI1R_IDE_Pos</a>)</td></tr>
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<tr class="separator:ga68b6e874a467bca60ef46e3ffb30f098"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8dcedeb4250767a66a4d60c67e367cf8" id="r_ga8dcedeb4250767a66a4d60c67e367cf8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8dcedeb4250767a66a4d60c67e367cf8">CAN_RI1R_IDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga68b6e874a467bca60ef46e3ffb30f098">CAN_RI1R_IDE_Msk</a></td></tr>
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<tr class="separator:ga8dcedeb4250767a66a4d60c67e367cf8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd36dce59fa984a072c332c0fae7a29a" id="r_gafd36dce59fa984a072c332c0fae7a29a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd36dce59fa984a072c332c0fae7a29a">CAN_RI1R_EXID_Pos</a>   (3U)</td></tr>
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<tr class="separator:gafd36dce59fa984a072c332c0fae7a29a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f8b1261a02cdc318caab37e7cff0f5f" id="r_ga1f8b1261a02cdc318caab37e7cff0f5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f8b1261a02cdc318caab37e7cff0f5f">CAN_RI1R_EXID_Msk</a>   (0x3FFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafd36dce59fa984a072c332c0fae7a29a">CAN_RI1R_EXID_Pos</a>)</td></tr>
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<tr class="separator:ga1f8b1261a02cdc318caab37e7cff0f5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ca45b282f2582c91450d4e1204121cf" id="r_ga2ca45b282f2582c91450d4e1204121cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ca45b282f2582c91450d4e1204121cf">CAN_RI1R_EXID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f8b1261a02cdc318caab37e7cff0f5f">CAN_RI1R_EXID_Msk</a></td></tr>
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<tr class="separator:ga2ca45b282f2582c91450d4e1204121cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7488f084446b0c0907a5f4851f48d38c" id="r_ga7488f084446b0c0907a5f4851f48d38c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7488f084446b0c0907a5f4851f48d38c">CAN_RI1R_STID_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga7488f084446b0c0907a5f4851f48d38c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27b4d8511b43ff7f56e18c15c6b260e0" id="r_ga27b4d8511b43ff7f56e18c15c6b260e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27b4d8511b43ff7f56e18c15c6b260e0">CAN_RI1R_STID_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7488f084446b0c0907a5f4851f48d38c">CAN_RI1R_STID_Pos</a>)</td></tr>
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<tr class="separator:ga27b4d8511b43ff7f56e18c15c6b260e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f3c3aab0f24533821188d14901b3980" id="r_ga7f3c3aab0f24533821188d14901b3980"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f3c3aab0f24533821188d14901b3980">CAN_RI1R_STID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga27b4d8511b43ff7f56e18c15c6b260e0">CAN_RI1R_STID_Msk</a></td></tr>
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<tr class="separator:ga7f3c3aab0f24533821188d14901b3980"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2e0b7a55b05caab1a213c35742696a6" id="r_gab2e0b7a55b05caab1a213c35742696a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2e0b7a55b05caab1a213c35742696a6">CAN_RDT1R_DLC_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab2e0b7a55b05caab1a213c35742696a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa33d633807f57ecc34d45c20e704a330" id="r_gaa33d633807f57ecc34d45c20e704a330"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa33d633807f57ecc34d45c20e704a330">CAN_RDT1R_DLC_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab2e0b7a55b05caab1a213c35742696a6">CAN_RDT1R_DLC_Pos</a>)</td></tr>
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<tr class="separator:gaa33d633807f57ecc34d45c20e704a330"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga964b0fa7c70a24a74165c57b3486aae8" id="r_ga964b0fa7c70a24a74165c57b3486aae8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga964b0fa7c70a24a74165c57b3486aae8">CAN_RDT1R_DLC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa33d633807f57ecc34d45c20e704a330">CAN_RDT1R_DLC_Msk</a></td></tr>
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<tr class="separator:ga964b0fa7c70a24a74165c57b3486aae8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga683fd9390aff2459ef66760d02f7f654" id="r_ga683fd9390aff2459ef66760d02f7f654"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga683fd9390aff2459ef66760d02f7f654">CAN_RDT1R_FMI_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga683fd9390aff2459ef66760d02f7f654"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41ca9a71d5f237de7e4d758b2b5850b5" id="r_ga41ca9a71d5f237de7e4d758b2b5850b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41ca9a71d5f237de7e4d758b2b5850b5">CAN_RDT1R_FMI_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga683fd9390aff2459ef66760d02f7f654">CAN_RDT1R_FMI_Pos</a>)</td></tr>
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<tr class="separator:ga41ca9a71d5f237de7e4d758b2b5850b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7f72aec91130a20e3a855e78eabb48b" id="r_gaf7f72aec91130a20e3a855e78eabb48b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7f72aec91130a20e3a855e78eabb48b">CAN_RDT1R_FMI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga41ca9a71d5f237de7e4d758b2b5850b5">CAN_RDT1R_FMI_Msk</a></td></tr>
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<tr class="separator:gaf7f72aec91130a20e3a855e78eabb48b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a2fdfc1f548be70a30752803fea6a27" id="r_ga4a2fdfc1f548be70a30752803fea6a27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a2fdfc1f548be70a30752803fea6a27">CAN_RDT1R_TIME_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga4a2fdfc1f548be70a30752803fea6a27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22e450deb1ed7a778b47b4cebad44f42" id="r_ga22e450deb1ed7a778b47b4cebad44f42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22e450deb1ed7a778b47b4cebad44f42">CAN_RDT1R_TIME_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a2fdfc1f548be70a30752803fea6a27">CAN_RDT1R_TIME_Pos</a>)</td></tr>
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<tr class="separator:ga22e450deb1ed7a778b47b4cebad44f42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac112cba5a4cd0b541c1150263132c68a" id="r_gac112cba5a4cd0b541c1150263132c68a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac112cba5a4cd0b541c1150263132c68a">CAN_RDT1R_TIME</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga22e450deb1ed7a778b47b4cebad44f42">CAN_RDT1R_TIME_Msk</a></td></tr>
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<tr class="separator:gac112cba5a4cd0b541c1150263132c68a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5c0ebcd26923922b646df3064f4d5ad" id="r_gaa5c0ebcd26923922b646df3064f4d5ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5c0ebcd26923922b646df3064f4d5ad">CAN_RDL1R_DATA0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa5c0ebcd26923922b646df3064f4d5ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d11f01bf6ac61f279f5227e5cfa87ac" id="r_ga3d11f01bf6ac61f279f5227e5cfa87ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d11f01bf6ac61f279f5227e5cfa87ac">CAN_RDL1R_DATA0_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5c0ebcd26923922b646df3064f4d5ad">CAN_RDL1R_DATA0_Pos</a>)</td></tr>
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<tr class="separator:ga3d11f01bf6ac61f279f5227e5cfa87ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e399fed282a5aac0b25b059fcf04020" id="r_ga1e399fed282a5aac0b25b059fcf04020"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e399fed282a5aac0b25b059fcf04020">CAN_RDL1R_DATA0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d11f01bf6ac61f279f5227e5cfa87ac">CAN_RDL1R_DATA0_Msk</a></td></tr>
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<tr class="separator:ga1e399fed282a5aac0b25b059fcf04020"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac291bf56ea60efcd3123d4c89fcc00fb" id="r_gac291bf56ea60efcd3123d4c89fcc00fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac291bf56ea60efcd3123d4c89fcc00fb">CAN_RDL1R_DATA1_Pos</a>   (8U)</td></tr>
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<tr class="separator:gac291bf56ea60efcd3123d4c89fcc00fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2754a3d3971d890a60306c923f4c027d" id="r_ga2754a3d3971d890a60306c923f4c027d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2754a3d3971d890a60306c923f4c027d">CAN_RDL1R_DATA1_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac291bf56ea60efcd3123d4c89fcc00fb">CAN_RDL1R_DATA1_Pos</a>)</td></tr>
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<tr class="separator:ga2754a3d3971d890a60306c923f4c027d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27ec34e08f87e8836f32bbfed52e860a" id="r_ga27ec34e08f87e8836f32bbfed52e860a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27ec34e08f87e8836f32bbfed52e860a">CAN_RDL1R_DATA1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2754a3d3971d890a60306c923f4c027d">CAN_RDL1R_DATA1_Msk</a></td></tr>
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<tr class="separator:ga27ec34e08f87e8836f32bbfed52e860a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38f1bee2b3aac2261c4f9c5aa92550bc" id="r_ga38f1bee2b3aac2261c4f9c5aa92550bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38f1bee2b3aac2261c4f9c5aa92550bc">CAN_RDL1R_DATA2_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga38f1bee2b3aac2261c4f9c5aa92550bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5ea71525f58798512e56b01db47f6d5" id="r_gae5ea71525f58798512e56b01db47f6d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5ea71525f58798512e56b01db47f6d5">CAN_RDL1R_DATA2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga38f1bee2b3aac2261c4f9c5aa92550bc">CAN_RDL1R_DATA2_Pos</a>)</td></tr>
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<tr class="separator:gae5ea71525f58798512e56b01db47f6d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea34eded40932d364743969643a598c4" id="r_gaea34eded40932d364743969643a598c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea34eded40932d364743969643a598c4">CAN_RDL1R_DATA2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae5ea71525f58798512e56b01db47f6d5">CAN_RDL1R_DATA2_Msk</a></td></tr>
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<tr class="separator:gaea34eded40932d364743969643a598c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f201d587103efa2fc6da443415d7127" id="r_ga7f201d587103efa2fc6da443415d7127"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f201d587103efa2fc6da443415d7127">CAN_RDL1R_DATA3_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga7f201d587103efa2fc6da443415d7127"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02684a0300f1d9e9c803b5afefb193fc" id="r_ga02684a0300f1d9e9c803b5afefb193fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02684a0300f1d9e9c803b5afefb193fc">CAN_RDL1R_DATA3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f201d587103efa2fc6da443415d7127">CAN_RDL1R_DATA3_Pos</a>)</td></tr>
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<tr class="separator:ga02684a0300f1d9e9c803b5afefb193fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80bfe3e724b28e8d2a5b7ac4393212cf" id="r_ga80bfe3e724b28e8d2a5b7ac4393212cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80bfe3e724b28e8d2a5b7ac4393212cf">CAN_RDL1R_DATA3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga02684a0300f1d9e9c803b5afefb193fc">CAN_RDL1R_DATA3_Msk</a></td></tr>
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<tr class="separator:ga80bfe3e724b28e8d2a5b7ac4393212cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48e5ea8ab1e1cf135a10b2dbc69932f2" id="r_ga48e5ea8ab1e1cf135a10b2dbc69932f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48e5ea8ab1e1cf135a10b2dbc69932f2">CAN_RDH1R_DATA4_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga48e5ea8ab1e1cf135a10b2dbc69932f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e0ca00fb558f95f4f692d5f7b90d157" id="r_ga0e0ca00fb558f95f4f692d5f7b90d157"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e0ca00fb558f95f4f692d5f7b90d157">CAN_RDH1R_DATA4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48e5ea8ab1e1cf135a10b2dbc69932f2">CAN_RDH1R_DATA4_Pos</a>)</td></tr>
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<tr class="separator:ga0e0ca00fb558f95f4f692d5f7b90d157"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc2a55c1b5195cf043ef33e79d736255" id="r_gafc2a55c1b5195cf043ef33e79d736255"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc2a55c1b5195cf043ef33e79d736255">CAN_RDH1R_DATA4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e0ca00fb558f95f4f692d5f7b90d157">CAN_RDH1R_DATA4_Msk</a></td></tr>
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<tr class="separator:gafc2a55c1b5195cf043ef33e79d736255"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacb82a6a71a2687b303c54a5c3aca105" id="r_gaacb82a6a71a2687b303c54a5c3aca105"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacb82a6a71a2687b303c54a5c3aca105">CAN_RDH1R_DATA5_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaacb82a6a71a2687b303c54a5c3aca105"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga247617fd1c2c8daa148b3ed059f0603a" id="r_ga247617fd1c2c8daa148b3ed059f0603a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga247617fd1c2c8daa148b3ed059f0603a">CAN_RDH1R_DATA5_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaacb82a6a71a2687b303c54a5c3aca105">CAN_RDH1R_DATA5_Pos</a>)</td></tr>
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<tr class="separator:ga247617fd1c2c8daa148b3ed059f0603a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81d25a1ea5ad28e7db4a2adbb8a651ad" id="r_ga81d25a1ea5ad28e7db4a2adbb8a651ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81d25a1ea5ad28e7db4a2adbb8a651ad">CAN_RDH1R_DATA5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga247617fd1c2c8daa148b3ed059f0603a">CAN_RDH1R_DATA5_Msk</a></td></tr>
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<tr class="separator:ga81d25a1ea5ad28e7db4a2adbb8a651ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab2ec9fa28c3b6f72ed102d5d255e875" id="r_gaab2ec9fa28c3b6f72ed102d5d255e875"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab2ec9fa28c3b6f72ed102d5d255e875">CAN_RDH1R_DATA6_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaab2ec9fa28c3b6f72ed102d5d255e875"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5eeec37fc704ce7cf1c9ef92f6d87635" id="r_ga5eeec37fc704ce7cf1c9ef92f6d87635"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5eeec37fc704ce7cf1c9ef92f6d87635">CAN_RDH1R_DATA6_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab2ec9fa28c3b6f72ed102d5d255e875">CAN_RDH1R_DATA6_Pos</a>)</td></tr>
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<tr class="separator:ga5eeec37fc704ce7cf1c9ef92f6d87635"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39212ea40388510bde1931f7b3a064ae" id="r_ga39212ea40388510bde1931f7b3a064ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39212ea40388510bde1931f7b3a064ae">CAN_RDH1R_DATA6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5eeec37fc704ce7cf1c9ef92f6d87635">CAN_RDH1R_DATA6_Msk</a></td></tr>
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<tr class="separator:ga39212ea40388510bde1931f7b3a064ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga021f76c67a2d07b56c4e10cd56cc416a" id="r_ga021f76c67a2d07b56c4e10cd56cc416a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga021f76c67a2d07b56c4e10cd56cc416a">CAN_RDH1R_DATA7_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga021f76c67a2d07b56c4e10cd56cc416a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9e7a5ddb046143d3ca7c85ddb9c94c0" id="r_gad9e7a5ddb046143d3ca7c85ddb9c94c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9e7a5ddb046143d3ca7c85ddb9c94c0">CAN_RDH1R_DATA7_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga021f76c67a2d07b56c4e10cd56cc416a">CAN_RDH1R_DATA7_Pos</a>)</td></tr>
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<tr class="separator:gad9e7a5ddb046143d3ca7c85ddb9c94c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdfbb90b5ef2ac1e7f23a5f15c0287eb" id="r_gafdfbb90b5ef2ac1e7f23a5f15c0287eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdfbb90b5ef2ac1e7f23a5f15c0287eb">CAN_RDH1R_DATA7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad9e7a5ddb046143d3ca7c85ddb9c94c0">CAN_RDH1R_DATA7_Msk</a></td></tr>
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<tr class="separator:gafdfbb90b5ef2ac1e7f23a5f15c0287eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d07843af8269762b43ed1bef5fc29b3" id="r_ga8d07843af8269762b43ed1bef5fc29b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d07843af8269762b43ed1bef5fc29b3">CAN_FMR_FINIT_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8d07843af8269762b43ed1bef5fc29b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99a8549f1c1784779e00b257c216102d" id="r_ga99a8549f1c1784779e00b257c216102d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99a8549f1c1784779e00b257c216102d">CAN_FMR_FINIT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d07843af8269762b43ed1bef5fc29b3">CAN_FMR_FINIT_Pos</a>)</td></tr>
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<tr class="separator:ga99a8549f1c1784779e00b257c216102d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5eb5b835ee11a78bd391b9d1049f2549" id="r_ga5eb5b835ee11a78bd391b9d1049f2549"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5eb5b835ee11a78bd391b9d1049f2549">CAN_FMR_FINIT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga99a8549f1c1784779e00b257c216102d">CAN_FMR_FINIT_Msk</a></td></tr>
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<tr class="separator:ga5eb5b835ee11a78bd391b9d1049f2549"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaaea537f2e7bfc1d90c43a60d12145b7" id="r_gaaaea537f2e7bfc1d90c43a60d12145b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaaea537f2e7bfc1d90c43a60d12145b7">CAN_FMR_CAN2SB_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaaaea537f2e7bfc1d90c43a60d12145b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92c82386fd3904c98b94f78cfb9570d2" id="r_ga92c82386fd3904c98b94f78cfb9570d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92c82386fd3904c98b94f78cfb9570d2">CAN_FMR_CAN2SB_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaaea537f2e7bfc1d90c43a60d12145b7">CAN_FMR_CAN2SB_Pos</a>)</td></tr>
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<tr class="separator:ga92c82386fd3904c98b94f78cfb9570d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3753c67c075a4508104d112ef9047f21" id="r_ga3753c67c075a4508104d112ef9047f21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3753c67c075a4508104d112ef9047f21">CAN_FMR_CAN2SB</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga92c82386fd3904c98b94f78cfb9570d2">CAN_FMR_CAN2SB_Msk</a></td></tr>
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<tr class="memitem:gaa97dffd3da7f8927e2168a6dce9d8312" id="r_gaa97dffd3da7f8927e2168a6dce9d8312"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa97dffd3da7f8927e2168a6dce9d8312">CAN_FM1R_FBM_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga97376a7949c1758c1f294cc9a85cbe8c" id="r_ga97376a7949c1758c1f294cc9a85cbe8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97376a7949c1758c1f294cc9a85cbe8c">CAN_FM1R_FBM_Msk</a>   (0xFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa97dffd3da7f8927e2168a6dce9d8312">CAN_FM1R_FBM_Pos</a>)</td></tr>
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<tr class="separator:ga97376a7949c1758c1f294cc9a85cbe8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga481099e17a895e92cfbcfca617d52860" id="r_ga481099e17a895e92cfbcfca617d52860"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga481099e17a895e92cfbcfca617d52860">CAN_FM1R_FBM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97376a7949c1758c1f294cc9a85cbe8c">CAN_FM1R_FBM_Msk</a></td></tr>
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<tr class="memitem:gab47e86b4f2e3c77569cfe84fbcb8806b" id="r_gab47e86b4f2e3c77569cfe84fbcb8806b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab47e86b4f2e3c77569cfe84fbcb8806b">CAN_FM1R_FBM0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab47e86b4f2e3c77569cfe84fbcb8806b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19e1fd75a24ae366d58b0a18e15f38bf" id="r_ga19e1fd75a24ae366d58b0a18e15f38bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19e1fd75a24ae366d58b0a18e15f38bf">CAN_FM1R_FBM0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab47e86b4f2e3c77569cfe84fbcb8806b">CAN_FM1R_FBM0_Pos</a>)</td></tr>
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<tr class="separator:ga19e1fd75a24ae366d58b0a18e15f38bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d95ff05ed6ef9a38e9af9c0d3db3687" id="r_ga2d95ff05ed6ef9a38e9af9c0d3db3687"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d95ff05ed6ef9a38e9af9c0d3db3687">CAN_FM1R_FBM0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga19e1fd75a24ae366d58b0a18e15f38bf">CAN_FM1R_FBM0_Msk</a></td></tr>
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<tr class="separator:ga2d95ff05ed6ef9a38e9af9c0d3db3687"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56b3a50f8a5df07e09f78d165ae0ebb0" id="r_ga56b3a50f8a5df07e09f78d165ae0ebb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56b3a50f8a5df07e09f78d165ae0ebb0">CAN_FM1R_FBM1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga56b3a50f8a5df07e09f78d165ae0ebb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad57540467b1e1e98c24df335d72b6715" id="r_gad57540467b1e1e98c24df335d72b6715"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad57540467b1e1e98c24df335d72b6715">CAN_FM1R_FBM1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga56b3a50f8a5df07e09f78d165ae0ebb0">CAN_FM1R_FBM1_Pos</a>)</td></tr>
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<tr class="separator:gad57540467b1e1e98c24df335d72b6715"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2839d73344a7601aa22b5ed3fc0e5d1" id="r_gac2839d73344a7601aa22b5ed3fc0e5d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2839d73344a7601aa22b5ed3fc0e5d1">CAN_FM1R_FBM1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad57540467b1e1e98c24df335d72b6715">CAN_FM1R_FBM1_Msk</a></td></tr>
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<tr class="memitem:ga9893bef42453161269747598ec908d49" id="r_ga9893bef42453161269747598ec908d49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9893bef42453161269747598ec908d49">CAN_FM1R_FBM2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga9893bef42453161269747598ec908d49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab036323d5ff180c94cb011bda0e93738" id="r_gab036323d5ff180c94cb011bda0e93738"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab036323d5ff180c94cb011bda0e93738">CAN_FM1R_FBM2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9893bef42453161269747598ec908d49">CAN_FM1R_FBM2_Pos</a>)</td></tr>
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<tr class="separator:gab036323d5ff180c94cb011bda0e93738"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ba7963ac4eb5b936c444258c13f8940" id="r_ga7ba7963ac4eb5b936c444258c13f8940"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ba7963ac4eb5b936c444258c13f8940">CAN_FM1R_FBM2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab036323d5ff180c94cb011bda0e93738">CAN_FM1R_FBM2_Msk</a></td></tr>
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<tr class="separator:ga7ba7963ac4eb5b936c444258c13f8940"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga612d9e0e776abfcdbc2b24a964d6ab6e" id="r_ga612d9e0e776abfcdbc2b24a964d6ab6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga612d9e0e776abfcdbc2b24a964d6ab6e">CAN_FM1R_FBM3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga612d9e0e776abfcdbc2b24a964d6ab6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8514f94421b8d4665c84a5e09ea814b6" id="r_ga8514f94421b8d4665c84a5e09ea814b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8514f94421b8d4665c84a5e09ea814b6">CAN_FM1R_FBM3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga612d9e0e776abfcdbc2b24a964d6ab6e">CAN_FM1R_FBM3_Pos</a>)</td></tr>
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<tr class="separator:ga8514f94421b8d4665c84a5e09ea814b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d129b27c2af41ae39e606e802a53386" id="r_ga2d129b27c2af41ae39e606e802a53386"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d129b27c2af41ae39e606e802a53386">CAN_FM1R_FBM3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8514f94421b8d4665c84a5e09ea814b6">CAN_FM1R_FBM3_Msk</a></td></tr>
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<tr class="separator:ga2d129b27c2af41ae39e606e802a53386"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb58de50d9b0a1508617d885f052d7a6" id="r_gacb58de50d9b0a1508617d885f052d7a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb58de50d9b0a1508617d885f052d7a6">CAN_FM1R_FBM4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gacb58de50d9b0a1508617d885f052d7a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bca8d2dab6ca215db7dfe45702c9c88" id="r_ga3bca8d2dab6ca215db7dfe45702c9c88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bca8d2dab6ca215db7dfe45702c9c88">CAN_FM1R_FBM4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacb58de50d9b0a1508617d885f052d7a6">CAN_FM1R_FBM4_Pos</a>)</td></tr>
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<tr class="separator:ga3bca8d2dab6ca215db7dfe45702c9c88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0c94e5f4dcceea510fc72b86128aff3" id="r_gaf0c94e5f4dcceea510fc72b86128aff3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0c94e5f4dcceea510fc72b86128aff3">CAN_FM1R_FBM4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bca8d2dab6ca215db7dfe45702c9c88">CAN_FM1R_FBM4_Msk</a></td></tr>
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<tr class="separator:gaf0c94e5f4dcceea510fc72b86128aff3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b8f80f23a5ab8f322c9b4b441a8d768" id="r_ga3b8f80f23a5ab8f322c9b4b441a8d768"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b8f80f23a5ab8f322c9b4b441a8d768">CAN_FM1R_FBM5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga3b8f80f23a5ab8f322c9b4b441a8d768"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8534298a873d6eeba40f67ccd8e44dc" id="r_gad8534298a873d6eeba40f67ccd8e44dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8534298a873d6eeba40f67ccd8e44dc">CAN_FM1R_FBM5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b8f80f23a5ab8f322c9b4b441a8d768">CAN_FM1R_FBM5_Pos</a>)</td></tr>
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<tr class="separator:gad8534298a873d6eeba40f67ccd8e44dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d7fb7c366544a1ef7a85481d3e6325d" id="r_ga2d7fb7c366544a1ef7a85481d3e6325d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d7fb7c366544a1ef7a85481d3e6325d">CAN_FM1R_FBM5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad8534298a873d6eeba40f67ccd8e44dc">CAN_FM1R_FBM5_Msk</a></td></tr>
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<tr class="separator:ga2d7fb7c366544a1ef7a85481d3e6325d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4a556397deec72a65aec5ec5600e16f" id="r_gad4a556397deec72a65aec5ec5600e16f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4a556397deec72a65aec5ec5600e16f">CAN_FM1R_FBM6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gad4a556397deec72a65aec5ec5600e16f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e635abf1f1fda09814600ac218b25a5" id="r_ga6e635abf1f1fda09814600ac218b25a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e635abf1f1fda09814600ac218b25a5">CAN_FM1R_FBM6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad4a556397deec72a65aec5ec5600e16f">CAN_FM1R_FBM6_Pos</a>)</td></tr>
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<tr class="separator:ga6e635abf1f1fda09814600ac218b25a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ff70e74447679a0d1cde1aa69ea2db1" id="r_ga3ff70e74447679a0d1cde1aa69ea2db1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ff70e74447679a0d1cde1aa69ea2db1">CAN_FM1R_FBM6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e635abf1f1fda09814600ac218b25a5">CAN_FM1R_FBM6_Msk</a></td></tr>
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<tr class="separator:ga3ff70e74447679a0d1cde1aa69ea2db1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2d58da6b63e9ebe66d43e438f0df884" id="r_gaf2d58da6b63e9ebe66d43e438f0df884"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2d58da6b63e9ebe66d43e438f0df884">CAN_FM1R_FBM7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaf2d58da6b63e9ebe66d43e438f0df884"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e697f5e347652a49756219c13e6cc89" id="r_ga0e697f5e347652a49756219c13e6cc89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e697f5e347652a49756219c13e6cc89">CAN_FM1R_FBM7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2d58da6b63e9ebe66d43e438f0df884">CAN_FM1R_FBM7_Pos</a>)</td></tr>
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<tr class="separator:ga0e697f5e347652a49756219c13e6cc89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga657fc12fd334bc626b2eb53fb03457b0" id="r_ga657fc12fd334bc626b2eb53fb03457b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga657fc12fd334bc626b2eb53fb03457b0">CAN_FM1R_FBM7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e697f5e347652a49756219c13e6cc89">CAN_FM1R_FBM7_Msk</a></td></tr>
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<tr class="separator:ga657fc12fd334bc626b2eb53fb03457b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30b41b013fad0569137363aa33b5fd8e" id="r_ga30b41b013fad0569137363aa33b5fd8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30b41b013fad0569137363aa33b5fd8e">CAN_FM1R_FBM8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga30b41b013fad0569137363aa33b5fd8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b3e86a2ff5df79cb0d1fc1d09da5309" id="r_ga1b3e86a2ff5df79cb0d1fc1d09da5309"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b3e86a2ff5df79cb0d1fc1d09da5309">CAN_FM1R_FBM8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30b41b013fad0569137363aa33b5fd8e">CAN_FM1R_FBM8_Pos</a>)</td></tr>
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<tr class="separator:ga1b3e86a2ff5df79cb0d1fc1d09da5309"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab6bc390ed9a658014fd09fd1073e3037" id="r_gab6bc390ed9a658014fd09fd1073e3037"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6bc390ed9a658014fd09fd1073e3037">CAN_FM1R_FBM8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b3e86a2ff5df79cb0d1fc1d09da5309">CAN_FM1R_FBM8_Msk</a></td></tr>
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<tr class="separator:gab6bc390ed9a658014fd09fd1073e3037"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae891964bdca74710cfb7a1587b9c75a2" id="r_gae891964bdca74710cfb7a1587b9c75a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae891964bdca74710cfb7a1587b9c75a2">CAN_FM1R_FBM9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gae891964bdca74710cfb7a1587b9c75a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9787e28f4d47535624b593b042e7aef" id="r_gac9787e28f4d47535624b593b042e7aef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9787e28f4d47535624b593b042e7aef">CAN_FM1R_FBM9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae891964bdca74710cfb7a1587b9c75a2">CAN_FM1R_FBM9_Pos</a>)</td></tr>
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<tr class="separator:gac9787e28f4d47535624b593b042e7aef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga375758246b99234dda725b7c64daff32" id="r_ga375758246b99234dda725b7c64daff32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga375758246b99234dda725b7c64daff32">CAN_FM1R_FBM9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9787e28f4d47535624b593b042e7aef">CAN_FM1R_FBM9_Msk</a></td></tr>
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<tr class="memitem:gab4c4d40f98e3c5e6116b323184afca0a" id="r_gab4c4d40f98e3c5e6116b323184afca0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4c4d40f98e3c5e6116b323184afca0a">CAN_FM1R_FBM10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gab4c4d40f98e3c5e6116b323184afca0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb10a1a029fdb320217c7443225df7f8" id="r_gaeb10a1a029fdb320217c7443225df7f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb10a1a029fdb320217c7443225df7f8">CAN_FM1R_FBM10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab4c4d40f98e3c5e6116b323184afca0a">CAN_FM1R_FBM10_Pos</a>)</td></tr>
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<tr class="separator:gaeb10a1a029fdb320217c7443225df7f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a98c6bde07c570463b6c0e32c0f6805" id="r_ga0a98c6bde07c570463b6c0e32c0f6805"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a98c6bde07c570463b6c0e32c0f6805">CAN_FM1R_FBM10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb10a1a029fdb320217c7443225df7f8">CAN_FM1R_FBM10_Msk</a></td></tr>
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<tr class="separator:ga0a98c6bde07c570463b6c0e32c0f6805"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8310bf4c9b121dad00152f0d9e0aaf3d" id="r_ga8310bf4c9b121dad00152f0d9e0aaf3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8310bf4c9b121dad00152f0d9e0aaf3d">CAN_FM1R_FBM11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga8310bf4c9b121dad00152f0d9e0aaf3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa8a7616c4e1d6b08a96a629877107ad" id="r_gaaa8a7616c4e1d6b08a96a629877107ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa8a7616c4e1d6b08a96a629877107ad">CAN_FM1R_FBM11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8310bf4c9b121dad00152f0d9e0aaf3d">CAN_FM1R_FBM11_Pos</a>)</td></tr>
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<tr class="separator:gaaa8a7616c4e1d6b08a96a629877107ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab88796333c19954176ef77208cae4964" id="r_gab88796333c19954176ef77208cae4964"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab88796333c19954176ef77208cae4964">CAN_FM1R_FBM11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa8a7616c4e1d6b08a96a629877107ad">CAN_FM1R_FBM11_Msk</a></td></tr>
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<tr class="separator:gab88796333c19954176ef77208cae4964"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c1c28f5a8c8f6e7c1203c3268307e7d" id="r_ga0c1c28f5a8c8f6e7c1203c3268307e7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c1c28f5a8c8f6e7c1203c3268307e7d">CAN_FM1R_FBM12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga0c1c28f5a8c8f6e7c1203c3268307e7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8b7c4c9581b2f876fe0cdf0bba3edaf" id="r_gae8b7c4c9581b2f876fe0cdf0bba3edaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8b7c4c9581b2f876fe0cdf0bba3edaf">CAN_FM1R_FBM12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c1c28f5a8c8f6e7c1203c3268307e7d">CAN_FM1R_FBM12_Pos</a>)</td></tr>
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<tr class="separator:gae8b7c4c9581b2f876fe0cdf0bba3edaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga858eaac0a8e23c03e13e5c1736bf9842" id="r_ga858eaac0a8e23c03e13e5c1736bf9842"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga858eaac0a8e23c03e13e5c1736bf9842">CAN_FM1R_FBM12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae8b7c4c9581b2f876fe0cdf0bba3edaf">CAN_FM1R_FBM12_Msk</a></td></tr>
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<tr class="separator:ga858eaac0a8e23c03e13e5c1736bf9842"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga510dd73a783e59a7d85c00d8190c89db" id="r_ga510dd73a783e59a7d85c00d8190c89db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga510dd73a783e59a7d85c00d8190c89db">CAN_FM1R_FBM13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga510dd73a783e59a7d85c00d8190c89db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13e0f2dc1023e882b4f2392c68444858" id="r_ga13e0f2dc1023e882b4f2392c68444858"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13e0f2dc1023e882b4f2392c68444858">CAN_FM1R_FBM13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga510dd73a783e59a7d85c00d8190c89db">CAN_FM1R_FBM13_Pos</a>)</td></tr>
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<tr class="separator:ga13e0f2dc1023e882b4f2392c68444858"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf03b553802edd3ae23b70e97228b6dcc" id="r_gaf03b553802edd3ae23b70e97228b6dcc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf03b553802edd3ae23b70e97228b6dcc">CAN_FM1R_FBM13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga13e0f2dc1023e882b4f2392c68444858">CAN_FM1R_FBM13_Msk</a></td></tr>
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<tr class="separator:gaf03b553802edd3ae23b70e97228b6dcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b3286a1f53a442b35a01c37ea2f1f08" id="r_ga6b3286a1f53a442b35a01c37ea2f1f08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b3286a1f53a442b35a01c37ea2f1f08">CAN_FM1R_FBM14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga6b3286a1f53a442b35a01c37ea2f1f08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bc6cdb01d2d74ae091d20b682ceb0e3" id="r_ga0bc6cdb01d2d74ae091d20b682ceb0e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bc6cdb01d2d74ae091d20b682ceb0e3">CAN_FM1R_FBM14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b3286a1f53a442b35a01c37ea2f1f08">CAN_FM1R_FBM14_Pos</a>)</td></tr>
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<tr class="separator:ga0bc6cdb01d2d74ae091d20b682ceb0e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae348cc5bec6eecd8a188c3e90a9618d1" id="r_gae348cc5bec6eecd8a188c3e90a9618d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae348cc5bec6eecd8a188c3e90a9618d1">CAN_FM1R_FBM14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bc6cdb01d2d74ae091d20b682ceb0e3">CAN_FM1R_FBM14_Msk</a></td></tr>
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<tr class="separator:gae348cc5bec6eecd8a188c3e90a9618d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa1a315f40ac71ced3066bf3edd9b459" id="r_gafa1a315f40ac71ced3066bf3edd9b459"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa1a315f40ac71ced3066bf3edd9b459">CAN_FM1R_FBM15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gafa1a315f40ac71ced3066bf3edd9b459"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d59e547e543eeddb35d6d003b18458c" id="r_ga6d59e547e543eeddb35d6d003b18458c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d59e547e543eeddb35d6d003b18458c">CAN_FM1R_FBM15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafa1a315f40ac71ced3066bf3edd9b459">CAN_FM1R_FBM15_Pos</a>)</td></tr>
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<tr class="separator:ga6d59e547e543eeddb35d6d003b18458c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga815c710d287cec5c46a901d01e4cac76" id="r_ga815c710d287cec5c46a901d01e4cac76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga815c710d287cec5c46a901d01e4cac76">CAN_FM1R_FBM15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d59e547e543eeddb35d6d003b18458c">CAN_FM1R_FBM15_Msk</a></td></tr>
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<tr class="separator:ga815c710d287cec5c46a901d01e4cac76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a18fbe03eb8d83dc877be06ecdc7810" id="r_ga7a18fbe03eb8d83dc877be06ecdc7810"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a18fbe03eb8d83dc877be06ecdc7810">CAN_FM1R_FBM16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga7a18fbe03eb8d83dc877be06ecdc7810"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd51db2c7330341bf43bb888e63a61f5" id="r_gafd51db2c7330341bf43bb888e63a61f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd51db2c7330341bf43bb888e63a61f5">CAN_FM1R_FBM16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a18fbe03eb8d83dc877be06ecdc7810">CAN_FM1R_FBM16_Pos</a>)</td></tr>
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<tr class="separator:gafd51db2c7330341bf43bb888e63a61f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6500fcdf1baf5d5019364ad155e30bf0" id="r_ga6500fcdf1baf5d5019364ad155e30bf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6500fcdf1baf5d5019364ad155e30bf0">CAN_FM1R_FBM16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafd51db2c7330341bf43bb888e63a61f5">CAN_FM1R_FBM16_Msk</a></td></tr>
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<tr class="separator:ga6500fcdf1baf5d5019364ad155e30bf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5b340bc770061dc909bbf5761db8352" id="r_gaf5b340bc770061dc909bbf5761db8352"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5b340bc770061dc909bbf5761db8352">CAN_FM1R_FBM17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gaf5b340bc770061dc909bbf5761db8352"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54acc06d013985e059388599e2df40b7" id="r_ga54acc06d013985e059388599e2df40b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54acc06d013985e059388599e2df40b7">CAN_FM1R_FBM17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5b340bc770061dc909bbf5761db8352">CAN_FM1R_FBM17_Pos</a>)</td></tr>
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<tr class="separator:ga54acc06d013985e059388599e2df40b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga698a1a5cf309ba539973ad61a08ed531" id="r_ga698a1a5cf309ba539973ad61a08ed531"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga698a1a5cf309ba539973ad61a08ed531">CAN_FM1R_FBM17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga54acc06d013985e059388599e2df40b7">CAN_FM1R_FBM17_Msk</a></td></tr>
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<tr class="separator:ga698a1a5cf309ba539973ad61a08ed531"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7c2e03e37aa98be8846eb3582a59515" id="r_gaa7c2e03e37aa98be8846eb3582a59515"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7c2e03e37aa98be8846eb3582a59515">CAN_FM1R_FBM18_Pos</a>   (18U)</td></tr>
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<tr class="separator:gaa7c2e03e37aa98be8846eb3582a59515"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7251ea74eaf728ad4538cd5a6ac34eaa" id="r_ga7251ea74eaf728ad4538cd5a6ac34eaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7251ea74eaf728ad4538cd5a6ac34eaa">CAN_FM1R_FBM18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7c2e03e37aa98be8846eb3582a59515">CAN_FM1R_FBM18_Pos</a>)</td></tr>
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<tr class="separator:ga7251ea74eaf728ad4538cd5a6ac34eaa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa47585a76a3ddf465abad7176e993ca1" id="r_gaa47585a76a3ddf465abad7176e993ca1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa47585a76a3ddf465abad7176e993ca1">CAN_FM1R_FBM18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7251ea74eaf728ad4538cd5a6ac34eaa">CAN_FM1R_FBM18_Msk</a></td></tr>
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<tr class="separator:gaa47585a76a3ddf465abad7176e993ca1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga728ea8bee75db988971d2f69cef3aa9a" id="r_ga728ea8bee75db988971d2f69cef3aa9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga728ea8bee75db988971d2f69cef3aa9a">CAN_FM1R_FBM19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga728ea8bee75db988971d2f69cef3aa9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga185b29bf8e41d61399645ccab8efdf07" id="r_ga185b29bf8e41d61399645ccab8efdf07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga185b29bf8e41d61399645ccab8efdf07">CAN_FM1R_FBM19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga728ea8bee75db988971d2f69cef3aa9a">CAN_FM1R_FBM19_Pos</a>)</td></tr>
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<tr class="separator:ga185b29bf8e41d61399645ccab8efdf07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70c9e6ce3b2e262912480c533cb94c30" id="r_ga70c9e6ce3b2e262912480c533cb94c30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70c9e6ce3b2e262912480c533cb94c30">CAN_FM1R_FBM19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga185b29bf8e41d61399645ccab8efdf07">CAN_FM1R_FBM19_Msk</a></td></tr>
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<tr class="separator:ga70c9e6ce3b2e262912480c533cb94c30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae918f1bdbe01f6350fe05cad4d2c07fc" id="r_gae918f1bdbe01f6350fe05cad4d2c07fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae918f1bdbe01f6350fe05cad4d2c07fc">CAN_FM1R_FBM20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gae918f1bdbe01f6350fe05cad4d2c07fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3557afecc8db6dab2c8ab6a19a76b245" id="r_ga3557afecc8db6dab2c8ab6a19a76b245"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3557afecc8db6dab2c8ab6a19a76b245">CAN_FM1R_FBM20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae918f1bdbe01f6350fe05cad4d2c07fc">CAN_FM1R_FBM20_Pos</a>)</td></tr>
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<tr class="separator:ga3557afecc8db6dab2c8ab6a19a76b245"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4af2f860f3d7c3bf3509daf366143baf" id="r_ga4af2f860f3d7c3bf3509daf366143baf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4af2f860f3d7c3bf3509daf366143baf">CAN_FM1R_FBM20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3557afecc8db6dab2c8ab6a19a76b245">CAN_FM1R_FBM20_Msk</a></td></tr>
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<tr class="separator:ga4af2f860f3d7c3bf3509daf366143baf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7890f90e73ef96b5497aeca708dd950a" id="r_ga7890f90e73ef96b5497aeca708dd950a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7890f90e73ef96b5497aeca708dd950a">CAN_FM1R_FBM21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga7890f90e73ef96b5497aeca708dd950a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c4575301b441f99be4fecfbdc0c06a5" id="r_ga4c4575301b441f99be4fecfbdc0c06a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c4575301b441f99be4fecfbdc0c06a5">CAN_FM1R_FBM21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7890f90e73ef96b5497aeca708dd950a">CAN_FM1R_FBM21_Pos</a>)</td></tr>
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<tr class="separator:ga4c4575301b441f99be4fecfbdc0c06a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bfdcf62b11bffb9afbee7f6258f089b" id="r_ga9bfdcf62b11bffb9afbee7f6258f089b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bfdcf62b11bffb9afbee7f6258f089b">CAN_FM1R_FBM21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c4575301b441f99be4fecfbdc0c06a5">CAN_FM1R_FBM21_Msk</a></td></tr>
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<tr class="separator:ga9bfdcf62b11bffb9afbee7f6258f089b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e18237e288612926c6e8855345b2d47" id="r_ga5e18237e288612926c6e8855345b2d47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e18237e288612926c6e8855345b2d47">CAN_FM1R_FBM22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga5e18237e288612926c6e8855345b2d47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad10cf074d53c11a4700ad7983e2ba34" id="r_gaad10cf074d53c11a4700ad7983e2ba34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad10cf074d53c11a4700ad7983e2ba34">CAN_FM1R_FBM22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e18237e288612926c6e8855345b2d47">CAN_FM1R_FBM22_Pos</a>)</td></tr>
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<tr class="separator:gaad10cf074d53c11a4700ad7983e2ba34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67e71ecc049fe1c882be5e03aaecdc01" id="r_ga67e71ecc049fe1c882be5e03aaecdc01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67e71ecc049fe1c882be5e03aaecdc01">CAN_FM1R_FBM22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaad10cf074d53c11a4700ad7983e2ba34">CAN_FM1R_FBM22_Msk</a></td></tr>
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<tr class="separator:ga67e71ecc049fe1c882be5e03aaecdc01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ced626c3b41a506cd8cd737c03fe787" id="r_ga1ced626c3b41a506cd8cd737c03fe787"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ced626c3b41a506cd8cd737c03fe787">CAN_FM1R_FBM23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga1ced626c3b41a506cd8cd737c03fe787"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d600617dc97adc1e75a2abcf1909d3b" id="r_ga3d600617dc97adc1e75a2abcf1909d3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d600617dc97adc1e75a2abcf1909d3b">CAN_FM1R_FBM23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ced626c3b41a506cd8cd737c03fe787">CAN_FM1R_FBM23_Pos</a>)</td></tr>
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<tr class="separator:ga3d600617dc97adc1e75a2abcf1909d3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70ac1d53ad6dbc162272b92aa704eff4" id="r_ga70ac1d53ad6dbc162272b92aa704eff4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70ac1d53ad6dbc162272b92aa704eff4">CAN_FM1R_FBM23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d600617dc97adc1e75a2abcf1909d3b">CAN_FM1R_FBM23_Msk</a></td></tr>
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<tr class="separator:ga70ac1d53ad6dbc162272b92aa704eff4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea93cbe9b69f821ed9475b0585c15637" id="r_gaea93cbe9b69f821ed9475b0585c15637"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea93cbe9b69f821ed9475b0585c15637">CAN_FM1R_FBM24_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaea93cbe9b69f821ed9475b0585c15637"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d68bf08a503f10fa7c9728ddafa8ed7" id="r_ga7d68bf08a503f10fa7c9728ddafa8ed7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d68bf08a503f10fa7c9728ddafa8ed7">CAN_FM1R_FBM24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea93cbe9b69f821ed9475b0585c15637">CAN_FM1R_FBM24_Pos</a>)</td></tr>
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<tr class="separator:ga7d68bf08a503f10fa7c9728ddafa8ed7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2befceefa1b4600adb96b1150a738dcf" id="r_ga2befceefa1b4600adb96b1150a738dcf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2befceefa1b4600adb96b1150a738dcf">CAN_FM1R_FBM24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d68bf08a503f10fa7c9728ddafa8ed7">CAN_FM1R_FBM24_Msk</a></td></tr>
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<tr class="separator:ga2befceefa1b4600adb96b1150a738dcf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cf69597e272b2e3db7bb54b60609553" id="r_ga0cf69597e272b2e3db7bb54b60609553"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cf69597e272b2e3db7bb54b60609553">CAN_FM1R_FBM25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga0cf69597e272b2e3db7bb54b60609553"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4f8c432102ad6270ae8c8faa92599e7" id="r_gae4f8c432102ad6270ae8c8faa92599e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4f8c432102ad6270ae8c8faa92599e7">CAN_FM1R_FBM25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cf69597e272b2e3db7bb54b60609553">CAN_FM1R_FBM25_Pos</a>)</td></tr>
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<tr class="separator:gae4f8c432102ad6270ae8c8faa92599e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8302ff02a952e32bd6cb5d8ce17ef94" id="r_gaf8302ff02a952e32bd6cb5d8ce17ef94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8302ff02a952e32bd6cb5d8ce17ef94">CAN_FM1R_FBM25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae4f8c432102ad6270ae8c8faa92599e7">CAN_FM1R_FBM25_Msk</a></td></tr>
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<tr class="separator:gaf8302ff02a952e32bd6cb5d8ce17ef94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20c45ed77383fe5ccf21614fe569ab6e" id="r_ga20c45ed77383fe5ccf21614fe569ab6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20c45ed77383fe5ccf21614fe569ab6e">CAN_FM1R_FBM26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga20c45ed77383fe5ccf21614fe569ab6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83528f848c64886be406a292c49f6b55" id="r_ga83528f848c64886be406a292c49f6b55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83528f848c64886be406a292c49f6b55">CAN_FM1R_FBM26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20c45ed77383fe5ccf21614fe569ab6e">CAN_FM1R_FBM26_Pos</a>)</td></tr>
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<tr class="separator:ga83528f848c64886be406a292c49f6b55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ea4af83b76361928669dc1de5681bd5" id="r_ga1ea4af83b76361928669dc1de5681bd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ea4af83b76361928669dc1de5681bd5">CAN_FM1R_FBM26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga83528f848c64886be406a292c49f6b55">CAN_FM1R_FBM26_Msk</a></td></tr>
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<tr class="separator:ga1ea4af83b76361928669dc1de5681bd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9dbac6ff3f18e5f1104e326dc24302bf" id="r_ga9dbac6ff3f18e5f1104e326dc24302bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9dbac6ff3f18e5f1104e326dc24302bf">CAN_FM1R_FBM27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga9dbac6ff3f18e5f1104e326dc24302bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf50cb4ff71b1cf38397efdff320e80cb" id="r_gaf50cb4ff71b1cf38397efdff320e80cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf50cb4ff71b1cf38397efdff320e80cb">CAN_FM1R_FBM27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9dbac6ff3f18e5f1104e326dc24302bf">CAN_FM1R_FBM27_Pos</a>)</td></tr>
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<tr class="separator:gaf50cb4ff71b1cf38397efdff320e80cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40ca208f170b85611874b2f832623aa8" id="r_ga40ca208f170b85611874b2f832623aa8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40ca208f170b85611874b2f832623aa8">CAN_FM1R_FBM27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf50cb4ff71b1cf38397efdff320e80cb">CAN_FM1R_FBM27_Msk</a></td></tr>
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<tr class="separator:ga40ca208f170b85611874b2f832623aa8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada2ff6f825375b0d42b92e7446a4e39c" id="r_gada2ff6f825375b0d42b92e7446a4e39c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada2ff6f825375b0d42b92e7446a4e39c">CAN_FS1R_FSC_Pos</a>   (0U)</td></tr>
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<tr class="separator:gada2ff6f825375b0d42b92e7446a4e39c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f5fd354abb81f726d16ba3df34d75d2" id="r_ga2f5fd354abb81f726d16ba3df34d75d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f5fd354abb81f726d16ba3df34d75d2">CAN_FS1R_FSC_Msk</a>   (0xFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada2ff6f825375b0d42b92e7446a4e39c">CAN_FS1R_FSC_Pos</a>)</td></tr>
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<tr class="separator:ga2f5fd354abb81f726d16ba3df34d75d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab41471f35878bcdff72d9cd05acf4714" id="r_gab41471f35878bcdff72d9cd05acf4714"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab41471f35878bcdff72d9cd05acf4714">CAN_FS1R_FSC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f5fd354abb81f726d16ba3df34d75d2">CAN_FS1R_FSC_Msk</a></td></tr>
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<tr class="separator:gab41471f35878bcdff72d9cd05acf4714"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga975c66c5f2d56c2ba83d022200c37958" id="r_ga975c66c5f2d56c2ba83d022200c37958"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga975c66c5f2d56c2ba83d022200c37958">CAN_FS1R_FSC0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga975c66c5f2d56c2ba83d022200c37958"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga521e7ed67be2a02528c2dd393abf8980" id="r_ga521e7ed67be2a02528c2dd393abf8980"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga521e7ed67be2a02528c2dd393abf8980">CAN_FS1R_FSC0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga975c66c5f2d56c2ba83d022200c37958">CAN_FS1R_FSC0_Pos</a>)</td></tr>
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<tr class="separator:ga521e7ed67be2a02528c2dd393abf8980"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab5ea9e0ed17df35894fff7828c89cad" id="r_gaab5ea9e0ed17df35894fff7828c89cad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab5ea9e0ed17df35894fff7828c89cad">CAN_FS1R_FSC0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga521e7ed67be2a02528c2dd393abf8980">CAN_FS1R_FSC0_Msk</a></td></tr>
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<tr class="separator:gaab5ea9e0ed17df35894fff7828c89cad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga642ead0693a426283dce755b276cc60b" id="r_ga642ead0693a426283dce755b276cc60b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga642ead0693a426283dce755b276cc60b">CAN_FS1R_FSC1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga642ead0693a426283dce755b276cc60b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1084aab8cb7c0fa2ebb1d54c8b1e5aec" id="r_ga1084aab8cb7c0fa2ebb1d54c8b1e5aec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1084aab8cb7c0fa2ebb1d54c8b1e5aec">CAN_FS1R_FSC1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga642ead0693a426283dce755b276cc60b">CAN_FS1R_FSC1_Pos</a>)</td></tr>
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<tr class="separator:ga1084aab8cb7c0fa2ebb1d54c8b1e5aec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83304e93d2e75c1cd8bfe7c2ec30c1c8" id="r_ga83304e93d2e75c1cd8bfe7c2ec30c1c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83304e93d2e75c1cd8bfe7c2ec30c1c8">CAN_FS1R_FSC1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1084aab8cb7c0fa2ebb1d54c8b1e5aec">CAN_FS1R_FSC1_Msk</a></td></tr>
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<tr class="separator:ga83304e93d2e75c1cd8bfe7c2ec30c1c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7026c45f4a48271ab35dd5e090c4568c" id="r_ga7026c45f4a48271ab35dd5e090c4568c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7026c45f4a48271ab35dd5e090c4568c">CAN_FS1R_FSC2_Pos</a>   (2U)</td></tr>
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<tr class="memitem:gab5c2bf5abff8b81f574f616837e91391" id="r_gab5c2bf5abff8b81f574f616837e91391"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5c2bf5abff8b81f574f616837e91391">CAN_FS1R_FSC2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7026c45f4a48271ab35dd5e090c4568c">CAN_FS1R_FSC2_Pos</a>)</td></tr>
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<tr class="memitem:ga0ba1fa61fcf851188a6f16323dda1358" id="r_ga0ba1fa61fcf851188a6f16323dda1358"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ba1fa61fcf851188a6f16323dda1358">CAN_FS1R_FSC2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab5c2bf5abff8b81f574f616837e91391">CAN_FS1R_FSC2_Msk</a></td></tr>
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<tr class="memitem:ga4262b5fb400ad83240758a8e0033bb98" id="r_ga4262b5fb400ad83240758a8e0033bb98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4262b5fb400ad83240758a8e0033bb98">CAN_FS1R_FSC3_Pos</a>   (3U)</td></tr>
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<tr class="memitem:ga8783da3e87efcfa99529dc7f6d3e9b8e" id="r_ga8783da3e87efcfa99529dc7f6d3e9b8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8783da3e87efcfa99529dc7f6d3e9b8e">CAN_FS1R_FSC3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4262b5fb400ad83240758a8e0033bb98">CAN_FS1R_FSC3_Pos</a>)</td></tr>
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<tr class="separator:ga8783da3e87efcfa99529dc7f6d3e9b8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2175f52f4308c088458f9e54a1f1354" id="r_gaf2175f52f4308c088458f9e54a1f1354"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2175f52f4308c088458f9e54a1f1354">CAN_FS1R_FSC3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8783da3e87efcfa99529dc7f6d3e9b8e">CAN_FS1R_FSC3_Msk</a></td></tr>
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<tr class="separator:gaf2175f52f4308c088458f9e54a1f1354"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba967abdc8c83c0d6e4590c691c16c1c" id="r_gaba967abdc8c83c0d6e4590c691c16c1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba967abdc8c83c0d6e4590c691c16c1c">CAN_FS1R_FSC4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaba967abdc8c83c0d6e4590c691c16c1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31ca51fc93d252a1a57a65ebf4163c46" id="r_ga31ca51fc93d252a1a57a65ebf4163c46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31ca51fc93d252a1a57a65ebf4163c46">CAN_FS1R_FSC4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba967abdc8c83c0d6e4590c691c16c1c">CAN_FS1R_FSC4_Pos</a>)</td></tr>
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<tr class="separator:ga31ca51fc93d252a1a57a65ebf4163c46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga791ac090d6a8f2c79cd72f9072aef30f" id="r_ga791ac090d6a8f2c79cd72f9072aef30f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga791ac090d6a8f2c79cd72f9072aef30f">CAN_FS1R_FSC4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31ca51fc93d252a1a57a65ebf4163c46">CAN_FS1R_FSC4_Msk</a></td></tr>
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<tr class="separator:ga791ac090d6a8f2c79cd72f9072aef30f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13a409ade293eec6d218a684042312d3" id="r_ga13a409ade293eec6d218a684042312d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13a409ade293eec6d218a684042312d3">CAN_FS1R_FSC5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga13a409ade293eec6d218a684042312d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f3efc361a57e98dc7fd35b9ad6db3f3" id="r_ga9f3efc361a57e98dc7fd35b9ad6db3f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f3efc361a57e98dc7fd35b9ad6db3f3">CAN_FS1R_FSC5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga13a409ade293eec6d218a684042312d3">CAN_FS1R_FSC5_Pos</a>)</td></tr>
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<tr class="separator:ga9f3efc361a57e98dc7fd35b9ad6db3f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb4ef2030ec70a4635ca4ac38cca76cb" id="r_gadb4ef2030ec70a4635ca4ac38cca76cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb4ef2030ec70a4635ca4ac38cca76cb">CAN_FS1R_FSC5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f3efc361a57e98dc7fd35b9ad6db3f3">CAN_FS1R_FSC5_Msk</a></td></tr>
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<tr class="memitem:gae8cf40d32e952d3fddc0cdc49ef695b5" id="r_gae8cf40d32e952d3fddc0cdc49ef695b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8cf40d32e952d3fddc0cdc49ef695b5">CAN_FS1R_FSC6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gae8cf40d32e952d3fddc0cdc49ef695b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a42808ce8e7e8c94c7a1748bc42b256" id="r_ga2a42808ce8e7e8c94c7a1748bc42b256"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a42808ce8e7e8c94c7a1748bc42b256">CAN_FS1R_FSC6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae8cf40d32e952d3fddc0cdc49ef695b5">CAN_FS1R_FSC6_Pos</a>)</td></tr>
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<tr class="separator:ga2a42808ce8e7e8c94c7a1748bc42b256"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf015be41f803007b9d0b2f3371e3621b" id="r_gaf015be41f803007b9d0b2f3371e3621b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf015be41f803007b9d0b2f3371e3621b">CAN_FS1R_FSC6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a42808ce8e7e8c94c7a1748bc42b256">CAN_FS1R_FSC6_Msk</a></td></tr>
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<tr class="separator:gaf015be41f803007b9d0b2f3371e3621b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8936fed15d6db3d7d1079851f2cf3679" id="r_ga8936fed15d6db3d7d1079851f2cf3679"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8936fed15d6db3d7d1079851f2cf3679">CAN_FS1R_FSC7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga8936fed15d6db3d7d1079851f2cf3679"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68d4a45e6f9068e4c7ed2af48eeb9e16" id="r_ga68d4a45e6f9068e4c7ed2af48eeb9e16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68d4a45e6f9068e4c7ed2af48eeb9e16">CAN_FS1R_FSC7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8936fed15d6db3d7d1079851f2cf3679">CAN_FS1R_FSC7_Pos</a>)</td></tr>
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<tr class="separator:ga68d4a45e6f9068e4c7ed2af48eeb9e16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga206d175417e2c787b44b0734708a5c9a" id="r_ga206d175417e2c787b44b0734708a5c9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga206d175417e2c787b44b0734708a5c9a">CAN_FS1R_FSC7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga68d4a45e6f9068e4c7ed2af48eeb9e16">CAN_FS1R_FSC7_Msk</a></td></tr>
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<tr class="separator:ga206d175417e2c787b44b0734708a5c9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed8e8f6dee42172cd578e1abab937b8b" id="r_gaed8e8f6dee42172cd578e1abab937b8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed8e8f6dee42172cd578e1abab937b8b">CAN_FS1R_FSC8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaed8e8f6dee42172cd578e1abab937b8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab90fee6d415260e5eb61df78ff0bbc3d" id="r_gab90fee6d415260e5eb61df78ff0bbc3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab90fee6d415260e5eb61df78ff0bbc3d">CAN_FS1R_FSC8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed8e8f6dee42172cd578e1abab937b8b">CAN_FS1R_FSC8_Pos</a>)</td></tr>
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<tr class="separator:gab90fee6d415260e5eb61df78ff0bbc3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7209f008874dadf147cb5357ee46c226" id="r_ga7209f008874dadf147cb5357ee46c226"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7209f008874dadf147cb5357ee46c226">CAN_FS1R_FSC8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab90fee6d415260e5eb61df78ff0bbc3d">CAN_FS1R_FSC8_Msk</a></td></tr>
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<tr class="memitem:ga4d172244d6448c45cb6be5d36474a4e1" id="r_ga4d172244d6448c45cb6be5d36474a4e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d172244d6448c45cb6be5d36474a4e1">CAN_FS1R_FSC9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga4d172244d6448c45cb6be5d36474a4e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fb2cac86c92bee0c7d29a1ee401aaa0" id="r_ga5fb2cac86c92bee0c7d29a1ee401aaa0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fb2cac86c92bee0c7d29a1ee401aaa0">CAN_FS1R_FSC9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d172244d6448c45cb6be5d36474a4e1">CAN_FS1R_FSC9_Pos</a>)</td></tr>
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<tr class="separator:ga5fb2cac86c92bee0c7d29a1ee401aaa0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58b4d8fa56d898ad6bf66ba8a4e098eb" id="r_ga58b4d8fa56d898ad6bf66ba8a4e098eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58b4d8fa56d898ad6bf66ba8a4e098eb">CAN_FS1R_FSC9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fb2cac86c92bee0c7d29a1ee401aaa0">CAN_FS1R_FSC9_Msk</a></td></tr>
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<tr class="separator:ga58b4d8fa56d898ad6bf66ba8a4e098eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaba757c59e5d37c1acdbed8af1ab90b4" id="r_gaaba757c59e5d37c1acdbed8af1ab90b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaba757c59e5d37c1acdbed8af1ab90b4">CAN_FS1R_FSC10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaaba757c59e5d37c1acdbed8af1ab90b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4915e6d23184afe98e5669b2575bfad" id="r_gae4915e6d23184afe98e5669b2575bfad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4915e6d23184afe98e5669b2575bfad">CAN_FS1R_FSC10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaba757c59e5d37c1acdbed8af1ab90b4">CAN_FS1R_FSC10_Pos</a>)</td></tr>
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<tr class="separator:gae4915e6d23184afe98e5669b2575bfad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93162a66091ffd4829ed8265f53fe977" id="r_ga93162a66091ffd4829ed8265f53fe977"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93162a66091ffd4829ed8265f53fe977">CAN_FS1R_FSC10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae4915e6d23184afe98e5669b2575bfad">CAN_FS1R_FSC10_Msk</a></td></tr>
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<tr class="separator:ga93162a66091ffd4829ed8265f53fe977"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2dd37596f667cdfd2771f05b413633e" id="r_gac2dd37596f667cdfd2771f05b413633e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2dd37596f667cdfd2771f05b413633e">CAN_FS1R_FSC11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gac2dd37596f667cdfd2771f05b413633e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17d1cabb7f95d9e773867888654ea3b0" id="r_ga17d1cabb7f95d9e773867888654ea3b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17d1cabb7f95d9e773867888654ea3b0">CAN_FS1R_FSC11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2dd37596f667cdfd2771f05b413633e">CAN_FS1R_FSC11_Pos</a>)</td></tr>
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<tr class="separator:ga17d1cabb7f95d9e773867888654ea3b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2e0bf399ea9175123c95c7010ef527d" id="r_gaf2e0bf399ea9175123c95c7010ef527d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2e0bf399ea9175123c95c7010ef527d">CAN_FS1R_FSC11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga17d1cabb7f95d9e773867888654ea3b0">CAN_FS1R_FSC11_Msk</a></td></tr>
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<tr class="separator:gaf2e0bf399ea9175123c95c7010ef527d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84011d0e3b79daa5ce4c9a076e774bca" id="r_ga84011d0e3b79daa5ce4c9a076e774bca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84011d0e3b79daa5ce4c9a076e774bca">CAN_FS1R_FSC12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga84011d0e3b79daa5ce4c9a076e774bca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad12de017f6c66c2b893b34d99c36c031" id="r_gad12de017f6c66c2b893b34d99c36c031"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad12de017f6c66c2b893b34d99c36c031">CAN_FS1R_FSC12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84011d0e3b79daa5ce4c9a076e774bca">CAN_FS1R_FSC12_Pos</a>)</td></tr>
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<tr class="separator:gad12de017f6c66c2b893b34d99c36c031"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89ea9e9c914052e2aecab16d57f2569d" id="r_ga89ea9e9c914052e2aecab16d57f2569d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89ea9e9c914052e2aecab16d57f2569d">CAN_FS1R_FSC12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad12de017f6c66c2b893b34d99c36c031">CAN_FS1R_FSC12_Msk</a></td></tr>
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<tr class="memitem:ga1e5c2f04599975dff25a01253f0ed0db" id="r_ga1e5c2f04599975dff25a01253f0ed0db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5c2f04599975dff25a01253f0ed0db">CAN_FS1R_FSC13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga1e5c2f04599975dff25a01253f0ed0db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga325adfc64e83297e5feb842002f09142" id="r_ga325adfc64e83297e5feb842002f09142"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga325adfc64e83297e5feb842002f09142">CAN_FS1R_FSC13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5c2f04599975dff25a01253f0ed0db">CAN_FS1R_FSC13_Pos</a>)</td></tr>
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<tr class="separator:ga325adfc64e83297e5feb842002f09142"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2df1f2a554fc014529da34620739bc4" id="r_gaf2df1f2a554fc014529da34620739bc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2df1f2a554fc014529da34620739bc4">CAN_FS1R_FSC13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga325adfc64e83297e5feb842002f09142">CAN_FS1R_FSC13_Msk</a></td></tr>
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<tr class="separator:gaf2df1f2a554fc014529da34620739bc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga711edd554bca297c3257d40b351c20c3" id="r_ga711edd554bca297c3257d40b351c20c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga711edd554bca297c3257d40b351c20c3">CAN_FS1R_FSC14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga711edd554bca297c3257d40b351c20c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34624026fcafcbee1b6c88d7e7756aae" id="r_ga34624026fcafcbee1b6c88d7e7756aae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34624026fcafcbee1b6c88d7e7756aae">CAN_FS1R_FSC14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga711edd554bca297c3257d40b351c20c3">CAN_FS1R_FSC14_Pos</a>)</td></tr>
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<tr class="separator:ga34624026fcafcbee1b6c88d7e7756aae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga361a4228de4644d1d6a810f4d074eb5f" id="r_ga361a4228de4644d1d6a810f4d074eb5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga361a4228de4644d1d6a810f4d074eb5f">CAN_FS1R_FSC14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34624026fcafcbee1b6c88d7e7756aae">CAN_FS1R_FSC14_Msk</a></td></tr>
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<tr class="separator:ga361a4228de4644d1d6a810f4d074eb5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3333c522cd42beec23bccc79a2ae1ba" id="r_gaf3333c522cd42beec23bccc79a2ae1ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3333c522cd42beec23bccc79a2ae1ba">CAN_FS1R_FSC15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaf3333c522cd42beec23bccc79a2ae1ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49834a4dc96f2cb8f792bd39d032abb4" id="r_ga49834a4dc96f2cb8f792bd39d032abb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49834a4dc96f2cb8f792bd39d032abb4">CAN_FS1R_FSC15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3333c522cd42beec23bccc79a2ae1ba">CAN_FS1R_FSC15_Pos</a>)</td></tr>
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<tr class="separator:ga49834a4dc96f2cb8f792bd39d032abb4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5ff2e59c16311405dc891f956c7ec96" id="r_gaa5ff2e59c16311405dc891f956c7ec96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5ff2e59c16311405dc891f956c7ec96">CAN_FS1R_FSC15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga49834a4dc96f2cb8f792bd39d032abb4">CAN_FS1R_FSC15_Msk</a></td></tr>
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<tr class="separator:gaa5ff2e59c16311405dc891f956c7ec96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94d84c5617fa0b58145211fc852fa55a" id="r_ga94d84c5617fa0b58145211fc852fa55a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94d84c5617fa0b58145211fc852fa55a">CAN_FS1R_FSC16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga94d84c5617fa0b58145211fc852fa55a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1eb533d142b86083e8b163adc30999a7" id="r_ga1eb533d142b86083e8b163adc30999a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1eb533d142b86083e8b163adc30999a7">CAN_FS1R_FSC16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga94d84c5617fa0b58145211fc852fa55a">CAN_FS1R_FSC16_Pos</a>)</td></tr>
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<tr class="separator:ga1eb533d142b86083e8b163adc30999a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0996ddbc1dcd487c052a0ae81ab852e" id="r_gad0996ddbc1dcd487c052a0ae81ab852e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0996ddbc1dcd487c052a0ae81ab852e">CAN_FS1R_FSC16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1eb533d142b86083e8b163adc30999a7">CAN_FS1R_FSC16_Msk</a></td></tr>
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<tr class="separator:gad0996ddbc1dcd487c052a0ae81ab852e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08ac31ff1870b11302f9e3b27d69789c" id="r_ga08ac31ff1870b11302f9e3b27d69789c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08ac31ff1870b11302f9e3b27d69789c">CAN_FS1R_FSC17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga08ac31ff1870b11302f9e3b27d69789c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d4c2ff7be6ee9b3e31108c9877aef03" id="r_ga7d4c2ff7be6ee9b3e31108c9877aef03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d4c2ff7be6ee9b3e31108c9877aef03">CAN_FS1R_FSC17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga08ac31ff1870b11302f9e3b27d69789c">CAN_FS1R_FSC17_Pos</a>)</td></tr>
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<tr class="separator:ga7d4c2ff7be6ee9b3e31108c9877aef03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65482dccb8701bf35d1397aadc1e7dde" id="r_ga65482dccb8701bf35d1397aadc1e7dde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65482dccb8701bf35d1397aadc1e7dde">CAN_FS1R_FSC17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d4c2ff7be6ee9b3e31108c9877aef03">CAN_FS1R_FSC17_Msk</a></td></tr>
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<tr class="separator:ga65482dccb8701bf35d1397aadc1e7dde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e256893bf2da548fa31dacc67b8833b" id="r_ga0e256893bf2da548fa31dacc67b8833b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e256893bf2da548fa31dacc67b8833b">CAN_FS1R_FSC18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga0e256893bf2da548fa31dacc67b8833b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8d890a441fc7b0a75e36caf1cbd7f2d" id="r_gad8d890a441fc7b0a75e36caf1cbd7f2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8d890a441fc7b0a75e36caf1cbd7f2d">CAN_FS1R_FSC18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e256893bf2da548fa31dacc67b8833b">CAN_FS1R_FSC18_Pos</a>)</td></tr>
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<tr class="separator:gad8d890a441fc7b0a75e36caf1cbd7f2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2657192999f8d7f7fdd5c5ef14d884f" id="r_gaf2657192999f8d7f7fdd5c5ef14d884f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2657192999f8d7f7fdd5c5ef14d884f">CAN_FS1R_FSC18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad8d890a441fc7b0a75e36caf1cbd7f2d">CAN_FS1R_FSC18_Msk</a></td></tr>
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<tr class="separator:gaf2657192999f8d7f7fdd5c5ef14d884f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga691b7c4f52419323104f755201811d0b" id="r_ga691b7c4f52419323104f755201811d0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga691b7c4f52419323104f755201811d0b">CAN_FS1R_FSC19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga691b7c4f52419323104f755201811d0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga562629687ae7a0c506aa310709b5451e" id="r_ga562629687ae7a0c506aa310709b5451e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga562629687ae7a0c506aa310709b5451e">CAN_FS1R_FSC19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga691b7c4f52419323104f755201811d0b">CAN_FS1R_FSC19_Pos</a>)</td></tr>
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<tr class="separator:ga562629687ae7a0c506aa310709b5451e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd584a3a9b6d6ae964c0484decb86a93" id="r_gafd584a3a9b6d6ae964c0484decb86a93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd584a3a9b6d6ae964c0484decb86a93">CAN_FS1R_FSC19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga562629687ae7a0c506aa310709b5451e">CAN_FS1R_FSC19_Msk</a></td></tr>
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<tr class="separator:gafd584a3a9b6d6ae964c0484decb86a93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0c2995214cad61a44cfbe386fafe5ff" id="r_gab0c2995214cad61a44cfbe386fafe5ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0c2995214cad61a44cfbe386fafe5ff">CAN_FS1R_FSC20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gab0c2995214cad61a44cfbe386fafe5ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0fce6ba0c9c134b3f634c8495b1e9a2" id="r_gad0fce6ba0c9c134b3f634c8495b1e9a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0fce6ba0c9c134b3f634c8495b1e9a2">CAN_FS1R_FSC20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab0c2995214cad61a44cfbe386fafe5ff">CAN_FS1R_FSC20_Pos</a>)</td></tr>
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<tr class="separator:gad0fce6ba0c9c134b3f634c8495b1e9a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5a5e1f0f1a66d607984d02b96b7fa2a" id="r_gae5a5e1f0f1a66d607984d02b96b7fa2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5a5e1f0f1a66d607984d02b96b7fa2a">CAN_FS1R_FSC20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad0fce6ba0c9c134b3f634c8495b1e9a2">CAN_FS1R_FSC20_Msk</a></td></tr>
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<tr class="separator:gae5a5e1f0f1a66d607984d02b96b7fa2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ea9c1362c0aa5d3d03f5df6b92ba9d4" id="r_ga6ea9c1362c0aa5d3d03f5df6b92ba9d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ea9c1362c0aa5d3d03f5df6b92ba9d4">CAN_FS1R_FSC21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga6ea9c1362c0aa5d3d03f5df6b92ba9d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga733db908c55117942e05d21f1ed80d7e" id="r_ga733db908c55117942e05d21f1ed80d7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga733db908c55117942e05d21f1ed80d7e">CAN_FS1R_FSC21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ea9c1362c0aa5d3d03f5df6b92ba9d4">CAN_FS1R_FSC21_Pos</a>)</td></tr>
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<tr class="separator:ga733db908c55117942e05d21f1ed80d7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa1d6dbc3fc5025a9e7416cc4b40cb7d" id="r_gafa1d6dbc3fc5025a9e7416cc4b40cb7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa1d6dbc3fc5025a9e7416cc4b40cb7d">CAN_FS1R_FSC21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga733db908c55117942e05d21f1ed80d7e">CAN_FS1R_FSC21_Msk</a></td></tr>
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<tr class="separator:gafa1d6dbc3fc5025a9e7416cc4b40cb7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2f345b172c571948a3357dd94b72adf" id="r_gaf2f345b172c571948a3357dd94b72adf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2f345b172c571948a3357dd94b72adf">CAN_FS1R_FSC22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gaf2f345b172c571948a3357dd94b72adf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabe5f4c3cd58ca9f4749942e3e6e04ee" id="r_gaabe5f4c3cd58ca9f4749942e3e6e04ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabe5f4c3cd58ca9f4749942e3e6e04ee">CAN_FS1R_FSC22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2f345b172c571948a3357dd94b72adf">CAN_FS1R_FSC22_Pos</a>)</td></tr>
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<tr class="separator:gaabe5f4c3cd58ca9f4749942e3e6e04ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga586c662a1dd2458cd1644e597c8da86d" id="r_ga586c662a1dd2458cd1644e597c8da86d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga586c662a1dd2458cd1644e597c8da86d">CAN_FS1R_FSC22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaabe5f4c3cd58ca9f4749942e3e6e04ee">CAN_FS1R_FSC22_Msk</a></td></tr>
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<tr class="separator:ga586c662a1dd2458cd1644e597c8da86d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga152bf04e1b1d963bfed4425d41dd27c8" id="r_ga152bf04e1b1d963bfed4425d41dd27c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga152bf04e1b1d963bfed4425d41dd27c8">CAN_FS1R_FSC23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga152bf04e1b1d963bfed4425d41dd27c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f8a8529c7e6e9b2d9bcd4512888365a" id="r_ga7f8a8529c7e6e9b2d9bcd4512888365a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f8a8529c7e6e9b2d9bcd4512888365a">CAN_FS1R_FSC23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga152bf04e1b1d963bfed4425d41dd27c8">CAN_FS1R_FSC23_Pos</a>)</td></tr>
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<tr class="separator:ga7f8a8529c7e6e9b2d9bcd4512888365a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga941b39874446041b446c3102646a49b8" id="r_ga941b39874446041b446c3102646a49b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga941b39874446041b446c3102646a49b8">CAN_FS1R_FSC23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f8a8529c7e6e9b2d9bcd4512888365a">CAN_FS1R_FSC23_Msk</a></td></tr>
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<tr class="separator:ga941b39874446041b446c3102646a49b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51ea9d18bbbe2db9eed4a8e58e59e957" id="r_ga51ea9d18bbbe2db9eed4a8e58e59e957"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51ea9d18bbbe2db9eed4a8e58e59e957">CAN_FS1R_FSC24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga51ea9d18bbbe2db9eed4a8e58e59e957"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68e6bfdc20abbec37b36857af02f466d" id="r_ga68e6bfdc20abbec37b36857af02f466d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68e6bfdc20abbec37b36857af02f466d">CAN_FS1R_FSC24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga51ea9d18bbbe2db9eed4a8e58e59e957">CAN_FS1R_FSC24_Pos</a>)</td></tr>
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<tr class="separator:ga68e6bfdc20abbec37b36857af02f466d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga702728de40ecf0afc5bc8f05ee243ece" id="r_ga702728de40ecf0afc5bc8f05ee243ece"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga702728de40ecf0afc5bc8f05ee243ece">CAN_FS1R_FSC24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga68e6bfdc20abbec37b36857af02f466d">CAN_FS1R_FSC24_Msk</a></td></tr>
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<tr class="separator:ga702728de40ecf0afc5bc8f05ee243ece"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f0bdcc4ed01c8beabedfc4b16a146f6" id="r_ga5f0bdcc4ed01c8beabedfc4b16a146f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f0bdcc4ed01c8beabedfc4b16a146f6">CAN_FS1R_FSC25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga5f0bdcc4ed01c8beabedfc4b16a146f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2211e33f4ca75397983086826a688656" id="r_ga2211e33f4ca75397983086826a688656"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2211e33f4ca75397983086826a688656">CAN_FS1R_FSC25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f0bdcc4ed01c8beabedfc4b16a146f6">CAN_FS1R_FSC25_Pos</a>)</td></tr>
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<tr class="separator:ga2211e33f4ca75397983086826a688656"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bd08e49dcb537e967ef7e8a7b30e9d0" id="r_ga1bd08e49dcb537e967ef7e8a7b30e9d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bd08e49dcb537e967ef7e8a7b30e9d0">CAN_FS1R_FSC25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2211e33f4ca75397983086826a688656">CAN_FS1R_FSC25_Msk</a></td></tr>
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<tr class="separator:ga1bd08e49dcb537e967ef7e8a7b30e9d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab61794b3ead79416791289685a95db4d" id="r_gab61794b3ead79416791289685a95db4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab61794b3ead79416791289685a95db4d">CAN_FS1R_FSC26_Pos</a>   (26U)</td></tr>
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<tr class="separator:gab61794b3ead79416791289685a95db4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d55d2d1459b5de35264036663bc430b" id="r_ga4d55d2d1459b5de35264036663bc430b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d55d2d1459b5de35264036663bc430b">CAN_FS1R_FSC26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab61794b3ead79416791289685a95db4d">CAN_FS1R_FSC26_Pos</a>)</td></tr>
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<tr class="separator:ga4d55d2d1459b5de35264036663bc430b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac642623c62041b1be7ce3af929c4f924" id="r_gac642623c62041b1be7ce3af929c4f924"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac642623c62041b1be7ce3af929c4f924">CAN_FS1R_FSC26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d55d2d1459b5de35264036663bc430b">CAN_FS1R_FSC26_Msk</a></td></tr>
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<tr class="separator:gac642623c62041b1be7ce3af929c4f924"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d7b516bf7cf68e60c3feb66b1c3588e" id="r_ga3d7b516bf7cf68e60c3feb66b1c3588e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d7b516bf7cf68e60c3feb66b1c3588e">CAN_FS1R_FSC27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga3d7b516bf7cf68e60c3feb66b1c3588e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c2c04e71ea402536a26c54e6f23116d" id="r_ga3c2c04e71ea402536a26c54e6f23116d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c2c04e71ea402536a26c54e6f23116d">CAN_FS1R_FSC27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d7b516bf7cf68e60c3feb66b1c3588e">CAN_FS1R_FSC27_Pos</a>)</td></tr>
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<tr class="separator:ga3c2c04e71ea402536a26c54e6f23116d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e86579ebc64eda3a65fd8d40e15af57" id="r_ga9e86579ebc64eda3a65fd8d40e15af57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e86579ebc64eda3a65fd8d40e15af57">CAN_FS1R_FSC27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c2c04e71ea402536a26c54e6f23116d">CAN_FS1R_FSC27_Msk</a></td></tr>
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<tr class="separator:ga9e86579ebc64eda3a65fd8d40e15af57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8a13781d7e62a0c62344a9e3d32c31b" id="r_gac8a13781d7e62a0c62344a9e3d32c31b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8a13781d7e62a0c62344a9e3d32c31b">CAN_FFA1R_FFA_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac8a13781d7e62a0c62344a9e3d32c31b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d6813f166c5bc78b7ceabcaf544202e" id="r_ga9d6813f166c5bc78b7ceabcaf544202e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d6813f166c5bc78b7ceabcaf544202e">CAN_FFA1R_FFA_Msk</a>   (0xFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8a13781d7e62a0c62344a9e3d32c31b">CAN_FFA1R_FFA_Pos</a>)</td></tr>
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<tr class="separator:ga9d6813f166c5bc78b7ceabcaf544202e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16fa4bf13579d29b57f7602489d043fe" id="r_ga16fa4bf13579d29b57f7602489d043fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16fa4bf13579d29b57f7602489d043fe">CAN_FFA1R_FFA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d6813f166c5bc78b7ceabcaf544202e">CAN_FFA1R_FFA_Msk</a></td></tr>
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<tr class="separator:ga16fa4bf13579d29b57f7602489d043fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e673e4b99624b2b674c1a0cb814af7d" id="r_ga8e673e4b99624b2b674c1a0cb814af7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e673e4b99624b2b674c1a0cb814af7d">CAN_FFA1R_FFA0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8e673e4b99624b2b674c1a0cb814af7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63a732f91a0c26a9e29151486e2af798" id="r_ga63a732f91a0c26a9e29151486e2af798"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63a732f91a0c26a9e29151486e2af798">CAN_FFA1R_FFA0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e673e4b99624b2b674c1a0cb814af7d">CAN_FFA1R_FFA0_Pos</a>)</td></tr>
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<tr class="separator:ga63a732f91a0c26a9e29151486e2af798"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b1a0f95bac4fed1a801da0cdbf2a833" id="r_ga4b1a0f95bac4fed1a801da0cdbf2a833"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b1a0f95bac4fed1a801da0cdbf2a833">CAN_FFA1R_FFA0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63a732f91a0c26a9e29151486e2af798">CAN_FFA1R_FFA0_Msk</a></td></tr>
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<tr class="separator:ga4b1a0f95bac4fed1a801da0cdbf2a833"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafce5ceec640174f6e6c06aafc980bb82" id="r_gafce5ceec640174f6e6c06aafc980bb82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafce5ceec640174f6e6c06aafc980bb82">CAN_FFA1R_FFA1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gafce5ceec640174f6e6c06aafc980bb82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga692f0c606853b771a99e052cd0fe0995" id="r_ga692f0c606853b771a99e052cd0fe0995"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga692f0c606853b771a99e052cd0fe0995">CAN_FFA1R_FFA1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafce5ceec640174f6e6c06aafc980bb82">CAN_FFA1R_FFA1_Pos</a>)</td></tr>
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<tr class="separator:ga692f0c606853b771a99e052cd0fe0995"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba35e135e17431de861e57b550421386" id="r_gaba35e135e17431de861e57b550421386"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba35e135e17431de861e57b550421386">CAN_FFA1R_FFA1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga692f0c606853b771a99e052cd0fe0995">CAN_FFA1R_FFA1_Msk</a></td></tr>
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<tr class="separator:gaba35e135e17431de861e57b550421386"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7a54c1f4d9f576917d36df988c7cce0" id="r_gaa7a54c1f4d9f576917d36df988c7cce0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7a54c1f4d9f576917d36df988c7cce0">CAN_FFA1R_FFA2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaa7a54c1f4d9f576917d36df988c7cce0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga197d8ba6187ed4b6842505ae99104992" id="r_ga197d8ba6187ed4b6842505ae99104992"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga197d8ba6187ed4b6842505ae99104992">CAN_FFA1R_FFA2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7a54c1f4d9f576917d36df988c7cce0">CAN_FFA1R_FFA2_Pos</a>)</td></tr>
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<tr class="separator:ga197d8ba6187ed4b6842505ae99104992"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b64393197f5cd0bd6e4853828a98065" id="r_ga5b64393197f5cd0bd6e4853828a98065"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b64393197f5cd0bd6e4853828a98065">CAN_FFA1R_FFA2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga197d8ba6187ed4b6842505ae99104992">CAN_FFA1R_FFA2_Msk</a></td></tr>
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<tr class="separator:ga5b64393197f5cd0bd6e4853828a98065"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57037066dc96ae3ac826b462ab6916ac" id="r_ga57037066dc96ae3ac826b462ab6916ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57037066dc96ae3ac826b462ab6916ac">CAN_FFA1R_FFA3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga57037066dc96ae3ac826b462ab6916ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6c1a5ee723cd899b098e277386d86a4" id="r_gae6c1a5ee723cd899b098e277386d86a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6c1a5ee723cd899b098e277386d86a4">CAN_FFA1R_FFA3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57037066dc96ae3ac826b462ab6916ac">CAN_FFA1R_FFA3_Pos</a>)</td></tr>
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<tr class="separator:gae6c1a5ee723cd899b098e277386d86a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga111ce1e4500e2c0f543128dddbe941e9" id="r_ga111ce1e4500e2c0f543128dddbe941e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga111ce1e4500e2c0f543128dddbe941e9">CAN_FFA1R_FFA3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae6c1a5ee723cd899b098e277386d86a4">CAN_FFA1R_FFA3_Msk</a></td></tr>
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<tr class="separator:ga111ce1e4500e2c0f543128dddbe941e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69b604f0eea6a02bb71611b830ff32c2" id="r_ga69b604f0eea6a02bb71611b830ff32c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69b604f0eea6a02bb71611b830ff32c2">CAN_FFA1R_FFA4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga69b604f0eea6a02bb71611b830ff32c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d03c010394020f6172d2fceba9e02ea" id="r_ga9d03c010394020f6172d2fceba9e02ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d03c010394020f6172d2fceba9e02ea">CAN_FFA1R_FFA4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69b604f0eea6a02bb71611b830ff32c2">CAN_FFA1R_FFA4_Pos</a>)</td></tr>
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<tr class="separator:ga9d03c010394020f6172d2fceba9e02ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a824c777e7fea25f580bc313ed2ece6" id="r_ga8a824c777e7fea25f580bc313ed2ece6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a824c777e7fea25f580bc313ed2ece6">CAN_FFA1R_FFA4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d03c010394020f6172d2fceba9e02ea">CAN_FFA1R_FFA4_Msk</a></td></tr>
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<tr class="separator:ga8a824c777e7fea25f580bc313ed2ece6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacacfe37b33ceac03e2abad22e7bbce28" id="r_gacacfe37b33ceac03e2abad22e7bbce28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacacfe37b33ceac03e2abad22e7bbce28">CAN_FFA1R_FFA5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gacacfe37b33ceac03e2abad22e7bbce28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51918688a8985d110c995bf441a4f763" id="r_ga51918688a8985d110c995bf441a4f763"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51918688a8985d110c995bf441a4f763">CAN_FFA1R_FFA5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacacfe37b33ceac03e2abad22e7bbce28">CAN_FFA1R_FFA5_Pos</a>)</td></tr>
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<tr class="separator:ga51918688a8985d110c995bf441a4f763"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd571c9c746225e9b856ce3a46c3bb2f" id="r_gabd571c9c746225e9b856ce3a46c3bb2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd571c9c746225e9b856ce3a46c3bb2f">CAN_FFA1R_FFA5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga51918688a8985d110c995bf441a4f763">CAN_FFA1R_FFA5_Msk</a></td></tr>
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<tr class="separator:gabd571c9c746225e9b856ce3a46c3bb2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga165fe8139c6eb2b3971def9579d1d497" id="r_ga165fe8139c6eb2b3971def9579d1d497"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga165fe8139c6eb2b3971def9579d1d497">CAN_FFA1R_FFA6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga165fe8139c6eb2b3971def9579d1d497"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01b319af3e2f1b59d544501192e24b68" id="r_ga01b319af3e2f1b59d544501192e24b68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01b319af3e2f1b59d544501192e24b68">CAN_FFA1R_FFA6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga165fe8139c6eb2b3971def9579d1d497">CAN_FFA1R_FFA6_Pos</a>)</td></tr>
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<tr class="separator:ga01b319af3e2f1b59d544501192e24b68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2afec157fe9684f1fa4b4401500f035" id="r_gab2afec157fe9684f1fa4b4401500f035"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2afec157fe9684f1fa4b4401500f035">CAN_FFA1R_FFA6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga01b319af3e2f1b59d544501192e24b68">CAN_FFA1R_FFA6_Msk</a></td></tr>
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<tr class="separator:gab2afec157fe9684f1fa4b4401500f035"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1f1bf154b1ffb5f5e1f7bb5d8b0a300" id="r_gab1f1bf154b1ffb5f5e1f7bb5d8b0a300"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1f1bf154b1ffb5f5e1f7bb5d8b0a300">CAN_FFA1R_FFA7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gab1f1bf154b1ffb5f5e1f7bb5d8b0a300"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62ff14edc65346f9e08e9f259a7fd45a" id="r_ga62ff14edc65346f9e08e9f259a7fd45a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62ff14edc65346f9e08e9f259a7fd45a">CAN_FFA1R_FFA7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab1f1bf154b1ffb5f5e1f7bb5d8b0a300">CAN_FFA1R_FFA7_Pos</a>)</td></tr>
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<tr class="separator:ga62ff14edc65346f9e08e9f259a7fd45a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d70e150cfd4866ea6b0a264ad45f51b" id="r_ga2d70e150cfd4866ea6b0a264ad45f51b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d70e150cfd4866ea6b0a264ad45f51b">CAN_FFA1R_FFA7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga62ff14edc65346f9e08e9f259a7fd45a">CAN_FFA1R_FFA7_Msk</a></td></tr>
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<tr class="separator:ga2d70e150cfd4866ea6b0a264ad45f51b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9092a75173fa128b0d1fb7616df2cd07" id="r_ga9092a75173fa128b0d1fb7616df2cd07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9092a75173fa128b0d1fb7616df2cd07">CAN_FFA1R_FFA8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga9092a75173fa128b0d1fb7616df2cd07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga141132dbc9c5d5a0a125c8aae363445b" id="r_ga141132dbc9c5d5a0a125c8aae363445b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga141132dbc9c5d5a0a125c8aae363445b">CAN_FFA1R_FFA8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9092a75173fa128b0d1fb7616df2cd07">CAN_FFA1R_FFA8_Pos</a>)</td></tr>
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<tr class="separator:ga141132dbc9c5d5a0a125c8aae363445b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa802583aa70aadeb46366ff98eccaf1" id="r_gafa802583aa70aadeb46366ff98eccaf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa802583aa70aadeb46366ff98eccaf1">CAN_FFA1R_FFA8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga141132dbc9c5d5a0a125c8aae363445b">CAN_FFA1R_FFA8_Msk</a></td></tr>
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<tr class="separator:gafa802583aa70aadeb46366ff98eccaf1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa26f182a322fb252ccb2c4e573677ad7" id="r_gaa26f182a322fb252ccb2c4e573677ad7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa26f182a322fb252ccb2c4e573677ad7">CAN_FFA1R_FFA9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaa26f182a322fb252ccb2c4e573677ad7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3270aaea7647ea2c5ccbaf747ceffb5b" id="r_ga3270aaea7647ea2c5ccbaf747ceffb5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3270aaea7647ea2c5ccbaf747ceffb5b">CAN_FFA1R_FFA9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa26f182a322fb252ccb2c4e573677ad7">CAN_FFA1R_FFA9_Pos</a>)</td></tr>
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<tr class="separator:ga3270aaea7647ea2c5ccbaf747ceffb5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ee7da4c7e42fa7576d965c4bf94c089" id="r_ga6ee7da4c7e42fa7576d965c4bf94c089"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ee7da4c7e42fa7576d965c4bf94c089">CAN_FFA1R_FFA9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3270aaea7647ea2c5ccbaf747ceffb5b">CAN_FFA1R_FFA9_Msk</a></td></tr>
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<tr class="separator:ga6ee7da4c7e42fa7576d965c4bf94c089"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf1221d604b06bcee9432d1438ddd2f1" id="r_gabf1221d604b06bcee9432d1438ddd2f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf1221d604b06bcee9432d1438ddd2f1">CAN_FFA1R_FFA10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gabf1221d604b06bcee9432d1438ddd2f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ac746965c32524f17be780be809bf29" id="r_ga7ac746965c32524f17be780be809bf29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac746965c32524f17be780be809bf29">CAN_FFA1R_FFA10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf1221d604b06bcee9432d1438ddd2f1">CAN_FFA1R_FFA10_Pos</a>)</td></tr>
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<tr class="separator:ga7ac746965c32524f17be780be809bf29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ac0384eab9b0cfdb491a960279fc438" id="r_ga8ac0384eab9b0cfdb491a960279fc438"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ac0384eab9b0cfdb491a960279fc438">CAN_FFA1R_FFA10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac746965c32524f17be780be809bf29">CAN_FFA1R_FFA10_Msk</a></td></tr>
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<tr class="separator:ga8ac0384eab9b0cfdb491a960279fc438"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4435daea27c23de8ac235d2dc6ce988d" id="r_ga4435daea27c23de8ac235d2dc6ce988d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4435daea27c23de8ac235d2dc6ce988d">CAN_FFA1R_FFA11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga4435daea27c23de8ac235d2dc6ce988d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5fec989f32c99595a73b0910dc92787" id="r_gab5fec989f32c99595a73b0910dc92787"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5fec989f32c99595a73b0910dc92787">CAN_FFA1R_FFA11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4435daea27c23de8ac235d2dc6ce988d">CAN_FFA1R_FFA11_Pos</a>)</td></tr>
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<tr class="separator:gab5fec989f32c99595a73b0910dc92787"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacd7e79ab503ec5143b5848edac71817" id="r_gaacd7e79ab503ec5143b5848edac71817"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacd7e79ab503ec5143b5848edac71817">CAN_FFA1R_FFA11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab5fec989f32c99595a73b0910dc92787">CAN_FFA1R_FFA11_Msk</a></td></tr>
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<tr class="separator:gaacd7e79ab503ec5143b5848edac71817"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga088625981d2bbc9e281ad21fb592022d" id="r_ga088625981d2bbc9e281ad21fb592022d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga088625981d2bbc9e281ad21fb592022d">CAN_FFA1R_FFA12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga088625981d2bbc9e281ad21fb592022d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e3859f0d8f9b1a52beaa72de195222b" id="r_ga0e3859f0d8f9b1a52beaa72de195222b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e3859f0d8f9b1a52beaa72de195222b">CAN_FFA1R_FFA12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga088625981d2bbc9e281ad21fb592022d">CAN_FFA1R_FFA12_Pos</a>)</td></tr>
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<tr class="separator:ga0e3859f0d8f9b1a52beaa72de195222b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7873f1526050f5e666c22fb6a7e68b65" id="r_ga7873f1526050f5e666c22fb6a7e68b65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7873f1526050f5e666c22fb6a7e68b65">CAN_FFA1R_FFA12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e3859f0d8f9b1a52beaa72de195222b">CAN_FFA1R_FFA12_Msk</a></td></tr>
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<tr class="separator:ga7873f1526050f5e666c22fb6a7e68b65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89646cfa2e98d87000f27e4bd22e0d48" id="r_ga89646cfa2e98d87000f27e4bd22e0d48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89646cfa2e98d87000f27e4bd22e0d48">CAN_FFA1R_FFA13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga89646cfa2e98d87000f27e4bd22e0d48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ff3bf3a563646cf44a6dacfa1652cb0" id="r_ga2ff3bf3a563646cf44a6dacfa1652cb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ff3bf3a563646cf44a6dacfa1652cb0">CAN_FFA1R_FFA13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga89646cfa2e98d87000f27e4bd22e0d48">CAN_FFA1R_FFA13_Pos</a>)</td></tr>
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<tr class="separator:ga2ff3bf3a563646cf44a6dacfa1652cb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac74339b69a2e6f67df9b6e136089c0ee" id="r_gac74339b69a2e6f67df9b6e136089c0ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac74339b69a2e6f67df9b6e136089c0ee">CAN_FFA1R_FFA13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ff3bf3a563646cf44a6dacfa1652cb0">CAN_FFA1R_FFA13_Msk</a></td></tr>
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<tr class="separator:gac74339b69a2e6f67df9b6e136089c0ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf8560a004719b166cfaf281a67f79e1" id="r_gaaf8560a004719b166cfaf281a67f79e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf8560a004719b166cfaf281a67f79e1">CAN_FFA1R_FFA14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gaaf8560a004719b166cfaf281a67f79e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10da524219356b7c7aa0fff90ef718f1" id="r_ga10da524219356b7c7aa0fff90ef718f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10da524219356b7c7aa0fff90ef718f1">CAN_FFA1R_FFA14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf8560a004719b166cfaf281a67f79e1">CAN_FFA1R_FFA14_Pos</a>)</td></tr>
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<tr class="separator:ga10da524219356b7c7aa0fff90ef718f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bdc473bfe275c940734d2c1775d982d" id="r_ga6bdc473bfe275c940734d2c1775d982d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bdc473bfe275c940734d2c1775d982d">CAN_FFA1R_FFA14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga10da524219356b7c7aa0fff90ef718f1">CAN_FFA1R_FFA14_Msk</a></td></tr>
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<tr class="separator:ga6bdc473bfe275c940734d2c1775d982d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae41306fbd5429b13073a556e9c851470" id="r_gae41306fbd5429b13073a556e9c851470"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae41306fbd5429b13073a556e9c851470">CAN_FFA1R_FFA15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gae41306fbd5429b13073a556e9c851470"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef1dfb17246f207f68f459a0f7f440df" id="r_gaef1dfb17246f207f68f459a0f7f440df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef1dfb17246f207f68f459a0f7f440df">CAN_FFA1R_FFA15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae41306fbd5429b13073a556e9c851470">CAN_FFA1R_FFA15_Pos</a>)</td></tr>
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<tr class="separator:gaef1dfb17246f207f68f459a0f7f440df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c72b1a17bc4a9c7ec3251af645e290d" id="r_ga8c72b1a17bc4a9c7ec3251af645e290d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c72b1a17bc4a9c7ec3251af645e290d">CAN_FFA1R_FFA15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaef1dfb17246f207f68f459a0f7f440df">CAN_FFA1R_FFA15_Msk</a></td></tr>
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<tr class="separator:ga8c72b1a17bc4a9c7ec3251af645e290d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga799996bdb9bc84e5bcd03e7d75f3ec4e" id="r_ga799996bdb9bc84e5bcd03e7d75f3ec4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga799996bdb9bc84e5bcd03e7d75f3ec4e">CAN_FFA1R_FFA16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga799996bdb9bc84e5bcd03e7d75f3ec4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f03a68e7428cc6c56b0f755246ecff4" id="r_ga0f03a68e7428cc6c56b0f755246ecff4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f03a68e7428cc6c56b0f755246ecff4">CAN_FFA1R_FFA16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga799996bdb9bc84e5bcd03e7d75f3ec4e">CAN_FFA1R_FFA16_Pos</a>)</td></tr>
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<tr class="separator:ga0f03a68e7428cc6c56b0f755246ecff4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadac411834c4a2118354f7b160c292dd6" id="r_gadac411834c4a2118354f7b160c292dd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadac411834c4a2118354f7b160c292dd6">CAN_FFA1R_FFA16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f03a68e7428cc6c56b0f755246ecff4">CAN_FFA1R_FFA16_Msk</a></td></tr>
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<tr class="separator:gadac411834c4a2118354f7b160c292dd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa772ef7c7e8e47f6c54d342f83a6f4ab" id="r_gaa772ef7c7e8e47f6c54d342f83a6f4ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa772ef7c7e8e47f6c54d342f83a6f4ab">CAN_FFA1R_FFA17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gaa772ef7c7e8e47f6c54d342f83a6f4ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9eccf63346520ce0fc6d72774b62957d" id="r_ga9eccf63346520ce0fc6d72774b62957d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9eccf63346520ce0fc6d72774b62957d">CAN_FFA1R_FFA17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa772ef7c7e8e47f6c54d342f83a6f4ab">CAN_FFA1R_FFA17_Pos</a>)</td></tr>
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<tr class="separator:ga9eccf63346520ce0fc6d72774b62957d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf73b3c3d378246929f1092416546aa45" id="r_gaf73b3c3d378246929f1092416546aa45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf73b3c3d378246929f1092416546aa45">CAN_FFA1R_FFA17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9eccf63346520ce0fc6d72774b62957d">CAN_FFA1R_FFA17_Msk</a></td></tr>
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<tr class="separator:gaf73b3c3d378246929f1092416546aa45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89199c68d5354b179d13f125beb8866b" id="r_ga89199c68d5354b179d13f125beb8866b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89199c68d5354b179d13f125beb8866b">CAN_FFA1R_FFA18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga89199c68d5354b179d13f125beb8866b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad328f6b0426811376fb96edd92ee17dd" id="r_gad328f6b0426811376fb96edd92ee17dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad328f6b0426811376fb96edd92ee17dd">CAN_FFA1R_FFA18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga89199c68d5354b179d13f125beb8866b">CAN_FFA1R_FFA18_Pos</a>)</td></tr>
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<tr class="separator:gad328f6b0426811376fb96edd92ee17dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc2bf72b9f9c57ddcaf09449a208a4ef" id="r_gadc2bf72b9f9c57ddcaf09449a208a4ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc2bf72b9f9c57ddcaf09449a208a4ef">CAN_FFA1R_FFA18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad328f6b0426811376fb96edd92ee17dd">CAN_FFA1R_FFA18_Msk</a></td></tr>
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<tr class="separator:gadc2bf72b9f9c57ddcaf09449a208a4ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d1c21deb9827442f5607348e34abc98" id="r_ga0d1c21deb9827442f5607348e34abc98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d1c21deb9827442f5607348e34abc98">CAN_FFA1R_FFA19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga0d1c21deb9827442f5607348e34abc98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffc95b44aaf8c77fb00666241311d78b" id="r_gaffc95b44aaf8c77fb00666241311d78b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffc95b44aaf8c77fb00666241311d78b">CAN_FFA1R_FFA19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d1c21deb9827442f5607348e34abc98">CAN_FFA1R_FFA19_Pos</a>)</td></tr>
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<tr class="separator:gaffc95b44aaf8c77fb00666241311d78b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a2371494a1ab03e90ff471b4e88d4eb" id="r_ga7a2371494a1ab03e90ff471b4e88d4eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a2371494a1ab03e90ff471b4e88d4eb">CAN_FFA1R_FFA19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaffc95b44aaf8c77fb00666241311d78b">CAN_FFA1R_FFA19_Msk</a></td></tr>
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<tr class="separator:ga7a2371494a1ab03e90ff471b4e88d4eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga077f389aa603e8dc048bc6af4cbec654" id="r_ga077f389aa603e8dc048bc6af4cbec654"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga077f389aa603e8dc048bc6af4cbec654">CAN_FFA1R_FFA20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga077f389aa603e8dc048bc6af4cbec654"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87cf0758a707ef8bae3f14ca07009487" id="r_ga87cf0758a707ef8bae3f14ca07009487"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87cf0758a707ef8bae3f14ca07009487">CAN_FFA1R_FFA20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga077f389aa603e8dc048bc6af4cbec654">CAN_FFA1R_FFA20_Pos</a>)</td></tr>
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<tr class="separator:ga87cf0758a707ef8bae3f14ca07009487"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7359bb245f5bc6f9298bdae577c7f2d1" id="r_ga7359bb245f5bc6f9298bdae577c7f2d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7359bb245f5bc6f9298bdae577c7f2d1">CAN_FFA1R_FFA20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga87cf0758a707ef8bae3f14ca07009487">CAN_FFA1R_FFA20_Msk</a></td></tr>
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<tr class="separator:ga7359bb245f5bc6f9298bdae577c7f2d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b4ab4a10e2a0cb2bb32bee0c1d1fe8d" id="r_ga6b4ab4a10e2a0cb2bb32bee0c1d1fe8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b4ab4a10e2a0cb2bb32bee0c1d1fe8d">CAN_FFA1R_FFA21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga6b4ab4a10e2a0cb2bb32bee0c1d1fe8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49398f11989a0fac67eea74c169add65" id="r_ga49398f11989a0fac67eea74c169add65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49398f11989a0fac67eea74c169add65">CAN_FFA1R_FFA21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b4ab4a10e2a0cb2bb32bee0c1d1fe8d">CAN_FFA1R_FFA21_Pos</a>)</td></tr>
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<tr class="separator:ga49398f11989a0fac67eea74c169add65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4390bdfd6fb22feb6b64de18b45304d8" id="r_ga4390bdfd6fb22feb6b64de18b45304d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4390bdfd6fb22feb6b64de18b45304d8">CAN_FFA1R_FFA21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga49398f11989a0fac67eea74c169add65">CAN_FFA1R_FFA21_Msk</a></td></tr>
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<tr class="separator:ga4390bdfd6fb22feb6b64de18b45304d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08da105ae70ea87f80128a8451fb14d8" id="r_ga08da105ae70ea87f80128a8451fb14d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08da105ae70ea87f80128a8451fb14d8">CAN_FFA1R_FFA22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga08da105ae70ea87f80128a8451fb14d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab501571f610235c7a89d5ed6148ee4bb" id="r_gab501571f610235c7a89d5ed6148ee4bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab501571f610235c7a89d5ed6148ee4bb">CAN_FFA1R_FFA22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga08da105ae70ea87f80128a8451fb14d8">CAN_FFA1R_FFA22_Pos</a>)</td></tr>
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<tr class="separator:gab501571f610235c7a89d5ed6148ee4bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga029cfaf7e13f5214dd3e056b0984b1d8" id="r_ga029cfaf7e13f5214dd3e056b0984b1d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga029cfaf7e13f5214dd3e056b0984b1d8">CAN_FFA1R_FFA22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab501571f610235c7a89d5ed6148ee4bb">CAN_FFA1R_FFA22_Msk</a></td></tr>
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<tr class="separator:ga029cfaf7e13f5214dd3e056b0984b1d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabcc71274e0234226241674e65a697913" id="r_gabcc71274e0234226241674e65a697913"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabcc71274e0234226241674e65a697913">CAN_FFA1R_FFA23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gabcc71274e0234226241674e65a697913"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1258ce7b88510c0942cca2ec7443c749" id="r_ga1258ce7b88510c0942cca2ec7443c749"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1258ce7b88510c0942cca2ec7443c749">CAN_FFA1R_FFA23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabcc71274e0234226241674e65a697913">CAN_FFA1R_FFA23_Pos</a>)</td></tr>
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<tr class="separator:ga1258ce7b88510c0942cca2ec7443c749"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad969df81e8f4d8902ddf9ac76c7ff9d2" id="r_gad969df81e8f4d8902ddf9ac76c7ff9d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad969df81e8f4d8902ddf9ac76c7ff9d2">CAN_FFA1R_FFA23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1258ce7b88510c0942cca2ec7443c749">CAN_FFA1R_FFA23_Msk</a></td></tr>
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<tr class="separator:gad969df81e8f4d8902ddf9ac76c7ff9d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabae42ffc06637b9ac6424b2019cef2a" id="r_gaabae42ffc06637b9ac6424b2019cef2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabae42ffc06637b9ac6424b2019cef2a">CAN_FFA1R_FFA24_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaabae42ffc06637b9ac6424b2019cef2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fe02633e558b53290fc5645ac903318" id="r_ga5fe02633e558b53290fc5645ac903318"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe02633e558b53290fc5645ac903318">CAN_FFA1R_FFA24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaabae42ffc06637b9ac6424b2019cef2a">CAN_FFA1R_FFA24_Pos</a>)</td></tr>
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<tr class="separator:ga5fe02633e558b53290fc5645ac903318"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d1adf29e37676017c67204623a45985" id="r_ga4d1adf29e37676017c67204623a45985"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d1adf29e37676017c67204623a45985">CAN_FFA1R_FFA24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe02633e558b53290fc5645ac903318">CAN_FFA1R_FFA24_Msk</a></td></tr>
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<tr class="separator:ga4d1adf29e37676017c67204623a45985"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcf4053a355ef612cbf6a56415cf8583" id="r_gafcf4053a355ef612cbf6a56415cf8583"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcf4053a355ef612cbf6a56415cf8583">CAN_FFA1R_FFA25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gafcf4053a355ef612cbf6a56415cf8583"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf586e3c813baaa9026b78e158c90df0c" id="r_gaf586e3c813baaa9026b78e158c90df0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf586e3c813baaa9026b78e158c90df0c">CAN_FFA1R_FFA25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcf4053a355ef612cbf6a56415cf8583">CAN_FFA1R_FFA25_Pos</a>)</td></tr>
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<tr class="separator:gaf586e3c813baaa9026b78e158c90df0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40553faf034d88e215c71d40c08f774e" id="r_ga40553faf034d88e215c71d40c08f774e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40553faf034d88e215c71d40c08f774e">CAN_FFA1R_FFA25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf586e3c813baaa9026b78e158c90df0c">CAN_FFA1R_FFA25_Msk</a></td></tr>
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<tr class="separator:ga40553faf034d88e215c71d40c08f774e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24094060ed59ce5c405fbb2f4212694a" id="r_ga24094060ed59ce5c405fbb2f4212694a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24094060ed59ce5c405fbb2f4212694a">CAN_FFA1R_FFA26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga24094060ed59ce5c405fbb2f4212694a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac224810fe7b45a273faa3d655bc64d44" id="r_gac224810fe7b45a273faa3d655bc64d44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac224810fe7b45a273faa3d655bc64d44">CAN_FFA1R_FFA26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24094060ed59ce5c405fbb2f4212694a">CAN_FFA1R_FFA26_Pos</a>)</td></tr>
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<tr class="separator:gac224810fe7b45a273faa3d655bc64d44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d347ff7528138f59d223adf7c838440" id="r_ga1d347ff7528138f59d223adf7c838440"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d347ff7528138f59d223adf7c838440">CAN_FFA1R_FFA26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac224810fe7b45a273faa3d655bc64d44">CAN_FFA1R_FFA26_Msk</a></td></tr>
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<tr class="memitem:ga7cf95c6d995ed5e1dded3e5d55020cbf" id="r_ga7cf95c6d995ed5e1dded3e5d55020cbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cf95c6d995ed5e1dded3e5d55020cbf">CAN_FFA1R_FFA27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga7cf95c6d995ed5e1dded3e5d55020cbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae312771a3ea200b9df91e30ddc1392d2" id="r_gae312771a3ea200b9df91e30ddc1392d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae312771a3ea200b9df91e30ddc1392d2">CAN_FFA1R_FFA27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cf95c6d995ed5e1dded3e5d55020cbf">CAN_FFA1R_FFA27_Pos</a>)</td></tr>
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<tr class="separator:gae312771a3ea200b9df91e30ddc1392d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ace5c7e4d87bebdc36d66de6cef7442" id="r_ga4ace5c7e4d87bebdc36d66de6cef7442"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ace5c7e4d87bebdc36d66de6cef7442">CAN_FFA1R_FFA27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae312771a3ea200b9df91e30ddc1392d2">CAN_FFA1R_FFA27_Msk</a></td></tr>
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<tr class="separator:ga4ace5c7e4d87bebdc36d66de6cef7442"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21e8eff485fa16ae0d289eacce72bd56" id="r_ga21e8eff485fa16ae0d289eacce72bd56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21e8eff485fa16ae0d289eacce72bd56">CAN_FA1R_FACT_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga21e8eff485fa16ae0d289eacce72bd56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f05941c6d7ad0294283a20dc4307a56" id="r_ga2f05941c6d7ad0294283a20dc4307a56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f05941c6d7ad0294283a20dc4307a56">CAN_FA1R_FACT_Msk</a>   (0xFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21e8eff485fa16ae0d289eacce72bd56">CAN_FA1R_FACT_Pos</a>)</td></tr>
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<tr class="separator:ga2f05941c6d7ad0294283a20dc4307a56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa571445875b08a9514e1d1b410a93ebd" id="r_gaa571445875b08a9514e1d1b410a93ebd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa571445875b08a9514e1d1b410a93ebd">CAN_FA1R_FACT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f05941c6d7ad0294283a20dc4307a56">CAN_FA1R_FACT_Msk</a></td></tr>
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<tr class="separator:gaa571445875b08a9514e1d1b410a93ebd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4be3d2c02fe8f070f95f234191482b86" id="r_ga4be3d2c02fe8f070f95f234191482b86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4be3d2c02fe8f070f95f234191482b86">CAN_FA1R_FACT0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4be3d2c02fe8f070f95f234191482b86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc33c5308d541004ba2961a7d0527278" id="r_gabc33c5308d541004ba2961a7d0527278"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc33c5308d541004ba2961a7d0527278">CAN_FA1R_FACT0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4be3d2c02fe8f070f95f234191482b86">CAN_FA1R_FACT0_Pos</a>)</td></tr>
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<tr class="separator:gabc33c5308d541004ba2961a7d0527278"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3ec1e2f9b9ccf2b4869cdf7c7328e60" id="r_gab3ec1e2f9b9ccf2b4869cdf7c7328e60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3ec1e2f9b9ccf2b4869cdf7c7328e60">CAN_FA1R_FACT0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabc33c5308d541004ba2961a7d0527278">CAN_FA1R_FACT0_Msk</a></td></tr>
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<tr class="separator:gab3ec1e2f9b9ccf2b4869cdf7c7328e60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd6506d842c27928a8647942fbdb0602" id="r_gabd6506d842c27928a8647942fbdb0602"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd6506d842c27928a8647942fbdb0602">CAN_FA1R_FACT1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gabd6506d842c27928a8647942fbdb0602"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10ee3a44fa9dc10a77c9a0668a19ddab" id="r_ga10ee3a44fa9dc10a77c9a0668a19ddab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10ee3a44fa9dc10a77c9a0668a19ddab">CAN_FA1R_FACT1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabd6506d842c27928a8647942fbdb0602">CAN_FA1R_FACT1_Pos</a>)</td></tr>
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<tr class="separator:ga10ee3a44fa9dc10a77c9a0668a19ddab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2457026460aecb52dba7ea17237b4dbe" id="r_ga2457026460aecb52dba7ea17237b4dbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2457026460aecb52dba7ea17237b4dbe">CAN_FA1R_FACT1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga10ee3a44fa9dc10a77c9a0668a19ddab">CAN_FA1R_FACT1_Msk</a></td></tr>
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<tr class="separator:ga2457026460aecb52dba7ea17237b4dbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac70ad8a114259387ba6eb4bf21a2c13" id="r_gaac70ad8a114259387ba6eb4bf21a2c13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac70ad8a114259387ba6eb4bf21a2c13">CAN_FA1R_FACT2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaac70ad8a114259387ba6eb4bf21a2c13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaafc57ac18afd7bd0eb14e84dbc265a83" id="r_gaafc57ac18afd7bd0eb14e84dbc265a83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafc57ac18afd7bd0eb14e84dbc265a83">CAN_FA1R_FACT2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaac70ad8a114259387ba6eb4bf21a2c13">CAN_FA1R_FACT2_Pos</a>)</td></tr>
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<tr class="separator:gaafc57ac18afd7bd0eb14e84dbc265a83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66354c26d0252cc86729365b315a69ee" id="r_ga66354c26d0252cc86729365b315a69ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66354c26d0252cc86729365b315a69ee">CAN_FA1R_FACT2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaafc57ac18afd7bd0eb14e84dbc265a83">CAN_FA1R_FACT2_Msk</a></td></tr>
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<tr class="separator:ga66354c26d0252cc86729365b315a69ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa93067be654983f42daf67ab9da3fbc3" id="r_gaa93067be654983f42daf67ab9da3fbc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa93067be654983f42daf67ab9da3fbc3">CAN_FA1R_FACT3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaa93067be654983f42daf67ab9da3fbc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b9b6a83d65b39753f8208f45d0d72ce" id="r_ga4b9b6a83d65b39753f8208f45d0d72ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b9b6a83d65b39753f8208f45d0d72ce">CAN_FA1R_FACT3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa93067be654983f42daf67ab9da3fbc3">CAN_FA1R_FACT3_Pos</a>)</td></tr>
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<tr class="separator:ga4b9b6a83d65b39753f8208f45d0d72ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga087dc5f2bdfe084eb98d2a0d06a29f1d" id="r_ga087dc5f2bdfe084eb98d2a0d06a29f1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga087dc5f2bdfe084eb98d2a0d06a29f1d">CAN_FA1R_FACT3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b9b6a83d65b39753f8208f45d0d72ce">CAN_FA1R_FACT3_Msk</a></td></tr>
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<tr class="separator:ga087dc5f2bdfe084eb98d2a0d06a29f1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd3f42141b00002a6db3db68ecd9909d" id="r_gafd3f42141b00002a6db3db68ecd9909d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd3f42141b00002a6db3db68ecd9909d">CAN_FA1R_FACT4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gafd3f42141b00002a6db3db68ecd9909d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga562dc354461029230ead72878c01ba30" id="r_ga562dc354461029230ead72878c01ba30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga562dc354461029230ead72878c01ba30">CAN_FA1R_FACT4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafd3f42141b00002a6db3db68ecd9909d">CAN_FA1R_FACT4_Pos</a>)</td></tr>
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<tr class="separator:ga562dc354461029230ead72878c01ba30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c46367b7e5ea831e34ba4cf824a63da" id="r_ga6c46367b7e5ea831e34ba4cf824a63da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c46367b7e5ea831e34ba4cf824a63da">CAN_FA1R_FACT4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga562dc354461029230ead72878c01ba30">CAN_FA1R_FACT4_Msk</a></td></tr>
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<tr class="separator:ga6c46367b7e5ea831e34ba4cf824a63da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf840e6f2d239bf5fc59c6f3454c2d122" id="r_gaf840e6f2d239bf5fc59c6f3454c2d122"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf840e6f2d239bf5fc59c6f3454c2d122">CAN_FA1R_FACT5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaf840e6f2d239bf5fc59c6f3454c2d122"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe67ef97c9d6b04fcad49eccad2ce8a1" id="r_gabe67ef97c9d6b04fcad49eccad2ce8a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe67ef97c9d6b04fcad49eccad2ce8a1">CAN_FA1R_FACT5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf840e6f2d239bf5fc59c6f3454c2d122">CAN_FA1R_FACT5_Pos</a>)</td></tr>
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<tr class="separator:gabe67ef97c9d6b04fcad49eccad2ce8a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga548238c7babf34116fdb44b4575e2664" id="r_ga548238c7babf34116fdb44b4575e2664"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga548238c7babf34116fdb44b4575e2664">CAN_FA1R_FACT5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe67ef97c9d6b04fcad49eccad2ce8a1">CAN_FA1R_FACT5_Msk</a></td></tr>
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<tr class="separator:ga548238c7babf34116fdb44b4575e2664"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga390f38386d4c2a6940d7dfe88bc4ab70" id="r_ga390f38386d4c2a6940d7dfe88bc4ab70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga390f38386d4c2a6940d7dfe88bc4ab70">CAN_FA1R_FACT6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga390f38386d4c2a6940d7dfe88bc4ab70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab13ad536db58592d5b4f2beb9c4f0469" id="r_gab13ad536db58592d5b4f2beb9c4f0469"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab13ad536db58592d5b4f2beb9c4f0469">CAN_FA1R_FACT6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga390f38386d4c2a6940d7dfe88bc4ab70">CAN_FA1R_FACT6_Pos</a>)</td></tr>
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<tr class="separator:gab13ad536db58592d5b4f2beb9c4f0469"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae403370a70f9ea2b6f9b449cafa6a91c" id="r_gae403370a70f9ea2b6f9b449cafa6a91c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae403370a70f9ea2b6f9b449cafa6a91c">CAN_FA1R_FACT6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab13ad536db58592d5b4f2beb9c4f0469">CAN_FA1R_FACT6_Msk</a></td></tr>
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<tr class="separator:gae403370a70f9ea2b6f9b449cafa6a91c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade2b7e97d515badec6d07154c8fdec2e" id="r_gade2b7e97d515badec6d07154c8fdec2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade2b7e97d515badec6d07154c8fdec2e">CAN_FA1R_FACT7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gade2b7e97d515badec6d07154c8fdec2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32a9fa687af9f4bc3800be29ee32a3e6" id="r_ga32a9fa687af9f4bc3800be29ee32a3e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32a9fa687af9f4bc3800be29ee32a3e6">CAN_FA1R_FACT7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade2b7e97d515badec6d07154c8fdec2e">CAN_FA1R_FACT7_Pos</a>)</td></tr>
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<tr class="separator:ga32a9fa687af9f4bc3800be29ee32a3e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33e9f4334cf3bf9e7e30d5edf278a02b" id="r_ga33e9f4334cf3bf9e7e30d5edf278a02b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33e9f4334cf3bf9e7e30d5edf278a02b">CAN_FA1R_FACT7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga32a9fa687af9f4bc3800be29ee32a3e6">CAN_FA1R_FACT7_Msk</a></td></tr>
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<tr class="separator:ga33e9f4334cf3bf9e7e30d5edf278a02b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac34978a6e1dbc7ff9a62d577d0473308" id="r_gac34978a6e1dbc7ff9a62d577d0473308"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac34978a6e1dbc7ff9a62d577d0473308">CAN_FA1R_FACT8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gac34978a6e1dbc7ff9a62d577d0473308"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9addaf5198f1b165bb8a1c5abe8c9a1f" id="r_ga9addaf5198f1b165bb8a1c5abe8c9a1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9addaf5198f1b165bb8a1c5abe8c9a1f">CAN_FA1R_FACT8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac34978a6e1dbc7ff9a62d577d0473308">CAN_FA1R_FACT8_Pos</a>)</td></tr>
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<tr class="separator:ga9addaf5198f1b165bb8a1c5abe8c9a1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ccbdd2932828bfa1d68777cb595f12e" id="r_ga0ccbdd2932828bfa1d68777cb595f12e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ccbdd2932828bfa1d68777cb595f12e">CAN_FA1R_FACT8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9addaf5198f1b165bb8a1c5abe8c9a1f">CAN_FA1R_FACT8_Msk</a></td></tr>
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<tr class="separator:ga0ccbdd2932828bfa1d68777cb595f12e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bd9a79b3e73c5343df683cb08e213e1" id="r_ga6bd9a79b3e73c5343df683cb08e213e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bd9a79b3e73c5343df683cb08e213e1">CAN_FA1R_FACT9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga6bd9a79b3e73c5343df683cb08e213e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9cb920b1dd24719e2fe959bc9fa27b2c" id="r_ga9cb920b1dd24719e2fe959bc9fa27b2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cb920b1dd24719e2fe959bc9fa27b2c">CAN_FA1R_FACT9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6bd9a79b3e73c5343df683cb08e213e1">CAN_FA1R_FACT9_Pos</a>)</td></tr>
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<tr class="separator:ga9cb920b1dd24719e2fe959bc9fa27b2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8e4011791e551feeae33c47ef2b6a6a" id="r_gaf8e4011791e551feeae33c47ef2b6a6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8e4011791e551feeae33c47ef2b6a6a">CAN_FA1R_FACT9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9cb920b1dd24719e2fe959bc9fa27b2c">CAN_FA1R_FACT9_Msk</a></td></tr>
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<tr class="separator:gaf8e4011791e551feeae33c47ef2b6a6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga095e0af1331f6dbf70921399cb9d5930" id="r_ga095e0af1331f6dbf70921399cb9d5930"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga095e0af1331f6dbf70921399cb9d5930">CAN_FA1R_FACT10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga095e0af1331f6dbf70921399cb9d5930"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafff61cabd030366925d3f3608cd81ec4" id="r_gafff61cabd030366925d3f3608cd81ec4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafff61cabd030366925d3f3608cd81ec4">CAN_FA1R_FACT10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga095e0af1331f6dbf70921399cb9d5930">CAN_FA1R_FACT10_Pos</a>)</td></tr>
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<tr class="separator:gafff61cabd030366925d3f3608cd81ec4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19696d8b702b33eafe7f18aa0c6c1955" id="r_ga19696d8b702b33eafe7f18aa0c6c1955"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19696d8b702b33eafe7f18aa0c6c1955">CAN_FA1R_FACT10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafff61cabd030366925d3f3608cd81ec4">CAN_FA1R_FACT10_Msk</a></td></tr>
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<tr class="separator:ga19696d8b702b33eafe7f18aa0c6c1955"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd79b5d1d4a66c46c60190ff3e356419" id="r_gabd79b5d1d4a66c46c60190ff3e356419"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd79b5d1d4a66c46c60190ff3e356419">CAN_FA1R_FACT11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gabd79b5d1d4a66c46c60190ff3e356419"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad043d708a8b891182f6f36217bba8a70" id="r_gad043d708a8b891182f6f36217bba8a70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad043d708a8b891182f6f36217bba8a70">CAN_FA1R_FACT11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabd79b5d1d4a66c46c60190ff3e356419">CAN_FA1R_FACT11_Pos</a>)</td></tr>
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<tr class="separator:gad043d708a8b891182f6f36217bba8a70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89e5e3ccd4250ad2360b91ef51248a66" id="r_ga89e5e3ccd4250ad2360b91ef51248a66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89e5e3ccd4250ad2360b91ef51248a66">CAN_FA1R_FACT11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad043d708a8b891182f6f36217bba8a70">CAN_FA1R_FACT11_Msk</a></td></tr>
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<tr class="separator:ga89e5e3ccd4250ad2360b91ef51248a66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ec82f6225d96fddd6fdb40033aa54d8" id="r_ga8ec82f6225d96fddd6fdb40033aa54d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ec82f6225d96fddd6fdb40033aa54d8">CAN_FA1R_FACT12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga8ec82f6225d96fddd6fdb40033aa54d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7de851ce57bd07d4913bd409dee3f51" id="r_gad7de851ce57bd07d4913bd409dee3f51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7de851ce57bd07d4913bd409dee3f51">CAN_FA1R_FACT12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ec82f6225d96fddd6fdb40033aa54d8">CAN_FA1R_FACT12_Pos</a>)</td></tr>
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<tr class="separator:gad7de851ce57bd07d4913bd409dee3f51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae78ec392640f05b20a7c6877983588ae" id="r_gae78ec392640f05b20a7c6877983588ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae78ec392640f05b20a7c6877983588ae">CAN_FA1R_FACT12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad7de851ce57bd07d4913bd409dee3f51">CAN_FA1R_FACT12_Msk</a></td></tr>
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<tr class="separator:gae78ec392640f05b20a7c6877983588ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6056bd9c2a6de9289b06bbcd0eab4599" id="r_ga6056bd9c2a6de9289b06bbcd0eab4599"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6056bd9c2a6de9289b06bbcd0eab4599">CAN_FA1R_FACT13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga6056bd9c2a6de9289b06bbcd0eab4599"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fc2cc6acea1e2a86083f9f0d5ce05c0" id="r_ga5fc2cc6acea1e2a86083f9f0d5ce05c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fc2cc6acea1e2a86083f9f0d5ce05c0">CAN_FA1R_FACT13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6056bd9c2a6de9289b06bbcd0eab4599">CAN_FA1R_FACT13_Pos</a>)</td></tr>
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<tr class="separator:ga5fc2cc6acea1e2a86083f9f0d5ce05c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa722eeef87f8a3f58ebfcb531645cc05" id="r_gaa722eeef87f8a3f58ebfcb531645cc05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa722eeef87f8a3f58ebfcb531645cc05">CAN_FA1R_FACT13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fc2cc6acea1e2a86083f9f0d5ce05c0">CAN_FA1R_FACT13_Msk</a></td></tr>
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<tr class="separator:gaa722eeef87f8a3f58ebfcb531645cc05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8afb5078389340fd934c7f18978f45ce" id="r_ga8afb5078389340fd934c7f18978f45ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8afb5078389340fd934c7f18978f45ce">CAN_FA1R_FACT14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga8afb5078389340fd934c7f18978f45ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5aad7b1d23bd498ecd99b4adcb239560" id="r_ga5aad7b1d23bd498ecd99b4adcb239560"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5aad7b1d23bd498ecd99b4adcb239560">CAN_FA1R_FACT14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8afb5078389340fd934c7f18978f45ce">CAN_FA1R_FACT14_Pos</a>)</td></tr>
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<tr class="separator:ga5aad7b1d23bd498ecd99b4adcb239560"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2de45b22180cee8e9b3fef000869af3" id="r_gae2de45b22180cee8e9b3fef000869af3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2de45b22180cee8e9b3fef000869af3">CAN_FA1R_FACT14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5aad7b1d23bd498ecd99b4adcb239560">CAN_FA1R_FACT14_Msk</a></td></tr>
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<tr class="separator:gae2de45b22180cee8e9b3fef000869af3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83dd3c9202d4e42a35c2b5ccb4eee21b" id="r_ga83dd3c9202d4e42a35c2b5ccb4eee21b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83dd3c9202d4e42a35c2b5ccb4eee21b">CAN_FA1R_FACT15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga83dd3c9202d4e42a35c2b5ccb4eee21b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d0e0b9363ac2965048f42ce3abc9518" id="r_ga2d0e0b9363ac2965048f42ce3abc9518"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d0e0b9363ac2965048f42ce3abc9518">CAN_FA1R_FACT15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83dd3c9202d4e42a35c2b5ccb4eee21b">CAN_FA1R_FACT15_Pos</a>)</td></tr>
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<tr class="separator:ga2d0e0b9363ac2965048f42ce3abc9518"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9e8c965500f24cb92a72038e9db3a03" id="r_gab9e8c965500f24cb92a72038e9db3a03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9e8c965500f24cb92a72038e9db3a03">CAN_FA1R_FACT15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d0e0b9363ac2965048f42ce3abc9518">CAN_FA1R_FACT15_Msk</a></td></tr>
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<tr class="separator:gab9e8c965500f24cb92a72038e9db3a03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0dd1b09262007ca3c8753891838f2291" id="r_ga0dd1b09262007ca3c8753891838f2291"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dd1b09262007ca3c8753891838f2291">CAN_FA1R_FACT16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga0dd1b09262007ca3c8753891838f2291"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b832148df149f3f89b168bf1da68449" id="r_ga2b832148df149f3f89b168bf1da68449"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b832148df149f3f89b168bf1da68449">CAN_FA1R_FACT16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dd1b09262007ca3c8753891838f2291">CAN_FA1R_FACT16_Pos</a>)</td></tr>
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<tr class="separator:ga2b832148df149f3f89b168bf1da68449"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4054fdf1fced195e59509a2282fd023" id="r_gae4054fdf1fced195e59509a2282fd023"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4054fdf1fced195e59509a2282fd023">CAN_FA1R_FACT16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b832148df149f3f89b168bf1da68449">CAN_FA1R_FACT16_Msk</a></td></tr>
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<tr class="separator:gae4054fdf1fced195e59509a2282fd023"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga061545e7d6c13e4699c81dc71e7ac59d" id="r_ga061545e7d6c13e4699c81dc71e7ac59d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga061545e7d6c13e4699c81dc71e7ac59d">CAN_FA1R_FACT17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga061545e7d6c13e4699c81dc71e7ac59d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec1081e22c20c398d0a24cf2dba852ba" id="r_gaec1081e22c20c398d0a24cf2dba852ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec1081e22c20c398d0a24cf2dba852ba">CAN_FA1R_FACT17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga061545e7d6c13e4699c81dc71e7ac59d">CAN_FA1R_FACT17_Pos</a>)</td></tr>
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<tr class="separator:gaec1081e22c20c398d0a24cf2dba852ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a0970d03bb791397495af0762f54d65" id="r_ga3a0970d03bb791397495af0762f54d65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a0970d03bb791397495af0762f54d65">CAN_FA1R_FACT17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec1081e22c20c398d0a24cf2dba852ba">CAN_FA1R_FACT17_Msk</a></td></tr>
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<tr class="separator:ga3a0970d03bb791397495af0762f54d65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccded4c9f678c1e12ecd3f296eaa6f6b" id="r_gaccded4c9f678c1e12ecd3f296eaa6f6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccded4c9f678c1e12ecd3f296eaa6f6b">CAN_FA1R_FACT18_Pos</a>   (18U)</td></tr>
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<tr class="separator:gaccded4c9f678c1e12ecd3f296eaa6f6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0844889fa76d91d278d5694d916a04ca" id="r_ga0844889fa76d91d278d5694d916a04ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0844889fa76d91d278d5694d916a04ca">CAN_FA1R_FACT18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaccded4c9f678c1e12ecd3f296eaa6f6b">CAN_FA1R_FACT18_Pos</a>)</td></tr>
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<tr class="separator:ga0844889fa76d91d278d5694d916a04ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98ba61a8ef9d4e5cea606148281e432d" id="r_ga98ba61a8ef9d4e5cea606148281e432d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98ba61a8ef9d4e5cea606148281e432d">CAN_FA1R_FACT18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0844889fa76d91d278d5694d916a04ca">CAN_FA1R_FACT18_Msk</a></td></tr>
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<tr class="separator:ga98ba61a8ef9d4e5cea606148281e432d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga707b4f7a3fd6e7ed30c17c5cd1933ef3" id="r_ga707b4f7a3fd6e7ed30c17c5cd1933ef3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga707b4f7a3fd6e7ed30c17c5cd1933ef3">CAN_FA1R_FACT19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga707b4f7a3fd6e7ed30c17c5cd1933ef3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74353cfdb58079f47563079de3fd778b" id="r_ga74353cfdb58079f47563079de3fd778b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74353cfdb58079f47563079de3fd778b">CAN_FA1R_FACT19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga707b4f7a3fd6e7ed30c17c5cd1933ef3">CAN_FA1R_FACT19_Pos</a>)</td></tr>
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<tr class="separator:ga74353cfdb58079f47563079de3fd778b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87064c634cec6fc2ee70fecbb04b92c2" id="r_ga87064c634cec6fc2ee70fecbb04b92c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87064c634cec6fc2ee70fecbb04b92c2">CAN_FA1R_FACT19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga74353cfdb58079f47563079de3fd778b">CAN_FA1R_FACT19_Msk</a></td></tr>
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<tr class="separator:ga87064c634cec6fc2ee70fecbb04b92c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a3d2f351f0a92a5604b01e36a921de2" id="r_ga0a3d2f351f0a92a5604b01e36a921de2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a3d2f351f0a92a5604b01e36a921de2">CAN_FA1R_FACT20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga0a3d2f351f0a92a5604b01e36a921de2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga093d17300bad7b8fa43bd6d264b07217" id="r_ga093d17300bad7b8fa43bd6d264b07217"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga093d17300bad7b8fa43bd6d264b07217">CAN_FA1R_FACT20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a3d2f351f0a92a5604b01e36a921de2">CAN_FA1R_FACT20_Pos</a>)</td></tr>
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<tr class="separator:ga093d17300bad7b8fa43bd6d264b07217"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0222f2ac5c4d4b9e6382d4dd8286bb2" id="r_gaa0222f2ac5c4d4b9e6382d4dd8286bb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0222f2ac5c4d4b9e6382d4dd8286bb2">CAN_FA1R_FACT20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga093d17300bad7b8fa43bd6d264b07217">CAN_FA1R_FACT20_Msk</a></td></tr>
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<tr class="separator:gaa0222f2ac5c4d4b9e6382d4dd8286bb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae280cc92b21856b1da77deef88ae0aea" id="r_gae280cc92b21856b1da77deef88ae0aea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae280cc92b21856b1da77deef88ae0aea">CAN_FA1R_FACT21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gae280cc92b21856b1da77deef88ae0aea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bcf854bcce93e28d97db435631b81d8" id="r_ga4bcf854bcce93e28d97db435631b81d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bcf854bcce93e28d97db435631b81d8">CAN_FA1R_FACT21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae280cc92b21856b1da77deef88ae0aea">CAN_FA1R_FACT21_Pos</a>)</td></tr>
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<tr class="separator:ga4bcf854bcce93e28d97db435631b81d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22534866322499e9d05513f0d41754fe" id="r_ga22534866322499e9d05513f0d41754fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22534866322499e9d05513f0d41754fe">CAN_FA1R_FACT21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bcf854bcce93e28d97db435631b81d8">CAN_FA1R_FACT21_Msk</a></td></tr>
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<tr class="separator:ga22534866322499e9d05513f0d41754fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae195ba574d695a543786b5a60e2535d3" id="r_gae195ba574d695a543786b5a60e2535d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae195ba574d695a543786b5a60e2535d3">CAN_FA1R_FACT22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gae195ba574d695a543786b5a60e2535d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1090ef53e33de146fb08fdee8e8874f9" id="r_ga1090ef53e33de146fb08fdee8e8874f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1090ef53e33de146fb08fdee8e8874f9">CAN_FA1R_FACT22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae195ba574d695a543786b5a60e2535d3">CAN_FA1R_FACT22_Pos</a>)</td></tr>
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<tr class="separator:ga1090ef53e33de146fb08fdee8e8874f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9febd35acb8257833bf9dbbe18b063b" id="r_gad9febd35acb8257833bf9dbbe18b063b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9febd35acb8257833bf9dbbe18b063b">CAN_FA1R_FACT22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1090ef53e33de146fb08fdee8e8874f9">CAN_FA1R_FACT22_Msk</a></td></tr>
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<tr class="separator:gad9febd35acb8257833bf9dbbe18b063b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36f892196608ea5f8567c9027e5f8f36" id="r_ga36f892196608ea5f8567c9027e5f8f36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36f892196608ea5f8567c9027e5f8f36">CAN_FA1R_FACT23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga36f892196608ea5f8567c9027e5f8f36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64eea4ed2c7c6a0c0c1a1b2e4acfd32f" id="r_ga64eea4ed2c7c6a0c0c1a1b2e4acfd32f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64eea4ed2c7c6a0c0c1a1b2e4acfd32f">CAN_FA1R_FACT23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga36f892196608ea5f8567c9027e5f8f36">CAN_FA1R_FACT23_Pos</a>)</td></tr>
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<tr class="separator:ga64eea4ed2c7c6a0c0c1a1b2e4acfd32f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12e95e773be98669c171971d3be8cc8b" id="r_ga12e95e773be98669c171971d3be8cc8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12e95e773be98669c171971d3be8cc8b">CAN_FA1R_FACT23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64eea4ed2c7c6a0c0c1a1b2e4acfd32f">CAN_FA1R_FACT23_Msk</a></td></tr>
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<tr class="separator:ga12e95e773be98669c171971d3be8cc8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga311ef25d716f12e324d3dccbe2f8ec66" id="r_ga311ef25d716f12e324d3dccbe2f8ec66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga311ef25d716f12e324d3dccbe2f8ec66">CAN_FA1R_FACT24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga311ef25d716f12e324d3dccbe2f8ec66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57f3f41e8a31cd07be66cbd05eabfbe4" id="r_ga57f3f41e8a31cd07be66cbd05eabfbe4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57f3f41e8a31cd07be66cbd05eabfbe4">CAN_FA1R_FACT24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga311ef25d716f12e324d3dccbe2f8ec66">CAN_FA1R_FACT24_Pos</a>)</td></tr>
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<tr class="separator:ga57f3f41e8a31cd07be66cbd05eabfbe4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63dd04052a79614027b3efe30ea1724a" id="r_ga63dd04052a79614027b3efe30ea1724a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63dd04052a79614027b3efe30ea1724a">CAN_FA1R_FACT24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57f3f41e8a31cd07be66cbd05eabfbe4">CAN_FA1R_FACT24_Msk</a></td></tr>
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<tr class="separator:ga63dd04052a79614027b3efe30ea1724a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5dfb5fd56f8ed22e24ee02ebbf37d58c" id="r_ga5dfb5fd56f8ed22e24ee02ebbf37d58c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5dfb5fd56f8ed22e24ee02ebbf37d58c">CAN_FA1R_FACT25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga5dfb5fd56f8ed22e24ee02ebbf37d58c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d5955b25bf2b59795d8864719ff0bf0" id="r_ga0d5955b25bf2b59795d8864719ff0bf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d5955b25bf2b59795d8864719ff0bf0">CAN_FA1R_FACT25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5dfb5fd56f8ed22e24ee02ebbf37d58c">CAN_FA1R_FACT25_Pos</a>)</td></tr>
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<tr class="separator:ga0d5955b25bf2b59795d8864719ff0bf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga994fbfb885e73b4221b64f8bcb19631e" id="r_ga994fbfb885e73b4221b64f8bcb19631e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga994fbfb885e73b4221b64f8bcb19631e">CAN_FA1R_FACT25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d5955b25bf2b59795d8864719ff0bf0">CAN_FA1R_FACT25_Msk</a></td></tr>
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<tr class="separator:ga994fbfb885e73b4221b64f8bcb19631e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01ddadbe0437498108088593d769776e" id="r_ga01ddadbe0437498108088593d769776e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01ddadbe0437498108088593d769776e">CAN_FA1R_FACT26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga01ddadbe0437498108088593d769776e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac30095caad0d9f62fc1aa0ba0ddd70c7" id="r_gac30095caad0d9f62fc1aa0ba0ddd70c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac30095caad0d9f62fc1aa0ba0ddd70c7">CAN_FA1R_FACT26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01ddadbe0437498108088593d769776e">CAN_FA1R_FACT26_Pos</a>)</td></tr>
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<tr class="separator:gac30095caad0d9f62fc1aa0ba0ddd70c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf64c2c798a0c3bbe2745bf603e034a89" id="r_gaf64c2c798a0c3bbe2745bf603e034a89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf64c2c798a0c3bbe2745bf603e034a89">CAN_FA1R_FACT26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac30095caad0d9f62fc1aa0ba0ddd70c7">CAN_FA1R_FACT26_Msk</a></td></tr>
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<tr class="separator:gaf64c2c798a0c3bbe2745bf603e034a89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20dee91cf99643da8f3cbcabefe188dc" id="r_ga20dee91cf99643da8f3cbcabefe188dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20dee91cf99643da8f3cbcabefe188dc">CAN_FA1R_FACT27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga20dee91cf99643da8f3cbcabefe188dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4c4ecc7e23c652a42b36df4494bc0bf" id="r_gae4c4ecc7e23c652a42b36df4494bc0bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4c4ecc7e23c652a42b36df4494bc0bf">CAN_FA1R_FACT27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20dee91cf99643da8f3cbcabefe188dc">CAN_FA1R_FACT27_Pos</a>)</td></tr>
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<tr class="separator:gae4c4ecc7e23c652a42b36df4494bc0bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf72e900b51c3c380a81832d0314643c2" id="r_gaf72e900b51c3c380a81832d0314643c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf72e900b51c3c380a81832d0314643c2">CAN_FA1R_FACT27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae4c4ecc7e23c652a42b36df4494bc0bf">CAN_FA1R_FACT27_Msk</a></td></tr>
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<tr class="separator:gaf72e900b51c3c380a81832d0314643c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c98aba7c4d97ff22da1127911917846" id="r_ga7c98aba7c4d97ff22da1127911917846"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c98aba7c4d97ff22da1127911917846">CAN_F0R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7c98aba7c4d97ff22da1127911917846"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf41ce0d3efb93360593d51fc1507ef37" id="r_gaf41ce0d3efb93360593d51fc1507ef37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf41ce0d3efb93360593d51fc1507ef37">CAN_F0R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c98aba7c4d97ff22da1127911917846">CAN_F0R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:gaf41ce0d3efb93360593d51fc1507ef37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38014ea45b62975627f8e222390f6819" id="r_ga38014ea45b62975627f8e222390f6819"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38014ea45b62975627f8e222390f6819">CAN_F0R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf41ce0d3efb93360593d51fc1507ef37">CAN_F0R1_FB0_Msk</a></td></tr>
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<tr class="separator:ga38014ea45b62975627f8e222390f6819"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa503478584d6bd0535d29df9839816a0" id="r_gaa503478584d6bd0535d29df9839816a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa503478584d6bd0535d29df9839816a0">CAN_F0R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaa503478584d6bd0535d29df9839816a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf16111eec26fa5058aeac0945c0a481" id="r_gaaf16111eec26fa5058aeac0945c0a481"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf16111eec26fa5058aeac0945c0a481">CAN_F0R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa503478584d6bd0535d29df9839816a0">CAN_F0R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:gaaf16111eec26fa5058aeac0945c0a481"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e01c05df79304035c7aab1c7295bf3f" id="r_ga9e01c05df79304035c7aab1c7295bf3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e01c05df79304035c7aab1c7295bf3f">CAN_F0R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf16111eec26fa5058aeac0945c0a481">CAN_F0R1_FB1_Msk</a></td></tr>
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<tr class="separator:ga9e01c05df79304035c7aab1c7295bf3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30edb71ea81cfa7a3e881e2692093d70" id="r_ga30edb71ea81cfa7a3e881e2692093d70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30edb71ea81cfa7a3e881e2692093d70">CAN_F0R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga30edb71ea81cfa7a3e881e2692093d70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga269a36e254bdc397d46b7b04b25cf58c" id="r_ga269a36e254bdc397d46b7b04b25cf58c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga269a36e254bdc397d46b7b04b25cf58c">CAN_F0R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30edb71ea81cfa7a3e881e2692093d70">CAN_F0R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga269a36e254bdc397d46b7b04b25cf58c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga083282146d4db7f757fef86cf302eded" id="r_ga083282146d4db7f757fef86cf302eded"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga083282146d4db7f757fef86cf302eded">CAN_F0R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga269a36e254bdc397d46b7b04b25cf58c">CAN_F0R1_FB2_Msk</a></td></tr>
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<tr class="separator:ga083282146d4db7f757fef86cf302eded"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3365da181d4986260f3f1d0adfe2337a" id="r_ga3365da181d4986260f3f1d0adfe2337a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3365da181d4986260f3f1d0adfe2337a">CAN_F0R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga3365da181d4986260f3f1d0adfe2337a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad40133f8c3bdff4edac51999e63eb616" id="r_gad40133f8c3bdff4edac51999e63eb616"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad40133f8c3bdff4edac51999e63eb616">CAN_F0R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3365da181d4986260f3f1d0adfe2337a">CAN_F0R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:gad40133f8c3bdff4edac51999e63eb616"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4a1adc2e4e550a38649a2bfd3662680" id="r_gae4a1adc2e4e550a38649a2bfd3662680"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4a1adc2e4e550a38649a2bfd3662680">CAN_F0R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad40133f8c3bdff4edac51999e63eb616">CAN_F0R1_FB3_Msk</a></td></tr>
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<tr class="separator:gae4a1adc2e4e550a38649a2bfd3662680"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5732df35cf88b47553b239d79818d29f" id="r_ga5732df35cf88b47553b239d79818d29f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5732df35cf88b47553b239d79818d29f">CAN_F0R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga5732df35cf88b47553b239d79818d29f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5be6df46bddda042bca88f23939d6cf" id="r_gac5be6df46bddda042bca88f23939d6cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5be6df46bddda042bca88f23939d6cf">CAN_F0R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5732df35cf88b47553b239d79818d29f">CAN_F0R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:gac5be6df46bddda042bca88f23939d6cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0bfa15bf30fefb21f351228cde87981" id="r_gaa0bfa15bf30fefb21f351228cde87981"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0bfa15bf30fefb21f351228cde87981">CAN_F0R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac5be6df46bddda042bca88f23939d6cf">CAN_F0R1_FB4_Msk</a></td></tr>
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<tr class="separator:gaa0bfa15bf30fefb21f351228cde87981"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ef90325b70b6dbc93a5468d6571ae60" id="r_ga1ef90325b70b6dbc93a5468d6571ae60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ef90325b70b6dbc93a5468d6571ae60">CAN_F0R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga1ef90325b70b6dbc93a5468d6571ae60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0d0c4979d148b7aadf88999d127a8e4" id="r_gae0d0c4979d148b7aadf88999d127a8e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0d0c4979d148b7aadf88999d127a8e4">CAN_F0R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ef90325b70b6dbc93a5468d6571ae60">CAN_F0R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:gae0d0c4979d148b7aadf88999d127a8e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5381c154ba89611bf4381657305ecb85" id="r_ga5381c154ba89611bf4381657305ecb85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5381c154ba89611bf4381657305ecb85">CAN_F0R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae0d0c4979d148b7aadf88999d127a8e4">CAN_F0R1_FB5_Msk</a></td></tr>
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<tr class="separator:ga5381c154ba89611bf4381657305ecb85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58c06570c4e947c9f58d0fa0ec81490b" id="r_ga58c06570c4e947c9f58d0fa0ec81490b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58c06570c4e947c9f58d0fa0ec81490b">CAN_F0R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga58c06570c4e947c9f58d0fa0ec81490b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga559e44745ca384b08f8e3d370539e2a4" id="r_ga559e44745ca384b08f8e3d370539e2a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga559e44745ca384b08f8e3d370539e2a4">CAN_F0R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58c06570c4e947c9f58d0fa0ec81490b">CAN_F0R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga559e44745ca384b08f8e3d370539e2a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae224160853946732608f00ad008a6b1a" id="r_gae224160853946732608f00ad008a6b1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae224160853946732608f00ad008a6b1a">CAN_F0R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga559e44745ca384b08f8e3d370539e2a4">CAN_F0R1_FB6_Msk</a></td></tr>
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<tr class="separator:gae224160853946732608f00ad008a6b1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19c4bdfb75f490af25c59c8feabf2be0" id="r_ga19c4bdfb75f490af25c59c8feabf2be0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19c4bdfb75f490af25c59c8feabf2be0">CAN_F0R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga19c4bdfb75f490af25c59c8feabf2be0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d0b187d74d01d2d7a9e0946287a523f" id="r_ga6d0b187d74d01d2d7a9e0946287a523f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d0b187d74d01d2d7a9e0946287a523f">CAN_F0R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga19c4bdfb75f490af25c59c8feabf2be0">CAN_F0R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga6d0b187d74d01d2d7a9e0946287a523f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0c44034b5f42fa8250dbb8e46bc83eb" id="r_gaa0c44034b5f42fa8250dbb8e46bc83eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0c44034b5f42fa8250dbb8e46bc83eb">CAN_F0R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d0b187d74d01d2d7a9e0946287a523f">CAN_F0R1_FB7_Msk</a></td></tr>
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<tr class="separator:gaa0c44034b5f42fa8250dbb8e46bc83eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6ba4e35ff552a0750f809d3749a5861" id="r_gac6ba4e35ff552a0750f809d3749a5861"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6ba4e35ff552a0750f809d3749a5861">CAN_F0R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gac6ba4e35ff552a0750f809d3749a5861"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae373e9d2f9a170895ffab6051243a0f6" id="r_gae373e9d2f9a170895ffab6051243a0f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae373e9d2f9a170895ffab6051243a0f6">CAN_F0R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac6ba4e35ff552a0750f809d3749a5861">CAN_F0R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:gae373e9d2f9a170895ffab6051243a0f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga465e092af3e73882f9eaffad13f36dea" id="r_ga465e092af3e73882f9eaffad13f36dea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga465e092af3e73882f9eaffad13f36dea">CAN_F0R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae373e9d2f9a170895ffab6051243a0f6">CAN_F0R1_FB8_Msk</a></td></tr>
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<tr class="separator:ga465e092af3e73882f9eaffad13f36dea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea4ec2d33b8ef0f635bfac9654be0551" id="r_gaea4ec2d33b8ef0f635bfac9654be0551"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea4ec2d33b8ef0f635bfac9654be0551">CAN_F0R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaea4ec2d33b8ef0f635bfac9654be0551"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ac0f1442cbee02cb21fca28b5fc61f6" id="r_ga4ac0f1442cbee02cb21fca28b5fc61f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ac0f1442cbee02cb21fca28b5fc61f6">CAN_F0R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea4ec2d33b8ef0f635bfac9654be0551">CAN_F0R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga4ac0f1442cbee02cb21fca28b5fc61f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1cb7ff6d513fec365eb5a830c3746f0" id="r_gad1cb7ff6d513fec365eb5a830c3746f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1cb7ff6d513fec365eb5a830c3746f0">CAN_F0R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ac0f1442cbee02cb21fca28b5fc61f6">CAN_F0R1_FB9_Msk</a></td></tr>
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<tr class="separator:gad1cb7ff6d513fec365eb5a830c3746f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5df4d89fa55adb9f8984b482e8b84598" id="r_ga5df4d89fa55adb9f8984b482e8b84598"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5df4d89fa55adb9f8984b482e8b84598">CAN_F0R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga5df4d89fa55adb9f8984b482e8b84598"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabcb7c073dbc77461d7519a85f6377a08" id="r_gabcb7c073dbc77461d7519a85f6377a08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabcb7c073dbc77461d7519a85f6377a08">CAN_F0R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5df4d89fa55adb9f8984b482e8b84598">CAN_F0R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:gabcb7c073dbc77461d7519a85f6377a08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b8a688856ca6b53417948f79932534d" id="r_ga6b8a688856ca6b53417948f79932534d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b8a688856ca6b53417948f79932534d">CAN_F0R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabcb7c073dbc77461d7519a85f6377a08">CAN_F0R1_FB10_Msk</a></td></tr>
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<tr class="separator:ga6b8a688856ca6b53417948f79932534d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51c39129e454b5f9ea84e7ff296d977b" id="r_ga51c39129e454b5f9ea84e7ff296d977b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51c39129e454b5f9ea84e7ff296d977b">CAN_F0R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga51c39129e454b5f9ea84e7ff296d977b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f982ab6a096e4421079c592b6791d47" id="r_ga8f982ab6a096e4421079c592b6791d47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f982ab6a096e4421079c592b6791d47">CAN_F0R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga51c39129e454b5f9ea84e7ff296d977b">CAN_F0R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga8f982ab6a096e4421079c592b6791d47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72b81011a2d626ac398a387c89055935" id="r_ga72b81011a2d626ac398a387c89055935"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72b81011a2d626ac398a387c89055935">CAN_F0R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f982ab6a096e4421079c592b6791d47">CAN_F0R1_FB11_Msk</a></td></tr>
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<tr class="separator:ga72b81011a2d626ac398a387c89055935"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83390adff1d103861b00e3a6a7ff4eb2" id="r_ga83390adff1d103861b00e3a6a7ff4eb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83390adff1d103861b00e3a6a7ff4eb2">CAN_F0R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga83390adff1d103861b00e3a6a7ff4eb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac70bfdc26446118697edbcd2d95b7676" id="r_gac70bfdc26446118697edbcd2d95b7676"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac70bfdc26446118697edbcd2d95b7676">CAN_F0R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83390adff1d103861b00e3a6a7ff4eb2">CAN_F0R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:gac70bfdc26446118697edbcd2d95b7676"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac178a6710aeb6c58f725dd7f00af5d5a" id="r_gac178a6710aeb6c58f725dd7f00af5d5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac178a6710aeb6c58f725dd7f00af5d5a">CAN_F0R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac70bfdc26446118697edbcd2d95b7676">CAN_F0R1_FB12_Msk</a></td></tr>
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<tr class="separator:gac178a6710aeb6c58f725dd7f00af5d5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cb3bc6c8af39e8e548d35945c4b4ec0" id="r_ga6cb3bc6c8af39e8e548d35945c4b4ec0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cb3bc6c8af39e8e548d35945c4b4ec0">CAN_F0R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="memitem:gad67a5fe07e6f9e3b3330ad2a46d69d98" id="r_gad67a5fe07e6f9e3b3330ad2a46d69d98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad67a5fe07e6f9e3b3330ad2a46d69d98">CAN_F0R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cb3bc6c8af39e8e548d35945c4b4ec0">CAN_F0R1_FB13_Pos</a>)</td></tr>
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<tr class="memitem:ga8aee1182bef65da056242c4ed49dd0ef" id="r_ga8aee1182bef65da056242c4ed49dd0ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8aee1182bef65da056242c4ed49dd0ef">CAN_F0R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad67a5fe07e6f9e3b3330ad2a46d69d98">CAN_F0R1_FB13_Msk</a></td></tr>
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<tr class="memitem:ga0802c1f18214f151a01a44be1669efac" id="r_ga0802c1f18214f151a01a44be1669efac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0802c1f18214f151a01a44be1669efac">CAN_F0R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gac932d38da89bcc4fe8cde14ebb59a29e" id="r_gac932d38da89bcc4fe8cde14ebb59a29e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac932d38da89bcc4fe8cde14ebb59a29e">CAN_F0R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0802c1f18214f151a01a44be1669efac">CAN_F0R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:gac932d38da89bcc4fe8cde14ebb59a29e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe16c95f454da44949977e4225590658" id="r_gafe16c95f454da44949977e4225590658"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe16c95f454da44949977e4225590658">CAN_F0R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac932d38da89bcc4fe8cde14ebb59a29e">CAN_F0R1_FB14_Msk</a></td></tr>
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<tr class="separator:gafe16c95f454da44949977e4225590658"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa270d9f780ab40ae9dc1a3650d4bd8d5" id="r_gaa270d9f780ab40ae9dc1a3650d4bd8d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa270d9f780ab40ae9dc1a3650d4bd8d5">CAN_F0R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaa270d9f780ab40ae9dc1a3650d4bd8d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71b253d3185e16b606150fee2a19760d" id="r_ga71b253d3185e16b606150fee2a19760d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71b253d3185e16b606150fee2a19760d">CAN_F0R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa270d9f780ab40ae9dc1a3650d4bd8d5">CAN_F0R1_FB15_Pos</a>)</td></tr>
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<tr class="memitem:gabb07dca9fddf64a3476f25f227e33e1f" id="r_gabb07dca9fddf64a3476f25f227e33e1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb07dca9fddf64a3476f25f227e33e1f">CAN_F0R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71b253d3185e16b606150fee2a19760d">CAN_F0R1_FB15_Msk</a></td></tr>
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<tr class="memitem:gad7ff7c8fd59e93239bfc6b509e3698ce" id="r_gad7ff7c8fd59e93239bfc6b509e3698ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7ff7c8fd59e93239bfc6b509e3698ce">CAN_F0R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:gad7ff7c8fd59e93239bfc6b509e3698ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab87631b267fd39cfee4d253a3d7295b2" id="r_gab87631b267fd39cfee4d253a3d7295b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab87631b267fd39cfee4d253a3d7295b2">CAN_F0R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad7ff7c8fd59e93239bfc6b509e3698ce">CAN_F0R1_FB16_Pos</a>)</td></tr>
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<tr class="memitem:gaf019423a4b07e564dfe917b859e68e80" id="r_gaf019423a4b07e564dfe917b859e68e80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf019423a4b07e564dfe917b859e68e80">CAN_F0R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab87631b267fd39cfee4d253a3d7295b2">CAN_F0R1_FB16_Msk</a></td></tr>
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<tr class="separator:gaf019423a4b07e564dfe917b859e68e80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga594b502afc2b215e7b712f53a14bc5bc" id="r_ga594b502afc2b215e7b712f53a14bc5bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga594b502afc2b215e7b712f53a14bc5bc">CAN_F0R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga594b502afc2b215e7b712f53a14bc5bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa35416758e3db5bceaff708bdbe5bdc0" id="r_gaa35416758e3db5bceaff708bdbe5bdc0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa35416758e3db5bceaff708bdbe5bdc0">CAN_F0R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga594b502afc2b215e7b712f53a14bc5bc">CAN_F0R1_FB17_Pos</a>)</td></tr>
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<tr class="separator:gaa35416758e3db5bceaff708bdbe5bdc0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ee508d40637a9d558d2ab85753395bd" id="r_ga6ee508d40637a9d558d2ab85753395bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ee508d40637a9d558d2ab85753395bd">CAN_F0R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa35416758e3db5bceaff708bdbe5bdc0">CAN_F0R1_FB17_Msk</a></td></tr>
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<tr class="separator:ga6ee508d40637a9d558d2ab85753395bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf097e8cb0757c526b83c45390ffa4b26" id="r_gaf097e8cb0757c526b83c45390ffa4b26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf097e8cb0757c526b83c45390ffa4b26">CAN_F0R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:gaf097e8cb0757c526b83c45390ffa4b26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1a49c7f4d13a4e4b4038caaea711391" id="r_gac1a49c7f4d13a4e4b4038caaea711391"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1a49c7f4d13a4e4b4038caaea711391">CAN_F0R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf097e8cb0757c526b83c45390ffa4b26">CAN_F0R1_FB18_Pos</a>)</td></tr>
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<tr class="separator:gac1a49c7f4d13a4e4b4038caaea711391"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga827a459cd51a193d571a16e1d38fac22" id="r_ga827a459cd51a193d571a16e1d38fac22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga827a459cd51a193d571a16e1d38fac22">CAN_F0R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac1a49c7f4d13a4e4b4038caaea711391">CAN_F0R1_FB18_Msk</a></td></tr>
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<tr class="memitem:ga467f1f2d0208a355d18cdd375eef9aed" id="r_ga467f1f2d0208a355d18cdd375eef9aed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga467f1f2d0208a355d18cdd375eef9aed">CAN_F0R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga467f1f2d0208a355d18cdd375eef9aed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75a34023fcd221fc010aaa51065d59dc" id="r_ga75a34023fcd221fc010aaa51065d59dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75a34023fcd221fc010aaa51065d59dc">CAN_F0R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga467f1f2d0208a355d18cdd375eef9aed">CAN_F0R1_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga75a34023fcd221fc010aaa51065d59dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ecfbfd6f5e129d690f1cb62ee344d78" id="r_ga1ecfbfd6f5e129d690f1cb62ee344d78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ecfbfd6f5e129d690f1cb62ee344d78">CAN_F0R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga75a34023fcd221fc010aaa51065d59dc">CAN_F0R1_FB19_Msk</a></td></tr>
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<tr class="separator:ga1ecfbfd6f5e129d690f1cb62ee344d78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffdb169bfcc229d44b6f2cbd39327458" id="r_gaffdb169bfcc229d44b6f2cbd39327458"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffdb169bfcc229d44b6f2cbd39327458">CAN_F0R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gaffdb169bfcc229d44b6f2cbd39327458"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga574954093b93f62bcfa5cd31e366c2e8" id="r_ga574954093b93f62bcfa5cd31e366c2e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga574954093b93f62bcfa5cd31e366c2e8">CAN_F0R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaffdb169bfcc229d44b6f2cbd39327458">CAN_F0R1_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga574954093b93f62bcfa5cd31e366c2e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a0568e276f245e1f167e673a1f5b92e" id="r_ga3a0568e276f245e1f167e673a1f5b92e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a0568e276f245e1f167e673a1f5b92e">CAN_F0R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga574954093b93f62bcfa5cd31e366c2e8">CAN_F0R1_FB20_Msk</a></td></tr>
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<tr class="separator:ga3a0568e276f245e1f167e673a1f5b92e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9e0fc7eadce21f8851416d9cecbdb22" id="r_gad9e0fc7eadce21f8851416d9cecbdb22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9e0fc7eadce21f8851416d9cecbdb22">CAN_F0R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gad9e0fc7eadce21f8851416d9cecbdb22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41cb6ebc16634fc1a187d536575f47dc" id="r_ga41cb6ebc16634fc1a187d536575f47dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41cb6ebc16634fc1a187d536575f47dc">CAN_F0R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9e0fc7eadce21f8851416d9cecbdb22">CAN_F0R1_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga41cb6ebc16634fc1a187d536575f47dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb71599bae1e35e750524708ac5824f1" id="r_gabb71599bae1e35e750524708ac5824f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb71599bae1e35e750524708ac5824f1">CAN_F0R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga41cb6ebc16634fc1a187d536575f47dc">CAN_F0R1_FB21_Msk</a></td></tr>
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<tr class="separator:gabb71599bae1e35e750524708ac5824f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb02ba4a871b3e83ba9ffddc0aa283da" id="r_gaeb02ba4a871b3e83ba9ffddc0aa283da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb02ba4a871b3e83ba9ffddc0aa283da">CAN_F0R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gaeb02ba4a871b3e83ba9ffddc0aa283da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56eff75e99dbbdd3e4ffe99ae98cd769" id="r_ga56eff75e99dbbdd3e4ffe99ae98cd769"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56eff75e99dbbdd3e4ffe99ae98cd769">CAN_F0R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb02ba4a871b3e83ba9ffddc0aa283da">CAN_F0R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga56eff75e99dbbdd3e4ffe99ae98cd769"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7589f9a62f9f5406934266820a265f3a" id="r_ga7589f9a62f9f5406934266820a265f3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7589f9a62f9f5406934266820a265f3a">CAN_F0R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga56eff75e99dbbdd3e4ffe99ae98cd769">CAN_F0R1_FB22_Msk</a></td></tr>
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<tr class="separator:ga7589f9a62f9f5406934266820a265f3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4fab79aa6648f9590bb08efd5ad74f4" id="r_gaf4fab79aa6648f9590bb08efd5ad74f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4fab79aa6648f9590bb08efd5ad74f4">CAN_F0R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gaf4fab79aa6648f9590bb08efd5ad74f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95d558afd743b97060008ebad600c249" id="r_ga95d558afd743b97060008ebad600c249"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95d558afd743b97060008ebad600c249">CAN_F0R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4fab79aa6648f9590bb08efd5ad74f4">CAN_F0R1_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga95d558afd743b97060008ebad600c249"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a0db2ff3fcf3ecd929d61e548905685" id="r_ga7a0db2ff3fcf3ecd929d61e548905685"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a0db2ff3fcf3ecd929d61e548905685">CAN_F0R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga95d558afd743b97060008ebad600c249">CAN_F0R1_FB23_Msk</a></td></tr>
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<tr class="separator:ga7a0db2ff3fcf3ecd929d61e548905685"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13b36c39c67b88f41d78466dabf1fc68" id="r_ga13b36c39c67b88f41d78466dabf1fc68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13b36c39c67b88f41d78466dabf1fc68">CAN_F0R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga13b36c39c67b88f41d78466dabf1fc68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05249fde15f0ea5a4447a370ba33f344" id="r_ga05249fde15f0ea5a4447a370ba33f344"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05249fde15f0ea5a4447a370ba33f344">CAN_F0R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga13b36c39c67b88f41d78466dabf1fc68">CAN_F0R1_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga05249fde15f0ea5a4447a370ba33f344"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2161321c3b0857a9ca07bc45ac9cd1be" id="r_ga2161321c3b0857a9ca07bc45ac9cd1be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2161321c3b0857a9ca07bc45ac9cd1be">CAN_F0R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga05249fde15f0ea5a4447a370ba33f344">CAN_F0R1_FB24_Msk</a></td></tr>
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<tr class="separator:ga2161321c3b0857a9ca07bc45ac9cd1be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32f93a785540423f910b0fbba693c50c" id="r_ga32f93a785540423f910b0fbba693c50c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32f93a785540423f910b0fbba693c50c">CAN_F0R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga32f93a785540423f910b0fbba693c50c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2e99f0edf1d250d640fda6790e5f8e7" id="r_gae2e99f0edf1d250d640fda6790e5f8e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2e99f0edf1d250d640fda6790e5f8e7">CAN_F0R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga32f93a785540423f910b0fbba693c50c">CAN_F0R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:gae2e99f0edf1d250d640fda6790e5f8e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa85c1d5ccfd6241059822a3aadc1053d" id="r_gaa85c1d5ccfd6241059822a3aadc1053d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa85c1d5ccfd6241059822a3aadc1053d">CAN_F0R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae2e99f0edf1d250d640fda6790e5f8e7">CAN_F0R1_FB25_Msk</a></td></tr>
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<tr class="separator:gaa85c1d5ccfd6241059822a3aadc1053d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd7f7ef5b97b2df3a159a4f5d0c62485" id="r_gafd7f7ef5b97b2df3a159a4f5d0c62485"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd7f7ef5b97b2df3a159a4f5d0c62485">CAN_F0R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:gafd7f7ef5b97b2df3a159a4f5d0c62485"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d00a7d84706b341bf587c7f329ddf88" id="r_ga5d00a7d84706b341bf587c7f329ddf88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d00a7d84706b341bf587c7f329ddf88">CAN_F0R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafd7f7ef5b97b2df3a159a4f5d0c62485">CAN_F0R1_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga5d00a7d84706b341bf587c7f329ddf88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d82ba565f065b4dec733d002c02498b" id="r_ga2d82ba565f065b4dec733d002c02498b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d82ba565f065b4dec733d002c02498b">CAN_F0R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5d00a7d84706b341bf587c7f329ddf88">CAN_F0R1_FB26_Msk</a></td></tr>
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<tr class="separator:ga2d82ba565f065b4dec733d002c02498b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga080266e7390127c1e4efa9bf8a1d3894" id="r_ga080266e7390127c1e4efa9bf8a1d3894"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga080266e7390127c1e4efa9bf8a1d3894">CAN_F0R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga080266e7390127c1e4efa9bf8a1d3894"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf334329b9d4faf3443e12317303b45d6" id="r_gaf334329b9d4faf3443e12317303b45d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf334329b9d4faf3443e12317303b45d6">CAN_F0R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga080266e7390127c1e4efa9bf8a1d3894">CAN_F0R1_FB27_Pos</a>)</td></tr>
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<tr class="separator:gaf334329b9d4faf3443e12317303b45d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga199d63d7155cb5212982d4902e31e70c" id="r_ga199d63d7155cb5212982d4902e31e70c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga199d63d7155cb5212982d4902e31e70c">CAN_F0R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf334329b9d4faf3443e12317303b45d6">CAN_F0R1_FB27_Msk</a></td></tr>
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<tr class="separator:ga199d63d7155cb5212982d4902e31e70c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga828088c9ccc3e6f4a3b16fe6cf527a58" id="r_ga828088c9ccc3e6f4a3b16fe6cf527a58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga828088c9ccc3e6f4a3b16fe6cf527a58">CAN_F0R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga828088c9ccc3e6f4a3b16fe6cf527a58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb63f1377b7f9dfd87c3ef59a5977ee3" id="r_gaeb63f1377b7f9dfd87c3ef59a5977ee3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb63f1377b7f9dfd87c3ef59a5977ee3">CAN_F0R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga828088c9ccc3e6f4a3b16fe6cf527a58">CAN_F0R1_FB28_Pos</a>)</td></tr>
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<tr class="separator:gaeb63f1377b7f9dfd87c3ef59a5977ee3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac82d92ad6fb51b340e8a52da903e1009" id="r_gac82d92ad6fb51b340e8a52da903e1009"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac82d92ad6fb51b340e8a52da903e1009">CAN_F0R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb63f1377b7f9dfd87c3ef59a5977ee3">CAN_F0R1_FB28_Msk</a></td></tr>
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<tr class="separator:gac82d92ad6fb51b340e8a52da903e1009"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b9440886e48f1f2f9c8737120f2458c" id="r_ga4b9440886e48f1f2f9c8737120f2458c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b9440886e48f1f2f9c8737120f2458c">CAN_F0R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga4b9440886e48f1f2f9c8737120f2458c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe7e2b3d7caf0ff01c856374d60f8345" id="r_gabe7e2b3d7caf0ff01c856374d60f8345"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe7e2b3d7caf0ff01c856374d60f8345">CAN_F0R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b9440886e48f1f2f9c8737120f2458c">CAN_F0R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:gabe7e2b3d7caf0ff01c856374d60f8345"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa0a651933135336bc14baa3e0a56ab1" id="r_gaaa0a651933135336bc14baa3e0a56ab1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa0a651933135336bc14baa3e0a56ab1">CAN_F0R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe7e2b3d7caf0ff01c856374d60f8345">CAN_F0R1_FB29_Msk</a></td></tr>
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<tr class="separator:gaaa0a651933135336bc14baa3e0a56ab1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fcf33bc1f1bcea9c87040747e2aa6ad" id="r_ga0fcf33bc1f1bcea9c87040747e2aa6ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fcf33bc1f1bcea9c87040747e2aa6ad">CAN_F0R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga0fcf33bc1f1bcea9c87040747e2aa6ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9766eac13c78b86a31cd64e0d6bea0d" id="r_gaa9766eac13c78b86a31cd64e0d6bea0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9766eac13c78b86a31cd64e0d6bea0d">CAN_F0R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0fcf33bc1f1bcea9c87040747e2aa6ad">CAN_F0R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:gaa9766eac13c78b86a31cd64e0d6bea0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad2a1d8bb83dfcd9f13d25e8ed098b54" id="r_gaad2a1d8bb83dfcd9f13d25e8ed098b54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad2a1d8bb83dfcd9f13d25e8ed098b54">CAN_F0R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9766eac13c78b86a31cd64e0d6bea0d">CAN_F0R1_FB30_Msk</a></td></tr>
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<tr class="separator:gaad2a1d8bb83dfcd9f13d25e8ed098b54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c57e8d1ef05bc7b1c23812904b290f3" id="r_ga0c57e8d1ef05bc7b1c23812904b290f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c57e8d1ef05bc7b1c23812904b290f3">CAN_F0R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga0c57e8d1ef05bc7b1c23812904b290f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e5e5a0416bc721a85eb46e256c35262" id="r_ga5e5e5a0416bc721a85eb46e256c35262"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e5e5a0416bc721a85eb46e256c35262">CAN_F0R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c57e8d1ef05bc7b1c23812904b290f3">CAN_F0R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga5e5e5a0416bc721a85eb46e256c35262"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c9745bc78a65538cbe0fb0d09911554" id="r_ga6c9745bc78a65538cbe0fb0d09911554"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c9745bc78a65538cbe0fb0d09911554">CAN_F0R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e5e5a0416bc721a85eb46e256c35262">CAN_F0R1_FB31_Msk</a></td></tr>
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<tr class="separator:ga6c9745bc78a65538cbe0fb0d09911554"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27eb131cdda754065a82c251b02d26ec" id="r_ga27eb131cdda754065a82c251b02d26ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27eb131cdda754065a82c251b02d26ec">CAN_F1R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga27eb131cdda754065a82c251b02d26ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7196f5a41c5a7692fa31249177a70de5" id="r_ga7196f5a41c5a7692fa31249177a70de5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7196f5a41c5a7692fa31249177a70de5">CAN_F1R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27eb131cdda754065a82c251b02d26ec">CAN_F1R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga7196f5a41c5a7692fa31249177a70de5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf74bbd84aff2eb3891f6f6d0c418793c" id="r_gaf74bbd84aff2eb3891f6f6d0c418793c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf74bbd84aff2eb3891f6f6d0c418793c">CAN_F1R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7196f5a41c5a7692fa31249177a70de5">CAN_F1R1_FB0_Msk</a></td></tr>
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<tr class="separator:gaf74bbd84aff2eb3891f6f6d0c418793c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1aecffb61aa34f1bfd36d4230fbf1e87" id="r_ga1aecffb61aa34f1bfd36d4230fbf1e87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1aecffb61aa34f1bfd36d4230fbf1e87">CAN_F1R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga1aecffb61aa34f1bfd36d4230fbf1e87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa957dafcd250c1c36d38a0da7a94d0b6" id="r_gaa957dafcd250c1c36d38a0da7a94d0b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa957dafcd250c1c36d38a0da7a94d0b6">CAN_F1R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1aecffb61aa34f1bfd36d4230fbf1e87">CAN_F1R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:gaa957dafcd250c1c36d38a0da7a94d0b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2cb33663f4220e5a0d416cbddcec193" id="r_gaa2cb33663f4220e5a0d416cbddcec193"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2cb33663f4220e5a0d416cbddcec193">CAN_F1R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa957dafcd250c1c36d38a0da7a94d0b6">CAN_F1R1_FB1_Msk</a></td></tr>
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<tr class="separator:gaa2cb33663f4220e5a0d416cbddcec193"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e4d64e1f9cacf34eb857db24e2aaed7" id="r_ga9e4d64e1f9cacf34eb857db24e2aaed7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e4d64e1f9cacf34eb857db24e2aaed7">CAN_F1R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga9e4d64e1f9cacf34eb857db24e2aaed7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab76348b5edccc3dff80131b8c8c66d91" id="r_gab76348b5edccc3dff80131b8c8c66d91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab76348b5edccc3dff80131b8c8c66d91">CAN_F1R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e4d64e1f9cacf34eb857db24e2aaed7">CAN_F1R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:gab76348b5edccc3dff80131b8c8c66d91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86d75200e9ead1afbe88add086ac4bb4" id="r_ga86d75200e9ead1afbe88add086ac4bb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86d75200e9ead1afbe88add086ac4bb4">CAN_F1R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab76348b5edccc3dff80131b8c8c66d91">CAN_F1R1_FB2_Msk</a></td></tr>
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<tr class="separator:ga86d75200e9ead1afbe88add086ac4bb4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70b163a4031c8c84fd3b1691a0310ffa" id="r_ga70b163a4031c8c84fd3b1691a0310ffa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70b163a4031c8c84fd3b1691a0310ffa">CAN_F1R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga70b163a4031c8c84fd3b1691a0310ffa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga489dfc442d364861f5f985aae7651179" id="r_ga489dfc442d364861f5f985aae7651179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga489dfc442d364861f5f985aae7651179">CAN_F1R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70b163a4031c8c84fd3b1691a0310ffa">CAN_F1R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga489dfc442d364861f5f985aae7651179"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4dbe3b567fca94f5d5e4c877e0383d4" id="r_gaa4dbe3b567fca94f5d5e4c877e0383d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4dbe3b567fca94f5d5e4c877e0383d4">CAN_F1R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga489dfc442d364861f5f985aae7651179">CAN_F1R1_FB3_Msk</a></td></tr>
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<tr class="separator:gaa4dbe3b567fca94f5d5e4c877e0383d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadfea6ec572e4c78a63141351020434f3" id="r_gadfea6ec572e4c78a63141351020434f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfea6ec572e4c78a63141351020434f3">CAN_F1R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gadfea6ec572e4c78a63141351020434f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48fba4b8013f5aa76ca9008eb1942423" id="r_ga48fba4b8013f5aa76ca9008eb1942423"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48fba4b8013f5aa76ca9008eb1942423">CAN_F1R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfea6ec572e4c78a63141351020434f3">CAN_F1R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga48fba4b8013f5aa76ca9008eb1942423"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab74c1e5fba0af06b783289d56a8d743a" id="r_gab74c1e5fba0af06b783289d56a8d743a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab74c1e5fba0af06b783289d56a8d743a">CAN_F1R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga48fba4b8013f5aa76ca9008eb1942423">CAN_F1R1_FB4_Msk</a></td></tr>
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<tr class="separator:gab74c1e5fba0af06b783289d56a8d743a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07413947413c933237227a8f37ac6728" id="r_ga07413947413c933237227a8f37ac6728"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07413947413c933237227a8f37ac6728">CAN_F1R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga07413947413c933237227a8f37ac6728"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13b02c35ea2380f0f839784fc618090a" id="r_ga13b02c35ea2380f0f839784fc618090a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13b02c35ea2380f0f839784fc618090a">CAN_F1R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07413947413c933237227a8f37ac6728">CAN_F1R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga13b02c35ea2380f0f839784fc618090a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga163dda15630c6f057bac420a8cb393d8" id="r_ga163dda15630c6f057bac420a8cb393d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga163dda15630c6f057bac420a8cb393d8">CAN_F1R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga13b02c35ea2380f0f839784fc618090a">CAN_F1R1_FB5_Msk</a></td></tr>
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<tr class="separator:ga163dda15630c6f057bac420a8cb393d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0428081f736b6a2888514dccd2af1f28" id="r_ga0428081f736b6a2888514dccd2af1f28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0428081f736b6a2888514dccd2af1f28">CAN_F1R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga0428081f736b6a2888514dccd2af1f28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbe821726bd0ab42de7eb6ba9b497e56" id="r_gacbe821726bd0ab42de7eb6ba9b497e56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbe821726bd0ab42de7eb6ba9b497e56">CAN_F1R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0428081f736b6a2888514dccd2af1f28">CAN_F1R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:gacbe821726bd0ab42de7eb6ba9b497e56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd27041e24d500c940abed9aaa53910d" id="r_gadd27041e24d500c940abed9aaa53910d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd27041e24d500c940abed9aaa53910d">CAN_F1R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacbe821726bd0ab42de7eb6ba9b497e56">CAN_F1R1_FB6_Msk</a></td></tr>
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<tr class="separator:gadd27041e24d500c940abed9aaa53910d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f7fad2e9157b6680041f1a4ff200af4" id="r_ga5f7fad2e9157b6680041f1a4ff200af4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f7fad2e9157b6680041f1a4ff200af4">CAN_F1R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga5f7fad2e9157b6680041f1a4ff200af4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga655b773dfa0dfe1e62cd8560a8dcb150" id="r_ga655b773dfa0dfe1e62cd8560a8dcb150"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga655b773dfa0dfe1e62cd8560a8dcb150">CAN_F1R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f7fad2e9157b6680041f1a4ff200af4">CAN_F1R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga655b773dfa0dfe1e62cd8560a8dcb150"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadfffc15f309b85cc3abd7439ea4b8c6" id="r_gaadfffc15f309b85cc3abd7439ea4b8c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadfffc15f309b85cc3abd7439ea4b8c6">CAN_F1R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga655b773dfa0dfe1e62cd8560a8dcb150">CAN_F1R1_FB7_Msk</a></td></tr>
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<tr class="separator:gaadfffc15f309b85cc3abd7439ea4b8c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72753a76f8413d0a00ace38793d7ec9a" id="r_ga72753a76f8413d0a00ace38793d7ec9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72753a76f8413d0a00ace38793d7ec9a">CAN_F1R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga72753a76f8413d0a00ace38793d7ec9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1dd516a1cf52c63b64b028d7528da7b" id="r_gaa1dd516a1cf52c63b64b028d7528da7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1dd516a1cf52c63b64b028d7528da7b">CAN_F1R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga72753a76f8413d0a00ace38793d7ec9a">CAN_F1R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:gaa1dd516a1cf52c63b64b028d7528da7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf2588b13464de27f12768d33a75d2ba" id="r_gadf2588b13464de27f12768d33a75d2ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf2588b13464de27f12768d33a75d2ba">CAN_F1R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1dd516a1cf52c63b64b028d7528da7b">CAN_F1R1_FB8_Msk</a></td></tr>
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<tr class="separator:gadf2588b13464de27f12768d33a75d2ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80f45f8de5ab075f633d21443c8b2226" id="r_ga80f45f8de5ab075f633d21443c8b2226"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80f45f8de5ab075f633d21443c8b2226">CAN_F1R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga80f45f8de5ab075f633d21443c8b2226"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4645154d1f265dee267626ae43e35eae" id="r_ga4645154d1f265dee267626ae43e35eae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4645154d1f265dee267626ae43e35eae">CAN_F1R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80f45f8de5ab075f633d21443c8b2226">CAN_F1R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga4645154d1f265dee267626ae43e35eae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga979839e5c63f94eb294a09b74f5c09bf" id="r_ga979839e5c63f94eb294a09b74f5c09bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga979839e5c63f94eb294a09b74f5c09bf">CAN_F1R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4645154d1f265dee267626ae43e35eae">CAN_F1R1_FB9_Msk</a></td></tr>
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<tr class="separator:ga979839e5c63f94eb294a09b74f5c09bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf483657f1c8087691588ad2b4e8aa007" id="r_gaf483657f1c8087691588ad2b4e8aa007"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf483657f1c8087691588ad2b4e8aa007">CAN_F1R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaf483657f1c8087691588ad2b4e8aa007"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0dbe75098babb0ad9de21a966115c4cb" id="r_ga0dbe75098babb0ad9de21a966115c4cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dbe75098babb0ad9de21a966115c4cb">CAN_F1R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf483657f1c8087691588ad2b4e8aa007">CAN_F1R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga0dbe75098babb0ad9de21a966115c4cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f049fa606d557a8a468747c6d285357" id="r_ga7f049fa606d557a8a468747c6d285357"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f049fa606d557a8a468747c6d285357">CAN_F1R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dbe75098babb0ad9de21a966115c4cb">CAN_F1R1_FB10_Msk</a></td></tr>
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<tr class="separator:ga7f049fa606d557a8a468747c6d285357"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6ebfb27d5d594fdb472d31751a25092" id="r_gad6ebfb27d5d594fdb472d31751a25092"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6ebfb27d5d594fdb472d31751a25092">CAN_F1R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gad6ebfb27d5d594fdb472d31751a25092"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b5ea83ec6fdbcc28d0f2c907276bec9" id="r_ga5b5ea83ec6fdbcc28d0f2c907276bec9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b5ea83ec6fdbcc28d0f2c907276bec9">CAN_F1R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad6ebfb27d5d594fdb472d31751a25092">CAN_F1R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga5b5ea83ec6fdbcc28d0f2c907276bec9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43409866ee9e6ea1712f50679a4bb212" id="r_ga43409866ee9e6ea1712f50679a4bb212"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43409866ee9e6ea1712f50679a4bb212">CAN_F1R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b5ea83ec6fdbcc28d0f2c907276bec9">CAN_F1R1_FB11_Msk</a></td></tr>
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<tr class="separator:ga43409866ee9e6ea1712f50679a4bb212"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f87b433c7752b209f54f04ecb3f2e40" id="r_ga8f87b433c7752b209f54f04ecb3f2e40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f87b433c7752b209f54f04ecb3f2e40">CAN_F1R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga8f87b433c7752b209f54f04ecb3f2e40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd728a049ed7528b585dd56bd4e1d2cd" id="r_gadd728a049ed7528b585dd56bd4e1d2cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd728a049ed7528b585dd56bd4e1d2cd">CAN_F1R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f87b433c7752b209f54f04ecb3f2e40">CAN_F1R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:gadd728a049ed7528b585dd56bd4e1d2cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f86fb2f2080f513d8392d389cdaa1fd" id="r_ga3f86fb2f2080f513d8392d389cdaa1fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f86fb2f2080f513d8392d389cdaa1fd">CAN_F1R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadd728a049ed7528b585dd56bd4e1d2cd">CAN_F1R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga3f86fb2f2080f513d8392d389cdaa1fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcf14a236c390185aa76b3223e2ab573" id="r_gadcf14a236c390185aa76b3223e2ab573"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcf14a236c390185aa76b3223e2ab573">CAN_F1R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gadcf14a236c390185aa76b3223e2ab573"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf67d90e15499f16cb9903c75ffa2cdd" id="r_gabf67d90e15499f16cb9903c75ffa2cdd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf67d90e15499f16cb9903c75ffa2cdd">CAN_F1R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadcf14a236c390185aa76b3223e2ab573">CAN_F1R1_FB13_Pos</a>)</td></tr>
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<tr class="memitem:ga2c1b7aeeb196a6564b2b3f049590520e" id="r_ga2c1b7aeeb196a6564b2b3f049590520e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c1b7aeeb196a6564b2b3f049590520e">CAN_F1R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabf67d90e15499f16cb9903c75ffa2cdd">CAN_F1R1_FB13_Msk</a></td></tr>
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<tr class="memitem:ga166ab6b1478e95f89a920b63c1fe83b3" id="r_ga166ab6b1478e95f89a920b63c1fe83b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga166ab6b1478e95f89a920b63c1fe83b3">CAN_F1R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga166ab6b1478e95f89a920b63c1fe83b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5dd92e83b650c454a58a4e5bb0a2bae0" id="r_ga5dd92e83b650c454a58a4e5bb0a2bae0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5dd92e83b650c454a58a4e5bb0a2bae0">CAN_F1R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga166ab6b1478e95f89a920b63c1fe83b3">CAN_F1R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:ga5dd92e83b650c454a58a4e5bb0a2bae0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45bad406315318f9cecb0c783ac7218d" id="r_ga45bad406315318f9cecb0c783ac7218d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45bad406315318f9cecb0c783ac7218d">CAN_F1R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5dd92e83b650c454a58a4e5bb0a2bae0">CAN_F1R1_FB14_Msk</a></td></tr>
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<tr class="separator:ga45bad406315318f9cecb0c783ac7218d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8dc185faf155706578f28896e413294" id="r_gae8dc185faf155706578f28896e413294"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8dc185faf155706578f28896e413294">CAN_F1R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gae8dc185faf155706578f28896e413294"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga303d03c806b2cd4ae51703db085ff55b" id="r_ga303d03c806b2cd4ae51703db085ff55b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga303d03c806b2cd4ae51703db085ff55b">CAN_F1R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae8dc185faf155706578f28896e413294">CAN_F1R1_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga303d03c806b2cd4ae51703db085ff55b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b105deaf668c0e04950be0de975bcde" id="r_ga9b105deaf668c0e04950be0de975bcde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b105deaf668c0e04950be0de975bcde">CAN_F1R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga303d03c806b2cd4ae51703db085ff55b">CAN_F1R1_FB15_Msk</a></td></tr>
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<tr class="separator:ga9b105deaf668c0e04950be0de975bcde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e9dd89c5bb2dbfb38154cf3d0f52f19" id="r_ga9e9dd89c5bb2dbfb38154cf3d0f52f19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e9dd89c5bb2dbfb38154cf3d0f52f19">CAN_F1R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga9e9dd89c5bb2dbfb38154cf3d0f52f19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd648d6b54d04ac636e7536a08d11ebb" id="r_gabd648d6b54d04ac636e7536a08d11ebb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd648d6b54d04ac636e7536a08d11ebb">CAN_F1R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e9dd89c5bb2dbfb38154cf3d0f52f19">CAN_F1R1_FB16_Pos</a>)</td></tr>
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<tr class="separator:gabd648d6b54d04ac636e7536a08d11ebb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84fabcf9736d7ef78587ff63cb6b1373" id="r_ga84fabcf9736d7ef78587ff63cb6b1373"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84fabcf9736d7ef78587ff63cb6b1373">CAN_F1R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd648d6b54d04ac636e7536a08d11ebb">CAN_F1R1_FB16_Msk</a></td></tr>
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<tr class="separator:ga84fabcf9736d7ef78587ff63cb6b1373"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9816f741200a82b429a0ea6e18d4f481" id="r_ga9816f741200a82b429a0ea6e18d4f481"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9816f741200a82b429a0ea6e18d4f481">CAN_F1R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga9816f741200a82b429a0ea6e18d4f481"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48d839533fbd0dcc34aee11644d5f849" id="r_ga48d839533fbd0dcc34aee11644d5f849"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48d839533fbd0dcc34aee11644d5f849">CAN_F1R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9816f741200a82b429a0ea6e18d4f481">CAN_F1R1_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga48d839533fbd0dcc34aee11644d5f849"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga966d41aca2269fd8cb6830dbbd176140" id="r_ga966d41aca2269fd8cb6830dbbd176140"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga966d41aca2269fd8cb6830dbbd176140">CAN_F1R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga48d839533fbd0dcc34aee11644d5f849">CAN_F1R1_FB17_Msk</a></td></tr>
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<tr class="separator:ga966d41aca2269fd8cb6830dbbd176140"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae67138d3787bf67035e1eb1d7420b999" id="r_gae67138d3787bf67035e1eb1d7420b999"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae67138d3787bf67035e1eb1d7420b999">CAN_F1R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:gae67138d3787bf67035e1eb1d7420b999"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab67914799f407244afdbf1ade349dbf3" id="r_gab67914799f407244afdbf1ade349dbf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab67914799f407244afdbf1ade349dbf3">CAN_F1R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae67138d3787bf67035e1eb1d7420b999">CAN_F1R1_FB18_Pos</a>)</td></tr>
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<tr class="separator:gab67914799f407244afdbf1ade349dbf3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a53cd0cf8722dc63b8ff26d4b0fa0f7" id="r_ga9a53cd0cf8722dc63b8ff26d4b0fa0f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a53cd0cf8722dc63b8ff26d4b0fa0f7">CAN_F1R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab67914799f407244afdbf1ade349dbf3">CAN_F1R1_FB18_Msk</a></td></tr>
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<tr class="separator:ga9a53cd0cf8722dc63b8ff26d4b0fa0f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac725ea9b9e3b26ac347f66ccc4ddfae4" id="r_gac725ea9b9e3b26ac347f66ccc4ddfae4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac725ea9b9e3b26ac347f66ccc4ddfae4">CAN_F1R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:gac725ea9b9e3b26ac347f66ccc4ddfae4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e0c47dda83f3ce3f3e5b18f3fb93b35" id="r_ga7e0c47dda83f3ce3f3e5b18f3fb93b35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e0c47dda83f3ce3f3e5b18f3fb93b35">CAN_F1R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac725ea9b9e3b26ac347f66ccc4ddfae4">CAN_F1R1_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga7e0c47dda83f3ce3f3e5b18f3fb93b35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3fb64b2b59f73045b3ead12ab1211b4b" id="r_ga3fb64b2b59f73045b3ead12ab1211b4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3fb64b2b59f73045b3ead12ab1211b4b">CAN_F1R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e0c47dda83f3ce3f3e5b18f3fb93b35">CAN_F1R1_FB19_Msk</a></td></tr>
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<tr class="separator:ga3fb64b2b59f73045b3ead12ab1211b4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeba0bf91f16395564def3f873084dc0b" id="r_gaeba0bf91f16395564def3f873084dc0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeba0bf91f16395564def3f873084dc0b">CAN_F1R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gaeba0bf91f16395564def3f873084dc0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga122f1435ff77893cee8ec0d39fbfb178" id="r_ga122f1435ff77893cee8ec0d39fbfb178"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga122f1435ff77893cee8ec0d39fbfb178">CAN_F1R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeba0bf91f16395564def3f873084dc0b">CAN_F1R1_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga122f1435ff77893cee8ec0d39fbfb178"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad558faeeeaf748bdface31d4bd3ed5b6" id="r_gad558faeeeaf748bdface31d4bd3ed5b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad558faeeeaf748bdface31d4bd3ed5b6">CAN_F1R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga122f1435ff77893cee8ec0d39fbfb178">CAN_F1R1_FB20_Msk</a></td></tr>
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<tr class="separator:gad558faeeeaf748bdface31d4bd3ed5b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16a40175f3f3d5fdb28dc172aa7a1595" id="r_ga16a40175f3f3d5fdb28dc172aa7a1595"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16a40175f3f3d5fdb28dc172aa7a1595">CAN_F1R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga16a40175f3f3d5fdb28dc172aa7a1595"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7164f10425d3caf734b284f3bc3b5449" id="r_ga7164f10425d3caf734b284f3bc3b5449"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7164f10425d3caf734b284f3bc3b5449">CAN_F1R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16a40175f3f3d5fdb28dc172aa7a1595">CAN_F1R1_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga7164f10425d3caf734b284f3bc3b5449"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab16bc53f206b1f318e5fe8c248294fec" id="r_gab16bc53f206b1f318e5fe8c248294fec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab16bc53f206b1f318e5fe8c248294fec">CAN_F1R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7164f10425d3caf734b284f3bc3b5449">CAN_F1R1_FB21_Msk</a></td></tr>
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<tr class="separator:gab16bc53f206b1f318e5fe8c248294fec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga069b7dc2e0e3e0ab6445a2bf2bfc3bed" id="r_ga069b7dc2e0e3e0ab6445a2bf2bfc3bed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga069b7dc2e0e3e0ab6445a2bf2bfc3bed">CAN_F1R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga069b7dc2e0e3e0ab6445a2bf2bfc3bed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ddbed5a2b9531b528d32857123af10a" id="r_ga3ddbed5a2b9531b528d32857123af10a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ddbed5a2b9531b528d32857123af10a">CAN_F1R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga069b7dc2e0e3e0ab6445a2bf2bfc3bed">CAN_F1R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga3ddbed5a2b9531b528d32857123af10a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42841c82744146dc70e8e679b5904e02" id="r_ga42841c82744146dc70e8e679b5904e02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42841c82744146dc70e8e679b5904e02">CAN_F1R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ddbed5a2b9531b528d32857123af10a">CAN_F1R1_FB22_Msk</a></td></tr>
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<tr class="separator:ga42841c82744146dc70e8e679b5904e02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1be33c0c1d5b547f65b90e763ac7bbd" id="r_gaf1be33c0c1d5b547f65b90e763ac7bbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1be33c0c1d5b547f65b90e763ac7bbd">CAN_F1R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gaf1be33c0c1d5b547f65b90e763ac7bbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccc01c86ecce551ede43bfeafbbbb384" id="r_gaccc01c86ecce551ede43bfeafbbbb384"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccc01c86ecce551ede43bfeafbbbb384">CAN_F1R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1be33c0c1d5b547f65b90e763ac7bbd">CAN_F1R1_FB23_Pos</a>)</td></tr>
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<tr class="separator:gaccc01c86ecce551ede43bfeafbbbb384"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1f961b642e42faaaf495c9ec099c128" id="r_gad1f961b642e42faaaf495c9ec099c128"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1f961b642e42faaaf495c9ec099c128">CAN_F1R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaccc01c86ecce551ede43bfeafbbbb384">CAN_F1R1_FB23_Msk</a></td></tr>
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<tr class="separator:gad1f961b642e42faaaf495c9ec099c128"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cf527d0f7d4dfa543c7961d56909885" id="r_ga2cf527d0f7d4dfa543c7961d56909885"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cf527d0f7d4dfa543c7961d56909885">CAN_F1R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga2cf527d0f7d4dfa543c7961d56909885"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9660622aa2fe3253f7b29e7591462002" id="r_ga9660622aa2fe3253f7b29e7591462002"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9660622aa2fe3253f7b29e7591462002">CAN_F1R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cf527d0f7d4dfa543c7961d56909885">CAN_F1R1_FB24_Pos</a>)</td></tr>
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<tr class="memitem:ga96670686c71a15631ec2f772973dd7d5" id="r_ga96670686c71a15631ec2f772973dd7d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96670686c71a15631ec2f772973dd7d5">CAN_F1R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9660622aa2fe3253f7b29e7591462002">CAN_F1R1_FB24_Msk</a></td></tr>
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<tr class="separator:ga96670686c71a15631ec2f772973dd7d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab6c5577c558a7f155db47732b868711c" id="r_gab6c5577c558a7f155db47732b868711c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6c5577c558a7f155db47732b868711c">CAN_F1R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gab6c5577c558a7f155db47732b868711c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0f80f8443876e5a992b6b320f19d537" id="r_gad0f80f8443876e5a992b6b320f19d537"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0f80f8443876e5a992b6b320f19d537">CAN_F1R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab6c5577c558a7f155db47732b868711c">CAN_F1R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:gad0f80f8443876e5a992b6b320f19d537"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2d8b1a30c3a6ae1f75369abc445ab7d" id="r_gaa2d8b1a30c3a6ae1f75369abc445ab7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2d8b1a30c3a6ae1f75369abc445ab7d">CAN_F1R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad0f80f8443876e5a992b6b320f19d537">CAN_F1R1_FB25_Msk</a></td></tr>
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<tr class="separator:gaa2d8b1a30c3a6ae1f75369abc445ab7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27cc17673e3a875235664981d3ca221a" id="r_ga27cc17673e3a875235664981d3ca221a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27cc17673e3a875235664981d3ca221a">CAN_F1R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga27cc17673e3a875235664981d3ca221a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad90d82d2f8485e7e9a530992ac4a84e0" id="r_gad90d82d2f8485e7e9a530992ac4a84e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad90d82d2f8485e7e9a530992ac4a84e0">CAN_F1R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27cc17673e3a875235664981d3ca221a">CAN_F1R1_FB26_Pos</a>)</td></tr>
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<tr class="separator:gad90d82d2f8485e7e9a530992ac4a84e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf027c958889ab93acfb1b86988269874" id="r_gaf027c958889ab93acfb1b86988269874"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf027c958889ab93acfb1b86988269874">CAN_F1R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad90d82d2f8485e7e9a530992ac4a84e0">CAN_F1R1_FB26_Msk</a></td></tr>
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<tr class="separator:gaf027c958889ab93acfb1b86988269874"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2db09a50ddde24f79862191ca42bc451" id="r_ga2db09a50ddde24f79862191ca42bc451"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2db09a50ddde24f79862191ca42bc451">CAN_F1R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga2db09a50ddde24f79862191ca42bc451"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1dd73fe9a0c9c29fcb103e241ed3c4af" id="r_ga1dd73fe9a0c9c29fcb103e241ed3c4af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1dd73fe9a0c9c29fcb103e241ed3c4af">CAN_F1R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db09a50ddde24f79862191ca42bc451">CAN_F1R1_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga1dd73fe9a0c9c29fcb103e241ed3c4af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32400e283bc0037da21f0c913bb860b6" id="r_ga32400e283bc0037da21f0c913bb860b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32400e283bc0037da21f0c913bb860b6">CAN_F1R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1dd73fe9a0c9c29fcb103e241ed3c4af">CAN_F1R1_FB27_Msk</a></td></tr>
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<tr class="separator:ga32400e283bc0037da21f0c913bb860b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e0fe7f80eac137fc59498aaf1a4cda5" id="r_ga1e0fe7f80eac137fc59498aaf1a4cda5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e0fe7f80eac137fc59498aaf1a4cda5">CAN_F1R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga1e0fe7f80eac137fc59498aaf1a4cda5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1bc410d11b14bfa426de7b7977bee14" id="r_gae1bc410d11b14bfa426de7b7977bee14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1bc410d11b14bfa426de7b7977bee14">CAN_F1R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e0fe7f80eac137fc59498aaf1a4cda5">CAN_F1R1_FB28_Pos</a>)</td></tr>
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<tr class="separator:gae1bc410d11b14bfa426de7b7977bee14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb0467d664f27b3ca8ef4ad220593c46" id="r_gadb0467d664f27b3ca8ef4ad220593c46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb0467d664f27b3ca8ef4ad220593c46">CAN_F1R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae1bc410d11b14bfa426de7b7977bee14">CAN_F1R1_FB28_Msk</a></td></tr>
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<tr class="separator:gadb0467d664f27b3ca8ef4ad220593c46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa51f300d424e7cd192b6af1f81cc2019" id="r_gaa51f300d424e7cd192b6af1f81cc2019"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa51f300d424e7cd192b6af1f81cc2019">CAN_F1R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:gaa51f300d424e7cd192b6af1f81cc2019"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac48a223c7f7282dc22db7c2e0d557f35" id="r_gac48a223c7f7282dc22db7c2e0d557f35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac48a223c7f7282dc22db7c2e0d557f35">CAN_F1R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa51f300d424e7cd192b6af1f81cc2019">CAN_F1R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:gac48a223c7f7282dc22db7c2e0d557f35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c3e3090ab67a54830be208a628efd8f" id="r_ga1c3e3090ab67a54830be208a628efd8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c3e3090ab67a54830be208a628efd8f">CAN_F1R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac48a223c7f7282dc22db7c2e0d557f35">CAN_F1R1_FB29_Msk</a></td></tr>
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<tr class="separator:ga1c3e3090ab67a54830be208a628efd8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20dd3f33af971def89d8e3ca8abd8f63" id="r_ga20dd3f33af971def89d8e3ca8abd8f63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20dd3f33af971def89d8e3ca8abd8f63">CAN_F1R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga20dd3f33af971def89d8e3ca8abd8f63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf45ba201e41f2fd71cda39c7010f65e0" id="r_gaf45ba201e41f2fd71cda39c7010f65e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf45ba201e41f2fd71cda39c7010f65e0">CAN_F1R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20dd3f33af971def89d8e3ca8abd8f63">CAN_F1R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:gaf45ba201e41f2fd71cda39c7010f65e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85034e026be1af5e45e5d15537449e6d" id="r_ga85034e026be1af5e45e5d15537449e6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85034e026be1af5e45e5d15537449e6d">CAN_F1R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf45ba201e41f2fd71cda39c7010f65e0">CAN_F1R1_FB30_Msk</a></td></tr>
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<tr class="separator:ga85034e026be1af5e45e5d15537449e6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e42f6407392d9744b324a3b9bca2ab8" id="r_ga9e42f6407392d9744b324a3b9bca2ab8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e42f6407392d9744b324a3b9bca2ab8">CAN_F1R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga9e42f6407392d9744b324a3b9bca2ab8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1345bf0889997c6316180e9754c3e18" id="r_gac1345bf0889997c6316180e9754c3e18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1345bf0889997c6316180e9754c3e18">CAN_F1R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e42f6407392d9744b324a3b9bca2ab8">CAN_F1R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:gac1345bf0889997c6316180e9754c3e18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ddfc083d58a190057fb67e4eb31136b" id="r_ga6ddfc083d58a190057fb67e4eb31136b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ddfc083d58a190057fb67e4eb31136b">CAN_F1R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac1345bf0889997c6316180e9754c3e18">CAN_F1R1_FB31_Msk</a></td></tr>
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<tr class="separator:ga6ddfc083d58a190057fb67e4eb31136b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d22e35b14dc0fd47606ec3e9f5433f0" id="r_ga6d22e35b14dc0fd47606ec3e9f5433f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d22e35b14dc0fd47606ec3e9f5433f0">CAN_F2R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga6d22e35b14dc0fd47606ec3e9f5433f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac32a7356281dd4bfe7825df1f7cf2cb9" id="r_gac32a7356281dd4bfe7825df1f7cf2cb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac32a7356281dd4bfe7825df1f7cf2cb9">CAN_F2R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d22e35b14dc0fd47606ec3e9f5433f0">CAN_F2R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:gac32a7356281dd4bfe7825df1f7cf2cb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf17f4c3e553020ee893415796bd29d84" id="r_gaf17f4c3e553020ee893415796bd29d84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf17f4c3e553020ee893415796bd29d84">CAN_F2R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac32a7356281dd4bfe7825df1f7cf2cb9">CAN_F2R1_FB0_Msk</a></td></tr>
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<tr class="separator:gaf17f4c3e553020ee893415796bd29d84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bde9b889c0e03d67ce1432aecbd75ce" id="r_ga0bde9b889c0e03d67ce1432aecbd75ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bde9b889c0e03d67ce1432aecbd75ce">CAN_F2R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga0bde9b889c0e03d67ce1432aecbd75ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63a45584a55de290532b6835fadf480a" id="r_ga63a45584a55de290532b6835fadf480a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63a45584a55de290532b6835fadf480a">CAN_F2R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bde9b889c0e03d67ce1432aecbd75ce">CAN_F2R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga63a45584a55de290532b6835fadf480a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae97de172023462e5f40d4b420209809b" id="r_gae97de172023462e5f40d4b420209809b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae97de172023462e5f40d4b420209809b">CAN_F2R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63a45584a55de290532b6835fadf480a">CAN_F2R1_FB1_Msk</a></td></tr>
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<tr class="separator:gae97de172023462e5f40d4b420209809b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacccd928df24722f7ac8cc22de452ab4b" id="r_gacccd928df24722f7ac8cc22de452ab4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacccd928df24722f7ac8cc22de452ab4b">CAN_F2R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gacccd928df24722f7ac8cc22de452ab4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42aa2e179dd31d2ef7373acb814223f2" id="r_ga42aa2e179dd31d2ef7373acb814223f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42aa2e179dd31d2ef7373acb814223f2">CAN_F2R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacccd928df24722f7ac8cc22de452ab4b">CAN_F2R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga42aa2e179dd31d2ef7373acb814223f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23008ac61893eb6a65ab9041c53a84ee" id="r_ga23008ac61893eb6a65ab9041c53a84ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23008ac61893eb6a65ab9041c53a84ee">CAN_F2R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga42aa2e179dd31d2ef7373acb814223f2">CAN_F2R1_FB2_Msk</a></td></tr>
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<tr class="separator:ga23008ac61893eb6a65ab9041c53a84ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca191ad3d0d9a8452f6dd9e8465695e5" id="r_gaca191ad3d0d9a8452f6dd9e8465695e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca191ad3d0d9a8452f6dd9e8465695e5">CAN_F2R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="memitem:gafc7f6fc0a5744d9f9246ae814dde3a00" id="r_gafc7f6fc0a5744d9f9246ae814dde3a00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc7f6fc0a5744d9f9246ae814dde3a00">CAN_F2R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaca191ad3d0d9a8452f6dd9e8465695e5">CAN_F2R1_FB3_Pos</a>)</td></tr>
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<tr class="memitem:gad559580b386d0c621a6bf7292c706e36" id="r_gad559580b386d0c621a6bf7292c706e36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad559580b386d0c621a6bf7292c706e36">CAN_F2R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafc7f6fc0a5744d9f9246ae814dde3a00">CAN_F2R1_FB3_Msk</a></td></tr>
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<tr class="memitem:gadc3a2fcc279f4d100b4bf0a3e56c027d" id="r_gadc3a2fcc279f4d100b4bf0a3e56c027d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc3a2fcc279f4d100b4bf0a3e56c027d">CAN_F2R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga7555733c5e81d91c22ef16a2954e58a0" id="r_ga7555733c5e81d91c22ef16a2954e58a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7555733c5e81d91c22ef16a2954e58a0">CAN_F2R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadc3a2fcc279f4d100b4bf0a3e56c027d">CAN_F2R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga7555733c5e81d91c22ef16a2954e58a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e52ca421788d68f3edb9a52434374dd" id="r_ga0e52ca421788d68f3edb9a52434374dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e52ca421788d68f3edb9a52434374dd">CAN_F2R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7555733c5e81d91c22ef16a2954e58a0">CAN_F2R1_FB4_Msk</a></td></tr>
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<tr class="separator:ga0e52ca421788d68f3edb9a52434374dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2706c0511eea92c7c23717696e2039ef" id="r_ga2706c0511eea92c7c23717696e2039ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2706c0511eea92c7c23717696e2039ef">CAN_F2R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga2706c0511eea92c7c23717696e2039ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3302502cfe80c87773630dbb3fe8eab1" id="r_ga3302502cfe80c87773630dbb3fe8eab1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3302502cfe80c87773630dbb3fe8eab1">CAN_F2R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2706c0511eea92c7c23717696e2039ef">CAN_F2R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga3302502cfe80c87773630dbb3fe8eab1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96a97a9711a0a53a7ee18907e95d8887" id="r_ga96a97a9711a0a53a7ee18907e95d8887"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96a97a9711a0a53a7ee18907e95d8887">CAN_F2R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3302502cfe80c87773630dbb3fe8eab1">CAN_F2R1_FB5_Msk</a></td></tr>
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<tr class="separator:ga96a97a9711a0a53a7ee18907e95d8887"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26f556ca64f9a621435b46e87266ceed" id="r_ga26f556ca64f9a621435b46e87266ceed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26f556ca64f9a621435b46e87266ceed">CAN_F2R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga26f556ca64f9a621435b46e87266ceed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c22e704c9d4404892df4086290e68ec" id="r_ga1c22e704c9d4404892df4086290e68ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c22e704c9d4404892df4086290e68ec">CAN_F2R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga26f556ca64f9a621435b46e87266ceed">CAN_F2R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga1c22e704c9d4404892df4086290e68ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f73f1bd0d3246f27d7a91a620fb3cc7" id="r_ga6f73f1bd0d3246f27d7a91a620fb3cc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f73f1bd0d3246f27d7a91a620fb3cc7">CAN_F2R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c22e704c9d4404892df4086290e68ec">CAN_F2R1_FB6_Msk</a></td></tr>
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<tr class="separator:ga6f73f1bd0d3246f27d7a91a620fb3cc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga417d9fb1cd03584958223984f973ae45" id="r_ga417d9fb1cd03584958223984f973ae45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga417d9fb1cd03584958223984f973ae45">CAN_F2R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga417d9fb1cd03584958223984f973ae45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga569ec796b80a5c48de939b628a2368d8" id="r_ga569ec796b80a5c48de939b628a2368d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga569ec796b80a5c48de939b628a2368d8">CAN_F2R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga417d9fb1cd03584958223984f973ae45">CAN_F2R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga569ec796b80a5c48de939b628a2368d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72bf4a6050af614eb1ac85c76feb95cc" id="r_ga72bf4a6050af614eb1ac85c76feb95cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72bf4a6050af614eb1ac85c76feb95cc">CAN_F2R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga569ec796b80a5c48de939b628a2368d8">CAN_F2R1_FB7_Msk</a></td></tr>
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<tr class="separator:ga72bf4a6050af614eb1ac85c76feb95cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ecf568bb243c39cb4b591e10ee4c264" id="r_ga2ecf568bb243c39cb4b591e10ee4c264"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ecf568bb243c39cb4b591e10ee4c264">CAN_F2R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga2ecf568bb243c39cb4b591e10ee4c264"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc5dd0d405b5a0e37c5a7b44e3ddb27d" id="r_gacc5dd0d405b5a0e37c5a7b44e3ddb27d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc5dd0d405b5a0e37c5a7b44e3ddb27d">CAN_F2R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ecf568bb243c39cb4b591e10ee4c264">CAN_F2R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:gacc5dd0d405b5a0e37c5a7b44e3ddb27d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad484c083bc2023deda5840facc549908" id="r_gad484c083bc2023deda5840facc549908"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad484c083bc2023deda5840facc549908">CAN_F2R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacc5dd0d405b5a0e37c5a7b44e3ddb27d">CAN_F2R1_FB8_Msk</a></td></tr>
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<tr class="separator:gad484c083bc2023deda5840facc549908"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb6429e869387e036a72125c767616a2" id="r_gadb6429e869387e036a72125c767616a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb6429e869387e036a72125c767616a2">CAN_F2R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gadb6429e869387e036a72125c767616a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c52c1e2532edd862c9480c22ee72340" id="r_ga6c52c1e2532edd862c9480c22ee72340"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c52c1e2532edd862c9480c22ee72340">CAN_F2R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb6429e869387e036a72125c767616a2">CAN_F2R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga6c52c1e2532edd862c9480c22ee72340"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d0e05e4824f05e2cf12b3d0a0b7f319" id="r_ga0d0e05e4824f05e2cf12b3d0a0b7f319"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d0e05e4824f05e2cf12b3d0a0b7f319">CAN_F2R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c52c1e2532edd862c9480c22ee72340">CAN_F2R1_FB9_Msk</a></td></tr>
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<tr class="separator:ga0d0e05e4824f05e2cf12b3d0a0b7f319"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bb1104df1f5ea9a52bad81c16a10f93" id="r_ga4bb1104df1f5ea9a52bad81c16a10f93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bb1104df1f5ea9a52bad81c16a10f93">CAN_F2R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga4bb1104df1f5ea9a52bad81c16a10f93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae64a55a94cadc65b398bd15569223715" id="r_gae64a55a94cadc65b398bd15569223715"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae64a55a94cadc65b398bd15569223715">CAN_F2R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bb1104df1f5ea9a52bad81c16a10f93">CAN_F2R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:gae64a55a94cadc65b398bd15569223715"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga022da7a86e8174aff1054eb1aef2c73c" id="r_ga022da7a86e8174aff1054eb1aef2c73c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga022da7a86e8174aff1054eb1aef2c73c">CAN_F2R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae64a55a94cadc65b398bd15569223715">CAN_F2R1_FB10_Msk</a></td></tr>
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<tr class="separator:ga022da7a86e8174aff1054eb1aef2c73c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8284e29a6acceb7cc51554bb5c1f4e9" id="r_gab8284e29a6acceb7cc51554bb5c1f4e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8284e29a6acceb7cc51554bb5c1f4e9">CAN_F2R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gab8284e29a6acceb7cc51554bb5c1f4e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaeac622ae5a702f2f5ca04eb6d07ba57" id="r_gaaeac622ae5a702f2f5ca04eb6d07ba57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaeac622ae5a702f2f5ca04eb6d07ba57">CAN_F2R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8284e29a6acceb7cc51554bb5c1f4e9">CAN_F2R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:gaaeac622ae5a702f2f5ca04eb6d07ba57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedf715fa1ef43c8461408944e4aecec7" id="r_gaedf715fa1ef43c8461408944e4aecec7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedf715fa1ef43c8461408944e4aecec7">CAN_F2R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaeac622ae5a702f2f5ca04eb6d07ba57">CAN_F2R1_FB11_Msk</a></td></tr>
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<tr class="separator:gaedf715fa1ef43c8461408944e4aecec7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacccd6d7c8fed17e8a960cdea12e9937c" id="r_gacccd6d7c8fed17e8a960cdea12e9937c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacccd6d7c8fed17e8a960cdea12e9937c">CAN_F2R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gacccd6d7c8fed17e8a960cdea12e9937c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6dae1f468ba956371b53f200658cb93e" id="r_ga6dae1f468ba956371b53f200658cb93e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6dae1f468ba956371b53f200658cb93e">CAN_F2R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacccd6d7c8fed17e8a960cdea12e9937c">CAN_F2R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:ga6dae1f468ba956371b53f200658cb93e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47960a79c582cbc9bfef85c411a2be94" id="r_ga47960a79c582cbc9bfef85c411a2be94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47960a79c582cbc9bfef85c411a2be94">CAN_F2R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6dae1f468ba956371b53f200658cb93e">CAN_F2R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga47960a79c582cbc9bfef85c411a2be94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga859f236a687e19660de99278b9f5639e" id="r_ga859f236a687e19660de99278b9f5639e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga859f236a687e19660de99278b9f5639e">CAN_F2R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga859f236a687e19660de99278b9f5639e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82190e04cc99936f1670f81b3e3306d5" id="r_ga82190e04cc99936f1670f81b3e3306d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82190e04cc99936f1670f81b3e3306d5">CAN_F2R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga859f236a687e19660de99278b9f5639e">CAN_F2R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga82190e04cc99936f1670f81b3e3306d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8c6e3cf3a4d1e9d722e820a3a0c1b6a" id="r_gae8c6e3cf3a4d1e9d722e820a3a0c1b6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8c6e3cf3a4d1e9d722e820a3a0c1b6a">CAN_F2R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga82190e04cc99936f1670f81b3e3306d5">CAN_F2R1_FB13_Msk</a></td></tr>
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<tr class="separator:gae8c6e3cf3a4d1e9d722e820a3a0c1b6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga719777f190551358a8e55b4551246985" id="r_ga719777f190551358a8e55b4551246985"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga719777f190551358a8e55b4551246985">CAN_F2R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gae6722c1954e4dc9dce4931ca68545afd" id="r_gae6722c1954e4dc9dce4931ca68545afd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6722c1954e4dc9dce4931ca68545afd">CAN_F2R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga719777f190551358a8e55b4551246985">CAN_F2R1_FB14_Pos</a>)</td></tr>
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<tr class="memitem:ga421a366074fb422686461a92abd1259e" id="r_ga421a366074fb422686461a92abd1259e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga421a366074fb422686461a92abd1259e">CAN_F2R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae6722c1954e4dc9dce4931ca68545afd">CAN_F2R1_FB14_Msk</a></td></tr>
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<tr class="memitem:ga37fe8abfa46f0bd92db7f7a8c67f89b5" id="r_ga37fe8abfa46f0bd92db7f7a8c67f89b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37fe8abfa46f0bd92db7f7a8c67f89b5">CAN_F2R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga3f6b097d716445b57eb181592d9543c7" id="r_ga3f6b097d716445b57eb181592d9543c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f6b097d716445b57eb181592d9543c7">CAN_F2R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga37fe8abfa46f0bd92db7f7a8c67f89b5">CAN_F2R1_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga3f6b097d716445b57eb181592d9543c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga178a0308db954b97818401be1f28a990" id="r_ga178a0308db954b97818401be1f28a990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga178a0308db954b97818401be1f28a990">CAN_F2R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f6b097d716445b57eb181592d9543c7">CAN_F2R1_FB15_Msk</a></td></tr>
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<tr class="separator:ga178a0308db954b97818401be1f28a990"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16b5440836903f347ea7693c40da4a01" id="r_ga16b5440836903f347ea7693c40da4a01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16b5440836903f347ea7693c40da4a01">CAN_F2R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga0d3c41f4d8ac19d40bc8ce0a6c4bf7bf" id="r_ga0d3c41f4d8ac19d40bc8ce0a6c4bf7bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d3c41f4d8ac19d40bc8ce0a6c4bf7bf">CAN_F2R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16b5440836903f347ea7693c40da4a01">CAN_F2R1_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga0d3c41f4d8ac19d40bc8ce0a6c4bf7bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab60aef7e45f8d12777032321a33cdb38" id="r_gab60aef7e45f8d12777032321a33cdb38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab60aef7e45f8d12777032321a33cdb38">CAN_F2R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d3c41f4d8ac19d40bc8ce0a6c4bf7bf">CAN_F2R1_FB16_Msk</a></td></tr>
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<tr class="separator:gab60aef7e45f8d12777032321a33cdb38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a962747d2c8ba69f77cccef2add0bf9" id="r_ga5a962747d2c8ba69f77cccef2add0bf9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a962747d2c8ba69f77cccef2add0bf9">CAN_F2R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga5a962747d2c8ba69f77cccef2add0bf9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa515e5239f2fb3f7669106b0a42ce00b" id="r_gaa515e5239f2fb3f7669106b0a42ce00b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa515e5239f2fb3f7669106b0a42ce00b">CAN_F2R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a962747d2c8ba69f77cccef2add0bf9">CAN_F2R1_FB17_Pos</a>)</td></tr>
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<tr class="separator:gaa515e5239f2fb3f7669106b0a42ce00b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0483dac5b6986246a3ba106fbeb8e3bd" id="r_ga0483dac5b6986246a3ba106fbeb8e3bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0483dac5b6986246a3ba106fbeb8e3bd">CAN_F2R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa515e5239f2fb3f7669106b0a42ce00b">CAN_F2R1_FB17_Msk</a></td></tr>
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<tr class="separator:ga0483dac5b6986246a3ba106fbeb8e3bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70c37fe14d32d847ebb6880849d71e11" id="r_ga70c37fe14d32d847ebb6880849d71e11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70c37fe14d32d847ebb6880849d71e11">CAN_F2R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga70c37fe14d32d847ebb6880849d71e11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7132daf6ddf622a30b31b0dc82b77bcf" id="r_ga7132daf6ddf622a30b31b0dc82b77bcf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7132daf6ddf622a30b31b0dc82b77bcf">CAN_F2R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70c37fe14d32d847ebb6880849d71e11">CAN_F2R1_FB18_Pos</a>)</td></tr>
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<tr class="separator:ga7132daf6ddf622a30b31b0dc82b77bcf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga259b472c9c9f158e1701c8b8d5a940b9" id="r_ga259b472c9c9f158e1701c8b8d5a940b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga259b472c9c9f158e1701c8b8d5a940b9">CAN_F2R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7132daf6ddf622a30b31b0dc82b77bcf">CAN_F2R1_FB18_Msk</a></td></tr>
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<tr class="separator:ga259b472c9c9f158e1701c8b8d5a940b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab020e6235fe4c66882df3b253b4898ef" id="r_gab020e6235fe4c66882df3b253b4898ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab020e6235fe4c66882df3b253b4898ef">CAN_F2R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:gab020e6235fe4c66882df3b253b4898ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55a8f0a1951ca9c9e8cdbac39f64ec6e" id="r_ga55a8f0a1951ca9c9e8cdbac39f64ec6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55a8f0a1951ca9c9e8cdbac39f64ec6e">CAN_F2R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab020e6235fe4c66882df3b253b4898ef">CAN_F2R1_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga55a8f0a1951ca9c9e8cdbac39f64ec6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23db612c79422bee815e437d6aaf5a6c" id="r_ga23db612c79422bee815e437d6aaf5a6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23db612c79422bee815e437d6aaf5a6c">CAN_F2R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga55a8f0a1951ca9c9e8cdbac39f64ec6e">CAN_F2R1_FB19_Msk</a></td></tr>
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<tr class="separator:ga23db612c79422bee815e437d6aaf5a6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32775644499bea180ed6be905e3ac7bc" id="r_ga32775644499bea180ed6be905e3ac7bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32775644499bea180ed6be905e3ac7bc">CAN_F2R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga32775644499bea180ed6be905e3ac7bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58042a29bd588ca97015f8de46239641" id="r_ga58042a29bd588ca97015f8de46239641"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58042a29bd588ca97015f8de46239641">CAN_F2R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga32775644499bea180ed6be905e3ac7bc">CAN_F2R1_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga58042a29bd588ca97015f8de46239641"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef9a469e877bfa29f4edb66730c43d43" id="r_gaef9a469e877bfa29f4edb66730c43d43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef9a469e877bfa29f4edb66730c43d43">CAN_F2R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga58042a29bd588ca97015f8de46239641">CAN_F2R1_FB20_Msk</a></td></tr>
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<tr class="separator:gaef9a469e877bfa29f4edb66730c43d43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaeb4b573d828f2498db857114f0b554f" id="r_gaaeb4b573d828f2498db857114f0b554f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaeb4b573d828f2498db857114f0b554f">CAN_F2R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gaaeb4b573d828f2498db857114f0b554f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6e2ea1ce258fc480fb8b2b12a885c9f" id="r_gad6e2ea1ce258fc480fb8b2b12a885c9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6e2ea1ce258fc480fb8b2b12a885c9f">CAN_F2R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaeb4b573d828f2498db857114f0b554f">CAN_F2R1_FB21_Pos</a>)</td></tr>
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<tr class="separator:gad6e2ea1ce258fc480fb8b2b12a885c9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4edc4a54cc13f63afe8dbe3aa37776a5" id="r_ga4edc4a54cc13f63afe8dbe3aa37776a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4edc4a54cc13f63afe8dbe3aa37776a5">CAN_F2R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad6e2ea1ce258fc480fb8b2b12a885c9f">CAN_F2R1_FB21_Msk</a></td></tr>
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<tr class="separator:ga4edc4a54cc13f63afe8dbe3aa37776a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ed5841ad79cc5cf7e76cc3315b65497" id="r_ga4ed5841ad79cc5cf7e76cc3315b65497"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ed5841ad79cc5cf7e76cc3315b65497">CAN_F2R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga4ed5841ad79cc5cf7e76cc3315b65497"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc6ff16cdc9d4b088573f668d99747af" id="r_gacc6ff16cdc9d4b088573f668d99747af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc6ff16cdc9d4b088573f668d99747af">CAN_F2R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ed5841ad79cc5cf7e76cc3315b65497">CAN_F2R1_FB22_Pos</a>)</td></tr>
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<tr class="memitem:ga169f5fb3dd35ae2b048c8c05c3e202d7" id="r_ga169f5fb3dd35ae2b048c8c05c3e202d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga169f5fb3dd35ae2b048c8c05c3e202d7">CAN_F2R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacc6ff16cdc9d4b088573f668d99747af">CAN_F2R1_FB22_Msk</a></td></tr>
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<tr class="separator:ga169f5fb3dd35ae2b048c8c05c3e202d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3ced515beee7bd23f0d93610bab275b" id="r_gae3ced515beee7bd23f0d93610bab275b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3ced515beee7bd23f0d93610bab275b">CAN_F2R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gae3ced515beee7bd23f0d93610bab275b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9dd3a87b66e7f305670c551b67bff47" id="r_gad9dd3a87b66e7f305670c551b67bff47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9dd3a87b66e7f305670c551b67bff47">CAN_F2R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3ced515beee7bd23f0d93610bab275b">CAN_F2R1_FB23_Pos</a>)</td></tr>
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<tr class="separator:gad9dd3a87b66e7f305670c551b67bff47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0073b206235b3c33a9b831e5027e3bf0" id="r_ga0073b206235b3c33a9b831e5027e3bf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0073b206235b3c33a9b831e5027e3bf0">CAN_F2R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad9dd3a87b66e7f305670c551b67bff47">CAN_F2R1_FB23_Msk</a></td></tr>
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<tr class="separator:ga0073b206235b3c33a9b831e5027e3bf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe33b16774b21585c3661fbe2d9123cd" id="r_gafe33b16774b21585c3661fbe2d9123cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe33b16774b21585c3661fbe2d9123cd">CAN_F2R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:gafe33b16774b21585c3661fbe2d9123cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga353eaadcd9e7a6ffd389c81f75e5b860" id="r_ga353eaadcd9e7a6ffd389c81f75e5b860"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga353eaadcd9e7a6ffd389c81f75e5b860">CAN_F2R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafe33b16774b21585c3661fbe2d9123cd">CAN_F2R1_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga353eaadcd9e7a6ffd389c81f75e5b860"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga459caea38417d17c042e52ba38eb3c1b" id="r_ga459caea38417d17c042e52ba38eb3c1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga459caea38417d17c042e52ba38eb3c1b">CAN_F2R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga353eaadcd9e7a6ffd389c81f75e5b860">CAN_F2R1_FB24_Msk</a></td></tr>
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<tr class="memitem:ga56ce415708ca6b0de210d624e9a5f606" id="r_ga56ce415708ca6b0de210d624e9a5f606"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56ce415708ca6b0de210d624e9a5f606">CAN_F2R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="memitem:ga6516de993c142d8a23cc647e9b06ecd2" id="r_ga6516de993c142d8a23cc647e9b06ecd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6516de993c142d8a23cc647e9b06ecd2">CAN_F2R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga56ce415708ca6b0de210d624e9a5f606">CAN_F2R1_FB25_Pos</a>)</td></tr>
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<tr class="memitem:gae0da8cd8657f6e67f1d86fc9f695bb4e" id="r_gae0da8cd8657f6e67f1d86fc9f695bb4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0da8cd8657f6e67f1d86fc9f695bb4e">CAN_F2R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6516de993c142d8a23cc647e9b06ecd2">CAN_F2R1_FB25_Msk</a></td></tr>
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<tr class="separator:gae0da8cd8657f6e67f1d86fc9f695bb4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga110456643d2876e34dd02e537d9c0453" id="r_ga110456643d2876e34dd02e537d9c0453"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga110456643d2876e34dd02e537d9c0453">CAN_F2R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="memitem:ga14b6583d5cb48decd72eb2bee4113c48" id="r_ga14b6583d5cb48decd72eb2bee4113c48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14b6583d5cb48decd72eb2bee4113c48">CAN_F2R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga110456643d2876e34dd02e537d9c0453">CAN_F2R1_FB26_Pos</a>)</td></tr>
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<tr class="memitem:ga80c9ae7f2eca3db813737c49d49f2b08" id="r_ga80c9ae7f2eca3db813737c49d49f2b08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80c9ae7f2eca3db813737c49d49f2b08">CAN_F2R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b6583d5cb48decd72eb2bee4113c48">CAN_F2R1_FB26_Msk</a></td></tr>
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<tr class="separator:ga80c9ae7f2eca3db813737c49d49f2b08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bfbbc6638ac01d28fe719942ed800cd" id="r_ga5bfbbc6638ac01d28fe719942ed800cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bfbbc6638ac01d28fe719942ed800cd">CAN_F2R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="memitem:ga14b6942aff7b854ed29d7bb8affba388" id="r_ga14b6942aff7b854ed29d7bb8affba388"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14b6942aff7b854ed29d7bb8affba388">CAN_F2R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bfbbc6638ac01d28fe719942ed800cd">CAN_F2R1_FB27_Pos</a>)</td></tr>
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<tr class="memitem:ga1d6b6c109e359e3d2a07e6626c2b4aff" id="r_ga1d6b6c109e359e3d2a07e6626c2b4aff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d6b6c109e359e3d2a07e6626c2b4aff">CAN_F2R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b6942aff7b854ed29d7bb8affba388">CAN_F2R1_FB27_Msk</a></td></tr>
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<tr class="separator:ga1d6b6c109e359e3d2a07e6626c2b4aff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga782f72de6bdfb681a0790934b38ff480" id="r_ga782f72de6bdfb681a0790934b38ff480"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga782f72de6bdfb681a0790934b38ff480">CAN_F2R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="memitem:gab6d262f3000a3723269b53cf0c4f3ad2" id="r_gab6d262f3000a3723269b53cf0c4f3ad2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6d262f3000a3723269b53cf0c4f3ad2">CAN_F2R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga782f72de6bdfb681a0790934b38ff480">CAN_F2R1_FB28_Pos</a>)</td></tr>
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<tr class="separator:gab6d262f3000a3723269b53cf0c4f3ad2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c4d05997d8930291c8ab2bb19545714" id="r_ga3c4d05997d8930291c8ab2bb19545714"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c4d05997d8930291c8ab2bb19545714">CAN_F2R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab6d262f3000a3723269b53cf0c4f3ad2">CAN_F2R1_FB28_Msk</a></td></tr>
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<tr class="memitem:ga0cb04ee516341a536f69fb6c4b87f8b9" id="r_ga0cb04ee516341a536f69fb6c4b87f8b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cb04ee516341a536f69fb6c4b87f8b9">CAN_F2R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga0cb04ee516341a536f69fb6c4b87f8b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7dc1ecaa773500c32c41363b2dff8e72" id="r_ga7dc1ecaa773500c32c41363b2dff8e72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc1ecaa773500c32c41363b2dff8e72">CAN_F2R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cb04ee516341a536f69fb6c4b87f8b9">CAN_F2R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:ga7dc1ecaa773500c32c41363b2dff8e72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5431f98aafd2a7f8158a335d65ebea1" id="r_gad5431f98aafd2a7f8158a335d65ebea1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5431f98aafd2a7f8158a335d65ebea1">CAN_F2R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc1ecaa773500c32c41363b2dff8e72">CAN_F2R1_FB29_Msk</a></td></tr>
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<tr class="separator:gad5431f98aafd2a7f8158a335d65ebea1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb8ecceb7be34c41af7c161d223689a8" id="r_gabb8ecceb7be34c41af7c161d223689a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb8ecceb7be34c41af7c161d223689a8">CAN_F2R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:gabb8ecceb7be34c41af7c161d223689a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga317461fc99abac5a1b3c44487499d315" id="r_ga317461fc99abac5a1b3c44487499d315"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga317461fc99abac5a1b3c44487499d315">CAN_F2R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb8ecceb7be34c41af7c161d223689a8">CAN_F2R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga317461fc99abac5a1b3c44487499d315"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad79345a758898023543bd5384be09758" id="r_gad79345a758898023543bd5384be09758"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad79345a758898023543bd5384be09758">CAN_F2R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga317461fc99abac5a1b3c44487499d315">CAN_F2R1_FB30_Msk</a></td></tr>
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<tr class="separator:gad79345a758898023543bd5384be09758"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab22488fb69df08c9ffc310f3ab575d02" id="r_gab22488fb69df08c9ffc310f3ab575d02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab22488fb69df08c9ffc310f3ab575d02">CAN_F2R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="memitem:ga4ef1c89364eec52f78811d7a8e40d0b4" id="r_ga4ef1c89364eec52f78811d7a8e40d0b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ef1c89364eec52f78811d7a8e40d0b4">CAN_F2R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab22488fb69df08c9ffc310f3ab575d02">CAN_F2R1_FB31_Pos</a>)</td></tr>
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<tr class="memitem:gaada8442f47c1fffb00c13e404d036122" id="r_gaada8442f47c1fffb00c13e404d036122"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaada8442f47c1fffb00c13e404d036122">CAN_F2R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ef1c89364eec52f78811d7a8e40d0b4">CAN_F2R1_FB31_Msk</a></td></tr>
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<tr class="memitem:ga30d5a0c988cb0f7bded01fd1c5bcd9bb" id="r_ga30d5a0c988cb0f7bded01fd1c5bcd9bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30d5a0c988cb0f7bded01fd1c5bcd9bb">CAN_F3R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga30d5a0c988cb0f7bded01fd1c5bcd9bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c1d5628f543d31326f122516ae8d36c" id="r_ga1c1d5628f543d31326f122516ae8d36c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c1d5628f543d31326f122516ae8d36c">CAN_F3R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30d5a0c988cb0f7bded01fd1c5bcd9bb">CAN_F3R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga1c1d5628f543d31326f122516ae8d36c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bc065319a9862c1f5ca7326b790ef53" id="r_ga6bc065319a9862c1f5ca7326b790ef53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bc065319a9862c1f5ca7326b790ef53">CAN_F3R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c1d5628f543d31326f122516ae8d36c">CAN_F3R1_FB0_Msk</a></td></tr>
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<tr class="memitem:ga423e569040031dc2b17a3923d02c7b0a" id="r_ga423e569040031dc2b17a3923d02c7b0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga423e569040031dc2b17a3923d02c7b0a">CAN_F3R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga423e569040031dc2b17a3923d02c7b0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4654a2f7909715abd47c047c550d2ca" id="r_gad4654a2f7909715abd47c047c550d2ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4654a2f7909715abd47c047c550d2ca">CAN_F3R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga423e569040031dc2b17a3923d02c7b0a">CAN_F3R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:gad4654a2f7909715abd47c047c550d2ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42e636521c72a20aa8380fe4fe150b91" id="r_ga42e636521c72a20aa8380fe4fe150b91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42e636521c72a20aa8380fe4fe150b91">CAN_F3R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad4654a2f7909715abd47c047c550d2ca">CAN_F3R1_FB1_Msk</a></td></tr>
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<tr class="memitem:ga183cdb0180529bd94bc2dfd3a2169316" id="r_ga183cdb0180529bd94bc2dfd3a2169316"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga183cdb0180529bd94bc2dfd3a2169316">CAN_F3R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga06d554341693c4f1e9cb5ec2d90c74ca" id="r_ga06d554341693c4f1e9cb5ec2d90c74ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06d554341693c4f1e9cb5ec2d90c74ca">CAN_F3R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga183cdb0180529bd94bc2dfd3a2169316">CAN_F3R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga06d554341693c4f1e9cb5ec2d90c74ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga217f5b77e4fefb2d1135187ee2b5bbf2" id="r_ga217f5b77e4fefb2d1135187ee2b5bbf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga217f5b77e4fefb2d1135187ee2b5bbf2">CAN_F3R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06d554341693c4f1e9cb5ec2d90c74ca">CAN_F3R1_FB2_Msk</a></td></tr>
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<tr class="separator:ga217f5b77e4fefb2d1135187ee2b5bbf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga264110432e8f853262985289f403cf69" id="r_ga264110432e8f853262985289f403cf69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga264110432e8f853262985289f403cf69">CAN_F3R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga264110432e8f853262985289f403cf69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga496aa97ec5c7995b3a6da8e9b33c660e" id="r_ga496aa97ec5c7995b3a6da8e9b33c660e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga496aa97ec5c7995b3a6da8e9b33c660e">CAN_F3R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga264110432e8f853262985289f403cf69">CAN_F3R1_FB3_Pos</a>)</td></tr>
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<tr class="memitem:ga7693dcf6c0011bbeb19e0413a5ce1f56" id="r_ga7693dcf6c0011bbeb19e0413a5ce1f56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7693dcf6c0011bbeb19e0413a5ce1f56">CAN_F3R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga496aa97ec5c7995b3a6da8e9b33c660e">CAN_F3R1_FB3_Msk</a></td></tr>
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<tr class="memitem:gad686b1dae4008be31598e02f433f4d6c" id="r_gad686b1dae4008be31598e02f433f4d6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad686b1dae4008be31598e02f433f4d6c">CAN_F3R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga62eb0d7464f228fd13f2d567e66b0225" id="r_ga62eb0d7464f228fd13f2d567e66b0225"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62eb0d7464f228fd13f2d567e66b0225">CAN_F3R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad686b1dae4008be31598e02f433f4d6c">CAN_F3R1_FB4_Pos</a>)</td></tr>
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<tr class="memitem:ga0bffde5d3e1e2e75f4facc98903620f7" id="r_ga0bffde5d3e1e2e75f4facc98903620f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bffde5d3e1e2e75f4facc98903620f7">CAN_F3R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga62eb0d7464f228fd13f2d567e66b0225">CAN_F3R1_FB4_Msk</a></td></tr>
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<tr class="memitem:ga38b58c76fcd660c939b781c7e82a8b81" id="r_ga38b58c76fcd660c939b781c7e82a8b81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38b58c76fcd660c939b781c7e82a8b81">CAN_F3R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="memitem:ga6e25fcc0e53a3e2d271e06f8985a1e98" id="r_ga6e25fcc0e53a3e2d271e06f8985a1e98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e25fcc0e53a3e2d271e06f8985a1e98">CAN_F3R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga38b58c76fcd660c939b781c7e82a8b81">CAN_F3R1_FB5_Pos</a>)</td></tr>
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<tr class="memitem:ga30ccdfd3676f314e749cc205ffcfe1cf" id="r_ga30ccdfd3676f314e749cc205ffcfe1cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30ccdfd3676f314e749cc205ffcfe1cf">CAN_F3R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e25fcc0e53a3e2d271e06f8985a1e98">CAN_F3R1_FB5_Msk</a></td></tr>
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<tr class="memitem:ga9c71ff110c18c45c1111ff2ec255da30" id="r_ga9c71ff110c18c45c1111ff2ec255da30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c71ff110c18c45c1111ff2ec255da30">CAN_F3R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="memitem:ga1fa5eeffce32825d18dd6ae540691a43" id="r_ga1fa5eeffce32825d18dd6ae540691a43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fa5eeffce32825d18dd6ae540691a43">CAN_F3R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c71ff110c18c45c1111ff2ec255da30">CAN_F3R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga1fa5eeffce32825d18dd6ae540691a43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b2aa80397b4961a33b41303aa348ea1" id="r_ga2b2aa80397b4961a33b41303aa348ea1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b2aa80397b4961a33b41303aa348ea1">CAN_F3R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fa5eeffce32825d18dd6ae540691a43">CAN_F3R1_FB6_Msk</a></td></tr>
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<tr class="memitem:ga2e1076d0bccc07adfcfdd9b10ef70d49" id="r_ga2e1076d0bccc07adfcfdd9b10ef70d49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e1076d0bccc07adfcfdd9b10ef70d49">CAN_F3R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga2e1076d0bccc07adfcfdd9b10ef70d49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f51e4b529f2c096fb6fec2b6d7df1f5" id="r_ga8f51e4b529f2c096fb6fec2b6d7df1f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f51e4b529f2c096fb6fec2b6d7df1f5">CAN_F3R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e1076d0bccc07adfcfdd9b10ef70d49">CAN_F3R1_FB7_Pos</a>)</td></tr>
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<tr class="memitem:ga7b7072c9b829c7df660eb2dea05ee8d8" id="r_ga7b7072c9b829c7df660eb2dea05ee8d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b7072c9b829c7df660eb2dea05ee8d8">CAN_F3R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f51e4b529f2c096fb6fec2b6d7df1f5">CAN_F3R1_FB7_Msk</a></td></tr>
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<tr class="separator:ga7b7072c9b829c7df660eb2dea05ee8d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99ec42fffa4e19dd6841adeb7c581bbe" id="r_ga99ec42fffa4e19dd6841adeb7c581bbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99ec42fffa4e19dd6841adeb7c581bbe">CAN_F3R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga99ec42fffa4e19dd6841adeb7c581bbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa223fb562425adcb7022b2b5e6f0da6" id="r_gafa223fb562425adcb7022b2b5e6f0da6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa223fb562425adcb7022b2b5e6f0da6">CAN_F3R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga99ec42fffa4e19dd6841adeb7c581bbe">CAN_F3R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:gafa223fb562425adcb7022b2b5e6f0da6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad016208d1aa9008aaba9a887a1e8b6fa" id="r_gad016208d1aa9008aaba9a887a1e8b6fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad016208d1aa9008aaba9a887a1e8b6fa">CAN_F3R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafa223fb562425adcb7022b2b5e6f0da6">CAN_F3R1_FB8_Msk</a></td></tr>
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<tr class="separator:gad016208d1aa9008aaba9a887a1e8b6fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a409b79ae2582691f8998c525f259fc" id="r_ga1a409b79ae2582691f8998c525f259fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a409b79ae2582691f8998c525f259fc">CAN_F3R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga1a409b79ae2582691f8998c525f259fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga900e4c0c595155e852cbc17fda96e9ee" id="r_ga900e4c0c595155e852cbc17fda96e9ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga900e4c0c595155e852cbc17fda96e9ee">CAN_F3R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a409b79ae2582691f8998c525f259fc">CAN_F3R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga900e4c0c595155e852cbc17fda96e9ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4f4f0d2b56860e36f7777ab397e8609" id="r_gad4f4f0d2b56860e36f7777ab397e8609"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4f4f0d2b56860e36f7777ab397e8609">CAN_F3R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga900e4c0c595155e852cbc17fda96e9ee">CAN_F3R1_FB9_Msk</a></td></tr>
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<tr class="separator:gad4f4f0d2b56860e36f7777ab397e8609"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5bff557fd63b73e4490b972bb5ac946" id="r_gac5bff557fd63b73e4490b972bb5ac946"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5bff557fd63b73e4490b972bb5ac946">CAN_F3R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gac5bff557fd63b73e4490b972bb5ac946"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a3ae8c895b853d340ff7a133870164a" id="r_ga8a3ae8c895b853d340ff7a133870164a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a3ae8c895b853d340ff7a133870164a">CAN_F3R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac5bff557fd63b73e4490b972bb5ac946">CAN_F3R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga8a3ae8c895b853d340ff7a133870164a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcfc2559b456c3af3804a22e0fb5c50d" id="r_gadcfc2559b456c3af3804a22e0fb5c50d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcfc2559b456c3af3804a22e0fb5c50d">CAN_F3R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a3ae8c895b853d340ff7a133870164a">CAN_F3R1_FB10_Msk</a></td></tr>
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<tr class="separator:gadcfc2559b456c3af3804a22e0fb5c50d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9f0a4a347f318e110ce2139acb78b13" id="r_gab9f0a4a347f318e110ce2139acb78b13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9f0a4a347f318e110ce2139acb78b13">CAN_F3R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gab9f0a4a347f318e110ce2139acb78b13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68222a41a14bb43bc6d2f0fc4dee1e0f" id="r_ga68222a41a14bb43bc6d2f0fc4dee1e0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68222a41a14bb43bc6d2f0fc4dee1e0f">CAN_F3R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9f0a4a347f318e110ce2139acb78b13">CAN_F3R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga68222a41a14bb43bc6d2f0fc4dee1e0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7df8031e3a2f661b45fdbde58a26c6b6" id="r_ga7df8031e3a2f661b45fdbde58a26c6b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7df8031e3a2f661b45fdbde58a26c6b6">CAN_F3R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga68222a41a14bb43bc6d2f0fc4dee1e0f">CAN_F3R1_FB11_Msk</a></td></tr>
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<tr class="separator:ga7df8031e3a2f661b45fdbde58a26c6b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2d38f5393492a54b470fa2b985cec67" id="r_gaf2d38f5393492a54b470fa2b985cec67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2d38f5393492a54b470fa2b985cec67">CAN_F3R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaf2d38f5393492a54b470fa2b985cec67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec2bac1777b3ebef8b3a22d22514a4b2" id="r_gaec2bac1777b3ebef8b3a22d22514a4b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec2bac1777b3ebef8b3a22d22514a4b2">CAN_F3R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2d38f5393492a54b470fa2b985cec67">CAN_F3R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:gaec2bac1777b3ebef8b3a22d22514a4b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c6baa9ac6a1cdd55c2d51ee40cf8f2d" id="r_ga6c6baa9ac6a1cdd55c2d51ee40cf8f2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c6baa9ac6a1cdd55c2d51ee40cf8f2d">CAN_F3R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec2bac1777b3ebef8b3a22d22514a4b2">CAN_F3R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga6c6baa9ac6a1cdd55c2d51ee40cf8f2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafaf1ceb6b25d05652aba0ef3a04caf40" id="r_gafaf1ceb6b25d05652aba0ef3a04caf40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafaf1ceb6b25d05652aba0ef3a04caf40">CAN_F3R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gafaf1ceb6b25d05652aba0ef3a04caf40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47f4c6942bebdcb179b5092520842e91" id="r_ga47f4c6942bebdcb179b5092520842e91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47f4c6942bebdcb179b5092520842e91">CAN_F3R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafaf1ceb6b25d05652aba0ef3a04caf40">CAN_F3R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga47f4c6942bebdcb179b5092520842e91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95fc8c778ffa6deac5a202985fdd98ae" id="r_ga95fc8c778ffa6deac5a202985fdd98ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95fc8c778ffa6deac5a202985fdd98ae">CAN_F3R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47f4c6942bebdcb179b5092520842e91">CAN_F3R1_FB13_Msk</a></td></tr>
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<tr class="separator:ga95fc8c778ffa6deac5a202985fdd98ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2792beb7bfcf3e2ca26e092bb4ed2d50" id="r_ga2792beb7bfcf3e2ca26e092bb4ed2d50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2792beb7bfcf3e2ca26e092bb4ed2d50">CAN_F3R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga2792beb7bfcf3e2ca26e092bb4ed2d50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3cbf7b6b28dce1e65f4377273b060b7" id="r_gaf3cbf7b6b28dce1e65f4377273b060b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3cbf7b6b28dce1e65f4377273b060b7">CAN_F3R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2792beb7bfcf3e2ca26e092bb4ed2d50">CAN_F3R1_FB14_Pos</a>)</td></tr>
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<tr class="memitem:ga0c4a4998f2ddc12771da116b1c20d765" id="r_ga0c4a4998f2ddc12771da116b1c20d765"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c4a4998f2ddc12771da116b1c20d765">CAN_F3R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3cbf7b6b28dce1e65f4377273b060b7">CAN_F3R1_FB14_Msk</a></td></tr>
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<tr class="separator:ga0c4a4998f2ddc12771da116b1c20d765"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7087ca402b574d4cce164525a75942c1" id="r_ga7087ca402b574d4cce164525a75942c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7087ca402b574d4cce164525a75942c1">CAN_F3R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga3d5afdf5c983489b0bcd8029a6e1c45a" id="r_ga3d5afdf5c983489b0bcd8029a6e1c45a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d5afdf5c983489b0bcd8029a6e1c45a">CAN_F3R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7087ca402b574d4cce164525a75942c1">CAN_F3R1_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga3d5afdf5c983489b0bcd8029a6e1c45a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fb6157fc48147e6c74ed348d156bfa1" id="r_ga5fb6157fc48147e6c74ed348d156bfa1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fb6157fc48147e6c74ed348d156bfa1">CAN_F3R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d5afdf5c983489b0bcd8029a6e1c45a">CAN_F3R1_FB15_Msk</a></td></tr>
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<tr class="memitem:ga69cf5d074fb4b4a823b2f2071b5a391d" id="r_ga69cf5d074fb4b4a823b2f2071b5a391d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69cf5d074fb4b4a823b2f2071b5a391d">CAN_F3R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gaadc1997d8f970761e068263b8aa9f439" id="r_gaadc1997d8f970761e068263b8aa9f439"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadc1997d8f970761e068263b8aa9f439">CAN_F3R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69cf5d074fb4b4a823b2f2071b5a391d">CAN_F3R1_FB16_Pos</a>)</td></tr>
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<tr class="memitem:gaadcf2a14e752519bf8a90129fb9d42b1" id="r_gaadcf2a14e752519bf8a90129fb9d42b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadcf2a14e752519bf8a90129fb9d42b1">CAN_F3R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaadc1997d8f970761e068263b8aa9f439">CAN_F3R1_FB16_Msk</a></td></tr>
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<tr class="separator:gaadcf2a14e752519bf8a90129fb9d42b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadccd15d0bba8530373bb5beafd51ccff" id="r_gadccd15d0bba8530373bb5beafd51ccff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadccd15d0bba8530373bb5beafd51ccff">CAN_F3R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="memitem:ga8221248c305454dd5071679742a56383" id="r_ga8221248c305454dd5071679742a56383"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8221248c305454dd5071679742a56383">CAN_F3R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadccd15d0bba8530373bb5beafd51ccff">CAN_F3R1_FB17_Pos</a>)</td></tr>
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<tr class="memitem:ga47c5296c991b481548302478df85e477" id="r_ga47c5296c991b481548302478df85e477"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47c5296c991b481548302478df85e477">CAN_F3R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8221248c305454dd5071679742a56383">CAN_F3R1_FB17_Msk</a></td></tr>
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<tr class="memitem:ga667df86ec3ab1ef7d9a90d3e69a97ef7" id="r_ga667df86ec3ab1ef7d9a90d3e69a97ef7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga667df86ec3ab1ef7d9a90d3e69a97ef7">CAN_F3R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga667df86ec3ab1ef7d9a90d3e69a97ef7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad84e18a8d220d1dbf071afcbe969b976" id="r_gad84e18a8d220d1dbf071afcbe969b976"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad84e18a8d220d1dbf071afcbe969b976">CAN_F3R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga667df86ec3ab1ef7d9a90d3e69a97ef7">CAN_F3R1_FB18_Pos</a>)</td></tr>
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<tr class="separator:gad84e18a8d220d1dbf071afcbe969b976"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga657b8cda94fd736a4831ab4086ae746f" id="r_ga657b8cda94fd736a4831ab4086ae746f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga657b8cda94fd736a4831ab4086ae746f">CAN_F3R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad84e18a8d220d1dbf071afcbe969b976">CAN_F3R1_FB18_Msk</a></td></tr>
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<tr class="separator:ga657b8cda94fd736a4831ab4086ae746f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e23acb5ecf6e18637060239a690c034" id="r_ga4e23acb5ecf6e18637060239a690c034"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e23acb5ecf6e18637060239a690c034">CAN_F3R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga4e23acb5ecf6e18637060239a690c034"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3806303c3cfe2dcee6e3409eb1492b6" id="r_gaa3806303c3cfe2dcee6e3409eb1492b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3806303c3cfe2dcee6e3409eb1492b6">CAN_F3R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e23acb5ecf6e18637060239a690c034">CAN_F3R1_FB19_Pos</a>)</td></tr>
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<tr class="memitem:ga435edc4b2055ac2d1c3ce616a9c1b236" id="r_ga435edc4b2055ac2d1c3ce616a9c1b236"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga435edc4b2055ac2d1c3ce616a9c1b236">CAN_F3R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3806303c3cfe2dcee6e3409eb1492b6">CAN_F3R1_FB19_Msk</a></td></tr>
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<tr class="separator:ga435edc4b2055ac2d1c3ce616a9c1b236"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf81dbe7a19466ef9c89804d77b695a8a" id="r_gaf81dbe7a19466ef9c89804d77b695a8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf81dbe7a19466ef9c89804d77b695a8a">CAN_F3R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gaf81dbe7a19466ef9c89804d77b695a8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05e8b9d7e4cdc6856c6ad61d15fae9f2" id="r_ga05e8b9d7e4cdc6856c6ad61d15fae9f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05e8b9d7e4cdc6856c6ad61d15fae9f2">CAN_F3R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf81dbe7a19466ef9c89804d77b695a8a">CAN_F3R1_FB20_Pos</a>)</td></tr>
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<tr class="memitem:gaaa508de7087eb832ecaf353a4b6821ef" id="r_gaaa508de7087eb832ecaf353a4b6821ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa508de7087eb832ecaf353a4b6821ef">CAN_F3R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga05e8b9d7e4cdc6856c6ad61d15fae9f2">CAN_F3R1_FB20_Msk</a></td></tr>
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<tr class="separator:gaaa508de7087eb832ecaf353a4b6821ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga504f3a0b162d61b85df522610ce39ef7" id="r_ga504f3a0b162d61b85df522610ce39ef7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga504f3a0b162d61b85df522610ce39ef7">CAN_F3R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga504f3a0b162d61b85df522610ce39ef7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1c6bf19e9356adcb47a75895b653025" id="r_gae1c6bf19e9356adcb47a75895b653025"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1c6bf19e9356adcb47a75895b653025">CAN_F3R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga504f3a0b162d61b85df522610ce39ef7">CAN_F3R1_FB21_Pos</a>)</td></tr>
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<tr class="memitem:ga643ceb9293665b8307e63ae0e1700d91" id="r_ga643ceb9293665b8307e63ae0e1700d91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga643ceb9293665b8307e63ae0e1700d91">CAN_F3R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae1c6bf19e9356adcb47a75895b653025">CAN_F3R1_FB21_Msk</a></td></tr>
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<tr class="separator:ga643ceb9293665b8307e63ae0e1700d91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga802dd3b3cb24cf29fef5a437d611f374" id="r_ga802dd3b3cb24cf29fef5a437d611f374"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga802dd3b3cb24cf29fef5a437d611f374">CAN_F3R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga802dd3b3cb24cf29fef5a437d611f374"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12f9cc55362b508457dae2a22f3577b9" id="r_ga12f9cc55362b508457dae2a22f3577b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12f9cc55362b508457dae2a22f3577b9">CAN_F3R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga802dd3b3cb24cf29fef5a437d611f374">CAN_F3R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga12f9cc55362b508457dae2a22f3577b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91f5887e884fcf423d680798f4e372bb" id="r_ga91f5887e884fcf423d680798f4e372bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91f5887e884fcf423d680798f4e372bb">CAN_F3R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga12f9cc55362b508457dae2a22f3577b9">CAN_F3R1_FB22_Msk</a></td></tr>
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<tr class="separator:ga91f5887e884fcf423d680798f4e372bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b4c505b76333edc055ec8185ce9cca3" id="r_ga3b4c505b76333edc055ec8185ce9cca3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b4c505b76333edc055ec8185ce9cca3">CAN_F3R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga3b4c505b76333edc055ec8185ce9cca3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53b384413c96686c5b6d955edf3605e7" id="r_ga53b384413c96686c5b6d955edf3605e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53b384413c96686c5b6d955edf3605e7">CAN_F3R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b4c505b76333edc055ec8185ce9cca3">CAN_F3R1_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga53b384413c96686c5b6d955edf3605e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6adc9c7706f39f7c33760fe6b8c5d17e" id="r_ga6adc9c7706f39f7c33760fe6b8c5d17e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6adc9c7706f39f7c33760fe6b8c5d17e">CAN_F3R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga53b384413c96686c5b6d955edf3605e7">CAN_F3R1_FB23_Msk</a></td></tr>
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<tr class="separator:ga6adc9c7706f39f7c33760fe6b8c5d17e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae72365189f731236a0347f2577b26ad1" id="r_gae72365189f731236a0347f2577b26ad1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae72365189f731236a0347f2577b26ad1">CAN_F3R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga84c095337bdce797f169006a2b79ecda" id="r_ga84c095337bdce797f169006a2b79ecda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84c095337bdce797f169006a2b79ecda">CAN_F3R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae72365189f731236a0347f2577b26ad1">CAN_F3R1_FB24_Pos</a>)</td></tr>
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<tr class="memitem:gad7581186f0241f6db9f63a0a0db22919" id="r_gad7581186f0241f6db9f63a0a0db22919"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7581186f0241f6db9f63a0a0db22919">CAN_F3R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga84c095337bdce797f169006a2b79ecda">CAN_F3R1_FB24_Msk</a></td></tr>
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<tr class="memitem:gaf7eb5954b6b37e1c895c7e5379b9ed89" id="r_gaf7eb5954b6b37e1c895c7e5379b9ed89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7eb5954b6b37e1c895c7e5379b9ed89">CAN_F3R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gaf7eb5954b6b37e1c895c7e5379b9ed89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad411d7ebb23972f68d8d3622a89de73e" id="r_gad411d7ebb23972f68d8d3622a89de73e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad411d7ebb23972f68d8d3622a89de73e">CAN_F3R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7eb5954b6b37e1c895c7e5379b9ed89">CAN_F3R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:gad411d7ebb23972f68d8d3622a89de73e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43b4c084e802398ad265ceb69cfd7519" id="r_ga43b4c084e802398ad265ceb69cfd7519"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43b4c084e802398ad265ceb69cfd7519">CAN_F3R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad411d7ebb23972f68d8d3622a89de73e">CAN_F3R1_FB25_Msk</a></td></tr>
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<tr class="separator:ga43b4c084e802398ad265ceb69cfd7519"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa963a783c31dfb619f95c5f36fbbbfbb" id="r_gaa963a783c31dfb619f95c5f36fbbbfbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa963a783c31dfb619f95c5f36fbbbfbb">CAN_F3R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:gaa963a783c31dfb619f95c5f36fbbbfbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56aa4a1d23228828e880810e6d644054" id="r_ga56aa4a1d23228828e880810e6d644054"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56aa4a1d23228828e880810e6d644054">CAN_F3R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa963a783c31dfb619f95c5f36fbbbfbb">CAN_F3R1_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga56aa4a1d23228828e880810e6d644054"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade732503a8d41e3f1bb338a2a8103bd2" id="r_gade732503a8d41e3f1bb338a2a8103bd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade732503a8d41e3f1bb338a2a8103bd2">CAN_F3R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga56aa4a1d23228828e880810e6d644054">CAN_F3R1_FB26_Msk</a></td></tr>
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<tr class="separator:gade732503a8d41e3f1bb338a2a8103bd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga402faf6e5640540970f69b796fec57bc" id="r_ga402faf6e5640540970f69b796fec57bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga402faf6e5640540970f69b796fec57bc">CAN_F3R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga402faf6e5640540970f69b796fec57bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a14d8e964a880b27705af96225917cb" id="r_ga8a14d8e964a880b27705af96225917cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a14d8e964a880b27705af96225917cb">CAN_F3R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga402faf6e5640540970f69b796fec57bc">CAN_F3R1_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga8a14d8e964a880b27705af96225917cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7539a7f651425a757a549205544e508c" id="r_ga7539a7f651425a757a549205544e508c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7539a7f651425a757a549205544e508c">CAN_F3R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a14d8e964a880b27705af96225917cb">CAN_F3R1_FB27_Msk</a></td></tr>
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<tr class="separator:ga7539a7f651425a757a549205544e508c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac25fde9cd308c5fde521c6c649112109" id="r_gac25fde9cd308c5fde521c6c649112109"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac25fde9cd308c5fde521c6c649112109">CAN_F3R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:gac25fde9cd308c5fde521c6c649112109"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62dea0d389306d34595416ca334c7bf1" id="r_ga62dea0d389306d34595416ca334c7bf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62dea0d389306d34595416ca334c7bf1">CAN_F3R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac25fde9cd308c5fde521c6c649112109">CAN_F3R1_FB28_Pos</a>)</td></tr>
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<tr class="separator:ga62dea0d389306d34595416ca334c7bf1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ec25e4ba3ebaf53780e2b8da63e4a3b" id="r_ga1ec25e4ba3ebaf53780e2b8da63e4a3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ec25e4ba3ebaf53780e2b8da63e4a3b">CAN_F3R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga62dea0d389306d34595416ca334c7bf1">CAN_F3R1_FB28_Msk</a></td></tr>
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<tr class="separator:ga1ec25e4ba3ebaf53780e2b8da63e4a3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf98ffdf9966c92a5cbbcb23ad6c36b1a" id="r_gaf98ffdf9966c92a5cbbcb23ad6c36b1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf98ffdf9966c92a5cbbcb23ad6c36b1a">CAN_F3R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:gaf98ffdf9966c92a5cbbcb23ad6c36b1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04da25e051a24c10b8d59f6a87818fb0" id="r_ga04da25e051a24c10b8d59f6a87818fb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04da25e051a24c10b8d59f6a87818fb0">CAN_F3R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf98ffdf9966c92a5cbbcb23ad6c36b1a">CAN_F3R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:ga04da25e051a24c10b8d59f6a87818fb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8268be8b5477f813c165e851acd41a2" id="r_gae8268be8b5477f813c165e851acd41a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8268be8b5477f813c165e851acd41a2">CAN_F3R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga04da25e051a24c10b8d59f6a87818fb0">CAN_F3R1_FB29_Msk</a></td></tr>
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<tr class="separator:gae8268be8b5477f813c165e851acd41a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a6f8058f778d1ec69794aa937d96337" id="r_ga5a6f8058f778d1ec69794aa937d96337"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a6f8058f778d1ec69794aa937d96337">CAN_F3R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga5a6f8058f778d1ec69794aa937d96337"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc9b888a2c0f23588c4f79d7e1545c61" id="r_gadc9b888a2c0f23588c4f79d7e1545c61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc9b888a2c0f23588c4f79d7e1545c61">CAN_F3R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a6f8058f778d1ec69794aa937d96337">CAN_F3R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:gadc9b888a2c0f23588c4f79d7e1545c61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga494ad7f35d8552b8494379916a987074" id="r_ga494ad7f35d8552b8494379916a987074"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga494ad7f35d8552b8494379916a987074">CAN_F3R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadc9b888a2c0f23588c4f79d7e1545c61">CAN_F3R1_FB30_Msk</a></td></tr>
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<tr class="separator:ga494ad7f35d8552b8494379916a987074"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab45325d0fb96d86f848601a582e47a5d" id="r_gab45325d0fb96d86f848601a582e47a5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab45325d0fb96d86f848601a582e47a5d">CAN_F3R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:gab45325d0fb96d86f848601a582e47a5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf5486013f92f3646e9ac903676b6743" id="r_gaaf5486013f92f3646e9ac903676b6743"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf5486013f92f3646e9ac903676b6743">CAN_F3R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab45325d0fb96d86f848601a582e47a5d">CAN_F3R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:gaaf5486013f92f3646e9ac903676b6743"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15bbe0d2d24dc95e10156c2541feb4c4" id="r_ga15bbe0d2d24dc95e10156c2541feb4c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15bbe0d2d24dc95e10156c2541feb4c4">CAN_F3R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf5486013f92f3646e9ac903676b6743">CAN_F3R1_FB31_Msk</a></td></tr>
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<tr class="separator:ga15bbe0d2d24dc95e10156c2541feb4c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5573bdc4becbeaab63e285f60bb316c6" id="r_ga5573bdc4becbeaab63e285f60bb316c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5573bdc4becbeaab63e285f60bb316c6">CAN_F4R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5573bdc4becbeaab63e285f60bb316c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7988e6a122cc6084ea40df4b66de5f0f" id="r_ga7988e6a122cc6084ea40df4b66de5f0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7988e6a122cc6084ea40df4b66de5f0f">CAN_F4R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5573bdc4becbeaab63e285f60bb316c6">CAN_F4R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga7988e6a122cc6084ea40df4b66de5f0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0eb0d4d21c082c8381271ab146431993" id="r_ga0eb0d4d21c082c8381271ab146431993"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0eb0d4d21c082c8381271ab146431993">CAN_F4R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7988e6a122cc6084ea40df4b66de5f0f">CAN_F4R1_FB0_Msk</a></td></tr>
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<tr class="separator:ga0eb0d4d21c082c8381271ab146431993"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga279a547f6c7143c59c912d85973493d1" id="r_ga279a547f6c7143c59c912d85973493d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga279a547f6c7143c59c912d85973493d1">CAN_F4R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga279a547f6c7143c59c912d85973493d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa88382bdd2a166258413d39fbb436050" id="r_gaa88382bdd2a166258413d39fbb436050"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa88382bdd2a166258413d39fbb436050">CAN_F4R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga279a547f6c7143c59c912d85973493d1">CAN_F4R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:gaa88382bdd2a166258413d39fbb436050"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91922c78bf92f051b8e8abbf9cc1f6e9" id="r_ga91922c78bf92f051b8e8abbf9cc1f6e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91922c78bf92f051b8e8abbf9cc1f6e9">CAN_F4R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa88382bdd2a166258413d39fbb436050">CAN_F4R1_FB1_Msk</a></td></tr>
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<tr class="separator:ga91922c78bf92f051b8e8abbf9cc1f6e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae735647331c284d403b4917ff3b213ce" id="r_gae735647331c284d403b4917ff3b213ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae735647331c284d403b4917ff3b213ce">CAN_F4R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gae735647331c284d403b4917ff3b213ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6564dfdae0be64785df0d766aa5c149" id="r_gaf6564dfdae0be64785df0d766aa5c149"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6564dfdae0be64785df0d766aa5c149">CAN_F4R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae735647331c284d403b4917ff3b213ce">CAN_F4R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:gaf6564dfdae0be64785df0d766aa5c149"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae56f77f869114e69525353f96004f955" id="r_gae56f77f869114e69525353f96004f955"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae56f77f869114e69525353f96004f955">CAN_F4R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6564dfdae0be64785df0d766aa5c149">CAN_F4R1_FB2_Msk</a></td></tr>
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<tr class="separator:gae56f77f869114e69525353f96004f955"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac731872ee45a7e0569871bfb02c6b6e9" id="r_gac731872ee45a7e0569871bfb02c6b6e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac731872ee45a7e0569871bfb02c6b6e9">CAN_F4R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gac731872ee45a7e0569871bfb02c6b6e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga786fe254e7a86a2ac517ea453f78e120" id="r_ga786fe254e7a86a2ac517ea453f78e120"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga786fe254e7a86a2ac517ea453f78e120">CAN_F4R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac731872ee45a7e0569871bfb02c6b6e9">CAN_F4R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga786fe254e7a86a2ac517ea453f78e120"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga951a8213e55b01ecedcef870c85841e7" id="r_ga951a8213e55b01ecedcef870c85841e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga951a8213e55b01ecedcef870c85841e7">CAN_F4R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga786fe254e7a86a2ac517ea453f78e120">CAN_F4R1_FB3_Msk</a></td></tr>
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<tr class="memitem:ga17f4894ca5438e060ea17fcb6d0d2f9b" id="r_ga17f4894ca5438e060ea17fcb6d0d2f9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17f4894ca5438e060ea17fcb6d0d2f9b">CAN_F4R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="memitem:gabd92184f0f30164e14b07a7a4e5208a2" id="r_gabd92184f0f30164e14b07a7a4e5208a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd92184f0f30164e14b07a7a4e5208a2">CAN_F4R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17f4894ca5438e060ea17fcb6d0d2f9b">CAN_F4R1_FB4_Pos</a>)</td></tr>
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<tr class="memitem:ga453f90cdd0b520b7d65e19af3868d4ec" id="r_ga453f90cdd0b520b7d65e19af3868d4ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga453f90cdd0b520b7d65e19af3868d4ec">CAN_F4R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd92184f0f30164e14b07a7a4e5208a2">CAN_F4R1_FB4_Msk</a></td></tr>
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<tr class="memitem:gaf3eff06bd3294a077a43d55419ecbfbb" id="r_gaf3eff06bd3294a077a43d55419ecbfbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3eff06bd3294a077a43d55419ecbfbb">CAN_F4R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="memitem:ga4a8707829180a6a5ea26822a408facce" id="r_ga4a8707829180a6a5ea26822a408facce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a8707829180a6a5ea26822a408facce">CAN_F4R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3eff06bd3294a077a43d55419ecbfbb">CAN_F4R1_FB5_Pos</a>)</td></tr>
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<tr class="memitem:gace348ba56c1f9676e5b605a6fe0cd52e" id="r_gace348ba56c1f9676e5b605a6fe0cd52e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace348ba56c1f9676e5b605a6fe0cd52e">CAN_F4R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a8707829180a6a5ea26822a408facce">CAN_F4R1_FB5_Msk</a></td></tr>
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<tr class="separator:gace348ba56c1f9676e5b605a6fe0cd52e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaea2a7ac1148da335845a257f1dde33e" id="r_gaaea2a7ac1148da335845a257f1dde33e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaea2a7ac1148da335845a257f1dde33e">CAN_F4R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="memitem:ga270fa51a92450225b554f19353f38f0e" id="r_ga270fa51a92450225b554f19353f38f0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga270fa51a92450225b554f19353f38f0e">CAN_F4R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaea2a7ac1148da335845a257f1dde33e">CAN_F4R1_FB6_Pos</a>)</td></tr>
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<tr class="memitem:gae99d36b50a16c38b2006fdba4683ddd9" id="r_gae99d36b50a16c38b2006fdba4683ddd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae99d36b50a16c38b2006fdba4683ddd9">CAN_F4R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga270fa51a92450225b554f19353f38f0e">CAN_F4R1_FB6_Msk</a></td></tr>
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<tr class="memitem:gac4c8a70e48e55e45b8d3322a344bfa45" id="r_gac4c8a70e48e55e45b8d3322a344bfa45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4c8a70e48e55e45b8d3322a344bfa45">CAN_F4R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="memitem:ga474765e4a523545019ad84e02c9af69c" id="r_ga474765e4a523545019ad84e02c9af69c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga474765e4a523545019ad84e02c9af69c">CAN_F4R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4c8a70e48e55e45b8d3322a344bfa45">CAN_F4R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga474765e4a523545019ad84e02c9af69c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d61ae4af9acc61476493b640cfb4745" id="r_ga5d61ae4af9acc61476493b640cfb4745"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d61ae4af9acc61476493b640cfb4745">CAN_F4R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga474765e4a523545019ad84e02c9af69c">CAN_F4R1_FB7_Msk</a></td></tr>
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<tr class="memitem:gab4e861543c2dd0e3bfbd34fd6e97927f" id="r_gab4e861543c2dd0e3bfbd34fd6e97927f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4e861543c2dd0e3bfbd34fd6e97927f">CAN_F4R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gaa256896c733d9155ab9c60d6f2d58a3b" id="r_gaa256896c733d9155ab9c60d6f2d58a3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa256896c733d9155ab9c60d6f2d58a3b">CAN_F4R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab4e861543c2dd0e3bfbd34fd6e97927f">CAN_F4R1_FB8_Pos</a>)</td></tr>
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<tr class="memitem:ga89ded00ec0b6c0918b019457d6cf43f5" id="r_ga89ded00ec0b6c0918b019457d6cf43f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89ded00ec0b6c0918b019457d6cf43f5">CAN_F4R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa256896c733d9155ab9c60d6f2d58a3b">CAN_F4R1_FB8_Msk</a></td></tr>
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<tr class="memitem:ga8fe495bcc370cfd21bdf1b6e751aa23a" id="r_ga8fe495bcc370cfd21bdf1b6e751aa23a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fe495bcc370cfd21bdf1b6e751aa23a">CAN_F4R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga8fe495bcc370cfd21bdf1b6e751aa23a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fdff1d01f74ad524f97bd3a138e6c4d" id="r_ga4fdff1d01f74ad524f97bd3a138e6c4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fdff1d01f74ad524f97bd3a138e6c4d">CAN_F4R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fe495bcc370cfd21bdf1b6e751aa23a">CAN_F4R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga4fdff1d01f74ad524f97bd3a138e6c4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac658a1ced873fd9dff54833d8c413536" id="r_gac658a1ced873fd9dff54833d8c413536"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac658a1ced873fd9dff54833d8c413536">CAN_F4R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4fdff1d01f74ad524f97bd3a138e6c4d">CAN_F4R1_FB9_Msk</a></td></tr>
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<tr class="memitem:ga34153173f76d8b1aacbdd013a733fdd2" id="r_ga34153173f76d8b1aacbdd013a733fdd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34153173f76d8b1aacbdd013a733fdd2">CAN_F4R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga34153173f76d8b1aacbdd013a733fdd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d5e8f2c67a528aa361922158ae8eb92" id="r_ga2d5e8f2c67a528aa361922158ae8eb92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d5e8f2c67a528aa361922158ae8eb92">CAN_F4R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34153173f76d8b1aacbdd013a733fdd2">CAN_F4R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga2d5e8f2c67a528aa361922158ae8eb92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad06bc748776a78f008895be9e0cc7a1d" id="r_gad06bc748776a78f008895be9e0cc7a1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad06bc748776a78f008895be9e0cc7a1d">CAN_F4R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d5e8f2c67a528aa361922158ae8eb92">CAN_F4R1_FB10_Msk</a></td></tr>
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<tr class="memitem:gac8adba35f6ed518c3d762d8c791cfb85" id="r_gac8adba35f6ed518c3d762d8c791cfb85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8adba35f6ed518c3d762d8c791cfb85">CAN_F4R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gac8adba35f6ed518c3d762d8c791cfb85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50cb96e2d638c18f5ce23bed3342f39d" id="r_ga50cb96e2d638c18f5ce23bed3342f39d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50cb96e2d638c18f5ce23bed3342f39d">CAN_F4R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8adba35f6ed518c3d762d8c791cfb85">CAN_F4R1_FB11_Pos</a>)</td></tr>
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<tr class="memitem:gaf612f239dcf45bd933136a5c8c5909f9" id="r_gaf612f239dcf45bd933136a5c8c5909f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf612f239dcf45bd933136a5c8c5909f9">CAN_F4R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga50cb96e2d638c18f5ce23bed3342f39d">CAN_F4R1_FB11_Msk</a></td></tr>
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<tr class="separator:gaf612f239dcf45bd933136a5c8c5909f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa308445d00347d34a263c82c0b5cc5a" id="r_gafa308445d00347d34a263c82c0b5cc5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa308445d00347d34a263c82c0b5cc5a">CAN_F4R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gafa308445d00347d34a263c82c0b5cc5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga613094782d73b0e3e5272eff72f04d42" id="r_ga613094782d73b0e3e5272eff72f04d42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga613094782d73b0e3e5272eff72f04d42">CAN_F4R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafa308445d00347d34a263c82c0b5cc5a">CAN_F4R1_FB12_Pos</a>)</td></tr>
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<tr class="memitem:ga6dc611a52acf6dfa1df7ebf867bc7e2f" id="r_ga6dc611a52acf6dfa1df7ebf867bc7e2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6dc611a52acf6dfa1df7ebf867bc7e2f">CAN_F4R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga613094782d73b0e3e5272eff72f04d42">CAN_F4R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga6dc611a52acf6dfa1df7ebf867bc7e2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6329ecd1b3904d370e9db06936fd0f5" id="r_gaa6329ecd1b3904d370e9db06936fd0f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6329ecd1b3904d370e9db06936fd0f5">CAN_F4R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaa6329ecd1b3904d370e9db06936fd0f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07c564a28ae0d2958891d26110e4c411" id="r_ga07c564a28ae0d2958891d26110e4c411"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07c564a28ae0d2958891d26110e4c411">CAN_F4R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6329ecd1b3904d370e9db06936fd0f5">CAN_F4R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga07c564a28ae0d2958891d26110e4c411"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1736bc2808a37aa82358fe1c36c963a6" id="r_ga1736bc2808a37aa82358fe1c36c963a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1736bc2808a37aa82358fe1c36c963a6">CAN_F4R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga07c564a28ae0d2958891d26110e4c411">CAN_F4R1_FB13_Msk</a></td></tr>
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<tr class="separator:ga1736bc2808a37aa82358fe1c36c963a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e223d1503fe560272d3851eef5850e0" id="r_ga2e223d1503fe560272d3851eef5850e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e223d1503fe560272d3851eef5850e0">CAN_F4R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga2e223d1503fe560272d3851eef5850e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c7d95aae3c918a4c446ecd57f876383" id="r_ga3c7d95aae3c918a4c446ecd57f876383"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c7d95aae3c918a4c446ecd57f876383">CAN_F4R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e223d1503fe560272d3851eef5850e0">CAN_F4R1_FB14_Pos</a>)</td></tr>
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<tr class="memitem:ga7d7ec466bbf196a41f6da2a7b506675d" id="r_ga7d7ec466bbf196a41f6da2a7b506675d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d7ec466bbf196a41f6da2a7b506675d">CAN_F4R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c7d95aae3c918a4c446ecd57f876383">CAN_F4R1_FB14_Msk</a></td></tr>
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<tr class="separator:ga7d7ec466bbf196a41f6da2a7b506675d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga801c05f9333d89c49f62aca3b77152c1" id="r_ga801c05f9333d89c49f62aca3b77152c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga801c05f9333d89c49f62aca3b77152c1">CAN_F4R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="memitem:gaf226c102853cbf2918931586573641bf" id="r_gaf226c102853cbf2918931586573641bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf226c102853cbf2918931586573641bf">CAN_F4R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga801c05f9333d89c49f62aca3b77152c1">CAN_F4R1_FB15_Pos</a>)</td></tr>
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<tr class="memitem:gad30ff7e7b0c0f7e56821ecbcd6fcc23c" id="r_gad30ff7e7b0c0f7e56821ecbcd6fcc23c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad30ff7e7b0c0f7e56821ecbcd6fcc23c">CAN_F4R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf226c102853cbf2918931586573641bf">CAN_F4R1_FB15_Msk</a></td></tr>
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<tr class="separator:gad30ff7e7b0c0f7e56821ecbcd6fcc23c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9961594daf8302213f375760ba658031" id="r_ga9961594daf8302213f375760ba658031"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9961594daf8302213f375760ba658031">CAN_F4R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga9961594daf8302213f375760ba658031"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5885429c36cad6e1bae78efccc6f4c59" id="r_ga5885429c36cad6e1bae78efccc6f4c59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5885429c36cad6e1bae78efccc6f4c59">CAN_F4R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9961594daf8302213f375760ba658031">CAN_F4R1_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga5885429c36cad6e1bae78efccc6f4c59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga199bd29b6f3ff56150a9dcd71c8ea13f" id="r_ga199bd29b6f3ff56150a9dcd71c8ea13f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga199bd29b6f3ff56150a9dcd71c8ea13f">CAN_F4R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5885429c36cad6e1bae78efccc6f4c59">CAN_F4R1_FB16_Msk</a></td></tr>
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<tr class="separator:ga199bd29b6f3ff56150a9dcd71c8ea13f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b0f6c8b0cd3bedcb4d900b936cb1206" id="r_ga9b0f6c8b0cd3bedcb4d900b936cb1206"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b0f6c8b0cd3bedcb4d900b936cb1206">CAN_F4R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga9b0f6c8b0cd3bedcb4d900b936cb1206"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa31c54bcaf590c65c626253362949c8" id="r_gafa31c54bcaf590c65c626253362949c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa31c54bcaf590c65c626253362949c8">CAN_F4R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b0f6c8b0cd3bedcb4d900b936cb1206">CAN_F4R1_FB17_Pos</a>)</td></tr>
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<tr class="separator:gafa31c54bcaf590c65c626253362949c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga893837534cbc7a043fa995de4619e2da" id="r_ga893837534cbc7a043fa995de4619e2da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga893837534cbc7a043fa995de4619e2da">CAN_F4R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafa31c54bcaf590c65c626253362949c8">CAN_F4R1_FB17_Msk</a></td></tr>
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<tr class="separator:ga893837534cbc7a043fa995de4619e2da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga618cffe573cd6ccff53130f3beb6bfcb" id="r_ga618cffe573cd6ccff53130f3beb6bfcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga618cffe573cd6ccff53130f3beb6bfcb">CAN_F4R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga618cffe573cd6ccff53130f3beb6bfcb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d6925aa9feee56fba36b3a4e399c2d8" id="r_ga6d6925aa9feee56fba36b3a4e399c2d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d6925aa9feee56fba36b3a4e399c2d8">CAN_F4R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga618cffe573cd6ccff53130f3beb6bfcb">CAN_F4R1_FB18_Pos</a>)</td></tr>
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<tr class="separator:ga6d6925aa9feee56fba36b3a4e399c2d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga551e80c41958417cbcf1d0c53e4947a3" id="r_ga551e80c41958417cbcf1d0c53e4947a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga551e80c41958417cbcf1d0c53e4947a3">CAN_F4R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d6925aa9feee56fba36b3a4e399c2d8">CAN_F4R1_FB18_Msk</a></td></tr>
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<tr class="separator:ga551e80c41958417cbcf1d0c53e4947a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe302668b9837570409f0e5dafca0480" id="r_gafe302668b9837570409f0e5dafca0480"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe302668b9837570409f0e5dafca0480">CAN_F4R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:gafe302668b9837570409f0e5dafca0480"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebb1f9e546b4c8bb2bcb3d6e9a1f0949" id="r_gaebb1f9e546b4c8bb2bcb3d6e9a1f0949"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebb1f9e546b4c8bb2bcb3d6e9a1f0949">CAN_F4R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafe302668b9837570409f0e5dafca0480">CAN_F4R1_FB19_Pos</a>)</td></tr>
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<tr class="separator:gaebb1f9e546b4c8bb2bcb3d6e9a1f0949"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80d9a946bd39dae4b0a862cf21f262ed" id="r_ga80d9a946bd39dae4b0a862cf21f262ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80d9a946bd39dae4b0a862cf21f262ed">CAN_F4R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaebb1f9e546b4c8bb2bcb3d6e9a1f0949">CAN_F4R1_FB19_Msk</a></td></tr>
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<tr class="separator:ga80d9a946bd39dae4b0a862cf21f262ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27b7d0c5f497cf6c9bc7e7fa16eccfd9" id="r_ga27b7d0c5f497cf6c9bc7e7fa16eccfd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27b7d0c5f497cf6c9bc7e7fa16eccfd9">CAN_F4R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga27b7d0c5f497cf6c9bc7e7fa16eccfd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga119fbe324a31a61a0b5aa989658cf15d" id="r_ga119fbe324a31a61a0b5aa989658cf15d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga119fbe324a31a61a0b5aa989658cf15d">CAN_F4R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27b7d0c5f497cf6c9bc7e7fa16eccfd9">CAN_F4R1_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga119fbe324a31a61a0b5aa989658cf15d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5646609987ce174cf3b94bb4538172f4" id="r_ga5646609987ce174cf3b94bb4538172f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5646609987ce174cf3b94bb4538172f4">CAN_F4R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga119fbe324a31a61a0b5aa989658cf15d">CAN_F4R1_FB20_Msk</a></td></tr>
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<tr class="separator:ga5646609987ce174cf3b94bb4538172f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec476098d3c0d9c6025f6a2bd35a7f9b" id="r_gaec476098d3c0d9c6025f6a2bd35a7f9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec476098d3c0d9c6025f6a2bd35a7f9b">CAN_F4R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gaec476098d3c0d9c6025f6a2bd35a7f9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa57165c0d07048b0024f56e0febdaccd" id="r_gaa57165c0d07048b0024f56e0febdaccd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa57165c0d07048b0024f56e0febdaccd">CAN_F4R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaec476098d3c0d9c6025f6a2bd35a7f9b">CAN_F4R1_FB21_Pos</a>)</td></tr>
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<tr class="separator:gaa57165c0d07048b0024f56e0febdaccd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga356faa77de97c61e9b5f6b763173a987" id="r_ga356faa77de97c61e9b5f6b763173a987"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga356faa77de97c61e9b5f6b763173a987">CAN_F4R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa57165c0d07048b0024f56e0febdaccd">CAN_F4R1_FB21_Msk</a></td></tr>
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<tr class="separator:ga356faa77de97c61e9b5f6b763173a987"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd5edc6ee520a4896e71f9613676f744" id="r_gadd5edc6ee520a4896e71f9613676f744"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd5edc6ee520a4896e71f9613676f744">CAN_F4R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gadd5edc6ee520a4896e71f9613676f744"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91bdc8395c27e8e23092b3f9784b7994" id="r_ga91bdc8395c27e8e23092b3f9784b7994"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91bdc8395c27e8e23092b3f9784b7994">CAN_F4R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadd5edc6ee520a4896e71f9613676f744">CAN_F4R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga91bdc8395c27e8e23092b3f9784b7994"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6b246b3df35cc1db06e8c809137562f" id="r_gac6b246b3df35cc1db06e8c809137562f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6b246b3df35cc1db06e8c809137562f">CAN_F4R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga91bdc8395c27e8e23092b3f9784b7994">CAN_F4R1_FB22_Msk</a></td></tr>
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<tr class="separator:gac6b246b3df35cc1db06e8c809137562f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb9a14d13a2ce6fb41594c8ebc9d1a62" id="r_gabb9a14d13a2ce6fb41594c8ebc9d1a62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb9a14d13a2ce6fb41594c8ebc9d1a62">CAN_F4R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gabb9a14d13a2ce6fb41594c8ebc9d1a62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac32276ab0a34c8ae46eee73ad1f208d7" id="r_gac32276ab0a34c8ae46eee73ad1f208d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac32276ab0a34c8ae46eee73ad1f208d7">CAN_F4R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb9a14d13a2ce6fb41594c8ebc9d1a62">CAN_F4R1_FB23_Pos</a>)</td></tr>
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<tr class="separator:gac32276ab0a34c8ae46eee73ad1f208d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4882da3ee5be3aed3d5eb46923859674" id="r_ga4882da3ee5be3aed3d5eb46923859674"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4882da3ee5be3aed3d5eb46923859674">CAN_F4R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac32276ab0a34c8ae46eee73ad1f208d7">CAN_F4R1_FB23_Msk</a></td></tr>
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<tr class="separator:ga4882da3ee5be3aed3d5eb46923859674"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5666249f8189bddecf0c24687fb8e1a" id="r_gae5666249f8189bddecf0c24687fb8e1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5666249f8189bddecf0c24687fb8e1a">CAN_F4R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:gae5666249f8189bddecf0c24687fb8e1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e1033412ffe01f17f87d0287af5bd70" id="r_ga4e1033412ffe01f17f87d0287af5bd70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e1033412ffe01f17f87d0287af5bd70">CAN_F4R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5666249f8189bddecf0c24687fb8e1a">CAN_F4R1_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga4e1033412ffe01f17f87d0287af5bd70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e178aa8c6f98a866aaae511b9da86c8" id="r_ga1e178aa8c6f98a866aaae511b9da86c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e178aa8c6f98a866aaae511b9da86c8">CAN_F4R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e1033412ffe01f17f87d0287af5bd70">CAN_F4R1_FB24_Msk</a></td></tr>
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<tr class="separator:ga1e178aa8c6f98a866aaae511b9da86c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6aedd4cfb249867dc58b58f6f4cbedbb" id="r_ga6aedd4cfb249867dc58b58f6f4cbedbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6aedd4cfb249867dc58b58f6f4cbedbb">CAN_F4R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga6aedd4cfb249867dc58b58f6f4cbedbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d8fcea6cb9dd0d6240208ed38acecdc" id="r_ga9d8fcea6cb9dd0d6240208ed38acecdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d8fcea6cb9dd0d6240208ed38acecdc">CAN_F4R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6aedd4cfb249867dc58b58f6f4cbedbb">CAN_F4R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga9d8fcea6cb9dd0d6240208ed38acecdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a5ca327060530761d71362d39b2d364" id="r_ga9a5ca327060530761d71362d39b2d364"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a5ca327060530761d71362d39b2d364">CAN_F4R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d8fcea6cb9dd0d6240208ed38acecdc">CAN_F4R1_FB25_Msk</a></td></tr>
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<tr class="separator:ga9a5ca327060530761d71362d39b2d364"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e69fe695c9a2aa5f7ebf5f8674022bd" id="r_ga2e69fe695c9a2aa5f7ebf5f8674022bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e69fe695c9a2aa5f7ebf5f8674022bd">CAN_F4R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga2e69fe695c9a2aa5f7ebf5f8674022bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2abd932d950db3d7aafbb9af2639a57" id="r_gae2abd932d950db3d7aafbb9af2639a57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2abd932d950db3d7aafbb9af2639a57">CAN_F4R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e69fe695c9a2aa5f7ebf5f8674022bd">CAN_F4R1_FB26_Pos</a>)</td></tr>
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<tr class="separator:gae2abd932d950db3d7aafbb9af2639a57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeabe4836aed74af4adba72b2c7684a6e" id="r_gaeabe4836aed74af4adba72b2c7684a6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeabe4836aed74af4adba72b2c7684a6e">CAN_F4R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae2abd932d950db3d7aafbb9af2639a57">CAN_F4R1_FB26_Msk</a></td></tr>
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<tr class="separator:gaeabe4836aed74af4adba72b2c7684a6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae89e6768b343f3cf2702266b2832ecdc" id="r_gae89e6768b343f3cf2702266b2832ecdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae89e6768b343f3cf2702266b2832ecdc">CAN_F4R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:gae89e6768b343f3cf2702266b2832ecdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac34b9b4abc8d9196ce7aab200c99787c" id="r_gac34b9b4abc8d9196ce7aab200c99787c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac34b9b4abc8d9196ce7aab200c99787c">CAN_F4R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae89e6768b343f3cf2702266b2832ecdc">CAN_F4R1_FB27_Pos</a>)</td></tr>
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<tr class="separator:gac34b9b4abc8d9196ce7aab200c99787c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa8e7d74919e74723f7df71357cc994a" id="r_gaaa8e7d74919e74723f7df71357cc994a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa8e7d74919e74723f7df71357cc994a">CAN_F4R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac34b9b4abc8d9196ce7aab200c99787c">CAN_F4R1_FB27_Msk</a></td></tr>
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<tr class="separator:gaaa8e7d74919e74723f7df71357cc994a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06a31d8ddb814f830f830b8831821bc4" id="r_ga06a31d8ddb814f830f830b8831821bc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06a31d8ddb814f830f830b8831821bc4">CAN_F4R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga06a31d8ddb814f830f830b8831821bc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga008f59ed84fb846c36803d37e52c09d0" id="r_ga008f59ed84fb846c36803d37e52c09d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga008f59ed84fb846c36803d37e52c09d0">CAN_F4R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga06a31d8ddb814f830f830b8831821bc4">CAN_F4R1_FB28_Pos</a>)</td></tr>
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<tr class="separator:ga008f59ed84fb846c36803d37e52c09d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e2b2b9bd5b397e58d57fb379546110b" id="r_ga6e2b2b9bd5b397e58d57fb379546110b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e2b2b9bd5b397e58d57fb379546110b">CAN_F4R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga008f59ed84fb846c36803d37e52c09d0">CAN_F4R1_FB28_Msk</a></td></tr>
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<tr class="separator:ga6e2b2b9bd5b397e58d57fb379546110b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6fcd8e8ee759e498a068f300ebd67923" id="r_ga6fcd8e8ee759e498a068f300ebd67923"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fcd8e8ee759e498a068f300ebd67923">CAN_F4R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga6fcd8e8ee759e498a068f300ebd67923"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd6c2fc9688b65bda0ca6b9e18e0c072" id="r_gacd6c2fc9688b65bda0ca6b9e18e0c072"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd6c2fc9688b65bda0ca6b9e18e0c072">CAN_F4R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6fcd8e8ee759e498a068f300ebd67923">CAN_F4R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:gacd6c2fc9688b65bda0ca6b9e18e0c072"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb165ede225dc35a825647e5efcab437" id="r_gaeb165ede225dc35a825647e5efcab437"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb165ede225dc35a825647e5efcab437">CAN_F4R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacd6c2fc9688b65bda0ca6b9e18e0c072">CAN_F4R1_FB29_Msk</a></td></tr>
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<tr class="separator:gaeb165ede225dc35a825647e5efcab437"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga905946914d80198f6e0ecc939097904d" id="r_ga905946914d80198f6e0ecc939097904d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga905946914d80198f6e0ecc939097904d">CAN_F4R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga905946914d80198f6e0ecc939097904d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2012557ac8ac7ddd510c1dd771062dc2" id="r_ga2012557ac8ac7ddd510c1dd771062dc2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2012557ac8ac7ddd510c1dd771062dc2">CAN_F4R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga905946914d80198f6e0ecc939097904d">CAN_F4R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga2012557ac8ac7ddd510c1dd771062dc2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7898b1f422424fd7fc0896b908748e7c" id="r_ga7898b1f422424fd7fc0896b908748e7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7898b1f422424fd7fc0896b908748e7c">CAN_F4R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2012557ac8ac7ddd510c1dd771062dc2">CAN_F4R1_FB30_Msk</a></td></tr>
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<tr class="separator:ga7898b1f422424fd7fc0896b908748e7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1788952bedbeb5ee6a7aff15180cdd85" id="r_ga1788952bedbeb5ee6a7aff15180cdd85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1788952bedbeb5ee6a7aff15180cdd85">CAN_F4R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga1788952bedbeb5ee6a7aff15180cdd85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe91e1b46bc8af15c5d727b81e51bfdb" id="r_gafe91e1b46bc8af15c5d727b81e51bfdb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe91e1b46bc8af15c5d727b81e51bfdb">CAN_F4R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1788952bedbeb5ee6a7aff15180cdd85">CAN_F4R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:gafe91e1b46bc8af15c5d727b81e51bfdb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92d7e6a44e87911e9cc14f6bff854fa2" id="r_ga92d7e6a44e87911e9cc14f6bff854fa2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92d7e6a44e87911e9cc14f6bff854fa2">CAN_F4R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafe91e1b46bc8af15c5d727b81e51bfdb">CAN_F4R1_FB31_Msk</a></td></tr>
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<tr class="separator:ga92d7e6a44e87911e9cc14f6bff854fa2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d79dff94ff5fac00e5f6a357e44f85e" id="r_ga6d79dff94ff5fac00e5f6a357e44f85e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d79dff94ff5fac00e5f6a357e44f85e">CAN_F5R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga6d79dff94ff5fac00e5f6a357e44f85e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18f8312b10016a8ad987ceaa48f7a67f" id="r_ga18f8312b10016a8ad987ceaa48f7a67f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18f8312b10016a8ad987ceaa48f7a67f">CAN_F5R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d79dff94ff5fac00e5f6a357e44f85e">CAN_F5R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga18f8312b10016a8ad987ceaa48f7a67f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cdf98e317662e286ad2a3344ee516df" id="r_ga5cdf98e317662e286ad2a3344ee516df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5cdf98e317662e286ad2a3344ee516df">CAN_F5R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga18f8312b10016a8ad987ceaa48f7a67f">CAN_F5R1_FB0_Msk</a></td></tr>
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<tr class="separator:ga5cdf98e317662e286ad2a3344ee516df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a8d5c8f4366ceabcfe2f90c570bb475" id="r_ga0a8d5c8f4366ceabcfe2f90c570bb475"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a8d5c8f4366ceabcfe2f90c570bb475">CAN_F5R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga0a8d5c8f4366ceabcfe2f90c570bb475"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4421f59236d1bd77fadc2e093c988466" id="r_ga4421f59236d1bd77fadc2e093c988466"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4421f59236d1bd77fadc2e093c988466">CAN_F5R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a8d5c8f4366ceabcfe2f90c570bb475">CAN_F5R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga4421f59236d1bd77fadc2e093c988466"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac814c424ed2ccc11645da6e62f3fb81" id="r_gaac814c424ed2ccc11645da6e62f3fb81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac814c424ed2ccc11645da6e62f3fb81">CAN_F5R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4421f59236d1bd77fadc2e093c988466">CAN_F5R1_FB1_Msk</a></td></tr>
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<tr class="separator:gaac814c424ed2ccc11645da6e62f3fb81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95b23df31b5f7c3556c2702e20c923d6" id="r_ga95b23df31b5f7c3556c2702e20c923d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95b23df31b5f7c3556c2702e20c923d6">CAN_F5R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga95b23df31b5f7c3556c2702e20c923d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39beb5641b129903d6d43a152b9b1fc2" id="r_ga39beb5641b129903d6d43a152b9b1fc2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39beb5641b129903d6d43a152b9b1fc2">CAN_F5R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga95b23df31b5f7c3556c2702e20c923d6">CAN_F5R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga39beb5641b129903d6d43a152b9b1fc2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b0af1936dd43bd319614e3298fd28d1" id="r_ga4b0af1936dd43bd319614e3298fd28d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b0af1936dd43bd319614e3298fd28d1">CAN_F5R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga39beb5641b129903d6d43a152b9b1fc2">CAN_F5R1_FB2_Msk</a></td></tr>
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<tr class="separator:ga4b0af1936dd43bd319614e3298fd28d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabca05592268e423c5ebe595aa0b66bab" id="r_gabca05592268e423c5ebe595aa0b66bab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabca05592268e423c5ebe595aa0b66bab">CAN_F5R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gabca05592268e423c5ebe595aa0b66bab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c30456c58159fc9c8b5fc705a897c4b" id="r_ga8c30456c58159fc9c8b5fc705a897c4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c30456c58159fc9c8b5fc705a897c4b">CAN_F5R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabca05592268e423c5ebe595aa0b66bab">CAN_F5R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga8c30456c58159fc9c8b5fc705a897c4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga013f84e3f3f0e148d3a9a071ccbf6738" id="r_ga013f84e3f3f0e148d3a9a071ccbf6738"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga013f84e3f3f0e148d3a9a071ccbf6738">CAN_F5R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c30456c58159fc9c8b5fc705a897c4b">CAN_F5R1_FB3_Msk</a></td></tr>
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<tr class="separator:ga013f84e3f3f0e148d3a9a071ccbf6738"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c9a7e1161697ffdc810058033c3c915" id="r_ga3c9a7e1161697ffdc810058033c3c915"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c9a7e1161697ffdc810058033c3c915">CAN_F5R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga3c9a7e1161697ffdc810058033c3c915"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaecdbb3ad483c253075f585fb453e6fb8" id="r_gaecdbb3ad483c253075f585fb453e6fb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecdbb3ad483c253075f585fb453e6fb8">CAN_F5R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c9a7e1161697ffdc810058033c3c915">CAN_F5R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:gaecdbb3ad483c253075f585fb453e6fb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cfc330921811d76ed6476d6935e84e7" id="r_ga7cfc330921811d76ed6476d6935e84e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cfc330921811d76ed6476d6935e84e7">CAN_F5R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaecdbb3ad483c253075f585fb453e6fb8">CAN_F5R1_FB4_Msk</a></td></tr>
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<tr class="separator:ga7cfc330921811d76ed6476d6935e84e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7703402af1cdf92f4711ced3fc67c1ca" id="r_ga7703402af1cdf92f4711ced3fc67c1ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7703402af1cdf92f4711ced3fc67c1ca">CAN_F5R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga7703402af1cdf92f4711ced3fc67c1ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa323c7e6521417879450a4d5996e256" id="r_gafa323c7e6521417879450a4d5996e256"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa323c7e6521417879450a4d5996e256">CAN_F5R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7703402af1cdf92f4711ced3fc67c1ca">CAN_F5R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:gafa323c7e6521417879450a4d5996e256"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9aebaa8e61198240c1564ce73acb1d2" id="r_gaf9aebaa8e61198240c1564ce73acb1d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9aebaa8e61198240c1564ce73acb1d2">CAN_F5R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafa323c7e6521417879450a4d5996e256">CAN_F5R1_FB5_Msk</a></td></tr>
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<tr class="separator:gaf9aebaa8e61198240c1564ce73acb1d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga256f07a9ee561dfc60a6a3f75d9802e9" id="r_ga256f07a9ee561dfc60a6a3f75d9802e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga256f07a9ee561dfc60a6a3f75d9802e9">CAN_F5R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga256f07a9ee561dfc60a6a3f75d9802e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7e09b9fe8aeb61f4253d15d6bd808f0" id="r_gaa7e09b9fe8aeb61f4253d15d6bd808f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e09b9fe8aeb61f4253d15d6bd808f0">CAN_F5R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga256f07a9ee561dfc60a6a3f75d9802e9">CAN_F5R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:gaa7e09b9fe8aeb61f4253d15d6bd808f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadea331fb6273fda80a8f5a3dc8eaf6f4" id="r_gadea331fb6273fda80a8f5a3dc8eaf6f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadea331fb6273fda80a8f5a3dc8eaf6f4">CAN_F5R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e09b9fe8aeb61f4253d15d6bd808f0">CAN_F5R1_FB6_Msk</a></td></tr>
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<tr class="separator:gadea331fb6273fda80a8f5a3dc8eaf6f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f5bf9e5ed786525dbe37eda02710a47" id="r_ga6f5bf9e5ed786525dbe37eda02710a47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f5bf9e5ed786525dbe37eda02710a47">CAN_F5R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga6f5bf9e5ed786525dbe37eda02710a47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8ddbee4662088695a19791d9754f060" id="r_gaa8ddbee4662088695a19791d9754f060"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8ddbee4662088695a19791d9754f060">CAN_F5R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f5bf9e5ed786525dbe37eda02710a47">CAN_F5R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:gaa8ddbee4662088695a19791d9754f060"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc7dfaacfba6a42a17b16281f690f952" id="r_gafc7dfaacfba6a42a17b16281f690f952"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc7dfaacfba6a42a17b16281f690f952">CAN_F5R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8ddbee4662088695a19791d9754f060">CAN_F5R1_FB7_Msk</a></td></tr>
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<tr class="separator:gafc7dfaacfba6a42a17b16281f690f952"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d5f9ec2683178e836dabd60294ed4b5" id="r_ga4d5f9ec2683178e836dabd60294ed4b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d5f9ec2683178e836dabd60294ed4b5">CAN_F5R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga4d5f9ec2683178e836dabd60294ed4b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b80299e85591ee7bb2669dfbd7beced" id="r_ga3b80299e85591ee7bb2669dfbd7beced"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b80299e85591ee7bb2669dfbd7beced">CAN_F5R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d5f9ec2683178e836dabd60294ed4b5">CAN_F5R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga3b80299e85591ee7bb2669dfbd7beced"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba0938e0f55773406fd59c2a0bd7c46e" id="r_gaba0938e0f55773406fd59c2a0bd7c46e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba0938e0f55773406fd59c2a0bd7c46e">CAN_F5R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b80299e85591ee7bb2669dfbd7beced">CAN_F5R1_FB8_Msk</a></td></tr>
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<tr class="separator:gaba0938e0f55773406fd59c2a0bd7c46e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefafeaebf2f2d7db4ec1c34ab58b7d0d" id="r_gaefafeaebf2f2d7db4ec1c34ab58b7d0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefafeaebf2f2d7db4ec1c34ab58b7d0d">CAN_F5R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaefafeaebf2f2d7db4ec1c34ab58b7d0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad909d1a8817b8daf42ad0ebd18551ae8" id="r_gad909d1a8817b8daf42ad0ebd18551ae8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad909d1a8817b8daf42ad0ebd18551ae8">CAN_F5R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaefafeaebf2f2d7db4ec1c34ab58b7d0d">CAN_F5R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:gad909d1a8817b8daf42ad0ebd18551ae8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9715c4445159d0068172309092e574e3" id="r_ga9715c4445159d0068172309092e574e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9715c4445159d0068172309092e574e3">CAN_F5R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad909d1a8817b8daf42ad0ebd18551ae8">CAN_F5R1_FB9_Msk</a></td></tr>
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<tr class="separator:ga9715c4445159d0068172309092e574e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d808208c09dd6604510d037d65d804a" id="r_ga0d808208c09dd6604510d037d65d804a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d808208c09dd6604510d037d65d804a">CAN_F5R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga0d808208c09dd6604510d037d65d804a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1eba02afe3b8e8f8eebaa38b8499604c" id="r_ga1eba02afe3b8e8f8eebaa38b8499604c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1eba02afe3b8e8f8eebaa38b8499604c">CAN_F5R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d808208c09dd6604510d037d65d804a">CAN_F5R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga1eba02afe3b8e8f8eebaa38b8499604c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7de15e73395473569a447023dae53c4" id="r_gae7de15e73395473569a447023dae53c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7de15e73395473569a447023dae53c4">CAN_F5R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1eba02afe3b8e8f8eebaa38b8499604c">CAN_F5R1_FB10_Msk</a></td></tr>
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<tr class="separator:gae7de15e73395473569a447023dae53c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8551f14a24c6f6dabb131b9e817a013e" id="r_ga8551f14a24c6f6dabb131b9e817a013e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8551f14a24c6f6dabb131b9e817a013e">CAN_F5R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga8551f14a24c6f6dabb131b9e817a013e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae735eeb78cc75daa1870ea4d2141e40e" id="r_gae735eeb78cc75daa1870ea4d2141e40e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae735eeb78cc75daa1870ea4d2141e40e">CAN_F5R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8551f14a24c6f6dabb131b9e817a013e">CAN_F5R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:gae735eeb78cc75daa1870ea4d2141e40e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39b60e0befdf681694bc4123b4b7f7bd" id="r_ga39b60e0befdf681694bc4123b4b7f7bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39b60e0befdf681694bc4123b4b7f7bd">CAN_F5R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae735eeb78cc75daa1870ea4d2141e40e">CAN_F5R1_FB11_Msk</a></td></tr>
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<tr class="separator:ga39b60e0befdf681694bc4123b4b7f7bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c27662a1518dfbd5d0217709864fc8c" id="r_ga4c27662a1518dfbd5d0217709864fc8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c27662a1518dfbd5d0217709864fc8c">CAN_F5R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga4c27662a1518dfbd5d0217709864fc8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa57169fb0310c42945b03d791c2f54b" id="r_gafa57169fb0310c42945b03d791c2f54b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa57169fb0310c42945b03d791c2f54b">CAN_F5R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c27662a1518dfbd5d0217709864fc8c">CAN_F5R1_FB12_Pos</a>)</td></tr>
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<tr class="memitem:ga0bc4598d0d603c802b7140f967d84e5c" id="r_ga0bc4598d0d603c802b7140f967d84e5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bc4598d0d603c802b7140f967d84e5c">CAN_F5R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafa57169fb0310c42945b03d791c2f54b">CAN_F5R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga0bc4598d0d603c802b7140f967d84e5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7b7acc6d79a2decd37c40676d6a2aa7" id="r_gab7b7acc6d79a2decd37c40676d6a2aa7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7b7acc6d79a2decd37c40676d6a2aa7">CAN_F5R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gab7b7acc6d79a2decd37c40676d6a2aa7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65f520a74c377435d6bbbaf002bd72bf" id="r_ga65f520a74c377435d6bbbaf002bd72bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65f520a74c377435d6bbbaf002bd72bf">CAN_F5R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab7b7acc6d79a2decd37c40676d6a2aa7">CAN_F5R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga65f520a74c377435d6bbbaf002bd72bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8b4439ac4bc79ff74d21060ff533b12" id="r_gac8b4439ac4bc79ff74d21060ff533b12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8b4439ac4bc79ff74d21060ff533b12">CAN_F5R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65f520a74c377435d6bbbaf002bd72bf">CAN_F5R1_FB13_Msk</a></td></tr>
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<tr class="separator:gac8b4439ac4bc79ff74d21060ff533b12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37ae18d19c8de2e1d7700aa436fbf0bb" id="r_ga37ae18d19c8de2e1d7700aa436fbf0bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37ae18d19c8de2e1d7700aa436fbf0bb">CAN_F5R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga37ae18d19c8de2e1d7700aa436fbf0bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35a677ded1b04b0ba090b33e4558f658" id="r_ga35a677ded1b04b0ba090b33e4558f658"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35a677ded1b04b0ba090b33e4558f658">CAN_F5R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga37ae18d19c8de2e1d7700aa436fbf0bb">CAN_F5R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:ga35a677ded1b04b0ba090b33e4558f658"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d117ee64d9c1673f22f12f24bd481a4" id="r_ga0d117ee64d9c1673f22f12f24bd481a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d117ee64d9c1673f22f12f24bd481a4">CAN_F5R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga35a677ded1b04b0ba090b33e4558f658">CAN_F5R1_FB14_Msk</a></td></tr>
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<tr class="separator:ga0d117ee64d9c1673f22f12f24bd481a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fb993ec1c88ae403c53a086db275ac2" id="r_ga5fb993ec1c88ae403c53a086db275ac2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fb993ec1c88ae403c53a086db275ac2">CAN_F5R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga5fb993ec1c88ae403c53a086db275ac2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfe4d49efd13e228ed872dbe7f8b5a6c" id="r_gacfe4d49efd13e228ed872dbe7f8b5a6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfe4d49efd13e228ed872dbe7f8b5a6c">CAN_F5R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fb993ec1c88ae403c53a086db275ac2">CAN_F5R1_FB15_Pos</a>)</td></tr>
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<tr class="separator:gacfe4d49efd13e228ed872dbe7f8b5a6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf761c448bf29c4d93f4c2a75981fa049" id="r_gaf761c448bf29c4d93f4c2a75981fa049"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf761c448bf29c4d93f4c2a75981fa049">CAN_F5R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacfe4d49efd13e228ed872dbe7f8b5a6c">CAN_F5R1_FB15_Msk</a></td></tr>
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<tr class="separator:gaf761c448bf29c4d93f4c2a75981fa049"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga092e685d17984f38bb1a88432ffc54ee" id="r_ga092e685d17984f38bb1a88432ffc54ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga092e685d17984f38bb1a88432ffc54ee">CAN_F5R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga092e685d17984f38bb1a88432ffc54ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6533312fc17838e6d13acb30b3920cb6" id="r_ga6533312fc17838e6d13acb30b3920cb6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6533312fc17838e6d13acb30b3920cb6">CAN_F5R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga092e685d17984f38bb1a88432ffc54ee">CAN_F5R1_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga6533312fc17838e6d13acb30b3920cb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87543e5b7c48580ca9925402ab6ca5a7" id="r_ga87543e5b7c48580ca9925402ab6ca5a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87543e5b7c48580ca9925402ab6ca5a7">CAN_F5R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6533312fc17838e6d13acb30b3920cb6">CAN_F5R1_FB16_Msk</a></td></tr>
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<tr class="separator:ga87543e5b7c48580ca9925402ab6ca5a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac82d98dee909d969dc96f564795027e2" id="r_gac82d98dee909d969dc96f564795027e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac82d98dee909d969dc96f564795027e2">CAN_F5R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gac82d98dee909d969dc96f564795027e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6f582e0d54bfd7467f6feed9834672a" id="r_gac6f582e0d54bfd7467f6feed9834672a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6f582e0d54bfd7467f6feed9834672a">CAN_F5R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac82d98dee909d969dc96f564795027e2">CAN_F5R1_FB17_Pos</a>)</td></tr>
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<tr class="separator:gac6f582e0d54bfd7467f6feed9834672a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b9c39ec4649cd68a540c88c3c64d506" id="r_ga9b9c39ec4649cd68a540c88c3c64d506"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b9c39ec4649cd68a540c88c3c64d506">CAN_F5R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac6f582e0d54bfd7467f6feed9834672a">CAN_F5R1_FB17_Msk</a></td></tr>
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<tr class="separator:ga9b9c39ec4649cd68a540c88c3c64d506"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52662c9e857187de4de1d65d6951bc7a" id="r_ga52662c9e857187de4de1d65d6951bc7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52662c9e857187de4de1d65d6951bc7a">CAN_F5R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga52662c9e857187de4de1d65d6951bc7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga241cc69a215db80ad1e1028462f05400" id="r_ga241cc69a215db80ad1e1028462f05400"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga241cc69a215db80ad1e1028462f05400">CAN_F5R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52662c9e857187de4de1d65d6951bc7a">CAN_F5R1_FB18_Pos</a>)</td></tr>
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<tr class="separator:ga241cc69a215db80ad1e1028462f05400"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4992301536d388de215273769708b843" id="r_ga4992301536d388de215273769708b843"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4992301536d388de215273769708b843">CAN_F5R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga241cc69a215db80ad1e1028462f05400">CAN_F5R1_FB18_Msk</a></td></tr>
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<tr class="separator:ga4992301536d388de215273769708b843"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c0a5a14d7c4b76f8e6682dd9ef5956f" id="r_ga3c0a5a14d7c4b76f8e6682dd9ef5956f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c0a5a14d7c4b76f8e6682dd9ef5956f">CAN_F5R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga3c0a5a14d7c4b76f8e6682dd9ef5956f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ce1dc2e2a4b715e83aeee7419bb9640" id="r_ga1ce1dc2e2a4b715e83aeee7419bb9640"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ce1dc2e2a4b715e83aeee7419bb9640">CAN_F5R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c0a5a14d7c4b76f8e6682dd9ef5956f">CAN_F5R1_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga1ce1dc2e2a4b715e83aeee7419bb9640"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab21c0b793d7aff03497a95d5c6528ab2" id="r_gab21c0b793d7aff03497a95d5c6528ab2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab21c0b793d7aff03497a95d5c6528ab2">CAN_F5R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ce1dc2e2a4b715e83aeee7419bb9640">CAN_F5R1_FB19_Msk</a></td></tr>
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<tr class="separator:gab21c0b793d7aff03497a95d5c6528ab2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab743a0f6dd5ac3c4bac9a036b29081ef" id="r_gab743a0f6dd5ac3c4bac9a036b29081ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab743a0f6dd5ac3c4bac9a036b29081ef">CAN_F5R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gab743a0f6dd5ac3c4bac9a036b29081ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0c7bd885ecb532509cd74d87eef62dc" id="r_gaf0c7bd885ecb532509cd74d87eef62dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0c7bd885ecb532509cd74d87eef62dc">CAN_F5R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab743a0f6dd5ac3c4bac9a036b29081ef">CAN_F5R1_FB20_Pos</a>)</td></tr>
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<tr class="separator:gaf0c7bd885ecb532509cd74d87eef62dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1c4c5d06a9da5f853aaede3470b07f4" id="r_gaf1c4c5d06a9da5f853aaede3470b07f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1c4c5d06a9da5f853aaede3470b07f4">CAN_F5R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0c7bd885ecb532509cd74d87eef62dc">CAN_F5R1_FB20_Msk</a></td></tr>
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<tr class="separator:gaf1c4c5d06a9da5f853aaede3470b07f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe48131ff33f7f9fbc7714c3d8c7bfeb" id="r_gafe48131ff33f7f9fbc7714c3d8c7bfeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe48131ff33f7f9fbc7714c3d8c7bfeb">CAN_F5R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gafe48131ff33f7f9fbc7714c3d8c7bfeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga481485aaa4f39fcdbc5e687452e08cab" id="r_ga481485aaa4f39fcdbc5e687452e08cab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga481485aaa4f39fcdbc5e687452e08cab">CAN_F5R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafe48131ff33f7f9fbc7714c3d8c7bfeb">CAN_F5R1_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga481485aaa4f39fcdbc5e687452e08cab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91214f1f7dbb4b75b0c425624640fd76" id="r_ga91214f1f7dbb4b75b0c425624640fd76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91214f1f7dbb4b75b0c425624640fd76">CAN_F5R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga481485aaa4f39fcdbc5e687452e08cab">CAN_F5R1_FB21_Msk</a></td></tr>
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<tr class="separator:ga91214f1f7dbb4b75b0c425624640fd76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa43bab79ebaba0ef928bdd3a1e63402e" id="r_gaa43bab79ebaba0ef928bdd3a1e63402e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa43bab79ebaba0ef928bdd3a1e63402e">CAN_F5R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gaa43bab79ebaba0ef928bdd3a1e63402e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4629b22e7deeac3e00278086311c7494" id="r_ga4629b22e7deeac3e00278086311c7494"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4629b22e7deeac3e00278086311c7494">CAN_F5R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa43bab79ebaba0ef928bdd3a1e63402e">CAN_F5R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga4629b22e7deeac3e00278086311c7494"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b24151a68c59fe0f3aa15e498fdc739" id="r_ga1b24151a68c59fe0f3aa15e498fdc739"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b24151a68c59fe0f3aa15e498fdc739">CAN_F5R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4629b22e7deeac3e00278086311c7494">CAN_F5R1_FB22_Msk</a></td></tr>
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<tr class="separator:ga1b24151a68c59fe0f3aa15e498fdc739"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga805d068ed5f42588a3cd264fdeaed117" id="r_ga805d068ed5f42588a3cd264fdeaed117"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga805d068ed5f42588a3cd264fdeaed117">CAN_F5R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga805d068ed5f42588a3cd264fdeaed117"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a285e060706ab40c834d30f23584f21" id="r_ga9a285e060706ab40c834d30f23584f21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a285e060706ab40c834d30f23584f21">CAN_F5R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga805d068ed5f42588a3cd264fdeaed117">CAN_F5R1_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga9a285e060706ab40c834d30f23584f21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadea89ef2e5c3dafae174b671c8e083d2" id="r_gadea89ef2e5c3dafae174b671c8e083d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadea89ef2e5c3dafae174b671c8e083d2">CAN_F5R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a285e060706ab40c834d30f23584f21">CAN_F5R1_FB23_Msk</a></td></tr>
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<tr class="separator:gadea89ef2e5c3dafae174b671c8e083d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11e981a2d5ffc5c12b41ee861e7bf776" id="r_ga11e981a2d5ffc5c12b41ee861e7bf776"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11e981a2d5ffc5c12b41ee861e7bf776">CAN_F5R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga11e981a2d5ffc5c12b41ee861e7bf776"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaafb36d512d79bbf393fd07152d0128b3" id="r_gaafb36d512d79bbf393fd07152d0128b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafb36d512d79bbf393fd07152d0128b3">CAN_F5R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11e981a2d5ffc5c12b41ee861e7bf776">CAN_F5R1_FB24_Pos</a>)</td></tr>
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<tr class="separator:gaafb36d512d79bbf393fd07152d0128b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2acccf9ab5708116cd888f2d65da54cc" id="r_ga2acccf9ab5708116cd888f2d65da54cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2acccf9ab5708116cd888f2d65da54cc">CAN_F5R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaafb36d512d79bbf393fd07152d0128b3">CAN_F5R1_FB24_Msk</a></td></tr>
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<tr class="separator:ga2acccf9ab5708116cd888f2d65da54cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37c511b19288ec9ba0732c9aff018656" id="r_ga37c511b19288ec9ba0732c9aff018656"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37c511b19288ec9ba0732c9aff018656">CAN_F5R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga37c511b19288ec9ba0732c9aff018656"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad908c2a3a6d777350aa5a7c926523d4" id="r_gaad908c2a3a6d777350aa5a7c926523d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad908c2a3a6d777350aa5a7c926523d4">CAN_F5R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga37c511b19288ec9ba0732c9aff018656">CAN_F5R1_FB25_Pos</a>)</td></tr>
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<tr class="memitem:ga3c0b9425117a2409b61032a9c746c2b5" id="r_ga3c0b9425117a2409b61032a9c746c2b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c0b9425117a2409b61032a9c746c2b5">CAN_F5R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaad908c2a3a6d777350aa5a7c926523d4">CAN_F5R1_FB25_Msk</a></td></tr>
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<tr class="memitem:gac24657fe7c1ff00ab6b3a5750ba99bd7" id="r_gac24657fe7c1ff00ab6b3a5750ba99bd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac24657fe7c1ff00ab6b3a5750ba99bd7">CAN_F5R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="memitem:gab9d0db33c0e7a81c01f442cd914348b7" id="r_gab9d0db33c0e7a81c01f442cd914348b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9d0db33c0e7a81c01f442cd914348b7">CAN_F5R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac24657fe7c1ff00ab6b3a5750ba99bd7">CAN_F5R1_FB26_Pos</a>)</td></tr>
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<tr class="memitem:ga0a0d31d96e75ea32299e78845f584632" id="r_ga0a0d31d96e75ea32299e78845f584632"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a0d31d96e75ea32299e78845f584632">CAN_F5R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9d0db33c0e7a81c01f442cd914348b7">CAN_F5R1_FB26_Msk</a></td></tr>
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<tr class="separator:ga0a0d31d96e75ea32299e78845f584632"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga840bed18d4fe71ed9e31e9df74daa351" id="r_ga840bed18d4fe71ed9e31e9df74daa351"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga840bed18d4fe71ed9e31e9df74daa351">CAN_F5R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="memitem:gaffa42eeb73609e01712771d123cf5d9b" id="r_gaffa42eeb73609e01712771d123cf5d9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffa42eeb73609e01712771d123cf5d9b">CAN_F5R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga840bed18d4fe71ed9e31e9df74daa351">CAN_F5R1_FB27_Pos</a>)</td></tr>
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<tr class="separator:gaffa42eeb73609e01712771d123cf5d9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade5db4ad8b19580b895356fff66bb6be" id="r_gade5db4ad8b19580b895356fff66bb6be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade5db4ad8b19580b895356fff66bb6be">CAN_F5R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaffa42eeb73609e01712771d123cf5d9b">CAN_F5R1_FB27_Msk</a></td></tr>
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<tr class="separator:gade5db4ad8b19580b895356fff66bb6be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47b688950a4a528471aa72a2fb4ee35b" id="r_ga47b688950a4a528471aa72a2fb4ee35b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47b688950a4a528471aa72a2fb4ee35b">CAN_F5R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga47b688950a4a528471aa72a2fb4ee35b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa88a15489fa10cf7d251f7faa5955ba5" id="r_gaa88a15489fa10cf7d251f7faa5955ba5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa88a15489fa10cf7d251f7faa5955ba5">CAN_F5R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga47b688950a4a528471aa72a2fb4ee35b">CAN_F5R1_FB28_Pos</a>)</td></tr>
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<tr class="memitem:ga4acec834c3eaf55af5e745d6988ddc1e" id="r_ga4acec834c3eaf55af5e745d6988ddc1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4acec834c3eaf55af5e745d6988ddc1e">CAN_F5R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa88a15489fa10cf7d251f7faa5955ba5">CAN_F5R1_FB28_Msk</a></td></tr>
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<tr class="memitem:gabd871efe11f26d251caa7bd258791e5b" id="r_gabd871efe11f26d251caa7bd258791e5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd871efe11f26d251caa7bd258791e5b">CAN_F5R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:gabd871efe11f26d251caa7bd258791e5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c619cf4d0662ee07d2621300d0a22e0" id="r_ga8c619cf4d0662ee07d2621300d0a22e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c619cf4d0662ee07d2621300d0a22e0">CAN_F5R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabd871efe11f26d251caa7bd258791e5b">CAN_F5R1_FB29_Pos</a>)</td></tr>
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<tr class="memitem:ga923a0086ada8e09a9202338b588f27d1" id="r_ga923a0086ada8e09a9202338b588f27d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga923a0086ada8e09a9202338b588f27d1">CAN_F5R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c619cf4d0662ee07d2621300d0a22e0">CAN_F5R1_FB29_Msk</a></td></tr>
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<tr class="memitem:gaa9f1a63c02db020d08a6337a5c35c72c" id="r_gaa9f1a63c02db020d08a6337a5c35c72c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9f1a63c02db020d08a6337a5c35c72c">CAN_F5R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:gaa9f1a63c02db020d08a6337a5c35c72c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad45b2c10d0637cb1279cfdaccd186e11" id="r_gad45b2c10d0637cb1279cfdaccd186e11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad45b2c10d0637cb1279cfdaccd186e11">CAN_F5R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9f1a63c02db020d08a6337a5c35c72c">CAN_F5R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:gad45b2c10d0637cb1279cfdaccd186e11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga840d2b3f751753e9d21b2e23506e6995" id="r_ga840d2b3f751753e9d21b2e23506e6995"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga840d2b3f751753e9d21b2e23506e6995">CAN_F5R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad45b2c10d0637cb1279cfdaccd186e11">CAN_F5R1_FB30_Msk</a></td></tr>
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<tr class="separator:ga840d2b3f751753e9d21b2e23506e6995"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83ac5fc7a98ea52047846b17abbf45f6" id="r_ga83ac5fc7a98ea52047846b17abbf45f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83ac5fc7a98ea52047846b17abbf45f6">CAN_F5R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="memitem:ga3cca1e8863cc27c3c8afb9d7cee55fe5" id="r_ga3cca1e8863cc27c3c8afb9d7cee55fe5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cca1e8863cc27c3c8afb9d7cee55fe5">CAN_F5R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83ac5fc7a98ea52047846b17abbf45f6">CAN_F5R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga3cca1e8863cc27c3c8afb9d7cee55fe5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8d28066798958e5730a95353690bcd0" id="r_gac8d28066798958e5730a95353690bcd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8d28066798958e5730a95353690bcd0">CAN_F5R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cca1e8863cc27c3c8afb9d7cee55fe5">CAN_F5R1_FB31_Msk</a></td></tr>
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<tr class="memitem:ga2a05745a737f85b835db1099ff6e7263" id="r_ga2a05745a737f85b835db1099ff6e7263"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a05745a737f85b835db1099ff6e7263">CAN_F6R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2a05745a737f85b835db1099ff6e7263"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8aaf448c354a5a325c540df29f7af6ad" id="r_ga8aaf448c354a5a325c540df29f7af6ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8aaf448c354a5a325c540df29f7af6ad">CAN_F6R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a05745a737f85b835db1099ff6e7263">CAN_F6R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga8aaf448c354a5a325c540df29f7af6ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb57fe42259bd37deffe11eded640c76" id="r_gacb57fe42259bd37deffe11eded640c76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb57fe42259bd37deffe11eded640c76">CAN_F6R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8aaf448c354a5a325c540df29f7af6ad">CAN_F6R1_FB0_Msk</a></td></tr>
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<tr class="separator:gacb57fe42259bd37deffe11eded640c76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc9c5707374ef1577ec2a5c7dec11322" id="r_gabc9c5707374ef1577ec2a5c7dec11322"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc9c5707374ef1577ec2a5c7dec11322">CAN_F6R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gabc9c5707374ef1577ec2a5c7dec11322"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3154b0f8cb4e1e230e37da1e696659f" id="r_gae3154b0f8cb4e1e230e37da1e696659f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3154b0f8cb4e1e230e37da1e696659f">CAN_F6R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc9c5707374ef1577ec2a5c7dec11322">CAN_F6R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:gae3154b0f8cb4e1e230e37da1e696659f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1de288e28d5547106645ecc5b0c47f2a" id="r_ga1de288e28d5547106645ecc5b0c47f2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1de288e28d5547106645ecc5b0c47f2a">CAN_F6R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3154b0f8cb4e1e230e37da1e696659f">CAN_F6R1_FB1_Msk</a></td></tr>
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<tr class="separator:ga1de288e28d5547106645ecc5b0c47f2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7015e00f7ebf7b7727c89dd1e4d39aa6" id="r_ga7015e00f7ebf7b7727c89dd1e4d39aa6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7015e00f7ebf7b7727c89dd1e4d39aa6">CAN_F6R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga7015e00f7ebf7b7727c89dd1e4d39aa6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c19eddf607d2cf5941d3b6807ff89cd" id="r_ga5c19eddf607d2cf5941d3b6807ff89cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c19eddf607d2cf5941d3b6807ff89cd">CAN_F6R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7015e00f7ebf7b7727c89dd1e4d39aa6">CAN_F6R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga5c19eddf607d2cf5941d3b6807ff89cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa8662caaa28aee37b2689f55400b75c" id="r_gaaa8662caaa28aee37b2689f55400b75c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa8662caaa28aee37b2689f55400b75c">CAN_F6R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c19eddf607d2cf5941d3b6807ff89cd">CAN_F6R1_FB2_Msk</a></td></tr>
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<tr class="separator:gaaa8662caaa28aee37b2689f55400b75c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac97c920c1437c8ac5df50b171f4aee5f" id="r_gac97c920c1437c8ac5df50b171f4aee5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac97c920c1437c8ac5df50b171f4aee5f">CAN_F6R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gac97c920c1437c8ac5df50b171f4aee5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec1656844d8617834262a5b6e24936bd" id="r_gaec1656844d8617834262a5b6e24936bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec1656844d8617834262a5b6e24936bd">CAN_F6R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac97c920c1437c8ac5df50b171f4aee5f">CAN_F6R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:gaec1656844d8617834262a5b6e24936bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4ccedde67989fcbaa84cae9cae4b1eb" id="r_gae4ccedde67989fcbaa84cae9cae4b1eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4ccedde67989fcbaa84cae9cae4b1eb">CAN_F6R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec1656844d8617834262a5b6e24936bd">CAN_F6R1_FB3_Msk</a></td></tr>
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<tr class="separator:gae4ccedde67989fcbaa84cae9cae4b1eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d7ff307582eac29ccb7608880ff227d" id="r_ga3d7ff307582eac29ccb7608880ff227d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d7ff307582eac29ccb7608880ff227d">CAN_F6R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga53a812ea22c8f0cfb484edc70dd19d6b" id="r_ga53a812ea22c8f0cfb484edc70dd19d6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53a812ea22c8f0cfb484edc70dd19d6b">CAN_F6R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d7ff307582eac29ccb7608880ff227d">CAN_F6R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga53a812ea22c8f0cfb484edc70dd19d6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45b063b3c14fd27bd63c03f878ac6cfc" id="r_ga45b063b3c14fd27bd63c03f878ac6cfc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45b063b3c14fd27bd63c03f878ac6cfc">CAN_F6R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga53a812ea22c8f0cfb484edc70dd19d6b">CAN_F6R1_FB4_Msk</a></td></tr>
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<tr class="separator:ga45b063b3c14fd27bd63c03f878ac6cfc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf3202c6c2ba274ba1a5920c47b2141d" id="r_gabf3202c6c2ba274ba1a5920c47b2141d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf3202c6c2ba274ba1a5920c47b2141d">CAN_F6R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gabf3202c6c2ba274ba1a5920c47b2141d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9afe1da36ff17919dc17466458f924a2" id="r_ga9afe1da36ff17919dc17466458f924a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9afe1da36ff17919dc17466458f924a2">CAN_F6R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf3202c6c2ba274ba1a5920c47b2141d">CAN_F6R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga9afe1da36ff17919dc17466458f924a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32f8566fab72dec6d52ad7262e67cbcc" id="r_ga32f8566fab72dec6d52ad7262e67cbcc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32f8566fab72dec6d52ad7262e67cbcc">CAN_F6R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9afe1da36ff17919dc17466458f924a2">CAN_F6R1_FB5_Msk</a></td></tr>
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<tr class="separator:ga32f8566fab72dec6d52ad7262e67cbcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43e24b0fe81f24078bdd007cbe832c07" id="r_ga43e24b0fe81f24078bdd007cbe832c07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43e24b0fe81f24078bdd007cbe832c07">CAN_F6R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga43e24b0fe81f24078bdd007cbe832c07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd31d2b1806cf454d51d956eb339d096" id="r_gacd31d2b1806cf454d51d956eb339d096"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd31d2b1806cf454d51d956eb339d096">CAN_F6R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga43e24b0fe81f24078bdd007cbe832c07">CAN_F6R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:gacd31d2b1806cf454d51d956eb339d096"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8636ecdacc3ca05d69e66737b7f2e7cf" id="r_ga8636ecdacc3ca05d69e66737b7f2e7cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8636ecdacc3ca05d69e66737b7f2e7cf">CAN_F6R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacd31d2b1806cf454d51d956eb339d096">CAN_F6R1_FB6_Msk</a></td></tr>
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<tr class="separator:ga8636ecdacc3ca05d69e66737b7f2e7cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2438dd17101c15d44b533cf1904f2fc" id="r_gad2438dd17101c15d44b533cf1904f2fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2438dd17101c15d44b533cf1904f2fc">CAN_F6R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gad2438dd17101c15d44b533cf1904f2fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87b36413ac64900c2398a530bbe647a6" id="r_ga87b36413ac64900c2398a530bbe647a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87b36413ac64900c2398a530bbe647a6">CAN_F6R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2438dd17101c15d44b533cf1904f2fc">CAN_F6R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga87b36413ac64900c2398a530bbe647a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb555ddab4853625c9b48b24e88d0dd8" id="r_gadb555ddab4853625c9b48b24e88d0dd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb555ddab4853625c9b48b24e88d0dd8">CAN_F6R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga87b36413ac64900c2398a530bbe647a6">CAN_F6R1_FB7_Msk</a></td></tr>
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<tr class="separator:gadb555ddab4853625c9b48b24e88d0dd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32fdb53fc39d6a2e09fcbbafb6d2ec81" id="r_ga32fdb53fc39d6a2e09fcbbafb6d2ec81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32fdb53fc39d6a2e09fcbbafb6d2ec81">CAN_F6R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga32fdb53fc39d6a2e09fcbbafb6d2ec81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45055999ce3c93c3f0e13f6a5fa1da30" id="r_ga45055999ce3c93c3f0e13f6a5fa1da30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45055999ce3c93c3f0e13f6a5fa1da30">CAN_F6R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga32fdb53fc39d6a2e09fcbbafb6d2ec81">CAN_F6R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga45055999ce3c93c3f0e13f6a5fa1da30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1e7ca2d014d77152ff0e6bbb8d5fb63" id="r_gaa1e7ca2d014d77152ff0e6bbb8d5fb63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1e7ca2d014d77152ff0e6bbb8d5fb63">CAN_F6R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45055999ce3c93c3f0e13f6a5fa1da30">CAN_F6R1_FB8_Msk</a></td></tr>
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<tr class="separator:gaa1e7ca2d014d77152ff0e6bbb8d5fb63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadad128a04f722f5190105f598e2b6ac8" id="r_gadad128a04f722f5190105f598e2b6ac8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadad128a04f722f5190105f598e2b6ac8">CAN_F6R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gadad128a04f722f5190105f598e2b6ac8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1904252fa35eca764e319ae3d124caa" id="r_gac1904252fa35eca764e319ae3d124caa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1904252fa35eca764e319ae3d124caa">CAN_F6R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadad128a04f722f5190105f598e2b6ac8">CAN_F6R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:gac1904252fa35eca764e319ae3d124caa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe4dc5e57c209eb4d3c5ed94b3a2e897" id="r_gafe4dc5e57c209eb4d3c5ed94b3a2e897"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe4dc5e57c209eb4d3c5ed94b3a2e897">CAN_F6R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac1904252fa35eca764e319ae3d124caa">CAN_F6R1_FB9_Msk</a></td></tr>
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<tr class="separator:gafe4dc5e57c209eb4d3c5ed94b3a2e897"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19bca6dcb49673694c6ac968da048d79" id="r_ga19bca6dcb49673694c6ac968da048d79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19bca6dcb49673694c6ac968da048d79">CAN_F6R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga19bca6dcb49673694c6ac968da048d79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a103dac7595c91ff96149735c5ce964" id="r_ga0a103dac7595c91ff96149735c5ce964"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a103dac7595c91ff96149735c5ce964">CAN_F6R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga19bca6dcb49673694c6ac968da048d79">CAN_F6R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga0a103dac7595c91ff96149735c5ce964"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa63ca9ec114f553d68e0b0d38ae57ff0" id="r_gaa63ca9ec114f553d68e0b0d38ae57ff0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa63ca9ec114f553d68e0b0d38ae57ff0">CAN_F6R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a103dac7595c91ff96149735c5ce964">CAN_F6R1_FB10_Msk</a></td></tr>
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<tr class="separator:gaa63ca9ec114f553d68e0b0d38ae57ff0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf750a53eaea8fac3215da663a4d1fbd7" id="r_gaf750a53eaea8fac3215da663a4d1fbd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf750a53eaea8fac3215da663a4d1fbd7">CAN_F6R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaf750a53eaea8fac3215da663a4d1fbd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf418fcb1f3c27715523268e65cacab77" id="r_gaf418fcb1f3c27715523268e65cacab77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf418fcb1f3c27715523268e65cacab77">CAN_F6R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf750a53eaea8fac3215da663a4d1fbd7">CAN_F6R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:gaf418fcb1f3c27715523268e65cacab77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf3394a2675a7cb30556a40cc5b77c08" id="r_gadf3394a2675a7cb30556a40cc5b77c08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf3394a2675a7cb30556a40cc5b77c08">CAN_F6R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf418fcb1f3c27715523268e65cacab77">CAN_F6R1_FB11_Msk</a></td></tr>
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<tr class="separator:gadf3394a2675a7cb30556a40cc5b77c08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7fe4fd95f7cac5eda54ed4260e350d8e" id="r_ga7fe4fd95f7cac5eda54ed4260e350d8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fe4fd95f7cac5eda54ed4260e350d8e">CAN_F6R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga7fe4fd95f7cac5eda54ed4260e350d8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf975da091767c6f1106d725426874602" id="r_gaf975da091767c6f1106d725426874602"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf975da091767c6f1106d725426874602">CAN_F6R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7fe4fd95f7cac5eda54ed4260e350d8e">CAN_F6R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:gaf975da091767c6f1106d725426874602"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9c9c04edb492e48619de926196ab695" id="r_gae9c9c04edb492e48619de926196ab695"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9c9c04edb492e48619de926196ab695">CAN_F6R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf975da091767c6f1106d725426874602">CAN_F6R1_FB12_Msk</a></td></tr>
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<tr class="separator:gae9c9c04edb492e48619de926196ab695"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0854e19abe416754a29c04869c5dd57b" id="r_ga0854e19abe416754a29c04869c5dd57b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0854e19abe416754a29c04869c5dd57b">CAN_F6R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0854e19abe416754a29c04869c5dd57b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf024ad0a5286c193a57e761ae8dd78ab" id="r_gaf024ad0a5286c193a57e761ae8dd78ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf024ad0a5286c193a57e761ae8dd78ab">CAN_F6R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0854e19abe416754a29c04869c5dd57b">CAN_F6R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:gaf024ad0a5286c193a57e761ae8dd78ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga070e91897e07ae11a9d2f60ff31e196a" id="r_ga070e91897e07ae11a9d2f60ff31e196a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga070e91897e07ae11a9d2f60ff31e196a">CAN_F6R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf024ad0a5286c193a57e761ae8dd78ab">CAN_F6R1_FB13_Msk</a></td></tr>
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<tr class="separator:ga070e91897e07ae11a9d2f60ff31e196a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06cb4f011cdc5345ffd410b209ae38ef" id="r_ga06cb4f011cdc5345ffd410b209ae38ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06cb4f011cdc5345ffd410b209ae38ef">CAN_F6R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga06cb4f011cdc5345ffd410b209ae38ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2dcc33648e9130b7b12dd082032e1e02" id="r_ga2dcc33648e9130b7b12dd082032e1e02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dcc33648e9130b7b12dd082032e1e02">CAN_F6R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga06cb4f011cdc5345ffd410b209ae38ef">CAN_F6R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:ga2dcc33648e9130b7b12dd082032e1e02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3479321a85f1f55e24a1b56d13226a22" id="r_ga3479321a85f1f55e24a1b56d13226a22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3479321a85f1f55e24a1b56d13226a22">CAN_F6R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2dcc33648e9130b7b12dd082032e1e02">CAN_F6R1_FB14_Msk</a></td></tr>
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<tr class="separator:ga3479321a85f1f55e24a1b56d13226a22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a55b3fc85269d073d5cda9c98e2e1ef" id="r_ga2a55b3fc85269d073d5cda9c98e2e1ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a55b3fc85269d073d5cda9c98e2e1ef">CAN_F6R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="memitem:gad577265745548ad4066ee66d7db968f5" id="r_gad577265745548ad4066ee66d7db968f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad577265745548ad4066ee66d7db968f5">CAN_F6R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a55b3fc85269d073d5cda9c98e2e1ef">CAN_F6R1_FB15_Pos</a>)</td></tr>
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<tr class="memitem:ga9a998a2b37fde5207b286a58c115a9e8" id="r_ga9a998a2b37fde5207b286a58c115a9e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a998a2b37fde5207b286a58c115a9e8">CAN_F6R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad577265745548ad4066ee66d7db968f5">CAN_F6R1_FB15_Msk</a></td></tr>
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<tr class="memitem:ga2d3df4af8b5925814763b952a9c6f328" id="r_ga2d3df4af8b5925814763b952a9c6f328"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d3df4af8b5925814763b952a9c6f328">CAN_F6R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gaba4c35e9c340e717ba471e6913120bac" id="r_gaba4c35e9c340e717ba471e6913120bac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba4c35e9c340e717ba471e6913120bac">CAN_F6R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d3df4af8b5925814763b952a9c6f328">CAN_F6R1_FB16_Pos</a>)</td></tr>
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<tr class="memitem:ga891ad3d341cee397d49fc982c509f7d5" id="r_ga891ad3d341cee397d49fc982c509f7d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga891ad3d341cee397d49fc982c509f7d5">CAN_F6R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba4c35e9c340e717ba471e6913120bac">CAN_F6R1_FB16_Msk</a></td></tr>
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<tr class="memitem:ga96c2447a18f72f6dd8d73e51d72ca71f" id="r_ga96c2447a18f72f6dd8d73e51d72ca71f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96c2447a18f72f6dd8d73e51d72ca71f">CAN_F6R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga96c2447a18f72f6dd8d73e51d72ca71f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b71b0660dd705a9ebe22c2e768e4172" id="r_ga4b71b0660dd705a9ebe22c2e768e4172"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b71b0660dd705a9ebe22c2e768e4172">CAN_F6R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96c2447a18f72f6dd8d73e51d72ca71f">CAN_F6R1_FB17_Pos</a>)</td></tr>
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<tr class="memitem:gac4a70606f1b07a6bbb5ae4fe8ad374e5" id="r_gac4a70606f1b07a6bbb5ae4fe8ad374e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4a70606f1b07a6bbb5ae4fe8ad374e5">CAN_F6R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b71b0660dd705a9ebe22c2e768e4172">CAN_F6R1_FB17_Msk</a></td></tr>
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<tr class="memitem:gae3aa83c6161527cef489d960584af040" id="r_gae3aa83c6161527cef489d960584af040"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3aa83c6161527cef489d960584af040">CAN_F6R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga42fa5a606d58f2a30da9a58581178127" id="r_ga42fa5a606d58f2a30da9a58581178127"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42fa5a606d58f2a30da9a58581178127">CAN_F6R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3aa83c6161527cef489d960584af040">CAN_F6R1_FB18_Pos</a>)</td></tr>
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<tr class="memitem:ga1542ea54030e3052c8991b249cd0e504" id="r_ga1542ea54030e3052c8991b249cd0e504"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1542ea54030e3052c8991b249cd0e504">CAN_F6R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga42fa5a606d58f2a30da9a58581178127">CAN_F6R1_FB18_Msk</a></td></tr>
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<tr class="memitem:gaa6a4e2993cf15d28b3ff030793d110a6" id="r_gaa6a4e2993cf15d28b3ff030793d110a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6a4e2993cf15d28b3ff030793d110a6">CAN_F6R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="memitem:ga433c7e51a79cc95f7aa5593c5d347dfc" id="r_ga433c7e51a79cc95f7aa5593c5d347dfc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga433c7e51a79cc95f7aa5593c5d347dfc">CAN_F6R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6a4e2993cf15d28b3ff030793d110a6">CAN_F6R1_FB19_Pos</a>)</td></tr>
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<tr class="memitem:ga1e1a7c680bcfc57c6cc521cbaa0749d6" id="r_ga1e1a7c680bcfc57c6cc521cbaa0749d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e1a7c680bcfc57c6cc521cbaa0749d6">CAN_F6R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga433c7e51a79cc95f7aa5593c5d347dfc">CAN_F6R1_FB19_Msk</a></td></tr>
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<tr class="separator:ga1e1a7c680bcfc57c6cc521cbaa0749d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9841eeaf6951092200c67ee2e1d8959d" id="r_ga9841eeaf6951092200c67ee2e1d8959d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9841eeaf6951092200c67ee2e1d8959d">CAN_F6R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga6b843a11577d4891e11238810c01ccea" id="r_ga6b843a11577d4891e11238810c01ccea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b843a11577d4891e11238810c01ccea">CAN_F6R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9841eeaf6951092200c67ee2e1d8959d">CAN_F6R1_FB20_Pos</a>)</td></tr>
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<tr class="memitem:ga6fba31d938ab3492c8855c26bebfbef2" id="r_ga6fba31d938ab3492c8855c26bebfbef2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fba31d938ab3492c8855c26bebfbef2">CAN_F6R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b843a11577d4891e11238810c01ccea">CAN_F6R1_FB20_Msk</a></td></tr>
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<tr class="memitem:gaef6fa85c2d4ef60e08f9cc04e5531c48" id="r_gaef6fa85c2d4ef60e08f9cc04e5531c48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef6fa85c2d4ef60e08f9cc04e5531c48">CAN_F6R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gaef6fa85c2d4ef60e08f9cc04e5531c48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab49834ceca6245c6bed6b011c37cb51c" id="r_gab49834ceca6245c6bed6b011c37cb51c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab49834ceca6245c6bed6b011c37cb51c">CAN_F6R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef6fa85c2d4ef60e08f9cc04e5531c48">CAN_F6R1_FB21_Pos</a>)</td></tr>
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<tr class="memitem:ga556f3b08cee839e038109e604e5bba4c" id="r_ga556f3b08cee839e038109e604e5bba4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga556f3b08cee839e038109e604e5bba4c">CAN_F6R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab49834ceca6245c6bed6b011c37cb51c">CAN_F6R1_FB21_Msk</a></td></tr>
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<tr class="separator:ga556f3b08cee839e038109e604e5bba4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7fbd8ee1cf6970c9065f5afa0a7f3d8" id="r_gad7fbd8ee1cf6970c9065f5afa0a7f3d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7fbd8ee1cf6970c9065f5afa0a7f3d8">CAN_F6R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="memitem:gabbd32cd4a51845ae3257bec44dea5f36" id="r_gabbd32cd4a51845ae3257bec44dea5f36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbd32cd4a51845ae3257bec44dea5f36">CAN_F6R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad7fbd8ee1cf6970c9065f5afa0a7f3d8">CAN_F6R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:gabbd32cd4a51845ae3257bec44dea5f36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdc41162219ed6f5be1b5ae7ba328754" id="r_gafdc41162219ed6f5be1b5ae7ba328754"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdc41162219ed6f5be1b5ae7ba328754">CAN_F6R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabbd32cd4a51845ae3257bec44dea5f36">CAN_F6R1_FB22_Msk</a></td></tr>
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<tr class="separator:gafdc41162219ed6f5be1b5ae7ba328754"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa12596b4ab04f15a4de2a08772365def" id="r_gaa12596b4ab04f15a4de2a08772365def"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa12596b4ab04f15a4de2a08772365def">CAN_F6R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gaa12596b4ab04f15a4de2a08772365def"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga601aa03929a9eed61e4191a049c75fb8" id="r_ga601aa03929a9eed61e4191a049c75fb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga601aa03929a9eed61e4191a049c75fb8">CAN_F6R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa12596b4ab04f15a4de2a08772365def">CAN_F6R1_FB23_Pos</a>)</td></tr>
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<tr class="memitem:ga89f4fd5c28d2fd7475081b39b2b358c6" id="r_ga89f4fd5c28d2fd7475081b39b2b358c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89f4fd5c28d2fd7475081b39b2b358c6">CAN_F6R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga601aa03929a9eed61e4191a049c75fb8">CAN_F6R1_FB23_Msk</a></td></tr>
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<tr class="separator:ga89f4fd5c28d2fd7475081b39b2b358c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadfa75de907e614398eb71f98ebcd4f9e" id="r_gadfa75de907e614398eb71f98ebcd4f9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfa75de907e614398eb71f98ebcd4f9e">CAN_F6R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:gadfa75de907e614398eb71f98ebcd4f9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2707b11422d80fcc55e5759c7d7a3983" id="r_ga2707b11422d80fcc55e5759c7d7a3983"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2707b11422d80fcc55e5759c7d7a3983">CAN_F6R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfa75de907e614398eb71f98ebcd4f9e">CAN_F6R1_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga2707b11422d80fcc55e5759c7d7a3983"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5eb9d0f3cad0eeea398f2ba5fd83cf2" id="r_gac5eb9d0f3cad0eeea398f2ba5fd83cf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5eb9d0f3cad0eeea398f2ba5fd83cf2">CAN_F6R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2707b11422d80fcc55e5759c7d7a3983">CAN_F6R1_FB24_Msk</a></td></tr>
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<tr class="separator:gac5eb9d0f3cad0eeea398f2ba5fd83cf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaafc2b7e2fbf01700501b1d5fb0ed54d6" id="r_gaafc2b7e2fbf01700501b1d5fb0ed54d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafc2b7e2fbf01700501b1d5fb0ed54d6">CAN_F6R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gaafc2b7e2fbf01700501b1d5fb0ed54d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50ed60d8e8930a207039da6873a403b4" id="r_ga50ed60d8e8930a207039da6873a403b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50ed60d8e8930a207039da6873a403b4">CAN_F6R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaafc2b7e2fbf01700501b1d5fb0ed54d6">CAN_F6R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga50ed60d8e8930a207039da6873a403b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3fa46e9d1fafcb3eb1189d6d43692cd" id="r_gaa3fa46e9d1fafcb3eb1189d6d43692cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3fa46e9d1fafcb3eb1189d6d43692cd">CAN_F6R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga50ed60d8e8930a207039da6873a403b4">CAN_F6R1_FB25_Msk</a></td></tr>
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<tr class="memitem:ga63a7a5394639689f077cd23a1bc2a2c3" id="r_ga63a7a5394639689f077cd23a1bc2a2c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63a7a5394639689f077cd23a1bc2a2c3">CAN_F6R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga63a7a5394639689f077cd23a1bc2a2c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2202fe7314b833d290f25a0e5234169" id="r_gae2202fe7314b833d290f25a0e5234169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2202fe7314b833d290f25a0e5234169">CAN_F6R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga63a7a5394639689f077cd23a1bc2a2c3">CAN_F6R1_FB26_Pos</a>)</td></tr>
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<tr class="memitem:gab9168b4d12ddb654b397ce3ffb66af4c" id="r_gab9168b4d12ddb654b397ce3ffb66af4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9168b4d12ddb654b397ce3ffb66af4c">CAN_F6R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae2202fe7314b833d290f25a0e5234169">CAN_F6R1_FB26_Msk</a></td></tr>
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<tr class="separator:gab9168b4d12ddb654b397ce3ffb66af4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga193993f46c36ffb52f560dd38e2f2b14" id="r_ga193993f46c36ffb52f560dd38e2f2b14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga193993f46c36ffb52f560dd38e2f2b14">CAN_F6R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga193993f46c36ffb52f560dd38e2f2b14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45b34d58ea8416ea9ccdadd87259d810" id="r_ga45b34d58ea8416ea9ccdadd87259d810"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45b34d58ea8416ea9ccdadd87259d810">CAN_F6R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga193993f46c36ffb52f560dd38e2f2b14">CAN_F6R1_FB27_Pos</a>)</td></tr>
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<tr class="memitem:ga610fdf301fb1cff5af38f83b4e0c81b1" id="r_ga610fdf301fb1cff5af38f83b4e0c81b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga610fdf301fb1cff5af38f83b4e0c81b1">CAN_F6R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45b34d58ea8416ea9ccdadd87259d810">CAN_F6R1_FB27_Msk</a></td></tr>
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<tr class="separator:ga610fdf301fb1cff5af38f83b4e0c81b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2064cf4f9bff8a3880b2b3f80225de4f" id="r_ga2064cf4f9bff8a3880b2b3f80225de4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2064cf4f9bff8a3880b2b3f80225de4f">CAN_F6R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga2064cf4f9bff8a3880b2b3f80225de4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab87f159252e6a934b1ecfb6082d8ac50" id="r_gab87f159252e6a934b1ecfb6082d8ac50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab87f159252e6a934b1ecfb6082d8ac50">CAN_F6R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2064cf4f9bff8a3880b2b3f80225de4f">CAN_F6R1_FB28_Pos</a>)</td></tr>
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<tr class="separator:gab87f159252e6a934b1ecfb6082d8ac50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a3e033aae51ff31b75fb801599232f5" id="r_ga8a3e033aae51ff31b75fb801599232f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a3e033aae51ff31b75fb801599232f5">CAN_F6R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab87f159252e6a934b1ecfb6082d8ac50">CAN_F6R1_FB28_Msk</a></td></tr>
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<tr class="separator:ga8a3e033aae51ff31b75fb801599232f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b8ac47a8b593b2d941f2df07adc8f65" id="r_ga8b8ac47a8b593b2d941f2df07adc8f65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b8ac47a8b593b2d941f2df07adc8f65">CAN_F6R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga8b8ac47a8b593b2d941f2df07adc8f65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87baee8a9cefd8158caf141f29881051" id="r_ga87baee8a9cefd8158caf141f29881051"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87baee8a9cefd8158caf141f29881051">CAN_F6R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b8ac47a8b593b2d941f2df07adc8f65">CAN_F6R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:ga87baee8a9cefd8158caf141f29881051"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga868ae6fc3bbe273b44d250791a80df58" id="r_ga868ae6fc3bbe273b44d250791a80df58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga868ae6fc3bbe273b44d250791a80df58">CAN_F6R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga87baee8a9cefd8158caf141f29881051">CAN_F6R1_FB29_Msk</a></td></tr>
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<tr class="separator:ga868ae6fc3bbe273b44d250791a80df58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga208a9734e163cf973b02b3e7a8d9271a" id="r_ga208a9734e163cf973b02b3e7a8d9271a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga208a9734e163cf973b02b3e7a8d9271a">CAN_F6R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga208a9734e163cf973b02b3e7a8d9271a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdec0e767a520aa7bcffac3e5652181b" id="r_gabdec0e767a520aa7bcffac3e5652181b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdec0e767a520aa7bcffac3e5652181b">CAN_F6R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga208a9734e163cf973b02b3e7a8d9271a">CAN_F6R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:gabdec0e767a520aa7bcffac3e5652181b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe08696e215f9e8f1605e60e4817dd8b" id="r_gafe08696e215f9e8f1605e60e4817dd8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe08696e215f9e8f1605e60e4817dd8b">CAN_F6R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabdec0e767a520aa7bcffac3e5652181b">CAN_F6R1_FB30_Msk</a></td></tr>
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<tr class="separator:gafe08696e215f9e8f1605e60e4817dd8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76a4f2683f6acc00c48fadadcc75f877" id="r_ga76a4f2683f6acc00c48fadadcc75f877"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76a4f2683f6acc00c48fadadcc75f877">CAN_F6R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga76a4f2683f6acc00c48fadadcc75f877"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f2f09b2ada8e9ea6e28a7abe6dfd678" id="r_ga8f2f09b2ada8e9ea6e28a7abe6dfd678"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f2f09b2ada8e9ea6e28a7abe6dfd678">CAN_F6R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga76a4f2683f6acc00c48fadadcc75f877">CAN_F6R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga8f2f09b2ada8e9ea6e28a7abe6dfd678"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69b2dffd9969ff8658b45a7a2bb1c5ee" id="r_ga69b2dffd9969ff8658b45a7a2bb1c5ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69b2dffd9969ff8658b45a7a2bb1c5ee">CAN_F6R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f2f09b2ada8e9ea6e28a7abe6dfd678">CAN_F6R1_FB31_Msk</a></td></tr>
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<tr class="separator:ga69b2dffd9969ff8658b45a7a2bb1c5ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07592cc9f142c86800624b80ac659191" id="r_ga07592cc9f142c86800624b80ac659191"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07592cc9f142c86800624b80ac659191">CAN_F7R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga07592cc9f142c86800624b80ac659191"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad19ad30a6bd063074a8e787ce24f7d3f" id="r_gad19ad30a6bd063074a8e787ce24f7d3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad19ad30a6bd063074a8e787ce24f7d3f">CAN_F7R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07592cc9f142c86800624b80ac659191">CAN_F7R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:gad19ad30a6bd063074a8e787ce24f7d3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2217bcc5b82de25751d3984884b0e0c1" id="r_ga2217bcc5b82de25751d3984884b0e0c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2217bcc5b82de25751d3984884b0e0c1">CAN_F7R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad19ad30a6bd063074a8e787ce24f7d3f">CAN_F7R1_FB0_Msk</a></td></tr>
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<tr class="separator:ga2217bcc5b82de25751d3984884b0e0c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab323a7481c5d75df36e9e2b25c7e6e32" id="r_gab323a7481c5d75df36e9e2b25c7e6e32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab323a7481c5d75df36e9e2b25c7e6e32">CAN_F7R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gab323a7481c5d75df36e9e2b25c7e6e32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab83bdd3955b202a00602bff176ab3cd8" id="r_gab83bdd3955b202a00602bff176ab3cd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab83bdd3955b202a00602bff176ab3cd8">CAN_F7R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab323a7481c5d75df36e9e2b25c7e6e32">CAN_F7R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:gab83bdd3955b202a00602bff176ab3cd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf71cbdd5cbe109fde119adb86d64f0a7" id="r_gaf71cbdd5cbe109fde119adb86d64f0a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf71cbdd5cbe109fde119adb86d64f0a7">CAN_F7R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab83bdd3955b202a00602bff176ab3cd8">CAN_F7R1_FB1_Msk</a></td></tr>
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<tr class="separator:gaf71cbdd5cbe109fde119adb86d64f0a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b06796d92491cd5111bad5c6c380190" id="r_ga4b06796d92491cd5111bad5c6c380190"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b06796d92491cd5111bad5c6c380190">CAN_F7R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga4b06796d92491cd5111bad5c6c380190"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffbf82ffead59ec0190dec25b9c8c621" id="r_gaffbf82ffead59ec0190dec25b9c8c621"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffbf82ffead59ec0190dec25b9c8c621">CAN_F7R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b06796d92491cd5111bad5c6c380190">CAN_F7R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:gaffbf82ffead59ec0190dec25b9c8c621"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0a7a004058a6b10b5cb3374eb82dd1d" id="r_gaa0a7a004058a6b10b5cb3374eb82dd1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0a7a004058a6b10b5cb3374eb82dd1d">CAN_F7R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaffbf82ffead59ec0190dec25b9c8c621">CAN_F7R1_FB2_Msk</a></td></tr>
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<tr class="separator:gaa0a7a004058a6b10b5cb3374eb82dd1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga548972b3e8900613c72d584ac0550d81" id="r_ga548972b3e8900613c72d584ac0550d81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga548972b3e8900613c72d584ac0550d81">CAN_F7R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga548972b3e8900613c72d584ac0550d81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab477aa17c626cac52ef965f21579dc69" id="r_gab477aa17c626cac52ef965f21579dc69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab477aa17c626cac52ef965f21579dc69">CAN_F7R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga548972b3e8900613c72d584ac0550d81">CAN_F7R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:gab477aa17c626cac52ef965f21579dc69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2224329373b490c8dd4f0c148ef58997" id="r_ga2224329373b490c8dd4f0c148ef58997"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2224329373b490c8dd4f0c148ef58997">CAN_F7R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab477aa17c626cac52ef965f21579dc69">CAN_F7R1_FB3_Msk</a></td></tr>
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<tr class="separator:ga2224329373b490c8dd4f0c148ef58997"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga428d061d3d6cd26401f09a0a9d888582" id="r_ga428d061d3d6cd26401f09a0a9d888582"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga428d061d3d6cd26401f09a0a9d888582">CAN_F7R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga428d061d3d6cd26401f09a0a9d888582"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e6552b734a4618cff826b853d8e5ac7" id="r_ga4e6552b734a4618cff826b853d8e5ac7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e6552b734a4618cff826b853d8e5ac7">CAN_F7R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga428d061d3d6cd26401f09a0a9d888582">CAN_F7R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga4e6552b734a4618cff826b853d8e5ac7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3574ea4882319ac08e0df065bdd3566" id="r_gad3574ea4882319ac08e0df065bdd3566"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3574ea4882319ac08e0df065bdd3566">CAN_F7R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e6552b734a4618cff826b853d8e5ac7">CAN_F7R1_FB4_Msk</a></td></tr>
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<tr class="separator:gad3574ea4882319ac08e0df065bdd3566"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51f21f5d42dc175f69e397d8a021ec17" id="r_ga51f21f5d42dc175f69e397d8a021ec17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51f21f5d42dc175f69e397d8a021ec17">CAN_F7R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga51f21f5d42dc175f69e397d8a021ec17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4b90d78121983740c8d803352b68cef" id="r_gad4b90d78121983740c8d803352b68cef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4b90d78121983740c8d803352b68cef">CAN_F7R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga51f21f5d42dc175f69e397d8a021ec17">CAN_F7R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:gad4b90d78121983740c8d803352b68cef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76f63e712a9a57dacab2874dd695254d" id="r_ga76f63e712a9a57dacab2874dd695254d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76f63e712a9a57dacab2874dd695254d">CAN_F7R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad4b90d78121983740c8d803352b68cef">CAN_F7R1_FB5_Msk</a></td></tr>
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<tr class="separator:ga76f63e712a9a57dacab2874dd695254d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafaf5d52b07d0fb670d7b754f293193b2" id="r_gafaf5d52b07d0fb670d7b754f293193b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafaf5d52b07d0fb670d7b754f293193b2">CAN_F7R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gafaf5d52b07d0fb670d7b754f293193b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e3a549c7bf229dda892b600b320b4e0" id="r_ga0e3a549c7bf229dda892b600b320b4e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e3a549c7bf229dda892b600b320b4e0">CAN_F7R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafaf5d52b07d0fb670d7b754f293193b2">CAN_F7R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga0e3a549c7bf229dda892b600b320b4e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22d969f17f8a25a63cb056ee2cb622d3" id="r_ga22d969f17f8a25a63cb056ee2cb622d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22d969f17f8a25a63cb056ee2cb622d3">CAN_F7R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e3a549c7bf229dda892b600b320b4e0">CAN_F7R1_FB6_Msk</a></td></tr>
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<tr class="separator:ga22d969f17f8a25a63cb056ee2cb622d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85318a4750085acc0f67eaf5d748f0b0" id="r_ga85318a4750085acc0f67eaf5d748f0b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85318a4750085acc0f67eaf5d748f0b0">CAN_F7R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga85318a4750085acc0f67eaf5d748f0b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb8ad36251e272dd1487dfec8f4b6cfd" id="r_gafb8ad36251e272dd1487dfec8f4b6cfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb8ad36251e272dd1487dfec8f4b6cfd">CAN_F7R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga85318a4750085acc0f67eaf5d748f0b0">CAN_F7R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:gafb8ad36251e272dd1487dfec8f4b6cfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae89ec51b51c83c108880e361caf17ac" id="r_gaae89ec51b51c83c108880e361caf17ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae89ec51b51c83c108880e361caf17ac">CAN_F7R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb8ad36251e272dd1487dfec8f4b6cfd">CAN_F7R1_FB7_Msk</a></td></tr>
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<tr class="separator:gaae89ec51b51c83c108880e361caf17ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3977b859e97377959d730d66dba4cea" id="r_gad3977b859e97377959d730d66dba4cea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3977b859e97377959d730d66dba4cea">CAN_F7R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gad3977b859e97377959d730d66dba4cea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2be453e8e7320b77bc242044038ab02" id="r_gad2be453e8e7320b77bc242044038ab02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2be453e8e7320b77bc242044038ab02">CAN_F7R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad3977b859e97377959d730d66dba4cea">CAN_F7R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:gad2be453e8e7320b77bc242044038ab02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67fca99c67cab6713605e14d96a9df62" id="r_ga67fca99c67cab6713605e14d96a9df62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67fca99c67cab6713605e14d96a9df62">CAN_F7R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad2be453e8e7320b77bc242044038ab02">CAN_F7R1_FB8_Msk</a></td></tr>
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<tr class="separator:ga67fca99c67cab6713605e14d96a9df62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8aaaf940b9f64ff8cf14a1ccb1f01353" id="r_ga8aaaf940b9f64ff8cf14a1ccb1f01353"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8aaaf940b9f64ff8cf14a1ccb1f01353">CAN_F7R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga8aaaf940b9f64ff8cf14a1ccb1f01353"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga271c074cc3a12f895a531d0cfb29a883" id="r_ga271c074cc3a12f895a531d0cfb29a883"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga271c074cc3a12f895a531d0cfb29a883">CAN_F7R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8aaaf940b9f64ff8cf14a1ccb1f01353">CAN_F7R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga271c074cc3a12f895a531d0cfb29a883"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacd1ef8f0870bc5a5422a6bedbb61d40" id="r_gaacd1ef8f0870bc5a5422a6bedbb61d40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacd1ef8f0870bc5a5422a6bedbb61d40">CAN_F7R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga271c074cc3a12f895a531d0cfb29a883">CAN_F7R1_FB9_Msk</a></td></tr>
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<tr class="separator:gaacd1ef8f0870bc5a5422a6bedbb61d40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e458cf6d5da73505414aa25098d9282" id="r_ga7e458cf6d5da73505414aa25098d9282"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e458cf6d5da73505414aa25098d9282">CAN_F7R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga7e458cf6d5da73505414aa25098d9282"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad708e8bc52c416ee38bc5bb93822a877" id="r_gad708e8bc52c416ee38bc5bb93822a877"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad708e8bc52c416ee38bc5bb93822a877">CAN_F7R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e458cf6d5da73505414aa25098d9282">CAN_F7R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:gad708e8bc52c416ee38bc5bb93822a877"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf56408d9914f566396d64609830e2d4f" id="r_gaf56408d9914f566396d64609830e2d4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf56408d9914f566396d64609830e2d4f">CAN_F7R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad708e8bc52c416ee38bc5bb93822a877">CAN_F7R1_FB10_Msk</a></td></tr>
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<tr class="separator:gaf56408d9914f566396d64609830e2d4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c05b416f990eebb80363c022661be43" id="r_ga9c05b416f990eebb80363c022661be43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c05b416f990eebb80363c022661be43">CAN_F7R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga9c05b416f990eebb80363c022661be43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8fa9afddd282899c92a7647e6f1eb8e" id="r_gad8fa9afddd282899c92a7647e6f1eb8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8fa9afddd282899c92a7647e6f1eb8e">CAN_F7R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c05b416f990eebb80363c022661be43">CAN_F7R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:gad8fa9afddd282899c92a7647e6f1eb8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65947100832111c7fb427d1982f801eb" id="r_ga65947100832111c7fb427d1982f801eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65947100832111c7fb427d1982f801eb">CAN_F7R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad8fa9afddd282899c92a7647e6f1eb8e">CAN_F7R1_FB11_Msk</a></td></tr>
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<tr class="separator:ga65947100832111c7fb427d1982f801eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae496f5c9c04aa8d161b380cfc46c1a89" id="r_gae496f5c9c04aa8d161b380cfc46c1a89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae496f5c9c04aa8d161b380cfc46c1a89">CAN_F7R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gae496f5c9c04aa8d161b380cfc46c1a89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad694f31ad366db83ec659c93fb75db7f" id="r_gad694f31ad366db83ec659c93fb75db7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad694f31ad366db83ec659c93fb75db7f">CAN_F7R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae496f5c9c04aa8d161b380cfc46c1a89">CAN_F7R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:gad694f31ad366db83ec659c93fb75db7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga175ed9cdbbf756ec76b9c6fb1f69adff" id="r_ga175ed9cdbbf756ec76b9c6fb1f69adff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga175ed9cdbbf756ec76b9c6fb1f69adff">CAN_F7R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad694f31ad366db83ec659c93fb75db7f">CAN_F7R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga175ed9cdbbf756ec76b9c6fb1f69adff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0706b04b0ddfa96c5ab1120d8973c8fd" id="r_ga0706b04b0ddfa96c5ab1120d8973c8fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0706b04b0ddfa96c5ab1120d8973c8fd">CAN_F7R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0706b04b0ddfa96c5ab1120d8973c8fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc73cd4c1973c6d575b12ef8a34aefdf" id="r_gafc73cd4c1973c6d575b12ef8a34aefdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc73cd4c1973c6d575b12ef8a34aefdf">CAN_F7R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0706b04b0ddfa96c5ab1120d8973c8fd">CAN_F7R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:gafc73cd4c1973c6d575b12ef8a34aefdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91af48b8cd11f119d257311dcf2cc291" id="r_ga91af48b8cd11f119d257311dcf2cc291"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91af48b8cd11f119d257311dcf2cc291">CAN_F7R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafc73cd4c1973c6d575b12ef8a34aefdf">CAN_F7R1_FB13_Msk</a></td></tr>
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<tr class="separator:ga91af48b8cd11f119d257311dcf2cc291"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace9cd9b7f8196e5831e7a68cc063eabb" id="r_gace9cd9b7f8196e5831e7a68cc063eabb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace9cd9b7f8196e5831e7a68cc063eabb">CAN_F7R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gace9cd9b7f8196e5831e7a68cc063eabb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa51f245c33277eb5e09db8b8302e2df6" id="r_gaa51f245c33277eb5e09db8b8302e2df6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa51f245c33277eb5e09db8b8302e2df6">CAN_F7R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gace9cd9b7f8196e5831e7a68cc063eabb">CAN_F7R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:gaa51f245c33277eb5e09db8b8302e2df6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7108bc449a6e328748dd8d2209b83753" id="r_ga7108bc449a6e328748dd8d2209b83753"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7108bc449a6e328748dd8d2209b83753">CAN_F7R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa51f245c33277eb5e09db8b8302e2df6">CAN_F7R1_FB14_Msk</a></td></tr>
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<tr class="separator:ga7108bc449a6e328748dd8d2209b83753"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a5c4ef28847f4fa0d27a781b0b8a986" id="r_ga6a5c4ef28847f4fa0d27a781b0b8a986"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a5c4ef28847f4fa0d27a781b0b8a986">CAN_F7R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga6a5c4ef28847f4fa0d27a781b0b8a986"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3dd14c5855dfe51bc8a1a44266d1c925" id="r_ga3dd14c5855dfe51bc8a1a44266d1c925"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3dd14c5855dfe51bc8a1a44266d1c925">CAN_F7R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a5c4ef28847f4fa0d27a781b0b8a986">CAN_F7R1_FB15_Pos</a>)</td></tr>
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<tr class="memitem:gacc47acac1bb59603f58d9aef661d9334" id="r_gacc47acac1bb59603f58d9aef661d9334"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc47acac1bb59603f58d9aef661d9334">CAN_F7R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3dd14c5855dfe51bc8a1a44266d1c925">CAN_F7R1_FB15_Msk</a></td></tr>
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<tr class="memitem:ga9d07c069c5aca9e42f268ab32a062c75" id="r_ga9d07c069c5aca9e42f268ab32a062c75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d07c069c5aca9e42f268ab32a062c75">CAN_F7R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gafc661e05b2422313bf88f39f049ce53e" id="r_gafc661e05b2422313bf88f39f049ce53e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc661e05b2422313bf88f39f049ce53e">CAN_F7R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d07c069c5aca9e42f268ab32a062c75">CAN_F7R1_FB16_Pos</a>)</td></tr>
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<tr class="memitem:ga7b07b4ebfaac9e60d6042b1bff98ec33" id="r_ga7b07b4ebfaac9e60d6042b1bff98ec33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b07b4ebfaac9e60d6042b1bff98ec33">CAN_F7R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafc661e05b2422313bf88f39f049ce53e">CAN_F7R1_FB16_Msk</a></td></tr>
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<tr class="separator:ga7b07b4ebfaac9e60d6042b1bff98ec33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga648db438e1aef7f7b35396757e7c7b52" id="r_ga648db438e1aef7f7b35396757e7c7b52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga648db438e1aef7f7b35396757e7c7b52">CAN_F7R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga648db438e1aef7f7b35396757e7c7b52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58a27e2e7fd333f0aba9fbd5919e260d" id="r_ga58a27e2e7fd333f0aba9fbd5919e260d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58a27e2e7fd333f0aba9fbd5919e260d">CAN_F7R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga648db438e1aef7f7b35396757e7c7b52">CAN_F7R1_FB17_Pos</a>)</td></tr>
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<tr class="memitem:gad3328e95d8ae911adc0e5dd4128f8161" id="r_gad3328e95d8ae911adc0e5dd4128f8161"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3328e95d8ae911adc0e5dd4128f8161">CAN_F7R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga58a27e2e7fd333f0aba9fbd5919e260d">CAN_F7R1_FB17_Msk</a></td></tr>
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<tr class="separator:gad3328e95d8ae911adc0e5dd4128f8161"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf56090225bc33669e07141a1243cec88" id="r_gaf56090225bc33669e07141a1243cec88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf56090225bc33669e07141a1243cec88">CAN_F7R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga278e31f437817faa9cad12cc69e3112b" id="r_ga278e31f437817faa9cad12cc69e3112b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga278e31f437817faa9cad12cc69e3112b">CAN_F7R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf56090225bc33669e07141a1243cec88">CAN_F7R1_FB18_Pos</a>)</td></tr>
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<tr class="memitem:ga473e4917f35772cd08b06e166d6e475e" id="r_ga473e4917f35772cd08b06e166d6e475e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga473e4917f35772cd08b06e166d6e475e">CAN_F7R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga278e31f437817faa9cad12cc69e3112b">CAN_F7R1_FB18_Msk</a></td></tr>
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<tr class="separator:ga473e4917f35772cd08b06e166d6e475e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ab1b958322e9e8924570497657ef396" id="r_ga2ab1b958322e9e8924570497657ef396"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ab1b958322e9e8924570497657ef396">CAN_F7R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga2ab1b958322e9e8924570497657ef396"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1422787fd4beb2c5679f45908214fd6" id="r_gaf1422787fd4beb2c5679f45908214fd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1422787fd4beb2c5679f45908214fd6">CAN_F7R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ab1b958322e9e8924570497657ef396">CAN_F7R1_FB19_Pos</a>)</td></tr>
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<tr class="memitem:gaf40a4dd0979fb7ffba4b4192fe6dde5f" id="r_gaf40a4dd0979fb7ffba4b4192fe6dde5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf40a4dd0979fb7ffba4b4192fe6dde5f">CAN_F7R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1422787fd4beb2c5679f45908214fd6">CAN_F7R1_FB19_Msk</a></td></tr>
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<tr class="separator:gaf40a4dd0979fb7ffba4b4192fe6dde5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga638a9090ca2ae17ea3d000deca166de3" id="r_ga638a9090ca2ae17ea3d000deca166de3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga638a9090ca2ae17ea3d000deca166de3">CAN_F7R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga638a9090ca2ae17ea3d000deca166de3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad71fb64ea19cf98ac384fed6babe5fdc" id="r_gad71fb64ea19cf98ac384fed6babe5fdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad71fb64ea19cf98ac384fed6babe5fdc">CAN_F7R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga638a9090ca2ae17ea3d000deca166de3">CAN_F7R1_FB20_Pos</a>)</td></tr>
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<tr class="separator:gad71fb64ea19cf98ac384fed6babe5fdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5854aa102655334a6242e43c0b25aede" id="r_ga5854aa102655334a6242e43c0b25aede"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5854aa102655334a6242e43c0b25aede">CAN_F7R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad71fb64ea19cf98ac384fed6babe5fdc">CAN_F7R1_FB20_Msk</a></td></tr>
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<tr class="separator:ga5854aa102655334a6242e43c0b25aede"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacf70e06346fa4c3754533c7743bd04f" id="r_gaacf70e06346fa4c3754533c7743bd04f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacf70e06346fa4c3754533c7743bd04f">CAN_F7R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gaacf70e06346fa4c3754533c7743bd04f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c1d29a629499734298ff81b9892cb0a" id="r_ga5c1d29a629499734298ff81b9892cb0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c1d29a629499734298ff81b9892cb0a">CAN_F7R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaacf70e06346fa4c3754533c7743bd04f">CAN_F7R1_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga5c1d29a629499734298ff81b9892cb0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga505dbdeaf89d103795046fb689b81664" id="r_ga505dbdeaf89d103795046fb689b81664"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga505dbdeaf89d103795046fb689b81664">CAN_F7R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c1d29a629499734298ff81b9892cb0a">CAN_F7R1_FB21_Msk</a></td></tr>
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<tr class="separator:ga505dbdeaf89d103795046fb689b81664"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcea76ba56f67ee953e46d4a2730b36a" id="r_gafcea76ba56f67ee953e46d4a2730b36a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcea76ba56f67ee953e46d4a2730b36a">CAN_F7R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gafcea76ba56f67ee953e46d4a2730b36a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4535f6c9da894cc9ef7a6ba6f6bc6525" id="r_ga4535f6c9da894cc9ef7a6ba6f6bc6525"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4535f6c9da894cc9ef7a6ba6f6bc6525">CAN_F7R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcea76ba56f67ee953e46d4a2730b36a">CAN_F7R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga4535f6c9da894cc9ef7a6ba6f6bc6525"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga692f7a0bbc73be14e9d554394dceb176" id="r_ga692f7a0bbc73be14e9d554394dceb176"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga692f7a0bbc73be14e9d554394dceb176">CAN_F7R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4535f6c9da894cc9ef7a6ba6f6bc6525">CAN_F7R1_FB22_Msk</a></td></tr>
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<tr class="separator:ga692f7a0bbc73be14e9d554394dceb176"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4853c3d121f3c2d11833d11b395e0038" id="r_ga4853c3d121f3c2d11833d11b395e0038"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4853c3d121f3c2d11833d11b395e0038">CAN_F7R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga4853c3d121f3c2d11833d11b395e0038"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14b9c180bade4dad957697b4f5b4354f" id="r_ga14b9c180bade4dad957697b4f5b4354f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9c180bade4dad957697b4f5b4354f">CAN_F7R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4853c3d121f3c2d11833d11b395e0038">CAN_F7R1_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga14b9c180bade4dad957697b4f5b4354f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a93f243e7acf3f749f2b6ec8ae7bc5f" id="r_ga5a93f243e7acf3f749f2b6ec8ae7bc5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a93f243e7acf3f749f2b6ec8ae7bc5f">CAN_F7R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9c180bade4dad957697b4f5b4354f">CAN_F7R1_FB23_Msk</a></td></tr>
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<tr class="separator:ga5a93f243e7acf3f749f2b6ec8ae7bc5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c2567b1837c81aba2759686438547cc" id="r_ga3c2567b1837c81aba2759686438547cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c2567b1837c81aba2759686438547cc">CAN_F7R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga347cad693a28b872fe402439c9548f35" id="r_ga347cad693a28b872fe402439c9548f35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga347cad693a28b872fe402439c9548f35">CAN_F7R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c2567b1837c81aba2759686438547cc">CAN_F7R1_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga347cad693a28b872fe402439c9548f35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68815c969c231268a63c8809a55bc866" id="r_ga68815c969c231268a63c8809a55bc866"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68815c969c231268a63c8809a55bc866">CAN_F7R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga347cad693a28b872fe402439c9548f35">CAN_F7R1_FB24_Msk</a></td></tr>
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<tr class="separator:ga68815c969c231268a63c8809a55bc866"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5867f7e9cb965e6a3768f6bb02f080e" id="r_gab5867f7e9cb965e6a3768f6bb02f080e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5867f7e9cb965e6a3768f6bb02f080e">CAN_F7R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gab5867f7e9cb965e6a3768f6bb02f080e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2aefee2f7b7c851315fd09a2ef4df5ed" id="r_ga2aefee2f7b7c851315fd09a2ef4df5ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2aefee2f7b7c851315fd09a2ef4df5ed">CAN_F7R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5867f7e9cb965e6a3768f6bb02f080e">CAN_F7R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga2aefee2f7b7c851315fd09a2ef4df5ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7055881b4a6d9fe51e8dcfb99a546139" id="r_ga7055881b4a6d9fe51e8dcfb99a546139"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7055881b4a6d9fe51e8dcfb99a546139">CAN_F7R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2aefee2f7b7c851315fd09a2ef4df5ed">CAN_F7R1_FB25_Msk</a></td></tr>
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<tr class="separator:ga7055881b4a6d9fe51e8dcfb99a546139"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb741309bad1c9aef3ede7c187c05a92" id="r_gaeb741309bad1c9aef3ede7c187c05a92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb741309bad1c9aef3ede7c187c05a92">CAN_F7R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:gaeb741309bad1c9aef3ede7c187c05a92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ae7335a105fc044215160bdafda2485" id="r_ga8ae7335a105fc044215160bdafda2485"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ae7335a105fc044215160bdafda2485">CAN_F7R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb741309bad1c9aef3ede7c187c05a92">CAN_F7R1_FB26_Pos</a>)</td></tr>
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<tr class="memitem:ga19ab918d9499635e8199a143833c6fdb" id="r_ga19ab918d9499635e8199a143833c6fdb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19ab918d9499635e8199a143833c6fdb">CAN_F7R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ae7335a105fc044215160bdafda2485">CAN_F7R1_FB26_Msk</a></td></tr>
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<tr class="memitem:gadae02d56cf4acb7e92586c65c2da805d" id="r_gadae02d56cf4acb7e92586c65c2da805d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadae02d56cf4acb7e92586c65c2da805d">CAN_F7R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="memitem:gaf1f9cbef574790752e5579402adbfcf9" id="r_gaf1f9cbef574790752e5579402adbfcf9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1f9cbef574790752e5579402adbfcf9">CAN_F7R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadae02d56cf4acb7e92586c65c2da805d">CAN_F7R1_FB27_Pos</a>)</td></tr>
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<tr class="memitem:ga8360f2a2ba21a1b2f361d4330026edfd" id="r_ga8360f2a2ba21a1b2f361d4330026edfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8360f2a2ba21a1b2f361d4330026edfd">CAN_F7R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1f9cbef574790752e5579402adbfcf9">CAN_F7R1_FB27_Msk</a></td></tr>
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<tr class="separator:ga8360f2a2ba21a1b2f361d4330026edfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab06f238fd2c787b94e9022a874f0e4f7" id="r_gab06f238fd2c787b94e9022a874f0e4f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab06f238fd2c787b94e9022a874f0e4f7">CAN_F7R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="memitem:gab5accb398c1b8d49f33264729b9248ba" id="r_gab5accb398c1b8d49f33264729b9248ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5accb398c1b8d49f33264729b9248ba">CAN_F7R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab06f238fd2c787b94e9022a874f0e4f7">CAN_F7R1_FB28_Pos</a>)</td></tr>
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<tr class="separator:gab5accb398c1b8d49f33264729b9248ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga681e922052442801310265bab7356fc4" id="r_ga681e922052442801310265bab7356fc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga681e922052442801310265bab7356fc4">CAN_F7R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab5accb398c1b8d49f33264729b9248ba">CAN_F7R1_FB28_Msk</a></td></tr>
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<tr class="separator:ga681e922052442801310265bab7356fc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec347619871661fb58366eb358f0d3c8" id="r_gaec347619871661fb58366eb358f0d3c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec347619871661fb58366eb358f0d3c8">CAN_F7R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="memitem:gaed2a0882ce4432f84db55f3f699cbd93" id="r_gaed2a0882ce4432f84db55f3f699cbd93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed2a0882ce4432f84db55f3f699cbd93">CAN_F7R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaec347619871661fb58366eb358f0d3c8">CAN_F7R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:gaed2a0882ce4432f84db55f3f699cbd93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab12aa3a716a85bf96a1496ecaeae0cec" id="r_gab12aa3a716a85bf96a1496ecaeae0cec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab12aa3a716a85bf96a1496ecaeae0cec">CAN_F7R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaed2a0882ce4432f84db55f3f699cbd93">CAN_F7R1_FB29_Msk</a></td></tr>
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<tr class="separator:gab12aa3a716a85bf96a1496ecaeae0cec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga920c885a992444b856bc4df2862f44ae" id="r_ga920c885a992444b856bc4df2862f44ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga920c885a992444b856bc4df2862f44ae">CAN_F7R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga920c885a992444b856bc4df2862f44ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63bedd413e3ab8e91f9d779ef40e45b5" id="r_ga63bedd413e3ab8e91f9d779ef40e45b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63bedd413e3ab8e91f9d779ef40e45b5">CAN_F7R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga920c885a992444b856bc4df2862f44ae">CAN_F7R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga63bedd413e3ab8e91f9d779ef40e45b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6774583920f7cd42976daa4cf389eff3" id="r_ga6774583920f7cd42976daa4cf389eff3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6774583920f7cd42976daa4cf389eff3">CAN_F7R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63bedd413e3ab8e91f9d779ef40e45b5">CAN_F7R1_FB30_Msk</a></td></tr>
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<tr class="separator:ga6774583920f7cd42976daa4cf389eff3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga099ccfbf473ed4897db9b4d16ac3c150" id="r_ga099ccfbf473ed4897db9b4d16ac3c150"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga099ccfbf473ed4897db9b4d16ac3c150">CAN_F7R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga099ccfbf473ed4897db9b4d16ac3c150"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa85d8f6af8cfade40eaef271291512ef" id="r_gaa85d8f6af8cfade40eaef271291512ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa85d8f6af8cfade40eaef271291512ef">CAN_F7R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga099ccfbf473ed4897db9b4d16ac3c150">CAN_F7R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:gaa85d8f6af8cfade40eaef271291512ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9990b9fd20bbe0ff114acace0cb47ad7" id="r_ga9990b9fd20bbe0ff114acace0cb47ad7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9990b9fd20bbe0ff114acace0cb47ad7">CAN_F7R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa85d8f6af8cfade40eaef271291512ef">CAN_F7R1_FB31_Msk</a></td></tr>
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<tr class="separator:ga9990b9fd20bbe0ff114acace0cb47ad7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e21006790f44d0394235edb9533fe9f" id="r_ga2e21006790f44d0394235edb9533fe9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e21006790f44d0394235edb9533fe9f">CAN_F8R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2e21006790f44d0394235edb9533fe9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43a1537e2aeed84464aed2c398cb24c5" id="r_ga43a1537e2aeed84464aed2c398cb24c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43a1537e2aeed84464aed2c398cb24c5">CAN_F8R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e21006790f44d0394235edb9533fe9f">CAN_F8R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga43a1537e2aeed84464aed2c398cb24c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13cd870005a4712c3a8b9675a962c642" id="r_ga13cd870005a4712c3a8b9675a962c642"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13cd870005a4712c3a8b9675a962c642">CAN_F8R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga43a1537e2aeed84464aed2c398cb24c5">CAN_F8R1_FB0_Msk</a></td></tr>
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<tr class="separator:ga13cd870005a4712c3a8b9675a962c642"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab537c0b3bf184ffb31d73312facd8d44" id="r_gab537c0b3bf184ffb31d73312facd8d44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab537c0b3bf184ffb31d73312facd8d44">CAN_F8R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gab537c0b3bf184ffb31d73312facd8d44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga136ab0937c4919934d7dc1185d3c4064" id="r_ga136ab0937c4919934d7dc1185d3c4064"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga136ab0937c4919934d7dc1185d3c4064">CAN_F8R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab537c0b3bf184ffb31d73312facd8d44">CAN_F8R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga136ab0937c4919934d7dc1185d3c4064"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49082d55960382ded8b2f7235dd3b33d" id="r_ga49082d55960382ded8b2f7235dd3b33d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49082d55960382ded8b2f7235dd3b33d">CAN_F8R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga136ab0937c4919934d7dc1185d3c4064">CAN_F8R1_FB1_Msk</a></td></tr>
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<tr class="separator:ga49082d55960382ded8b2f7235dd3b33d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d30a98a695d270dbff8e07b9079e5d8" id="r_ga6d30a98a695d270dbff8e07b9079e5d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d30a98a695d270dbff8e07b9079e5d8">CAN_F8R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga6d30a98a695d270dbff8e07b9079e5d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9fac3bd96ed91e471081a51b6b08ca3" id="r_gab9fac3bd96ed91e471081a51b6b08ca3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9fac3bd96ed91e471081a51b6b08ca3">CAN_F8R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d30a98a695d270dbff8e07b9079e5d8">CAN_F8R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:gab9fac3bd96ed91e471081a51b6b08ca3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdb99f376b40d3933ce6a28ad31f496a" id="r_gafdb99f376b40d3933ce6a28ad31f496a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdb99f376b40d3933ce6a28ad31f496a">CAN_F8R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9fac3bd96ed91e471081a51b6b08ca3">CAN_F8R1_FB2_Msk</a></td></tr>
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<tr class="separator:gafdb99f376b40d3933ce6a28ad31f496a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1894d0455f9488198430c70db97c865" id="r_gaa1894d0455f9488198430c70db97c865"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1894d0455f9488198430c70db97c865">CAN_F8R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaa1894d0455f9488198430c70db97c865"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5b9c8ec036840da8f0b04aaa715d031" id="r_gaa5b9c8ec036840da8f0b04aaa715d031"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5b9c8ec036840da8f0b04aaa715d031">CAN_F8R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1894d0455f9488198430c70db97c865">CAN_F8R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:gaa5b9c8ec036840da8f0b04aaa715d031"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cd97fc37fa6ffadbb7af4f9ddf1d014" id="r_ga2cd97fc37fa6ffadbb7af4f9ddf1d014"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cd97fc37fa6ffadbb7af4f9ddf1d014">CAN_F8R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5b9c8ec036840da8f0b04aaa715d031">CAN_F8R1_FB3_Msk</a></td></tr>
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<tr class="separator:ga2cd97fc37fa6ffadbb7af4f9ddf1d014"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a0ded25fe64917e6868d95b1d468771" id="r_ga1a0ded25fe64917e6868d95b1d468771"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a0ded25fe64917e6868d95b1d468771">CAN_F8R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga1a0ded25fe64917e6868d95b1d468771"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9829df8a13336ccf61d59be6c282d52" id="r_gab9829df8a13336ccf61d59be6c282d52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9829df8a13336ccf61d59be6c282d52">CAN_F8R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a0ded25fe64917e6868d95b1d468771">CAN_F8R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:gab9829df8a13336ccf61d59be6c282d52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5842614b55172086992fc085955168d7" id="r_ga5842614b55172086992fc085955168d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5842614b55172086992fc085955168d7">CAN_F8R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9829df8a13336ccf61d59be6c282d52">CAN_F8R1_FB4_Msk</a></td></tr>
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<tr class="separator:ga5842614b55172086992fc085955168d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5792df4298b71222586c057d8c783ed2" id="r_ga5792df4298b71222586c057d8c783ed2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5792df4298b71222586c057d8c783ed2">CAN_F8R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga5792df4298b71222586c057d8c783ed2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70d67631dbfe1a1f15fb712df7cca4d8" id="r_ga70d67631dbfe1a1f15fb712df7cca4d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70d67631dbfe1a1f15fb712df7cca4d8">CAN_F8R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5792df4298b71222586c057d8c783ed2">CAN_F8R1_FB5_Pos</a>)</td></tr>
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<tr class="memitem:ga373c77cab88912e816a6e12195bd3205" id="r_ga373c77cab88912e816a6e12195bd3205"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga373c77cab88912e816a6e12195bd3205">CAN_F8R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga70d67631dbfe1a1f15fb712df7cca4d8">CAN_F8R1_FB5_Msk</a></td></tr>
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<tr class="memitem:ga28d2bdc498bb762e71c06682ddcffcd0" id="r_ga28d2bdc498bb762e71c06682ddcffcd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28d2bdc498bb762e71c06682ddcffcd0">CAN_F8R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="memitem:gaf1d9da45066db64dcc7b6d6ea9d8d3f8" id="r_gaf1d9da45066db64dcc7b6d6ea9d8d3f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1d9da45066db64dcc7b6d6ea9d8d3f8">CAN_F8R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga28d2bdc498bb762e71c06682ddcffcd0">CAN_F8R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:gaf1d9da45066db64dcc7b6d6ea9d8d3f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5937607627dd44c4fb79f9063534e2b1" id="r_ga5937607627dd44c4fb79f9063534e2b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5937607627dd44c4fb79f9063534e2b1">CAN_F8R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1d9da45066db64dcc7b6d6ea9d8d3f8">CAN_F8R1_FB6_Msk</a></td></tr>
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<tr class="separator:ga5937607627dd44c4fb79f9063534e2b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40a3d24b2ddf64251f6257500549eb78" id="r_ga40a3d24b2ddf64251f6257500549eb78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40a3d24b2ddf64251f6257500549eb78">CAN_F8R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga40a3d24b2ddf64251f6257500549eb78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14a2fe60539e333588226dbc4de4fffa" id="r_ga14a2fe60539e333588226dbc4de4fffa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14a2fe60539e333588226dbc4de4fffa">CAN_F8R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga40a3d24b2ddf64251f6257500549eb78">CAN_F8R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga14a2fe60539e333588226dbc4de4fffa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b6765194a47f1a6d7dfbf78e0b4139c" id="r_ga5b6765194a47f1a6d7dfbf78e0b4139c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b6765194a47f1a6d7dfbf78e0b4139c">CAN_F8R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga14a2fe60539e333588226dbc4de4fffa">CAN_F8R1_FB7_Msk</a></td></tr>
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<tr class="separator:ga5b6765194a47f1a6d7dfbf78e0b4139c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc32c5836d51b1c7aa00509af2f84335" id="r_gabc32c5836d51b1c7aa00509af2f84335"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc32c5836d51b1c7aa00509af2f84335">CAN_F8R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gabc32c5836d51b1c7aa00509af2f84335"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f57e77aa8ea032bc07463d82e451e1b" id="r_ga3f57e77aa8ea032bc07463d82e451e1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f57e77aa8ea032bc07463d82e451e1b">CAN_F8R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc32c5836d51b1c7aa00509af2f84335">CAN_F8R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga3f57e77aa8ea032bc07463d82e451e1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa79159b413994d12b593cc4f1b23d1fa" id="r_gaa79159b413994d12b593cc4f1b23d1fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa79159b413994d12b593cc4f1b23d1fa">CAN_F8R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f57e77aa8ea032bc07463d82e451e1b">CAN_F8R1_FB8_Msk</a></td></tr>
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<tr class="separator:gaa79159b413994d12b593cc4f1b23d1fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33e709811995d99e00d150e9bc96fa27" id="r_ga33e709811995d99e00d150e9bc96fa27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33e709811995d99e00d150e9bc96fa27">CAN_F8R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga33e709811995d99e00d150e9bc96fa27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab30a05da2419398ee1eb3cc0d0c468f3" id="r_gab30a05da2419398ee1eb3cc0d0c468f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab30a05da2419398ee1eb3cc0d0c468f3">CAN_F8R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga33e709811995d99e00d150e9bc96fa27">CAN_F8R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:gab30a05da2419398ee1eb3cc0d0c468f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b959e903cdac33f5da71aa5c7477a0d" id="r_ga2b959e903cdac33f5da71aa5c7477a0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b959e903cdac33f5da71aa5c7477a0d">CAN_F8R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab30a05da2419398ee1eb3cc0d0c468f3">CAN_F8R1_FB9_Msk</a></td></tr>
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<tr class="separator:ga2b959e903cdac33f5da71aa5c7477a0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9d988713272210141906dbbf7c86e9a" id="r_gad9d988713272210141906dbbf7c86e9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9d988713272210141906dbbf7c86e9a">CAN_F8R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gad9d988713272210141906dbbf7c86e9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga250ae96856872467bd01177a14cbd757" id="r_ga250ae96856872467bd01177a14cbd757"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga250ae96856872467bd01177a14cbd757">CAN_F8R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9d988713272210141906dbbf7c86e9a">CAN_F8R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga250ae96856872467bd01177a14cbd757"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5de7f304ca7bfcb9e78c9c2d346d300" id="r_gab5de7f304ca7bfcb9e78c9c2d346d300"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5de7f304ca7bfcb9e78c9c2d346d300">CAN_F8R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga250ae96856872467bd01177a14cbd757">CAN_F8R1_FB10_Msk</a></td></tr>
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<tr class="separator:gab5de7f304ca7bfcb9e78c9c2d346d300"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b1a8d858999311a306e931621b57f21" id="r_ga0b1a8d858999311a306e931621b57f21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b1a8d858999311a306e931621b57f21">CAN_F8R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga0b1a8d858999311a306e931621b57f21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f936dea8e23ad47f01a690e3144442c" id="r_ga8f936dea8e23ad47f01a690e3144442c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f936dea8e23ad47f01a690e3144442c">CAN_F8R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b1a8d858999311a306e931621b57f21">CAN_F8R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga8f936dea8e23ad47f01a690e3144442c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d5a19fa7032ef2b68e2feebd0db15e6" id="r_ga0d5a19fa7032ef2b68e2feebd0db15e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d5a19fa7032ef2b68e2feebd0db15e6">CAN_F8R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f936dea8e23ad47f01a690e3144442c">CAN_F8R1_FB11_Msk</a></td></tr>
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<tr class="separator:ga0d5a19fa7032ef2b68e2feebd0db15e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6dee94be5857587a290a91b8e69ebd75" id="r_ga6dee94be5857587a290a91b8e69ebd75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6dee94be5857587a290a91b8e69ebd75">CAN_F8R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga6dee94be5857587a290a91b8e69ebd75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad340588e0f2e4424892bf86a3df02297" id="r_gad340588e0f2e4424892bf86a3df02297"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad340588e0f2e4424892bf86a3df02297">CAN_F8R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6dee94be5857587a290a91b8e69ebd75">CAN_F8R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:gad340588e0f2e4424892bf86a3df02297"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga943a685663474ed7aa509eaccbda2ffb" id="r_ga943a685663474ed7aa509eaccbda2ffb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga943a685663474ed7aa509eaccbda2ffb">CAN_F8R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad340588e0f2e4424892bf86a3df02297">CAN_F8R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga943a685663474ed7aa509eaccbda2ffb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa36fb31c4e4460571555e84cb306cf0" id="r_gaaa36fb31c4e4460571555e84cb306cf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa36fb31c4e4460571555e84cb306cf0">CAN_F8R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaaa36fb31c4e4460571555e84cb306cf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38c0634095cd3178f8b2836d6855d3f3" id="r_ga38c0634095cd3178f8b2836d6855d3f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38c0634095cd3178f8b2836d6855d3f3">CAN_F8R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa36fb31c4e4460571555e84cb306cf0">CAN_F8R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga38c0634095cd3178f8b2836d6855d3f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga668cb8a75c4166b5287a09ba98c8ec70" id="r_ga668cb8a75c4166b5287a09ba98c8ec70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga668cb8a75c4166b5287a09ba98c8ec70">CAN_F8R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38c0634095cd3178f8b2836d6855d3f3">CAN_F8R1_FB13_Msk</a></td></tr>
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<tr class="separator:ga668cb8a75c4166b5287a09ba98c8ec70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6c42fee1e932aebc586aa5cfa634be5" id="r_gaf6c42fee1e932aebc586aa5cfa634be5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6c42fee1e932aebc586aa5cfa634be5">CAN_F8R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gaf6c42fee1e932aebc586aa5cfa634be5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac0c83e006384165f5d1cb982728cc50" id="r_gaac0c83e006384165f5d1cb982728cc50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac0c83e006384165f5d1cb982728cc50">CAN_F8R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6c42fee1e932aebc586aa5cfa634be5">CAN_F8R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:gaac0c83e006384165f5d1cb982728cc50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84727d6a0fdcb2870529d7a371a0b660" id="r_ga84727d6a0fdcb2870529d7a371a0b660"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84727d6a0fdcb2870529d7a371a0b660">CAN_F8R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac0c83e006384165f5d1cb982728cc50">CAN_F8R1_FB14_Msk</a></td></tr>
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<tr class="separator:ga84727d6a0fdcb2870529d7a371a0b660"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b62ff2f6a779932be13dfa2eba51c8c" id="r_ga1b62ff2f6a779932be13dfa2eba51c8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b62ff2f6a779932be13dfa2eba51c8c">CAN_F8R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga1b62ff2f6a779932be13dfa2eba51c8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42f23b1489ef4904d4f0a629f4fff1da" id="r_ga42f23b1489ef4904d4f0a629f4fff1da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42f23b1489ef4904d4f0a629f4fff1da">CAN_F8R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b62ff2f6a779932be13dfa2eba51c8c">CAN_F8R1_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga42f23b1489ef4904d4f0a629f4fff1da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9eb9c851eb03c49bc02f686aee490a28" id="r_ga9eb9c851eb03c49bc02f686aee490a28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9eb9c851eb03c49bc02f686aee490a28">CAN_F8R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga42f23b1489ef4904d4f0a629f4fff1da">CAN_F8R1_FB15_Msk</a></td></tr>
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<tr class="separator:ga9eb9c851eb03c49bc02f686aee490a28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab6b2bfaa28bb99475c1ffe09c55bedb" id="r_gaab6b2bfaa28bb99475c1ffe09c55bedb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab6b2bfaa28bb99475c1ffe09c55bedb">CAN_F8R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaab6b2bfaa28bb99475c1ffe09c55bedb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98a05e0a87d907888aed8f07c72d00f9" id="r_ga98a05e0a87d907888aed8f07c72d00f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98a05e0a87d907888aed8f07c72d00f9">CAN_F8R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab6b2bfaa28bb99475c1ffe09c55bedb">CAN_F8R1_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga98a05e0a87d907888aed8f07c72d00f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ccc46770c70da8546bbbcf492bcdd95" id="r_ga4ccc46770c70da8546bbbcf492bcdd95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ccc46770c70da8546bbbcf492bcdd95">CAN_F8R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga98a05e0a87d907888aed8f07c72d00f9">CAN_F8R1_FB16_Msk</a></td></tr>
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<tr class="separator:ga4ccc46770c70da8546bbbcf492bcdd95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3e73d311df6235cbf5fc02a800628db" id="r_gae3e73d311df6235cbf5fc02a800628db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3e73d311df6235cbf5fc02a800628db">CAN_F8R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="memitem:ga0b5980d9a8107fa12b63f1ee0abe74cd" id="r_ga0b5980d9a8107fa12b63f1ee0abe74cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b5980d9a8107fa12b63f1ee0abe74cd">CAN_F8R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3e73d311df6235cbf5fc02a800628db">CAN_F8R1_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga0b5980d9a8107fa12b63f1ee0abe74cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf24b0628e89b2c27cb9e13b0492876eb" id="r_gaf24b0628e89b2c27cb9e13b0492876eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf24b0628e89b2c27cb9e13b0492876eb">CAN_F8R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b5980d9a8107fa12b63f1ee0abe74cd">CAN_F8R1_FB17_Msk</a></td></tr>
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<tr class="separator:gaf24b0628e89b2c27cb9e13b0492876eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf59f6130156da5081b0eee3acb154374" id="r_gaf59f6130156da5081b0eee3acb154374"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf59f6130156da5081b0eee3acb154374">CAN_F8R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:gaf59f6130156da5081b0eee3acb154374"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae850211d9876f0063e13b5610cf8ac65" id="r_gae850211d9876f0063e13b5610cf8ac65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae850211d9876f0063e13b5610cf8ac65">CAN_F8R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf59f6130156da5081b0eee3acb154374">CAN_F8R1_FB18_Pos</a>)</td></tr>
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<tr class="memitem:ga36b946c123c3c3f1cdbd1272db24c58b" id="r_ga36b946c123c3c3f1cdbd1272db24c58b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36b946c123c3c3f1cdbd1272db24c58b">CAN_F8R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae850211d9876f0063e13b5610cf8ac65">CAN_F8R1_FB18_Msk</a></td></tr>
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<tr class="separator:ga36b946c123c3c3f1cdbd1272db24c58b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fe27087a9da8f3202a319dbaf07b6d6" id="r_ga0fe27087a9da8f3202a319dbaf07b6d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fe27087a9da8f3202a319dbaf07b6d6">CAN_F8R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga0fe27087a9da8f3202a319dbaf07b6d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga666296673c08dd22ca95dab553d430ef" id="r_ga666296673c08dd22ca95dab553d430ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga666296673c08dd22ca95dab553d430ef">CAN_F8R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0fe27087a9da8f3202a319dbaf07b6d6">CAN_F8R1_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga666296673c08dd22ca95dab553d430ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab91129b8b7746111a31a968c1f1a8b19" id="r_gab91129b8b7746111a31a968c1f1a8b19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab91129b8b7746111a31a968c1f1a8b19">CAN_F8R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga666296673c08dd22ca95dab553d430ef">CAN_F8R1_FB19_Msk</a></td></tr>
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<tr class="separator:gab91129b8b7746111a31a968c1f1a8b19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55046c532cef29a6df857a821d8d9750" id="r_ga55046c532cef29a6df857a821d8d9750"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55046c532cef29a6df857a821d8d9750">CAN_F8R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga55046c532cef29a6df857a821d8d9750"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82b241f62e465fede05a749af4f6d46d" id="r_ga82b241f62e465fede05a749af4f6d46d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82b241f62e465fede05a749af4f6d46d">CAN_F8R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55046c532cef29a6df857a821d8d9750">CAN_F8R1_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga82b241f62e465fede05a749af4f6d46d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19663b29868ae926896961451768d748" id="r_ga19663b29868ae926896961451768d748"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19663b29868ae926896961451768d748">CAN_F8R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga82b241f62e465fede05a749af4f6d46d">CAN_F8R1_FB20_Msk</a></td></tr>
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<tr class="separator:ga19663b29868ae926896961451768d748"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef11cb2b0be6f8a07ca34699c89a7098" id="r_gaef11cb2b0be6f8a07ca34699c89a7098"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef11cb2b0be6f8a07ca34699c89a7098">CAN_F8R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gaef11cb2b0be6f8a07ca34699c89a7098"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga894777fbc3a4cfc64d779ee1bb28447a" id="r_ga894777fbc3a4cfc64d779ee1bb28447a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga894777fbc3a4cfc64d779ee1bb28447a">CAN_F8R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef11cb2b0be6f8a07ca34699c89a7098">CAN_F8R1_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga894777fbc3a4cfc64d779ee1bb28447a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19d8c89621a78de5177481d217bb5033" id="r_ga19d8c89621a78de5177481d217bb5033"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19d8c89621a78de5177481d217bb5033">CAN_F8R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga894777fbc3a4cfc64d779ee1bb28447a">CAN_F8R1_FB21_Msk</a></td></tr>
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<tr class="separator:ga19d8c89621a78de5177481d217bb5033"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44d6b1387dd6af3f5f6ad71dc57738bb" id="r_ga44d6b1387dd6af3f5f6ad71dc57738bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44d6b1387dd6af3f5f6ad71dc57738bb">CAN_F8R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga44d6b1387dd6af3f5f6ad71dc57738bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95a971879dd5369d39b1b5a2d55af7f2" id="r_ga95a971879dd5369d39b1b5a2d55af7f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95a971879dd5369d39b1b5a2d55af7f2">CAN_F8R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga44d6b1387dd6af3f5f6ad71dc57738bb">CAN_F8R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga95a971879dd5369d39b1b5a2d55af7f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab265fadfeb8674b869264ad25bedcac4" id="r_gab265fadfeb8674b869264ad25bedcac4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab265fadfeb8674b869264ad25bedcac4">CAN_F8R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga95a971879dd5369d39b1b5a2d55af7f2">CAN_F8R1_FB22_Msk</a></td></tr>
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<tr class="separator:gab265fadfeb8674b869264ad25bedcac4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga928556e1ce80afd85bc49deca2f1dc2a" id="r_ga928556e1ce80afd85bc49deca2f1dc2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga928556e1ce80afd85bc49deca2f1dc2a">CAN_F8R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga928556e1ce80afd85bc49deca2f1dc2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c136499422980d6a619619b67024115" id="r_ga7c136499422980d6a619619b67024115"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c136499422980d6a619619b67024115">CAN_F8R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga928556e1ce80afd85bc49deca2f1dc2a">CAN_F8R1_FB23_Pos</a>)</td></tr>
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<tr class="memitem:ga102fdb92fecd6aa86e5dbd2fea2b2e79" id="r_ga102fdb92fecd6aa86e5dbd2fea2b2e79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga102fdb92fecd6aa86e5dbd2fea2b2e79">CAN_F8R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c136499422980d6a619619b67024115">CAN_F8R1_FB23_Msk</a></td></tr>
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<tr class="separator:ga102fdb92fecd6aa86e5dbd2fea2b2e79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6287f1cbffc6c85b5a8c540bdd238dd1" id="r_ga6287f1cbffc6c85b5a8c540bdd238dd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6287f1cbffc6c85b5a8c540bdd238dd1">CAN_F8R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga6287f1cbffc6c85b5a8c540bdd238dd1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5cb63c9cc186f5a6a188e50e9440b71" id="r_gad5cb63c9cc186f5a6a188e50e9440b71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5cb63c9cc186f5a6a188e50e9440b71">CAN_F8R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6287f1cbffc6c85b5a8c540bdd238dd1">CAN_F8R1_FB24_Pos</a>)</td></tr>
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<tr class="separator:gad5cb63c9cc186f5a6a188e50e9440b71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b73f4ab4941e6d920e75f7197ed025b" id="r_ga0b73f4ab4941e6d920e75f7197ed025b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b73f4ab4941e6d920e75f7197ed025b">CAN_F8R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad5cb63c9cc186f5a6a188e50e9440b71">CAN_F8R1_FB24_Msk</a></td></tr>
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<tr class="separator:ga0b73f4ab4941e6d920e75f7197ed025b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b42664c93972b8ceef0bb224465868a" id="r_ga5b42664c93972b8ceef0bb224465868a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b42664c93972b8ceef0bb224465868a">CAN_F8R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga5b42664c93972b8ceef0bb224465868a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad66fb66d8e41424f6a5df8645e889aed" id="r_gad66fb66d8e41424f6a5df8645e889aed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad66fb66d8e41424f6a5df8645e889aed">CAN_F8R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b42664c93972b8ceef0bb224465868a">CAN_F8R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:gad66fb66d8e41424f6a5df8645e889aed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d72a1b4728fa13d4a2a3f7478f8398b" id="r_ga9d72a1b4728fa13d4a2a3f7478f8398b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d72a1b4728fa13d4a2a3f7478f8398b">CAN_F8R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad66fb66d8e41424f6a5df8645e889aed">CAN_F8R1_FB25_Msk</a></td></tr>
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<tr class="separator:ga9d72a1b4728fa13d4a2a3f7478f8398b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4046289146213969c12a1a9c88756853" id="r_ga4046289146213969c12a1a9c88756853"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4046289146213969c12a1a9c88756853">CAN_F8R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga4046289146213969c12a1a9c88756853"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e4ac7b030b72119e7ff52cd7ed2c22b" id="r_ga4e4ac7b030b72119e7ff52cd7ed2c22b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e4ac7b030b72119e7ff52cd7ed2c22b">CAN_F8R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4046289146213969c12a1a9c88756853">CAN_F8R1_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga4e4ac7b030b72119e7ff52cd7ed2c22b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5826d272442cf9b69336172a039bc439" id="r_ga5826d272442cf9b69336172a039bc439"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5826d272442cf9b69336172a039bc439">CAN_F8R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e4ac7b030b72119e7ff52cd7ed2c22b">CAN_F8R1_FB26_Msk</a></td></tr>
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<tr class="separator:ga5826d272442cf9b69336172a039bc439"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32f7d4b16bb82b31e2fb4879e64a7632" id="r_ga32f7d4b16bb82b31e2fb4879e64a7632"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32f7d4b16bb82b31e2fb4879e64a7632">CAN_F8R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga32f7d4b16bb82b31e2fb4879e64a7632"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36df86343d04760bb4fef8b027e668d6" id="r_ga36df86343d04760bb4fef8b027e668d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36df86343d04760bb4fef8b027e668d6">CAN_F8R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga32f7d4b16bb82b31e2fb4879e64a7632">CAN_F8R1_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga36df86343d04760bb4fef8b027e668d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdb656881f89c0da122383403a816ce1" id="r_gacdb656881f89c0da122383403a816ce1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdb656881f89c0da122383403a816ce1">CAN_F8R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36df86343d04760bb4fef8b027e668d6">CAN_F8R1_FB27_Msk</a></td></tr>
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<tr class="separator:gacdb656881f89c0da122383403a816ce1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d24f22e4e970b13528482d65e0bcd21" id="r_ga7d24f22e4e970b13528482d65e0bcd21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d24f22e4e970b13528482d65e0bcd21">CAN_F8R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga7d24f22e4e970b13528482d65e0bcd21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga647ae349a353febc85e2d06384798e35" id="r_ga647ae349a353febc85e2d06384798e35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga647ae349a353febc85e2d06384798e35">CAN_F8R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d24f22e4e970b13528482d65e0bcd21">CAN_F8R1_FB28_Pos</a>)</td></tr>
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<tr class="separator:ga647ae349a353febc85e2d06384798e35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d8c536aab73553ff1913ba806be351c" id="r_ga2d8c536aab73553ff1913ba806be351c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d8c536aab73553ff1913ba806be351c">CAN_F8R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga647ae349a353febc85e2d06384798e35">CAN_F8R1_FB28_Msk</a></td></tr>
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<tr class="separator:ga2d8c536aab73553ff1913ba806be351c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga270dce4d4b698b43b0f9eed16a95b336" id="r_ga270dce4d4b698b43b0f9eed16a95b336"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga270dce4d4b698b43b0f9eed16a95b336">CAN_F8R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga270dce4d4b698b43b0f9eed16a95b336"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaddb3d32fc778601342a863d0a6612f5" id="r_gaaddb3d32fc778601342a863d0a6612f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaddb3d32fc778601342a863d0a6612f5">CAN_F8R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga270dce4d4b698b43b0f9eed16a95b336">CAN_F8R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:gaaddb3d32fc778601342a863d0a6612f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fb8328cdbf23c9982b769bd39a24113" id="r_ga8fb8328cdbf23c9982b769bd39a24113"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fb8328cdbf23c9982b769bd39a24113">CAN_F8R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaddb3d32fc778601342a863d0a6612f5">CAN_F8R1_FB29_Msk</a></td></tr>
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<tr class="separator:ga8fb8328cdbf23c9982b769bd39a24113"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ac7d47b043f02ea1fe15f4ed1ea69ea" id="r_ga1ac7d47b043f02ea1fe15f4ed1ea69ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ac7d47b043f02ea1fe15f4ed1ea69ea">CAN_F8R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga1ac7d47b043f02ea1fe15f4ed1ea69ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8cfc8c264df5fef0511b3cd66e459c3" id="r_gae8cfc8c264df5fef0511b3cd66e459c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8cfc8c264df5fef0511b3cd66e459c3">CAN_F8R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ac7d47b043f02ea1fe15f4ed1ea69ea">CAN_F8R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:gae8cfc8c264df5fef0511b3cd66e459c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78861665c78657330f9fcfc17283529f" id="r_ga78861665c78657330f9fcfc17283529f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78861665c78657330f9fcfc17283529f">CAN_F8R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae8cfc8c264df5fef0511b3cd66e459c3">CAN_F8R1_FB30_Msk</a></td></tr>
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<tr class="separator:ga78861665c78657330f9fcfc17283529f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85f280f7adb7d1b1f1a2fd964496d382" id="r_ga85f280f7adb7d1b1f1a2fd964496d382"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85f280f7adb7d1b1f1a2fd964496d382">CAN_F8R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga85f280f7adb7d1b1f1a2fd964496d382"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf1306a969e63813c78f15304cfeef9d" id="r_gacf1306a969e63813c78f15304cfeef9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf1306a969e63813c78f15304cfeef9d">CAN_F8R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga85f280f7adb7d1b1f1a2fd964496d382">CAN_F8R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:gacf1306a969e63813c78f15304cfeef9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b2fa38175302b2d91f2b45ae16c5db7" id="r_ga6b2fa38175302b2d91f2b45ae16c5db7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b2fa38175302b2d91f2b45ae16c5db7">CAN_F8R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacf1306a969e63813c78f15304cfeef9d">CAN_F8R1_FB31_Msk</a></td></tr>
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<tr class="separator:ga6b2fa38175302b2d91f2b45ae16c5db7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e408d4dcf2104036587654b320ef837" id="r_ga2e408d4dcf2104036587654b320ef837"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e408d4dcf2104036587654b320ef837">CAN_F9R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2e408d4dcf2104036587654b320ef837"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedc0e0cbb432679fb469888559cd8ba0" id="r_gaedc0e0cbb432679fb469888559cd8ba0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedc0e0cbb432679fb469888559cd8ba0">CAN_F9R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e408d4dcf2104036587654b320ef837">CAN_F9R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:gaedc0e0cbb432679fb469888559cd8ba0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga930a17d830cb9a95a79531dac2220785" id="r_ga930a17d830cb9a95a79531dac2220785"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga930a17d830cb9a95a79531dac2220785">CAN_F9R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaedc0e0cbb432679fb469888559cd8ba0">CAN_F9R1_FB0_Msk</a></td></tr>
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<tr class="separator:ga930a17d830cb9a95a79531dac2220785"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4b2c5ddbad8e4d30df6bae1553ae95f" id="r_gaf4b2c5ddbad8e4d30df6bae1553ae95f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4b2c5ddbad8e4d30df6bae1553ae95f">CAN_F9R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaf4b2c5ddbad8e4d30df6bae1553ae95f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga311d13b8b6763e76d9c889e49c7f5254" id="r_ga311d13b8b6763e76d9c889e49c7f5254"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga311d13b8b6763e76d9c889e49c7f5254">CAN_F9R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4b2c5ddbad8e4d30df6bae1553ae95f">CAN_F9R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga311d13b8b6763e76d9c889e49c7f5254"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8671eac978ebea75e6345adbcdf78026" id="r_ga8671eac978ebea75e6345adbcdf78026"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8671eac978ebea75e6345adbcdf78026">CAN_F9R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga311d13b8b6763e76d9c889e49c7f5254">CAN_F9R1_FB1_Msk</a></td></tr>
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<tr class="separator:ga8671eac978ebea75e6345adbcdf78026"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdac08de057f74084b0df1bdd49ffaa4" id="r_gacdac08de057f74084b0df1bdd49ffaa4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdac08de057f74084b0df1bdd49ffaa4">CAN_F9R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gacdac08de057f74084b0df1bdd49ffaa4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac66033af8f1d5f936090a464ef6af680" id="r_gac66033af8f1d5f936090a464ef6af680"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac66033af8f1d5f936090a464ef6af680">CAN_F9R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacdac08de057f74084b0df1bdd49ffaa4">CAN_F9R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:gac66033af8f1d5f936090a464ef6af680"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee3585fb5ee4081dffeb2a2dda1ce72f" id="r_gaee3585fb5ee4081dffeb2a2dda1ce72f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee3585fb5ee4081dffeb2a2dda1ce72f">CAN_F9R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac66033af8f1d5f936090a464ef6af680">CAN_F9R1_FB2_Msk</a></td></tr>
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<tr class="separator:gaee3585fb5ee4081dffeb2a2dda1ce72f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga693575c5b64ad798658952694e636204" id="r_ga693575c5b64ad798658952694e636204"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga693575c5b64ad798658952694e636204">CAN_F9R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga693575c5b64ad798658952694e636204"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bfd9933c0a4fb97ece209b9fcdfa794" id="r_ga4bfd9933c0a4fb97ece209b9fcdfa794"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bfd9933c0a4fb97ece209b9fcdfa794">CAN_F9R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga693575c5b64ad798658952694e636204">CAN_F9R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga4bfd9933c0a4fb97ece209b9fcdfa794"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga807e831fafa69e9df65618de855ea186" id="r_ga807e831fafa69e9df65618de855ea186"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga807e831fafa69e9df65618de855ea186">CAN_F9R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bfd9933c0a4fb97ece209b9fcdfa794">CAN_F9R1_FB3_Msk</a></td></tr>
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<tr class="separator:ga807e831fafa69e9df65618de855ea186"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga726f4f35552287c718dce9b5c46baba1" id="r_ga726f4f35552287c718dce9b5c46baba1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga726f4f35552287c718dce9b5c46baba1">CAN_F9R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga726f4f35552287c718dce9b5c46baba1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga362251d468d76c64459afc82f84acd06" id="r_ga362251d468d76c64459afc82f84acd06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga362251d468d76c64459afc82f84acd06">CAN_F9R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga726f4f35552287c718dce9b5c46baba1">CAN_F9R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga362251d468d76c64459afc82f84acd06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaddce646e28626a508b2f98c4f35148b3" id="r_gaddce646e28626a508b2f98c4f35148b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddce646e28626a508b2f98c4f35148b3">CAN_F9R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga362251d468d76c64459afc82f84acd06">CAN_F9R1_FB4_Msk</a></td></tr>
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<tr class="separator:gaddce646e28626a508b2f98c4f35148b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6064e11830367708fa478a64d6134471" id="r_ga6064e11830367708fa478a64d6134471"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6064e11830367708fa478a64d6134471">CAN_F9R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga6064e11830367708fa478a64d6134471"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9af391a698294bbcfd73e13d7bc3d45f" id="r_ga9af391a698294bbcfd73e13d7bc3d45f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9af391a698294bbcfd73e13d7bc3d45f">CAN_F9R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6064e11830367708fa478a64d6134471">CAN_F9R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga9af391a698294bbcfd73e13d7bc3d45f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ea72662e0243714ace5c0b48e7912f6" id="r_ga9ea72662e0243714ace5c0b48e7912f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ea72662e0243714ace5c0b48e7912f6">CAN_F9R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9af391a698294bbcfd73e13d7bc3d45f">CAN_F9R1_FB5_Msk</a></td></tr>
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<tr class="separator:ga9ea72662e0243714ace5c0b48e7912f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa48d9cd13e58139129678537b2a46a54" id="r_gaa48d9cd13e58139129678537b2a46a54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa48d9cd13e58139129678537b2a46a54">CAN_F9R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaa48d9cd13e58139129678537b2a46a54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf73980f9d3a6a660ab4b0742b849827" id="r_gadf73980f9d3a6a660ab4b0742b849827"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf73980f9d3a6a660ab4b0742b849827">CAN_F9R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa48d9cd13e58139129678537b2a46a54">CAN_F9R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:gadf73980f9d3a6a660ab4b0742b849827"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b08ddbc0bed91c6a1933e6485ded5e2" id="r_ga6b08ddbc0bed91c6a1933e6485ded5e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b08ddbc0bed91c6a1933e6485ded5e2">CAN_F9R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadf73980f9d3a6a660ab4b0742b849827">CAN_F9R1_FB6_Msk</a></td></tr>
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<tr class="separator:ga6b08ddbc0bed91c6a1933e6485ded5e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c12d5c48b26fa65b51d8978f372d235" id="r_ga7c12d5c48b26fa65b51d8978f372d235"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c12d5c48b26fa65b51d8978f372d235">CAN_F9R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga7c12d5c48b26fa65b51d8978f372d235"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93cc25aaf5401c7a3e16cb4609ee0e07" id="r_ga93cc25aaf5401c7a3e16cb4609ee0e07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93cc25aaf5401c7a3e16cb4609ee0e07">CAN_F9R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c12d5c48b26fa65b51d8978f372d235">CAN_F9R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga93cc25aaf5401c7a3e16cb4609ee0e07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae21fd9c8c790d4bc229c7ccb6d99dd36" id="r_gae21fd9c8c790d4bc229c7ccb6d99dd36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae21fd9c8c790d4bc229c7ccb6d99dd36">CAN_F9R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga93cc25aaf5401c7a3e16cb4609ee0e07">CAN_F9R1_FB7_Msk</a></td></tr>
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<tr class="separator:gae21fd9c8c790d4bc229c7ccb6d99dd36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fce8e9c5098084f4b4e9fffe064627c" id="r_ga8fce8e9c5098084f4b4e9fffe064627c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fce8e9c5098084f4b4e9fffe064627c">CAN_F9R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga8fce8e9c5098084f4b4e9fffe064627c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba01d797a4d055fe0a1af549c3fb4734" id="r_gaba01d797a4d055fe0a1af549c3fb4734"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba01d797a4d055fe0a1af549c3fb4734">CAN_F9R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fce8e9c5098084f4b4e9fffe064627c">CAN_F9R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:gaba01d797a4d055fe0a1af549c3fb4734"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf1a8f02576caccfddc12f2ead734762" id="r_gadf1a8f02576caccfddc12f2ead734762"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf1a8f02576caccfddc12f2ead734762">CAN_F9R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba01d797a4d055fe0a1af549c3fb4734">CAN_F9R1_FB8_Msk</a></td></tr>
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<tr class="separator:gadf1a8f02576caccfddc12f2ead734762"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f9d0da640c988023228da572b39189f" id="r_ga4f9d0da640c988023228da572b39189f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f9d0da640c988023228da572b39189f">CAN_F9R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga4f9d0da640c988023228da572b39189f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2e7a7ac6a91de762e00f6ccbde5c982" id="r_gac2e7a7ac6a91de762e00f6ccbde5c982"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2e7a7ac6a91de762e00f6ccbde5c982">CAN_F9R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f9d0da640c988023228da572b39189f">CAN_F9R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:gac2e7a7ac6a91de762e00f6ccbde5c982"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80a2594aaa275fd88225927e7115085b" id="r_ga80a2594aaa275fd88225927e7115085b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80a2594aaa275fd88225927e7115085b">CAN_F9R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac2e7a7ac6a91de762e00f6ccbde5c982">CAN_F9R1_FB9_Msk</a></td></tr>
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<tr class="separator:ga80a2594aaa275fd88225927e7115085b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga382c3bfb429d3dcb4dc665af752e569b" id="r_ga382c3bfb429d3dcb4dc665af752e569b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga382c3bfb429d3dcb4dc665af752e569b">CAN_F9R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga382c3bfb429d3dcb4dc665af752e569b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd756a032170c40a6e99e78c1c52eb95" id="r_gabd756a032170c40a6e99e78c1c52eb95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd756a032170c40a6e99e78c1c52eb95">CAN_F9R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga382c3bfb429d3dcb4dc665af752e569b">CAN_F9R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:gabd756a032170c40a6e99e78c1c52eb95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3db445a3214057317d84269116c9a3de" id="r_ga3db445a3214057317d84269116c9a3de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3db445a3214057317d84269116c9a3de">CAN_F9R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd756a032170c40a6e99e78c1c52eb95">CAN_F9R1_FB10_Msk</a></td></tr>
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<tr class="separator:ga3db445a3214057317d84269116c9a3de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8154705ae1b389be82edd66ab25b9f81" id="r_ga8154705ae1b389be82edd66ab25b9f81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8154705ae1b389be82edd66ab25b9f81">CAN_F9R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga8154705ae1b389be82edd66ab25b9f81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7239e8ffb07b9aea8013fec8dded9153" id="r_ga7239e8ffb07b9aea8013fec8dded9153"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7239e8ffb07b9aea8013fec8dded9153">CAN_F9R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8154705ae1b389be82edd66ab25b9f81">CAN_F9R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga7239e8ffb07b9aea8013fec8dded9153"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf09c1d038af593122315a878c15f608" id="r_gadf09c1d038af593122315a878c15f608"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf09c1d038af593122315a878c15f608">CAN_F9R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7239e8ffb07b9aea8013fec8dded9153">CAN_F9R1_FB11_Msk</a></td></tr>
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<tr class="separator:gadf09c1d038af593122315a878c15f608"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae584c59edb1f026fe49dc993eb084dd3" id="r_gae584c59edb1f026fe49dc993eb084dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae584c59edb1f026fe49dc993eb084dd3">CAN_F9R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gae584c59edb1f026fe49dc993eb084dd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7fdb5f76ff7140ead344e774d2a7624" id="r_gad7fdb5f76ff7140ead344e774d2a7624"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7fdb5f76ff7140ead344e774d2a7624">CAN_F9R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae584c59edb1f026fe49dc993eb084dd3">CAN_F9R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:gad7fdb5f76ff7140ead344e774d2a7624"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12b2a29143ddf47eb1eddf76f9289cb9" id="r_ga12b2a29143ddf47eb1eddf76f9289cb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12b2a29143ddf47eb1eddf76f9289cb9">CAN_F9R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad7fdb5f76ff7140ead344e774d2a7624">CAN_F9R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga12b2a29143ddf47eb1eddf76f9289cb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8bce562ccc80042ac70f70fc9c0bc35" id="r_gaf8bce562ccc80042ac70f70fc9c0bc35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8bce562ccc80042ac70f70fc9c0bc35">CAN_F9R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaf8bce562ccc80042ac70f70fc9c0bc35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga156dc983e417d37a94dd165f5d3d2f93" id="r_ga156dc983e417d37a94dd165f5d3d2f93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga156dc983e417d37a94dd165f5d3d2f93">CAN_F9R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8bce562ccc80042ac70f70fc9c0bc35">CAN_F9R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga156dc983e417d37a94dd165f5d3d2f93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga691bc907b71c30dffdf246c95240ac9b" id="r_ga691bc907b71c30dffdf246c95240ac9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga691bc907b71c30dffdf246c95240ac9b">CAN_F9R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga156dc983e417d37a94dd165f5d3d2f93">CAN_F9R1_FB13_Msk</a></td></tr>
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<tr class="separator:ga691bc907b71c30dffdf246c95240ac9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6618206f24c69189d2e432bd4efc0651" id="r_ga6618206f24c69189d2e432bd4efc0651"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6618206f24c69189d2e432bd4efc0651">CAN_F9R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga6618206f24c69189d2e432bd4efc0651"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga396a55b76a656a8592faa6c6910dbb40" id="r_ga396a55b76a656a8592faa6c6910dbb40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga396a55b76a656a8592faa6c6910dbb40">CAN_F9R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6618206f24c69189d2e432bd4efc0651">CAN_F9R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:ga396a55b76a656a8592faa6c6910dbb40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8669ceaa46f5aecada88accedfb4dbb" id="r_gaf8669ceaa46f5aecada88accedfb4dbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8669ceaa46f5aecada88accedfb4dbb">CAN_F9R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga396a55b76a656a8592faa6c6910dbb40">CAN_F9R1_FB14_Msk</a></td></tr>
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<tr class="separator:gaf8669ceaa46f5aecada88accedfb4dbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee8557da5e6de53987fbd0a185596107" id="r_gaee8557da5e6de53987fbd0a185596107"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee8557da5e6de53987fbd0a185596107">CAN_F9R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaee8557da5e6de53987fbd0a185596107"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd456c2656ca51201b43ed9831d24d4d" id="r_gadd456c2656ca51201b43ed9831d24d4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd456c2656ca51201b43ed9831d24d4d">CAN_F9R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee8557da5e6de53987fbd0a185596107">CAN_F9R1_FB15_Pos</a>)</td></tr>
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<tr class="separator:gadd456c2656ca51201b43ed9831d24d4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35e8769a1e21c4cf3714667e07201804" id="r_ga35e8769a1e21c4cf3714667e07201804"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35e8769a1e21c4cf3714667e07201804">CAN_F9R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadd456c2656ca51201b43ed9831d24d4d">CAN_F9R1_FB15_Msk</a></td></tr>
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<tr class="separator:ga35e8769a1e21c4cf3714667e07201804"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe418890b1a83c8846daace95b47edf9" id="r_gabe418890b1a83c8846daace95b47edf9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe418890b1a83c8846daace95b47edf9">CAN_F9R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:gabe418890b1a83c8846daace95b47edf9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fc59d106067ea2d6a18fd5f08ba2767" id="r_ga9fc59d106067ea2d6a18fd5f08ba2767"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fc59d106067ea2d6a18fd5f08ba2767">CAN_F9R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabe418890b1a83c8846daace95b47edf9">CAN_F9R1_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga9fc59d106067ea2d6a18fd5f08ba2767"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7060a1863aa5b08ce8469001d46c630" id="r_gad7060a1863aa5b08ce8469001d46c630"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7060a1863aa5b08ce8469001d46c630">CAN_F9R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9fc59d106067ea2d6a18fd5f08ba2767">CAN_F9R1_FB16_Msk</a></td></tr>
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<tr class="memitem:ga04c61d64fef04b48caeba748a9a22aa6" id="r_ga04c61d64fef04b48caeba748a9a22aa6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04c61d64fef04b48caeba748a9a22aa6">CAN_F9R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="memitem:gaf4ff327faa1fe85083a3ef4f071e86e9" id="r_gaf4ff327faa1fe85083a3ef4f071e86e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4ff327faa1fe85083a3ef4f071e86e9">CAN_F9R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga04c61d64fef04b48caeba748a9a22aa6">CAN_F9R1_FB17_Pos</a>)</td></tr>
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<tr class="memitem:gacf015fb7231bd315f82948019dcfc725" id="r_gacf015fb7231bd315f82948019dcfc725"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf015fb7231bd315f82948019dcfc725">CAN_F9R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4ff327faa1fe85083a3ef4f071e86e9">CAN_F9R1_FB17_Msk</a></td></tr>
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<tr class="memitem:ga35916c6399028aaf16c864a1b37f191e" id="r_ga35916c6399028aaf16c864a1b37f191e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35916c6399028aaf16c864a1b37f191e">CAN_F9R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga1580585e09b20a6bc206c033139649a6" id="r_ga1580585e09b20a6bc206c033139649a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1580585e09b20a6bc206c033139649a6">CAN_F9R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga35916c6399028aaf16c864a1b37f191e">CAN_F9R1_FB18_Pos</a>)</td></tr>
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<tr class="memitem:ga02c06b01abb3414394747a7cf8eac888" id="r_ga02c06b01abb3414394747a7cf8eac888"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02c06b01abb3414394747a7cf8eac888">CAN_F9R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1580585e09b20a6bc206c033139649a6">CAN_F9R1_FB18_Msk</a></td></tr>
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<tr class="memitem:gafa5760e3a9d5b2ae2596c1a203ac772a" id="r_gafa5760e3a9d5b2ae2596c1a203ac772a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa5760e3a9d5b2ae2596c1a203ac772a">CAN_F9R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="memitem:gaa356b4a420c19ac07bfa409d55e53adc" id="r_gaa356b4a420c19ac07bfa409d55e53adc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa356b4a420c19ac07bfa409d55e53adc">CAN_F9R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafa5760e3a9d5b2ae2596c1a203ac772a">CAN_F9R1_FB19_Pos</a>)</td></tr>
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<tr class="memitem:ga99a1a20417252e33a4817c0530745239" id="r_ga99a1a20417252e33a4817c0530745239"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99a1a20417252e33a4817c0530745239">CAN_F9R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa356b4a420c19ac07bfa409d55e53adc">CAN_F9R1_FB19_Msk</a></td></tr>
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<tr class="memitem:ga8e961ee93fb85b21e152e98eb2d69e08" id="r_ga8e961ee93fb85b21e152e98eb2d69e08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e961ee93fb85b21e152e98eb2d69e08">CAN_F9R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga8f43ec3ddec319e7dfbda3b44c7c2df4" id="r_ga8f43ec3ddec319e7dfbda3b44c7c2df4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f43ec3ddec319e7dfbda3b44c7c2df4">CAN_F9R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e961ee93fb85b21e152e98eb2d69e08">CAN_F9R1_FB20_Pos</a>)</td></tr>
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<tr class="memitem:ga09c0f503e2ef85b3b6332ccbca7b0251" id="r_ga09c0f503e2ef85b3b6332ccbca7b0251"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09c0f503e2ef85b3b6332ccbca7b0251">CAN_F9R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f43ec3ddec319e7dfbda3b44c7c2df4">CAN_F9R1_FB20_Msk</a></td></tr>
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<tr class="separator:ga09c0f503e2ef85b3b6332ccbca7b0251"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedf1cb9ca8fd641443fbddc3b66dd953" id="r_gaedf1cb9ca8fd641443fbddc3b66dd953"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedf1cb9ca8fd641443fbddc3b66dd953">CAN_F9R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="memitem:ga8a5361a1933b142476427e60fc3f9c72" id="r_ga8a5361a1933b142476427e60fc3f9c72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a5361a1933b142476427e60fc3f9c72">CAN_F9R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaedf1cb9ca8fd641443fbddc3b66dd953">CAN_F9R1_FB21_Pos</a>)</td></tr>
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<tr class="memitem:gacab12d06dee3d6dad5fd7c56c23c70d1" id="r_gacab12d06dee3d6dad5fd7c56c23c70d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacab12d06dee3d6dad5fd7c56c23c70d1">CAN_F9R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a5361a1933b142476427e60fc3f9c72">CAN_F9R1_FB21_Msk</a></td></tr>
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<tr class="separator:gacab12d06dee3d6dad5fd7c56c23c70d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad975dfcf3d01716533fb54d8b61787c2" id="r_gad975dfcf3d01716533fb54d8b61787c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad975dfcf3d01716533fb54d8b61787c2">CAN_F9R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="memitem:ga55a508f12177632ba51a7ddc551ed9e2" id="r_ga55a508f12177632ba51a7ddc551ed9e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55a508f12177632ba51a7ddc551ed9e2">CAN_F9R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad975dfcf3d01716533fb54d8b61787c2">CAN_F9R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga55a508f12177632ba51a7ddc551ed9e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c72a8d17db1de69086f19579b169c04" id="r_ga5c72a8d17db1de69086f19579b169c04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c72a8d17db1de69086f19579b169c04">CAN_F9R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga55a508f12177632ba51a7ddc551ed9e2">CAN_F9R1_FB22_Msk</a></td></tr>
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<tr class="separator:ga5c72a8d17db1de69086f19579b169c04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad49102a5c0f38207584062f8303da2f5" id="r_gad49102a5c0f38207584062f8303da2f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad49102a5c0f38207584062f8303da2f5">CAN_F9R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gad49102a5c0f38207584062f8303da2f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65ef341230d8345ce5e8176674f9f745" id="r_ga65ef341230d8345ce5e8176674f9f745"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65ef341230d8345ce5e8176674f9f745">CAN_F9R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad49102a5c0f38207584062f8303da2f5">CAN_F9R1_FB23_Pos</a>)</td></tr>
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<tr class="memitem:ga4bb3ba674ec6c82ed108f6c0bfb2f854" id="r_ga4bb3ba674ec6c82ed108f6c0bfb2f854"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bb3ba674ec6c82ed108f6c0bfb2f854">CAN_F9R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65ef341230d8345ce5e8176674f9f745">CAN_F9R1_FB23_Msk</a></td></tr>
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<tr class="separator:ga4bb3ba674ec6c82ed108f6c0bfb2f854"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac621c869012858627036bd298ced7e8f" id="r_gac621c869012858627036bd298ced7e8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac621c869012858627036bd298ced7e8f">CAN_F9R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga309068d091fa9bd5abd28c709efb96c8" id="r_ga309068d091fa9bd5abd28c709efb96c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga309068d091fa9bd5abd28c709efb96c8">CAN_F9R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac621c869012858627036bd298ced7e8f">CAN_F9R1_FB24_Pos</a>)</td></tr>
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<tr class="memitem:gaba13bd7fa1e4c2eaef3de31d933cbc10" id="r_gaba13bd7fa1e4c2eaef3de31d933cbc10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba13bd7fa1e4c2eaef3de31d933cbc10">CAN_F9R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga309068d091fa9bd5abd28c709efb96c8">CAN_F9R1_FB24_Msk</a></td></tr>
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<tr class="separator:gaba13bd7fa1e4c2eaef3de31d933cbc10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4cb66980120bd88fc4a472a87ea672e4" id="r_ga4cb66980120bd88fc4a472a87ea672e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4cb66980120bd88fc4a472a87ea672e4">CAN_F9R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="memitem:gac97a1bd116fc0f32a29c4c3006d0330d" id="r_gac97a1bd116fc0f32a29c4c3006d0330d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac97a1bd116fc0f32a29c4c3006d0330d">CAN_F9R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4cb66980120bd88fc4a472a87ea672e4">CAN_F9R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:gac97a1bd116fc0f32a29c4c3006d0330d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa72247fe16d8f777c26726063fa43536" id="r_gaa72247fe16d8f777c26726063fa43536"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa72247fe16d8f777c26726063fa43536">CAN_F9R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac97a1bd116fc0f32a29c4c3006d0330d">CAN_F9R1_FB25_Msk</a></td></tr>
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<tr class="separator:gaa72247fe16d8f777c26726063fa43536"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f2aaac573ee7915936b4c68ab36fc5a" id="r_ga7f2aaac573ee7915936b4c68ab36fc5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f2aaac573ee7915936b4c68ab36fc5a">CAN_F9R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga7f2aaac573ee7915936b4c68ab36fc5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ed19ac97bbe1e8d109a31af97ac183c" id="r_ga9ed19ac97bbe1e8d109a31af97ac183c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ed19ac97bbe1e8d109a31af97ac183c">CAN_F9R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f2aaac573ee7915936b4c68ab36fc5a">CAN_F9R1_FB26_Pos</a>)</td></tr>
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<tr class="memitem:ga32d7c1678449ff8f4e4b6f548ba85be4" id="r_ga32d7c1678449ff8f4e4b6f548ba85be4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32d7c1678449ff8f4e4b6f548ba85be4">CAN_F9R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ed19ac97bbe1e8d109a31af97ac183c">CAN_F9R1_FB26_Msk</a></td></tr>
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<tr class="separator:ga32d7c1678449ff8f4e4b6f548ba85be4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00c420c0a498d9f93ae7b78d10c90171" id="r_ga00c420c0a498d9f93ae7b78d10c90171"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00c420c0a498d9f93ae7b78d10c90171">CAN_F9R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga00c420c0a498d9f93ae7b78d10c90171"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bfa05da1393f001376725caac1a5cb1" id="r_ga3bfa05da1393f001376725caac1a5cb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bfa05da1393f001376725caac1a5cb1">CAN_F9R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga00c420c0a498d9f93ae7b78d10c90171">CAN_F9R1_FB27_Pos</a>)</td></tr>
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<tr class="memitem:ga678d4a0a39b379db5c2e0285782c686f" id="r_ga678d4a0a39b379db5c2e0285782c686f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga678d4a0a39b379db5c2e0285782c686f">CAN_F9R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bfa05da1393f001376725caac1a5cb1">CAN_F9R1_FB27_Msk</a></td></tr>
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<tr class="separator:ga678d4a0a39b379db5c2e0285782c686f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e5d9b745f7bd053a3843faf405b7eb1" id="r_ga0e5d9b745f7bd053a3843faf405b7eb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e5d9b745f7bd053a3843faf405b7eb1">CAN_F9R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga0e5d9b745f7bd053a3843faf405b7eb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab301858f2e91edd141441ebf4be606b" id="r_gaab301858f2e91edd141441ebf4be606b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab301858f2e91edd141441ebf4be606b">CAN_F9R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e5d9b745f7bd053a3843faf405b7eb1">CAN_F9R1_FB28_Pos</a>)</td></tr>
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<tr class="separator:gaab301858f2e91edd141441ebf4be606b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6033aa5f4d140dc48ddb4a777583163c" id="r_ga6033aa5f4d140dc48ddb4a777583163c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6033aa5f4d140dc48ddb4a777583163c">CAN_F9R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaab301858f2e91edd141441ebf4be606b">CAN_F9R1_FB28_Msk</a></td></tr>
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<tr class="separator:ga6033aa5f4d140dc48ddb4a777583163c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8fc29302b5a2404550b37a1e62c0f11" id="r_gaa8fc29302b5a2404550b37a1e62c0f11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8fc29302b5a2404550b37a1e62c0f11">CAN_F9R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:gaa8fc29302b5a2404550b37a1e62c0f11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac23f3b612ef426adf60238083766f4a8" id="r_gac23f3b612ef426adf60238083766f4a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac23f3b612ef426adf60238083766f4a8">CAN_F9R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8fc29302b5a2404550b37a1e62c0f11">CAN_F9R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:gac23f3b612ef426adf60238083766f4a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fda159c684d7361094da1883473b544" id="r_ga9fda159c684d7361094da1883473b544"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fda159c684d7361094da1883473b544">CAN_F9R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac23f3b612ef426adf60238083766f4a8">CAN_F9R1_FB29_Msk</a></td></tr>
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<tr class="separator:ga9fda159c684d7361094da1883473b544"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec4d21090abcdafb53a216c6507cbf57" id="r_gaec4d21090abcdafb53a216c6507cbf57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec4d21090abcdafb53a216c6507cbf57">CAN_F9R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:gaec4d21090abcdafb53a216c6507cbf57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0799e2743ca085ddc2d3557c81d4fb5a" id="r_ga0799e2743ca085ddc2d3557c81d4fb5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0799e2743ca085ddc2d3557c81d4fb5a">CAN_F9R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaec4d21090abcdafb53a216c6507cbf57">CAN_F9R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga0799e2743ca085ddc2d3557c81d4fb5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83cf4080564c51a0123b97840576c0ab" id="r_ga83cf4080564c51a0123b97840576c0ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83cf4080564c51a0123b97840576c0ab">CAN_F9R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0799e2743ca085ddc2d3557c81d4fb5a">CAN_F9R1_FB30_Msk</a></td></tr>
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<tr class="separator:ga83cf4080564c51a0123b97840576c0ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c781d400959fec8e3f8636b97c6227c" id="r_ga5c781d400959fec8e3f8636b97c6227c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c781d400959fec8e3f8636b97c6227c">CAN_F9R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga5c781d400959fec8e3f8636b97c6227c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac69d0815a7cd9bf18de74375fea92676" id="r_gac69d0815a7cd9bf18de74375fea92676"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac69d0815a7cd9bf18de74375fea92676">CAN_F9R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c781d400959fec8e3f8636b97c6227c">CAN_F9R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:gac69d0815a7cd9bf18de74375fea92676"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga127c155bc5c5236f04cfdcf96ff66cc5" id="r_ga127c155bc5c5236f04cfdcf96ff66cc5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga127c155bc5c5236f04cfdcf96ff66cc5">CAN_F9R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac69d0815a7cd9bf18de74375fea92676">CAN_F9R1_FB31_Msk</a></td></tr>
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<tr class="separator:ga127c155bc5c5236f04cfdcf96ff66cc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34b8639dd16a3b599266e6a777fb604d" id="r_ga34b8639dd16a3b599266e6a777fb604d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34b8639dd16a3b599266e6a777fb604d">CAN_F10R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga34b8639dd16a3b599266e6a777fb604d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a05b74c330bf04f1f6f3ae982306f57" id="r_ga7a05b74c330bf04f1f6f3ae982306f57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a05b74c330bf04f1f6f3ae982306f57">CAN_F10R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34b8639dd16a3b599266e6a777fb604d">CAN_F10R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga7a05b74c330bf04f1f6f3ae982306f57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d5b5b7bc147da430d9c8fbe03679ca3" id="r_ga1d5b5b7bc147da430d9c8fbe03679ca3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d5b5b7bc147da430d9c8fbe03679ca3">CAN_F10R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a05b74c330bf04f1f6f3ae982306f57">CAN_F10R1_FB0_Msk</a></td></tr>
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<tr class="separator:ga1d5b5b7bc147da430d9c8fbe03679ca3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61d255693dabbb9177ad7a611aac5958" id="r_ga61d255693dabbb9177ad7a611aac5958"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61d255693dabbb9177ad7a611aac5958">CAN_F10R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga61d255693dabbb9177ad7a611aac5958"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccc10e15c593cf151539aaf626131cd6" id="r_gaccc10e15c593cf151539aaf626131cd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccc10e15c593cf151539aaf626131cd6">CAN_F10R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61d255693dabbb9177ad7a611aac5958">CAN_F10R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:gaccc10e15c593cf151539aaf626131cd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ed7be0180fd7096f10cfde27261ecc9" id="r_ga3ed7be0180fd7096f10cfde27261ecc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ed7be0180fd7096f10cfde27261ecc9">CAN_F10R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaccc10e15c593cf151539aaf626131cd6">CAN_F10R1_FB1_Msk</a></td></tr>
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<tr class="separator:ga3ed7be0180fd7096f10cfde27261ecc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e899e29234df6b50a1866c607823ca8" id="r_ga2e899e29234df6b50a1866c607823ca8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e899e29234df6b50a1866c607823ca8">CAN_F10R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga2e899e29234df6b50a1866c607823ca8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cc815403ff9f3643971ecd50b8e1c0a" id="r_ga3cc815403ff9f3643971ecd50b8e1c0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cc815403ff9f3643971ecd50b8e1c0a">CAN_F10R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e899e29234df6b50a1866c607823ca8">CAN_F10R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga3cc815403ff9f3643971ecd50b8e1c0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad099442eb6b71912a81d1f6fccbaec0a" id="r_gad099442eb6b71912a81d1f6fccbaec0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad099442eb6b71912a81d1f6fccbaec0a">CAN_F10R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cc815403ff9f3643971ecd50b8e1c0a">CAN_F10R1_FB2_Msk</a></td></tr>
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<tr class="separator:gad099442eb6b71912a81d1f6fccbaec0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b6414ba4791274ad1dedeae302deb8c" id="r_ga5b6414ba4791274ad1dedeae302deb8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b6414ba4791274ad1dedeae302deb8c">CAN_F10R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga5b6414ba4791274ad1dedeae302deb8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc1db4c0b25f68a6bd3c6cbb2d2c82ee" id="r_gabc1db4c0b25f68a6bd3c6cbb2d2c82ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc1db4c0b25f68a6bd3c6cbb2d2c82ee">CAN_F10R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b6414ba4791274ad1dedeae302deb8c">CAN_F10R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:gabc1db4c0b25f68a6bd3c6cbb2d2c82ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4024c53b7b0cec550baed99ae92e3465" id="r_ga4024c53b7b0cec550baed99ae92e3465"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4024c53b7b0cec550baed99ae92e3465">CAN_F10R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabc1db4c0b25f68a6bd3c6cbb2d2c82ee">CAN_F10R1_FB3_Msk</a></td></tr>
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<tr class="separator:ga4024c53b7b0cec550baed99ae92e3465"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1468d4f971fefa12ac2373e9059fcc4" id="r_gab1468d4f971fefa12ac2373e9059fcc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1468d4f971fefa12ac2373e9059fcc4">CAN_F10R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gab1468d4f971fefa12ac2373e9059fcc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad91329ef7b3229b4f06f31c8fbaa8507" id="r_gad91329ef7b3229b4f06f31c8fbaa8507"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad91329ef7b3229b4f06f31c8fbaa8507">CAN_F10R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab1468d4f971fefa12ac2373e9059fcc4">CAN_F10R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:gad91329ef7b3229b4f06f31c8fbaa8507"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1859eaac9ae1220c752218e5ad526179" id="r_ga1859eaac9ae1220c752218e5ad526179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1859eaac9ae1220c752218e5ad526179">CAN_F10R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad91329ef7b3229b4f06f31c8fbaa8507">CAN_F10R1_FB4_Msk</a></td></tr>
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<tr class="separator:ga1859eaac9ae1220c752218e5ad526179"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5059f789c76d31ef43d2933a6794ebef" id="r_ga5059f789c76d31ef43d2933a6794ebef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5059f789c76d31ef43d2933a6794ebef">CAN_F10R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga5059f789c76d31ef43d2933a6794ebef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf7af08619a0d22a111e253c1059024d" id="r_gadf7af08619a0d22a111e253c1059024d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf7af08619a0d22a111e253c1059024d">CAN_F10R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5059f789c76d31ef43d2933a6794ebef">CAN_F10R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:gadf7af08619a0d22a111e253c1059024d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5683dc25f0aae9a802a5f57c88bec856" id="r_ga5683dc25f0aae9a802a5f57c88bec856"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5683dc25f0aae9a802a5f57c88bec856">CAN_F10R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadf7af08619a0d22a111e253c1059024d">CAN_F10R1_FB5_Msk</a></td></tr>
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<tr class="separator:ga5683dc25f0aae9a802a5f57c88bec856"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c9f5e78c2fbffbca7976837c901ae11" id="r_ga4c9f5e78c2fbffbca7976837c901ae11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c9f5e78c2fbffbca7976837c901ae11">CAN_F10R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga4c9f5e78c2fbffbca7976837c901ae11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fcb5577636b7acc70f13f92cbfa3f9a" id="r_ga9fcb5577636b7acc70f13f92cbfa3f9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fcb5577636b7acc70f13f92cbfa3f9a">CAN_F10R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c9f5e78c2fbffbca7976837c901ae11">CAN_F10R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga9fcb5577636b7acc70f13f92cbfa3f9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae83dd9ce8a2c7917e278ce4755f8f43e" id="r_gae83dd9ce8a2c7917e278ce4755f8f43e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae83dd9ce8a2c7917e278ce4755f8f43e">CAN_F10R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9fcb5577636b7acc70f13f92cbfa3f9a">CAN_F10R1_FB6_Msk</a></td></tr>
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<tr class="separator:gae83dd9ce8a2c7917e278ce4755f8f43e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3456bf703efc85fb20bc9ccae394e575" id="r_ga3456bf703efc85fb20bc9ccae394e575"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3456bf703efc85fb20bc9ccae394e575">CAN_F10R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga3456bf703efc85fb20bc9ccae394e575"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga557466eedc11bcfb78333511b3465921" id="r_ga557466eedc11bcfb78333511b3465921"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga557466eedc11bcfb78333511b3465921">CAN_F10R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3456bf703efc85fb20bc9ccae394e575">CAN_F10R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga557466eedc11bcfb78333511b3465921"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93ad070c9f5abca3c9b9095e3a13db9c" id="r_ga93ad070c9f5abca3c9b9095e3a13db9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93ad070c9f5abca3c9b9095e3a13db9c">CAN_F10R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga557466eedc11bcfb78333511b3465921">CAN_F10R1_FB7_Msk</a></td></tr>
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<tr class="separator:ga93ad070c9f5abca3c9b9095e3a13db9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac77280ec33da757f550aa90612a3e45c" id="r_gac77280ec33da757f550aa90612a3e45c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac77280ec33da757f550aa90612a3e45c">CAN_F10R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gac77280ec33da757f550aa90612a3e45c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga451e0f30e41e5216fb223e52bdadce7a" id="r_ga451e0f30e41e5216fb223e52bdadce7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga451e0f30e41e5216fb223e52bdadce7a">CAN_F10R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac77280ec33da757f550aa90612a3e45c">CAN_F10R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga451e0f30e41e5216fb223e52bdadce7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd32db3ffec3536cd842e17c34c210d9" id="r_gadd32db3ffec3536cd842e17c34c210d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd32db3ffec3536cd842e17c34c210d9">CAN_F10R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga451e0f30e41e5216fb223e52bdadce7a">CAN_F10R1_FB8_Msk</a></td></tr>
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<tr class="separator:gadd32db3ffec3536cd842e17c34c210d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5340c5e8483f2ab61e51f7f4b0d6a78a" id="r_ga5340c5e8483f2ab61e51f7f4b0d6a78a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5340c5e8483f2ab61e51f7f4b0d6a78a">CAN_F10R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga5340c5e8483f2ab61e51f7f4b0d6a78a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga434ad62e086a866ca425960236216d34" id="r_ga434ad62e086a866ca425960236216d34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga434ad62e086a866ca425960236216d34">CAN_F10R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5340c5e8483f2ab61e51f7f4b0d6a78a">CAN_F10R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga434ad62e086a866ca425960236216d34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85673ce7a92ae8ca9a13ed2fb5574a76" id="r_ga85673ce7a92ae8ca9a13ed2fb5574a76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85673ce7a92ae8ca9a13ed2fb5574a76">CAN_F10R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga434ad62e086a866ca425960236216d34">CAN_F10R1_FB9_Msk</a></td></tr>
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<tr class="separator:ga85673ce7a92ae8ca9a13ed2fb5574a76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52a16b6466cddacc04e9200bea868510" id="r_ga52a16b6466cddacc04e9200bea868510"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52a16b6466cddacc04e9200bea868510">CAN_F10R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga52a16b6466cddacc04e9200bea868510"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga159afb7939de25a56d4a7c72e3669b8c" id="r_ga159afb7939de25a56d4a7c72e3669b8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga159afb7939de25a56d4a7c72e3669b8c">CAN_F10R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52a16b6466cddacc04e9200bea868510">CAN_F10R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga159afb7939de25a56d4a7c72e3669b8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d525825fe4bfc1d4ffccc21ab89a3fa" id="r_ga6d525825fe4bfc1d4ffccc21ab89a3fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d525825fe4bfc1d4ffccc21ab89a3fa">CAN_F10R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga159afb7939de25a56d4a7c72e3669b8c">CAN_F10R1_FB10_Msk</a></td></tr>
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<tr class="separator:ga6d525825fe4bfc1d4ffccc21ab89a3fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77878bda5d61d09fa0b3ea54a208c889" id="r_ga77878bda5d61d09fa0b3ea54a208c889"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77878bda5d61d09fa0b3ea54a208c889">CAN_F10R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga77878bda5d61d09fa0b3ea54a208c889"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa37f47760352e40a33327441fa44917a" id="r_gaa37f47760352e40a33327441fa44917a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa37f47760352e40a33327441fa44917a">CAN_F10R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga77878bda5d61d09fa0b3ea54a208c889">CAN_F10R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:gaa37f47760352e40a33327441fa44917a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33336e283eeee9b77f1f289d77f2304e" id="r_ga33336e283eeee9b77f1f289d77f2304e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33336e283eeee9b77f1f289d77f2304e">CAN_F10R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa37f47760352e40a33327441fa44917a">CAN_F10R1_FB11_Msk</a></td></tr>
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<tr class="separator:ga33336e283eeee9b77f1f289d77f2304e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb667a50ca9535347b011c47aa7f7f8a" id="r_gafb667a50ca9535347b011c47aa7f7f8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb667a50ca9535347b011c47aa7f7f8a">CAN_F10R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gafb667a50ca9535347b011c47aa7f7f8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6456e18d6659ec3437ab1b5c84b60681" id="r_ga6456e18d6659ec3437ab1b5c84b60681"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6456e18d6659ec3437ab1b5c84b60681">CAN_F10R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafb667a50ca9535347b011c47aa7f7f8a">CAN_F10R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:ga6456e18d6659ec3437ab1b5c84b60681"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf74ee01e72b3de69d6e8fcc092f7461" id="r_gadf74ee01e72b3de69d6e8fcc092f7461"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf74ee01e72b3de69d6e8fcc092f7461">CAN_F10R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6456e18d6659ec3437ab1b5c84b60681">CAN_F10R1_FB12_Msk</a></td></tr>
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<tr class="separator:gadf74ee01e72b3de69d6e8fcc092f7461"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf29dbf589e4978181256649c864076da" id="r_gaf29dbf589e4978181256649c864076da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf29dbf589e4978181256649c864076da">CAN_F10R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaf29dbf589e4978181256649c864076da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f0b809ab8b05e662982533d29d34196" id="r_ga1f0b809ab8b05e662982533d29d34196"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f0b809ab8b05e662982533d29d34196">CAN_F10R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf29dbf589e4978181256649c864076da">CAN_F10R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga1f0b809ab8b05e662982533d29d34196"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ee416ff22b47bb289bab34afbc74f19" id="r_ga8ee416ff22b47bb289bab34afbc74f19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ee416ff22b47bb289bab34afbc74f19">CAN_F10R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f0b809ab8b05e662982533d29d34196">CAN_F10R1_FB13_Msk</a></td></tr>
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<tr class="separator:ga8ee416ff22b47bb289bab34afbc74f19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1630e20424cfa65e81a05cce2c1f7337" id="r_ga1630e20424cfa65e81a05cce2c1f7337"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1630e20424cfa65e81a05cce2c1f7337">CAN_F10R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga1630e20424cfa65e81a05cce2c1f7337"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1553e078a11eeb8d8ea8c0e0448b4d0" id="r_gae1553e078a11eeb8d8ea8c0e0448b4d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1553e078a11eeb8d8ea8c0e0448b4d0">CAN_F10R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1630e20424cfa65e81a05cce2c1f7337">CAN_F10R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:gae1553e078a11eeb8d8ea8c0e0448b4d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97a8d8586c64910b0f6c09fef44c4ea7" id="r_ga97a8d8586c64910b0f6c09fef44c4ea7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97a8d8586c64910b0f6c09fef44c4ea7">CAN_F10R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae1553e078a11eeb8d8ea8c0e0448b4d0">CAN_F10R1_FB14_Msk</a></td></tr>
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<tr class="separator:ga97a8d8586c64910b0f6c09fef44c4ea7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1651020c3774aaad2dcda820e38a4b61" id="r_ga1651020c3774aaad2dcda820e38a4b61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1651020c3774aaad2dcda820e38a4b61">CAN_F10R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga1651020c3774aaad2dcda820e38a4b61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga372ca9243e9a38085b93d717f05b885a" id="r_ga372ca9243e9a38085b93d717f05b885a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga372ca9243e9a38085b93d717f05b885a">CAN_F10R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1651020c3774aaad2dcda820e38a4b61">CAN_F10R1_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga372ca9243e9a38085b93d717f05b885a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9e8e43adc56ba1e593b97e062c79075" id="r_gab9e8e43adc56ba1e593b97e062c79075"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9e8e43adc56ba1e593b97e062c79075">CAN_F10R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga372ca9243e9a38085b93d717f05b885a">CAN_F10R1_FB15_Msk</a></td></tr>
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<tr class="separator:gab9e8e43adc56ba1e593b97e062c79075"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad18243430f119e7ed075890d0c4ee9bd" id="r_gad18243430f119e7ed075890d0c4ee9bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad18243430f119e7ed075890d0c4ee9bd">CAN_F10R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:gad18243430f119e7ed075890d0c4ee9bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90ecfd894be7f8a4d1eb0cbfe995f7a8" id="r_ga90ecfd894be7f8a4d1eb0cbfe995f7a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90ecfd894be7f8a4d1eb0cbfe995f7a8">CAN_F10R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad18243430f119e7ed075890d0c4ee9bd">CAN_F10R1_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga90ecfd894be7f8a4d1eb0cbfe995f7a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa64a0b16c073b51cb5e90b94c638fd95" id="r_gaa64a0b16c073b51cb5e90b94c638fd95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa64a0b16c073b51cb5e90b94c638fd95">CAN_F10R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga90ecfd894be7f8a4d1eb0cbfe995f7a8">CAN_F10R1_FB16_Msk</a></td></tr>
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<tr class="separator:gaa64a0b16c073b51cb5e90b94c638fd95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d5b824a1aa2f34e1c413feffd1503fd" id="r_ga7d5b824a1aa2f34e1c413feffd1503fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d5b824a1aa2f34e1c413feffd1503fd">CAN_F10R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="memitem:ga4d4bfbfb134e99de69fe63974eae0eba" id="r_ga4d4bfbfb134e99de69fe63974eae0eba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d4bfbfb134e99de69fe63974eae0eba">CAN_F10R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d5b824a1aa2f34e1c413feffd1503fd">CAN_F10R1_FB17_Pos</a>)</td></tr>
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<tr class="memitem:ga65f5cc396cfcf3bad71a71326e64f7d9" id="r_ga65f5cc396cfcf3bad71a71326e64f7d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65f5cc396cfcf3bad71a71326e64f7d9">CAN_F10R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d4bfbfb134e99de69fe63974eae0eba">CAN_F10R1_FB17_Msk</a></td></tr>
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<tr class="memitem:ga3ca233f5cf20e9ec03df3088fdf56f06" id="r_ga3ca233f5cf20e9ec03df3088fdf56f06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ca233f5cf20e9ec03df3088fdf56f06">CAN_F10R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga59843c48e4723e0d3cb389b8dc31e95a" id="r_ga59843c48e4723e0d3cb389b8dc31e95a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59843c48e4723e0d3cb389b8dc31e95a">CAN_F10R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ca233f5cf20e9ec03df3088fdf56f06">CAN_F10R1_FB18_Pos</a>)</td></tr>
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<tr class="separator:ga59843c48e4723e0d3cb389b8dc31e95a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga424940f535aa9a1520e25df53673d01f" id="r_ga424940f535aa9a1520e25df53673d01f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga424940f535aa9a1520e25df53673d01f">CAN_F10R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga59843c48e4723e0d3cb389b8dc31e95a">CAN_F10R1_FB18_Msk</a></td></tr>
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<tr class="memitem:ga6910b732b7855530c3a345d1b027a7f4" id="r_ga6910b732b7855530c3a345d1b027a7f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6910b732b7855530c3a345d1b027a7f4">CAN_F10R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga6910b732b7855530c3a345d1b027a7f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga028e9c16a75cfe1a4209db5761793d65" id="r_ga028e9c16a75cfe1a4209db5761793d65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga028e9c16a75cfe1a4209db5761793d65">CAN_F10R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6910b732b7855530c3a345d1b027a7f4">CAN_F10R1_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga028e9c16a75cfe1a4209db5761793d65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga166a4035770c58147d583c3dc571d10a" id="r_ga166a4035770c58147d583c3dc571d10a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga166a4035770c58147d583c3dc571d10a">CAN_F10R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga028e9c16a75cfe1a4209db5761793d65">CAN_F10R1_FB19_Msk</a></td></tr>
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<tr class="memitem:gab55c921e020738e5610d97fe033855c7" id="r_gab55c921e020738e5610d97fe033855c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab55c921e020738e5610d97fe033855c7">CAN_F10R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga0d3e3967b90e93cdf5d2dff50ccd6467" id="r_ga0d3e3967b90e93cdf5d2dff50ccd6467"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d3e3967b90e93cdf5d2dff50ccd6467">CAN_F10R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab55c921e020738e5610d97fe033855c7">CAN_F10R1_FB20_Pos</a>)</td></tr>
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<tr class="memitem:ga302214ece439e8913b47949bd07d118a" id="r_ga302214ece439e8913b47949bd07d118a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga302214ece439e8913b47949bd07d118a">CAN_F10R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d3e3967b90e93cdf5d2dff50ccd6467">CAN_F10R1_FB20_Msk</a></td></tr>
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<tr class="memitem:ga971d242e49fe7359b6e741466d305411" id="r_ga971d242e49fe7359b6e741466d305411"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga971d242e49fe7359b6e741466d305411">CAN_F10R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga971d242e49fe7359b6e741466d305411"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f7d08dc1418dc7260c85dcd41c3f2f7" id="r_ga4f7d08dc1418dc7260c85dcd41c3f2f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f7d08dc1418dc7260c85dcd41c3f2f7">CAN_F10R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga971d242e49fe7359b6e741466d305411">CAN_F10R1_FB21_Pos</a>)</td></tr>
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<tr class="memitem:gad9abe6ae1dcb2bd140e7e28d37fd8abb" id="r_gad9abe6ae1dcb2bd140e7e28d37fd8abb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9abe6ae1dcb2bd140e7e28d37fd8abb">CAN_F10R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f7d08dc1418dc7260c85dcd41c3f2f7">CAN_F10R1_FB21_Msk</a></td></tr>
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<tr class="separator:gad9abe6ae1dcb2bd140e7e28d37fd8abb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf28c54456414ccbb9b51ce644d47601" id="r_gabf28c54456414ccbb9b51ce644d47601"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf28c54456414ccbb9b51ce644d47601">CAN_F10R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="memitem:ga33f696dbd8db5370eb9701e521227e2e" id="r_ga33f696dbd8db5370eb9701e521227e2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33f696dbd8db5370eb9701e521227e2e">CAN_F10R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf28c54456414ccbb9b51ce644d47601">CAN_F10R1_FB22_Pos</a>)</td></tr>
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<tr class="memitem:ga99063956b41c4dcf6c78cc29305b1cd1" id="r_ga99063956b41c4dcf6c78cc29305b1cd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99063956b41c4dcf6c78cc29305b1cd1">CAN_F10R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga33f696dbd8db5370eb9701e521227e2e">CAN_F10R1_FB22_Msk</a></td></tr>
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<tr class="memitem:ga9adb7b8a937732924faef5a13b6d691c" id="r_ga9adb7b8a937732924faef5a13b6d691c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9adb7b8a937732924faef5a13b6d691c">CAN_F10R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga9adb7b8a937732924faef5a13b6d691c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4b78077f4a9d949debb3c345fcc8203" id="r_gab4b78077f4a9d949debb3c345fcc8203"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4b78077f4a9d949debb3c345fcc8203">CAN_F10R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9adb7b8a937732924faef5a13b6d691c">CAN_F10R1_FB23_Pos</a>)</td></tr>
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<tr class="separator:gab4b78077f4a9d949debb3c345fcc8203"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81ae64786c3a83bdd21cf72c560c7c1e" id="r_ga81ae64786c3a83bdd21cf72c560c7c1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81ae64786c3a83bdd21cf72c560c7c1e">CAN_F10R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab4b78077f4a9d949debb3c345fcc8203">CAN_F10R1_FB23_Msk</a></td></tr>
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<tr class="memitem:ga3774098d002351e5997edddd0c0ce5d0" id="r_ga3774098d002351e5997edddd0c0ce5d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3774098d002351e5997edddd0c0ce5d0">CAN_F10R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga3774098d002351e5997edddd0c0ce5d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadaa800d4dbab113869136419067683b7" id="r_gadaa800d4dbab113869136419067683b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadaa800d4dbab113869136419067683b7">CAN_F10R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3774098d002351e5997edddd0c0ce5d0">CAN_F10R1_FB24_Pos</a>)</td></tr>
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<tr class="memitem:ga0f9083faf8395701c892814694b45d2c" id="r_ga0f9083faf8395701c892814694b45d2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f9083faf8395701c892814694b45d2c">CAN_F10R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadaa800d4dbab113869136419067683b7">CAN_F10R1_FB24_Msk</a></td></tr>
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<tr class="separator:ga0f9083faf8395701c892814694b45d2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91439fb8d069e77aeb88065b1c685f89" id="r_ga91439fb8d069e77aeb88065b1c685f89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91439fb8d069e77aeb88065b1c685f89">CAN_F10R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga91439fb8d069e77aeb88065b1c685f89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2755b753aff086d43feba71cc367da2" id="r_gab2755b753aff086d43feba71cc367da2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2755b753aff086d43feba71cc367da2">CAN_F10R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga91439fb8d069e77aeb88065b1c685f89">CAN_F10R1_FB25_Pos</a>)</td></tr>
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<tr class="memitem:gaaeb6942affe306b407940fdf01534e4a" id="r_gaaeb6942affe306b407940fdf01534e4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaeb6942affe306b407940fdf01534e4a">CAN_F10R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab2755b753aff086d43feba71cc367da2">CAN_F10R1_FB25_Msk</a></td></tr>
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<tr class="memitem:gaed8963dfbdac3df92f96632e9f8973a9" id="r_gaed8963dfbdac3df92f96632e9f8973a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed8963dfbdac3df92f96632e9f8973a9">CAN_F10R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:gaed8963dfbdac3df92f96632e9f8973a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea7c4b309760f303d4bbd9ef507673d9" id="r_gaea7c4b309760f303d4bbd9ef507673d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea7c4b309760f303d4bbd9ef507673d9">CAN_F10R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed8963dfbdac3df92f96632e9f8973a9">CAN_F10R1_FB26_Pos</a>)</td></tr>
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<tr class="separator:gaea7c4b309760f303d4bbd9ef507673d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e4ee946a9614316f666852bc266c1f7" id="r_ga1e4ee946a9614316f666852bc266c1f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e4ee946a9614316f666852bc266c1f7">CAN_F10R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaea7c4b309760f303d4bbd9ef507673d9">CAN_F10R1_FB26_Msk</a></td></tr>
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<tr class="separator:ga1e4ee946a9614316f666852bc266c1f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacffecbefab44f2d80330ff6b3316404" id="r_gaacffecbefab44f2d80330ff6b3316404"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacffecbefab44f2d80330ff6b3316404">CAN_F10R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:gaacffecbefab44f2d80330ff6b3316404"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga713459bb360bab56e68cd562bcc86992" id="r_ga713459bb360bab56e68cd562bcc86992"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga713459bb360bab56e68cd562bcc86992">CAN_F10R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaacffecbefab44f2d80330ff6b3316404">CAN_F10R1_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga713459bb360bab56e68cd562bcc86992"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99153cddc8fc7e846fcc44383936541f" id="r_ga99153cddc8fc7e846fcc44383936541f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99153cddc8fc7e846fcc44383936541f">CAN_F10R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga713459bb360bab56e68cd562bcc86992">CAN_F10R1_FB27_Msk</a></td></tr>
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<tr class="memitem:gac8670b0f5b08f2106aed385abe471988" id="r_gac8670b0f5b08f2106aed385abe471988"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8670b0f5b08f2106aed385abe471988">CAN_F10R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="memitem:ga904044b84be51c67151570af41280109" id="r_ga904044b84be51c67151570af41280109"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga904044b84be51c67151570af41280109">CAN_F10R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8670b0f5b08f2106aed385abe471988">CAN_F10R1_FB28_Pos</a>)</td></tr>
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<tr class="memitem:ga0e2ba1740577246368e60d94fd3d7c69" id="r_ga0e2ba1740577246368e60d94fd3d7c69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e2ba1740577246368e60d94fd3d7c69">CAN_F10R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga904044b84be51c67151570af41280109">CAN_F10R1_FB28_Msk</a></td></tr>
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<tr class="separator:ga0e2ba1740577246368e60d94fd3d7c69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac47d24136b51470d74e9e0416110e608" id="r_gac47d24136b51470d74e9e0416110e608"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac47d24136b51470d74e9e0416110e608">CAN_F10R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:gac47d24136b51470d74e9e0416110e608"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb9254a4f5e458db48b99024ee4dcf28" id="r_gabb9254a4f5e458db48b99024ee4dcf28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb9254a4f5e458db48b99024ee4dcf28">CAN_F10R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac47d24136b51470d74e9e0416110e608">CAN_F10R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:gabb9254a4f5e458db48b99024ee4dcf28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca062686821fba26a0e5e5b0a6c5b855" id="r_gaca062686821fba26a0e5e5b0a6c5b855"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca062686821fba26a0e5e5b0a6c5b855">CAN_F10R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabb9254a4f5e458db48b99024ee4dcf28">CAN_F10R1_FB29_Msk</a></td></tr>
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<tr class="separator:gaca062686821fba26a0e5e5b0a6c5b855"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29cf8efcf620782b10885d84e0ebd370" id="r_ga29cf8efcf620782b10885d84e0ebd370"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29cf8efcf620782b10885d84e0ebd370">CAN_F10R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga29cf8efcf620782b10885d84e0ebd370"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc17c37afd6e8048e5561cc76204de98" id="r_gadc17c37afd6e8048e5561cc76204de98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc17c37afd6e8048e5561cc76204de98">CAN_F10R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga29cf8efcf620782b10885d84e0ebd370">CAN_F10R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:gadc17c37afd6e8048e5561cc76204de98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8981f420ef4c8fe1976a09f27a9c13f1" id="r_ga8981f420ef4c8fe1976a09f27a9c13f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8981f420ef4c8fe1976a09f27a9c13f1">CAN_F10R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadc17c37afd6e8048e5561cc76204de98">CAN_F10R1_FB30_Msk</a></td></tr>
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<tr class="separator:ga8981f420ef4c8fe1976a09f27a9c13f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga486a9b2d165733097746c0e075332056" id="r_ga486a9b2d165733097746c0e075332056"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga486a9b2d165733097746c0e075332056">CAN_F10R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga486a9b2d165733097746c0e075332056"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0010aac3ddd9cb356328c22fcab2fd9" id="r_gaa0010aac3ddd9cb356328c22fcab2fd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0010aac3ddd9cb356328c22fcab2fd9">CAN_F10R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga486a9b2d165733097746c0e075332056">CAN_F10R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:gaa0010aac3ddd9cb356328c22fcab2fd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0424bf38917058b166a8bfd861d22b40" id="r_ga0424bf38917058b166a8bfd861d22b40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0424bf38917058b166a8bfd861d22b40">CAN_F10R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0010aac3ddd9cb356328c22fcab2fd9">CAN_F10R1_FB31_Msk</a></td></tr>
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<tr class="memitem:gad825b1610c2deb52c7e2a14d4ffb33ae" id="r_gad825b1610c2deb52c7e2a14d4ffb33ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad825b1610c2deb52c7e2a14d4ffb33ae">CAN_F11R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad825b1610c2deb52c7e2a14d4ffb33ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29cf61e4385aa30fbdff533d51bdd612" id="r_ga29cf61e4385aa30fbdff533d51bdd612"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29cf61e4385aa30fbdff533d51bdd612">CAN_F11R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad825b1610c2deb52c7e2a14d4ffb33ae">CAN_F11R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga29cf61e4385aa30fbdff533d51bdd612"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad059cc9b2fe5634b9330b44c37dadf06" id="r_gad059cc9b2fe5634b9330b44c37dadf06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad059cc9b2fe5634b9330b44c37dadf06">CAN_F11R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga29cf61e4385aa30fbdff533d51bdd612">CAN_F11R1_FB0_Msk</a></td></tr>
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<tr class="separator:gad059cc9b2fe5634b9330b44c37dadf06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga786a94d3ab775de9da9195130b1b76bb" id="r_ga786a94d3ab775de9da9195130b1b76bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga786a94d3ab775de9da9195130b1b76bb">CAN_F11R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga786a94d3ab775de9da9195130b1b76bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e4ad3f7a5ffa1fd9136447924950ea6" id="r_ga1e4ad3f7a5ffa1fd9136447924950ea6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e4ad3f7a5ffa1fd9136447924950ea6">CAN_F11R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga786a94d3ab775de9da9195130b1b76bb">CAN_F11R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga1e4ad3f7a5ffa1fd9136447924950ea6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad74b116cda63fcd1a662c4de835616e7" id="r_gad74b116cda63fcd1a662c4de835616e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad74b116cda63fcd1a662c4de835616e7">CAN_F11R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e4ad3f7a5ffa1fd9136447924950ea6">CAN_F11R1_FB1_Msk</a></td></tr>
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<tr class="separator:gad74b116cda63fcd1a662c4de835616e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b59aee05e1add366c493e4ccd2637c5" id="r_ga9b59aee05e1add366c493e4ccd2637c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b59aee05e1add366c493e4ccd2637c5">CAN_F11R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga9b59aee05e1add366c493e4ccd2637c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5614e1e331777400a4903b74f3398d1c" id="r_ga5614e1e331777400a4903b74f3398d1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5614e1e331777400a4903b74f3398d1c">CAN_F11R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b59aee05e1add366c493e4ccd2637c5">CAN_F11R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga5614e1e331777400a4903b74f3398d1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e05bb0c2a5bdcebb974f7dd409724bc" id="r_ga4e05bb0c2a5bdcebb974f7dd409724bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e05bb0c2a5bdcebb974f7dd409724bc">CAN_F11R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5614e1e331777400a4903b74f3398d1c">CAN_F11R1_FB2_Msk</a></td></tr>
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<tr class="separator:ga4e05bb0c2a5bdcebb974f7dd409724bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9db6817cdb088212132aebd6b1e6fadb" id="r_ga9db6817cdb088212132aebd6b1e6fadb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9db6817cdb088212132aebd6b1e6fadb">CAN_F11R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga9db6817cdb088212132aebd6b1e6fadb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cf6f2e8167bd44d1f02ff8de4574d4d" id="r_ga3cf6f2e8167bd44d1f02ff8de4574d4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cf6f2e8167bd44d1f02ff8de4574d4d">CAN_F11R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9db6817cdb088212132aebd6b1e6fadb">CAN_F11R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga3cf6f2e8167bd44d1f02ff8de4574d4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa17242aed4365034dc660ef9e8b9f1bf" id="r_gaa17242aed4365034dc660ef9e8b9f1bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa17242aed4365034dc660ef9e8b9f1bf">CAN_F11R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cf6f2e8167bd44d1f02ff8de4574d4d">CAN_F11R1_FB3_Msk</a></td></tr>
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<tr class="separator:gaa17242aed4365034dc660ef9e8b9f1bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefa798693295399620c2a62defb02ad5" id="r_gaefa798693295399620c2a62defb02ad5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefa798693295399620c2a62defb02ad5">CAN_F11R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaefa798693295399620c2a62defb02ad5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ab99e31bdf86aaad8ba7d6ad75ba7dc" id="r_ga1ab99e31bdf86aaad8ba7d6ad75ba7dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ab99e31bdf86aaad8ba7d6ad75ba7dc">CAN_F11R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaefa798693295399620c2a62defb02ad5">CAN_F11R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga1ab99e31bdf86aaad8ba7d6ad75ba7dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga450dbed19882423d70ed7606aada2453" id="r_ga450dbed19882423d70ed7606aada2453"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga450dbed19882423d70ed7606aada2453">CAN_F11R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ab99e31bdf86aaad8ba7d6ad75ba7dc">CAN_F11R1_FB4_Msk</a></td></tr>
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<tr class="separator:ga450dbed19882423d70ed7606aada2453"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf95e8d5586045005c6fc0dbb9d42017" id="r_gabf95e8d5586045005c6fc0dbb9d42017"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf95e8d5586045005c6fc0dbb9d42017">CAN_F11R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gabf95e8d5586045005c6fc0dbb9d42017"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga554f40a4480434bf6e3633e52d45e6bd" id="r_ga554f40a4480434bf6e3633e52d45e6bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga554f40a4480434bf6e3633e52d45e6bd">CAN_F11R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf95e8d5586045005c6fc0dbb9d42017">CAN_F11R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga554f40a4480434bf6e3633e52d45e6bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7ace73f2d3db1e2a1e55257d210fa04" id="r_gad7ace73f2d3db1e2a1e55257d210fa04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7ace73f2d3db1e2a1e55257d210fa04">CAN_F11R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga554f40a4480434bf6e3633e52d45e6bd">CAN_F11R1_FB5_Msk</a></td></tr>
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<tr class="separator:gad7ace73f2d3db1e2a1e55257d210fa04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33946da5363485ee484a5fd3b977068d" id="r_ga33946da5363485ee484a5fd3b977068d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33946da5363485ee484a5fd3b977068d">CAN_F11R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga33946da5363485ee484a5fd3b977068d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4aed14b088705fde497369d39675369e" id="r_ga4aed14b088705fde497369d39675369e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4aed14b088705fde497369d39675369e">CAN_F11R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga33946da5363485ee484a5fd3b977068d">CAN_F11R1_FB6_Pos</a>)</td></tr>
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<tr class="memitem:ga1459d395a3b08a948c3f5002e0914516" id="r_ga1459d395a3b08a948c3f5002e0914516"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1459d395a3b08a948c3f5002e0914516">CAN_F11R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4aed14b088705fde497369d39675369e">CAN_F11R1_FB6_Msk</a></td></tr>
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<tr class="separator:ga1459d395a3b08a948c3f5002e0914516"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga390e032609e5d44f7dd0c7e9d2f5ee16" id="r_ga390e032609e5d44f7dd0c7e9d2f5ee16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga390e032609e5d44f7dd0c7e9d2f5ee16">CAN_F11R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga390e032609e5d44f7dd0c7e9d2f5ee16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8580e565ee4bc7966aa7c515d6fab446" id="r_ga8580e565ee4bc7966aa7c515d6fab446"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8580e565ee4bc7966aa7c515d6fab446">CAN_F11R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga390e032609e5d44f7dd0c7e9d2f5ee16">CAN_F11R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga8580e565ee4bc7966aa7c515d6fab446"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30fc2236c2a18b7cb6e493fad36d8efe" id="r_ga30fc2236c2a18b7cb6e493fad36d8efe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30fc2236c2a18b7cb6e493fad36d8efe">CAN_F11R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8580e565ee4bc7966aa7c515d6fab446">CAN_F11R1_FB7_Msk</a></td></tr>
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<tr class="separator:ga30fc2236c2a18b7cb6e493fad36d8efe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73563f8f0592450f6c15ad9d91495e62" id="r_ga73563f8f0592450f6c15ad9d91495e62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73563f8f0592450f6c15ad9d91495e62">CAN_F11R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga73563f8f0592450f6c15ad9d91495e62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga639a8dc5a46ee8b2a380ac7978fb0672" id="r_ga639a8dc5a46ee8b2a380ac7978fb0672"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga639a8dc5a46ee8b2a380ac7978fb0672">CAN_F11R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga73563f8f0592450f6c15ad9d91495e62">CAN_F11R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga639a8dc5a46ee8b2a380ac7978fb0672"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74ab4a6f6b5a751acda410e0c39b87af" id="r_ga74ab4a6f6b5a751acda410e0c39b87af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74ab4a6f6b5a751acda410e0c39b87af">CAN_F11R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga639a8dc5a46ee8b2a380ac7978fb0672">CAN_F11R1_FB8_Msk</a></td></tr>
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<tr class="separator:ga74ab4a6f6b5a751acda410e0c39b87af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01de290d95f18b06e6aed12bb01cbe88" id="r_ga01de290d95f18b06e6aed12bb01cbe88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01de290d95f18b06e6aed12bb01cbe88">CAN_F11R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga01de290d95f18b06e6aed12bb01cbe88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cd49481651b80f8fdcf08efd0e07f8c" id="r_ga0cd49481651b80f8fdcf08efd0e07f8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cd49481651b80f8fdcf08efd0e07f8c">CAN_F11R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01de290d95f18b06e6aed12bb01cbe88">CAN_F11R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga0cd49481651b80f8fdcf08efd0e07f8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e69f7001534264fd027371fa188ac52" id="r_ga4e69f7001534264fd027371fa188ac52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e69f7001534264fd027371fa188ac52">CAN_F11R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cd49481651b80f8fdcf08efd0e07f8c">CAN_F11R1_FB9_Msk</a></td></tr>
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<tr class="separator:ga4e69f7001534264fd027371fa188ac52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ccf16da47b6e8c9a396eaca7ae390d7" id="r_ga8ccf16da47b6e8c9a396eaca7ae390d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ccf16da47b6e8c9a396eaca7ae390d7">CAN_F11R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga8ccf16da47b6e8c9a396eaca7ae390d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7cb55bd09dade7046aa52361411fb68" id="r_gab7cb55bd09dade7046aa52361411fb68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7cb55bd09dade7046aa52361411fb68">CAN_F11R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ccf16da47b6e8c9a396eaca7ae390d7">CAN_F11R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:gab7cb55bd09dade7046aa52361411fb68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e858dd29f741910c8ed8c512cae81b1" id="r_ga1e858dd29f741910c8ed8c512cae81b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e858dd29f741910c8ed8c512cae81b1">CAN_F11R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab7cb55bd09dade7046aa52361411fb68">CAN_F11R1_FB10_Msk</a></td></tr>
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<tr class="separator:ga1e858dd29f741910c8ed8c512cae81b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91b2fe2b66aa2708feafdf1b5fac1a5d" id="r_ga91b2fe2b66aa2708feafdf1b5fac1a5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91b2fe2b66aa2708feafdf1b5fac1a5d">CAN_F11R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga91b2fe2b66aa2708feafdf1b5fac1a5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6235ef02d18d862d4018aa9d3f2612bd" id="r_ga6235ef02d18d862d4018aa9d3f2612bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6235ef02d18d862d4018aa9d3f2612bd">CAN_F11R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga91b2fe2b66aa2708feafdf1b5fac1a5d">CAN_F11R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga6235ef02d18d862d4018aa9d3f2612bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6ba167c6cd5bc080065430e24c3a866" id="r_gaf6ba167c6cd5bc080065430e24c3a866"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6ba167c6cd5bc080065430e24c3a866">CAN_F11R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6235ef02d18d862d4018aa9d3f2612bd">CAN_F11R1_FB11_Msk</a></td></tr>
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<tr class="separator:gaf6ba167c6cd5bc080065430e24c3a866"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8638152a30201e227efb08a7239a9a1" id="r_gac8638152a30201e227efb08a7239a9a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8638152a30201e227efb08a7239a9a1">CAN_F11R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gac8638152a30201e227efb08a7239a9a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga488ce892527f6e05b74c72d3540e86e9" id="r_ga488ce892527f6e05b74c72d3540e86e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga488ce892527f6e05b74c72d3540e86e9">CAN_F11R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8638152a30201e227efb08a7239a9a1">CAN_F11R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:ga488ce892527f6e05b74c72d3540e86e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4629ab1e8632c82f3fb2648a574963b1" id="r_ga4629ab1e8632c82f3fb2648a574963b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4629ab1e8632c82f3fb2648a574963b1">CAN_F11R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga488ce892527f6e05b74c72d3540e86e9">CAN_F11R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga4629ab1e8632c82f3fb2648a574963b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b4ada853a29ea4b6975619939ad6aeb" id="r_ga0b4ada853a29ea4b6975619939ad6aeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b4ada853a29ea4b6975619939ad6aeb">CAN_F11R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0b4ada853a29ea4b6975619939ad6aeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34726d941ba918d973035cdfd4956f22" id="r_ga34726d941ba918d973035cdfd4956f22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34726d941ba918d973035cdfd4956f22">CAN_F11R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b4ada853a29ea4b6975619939ad6aeb">CAN_F11R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga34726d941ba918d973035cdfd4956f22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga833c408a165cc4ac87a242c08d4ba9b9" id="r_ga833c408a165cc4ac87a242c08d4ba9b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga833c408a165cc4ac87a242c08d4ba9b9">CAN_F11R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34726d941ba918d973035cdfd4956f22">CAN_F11R1_FB13_Msk</a></td></tr>
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<tr class="separator:ga833c408a165cc4ac87a242c08d4ba9b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga623aadd0e75b5b15052e0ee6db31b9e8" id="r_ga623aadd0e75b5b15052e0ee6db31b9e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga623aadd0e75b5b15052e0ee6db31b9e8">CAN_F11R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga623aadd0e75b5b15052e0ee6db31b9e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a261d1beaaa14ef8021eaa305b4cdf6" id="r_ga0a261d1beaaa14ef8021eaa305b4cdf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a261d1beaaa14ef8021eaa305b4cdf6">CAN_F11R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga623aadd0e75b5b15052e0ee6db31b9e8">CAN_F11R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:ga0a261d1beaaa14ef8021eaa305b4cdf6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabfecd6bbe1a15cd341942d1840b476cc" id="r_gabfecd6bbe1a15cd341942d1840b476cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfecd6bbe1a15cd341942d1840b476cc">CAN_F11R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a261d1beaaa14ef8021eaa305b4cdf6">CAN_F11R1_FB14_Msk</a></td></tr>
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<tr class="separator:gabfecd6bbe1a15cd341942d1840b476cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2162c84a2aee3dc40f2822bbf8967b5d" id="r_ga2162c84a2aee3dc40f2822bbf8967b5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2162c84a2aee3dc40f2822bbf8967b5d">CAN_F11R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga2162c84a2aee3dc40f2822bbf8967b5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaddc324a22f00abfe9bcf15478238eeda" id="r_gaddc324a22f00abfe9bcf15478238eeda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddc324a22f00abfe9bcf15478238eeda">CAN_F11R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2162c84a2aee3dc40f2822bbf8967b5d">CAN_F11R1_FB15_Pos</a>)</td></tr>
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<tr class="separator:gaddc324a22f00abfe9bcf15478238eeda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf50e1747d1d9369b7b22c5d591ae82b9" id="r_gaf50e1747d1d9369b7b22c5d591ae82b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf50e1747d1d9369b7b22c5d591ae82b9">CAN_F11R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaddc324a22f00abfe9bcf15478238eeda">CAN_F11R1_FB15_Msk</a></td></tr>
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<tr class="separator:gaf50e1747d1d9369b7b22c5d591ae82b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2464caefce933de15008f8e10a0229a" id="r_gaf2464caefce933de15008f8e10a0229a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2464caefce933de15008f8e10a0229a">CAN_F11R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaf2464caefce933de15008f8e10a0229a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67cc7cf7f00a9e32c2bd48dcd4941eeb" id="r_ga67cc7cf7f00a9e32c2bd48dcd4941eeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67cc7cf7f00a9e32c2bd48dcd4941eeb">CAN_F11R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2464caefce933de15008f8e10a0229a">CAN_F11R1_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga67cc7cf7f00a9e32c2bd48dcd4941eeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga603d63333a621594a15696cb03f59eeb" id="r_ga603d63333a621594a15696cb03f59eeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga603d63333a621594a15696cb03f59eeb">CAN_F11R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67cc7cf7f00a9e32c2bd48dcd4941eeb">CAN_F11R1_FB16_Msk</a></td></tr>
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<tr class="separator:ga603d63333a621594a15696cb03f59eeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac59287ed65d1bab31859947cf1c0e520" id="r_gac59287ed65d1bab31859947cf1c0e520"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac59287ed65d1bab31859947cf1c0e520">CAN_F11R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gac59287ed65d1bab31859947cf1c0e520"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5442d8600f85b1f2efb8cd2a0a9ec764" id="r_ga5442d8600f85b1f2efb8cd2a0a9ec764"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5442d8600f85b1f2efb8cd2a0a9ec764">CAN_F11R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac59287ed65d1bab31859947cf1c0e520">CAN_F11R1_FB17_Pos</a>)</td></tr>
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<tr class="memitem:gadb361a00177e6aa2ee19aa5a2d1781aa" id="r_gadb361a00177e6aa2ee19aa5a2d1781aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb361a00177e6aa2ee19aa5a2d1781aa">CAN_F11R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5442d8600f85b1f2efb8cd2a0a9ec764">CAN_F11R1_FB17_Msk</a></td></tr>
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<tr class="separator:gadb361a00177e6aa2ee19aa5a2d1781aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd205d1cabe770ac20592d94a9a59a02" id="r_gadd205d1cabe770ac20592d94a9a59a02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd205d1cabe770ac20592d94a9a59a02">CAN_F11R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga882ce3ab193542e376fb5f6d4f497a46" id="r_ga882ce3ab193542e376fb5f6d4f497a46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga882ce3ab193542e376fb5f6d4f497a46">CAN_F11R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadd205d1cabe770ac20592d94a9a59a02">CAN_F11R1_FB18_Pos</a>)</td></tr>
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<tr class="memitem:gaf111110e0f5dbda31962f7732e3480c7" id="r_gaf111110e0f5dbda31962f7732e3480c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf111110e0f5dbda31962f7732e3480c7">CAN_F11R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga882ce3ab193542e376fb5f6d4f497a46">CAN_F11R1_FB18_Msk</a></td></tr>
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<tr class="separator:gaf111110e0f5dbda31962f7732e3480c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdda7d2445b53f67f690c62be9246090" id="r_gacdda7d2445b53f67f690c62be9246090"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdda7d2445b53f67f690c62be9246090">CAN_F11R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:gacdda7d2445b53f67f690c62be9246090"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d345cf87d73bed1e41d1fdd1da16378" id="r_ga3d345cf87d73bed1e41d1fdd1da16378"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d345cf87d73bed1e41d1fdd1da16378">CAN_F11R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacdda7d2445b53f67f690c62be9246090">CAN_F11R1_FB19_Pos</a>)</td></tr>
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<tr class="memitem:gabf2c4828b07b2b315d27b382818de285" id="r_gabf2c4828b07b2b315d27b382818de285"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf2c4828b07b2b315d27b382818de285">CAN_F11R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d345cf87d73bed1e41d1fdd1da16378">CAN_F11R1_FB19_Msk</a></td></tr>
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<tr class="separator:gabf2c4828b07b2b315d27b382818de285"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bc43b832b438ebbad185e628f43c46c" id="r_ga0bc43b832b438ebbad185e628f43c46c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bc43b832b438ebbad185e628f43c46c">CAN_F11R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga0bc43b832b438ebbad185e628f43c46c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7955a656970b266f1398cdfc4bdb6cb" id="r_gad7955a656970b266f1398cdfc4bdb6cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7955a656970b266f1398cdfc4bdb6cb">CAN_F11R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bc43b832b438ebbad185e628f43c46c">CAN_F11R1_FB20_Pos</a>)</td></tr>
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<tr class="separator:gad7955a656970b266f1398cdfc4bdb6cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5afa52941bb68a03ec9804b817d5a90e" id="r_ga5afa52941bb68a03ec9804b817d5a90e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5afa52941bb68a03ec9804b817d5a90e">CAN_F11R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad7955a656970b266f1398cdfc4bdb6cb">CAN_F11R1_FB20_Msk</a></td></tr>
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<tr class="separator:ga5afa52941bb68a03ec9804b817d5a90e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga407a5d20941e9430ed2d0a146328ac31" id="r_ga407a5d20941e9430ed2d0a146328ac31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga407a5d20941e9430ed2d0a146328ac31">CAN_F11R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="memitem:ga0a5b2c12419c4cff708970be601ad3e2" id="r_ga0a5b2c12419c4cff708970be601ad3e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a5b2c12419c4cff708970be601ad3e2">CAN_F11R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga407a5d20941e9430ed2d0a146328ac31">CAN_F11R1_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga0a5b2c12419c4cff708970be601ad3e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac042471dbcb1a32ce161f38a144ac5aa" id="r_gac042471dbcb1a32ce161f38a144ac5aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac042471dbcb1a32ce161f38a144ac5aa">CAN_F11R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a5b2c12419c4cff708970be601ad3e2">CAN_F11R1_FB21_Msk</a></td></tr>
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<tr class="separator:gac042471dbcb1a32ce161f38a144ac5aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2af39e6af45c497fc6f8f9e21892aff" id="r_gae2af39e6af45c497fc6f8f9e21892aff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2af39e6af45c497fc6f8f9e21892aff">CAN_F11R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gae2af39e6af45c497fc6f8f9e21892aff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ad2a3cd3442663331b96444d1ed798e" id="r_ga5ad2a3cd3442663331b96444d1ed798e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ad2a3cd3442663331b96444d1ed798e">CAN_F11R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae2af39e6af45c497fc6f8f9e21892aff">CAN_F11R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga5ad2a3cd3442663331b96444d1ed798e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac46f233c9692cb2a2e246daf6547a38" id="r_gaac46f233c9692cb2a2e246daf6547a38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac46f233c9692cb2a2e246daf6547a38">CAN_F11R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ad2a3cd3442663331b96444d1ed798e">CAN_F11R1_FB22_Msk</a></td></tr>
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<tr class="separator:gaac46f233c9692cb2a2e246daf6547a38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga413238cb6d5869b63b343f15b589a7d0" id="r_ga413238cb6d5869b63b343f15b589a7d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga413238cb6d5869b63b343f15b589a7d0">CAN_F11R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga413238cb6d5869b63b343f15b589a7d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0869365b6223739ccb3b62cfadd9f1db" id="r_ga0869365b6223739ccb3b62cfadd9f1db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0869365b6223739ccb3b62cfadd9f1db">CAN_F11R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga413238cb6d5869b63b343f15b589a7d0">CAN_F11R1_FB23_Pos</a>)</td></tr>
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<tr class="memitem:gab8b379e3832482f2b18f01713d3338d5" id="r_gab8b379e3832482f2b18f01713d3338d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8b379e3832482f2b18f01713d3338d5">CAN_F11R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0869365b6223739ccb3b62cfadd9f1db">CAN_F11R1_FB23_Msk</a></td></tr>
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<tr class="separator:gab8b379e3832482f2b18f01713d3338d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac72a9af5034ed0aedfb37bf45717785f" id="r_gac72a9af5034ed0aedfb37bf45717785f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac72a9af5034ed0aedfb37bf45717785f">CAN_F11R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga4ed24f7ad9ae64b130e3e2ce65cf5d04" id="r_ga4ed24f7ad9ae64b130e3e2ce65cf5d04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ed24f7ad9ae64b130e3e2ce65cf5d04">CAN_F11R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac72a9af5034ed0aedfb37bf45717785f">CAN_F11R1_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga4ed24f7ad9ae64b130e3e2ce65cf5d04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60eabd8db9ec6b439d60dbc2374ce84d" id="r_ga60eabd8db9ec6b439d60dbc2374ce84d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60eabd8db9ec6b439d60dbc2374ce84d">CAN_F11R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ed24f7ad9ae64b130e3e2ce65cf5d04">CAN_F11R1_FB24_Msk</a></td></tr>
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<tr class="separator:ga60eabd8db9ec6b439d60dbc2374ce84d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3375fdb7a20bb2603e470ceefb5ea811" id="r_ga3375fdb7a20bb2603e470ceefb5ea811"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3375fdb7a20bb2603e470ceefb5ea811">CAN_F11R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga3375fdb7a20bb2603e470ceefb5ea811"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c2fdd934f06f41139da93cf271c9e5b" id="r_ga9c2fdd934f06f41139da93cf271c9e5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c2fdd934f06f41139da93cf271c9e5b">CAN_F11R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3375fdb7a20bb2603e470ceefb5ea811">CAN_F11R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga9c2fdd934f06f41139da93cf271c9e5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga351a183cfab10d3daab415c85cc16203" id="r_ga351a183cfab10d3daab415c85cc16203"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga351a183cfab10d3daab415c85cc16203">CAN_F11R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c2fdd934f06f41139da93cf271c9e5b">CAN_F11R1_FB25_Msk</a></td></tr>
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<tr class="separator:ga351a183cfab10d3daab415c85cc16203"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga856a5c13143c62e9fe351bc40419273a" id="r_ga856a5c13143c62e9fe351bc40419273a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga856a5c13143c62e9fe351bc40419273a">CAN_F11R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga856a5c13143c62e9fe351bc40419273a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga547f899b4aaa6323c75dc4660cc6dd4e" id="r_ga547f899b4aaa6323c75dc4660cc6dd4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga547f899b4aaa6323c75dc4660cc6dd4e">CAN_F11R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga856a5c13143c62e9fe351bc40419273a">CAN_F11R1_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga547f899b4aaa6323c75dc4660cc6dd4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb854a85c7a575a45cdade37efb4edee" id="r_gabb854a85c7a575a45cdade37efb4edee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb854a85c7a575a45cdade37efb4edee">CAN_F11R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga547f899b4aaa6323c75dc4660cc6dd4e">CAN_F11R1_FB26_Msk</a></td></tr>
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<tr class="separator:gabb854a85c7a575a45cdade37efb4edee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bc7863389837d8c6e58d46c87543339" id="r_ga4bc7863389837d8c6e58d46c87543339"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bc7863389837d8c6e58d46c87543339">CAN_F11R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga4bc7863389837d8c6e58d46c87543339"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5499db54e781ed6a09c987857d851e4b" id="r_ga5499db54e781ed6a09c987857d851e4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5499db54e781ed6a09c987857d851e4b">CAN_F11R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bc7863389837d8c6e58d46c87543339">CAN_F11R1_FB27_Pos</a>)</td></tr>
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<tr class="memitem:ga131776c359f81500d3d2a97535d7e718" id="r_ga131776c359f81500d3d2a97535d7e718"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga131776c359f81500d3d2a97535d7e718">CAN_F11R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5499db54e781ed6a09c987857d851e4b">CAN_F11R1_FB27_Msk</a></td></tr>
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<tr class="separator:ga131776c359f81500d3d2a97535d7e718"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6146861f9546873f507b6ec159010caf" id="r_ga6146861f9546873f507b6ec159010caf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6146861f9546873f507b6ec159010caf">CAN_F11R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="memitem:ga80b8ed435fa7866580be0ec7cfada3ce" id="r_ga80b8ed435fa7866580be0ec7cfada3ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80b8ed435fa7866580be0ec7cfada3ce">CAN_F11R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6146861f9546873f507b6ec159010caf">CAN_F11R1_FB28_Pos</a>)</td></tr>
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<tr class="memitem:ga680d7e4c7ebc431a8c72c00e9f110563" id="r_ga680d7e4c7ebc431a8c72c00e9f110563"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga680d7e4c7ebc431a8c72c00e9f110563">CAN_F11R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga80b8ed435fa7866580be0ec7cfada3ce">CAN_F11R1_FB28_Msk</a></td></tr>
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<tr class="separator:ga680d7e4c7ebc431a8c72c00e9f110563"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14db22bec110547f85af0a1d37723bdc" id="r_ga14db22bec110547f85af0a1d37723bdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14db22bec110547f85af0a1d37723bdc">CAN_F11R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="memitem:ga2fa11c1e2e43d9234f768ca5f3db3521" id="r_ga2fa11c1e2e43d9234f768ca5f3db3521"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fa11c1e2e43d9234f768ca5f3db3521">CAN_F11R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14db22bec110547f85af0a1d37723bdc">CAN_F11R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:ga2fa11c1e2e43d9234f768ca5f3db3521"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c1fa00ee18804c169541d18995dc3c1" id="r_ga9c1fa00ee18804c169541d18995dc3c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c1fa00ee18804c169541d18995dc3c1">CAN_F11R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2fa11c1e2e43d9234f768ca5f3db3521">CAN_F11R1_FB29_Msk</a></td></tr>
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<tr class="separator:ga9c1fa00ee18804c169541d18995dc3c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed80cbf06c649fa59a60cc19bffb3ca5" id="r_gaed80cbf06c649fa59a60cc19bffb3ca5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed80cbf06c649fa59a60cc19bffb3ca5">CAN_F11R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="memitem:ga665b624ef9be8a7b67fd0d0c8a2cc28d" id="r_ga665b624ef9be8a7b67fd0d0c8a2cc28d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga665b624ef9be8a7b67fd0d0c8a2cc28d">CAN_F11R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed80cbf06c649fa59a60cc19bffb3ca5">CAN_F11R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga665b624ef9be8a7b67fd0d0c8a2cc28d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec35d8d1097816c5ef8e28ff61469669" id="r_gaec35d8d1097816c5ef8e28ff61469669"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec35d8d1097816c5ef8e28ff61469669">CAN_F11R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga665b624ef9be8a7b67fd0d0c8a2cc28d">CAN_F11R1_FB30_Msk</a></td></tr>
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<tr class="memitem:gac933da1992c44dc61bea38e44c376f01" id="r_gac933da1992c44dc61bea38e44c376f01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac933da1992c44dc61bea38e44c376f01">CAN_F11R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:gac933da1992c44dc61bea38e44c376f01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb79224e74be4064c186c1fd8f430b3f" id="r_gafb79224e74be4064c186c1fd8f430b3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb79224e74be4064c186c1fd8f430b3f">CAN_F11R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac933da1992c44dc61bea38e44c376f01">CAN_F11R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:gafb79224e74be4064c186c1fd8f430b3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96180b8c64aabd33f016fb97ba152f07" id="r_ga96180b8c64aabd33f016fb97ba152f07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96180b8c64aabd33f016fb97ba152f07">CAN_F11R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb79224e74be4064c186c1fd8f430b3f">CAN_F11R1_FB31_Msk</a></td></tr>
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<tr class="memitem:ga3f295f2367e770b2d0a6c376512bf73a" id="r_ga3f295f2367e770b2d0a6c376512bf73a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f295f2367e770b2d0a6c376512bf73a">CAN_F12R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3f295f2367e770b2d0a6c376512bf73a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga493ad4f71737d83380a81e3df1fafca6" id="r_ga493ad4f71737d83380a81e3df1fafca6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga493ad4f71737d83380a81e3df1fafca6">CAN_F12R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f295f2367e770b2d0a6c376512bf73a">CAN_F12R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga493ad4f71737d83380a81e3df1fafca6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccbe3637fb55f28496ca7f692a69f6ca" id="r_gaccbe3637fb55f28496ca7f692a69f6ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccbe3637fb55f28496ca7f692a69f6ca">CAN_F12R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga493ad4f71737d83380a81e3df1fafca6">CAN_F12R1_FB0_Msk</a></td></tr>
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<tr class="separator:gaccbe3637fb55f28496ca7f692a69f6ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17093a08b107416231f3d9028b7e161d" id="r_ga17093a08b107416231f3d9028b7e161d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17093a08b107416231f3d9028b7e161d">CAN_F12R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga17093a08b107416231f3d9028b7e161d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a4cc96e515fe07094a824e27ad4d925" id="r_ga2a4cc96e515fe07094a824e27ad4d925"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a4cc96e515fe07094a824e27ad4d925">CAN_F12R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17093a08b107416231f3d9028b7e161d">CAN_F12R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga2a4cc96e515fe07094a824e27ad4d925"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae625d21947ae82cc3509b06363ad0635" id="r_gae625d21947ae82cc3509b06363ad0635"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae625d21947ae82cc3509b06363ad0635">CAN_F12R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a4cc96e515fe07094a824e27ad4d925">CAN_F12R1_FB1_Msk</a></td></tr>
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<tr class="separator:gae625d21947ae82cc3509b06363ad0635"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9311ab17c937d6e57b9e2e5ae93494b4" id="r_ga9311ab17c937d6e57b9e2e5ae93494b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9311ab17c937d6e57b9e2e5ae93494b4">CAN_F12R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga9311ab17c937d6e57b9e2e5ae93494b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c8d6c0e2c177e40ff60568beffac86b" id="r_ga6c8d6c0e2c177e40ff60568beffac86b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c8d6c0e2c177e40ff60568beffac86b">CAN_F12R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9311ab17c937d6e57b9e2e5ae93494b4">CAN_F12R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga6c8d6c0e2c177e40ff60568beffac86b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9de7cc313f2b6b16a564b13b1bc30157" id="r_ga9de7cc313f2b6b16a564b13b1bc30157"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9de7cc313f2b6b16a564b13b1bc30157">CAN_F12R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c8d6c0e2c177e40ff60568beffac86b">CAN_F12R1_FB2_Msk</a></td></tr>
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<tr class="separator:ga9de7cc313f2b6b16a564b13b1bc30157"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8158fab7bc36d56b1202e637d45e0ee9" id="r_ga8158fab7bc36d56b1202e637d45e0ee9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8158fab7bc36d56b1202e637d45e0ee9">CAN_F12R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga8158fab7bc36d56b1202e637d45e0ee9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34c79794004930e3de57c8417f7c5d6d" id="r_ga34c79794004930e3de57c8417f7c5d6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34c79794004930e3de57c8417f7c5d6d">CAN_F12R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8158fab7bc36d56b1202e637d45e0ee9">CAN_F12R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga34c79794004930e3de57c8417f7c5d6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac039cc1ce2281cf10be62cbc44748f5f" id="r_gac039cc1ce2281cf10be62cbc44748f5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac039cc1ce2281cf10be62cbc44748f5f">CAN_F12R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34c79794004930e3de57c8417f7c5d6d">CAN_F12R1_FB3_Msk</a></td></tr>
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<tr class="separator:gac039cc1ce2281cf10be62cbc44748f5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2db6bf56bfc0ceb513363931e2f032dc" id="r_ga2db6bf56bfc0ceb513363931e2f032dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6bf56bfc0ceb513363931e2f032dc">CAN_F12R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga2db6bf56bfc0ceb513363931e2f032dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93b358c5c72ac735e4c7c802287f9903" id="r_ga93b358c5c72ac735e4c7c802287f9903"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93b358c5c72ac735e4c7c802287f9903">CAN_F12R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6bf56bfc0ceb513363931e2f032dc">CAN_F12R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga93b358c5c72ac735e4c7c802287f9903"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc3a35b6f6b3a46c176398ec322fd6fb" id="r_gabc3a35b6f6b3a46c176398ec322fd6fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc3a35b6f6b3a46c176398ec322fd6fb">CAN_F12R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga93b358c5c72ac735e4c7c802287f9903">CAN_F12R1_FB4_Msk</a></td></tr>
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<tr class="separator:gabc3a35b6f6b3a46c176398ec322fd6fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2298551f803cc3ee122b170a68369c63" id="r_ga2298551f803cc3ee122b170a68369c63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2298551f803cc3ee122b170a68369c63">CAN_F12R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga2298551f803cc3ee122b170a68369c63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9cc058f703f84921bf889c9ce3c000d0" id="r_ga9cc058f703f84921bf889c9ce3c000d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cc058f703f84921bf889c9ce3c000d0">CAN_F12R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2298551f803cc3ee122b170a68369c63">CAN_F12R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga9cc058f703f84921bf889c9ce3c000d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d005c10fe75169336104c3155294000" id="r_ga4d005c10fe75169336104c3155294000"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d005c10fe75169336104c3155294000">CAN_F12R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9cc058f703f84921bf889c9ce3c000d0">CAN_F12R1_FB5_Msk</a></td></tr>
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<tr class="separator:ga4d005c10fe75169336104c3155294000"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2183cc81753585bdca7ca731db48f6ae" id="r_ga2183cc81753585bdca7ca731db48f6ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2183cc81753585bdca7ca731db48f6ae">CAN_F12R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga2183cc81753585bdca7ca731db48f6ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86849d0bdcd7b03a0770c9fb4e1c0cf8" id="r_ga86849d0bdcd7b03a0770c9fb4e1c0cf8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86849d0bdcd7b03a0770c9fb4e1c0cf8">CAN_F12R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2183cc81753585bdca7ca731db48f6ae">CAN_F12R1_FB6_Pos</a>)</td></tr>
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<tr class="memitem:ga51256bfed734a95da3e7880e279432bf" id="r_ga51256bfed734a95da3e7880e279432bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51256bfed734a95da3e7880e279432bf">CAN_F12R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86849d0bdcd7b03a0770c9fb4e1c0cf8">CAN_F12R1_FB6_Msk</a></td></tr>
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<tr class="memitem:ga7f008c792182223c7f2ed45c5cec3461" id="r_ga7f008c792182223c7f2ed45c5cec3461"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f008c792182223c7f2ed45c5cec3461">CAN_F12R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga7f008c792182223c7f2ed45c5cec3461"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd7e08cb6960016b6a352bd8353733dd" id="r_gabd7e08cb6960016b6a352bd8353733dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd7e08cb6960016b6a352bd8353733dd">CAN_F12R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f008c792182223c7f2ed45c5cec3461">CAN_F12R1_FB7_Pos</a>)</td></tr>
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<tr class="separator:gabd7e08cb6960016b6a352bd8353733dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c967f124b03968372d801e1393fa209" id="r_ga2c967f124b03968372d801e1393fa209"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c967f124b03968372d801e1393fa209">CAN_F12R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd7e08cb6960016b6a352bd8353733dd">CAN_F12R1_FB7_Msk</a></td></tr>
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<tr class="separator:ga2c967f124b03968372d801e1393fa209"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb125f5efb6b0daae3758f92a2aadcbb" id="r_gadb125f5efb6b0daae3758f92a2aadcbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb125f5efb6b0daae3758f92a2aadcbb">CAN_F12R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gadb125f5efb6b0daae3758f92a2aadcbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad138ae340d080c7b69b9dfe0814234f6" id="r_gad138ae340d080c7b69b9dfe0814234f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad138ae340d080c7b69b9dfe0814234f6">CAN_F12R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb125f5efb6b0daae3758f92a2aadcbb">CAN_F12R1_FB8_Pos</a>)</td></tr>
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<tr class="separator:gad138ae340d080c7b69b9dfe0814234f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga592f9953deeb56888144c72060d04e24" id="r_ga592f9953deeb56888144c72060d04e24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga592f9953deeb56888144c72060d04e24">CAN_F12R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad138ae340d080c7b69b9dfe0814234f6">CAN_F12R1_FB8_Msk</a></td></tr>
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<tr class="separator:ga592f9953deeb56888144c72060d04e24"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf5573719f28f6259a0c06f933691797" id="r_gacf5573719f28f6259a0c06f933691797"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf5573719f28f6259a0c06f933691797">CAN_F12R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gacf5573719f28f6259a0c06f933691797"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb0713b2abf45e4c66dfc0c2f4aa902c" id="r_gadb0713b2abf45e4c66dfc0c2f4aa902c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb0713b2abf45e4c66dfc0c2f4aa902c">CAN_F12R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf5573719f28f6259a0c06f933691797">CAN_F12R1_FB9_Pos</a>)</td></tr>
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<tr class="separator:gadb0713b2abf45e4c66dfc0c2f4aa902c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d1613eac2aaeafda711cf3308ccd44c" id="r_ga4d1613eac2aaeafda711cf3308ccd44c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d1613eac2aaeafda711cf3308ccd44c">CAN_F12R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadb0713b2abf45e4c66dfc0c2f4aa902c">CAN_F12R1_FB9_Msk</a></td></tr>
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<tr class="separator:ga4d1613eac2aaeafda711cf3308ccd44c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae32861a7d09171945a044611c0799be5" id="r_gae32861a7d09171945a044611c0799be5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae32861a7d09171945a044611c0799be5">CAN_F12R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gae32861a7d09171945a044611c0799be5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3becedeec4964364eb6a6ca51af6c7a7" id="r_ga3becedeec4964364eb6a6ca51af6c7a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3becedeec4964364eb6a6ca51af6c7a7">CAN_F12R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae32861a7d09171945a044611c0799be5">CAN_F12R1_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga3becedeec4964364eb6a6ca51af6c7a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b8594ab0c5d9124accd2d6ca85cf4bd" id="r_ga1b8594ab0c5d9124accd2d6ca85cf4bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b8594ab0c5d9124accd2d6ca85cf4bd">CAN_F12R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3becedeec4964364eb6a6ca51af6c7a7">CAN_F12R1_FB10_Msk</a></td></tr>
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<tr class="separator:ga1b8594ab0c5d9124accd2d6ca85cf4bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga038226b9a5057333b93511a33a628df5" id="r_ga038226b9a5057333b93511a33a628df5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga038226b9a5057333b93511a33a628df5">CAN_F12R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga038226b9a5057333b93511a33a628df5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ab33464326b0107849ae73eb2d74649" id="r_ga0ab33464326b0107849ae73eb2d74649"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ab33464326b0107849ae73eb2d74649">CAN_F12R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga038226b9a5057333b93511a33a628df5">CAN_F12R1_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga0ab33464326b0107849ae73eb2d74649"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4025ed76892f23e5a63d0d8ac6a2be5f" id="r_ga4025ed76892f23e5a63d0d8ac6a2be5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4025ed76892f23e5a63d0d8ac6a2be5f">CAN_F12R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ab33464326b0107849ae73eb2d74649">CAN_F12R1_FB11_Msk</a></td></tr>
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<tr class="separator:ga4025ed76892f23e5a63d0d8ac6a2be5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50aa1cdae5ac88b5dfb35f4e7fa1efa6" id="r_ga50aa1cdae5ac88b5dfb35f4e7fa1efa6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50aa1cdae5ac88b5dfb35f4e7fa1efa6">CAN_F12R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga50aa1cdae5ac88b5dfb35f4e7fa1efa6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac55c96f63d9cb2115cf779e2108cd2c2" id="r_gac55c96f63d9cb2115cf779e2108cd2c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac55c96f63d9cb2115cf779e2108cd2c2">CAN_F12R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga50aa1cdae5ac88b5dfb35f4e7fa1efa6">CAN_F12R1_FB12_Pos</a>)</td></tr>
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<tr class="separator:gac55c96f63d9cb2115cf779e2108cd2c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e2e318cc14828c118bd40d982922e14" id="r_ga6e2e318cc14828c118bd40d982922e14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e2e318cc14828c118bd40d982922e14">CAN_F12R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac55c96f63d9cb2115cf779e2108cd2c2">CAN_F12R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga6e2e318cc14828c118bd40d982922e14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4705c5fa21a51b511e077c3812068f53" id="r_ga4705c5fa21a51b511e077c3812068f53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4705c5fa21a51b511e077c3812068f53">CAN_F12R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga4705c5fa21a51b511e077c3812068f53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6754922701ae479453231e3082f5995" id="r_gaf6754922701ae479453231e3082f5995"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6754922701ae479453231e3082f5995">CAN_F12R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4705c5fa21a51b511e077c3812068f53">CAN_F12R1_FB13_Pos</a>)</td></tr>
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<tr class="separator:gaf6754922701ae479453231e3082f5995"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e0ff698b5e9f3f99a421166611b041d" id="r_ga4e0ff698b5e9f3f99a421166611b041d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e0ff698b5e9f3f99a421166611b041d">CAN_F12R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6754922701ae479453231e3082f5995">CAN_F12R1_FB13_Msk</a></td></tr>
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<tr class="separator:ga4e0ff698b5e9f3f99a421166611b041d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabece220b17e1d4e3d305e083f7a8cdf6" id="r_gabece220b17e1d4e3d305e083f7a8cdf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabece220b17e1d4e3d305e083f7a8cdf6">CAN_F12R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gabece220b17e1d4e3d305e083f7a8cdf6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40af5057b396387a1162d0091b2d826e" id="r_ga40af5057b396387a1162d0091b2d826e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40af5057b396387a1162d0091b2d826e">CAN_F12R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabece220b17e1d4e3d305e083f7a8cdf6">CAN_F12R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:ga40af5057b396387a1162d0091b2d826e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b0666538a7646ddc0fcd882a261f5d9" id="r_ga6b0666538a7646ddc0fcd882a261f5d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b0666538a7646ddc0fcd882a261f5d9">CAN_F12R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga40af5057b396387a1162d0091b2d826e">CAN_F12R1_FB14_Msk</a></td></tr>
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<tr class="separator:ga6b0666538a7646ddc0fcd882a261f5d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdd867683a9a1ea022cfa4211a5079d0" id="r_gabdd867683a9a1ea022cfa4211a5079d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdd867683a9a1ea022cfa4211a5079d0">CAN_F12R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gabdd867683a9a1ea022cfa4211a5079d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4a4f362ed99f3b71078c88c720f7603" id="r_gae4a4f362ed99f3b71078c88c720f7603"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4a4f362ed99f3b71078c88c720f7603">CAN_F12R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabdd867683a9a1ea022cfa4211a5079d0">CAN_F12R1_FB15_Pos</a>)</td></tr>
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<tr class="separator:gae4a4f362ed99f3b71078c88c720f7603"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga846d84b3d53e305b093198379f442528" id="r_ga846d84b3d53e305b093198379f442528"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga846d84b3d53e305b093198379f442528">CAN_F12R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae4a4f362ed99f3b71078c88c720f7603">CAN_F12R1_FB15_Msk</a></td></tr>
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<tr class="separator:ga846d84b3d53e305b093198379f442528"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab018f535eba98e6869cb39a15b6b27d6" id="r_gab018f535eba98e6869cb39a15b6b27d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab018f535eba98e6869cb39a15b6b27d6">CAN_F12R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:gab018f535eba98e6869cb39a15b6b27d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44038ad11ff535489420a521d43090cd" id="r_ga44038ad11ff535489420a521d43090cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44038ad11ff535489420a521d43090cd">CAN_F12R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab018f535eba98e6869cb39a15b6b27d6">CAN_F12R1_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga44038ad11ff535489420a521d43090cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7940c0898c2ef1d9f829bf1b6b5fcf3" id="r_gad7940c0898c2ef1d9f829bf1b6b5fcf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7940c0898c2ef1d9f829bf1b6b5fcf3">CAN_F12R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44038ad11ff535489420a521d43090cd">CAN_F12R1_FB16_Msk</a></td></tr>
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<tr class="separator:gad7940c0898c2ef1d9f829bf1b6b5fcf3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga518951f7f8d5f8a22f7782ea13a2ac0c" id="r_ga518951f7f8d5f8a22f7782ea13a2ac0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga518951f7f8d5f8a22f7782ea13a2ac0c">CAN_F12R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga518951f7f8d5f8a22f7782ea13a2ac0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1462a6bf5fd7f197bf4fc6b40f3531e" id="r_gab1462a6bf5fd7f197bf4fc6b40f3531e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1462a6bf5fd7f197bf4fc6b40f3531e">CAN_F12R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga518951f7f8d5f8a22f7782ea13a2ac0c">CAN_F12R1_FB17_Pos</a>)</td></tr>
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<tr class="separator:gab1462a6bf5fd7f197bf4fc6b40f3531e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bdc7bd4dbad1f8e3bb622343bd7c522" id="r_ga6bdc7bd4dbad1f8e3bb622343bd7c522"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bdc7bd4dbad1f8e3bb622343bd7c522">CAN_F12R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab1462a6bf5fd7f197bf4fc6b40f3531e">CAN_F12R1_FB17_Msk</a></td></tr>
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<tr class="separator:ga6bdc7bd4dbad1f8e3bb622343bd7c522"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1f6af451262400037581950b32da4b8" id="r_gac1f6af451262400037581950b32da4b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1f6af451262400037581950b32da4b8">CAN_F12R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga1ded4d9316004285d4c49d62eb48cce6" id="r_ga1ded4d9316004285d4c49d62eb48cce6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ded4d9316004285d4c49d62eb48cce6">CAN_F12R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac1f6af451262400037581950b32da4b8">CAN_F12R1_FB18_Pos</a>)</td></tr>
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<tr class="separator:ga1ded4d9316004285d4c49d62eb48cce6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c870a6fbae41b4f1c6d66ab690789d6" id="r_ga7c870a6fbae41b4f1c6d66ab690789d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c870a6fbae41b4f1c6d66ab690789d6">CAN_F12R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ded4d9316004285d4c49d62eb48cce6">CAN_F12R1_FB18_Msk</a></td></tr>
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<tr class="separator:ga7c870a6fbae41b4f1c6d66ab690789d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f9e3a6b9cf0673647bd9adfeadb887c" id="r_ga3f9e3a6b9cf0673647bd9adfeadb887c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f9e3a6b9cf0673647bd9adfeadb887c">CAN_F12R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga3f9e3a6b9cf0673647bd9adfeadb887c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38b5a9bb84c7973eb3aee9bcc751a402" id="r_ga38b5a9bb84c7973eb3aee9bcc751a402"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38b5a9bb84c7973eb3aee9bcc751a402">CAN_F12R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f9e3a6b9cf0673647bd9adfeadb887c">CAN_F12R1_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga38b5a9bb84c7973eb3aee9bcc751a402"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09e179b38460e47b81616c46a5f356f8" id="r_ga09e179b38460e47b81616c46a5f356f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09e179b38460e47b81616c46a5f356f8">CAN_F12R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38b5a9bb84c7973eb3aee9bcc751a402">CAN_F12R1_FB19_Msk</a></td></tr>
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<tr class="separator:ga09e179b38460e47b81616c46a5f356f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a25348307ed3392337ad2a40bdfe73a" id="r_ga4a25348307ed3392337ad2a40bdfe73a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a25348307ed3392337ad2a40bdfe73a">CAN_F12R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga4a25348307ed3392337ad2a40bdfe73a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33e4aaef17496cf40db364d4c7ead7d5" id="r_ga33e4aaef17496cf40db364d4c7ead7d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33e4aaef17496cf40db364d4c7ead7d5">CAN_F12R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a25348307ed3392337ad2a40bdfe73a">CAN_F12R1_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga33e4aaef17496cf40db364d4c7ead7d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad42e298d4d97c98cc5149bc552a598fa" id="r_gad42e298d4d97c98cc5149bc552a598fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad42e298d4d97c98cc5149bc552a598fa">CAN_F12R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga33e4aaef17496cf40db364d4c7ead7d5">CAN_F12R1_FB20_Msk</a></td></tr>
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<tr class="separator:gad42e298d4d97c98cc5149bc552a598fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga752faf78fd8e420905118261b231241c" id="r_ga752faf78fd8e420905118261b231241c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga752faf78fd8e420905118261b231241c">CAN_F12R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga752faf78fd8e420905118261b231241c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga776befd35d22caa64a1754b75134f2a6" id="r_ga776befd35d22caa64a1754b75134f2a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga776befd35d22caa64a1754b75134f2a6">CAN_F12R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga752faf78fd8e420905118261b231241c">CAN_F12R1_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga776befd35d22caa64a1754b75134f2a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga318e2a6ae62d5172dcdb45e011d5e0c4" id="r_ga318e2a6ae62d5172dcdb45e011d5e0c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga318e2a6ae62d5172dcdb45e011d5e0c4">CAN_F12R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga776befd35d22caa64a1754b75134f2a6">CAN_F12R1_FB21_Msk</a></td></tr>
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<tr class="separator:ga318e2a6ae62d5172dcdb45e011d5e0c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3238cf7161e4270d40115f5b61431a22" id="r_ga3238cf7161e4270d40115f5b61431a22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3238cf7161e4270d40115f5b61431a22">CAN_F12R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga3238cf7161e4270d40115f5b61431a22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d5b00cf1faf748d52633ee2a1989b49" id="r_ga2d5b00cf1faf748d52633ee2a1989b49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d5b00cf1faf748d52633ee2a1989b49">CAN_F12R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3238cf7161e4270d40115f5b61431a22">CAN_F12R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga2d5b00cf1faf748d52633ee2a1989b49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90e95cb0020289335acd5d7f4b62a880" id="r_ga90e95cb0020289335acd5d7f4b62a880"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90e95cb0020289335acd5d7f4b62a880">CAN_F12R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d5b00cf1faf748d52633ee2a1989b49">CAN_F12R1_FB22_Msk</a></td></tr>
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<tr class="separator:ga90e95cb0020289335acd5d7f4b62a880"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd7d9b502598ae8cc04847d5cf9c0b52" id="r_gabd7d9b502598ae8cc04847d5cf9c0b52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd7d9b502598ae8cc04847d5cf9c0b52">CAN_F12R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gabd7d9b502598ae8cc04847d5cf9c0b52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa9c58f403ed9bfc19a23aff1960065e" id="r_gaaa9c58f403ed9bfc19a23aff1960065e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa9c58f403ed9bfc19a23aff1960065e">CAN_F12R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabd7d9b502598ae8cc04847d5cf9c0b52">CAN_F12R1_FB23_Pos</a>)</td></tr>
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<tr class="separator:gaaa9c58f403ed9bfc19a23aff1960065e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e2720e18fdff00c9fb75d5136e485dc" id="r_ga2e2720e18fdff00c9fb75d5136e485dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e2720e18fdff00c9fb75d5136e485dc">CAN_F12R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa9c58f403ed9bfc19a23aff1960065e">CAN_F12R1_FB23_Msk</a></td></tr>
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<tr class="separator:ga2e2720e18fdff00c9fb75d5136e485dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b9e2a2787690c33948183acf3e600fd" id="r_ga1b9e2a2787690c33948183acf3e600fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b9e2a2787690c33948183acf3e600fd">CAN_F12R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga1b9e2a2787690c33948183acf3e600fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7efaf0ba941dc22a8a322e75d6495237" id="r_ga7efaf0ba941dc22a8a322e75d6495237"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7efaf0ba941dc22a8a322e75d6495237">CAN_F12R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b9e2a2787690c33948183acf3e600fd">CAN_F12R1_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga7efaf0ba941dc22a8a322e75d6495237"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4a87123ae5ff76992162152fbb4c92a" id="r_gae4a87123ae5ff76992162152fbb4c92a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4a87123ae5ff76992162152fbb4c92a">CAN_F12R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7efaf0ba941dc22a8a322e75d6495237">CAN_F12R1_FB24_Msk</a></td></tr>
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<tr class="separator:gae4a87123ae5ff76992162152fbb4c92a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae772d3a7da965bbd759aa2ffceeb3ae4" id="r_gae772d3a7da965bbd759aa2ffceeb3ae4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae772d3a7da965bbd759aa2ffceeb3ae4">CAN_F12R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gae772d3a7da965bbd759aa2ffceeb3ae4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga495bdfd934bc40aeabfcb0454e47a2c7" id="r_ga495bdfd934bc40aeabfcb0454e47a2c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga495bdfd934bc40aeabfcb0454e47a2c7">CAN_F12R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae772d3a7da965bbd759aa2ffceeb3ae4">CAN_F12R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga495bdfd934bc40aeabfcb0454e47a2c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9582717e16455f97c7dff65f7beadd6e" id="r_ga9582717e16455f97c7dff65f7beadd6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9582717e16455f97c7dff65f7beadd6e">CAN_F12R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga495bdfd934bc40aeabfcb0454e47a2c7">CAN_F12R1_FB25_Msk</a></td></tr>
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<tr class="separator:ga9582717e16455f97c7dff65f7beadd6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48905689b327cf537df7a4e7f12ed097" id="r_ga48905689b327cf537df7a4e7f12ed097"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48905689b327cf537df7a4e7f12ed097">CAN_F12R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga48905689b327cf537df7a4e7f12ed097"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26edbc0aad33ae916a2c765f8a463023" id="r_ga26edbc0aad33ae916a2c765f8a463023"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26edbc0aad33ae916a2c765f8a463023">CAN_F12R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48905689b327cf537df7a4e7f12ed097">CAN_F12R1_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga26edbc0aad33ae916a2c765f8a463023"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf15e362beb5a3b733c08c8c2ab81efcb" id="r_gaf15e362beb5a3b733c08c8c2ab81efcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf15e362beb5a3b733c08c8c2ab81efcb">CAN_F12R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga26edbc0aad33ae916a2c765f8a463023">CAN_F12R1_FB26_Msk</a></td></tr>
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<tr class="separator:gaf15e362beb5a3b733c08c8c2ab81efcb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaece06032650d7777a44ada0b8cc4a85b" id="r_gaece06032650d7777a44ada0b8cc4a85b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaece06032650d7777a44ada0b8cc4a85b">CAN_F12R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:gaece06032650d7777a44ada0b8cc4a85b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb051023923964df52386c58e0ee26ed" id="r_gabb051023923964df52386c58e0ee26ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb051023923964df52386c58e0ee26ed">CAN_F12R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaece06032650d7777a44ada0b8cc4a85b">CAN_F12R1_FB27_Pos</a>)</td></tr>
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<tr class="separator:gabb051023923964df52386c58e0ee26ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d600a7a39c7069c216db511d3a5d866" id="r_ga3d600a7a39c7069c216db511d3a5d866"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d600a7a39c7069c216db511d3a5d866">CAN_F12R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabb051023923964df52386c58e0ee26ed">CAN_F12R1_FB27_Msk</a></td></tr>
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<tr class="separator:ga3d600a7a39c7069c216db511d3a5d866"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3fe5041f598b90c619dfa60edee91ced" id="r_ga3fe5041f598b90c619dfa60edee91ced"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3fe5041f598b90c619dfa60edee91ced">CAN_F12R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga3fe5041f598b90c619dfa60edee91ced"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e1bbde0fef2e2dab933da257a3afd66" id="r_ga8e1bbde0fef2e2dab933da257a3afd66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e1bbde0fef2e2dab933da257a3afd66">CAN_F12R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3fe5041f598b90c619dfa60edee91ced">CAN_F12R1_FB28_Pos</a>)</td></tr>
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<tr class="memitem:gab9a6addc248c6db2118d1ce6e049d331" id="r_gab9a6addc248c6db2118d1ce6e049d331"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9a6addc248c6db2118d1ce6e049d331">CAN_F12R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e1bbde0fef2e2dab933da257a3afd66">CAN_F12R1_FB28_Msk</a></td></tr>
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<tr class="memitem:ga89f3ef59e719e677cd850e299d9961a5" id="r_ga89f3ef59e719e677cd850e299d9961a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89f3ef59e719e677cd850e299d9961a5">CAN_F12R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="memitem:ga9d988431331cf581558317c045e1117b" id="r_ga9d988431331cf581558317c045e1117b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d988431331cf581558317c045e1117b">CAN_F12R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga89f3ef59e719e677cd850e299d9961a5">CAN_F12R1_FB29_Pos</a>)</td></tr>
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<tr class="memitem:ga31d3a46845cd9ca6670472aae2aa2ebe" id="r_ga31d3a46845cd9ca6670472aae2aa2ebe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31d3a46845cd9ca6670472aae2aa2ebe">CAN_F12R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d988431331cf581558317c045e1117b">CAN_F12R1_FB29_Msk</a></td></tr>
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<tr class="separator:ga31d3a46845cd9ca6670472aae2aa2ebe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0704718cb8d28fcbdb546e660b109e73" id="r_ga0704718cb8d28fcbdb546e660b109e73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0704718cb8d28fcbdb546e660b109e73">CAN_F12R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga0704718cb8d28fcbdb546e660b109e73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03b733b7cb7755ebe4678bf011a490f5" id="r_ga03b733b7cb7755ebe4678bf011a490f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03b733b7cb7755ebe4678bf011a490f5">CAN_F12R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0704718cb8d28fcbdb546e660b109e73">CAN_F12R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga03b733b7cb7755ebe4678bf011a490f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa06596dcbb545fbeea2ec20f629d9555" id="r_gaa06596dcbb545fbeea2ec20f629d9555"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa06596dcbb545fbeea2ec20f629d9555">CAN_F12R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga03b733b7cb7755ebe4678bf011a490f5">CAN_F12R1_FB30_Msk</a></td></tr>
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<tr class="separator:gaa06596dcbb545fbeea2ec20f629d9555"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b666278c8cbde1fda669c22af52c2ab" id="r_ga5b666278c8cbde1fda669c22af52c2ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b666278c8cbde1fda669c22af52c2ab">CAN_F12R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga5b666278c8cbde1fda669c22af52c2ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47ce05849eef3967db74c9dcab8d936e" id="r_ga47ce05849eef3967db74c9dcab8d936e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47ce05849eef3967db74c9dcab8d936e">CAN_F12R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b666278c8cbde1fda669c22af52c2ab">CAN_F12R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga47ce05849eef3967db74c9dcab8d936e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac441b11b1be9b3608b9a09c2b8069722" id="r_gac441b11b1be9b3608b9a09c2b8069722"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac441b11b1be9b3608b9a09c2b8069722">CAN_F12R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47ce05849eef3967db74c9dcab8d936e">CAN_F12R1_FB31_Msk</a></td></tr>
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<tr class="separator:gac441b11b1be9b3608b9a09c2b8069722"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02ab98a53a5893c727ea9957188ee26a" id="r_ga02ab98a53a5893c727ea9957188ee26a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02ab98a53a5893c727ea9957188ee26a">CAN_F13R1_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga02ab98a53a5893c727ea9957188ee26a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0775804606cd66638da3f6ba1b3b493" id="r_gae0775804606cd66638da3f6ba1b3b493"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0775804606cd66638da3f6ba1b3b493">CAN_F13R1_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02ab98a53a5893c727ea9957188ee26a">CAN_F13R1_FB0_Pos</a>)</td></tr>
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<tr class="separator:gae0775804606cd66638da3f6ba1b3b493"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa20d063950ad122a1965527a17d93c37" id="r_gaa20d063950ad122a1965527a17d93c37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa20d063950ad122a1965527a17d93c37">CAN_F13R1_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae0775804606cd66638da3f6ba1b3b493">CAN_F13R1_FB0_Msk</a></td></tr>
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<tr class="separator:gaa20d063950ad122a1965527a17d93c37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35f9a2ceccf6229be57bb4145d593543" id="r_ga35f9a2ceccf6229be57bb4145d593543"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35f9a2ceccf6229be57bb4145d593543">CAN_F13R1_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga35f9a2ceccf6229be57bb4145d593543"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5af825390c54a3a65aac39d6a998ca48" id="r_ga5af825390c54a3a65aac39d6a998ca48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5af825390c54a3a65aac39d6a998ca48">CAN_F13R1_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga35f9a2ceccf6229be57bb4145d593543">CAN_F13R1_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga5af825390c54a3a65aac39d6a998ca48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf60decd61c8a8dc9e4342de8ad67ea76" id="r_gaf60decd61c8a8dc9e4342de8ad67ea76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf60decd61c8a8dc9e4342de8ad67ea76">CAN_F13R1_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5af825390c54a3a65aac39d6a998ca48">CAN_F13R1_FB1_Msk</a></td></tr>
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<tr class="separator:gaf60decd61c8a8dc9e4342de8ad67ea76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6613018ad3a9b1086f63172d3fa5322" id="r_gad6613018ad3a9b1086f63172d3fa5322"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6613018ad3a9b1086f63172d3fa5322">CAN_F13R1_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gad6613018ad3a9b1086f63172d3fa5322"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34ca97bf95c63ac91fe0bbf664f96c5a" id="r_ga34ca97bf95c63ac91fe0bbf664f96c5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34ca97bf95c63ac91fe0bbf664f96c5a">CAN_F13R1_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad6613018ad3a9b1086f63172d3fa5322">CAN_F13R1_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga34ca97bf95c63ac91fe0bbf664f96c5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7863b3af06385d0e9037c57a5d2091e2" id="r_ga7863b3af06385d0e9037c57a5d2091e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7863b3af06385d0e9037c57a5d2091e2">CAN_F13R1_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34ca97bf95c63ac91fe0bbf664f96c5a">CAN_F13R1_FB2_Msk</a></td></tr>
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<tr class="separator:ga7863b3af06385d0e9037c57a5d2091e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38212e081d0a3d8b9b5384f034a5407a" id="r_ga38212e081d0a3d8b9b5384f034a5407a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38212e081d0a3d8b9b5384f034a5407a">CAN_F13R1_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga38212e081d0a3d8b9b5384f034a5407a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf217b9312083ea4fee7d1e808d6abb84" id="r_gaf217b9312083ea4fee7d1e808d6abb84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf217b9312083ea4fee7d1e808d6abb84">CAN_F13R1_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga38212e081d0a3d8b9b5384f034a5407a">CAN_F13R1_FB3_Pos</a>)</td></tr>
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<tr class="separator:gaf217b9312083ea4fee7d1e808d6abb84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga043282b30813ce88dbdb320936ff6aca" id="r_ga043282b30813ce88dbdb320936ff6aca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga043282b30813ce88dbdb320936ff6aca">CAN_F13R1_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf217b9312083ea4fee7d1e808d6abb84">CAN_F13R1_FB3_Msk</a></td></tr>
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<tr class="separator:ga043282b30813ce88dbdb320936ff6aca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdcbf72e68c8d4c217a3cc35c9a6a19d" id="r_gacdcbf72e68c8d4c217a3cc35c9a6a19d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdcbf72e68c8d4c217a3cc35c9a6a19d">CAN_F13R1_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gacdcbf72e68c8d4c217a3cc35c9a6a19d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga325e27d4b7557c9da7685eaaefdd9bbe" id="r_ga325e27d4b7557c9da7685eaaefdd9bbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga325e27d4b7557c9da7685eaaefdd9bbe">CAN_F13R1_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacdcbf72e68c8d4c217a3cc35c9a6a19d">CAN_F13R1_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga325e27d4b7557c9da7685eaaefdd9bbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bbc9e9866f20d9d2f3cea1c6777c673" id="r_ga3bbc9e9866f20d9d2f3cea1c6777c673"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bbc9e9866f20d9d2f3cea1c6777c673">CAN_F13R1_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga325e27d4b7557c9da7685eaaefdd9bbe">CAN_F13R1_FB4_Msk</a></td></tr>
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<tr class="separator:ga3bbc9e9866f20d9d2f3cea1c6777c673"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6317c62241dd862ad43be5bd0ce74696" id="r_ga6317c62241dd862ad43be5bd0ce74696"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6317c62241dd862ad43be5bd0ce74696">CAN_F13R1_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga6317c62241dd862ad43be5bd0ce74696"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53dda4ae54ad09328863f96688745173" id="r_ga53dda4ae54ad09328863f96688745173"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53dda4ae54ad09328863f96688745173">CAN_F13R1_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6317c62241dd862ad43be5bd0ce74696">CAN_F13R1_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga53dda4ae54ad09328863f96688745173"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga885b36e017b013ab6deedd91d9ac2c66" id="r_ga885b36e017b013ab6deedd91d9ac2c66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga885b36e017b013ab6deedd91d9ac2c66">CAN_F13R1_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga53dda4ae54ad09328863f96688745173">CAN_F13R1_FB5_Msk</a></td></tr>
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<tr class="separator:ga885b36e017b013ab6deedd91d9ac2c66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga097998c68e6f03b713fe2eae37670c72" id="r_ga097998c68e6f03b713fe2eae37670c72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga097998c68e6f03b713fe2eae37670c72">CAN_F13R1_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga097998c68e6f03b713fe2eae37670c72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae396c50fbe96dbdd418620ffd2fa5b4" id="r_gaae396c50fbe96dbdd418620ffd2fa5b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae396c50fbe96dbdd418620ffd2fa5b4">CAN_F13R1_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga097998c68e6f03b713fe2eae37670c72">CAN_F13R1_FB6_Pos</a>)</td></tr>
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<tr class="separator:gaae396c50fbe96dbdd418620ffd2fa5b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa389b53582e5cacf326fff4512626d68" id="r_gaa389b53582e5cacf326fff4512626d68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa389b53582e5cacf326fff4512626d68">CAN_F13R1_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae396c50fbe96dbdd418620ffd2fa5b4">CAN_F13R1_FB6_Msk</a></td></tr>
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<tr class="separator:gaa389b53582e5cacf326fff4512626d68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad30d6f9e145dbaf24c55480181072280" id="r_gad30d6f9e145dbaf24c55480181072280"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad30d6f9e145dbaf24c55480181072280">CAN_F13R1_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gad30d6f9e145dbaf24c55480181072280"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0a54488273ee23a74dfe0a0deca7d7d" id="r_gad0a54488273ee23a74dfe0a0deca7d7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0a54488273ee23a74dfe0a0deca7d7d">CAN_F13R1_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad30d6f9e145dbaf24c55480181072280">CAN_F13R1_FB7_Pos</a>)</td></tr>
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<tr class="memitem:gad09b75feeda08b16962db7da6a32dc9b" id="r_gad09b75feeda08b16962db7da6a32dc9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad09b75feeda08b16962db7da6a32dc9b">CAN_F13R1_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad0a54488273ee23a74dfe0a0deca7d7d">CAN_F13R1_FB7_Msk</a></td></tr>
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<tr class="memitem:ga1b8cb9dd079a3116919ec1e48f3267b7" id="r_ga1b8cb9dd079a3116919ec1e48f3267b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b8cb9dd079a3116919ec1e48f3267b7">CAN_F13R1_FB8_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gad8c2421189d009e0b2630cf53f0caaf1" id="r_gad8c2421189d009e0b2630cf53f0caaf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8c2421189d009e0b2630cf53f0caaf1">CAN_F13R1_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b8cb9dd079a3116919ec1e48f3267b7">CAN_F13R1_FB8_Pos</a>)</td></tr>
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<tr class="memitem:gaaba75675c019979882ecd8c6ef82d7a4" id="r_gaaba75675c019979882ecd8c6ef82d7a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaba75675c019979882ecd8c6ef82d7a4">CAN_F13R1_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad8c2421189d009e0b2630cf53f0caaf1">CAN_F13R1_FB8_Msk</a></td></tr>
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<tr class="memitem:gacd53ccc27879017d3a67b404b6cc2e8e" id="r_gacd53ccc27879017d3a67b404b6cc2e8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd53ccc27879017d3a67b404b6cc2e8e">CAN_F13R1_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gacd53ccc27879017d3a67b404b6cc2e8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa365ae887f59e0e1684a5ed96fb50042" id="r_gaa365ae887f59e0e1684a5ed96fb50042"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa365ae887f59e0e1684a5ed96fb50042">CAN_F13R1_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacd53ccc27879017d3a67b404b6cc2e8e">CAN_F13R1_FB9_Pos</a>)</td></tr>
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<tr class="memitem:gac579473f666edec0e0fcce278b642a9d" id="r_gac579473f666edec0e0fcce278b642a9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac579473f666edec0e0fcce278b642a9d">CAN_F13R1_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa365ae887f59e0e1684a5ed96fb50042">CAN_F13R1_FB9_Msk</a></td></tr>
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<tr class="memitem:ga25a6f5d5b2e92245427b68c7961e76c6" id="r_ga25a6f5d5b2e92245427b68c7961e76c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25a6f5d5b2e92245427b68c7961e76c6">CAN_F13R1_FB10_Pos</a>   (10U)</td></tr>
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<tr class="memitem:ga2439f107e699d239c00b630979ba87e1" id="r_ga2439f107e699d239c00b630979ba87e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2439f107e699d239c00b630979ba87e1">CAN_F13R1_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25a6f5d5b2e92245427b68c7961e76c6">CAN_F13R1_FB10_Pos</a>)</td></tr>
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<tr class="memitem:ga14640c225c434428ef1870f462eb9bbd" id="r_ga14640c225c434428ef1870f462eb9bbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14640c225c434428ef1870f462eb9bbd">CAN_F13R1_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2439f107e699d239c00b630979ba87e1">CAN_F13R1_FB10_Msk</a></td></tr>
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<tr class="memitem:gab5f5353506ab2189b95cc97232c4fae4" id="r_gab5f5353506ab2189b95cc97232c4fae4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5f5353506ab2189b95cc97232c4fae4">CAN_F13R1_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gab5f5353506ab2189b95cc97232c4fae4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9103107051eb07e5ae903489b76eb2c4" id="r_ga9103107051eb07e5ae903489b76eb2c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9103107051eb07e5ae903489b76eb2c4">CAN_F13R1_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5f5353506ab2189b95cc97232c4fae4">CAN_F13R1_FB11_Pos</a>)</td></tr>
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<tr class="memitem:ga7d8c9f5879cc4e31fe2e63f82febbc69" id="r_ga7d8c9f5879cc4e31fe2e63f82febbc69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d8c9f5879cc4e31fe2e63f82febbc69">CAN_F13R1_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9103107051eb07e5ae903489b76eb2c4">CAN_F13R1_FB11_Msk</a></td></tr>
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<tr class="memitem:gaef2be27cb238beb59c18bdb3b874f96e" id="r_gaef2be27cb238beb59c18bdb3b874f96e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef2be27cb238beb59c18bdb3b874f96e">CAN_F13R1_FB12_Pos</a>   (12U)</td></tr>
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<tr class="memitem:ga9dabd107a2de9ccd6461da5926e4d4e4" id="r_ga9dabd107a2de9ccd6461da5926e4d4e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9dabd107a2de9ccd6461da5926e4d4e4">CAN_F13R1_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef2be27cb238beb59c18bdb3b874f96e">CAN_F13R1_FB12_Pos</a>)</td></tr>
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<tr class="memitem:ga8e0e3cfe033bb34f62312cfe47d1b84a" id="r_ga8e0e3cfe033bb34f62312cfe47d1b84a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e0e3cfe033bb34f62312cfe47d1b84a">CAN_F13R1_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9dabd107a2de9ccd6461da5926e4d4e4">CAN_F13R1_FB12_Msk</a></td></tr>
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<tr class="separator:ga8e0e3cfe033bb34f62312cfe47d1b84a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c3512eefb28504e6db269b9cd68202e" id="r_ga7c3512eefb28504e6db269b9cd68202e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c3512eefb28504e6db269b9cd68202e">CAN_F13R1_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga7c3512eefb28504e6db269b9cd68202e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1db0ef6756bc958994e6fc702ce75b81" id="r_ga1db0ef6756bc958994e6fc702ce75b81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1db0ef6756bc958994e6fc702ce75b81">CAN_F13R1_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c3512eefb28504e6db269b9cd68202e">CAN_F13R1_FB13_Pos</a>)</td></tr>
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<tr class="memitem:ga93d91a28c1ffca3f72f10e0b44040791" id="r_ga93d91a28c1ffca3f72f10e0b44040791"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93d91a28c1ffca3f72f10e0b44040791">CAN_F13R1_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1db0ef6756bc958994e6fc702ce75b81">CAN_F13R1_FB13_Msk</a></td></tr>
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<tr class="memitem:gac817b1dbf5b97572d61f4cb97ac35395" id="r_gac817b1dbf5b97572d61f4cb97ac35395"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac817b1dbf5b97572d61f4cb97ac35395">CAN_F13R1_FB14_Pos</a>   (14U)</td></tr>
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<tr class="memitem:ga1412e4fcd6edb251cf356694de9f3f42" id="r_ga1412e4fcd6edb251cf356694de9f3f42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1412e4fcd6edb251cf356694de9f3f42">CAN_F13R1_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac817b1dbf5b97572d61f4cb97ac35395">CAN_F13R1_FB14_Pos</a>)</td></tr>
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<tr class="separator:ga1412e4fcd6edb251cf356694de9f3f42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga355b438a5abccec89e13bdd00206b36f" id="r_ga355b438a5abccec89e13bdd00206b36f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga355b438a5abccec89e13bdd00206b36f">CAN_F13R1_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1412e4fcd6edb251cf356694de9f3f42">CAN_F13R1_FB14_Msk</a></td></tr>
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<tr class="separator:ga355b438a5abccec89e13bdd00206b36f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba2fba83e1654499f506bfe603b877a6" id="r_gaba2fba83e1654499f506bfe603b877a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba2fba83e1654499f506bfe603b877a6">CAN_F13R1_FB15_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga0cc8b54a2836661fdd482c004556cba1" id="r_ga0cc8b54a2836661fdd482c004556cba1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cc8b54a2836661fdd482c004556cba1">CAN_F13R1_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba2fba83e1654499f506bfe603b877a6">CAN_F13R1_FB15_Pos</a>)</td></tr>
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<tr class="memitem:ga89b23d147d2c040eb2317633b3ef46da" id="r_ga89b23d147d2c040eb2317633b3ef46da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89b23d147d2c040eb2317633b3ef46da">CAN_F13R1_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cc8b54a2836661fdd482c004556cba1">CAN_F13R1_FB15_Msk</a></td></tr>
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<tr class="memitem:ga0cdea57e0dff6ff19f5cc60f4307e25c" id="r_ga0cdea57e0dff6ff19f5cc60f4307e25c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cdea57e0dff6ff19f5cc60f4307e25c">CAN_F13R1_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga0cdea57e0dff6ff19f5cc60f4307e25c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d570ecd25032c69017c3c117f0aebdf" id="r_ga7d570ecd25032c69017c3c117f0aebdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d570ecd25032c69017c3c117f0aebdf">CAN_F13R1_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cdea57e0dff6ff19f5cc60f4307e25c">CAN_F13R1_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga7d570ecd25032c69017c3c117f0aebdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81d184cd46306fe24b46087a90e8f8f2" id="r_ga81d184cd46306fe24b46087a90e8f8f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81d184cd46306fe24b46087a90e8f8f2">CAN_F13R1_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d570ecd25032c69017c3c117f0aebdf">CAN_F13R1_FB16_Msk</a></td></tr>
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<tr class="separator:ga81d184cd46306fe24b46087a90e8f8f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa862da872daa901ad2449731d9218b4d" id="r_gaa862da872daa901ad2449731d9218b4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa862da872daa901ad2449731d9218b4d">CAN_F13R1_FB17_Pos</a>   (17U)</td></tr>
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<tr class="memitem:gaef2321a184dc8aa13baef70a5cb6193f" id="r_gaef2321a184dc8aa13baef70a5cb6193f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef2321a184dc8aa13baef70a5cb6193f">CAN_F13R1_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa862da872daa901ad2449731d9218b4d">CAN_F13R1_FB17_Pos</a>)</td></tr>
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<tr class="memitem:ga151a0e903046edc92bddcd0ef4a23449" id="r_ga151a0e903046edc92bddcd0ef4a23449"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga151a0e903046edc92bddcd0ef4a23449">CAN_F13R1_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaef2321a184dc8aa13baef70a5cb6193f">CAN_F13R1_FB17_Msk</a></td></tr>
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<tr class="memitem:ga8f93c38f644d676c7241d539765e044a" id="r_ga8f93c38f644d676c7241d539765e044a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f93c38f644d676c7241d539765e044a">CAN_F13R1_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:gae27c24ba203819e140dfddb8bc05c473" id="r_gae27c24ba203819e140dfddb8bc05c473"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae27c24ba203819e140dfddb8bc05c473">CAN_F13R1_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f93c38f644d676c7241d539765e044a">CAN_F13R1_FB18_Pos</a>)</td></tr>
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<tr class="memitem:ga9e95e6d0d060fb2cfdf31e1b5fdfe3de" id="r_ga9e95e6d0d060fb2cfdf31e1b5fdfe3de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e95e6d0d060fb2cfdf31e1b5fdfe3de">CAN_F13R1_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae27c24ba203819e140dfddb8bc05c473">CAN_F13R1_FB18_Msk</a></td></tr>
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<tr class="separator:ga9e95e6d0d060fb2cfdf31e1b5fdfe3de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga962217baf4c2af30fc495a0eb0b51879" id="r_ga962217baf4c2af30fc495a0eb0b51879"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga962217baf4c2af30fc495a0eb0b51879">CAN_F13R1_FB19_Pos</a>   (19U)</td></tr>
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<tr class="memitem:ga471095d382cce78017304b5db76f7a04" id="r_ga471095d382cce78017304b5db76f7a04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga471095d382cce78017304b5db76f7a04">CAN_F13R1_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga962217baf4c2af30fc495a0eb0b51879">CAN_F13R1_FB19_Pos</a>)</td></tr>
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<tr class="memitem:ga1e0fb1cf032c57f954dd2679a05f8115" id="r_ga1e0fb1cf032c57f954dd2679a05f8115"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e0fb1cf032c57f954dd2679a05f8115">CAN_F13R1_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga471095d382cce78017304b5db76f7a04">CAN_F13R1_FB19_Msk</a></td></tr>
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<tr class="separator:ga1e0fb1cf032c57f954dd2679a05f8115"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48c0363bcb1ee7fa09ecf22f6b94ed2a" id="r_ga48c0363bcb1ee7fa09ecf22f6b94ed2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48c0363bcb1ee7fa09ecf22f6b94ed2a">CAN_F13R1_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga48c0363bcb1ee7fa09ecf22f6b94ed2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c097cf8909e3cc7825d9500a891be52" id="r_ga5c097cf8909e3cc7825d9500a891be52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c097cf8909e3cc7825d9500a891be52">CAN_F13R1_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48c0363bcb1ee7fa09ecf22f6b94ed2a">CAN_F13R1_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga5c097cf8909e3cc7825d9500a891be52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb775bb1ded6a8f55f2a0849bec2eeac" id="r_gaeb775bb1ded6a8f55f2a0849bec2eeac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb775bb1ded6a8f55f2a0849bec2eeac">CAN_F13R1_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c097cf8909e3cc7825d9500a891be52">CAN_F13R1_FB20_Msk</a></td></tr>
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<tr class="separator:gaeb775bb1ded6a8f55f2a0849bec2eeac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga556fb1d9d20383d707a69806152d2571" id="r_ga556fb1d9d20383d707a69806152d2571"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga556fb1d9d20383d707a69806152d2571">CAN_F13R1_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga556fb1d9d20383d707a69806152d2571"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3523d0b622d476255e22d07d76831a75" id="r_ga3523d0b622d476255e22d07d76831a75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3523d0b622d476255e22d07d76831a75">CAN_F13R1_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga556fb1d9d20383d707a69806152d2571">CAN_F13R1_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga3523d0b622d476255e22d07d76831a75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8743dfb60255d98911ea66605efd3b2f" id="r_ga8743dfb60255d98911ea66605efd3b2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8743dfb60255d98911ea66605efd3b2f">CAN_F13R1_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3523d0b622d476255e22d07d76831a75">CAN_F13R1_FB21_Msk</a></td></tr>
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<tr class="memitem:gaec41136c74e99a37d9aca5c92ac9a93c" id="r_gaec41136c74e99a37d9aca5c92ac9a93c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec41136c74e99a37d9aca5c92ac9a93c">CAN_F13R1_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gaec41136c74e99a37d9aca5c92ac9a93c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae50e71fdf75fcc3e59b95b855d3bf30a" id="r_gae50e71fdf75fcc3e59b95b855d3bf30a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae50e71fdf75fcc3e59b95b855d3bf30a">CAN_F13R1_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaec41136c74e99a37d9aca5c92ac9a93c">CAN_F13R1_FB22_Pos</a>)</td></tr>
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<tr class="separator:gae50e71fdf75fcc3e59b95b855d3bf30a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54b067c38f3be3ad6041ea12fec15700" id="r_ga54b067c38f3be3ad6041ea12fec15700"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54b067c38f3be3ad6041ea12fec15700">CAN_F13R1_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae50e71fdf75fcc3e59b95b855d3bf30a">CAN_F13R1_FB22_Msk</a></td></tr>
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<tr class="separator:ga54b067c38f3be3ad6041ea12fec15700"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7686cf2ffa6e927845c1064994c8d392" id="r_ga7686cf2ffa6e927845c1064994c8d392"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7686cf2ffa6e927845c1064994c8d392">CAN_F13R1_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga7686cf2ffa6e927845c1064994c8d392"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45b6b1f5126bfa15739a086d6734cfd5" id="r_ga45b6b1f5126bfa15739a086d6734cfd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45b6b1f5126bfa15739a086d6734cfd5">CAN_F13R1_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7686cf2ffa6e927845c1064994c8d392">CAN_F13R1_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga45b6b1f5126bfa15739a086d6734cfd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00fe1942d9a8767a76f139bd74eafea0" id="r_ga00fe1942d9a8767a76f139bd74eafea0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00fe1942d9a8767a76f139bd74eafea0">CAN_F13R1_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45b6b1f5126bfa15739a086d6734cfd5">CAN_F13R1_FB23_Msk</a></td></tr>
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<tr class="separator:ga00fe1942d9a8767a76f139bd74eafea0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab03f0061f54b4b410c91e61836225912" id="r_gab03f0061f54b4b410c91e61836225912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab03f0061f54b4b410c91e61836225912">CAN_F13R1_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:gab03f0061f54b4b410c91e61836225912"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga710ae584f88078c05820eede3729b65c" id="r_ga710ae584f88078c05820eede3729b65c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga710ae584f88078c05820eede3729b65c">CAN_F13R1_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab03f0061f54b4b410c91e61836225912">CAN_F13R1_FB24_Pos</a>)</td></tr>
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<tr class="memitem:ga05db1c0a2e6e051d616b59f386dc7b1e" id="r_ga05db1c0a2e6e051d616b59f386dc7b1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05db1c0a2e6e051d616b59f386dc7b1e">CAN_F13R1_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga710ae584f88078c05820eede3729b65c">CAN_F13R1_FB24_Msk</a></td></tr>
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<tr class="memitem:ga2e9fea689cdeac8918508a183517d0db" id="r_ga2e9fea689cdeac8918508a183517d0db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e9fea689cdeac8918508a183517d0db">CAN_F13R1_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga2e9fea689cdeac8918508a183517d0db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f2580d7250fa56c7a1e25f9d282c942" id="r_ga0f2580d7250fa56c7a1e25f9d282c942"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f2580d7250fa56c7a1e25f9d282c942">CAN_F13R1_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e9fea689cdeac8918508a183517d0db">CAN_F13R1_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga0f2580d7250fa56c7a1e25f9d282c942"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66dd0da9fd8ef27b30f1ad56a9982caf" id="r_ga66dd0da9fd8ef27b30f1ad56a9982caf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66dd0da9fd8ef27b30f1ad56a9982caf">CAN_F13R1_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f2580d7250fa56c7a1e25f9d282c942">CAN_F13R1_FB25_Msk</a></td></tr>
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<tr class="separator:ga66dd0da9fd8ef27b30f1ad56a9982caf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9eb77bfba6b6a7db4562bce8bb35316b" id="r_ga9eb77bfba6b6a7db4562bce8bb35316b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9eb77bfba6b6a7db4562bce8bb35316b">CAN_F13R1_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga9eb77bfba6b6a7db4562bce8bb35316b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdd8f8b38bc3d56b97c8909c7dbb7560" id="r_gafdd8f8b38bc3d56b97c8909c7dbb7560"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdd8f8b38bc3d56b97c8909c7dbb7560">CAN_F13R1_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9eb77bfba6b6a7db4562bce8bb35316b">CAN_F13R1_FB26_Pos</a>)</td></tr>
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<tr class="memitem:gaf3b8381bc6ce5ab107cc1a92e565387a" id="r_gaf3b8381bc6ce5ab107cc1a92e565387a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3b8381bc6ce5ab107cc1a92e565387a">CAN_F13R1_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafdd8f8b38bc3d56b97c8909c7dbb7560">CAN_F13R1_FB26_Msk</a></td></tr>
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<tr class="separator:gaf3b8381bc6ce5ab107cc1a92e565387a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb78e36a1d8975246d7437b4b3d8c0aa" id="r_gadb78e36a1d8975246d7437b4b3d8c0aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb78e36a1d8975246d7437b4b3d8c0aa">CAN_F13R1_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:gadb78e36a1d8975246d7437b4b3d8c0aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc69c07f91f2c9d6b85c3f26532fad1f" id="r_gafc69c07f91f2c9d6b85c3f26532fad1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc69c07f91f2c9d6b85c3f26532fad1f">CAN_F13R1_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb78e36a1d8975246d7437b4b3d8c0aa">CAN_F13R1_FB27_Pos</a>)</td></tr>
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<tr class="separator:gafc69c07f91f2c9d6b85c3f26532fad1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91c99de5ae099ecdee50ebd62e552df5" id="r_ga91c99de5ae099ecdee50ebd62e552df5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91c99de5ae099ecdee50ebd62e552df5">CAN_F13R1_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafc69c07f91f2c9d6b85c3f26532fad1f">CAN_F13R1_FB27_Msk</a></td></tr>
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<tr class="separator:ga91c99de5ae099ecdee50ebd62e552df5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ab2ee1db50c027b505177c9b65af835" id="r_ga4ab2ee1db50c027b505177c9b65af835"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ab2ee1db50c027b505177c9b65af835">CAN_F13R1_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga4ab2ee1db50c027b505177c9b65af835"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1dd7a2e1000f7df336489982291d76d8" id="r_ga1dd7a2e1000f7df336489982291d76d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1dd7a2e1000f7df336489982291d76d8">CAN_F13R1_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ab2ee1db50c027b505177c9b65af835">CAN_F13R1_FB28_Pos</a>)</td></tr>
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<tr class="memitem:ga83713f9e2c3c90f001ab378d9ca1f488" id="r_ga83713f9e2c3c90f001ab378d9ca1f488"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83713f9e2c3c90f001ab378d9ca1f488">CAN_F13R1_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1dd7a2e1000f7df336489982291d76d8">CAN_F13R1_FB28_Msk</a></td></tr>
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<tr class="separator:ga83713f9e2c3c90f001ab378d9ca1f488"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9eed6320b23de2023e8c8ddeb7efaa1b" id="r_ga9eed6320b23de2023e8c8ddeb7efaa1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9eed6320b23de2023e8c8ddeb7efaa1b">CAN_F13R1_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga9eed6320b23de2023e8c8ddeb7efaa1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ed837627ac02698016cdf0439782fec" id="r_ga3ed837627ac02698016cdf0439782fec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ed837627ac02698016cdf0439782fec">CAN_F13R1_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9eed6320b23de2023e8c8ddeb7efaa1b">CAN_F13R1_FB29_Pos</a>)</td></tr>
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<tr class="separator:ga3ed837627ac02698016cdf0439782fec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga050fb1e9555d0d24f81682e194677684" id="r_ga050fb1e9555d0d24f81682e194677684"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga050fb1e9555d0d24f81682e194677684">CAN_F13R1_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ed837627ac02698016cdf0439782fec">CAN_F13R1_FB29_Msk</a></td></tr>
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<tr class="memitem:ga86ba01c60b4b90ff0c58dab1c7e8bc6a" id="r_ga86ba01c60b4b90ff0c58dab1c7e8bc6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86ba01c60b4b90ff0c58dab1c7e8bc6a">CAN_F13R1_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga86ba01c60b4b90ff0c58dab1c7e8bc6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e7f63726fd4dffa870717dbf3079be8" id="r_ga6e7f63726fd4dffa870717dbf3079be8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e7f63726fd4dffa870717dbf3079be8">CAN_F13R1_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga86ba01c60b4b90ff0c58dab1c7e8bc6a">CAN_F13R1_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga6e7f63726fd4dffa870717dbf3079be8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga761164856a25bc246396c7c82fdeb447" id="r_ga761164856a25bc246396c7c82fdeb447"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga761164856a25bc246396c7c82fdeb447">CAN_F13R1_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e7f63726fd4dffa870717dbf3079be8">CAN_F13R1_FB30_Msk</a></td></tr>
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<tr class="separator:ga761164856a25bc246396c7c82fdeb447"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa0459499e89cee6ff87bb40d6b6a0d7" id="r_gaaa0459499e89cee6ff87bb40d6b6a0d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa0459499e89cee6ff87bb40d6b6a0d7">CAN_F13R1_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:gaaa0459499e89cee6ff87bb40d6b6a0d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad950a42557716b1e66d0e675d4ed0388" id="r_gad950a42557716b1e66d0e675d4ed0388"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad950a42557716b1e66d0e675d4ed0388">CAN_F13R1_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa0459499e89cee6ff87bb40d6b6a0d7">CAN_F13R1_FB31_Pos</a>)</td></tr>
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<tr class="separator:gad950a42557716b1e66d0e675d4ed0388"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a750d71e94876d2f6e73a0e8b7217b2" id="r_ga1a750d71e94876d2f6e73a0e8b7217b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a750d71e94876d2f6e73a0e8b7217b2">CAN_F13R1_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad950a42557716b1e66d0e675d4ed0388">CAN_F13R1_FB31_Msk</a></td></tr>
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<tr class="separator:ga1a750d71e94876d2f6e73a0e8b7217b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f183a8e746831c98ca9cdb8eabe867b" id="r_ga2f183a8e746831c98ca9cdb8eabe867b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f183a8e746831c98ca9cdb8eabe867b">CAN_F0R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2f183a8e746831c98ca9cdb8eabe867b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa061083b9a300dcb531acbb0ca426943" id="r_gaa061083b9a300dcb531acbb0ca426943"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa061083b9a300dcb531acbb0ca426943">CAN_F0R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f183a8e746831c98ca9cdb8eabe867b">CAN_F0R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:gaa061083b9a300dcb531acbb0ca426943"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34282ddec559ecea4b613f2430334237" id="r_ga34282ddec559ecea4b613f2430334237"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34282ddec559ecea4b613f2430334237">CAN_F0R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa061083b9a300dcb531acbb0ca426943">CAN_F0R2_FB0_Msk</a></td></tr>
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<tr class="separator:ga34282ddec559ecea4b613f2430334237"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e70a04e0d25e9e87d225a66110b5a26" id="r_ga7e70a04e0d25e9e87d225a66110b5a26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e70a04e0d25e9e87d225a66110b5a26">CAN_F0R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga7e70a04e0d25e9e87d225a66110b5a26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95c94101334ccda880f2c3a2e9e35803" id="r_ga95c94101334ccda880f2c3a2e9e35803"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95c94101334ccda880f2c3a2e9e35803">CAN_F0R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e70a04e0d25e9e87d225a66110b5a26">CAN_F0R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga95c94101334ccda880f2c3a2e9e35803"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f23fc3814e0eb6af35c01e22c5dc6a7" id="r_ga6f23fc3814e0eb6af35c01e22c5dc6a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f23fc3814e0eb6af35c01e22c5dc6a7">CAN_F0R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga95c94101334ccda880f2c3a2e9e35803">CAN_F0R2_FB1_Msk</a></td></tr>
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<tr class="separator:ga6f23fc3814e0eb6af35c01e22c5dc6a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85d2b4b2c0ce324d0b1356c60cf63257" id="r_ga85d2b4b2c0ce324d0b1356c60cf63257"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85d2b4b2c0ce324d0b1356c60cf63257">CAN_F0R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga85d2b4b2c0ce324d0b1356c60cf63257"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81d454ef34d31e40aeecb2da25e5004d" id="r_ga81d454ef34d31e40aeecb2da25e5004d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81d454ef34d31e40aeecb2da25e5004d">CAN_F0R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga85d2b4b2c0ce324d0b1356c60cf63257">CAN_F0R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga81d454ef34d31e40aeecb2da25e5004d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82ee32b6ec44d763b4364fa032d3439c" id="r_ga82ee32b6ec44d763b4364fa032d3439c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82ee32b6ec44d763b4364fa032d3439c">CAN_F0R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga81d454ef34d31e40aeecb2da25e5004d">CAN_F0R2_FB2_Msk</a></td></tr>
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<tr class="separator:ga82ee32b6ec44d763b4364fa032d3439c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad65a92a16e022fd160904677f2aa2232" id="r_gad65a92a16e022fd160904677f2aa2232"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad65a92a16e022fd160904677f2aa2232">CAN_F0R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gad65a92a16e022fd160904677f2aa2232"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga526563dd72eb6023c8c6b70ed3eef49f" id="r_ga526563dd72eb6023c8c6b70ed3eef49f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga526563dd72eb6023c8c6b70ed3eef49f">CAN_F0R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad65a92a16e022fd160904677f2aa2232">CAN_F0R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga526563dd72eb6023c8c6b70ed3eef49f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7867b1d377088c63cdcc615932101997" id="r_ga7867b1d377088c63cdcc615932101997"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7867b1d377088c63cdcc615932101997">CAN_F0R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga526563dd72eb6023c8c6b70ed3eef49f">CAN_F0R2_FB3_Msk</a></td></tr>
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<tr class="separator:ga7867b1d377088c63cdcc615932101997"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34c12a03bd031d6e0f15091903bebca4" id="r_ga34c12a03bd031d6e0f15091903bebca4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34c12a03bd031d6e0f15091903bebca4">CAN_F0R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga34c12a03bd031d6e0f15091903bebca4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e2ad8285cf2dbc13f19cde26aa841ee" id="r_ga3e2ad8285cf2dbc13f19cde26aa841ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e2ad8285cf2dbc13f19cde26aa841ee">CAN_F0R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34c12a03bd031d6e0f15091903bebca4">CAN_F0R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga3e2ad8285cf2dbc13f19cde26aa841ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37fc5c9115eb669f1ac493b1c7296250" id="r_ga37fc5c9115eb669f1ac493b1c7296250"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37fc5c9115eb669f1ac493b1c7296250">CAN_F0R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e2ad8285cf2dbc13f19cde26aa841ee">CAN_F0R2_FB4_Msk</a></td></tr>
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<tr class="separator:ga37fc5c9115eb669f1ac493b1c7296250"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e4adcc243dd4cd40a7221755e583c91" id="r_ga6e4adcc243dd4cd40a7221755e583c91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e4adcc243dd4cd40a7221755e583c91">CAN_F0R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga6e4adcc243dd4cd40a7221755e583c91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae572f8b4bb3bfa4dca31b1d4b189c277" id="r_gae572f8b4bb3bfa4dca31b1d4b189c277"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae572f8b4bb3bfa4dca31b1d4b189c277">CAN_F0R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e4adcc243dd4cd40a7221755e583c91">CAN_F0R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:gae572f8b4bb3bfa4dca31b1d4b189c277"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae04b27aad09a3027f20a4eb48884c463" id="r_gae04b27aad09a3027f20a4eb48884c463"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae04b27aad09a3027f20a4eb48884c463">CAN_F0R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae572f8b4bb3bfa4dca31b1d4b189c277">CAN_F0R2_FB5_Msk</a></td></tr>
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<tr class="separator:gae04b27aad09a3027f20a4eb48884c463"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf319616807592f75d1a61ee9d8607265" id="r_gaf319616807592f75d1a61ee9d8607265"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf319616807592f75d1a61ee9d8607265">CAN_F0R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaf319616807592f75d1a61ee9d8607265"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d86d510a3fa0f7bb396b2535ff7412f" id="r_ga1d86d510a3fa0f7bb396b2535ff7412f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d86d510a3fa0f7bb396b2535ff7412f">CAN_F0R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf319616807592f75d1a61ee9d8607265">CAN_F0R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga1d86d510a3fa0f7bb396b2535ff7412f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae58d87c9513c11593041c3d43b955e8b" id="r_gae58d87c9513c11593041c3d43b955e8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae58d87c9513c11593041c3d43b955e8b">CAN_F0R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d86d510a3fa0f7bb396b2535ff7412f">CAN_F0R2_FB6_Msk</a></td></tr>
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<tr class="separator:gae58d87c9513c11593041c3d43b955e8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e7fb85c2a88f84eb38d43bf730a11c1" id="r_ga9e7fb85c2a88f84eb38d43bf730a11c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e7fb85c2a88f84eb38d43bf730a11c1">CAN_F0R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga9e7fb85c2a88f84eb38d43bf730a11c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga931a307d0830015fa4494ed6a34e3fb5" id="r_ga931a307d0830015fa4494ed6a34e3fb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga931a307d0830015fa4494ed6a34e3fb5">CAN_F0R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e7fb85c2a88f84eb38d43bf730a11c1">CAN_F0R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga931a307d0830015fa4494ed6a34e3fb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03a6328d408b8015bb472c76f96a4dd8" id="r_ga03a6328d408b8015bb472c76f96a4dd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03a6328d408b8015bb472c76f96a4dd8">CAN_F0R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga931a307d0830015fa4494ed6a34e3fb5">CAN_F0R2_FB7_Msk</a></td></tr>
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<tr class="separator:ga03a6328d408b8015bb472c76f96a4dd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8dfb2cfa716e20ca94c9461d0c75dc1f" id="r_ga8dfb2cfa716e20ca94c9461d0c75dc1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8dfb2cfa716e20ca94c9461d0c75dc1f">CAN_F0R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga8dfb2cfa716e20ca94c9461d0c75dc1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f123f65007d2d150da67e5114b8354f" id="r_ga4f123f65007d2d150da67e5114b8354f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f123f65007d2d150da67e5114b8354f">CAN_F0R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8dfb2cfa716e20ca94c9461d0c75dc1f">CAN_F0R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga4f123f65007d2d150da67e5114b8354f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92fd1acf48665f966b670a0457456deb" id="r_ga92fd1acf48665f966b670a0457456deb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92fd1acf48665f966b670a0457456deb">CAN_F0R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f123f65007d2d150da67e5114b8354f">CAN_F0R2_FB8_Msk</a></td></tr>
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<tr class="separator:ga92fd1acf48665f966b670a0457456deb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf66c4a2200af005c5035aca282158e29" id="r_gaf66c4a2200af005c5035aca282158e29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf66c4a2200af005c5035aca282158e29">CAN_F0R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaf66c4a2200af005c5035aca282158e29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31eeb8ac004bb1a829c442474a019b05" id="r_ga31eeb8ac004bb1a829c442474a019b05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31eeb8ac004bb1a829c442474a019b05">CAN_F0R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf66c4a2200af005c5035aca282158e29">CAN_F0R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga31eeb8ac004bb1a829c442474a019b05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa853cff5493c4e857b7bb1ad28678ed4" id="r_gaa853cff5493c4e857b7bb1ad28678ed4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa853cff5493c4e857b7bb1ad28678ed4">CAN_F0R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31eeb8ac004bb1a829c442474a019b05">CAN_F0R2_FB9_Msk</a></td></tr>
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<tr class="separator:gaa853cff5493c4e857b7bb1ad28678ed4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga228d943d2ac8c3e3ca52bcc68bdd0b71" id="r_ga228d943d2ac8c3e3ca52bcc68bdd0b71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga228d943d2ac8c3e3ca52bcc68bdd0b71">CAN_F0R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga228d943d2ac8c3e3ca52bcc68bdd0b71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb8eae7e6372cafdfbb97cee0d3a5906" id="r_gadb8eae7e6372cafdfbb97cee0d3a5906"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb8eae7e6372cafdfbb97cee0d3a5906">CAN_F0R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga228d943d2ac8c3e3ca52bcc68bdd0b71">CAN_F0R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:gadb8eae7e6372cafdfbb97cee0d3a5906"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa43bba65dd777c71e07130fde3fa6216" id="r_gaa43bba65dd777c71e07130fde3fa6216"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa43bba65dd777c71e07130fde3fa6216">CAN_F0R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadb8eae7e6372cafdfbb97cee0d3a5906">CAN_F0R2_FB10_Msk</a></td></tr>
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<tr class="separator:gaa43bba65dd777c71e07130fde3fa6216"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef610b498994f7ba1842966f9390548c" id="r_gaef610b498994f7ba1842966f9390548c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef610b498994f7ba1842966f9390548c">CAN_F0R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaef610b498994f7ba1842966f9390548c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15c19ccbf1f927445c99e0075e4743f4" id="r_ga15c19ccbf1f927445c99e0075e4743f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15c19ccbf1f927445c99e0075e4743f4">CAN_F0R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef610b498994f7ba1842966f9390548c">CAN_F0R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga15c19ccbf1f927445c99e0075e4743f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9077b9c35c6721d2a0e090a42af0eaaf" id="r_ga9077b9c35c6721d2a0e090a42af0eaaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9077b9c35c6721d2a0e090a42af0eaaf">CAN_F0R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga15c19ccbf1f927445c99e0075e4743f4">CAN_F0R2_FB11_Msk</a></td></tr>
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<tr class="separator:ga9077b9c35c6721d2a0e090a42af0eaaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7158038c6c98cd727869fa152286ac06" id="r_ga7158038c6c98cd727869fa152286ac06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7158038c6c98cd727869fa152286ac06">CAN_F0R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga7158038c6c98cd727869fa152286ac06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec6f3f414927987a2409f6a4fcee1950" id="r_gaec6f3f414927987a2409f6a4fcee1950"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec6f3f414927987a2409f6a4fcee1950">CAN_F0R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7158038c6c98cd727869fa152286ac06">CAN_F0R2_FB12_Pos</a>)</td></tr>
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<tr class="separator:gaec6f3f414927987a2409f6a4fcee1950"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23af8df7d4e843a6e196b1542421ef45" id="r_ga23af8df7d4e843a6e196b1542421ef45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23af8df7d4e843a6e196b1542421ef45">CAN_F0R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec6f3f414927987a2409f6a4fcee1950">CAN_F0R2_FB12_Msk</a></td></tr>
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<tr class="separator:ga23af8df7d4e843a6e196b1542421ef45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0430b63b617ae1318cbb17291a67035" id="r_gaa0430b63b617ae1318cbb17291a67035"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0430b63b617ae1318cbb17291a67035">CAN_F0R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaa0430b63b617ae1318cbb17291a67035"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f965255e5ae450386165052ebc91266" id="r_ga0f965255e5ae450386165052ebc91266"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f965255e5ae450386165052ebc91266">CAN_F0R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0430b63b617ae1318cbb17291a67035">CAN_F0R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga0f965255e5ae450386165052ebc91266"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fe7776af3adce7d203aeb16d55d86d4" id="r_ga0fe7776af3adce7d203aeb16d55d86d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fe7776af3adce7d203aeb16d55d86d4">CAN_F0R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f965255e5ae450386165052ebc91266">CAN_F0R2_FB13_Msk</a></td></tr>
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<tr class="separator:ga0fe7776af3adce7d203aeb16d55d86d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f653bbe8993cfe6546ea2947fe85837" id="r_ga5f653bbe8993cfe6546ea2947fe85837"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f653bbe8993cfe6546ea2947fe85837">CAN_F0R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga5f653bbe8993cfe6546ea2947fe85837"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga541cda96227f171eeaef984ec3f3bfde" id="r_ga541cda96227f171eeaef984ec3f3bfde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga541cda96227f171eeaef984ec3f3bfde">CAN_F0R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f653bbe8993cfe6546ea2947fe85837">CAN_F0R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:ga541cda96227f171eeaef984ec3f3bfde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81168efb90a776e44a96d1fe5e3b88c3" id="r_ga81168efb90a776e44a96d1fe5e3b88c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81168efb90a776e44a96d1fe5e3b88c3">CAN_F0R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga541cda96227f171eeaef984ec3f3bfde">CAN_F0R2_FB14_Msk</a></td></tr>
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<tr class="separator:ga81168efb90a776e44a96d1fe5e3b88c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07875079d9eb2ea959eeec1f42e8e469" id="r_ga07875079d9eb2ea959eeec1f42e8e469"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07875079d9eb2ea959eeec1f42e8e469">CAN_F0R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga07875079d9eb2ea959eeec1f42e8e469"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ec4acee70dd0bad3bcfb650e47f99b5" id="r_ga9ec4acee70dd0bad3bcfb650e47f99b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ec4acee70dd0bad3bcfb650e47f99b5">CAN_F0R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07875079d9eb2ea959eeec1f42e8e469">CAN_F0R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga9ec4acee70dd0bad3bcfb650e47f99b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9708e7cde70a19e8e8fa33291e1b9d5" id="r_gae9708e7cde70a19e8e8fa33291e1b9d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9708e7cde70a19e8e8fa33291e1b9d5">CAN_F0R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ec4acee70dd0bad3bcfb650e47f99b5">CAN_F0R2_FB15_Msk</a></td></tr>
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<tr class="separator:gae9708e7cde70a19e8e8fa33291e1b9d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7867b900606b53808ce9dbe518513e55" id="r_ga7867b900606b53808ce9dbe518513e55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7867b900606b53808ce9dbe518513e55">CAN_F0R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga7867b900606b53808ce9dbe518513e55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae046a3f26c0161e3c40dc1bc568db3b" id="r_gaae046a3f26c0161e3c40dc1bc568db3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae046a3f26c0161e3c40dc1bc568db3b">CAN_F0R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7867b900606b53808ce9dbe518513e55">CAN_F0R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:gaae046a3f26c0161e3c40dc1bc568db3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2f2154c3030cebcfc3f1e4aed74fbf1" id="r_gab2f2154c3030cebcfc3f1e4aed74fbf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2f2154c3030cebcfc3f1e4aed74fbf1">CAN_F0R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae046a3f26c0161e3c40dc1bc568db3b">CAN_F0R2_FB16_Msk</a></td></tr>
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<tr class="separator:gab2f2154c3030cebcfc3f1e4aed74fbf1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f2272ba668cd632f30d77814bc8e465" id="r_ga7f2272ba668cd632f30d77814bc8e465"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f2272ba668cd632f30d77814bc8e465">CAN_F0R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga7f2272ba668cd632f30d77814bc8e465"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06f28b2b9fdaaba93dd8268b5567a8ad" id="r_ga06f28b2b9fdaaba93dd8268b5567a8ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06f28b2b9fdaaba93dd8268b5567a8ad">CAN_F0R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f2272ba668cd632f30d77814bc8e465">CAN_F0R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga06f28b2b9fdaaba93dd8268b5567a8ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae87c14b75911aa0a9d0349d02d342711" id="r_gae87c14b75911aa0a9d0349d02d342711"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae87c14b75911aa0a9d0349d02d342711">CAN_F0R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06f28b2b9fdaaba93dd8268b5567a8ad">CAN_F0R2_FB17_Msk</a></td></tr>
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<tr class="separator:gae87c14b75911aa0a9d0349d02d342711"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad72df4766cb512aa607194c64484d9fb" id="r_gad72df4766cb512aa607194c64484d9fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad72df4766cb512aa607194c64484d9fb">CAN_F0R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga134eae58ad5e99cc09201e3f806390b2" id="r_ga134eae58ad5e99cc09201e3f806390b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga134eae58ad5e99cc09201e3f806390b2">CAN_F0R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad72df4766cb512aa607194c64484d9fb">CAN_F0R2_FB18_Pos</a>)</td></tr>
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<tr class="memitem:ga6fd7859cfc05300f68b175f520ddc31e" id="r_ga6fd7859cfc05300f68b175f520ddc31e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fd7859cfc05300f68b175f520ddc31e">CAN_F0R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga134eae58ad5e99cc09201e3f806390b2">CAN_F0R2_FB18_Msk</a></td></tr>
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<tr class="memitem:ga935ebc3c9dd606d36290e38c265ef7dc" id="r_ga935ebc3c9dd606d36290e38c265ef7dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga935ebc3c9dd606d36290e38c265ef7dc">CAN_F0R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="memitem:ga2288da969d823cf883f0a11d0e66db51" id="r_ga2288da969d823cf883f0a11d0e66db51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2288da969d823cf883f0a11d0e66db51">CAN_F0R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga935ebc3c9dd606d36290e38c265ef7dc">CAN_F0R2_FB19_Pos</a>)</td></tr>
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<tr class="memitem:gaaea36db8fcada46357137efeea256457" id="r_gaaea36db8fcada46357137efeea256457"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaea36db8fcada46357137efeea256457">CAN_F0R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2288da969d823cf883f0a11d0e66db51">CAN_F0R2_FB19_Msk</a></td></tr>
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<tr class="memitem:ga392416946fa28a09ba37f510aa39ee2f" id="r_ga392416946fa28a09ba37f510aa39ee2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga392416946fa28a09ba37f510aa39ee2f">CAN_F0R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga5e695a429859e9c143330c5cf6ad3229" id="r_ga5e695a429859e9c143330c5cf6ad3229"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e695a429859e9c143330c5cf6ad3229">CAN_F0R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga392416946fa28a09ba37f510aa39ee2f">CAN_F0R2_FB20_Pos</a>)</td></tr>
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<tr class="memitem:ga57872dcfea1f8a56170640842edf9c1a" id="r_ga57872dcfea1f8a56170640842edf9c1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57872dcfea1f8a56170640842edf9c1a">CAN_F0R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e695a429859e9c143330c5cf6ad3229">CAN_F0R2_FB20_Msk</a></td></tr>
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<tr class="memitem:gac77ccf85d70f580674fcce170c086071" id="r_gac77ccf85d70f580674fcce170c086071"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac77ccf85d70f580674fcce170c086071">CAN_F0R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="memitem:ga9b4a66ffe52286fd25f6bb36fa2e6f21" id="r_ga9b4a66ffe52286fd25f6bb36fa2e6f21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b4a66ffe52286fd25f6bb36fa2e6f21">CAN_F0R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac77ccf85d70f580674fcce170c086071">CAN_F0R2_FB21_Pos</a>)</td></tr>
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<tr class="memitem:gacc01e7f26d0e85da93ca78d0d71a4fed" id="r_gacc01e7f26d0e85da93ca78d0d71a4fed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc01e7f26d0e85da93ca78d0d71a4fed">CAN_F0R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b4a66ffe52286fd25f6bb36fa2e6f21">CAN_F0R2_FB21_Msk</a></td></tr>
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<tr class="memitem:ga7de0dedff4a0a111022b7f750c52d8a9" id="r_ga7de0dedff4a0a111022b7f750c52d8a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7de0dedff4a0a111022b7f750c52d8a9">CAN_F0R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="memitem:ga6d02ac9f9a07b7c47059c84a2b0782ee" id="r_ga6d02ac9f9a07b7c47059c84a2b0782ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d02ac9f9a07b7c47059c84a2b0782ee">CAN_F0R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7de0dedff4a0a111022b7f750c52d8a9">CAN_F0R2_FB22_Pos</a>)</td></tr>
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<tr class="memitem:ga07d8c3c8c3eb3c97b5979388c548e2fc" id="r_ga07d8c3c8c3eb3c97b5979388c548e2fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07d8c3c8c3eb3c97b5979388c548e2fc">CAN_F0R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d02ac9f9a07b7c47059c84a2b0782ee">CAN_F0R2_FB22_Msk</a></td></tr>
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<tr class="memitem:ga46768113fa95f91e263d6a4b62cffdd3" id="r_ga46768113fa95f91e263d6a4b62cffdd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46768113fa95f91e263d6a4b62cffdd3">CAN_F0R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga46768113fa95f91e263d6a4b62cffdd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cd190536d4b825b086f682b40886f7f" id="r_ga8cd190536d4b825b086f682b40886f7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cd190536d4b825b086f682b40886f7f">CAN_F0R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46768113fa95f91e263d6a4b62cffdd3">CAN_F0R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga8cd190536d4b825b086f682b40886f7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade31bd75624afeaef9b5ab45a5057db9" id="r_gade31bd75624afeaef9b5ab45a5057db9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade31bd75624afeaef9b5ab45a5057db9">CAN_F0R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8cd190536d4b825b086f682b40886f7f">CAN_F0R2_FB23_Msk</a></td></tr>
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<tr class="memitem:ga8c235ae356a2cce22c4c3a46099e3395" id="r_ga8c235ae356a2cce22c4c3a46099e3395"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c235ae356a2cce22c4c3a46099e3395">CAN_F0R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga8c235ae356a2cce22c4c3a46099e3395"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49d6929299df0a13244f0e7958eb711a" id="r_ga49d6929299df0a13244f0e7958eb711a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49d6929299df0a13244f0e7958eb711a">CAN_F0R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c235ae356a2cce22c4c3a46099e3395">CAN_F0R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga49d6929299df0a13244f0e7958eb711a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa78ff8fcfe0f14655aaf94ecc92d7532" id="r_gaa78ff8fcfe0f14655aaf94ecc92d7532"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa78ff8fcfe0f14655aaf94ecc92d7532">CAN_F0R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga49d6929299df0a13244f0e7958eb711a">CAN_F0R2_FB24_Msk</a></td></tr>
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<tr class="separator:gaa78ff8fcfe0f14655aaf94ecc92d7532"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc439d9206a0fe829811ba950c98cbb7" id="r_gafc439d9206a0fe829811ba950c98cbb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc439d9206a0fe829811ba950c98cbb7">CAN_F0R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gafc439d9206a0fe829811ba950c98cbb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf6e6acb5b23357732909d4bec0eb95e" id="r_gaaf6e6acb5b23357732909d4bec0eb95e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf6e6acb5b23357732909d4bec0eb95e">CAN_F0R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafc439d9206a0fe829811ba950c98cbb7">CAN_F0R2_FB25_Pos</a>)</td></tr>
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<tr class="memitem:gaad577ebd9a8cedd1b8b13d5a41d2fbab" id="r_gaad577ebd9a8cedd1b8b13d5a41d2fbab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad577ebd9a8cedd1b8b13d5a41d2fbab">CAN_F0R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf6e6acb5b23357732909d4bec0eb95e">CAN_F0R2_FB25_Msk</a></td></tr>
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<tr class="memitem:ga3102f1fa9437f6fcd9fa4a51074a837d" id="r_ga3102f1fa9437f6fcd9fa4a51074a837d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3102f1fa9437f6fcd9fa4a51074a837d">CAN_F0R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga3102f1fa9437f6fcd9fa4a51074a837d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0c77950c4ec1c45ab5c4c2936186d36" id="r_gab0c77950c4ec1c45ab5c4c2936186d36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0c77950c4ec1c45ab5c4c2936186d36">CAN_F0R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3102f1fa9437f6fcd9fa4a51074a837d">CAN_F0R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:gab0c77950c4ec1c45ab5c4c2936186d36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab814105bcd2a2c636c26197b21ead2b0" id="r_gab814105bcd2a2c636c26197b21ead2b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab814105bcd2a2c636c26197b21ead2b0">CAN_F0R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab0c77950c4ec1c45ab5c4c2936186d36">CAN_F0R2_FB26_Msk</a></td></tr>
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<tr class="separator:gab814105bcd2a2c636c26197b21ead2b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf09a3ca077d2274a12ecbf0f8d0aab6" id="r_gacf09a3ca077d2274a12ecbf0f8d0aab6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf09a3ca077d2274a12ecbf0f8d0aab6">CAN_F0R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:gacf09a3ca077d2274a12ecbf0f8d0aab6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47a37ea3a0bc9d4232ee89f18782ff53" id="r_ga47a37ea3a0bc9d4232ee89f18782ff53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47a37ea3a0bc9d4232ee89f18782ff53">CAN_F0R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf09a3ca077d2274a12ecbf0f8d0aab6">CAN_F0R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga47a37ea3a0bc9d4232ee89f18782ff53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea82daeaa71ecddb187613df9517e51c" id="r_gaea82daeaa71ecddb187613df9517e51c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea82daeaa71ecddb187613df9517e51c">CAN_F0R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47a37ea3a0bc9d4232ee89f18782ff53">CAN_F0R2_FB27_Msk</a></td></tr>
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<tr class="separator:gaea82daeaa71ecddb187613df9517e51c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90c21de25c1da4b3a3c5715e6212c1e9" id="r_ga90c21de25c1da4b3a3c5715e6212c1e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90c21de25c1da4b3a3c5715e6212c1e9">CAN_F0R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga90c21de25c1da4b3a3c5715e6212c1e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadfb99d019f1abf788685338176fa8595" id="r_gadfb99d019f1abf788685338176fa8595"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfb99d019f1abf788685338176fa8595">CAN_F0R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga90c21de25c1da4b3a3c5715e6212c1e9">CAN_F0R2_FB28_Pos</a>)</td></tr>
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<tr class="memitem:gaef5036edf5bd310e5e06f3ea5cb818a2" id="r_gaef5036edf5bd310e5e06f3ea5cb818a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef5036edf5bd310e5e06f3ea5cb818a2">CAN_F0R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadfb99d019f1abf788685338176fa8595">CAN_F0R2_FB28_Msk</a></td></tr>
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<tr class="memitem:ga168f5225f2ca892513f4d58e7c348c58" id="r_ga168f5225f2ca892513f4d58e7c348c58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga168f5225f2ca892513f4d58e7c348c58">CAN_F0R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga168f5225f2ca892513f4d58e7c348c58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga875a0587956149206e0df84242e5c38a" id="r_ga875a0587956149206e0df84242e5c38a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga875a0587956149206e0df84242e5c38a">CAN_F0R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga168f5225f2ca892513f4d58e7c348c58">CAN_F0R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:ga875a0587956149206e0df84242e5c38a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0c2db96ddbcfa1b838c283e20ca554b" id="r_gaa0c2db96ddbcfa1b838c283e20ca554b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0c2db96ddbcfa1b838c283e20ca554b">CAN_F0R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga875a0587956149206e0df84242e5c38a">CAN_F0R2_FB29_Msk</a></td></tr>
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<tr class="separator:gaa0c2db96ddbcfa1b838c283e20ca554b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac273be775b429ef41f46885be62c040d" id="r_gac273be775b429ef41f46885be62c040d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac273be775b429ef41f46885be62c040d">CAN_F0R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:gac273be775b429ef41f46885be62c040d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ee59bc46345bde430c9ecf20c8df7a2" id="r_ga4ee59bc46345bde430c9ecf20c8df7a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ee59bc46345bde430c9ecf20c8df7a2">CAN_F0R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac273be775b429ef41f46885be62c040d">CAN_F0R2_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga4ee59bc46345bde430c9ecf20c8df7a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5afb46a2d4ccb3f28e8579b26e2b2e2e" id="r_ga5afb46a2d4ccb3f28e8579b26e2b2e2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5afb46a2d4ccb3f28e8579b26e2b2e2e">CAN_F0R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ee59bc46345bde430c9ecf20c8df7a2">CAN_F0R2_FB30_Msk</a></td></tr>
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<tr class="separator:ga5afb46a2d4ccb3f28e8579b26e2b2e2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa39384b9da02ee18353528a10b08920" id="r_gafa39384b9da02ee18353528a10b08920"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa39384b9da02ee18353528a10b08920">CAN_F0R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:gafa39384b9da02ee18353528a10b08920"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90f146c0436009e8b77597db4f06dc88" id="r_ga90f146c0436009e8b77597db4f06dc88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90f146c0436009e8b77597db4f06dc88">CAN_F0R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafa39384b9da02ee18353528a10b08920">CAN_F0R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga90f146c0436009e8b77597db4f06dc88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ace83e798931f35c123507e1ef59fbb" id="r_ga1ace83e798931f35c123507e1ef59fbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ace83e798931f35c123507e1ef59fbb">CAN_F0R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga90f146c0436009e8b77597db4f06dc88">CAN_F0R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga1ace83e798931f35c123507e1ef59fbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0dec2c89cd678f3fd1fa90ba991c77c8" id="r_ga0dec2c89cd678f3fd1fa90ba991c77c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dec2c89cd678f3fd1fa90ba991c77c8">CAN_F1R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0dec2c89cd678f3fd1fa90ba991c77c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac37390e12fa87a072599d57c581f82b1" id="r_gac37390e12fa87a072599d57c581f82b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac37390e12fa87a072599d57c581f82b1">CAN_F1R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dec2c89cd678f3fd1fa90ba991c77c8">CAN_F1R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:gac37390e12fa87a072599d57c581f82b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ea3c5d8ab8962d9cd0e2b067167d3d4" id="r_ga7ea3c5d8ab8962d9cd0e2b067167d3d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ea3c5d8ab8962d9cd0e2b067167d3d4">CAN_F1R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac37390e12fa87a072599d57c581f82b1">CAN_F1R2_FB0_Msk</a></td></tr>
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<tr class="separator:ga7ea3c5d8ab8962d9cd0e2b067167d3d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6841efe21767654ecaee1bb96755970" id="r_gaa6841efe21767654ecaee1bb96755970"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6841efe21767654ecaee1bb96755970">CAN_F1R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaa6841efe21767654ecaee1bb96755970"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f4652769a8b81aefaa5acbaddc83e47" id="r_ga4f4652769a8b81aefaa5acbaddc83e47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f4652769a8b81aefaa5acbaddc83e47">CAN_F1R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6841efe21767654ecaee1bb96755970">CAN_F1R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga4f4652769a8b81aefaa5acbaddc83e47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfa5449488e7330d8f11f75fcf3e75cd" id="r_gacfa5449488e7330d8f11f75fcf3e75cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfa5449488e7330d8f11f75fcf3e75cd">CAN_F1R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f4652769a8b81aefaa5acbaddc83e47">CAN_F1R2_FB1_Msk</a></td></tr>
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<tr class="separator:gacfa5449488e7330d8f11f75fcf3e75cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga622010c50665f9ae395641902d1834d4" id="r_ga622010c50665f9ae395641902d1834d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga622010c50665f9ae395641902d1834d4">CAN_F1R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga622010c50665f9ae395641902d1834d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga550988821dc17b71e58d745367d552fb" id="r_ga550988821dc17b71e58d745367d552fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga550988821dc17b71e58d745367d552fb">CAN_F1R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga622010c50665f9ae395641902d1834d4">CAN_F1R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga550988821dc17b71e58d745367d552fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe49a3e224459f1bd9b3279ebfa8803b" id="r_gafe49a3e224459f1bd9b3279ebfa8803b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe49a3e224459f1bd9b3279ebfa8803b">CAN_F1R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga550988821dc17b71e58d745367d552fb">CAN_F1R2_FB2_Msk</a></td></tr>
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<tr class="separator:gafe49a3e224459f1bd9b3279ebfa8803b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24e392fb487c7c70667c53e868bd8ec7" id="r_ga24e392fb487c7c70667c53e868bd8ec7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24e392fb487c7c70667c53e868bd8ec7">CAN_F1R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga24e392fb487c7c70667c53e868bd8ec7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad52c7978074227730285d698cdcb15c7" id="r_gad52c7978074227730285d698cdcb15c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad52c7978074227730285d698cdcb15c7">CAN_F1R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24e392fb487c7c70667c53e868bd8ec7">CAN_F1R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:gad52c7978074227730285d698cdcb15c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77cf2217ec29e2043bada827249dedd5" id="r_ga77cf2217ec29e2043bada827249dedd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77cf2217ec29e2043bada827249dedd5">CAN_F1R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad52c7978074227730285d698cdcb15c7">CAN_F1R2_FB3_Msk</a></td></tr>
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<tr class="separator:ga77cf2217ec29e2043bada827249dedd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga937b036cc35761691dae4719da547038" id="r_ga937b036cc35761691dae4719da547038"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga937b036cc35761691dae4719da547038">CAN_F1R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga937b036cc35761691dae4719da547038"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab404d9e8cd80526beb5b83ea62236c40" id="r_gab404d9e8cd80526beb5b83ea62236c40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab404d9e8cd80526beb5b83ea62236c40">CAN_F1R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga937b036cc35761691dae4719da547038">CAN_F1R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:gab404d9e8cd80526beb5b83ea62236c40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf35643f0148ed0f93e3ba52e95a4cf6b" id="r_gaf35643f0148ed0f93e3ba52e95a4cf6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf35643f0148ed0f93e3ba52e95a4cf6b">CAN_F1R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab404d9e8cd80526beb5b83ea62236c40">CAN_F1R2_FB4_Msk</a></td></tr>
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<tr class="separator:gaf35643f0148ed0f93e3ba52e95a4cf6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9021382fb04157c3a4ea991a1a0d654" id="r_gaf9021382fb04157c3a4ea991a1a0d654"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9021382fb04157c3a4ea991a1a0d654">CAN_F1R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaf9021382fb04157c3a4ea991a1a0d654"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3210b70ca25333f077035c8178683b3c" id="r_ga3210b70ca25333f077035c8178683b3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3210b70ca25333f077035c8178683b3c">CAN_F1R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9021382fb04157c3a4ea991a1a0d654">CAN_F1R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga3210b70ca25333f077035c8178683b3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae08798adabd9cc0fb2b07eaff6444878" id="r_gae08798adabd9cc0fb2b07eaff6444878"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae08798adabd9cc0fb2b07eaff6444878">CAN_F1R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3210b70ca25333f077035c8178683b3c">CAN_F1R2_FB5_Msk</a></td></tr>
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<tr class="separator:gae08798adabd9cc0fb2b07eaff6444878"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga282ffe71282dcacb6bd4a49da646a7ae" id="r_ga282ffe71282dcacb6bd4a49da646a7ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga282ffe71282dcacb6bd4a49da646a7ae">CAN_F1R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga282ffe71282dcacb6bd4a49da646a7ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab840206e4408eeadf35ca5ce492121b7" id="r_gab840206e4408eeadf35ca5ce492121b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab840206e4408eeadf35ca5ce492121b7">CAN_F1R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga282ffe71282dcacb6bd4a49da646a7ae">CAN_F1R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:gab840206e4408eeadf35ca5ce492121b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06659c9a418d7f4a8729d87bc397be23" id="r_ga06659c9a418d7f4a8729d87bc397be23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06659c9a418d7f4a8729d87bc397be23">CAN_F1R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab840206e4408eeadf35ca5ce492121b7">CAN_F1R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga06659c9a418d7f4a8729d87bc397be23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34ffa785ed1b4ab61dfcb4e5d203ec57" id="r_ga34ffa785ed1b4ab61dfcb4e5d203ec57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34ffa785ed1b4ab61dfcb4e5d203ec57">CAN_F1R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga34ffa785ed1b4ab61dfcb4e5d203ec57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93f9f5471e1a8abd2ca55fe5a4cf120f" id="r_ga93f9f5471e1a8abd2ca55fe5a4cf120f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93f9f5471e1a8abd2ca55fe5a4cf120f">CAN_F1R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34ffa785ed1b4ab61dfcb4e5d203ec57">CAN_F1R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga93f9f5471e1a8abd2ca55fe5a4cf120f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36bb9ca8dadd6714052f8d31cb01cb7b" id="r_ga36bb9ca8dadd6714052f8d31cb01cb7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36bb9ca8dadd6714052f8d31cb01cb7b">CAN_F1R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga93f9f5471e1a8abd2ca55fe5a4cf120f">CAN_F1R2_FB7_Msk</a></td></tr>
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<tr class="separator:ga36bb9ca8dadd6714052f8d31cb01cb7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83f47b48b80736f5526b826a9150e32a" id="r_ga83f47b48b80736f5526b826a9150e32a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83f47b48b80736f5526b826a9150e32a">CAN_F1R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga83f47b48b80736f5526b826a9150e32a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade520b46b08abd462743828dfdb211e1" id="r_gade520b46b08abd462743828dfdb211e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade520b46b08abd462743828dfdb211e1">CAN_F1R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83f47b48b80736f5526b826a9150e32a">CAN_F1R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:gade520b46b08abd462743828dfdb211e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d400044261146be3deb722d9cf3d5c1" id="r_ga2d400044261146be3deb722d9cf3d5c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d400044261146be3deb722d9cf3d5c1">CAN_F1R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gade520b46b08abd462743828dfdb211e1">CAN_F1R2_FB8_Msk</a></td></tr>
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<tr class="separator:ga2d400044261146be3deb722d9cf3d5c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5018a74c3736b3246b93e642100f1d9" id="r_gad5018a74c3736b3246b93e642100f1d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5018a74c3736b3246b93e642100f1d9">CAN_F1R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gad5018a74c3736b3246b93e642100f1d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28e355feec329b328d200ea79a3c4e73" id="r_ga28e355feec329b328d200ea79a3c4e73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28e355feec329b328d200ea79a3c4e73">CAN_F1R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad5018a74c3736b3246b93e642100f1d9">CAN_F1R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga28e355feec329b328d200ea79a3c4e73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3e5769ea8faaed16c6cb2ce979d28a9" id="r_gab3e5769ea8faaed16c6cb2ce979d28a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3e5769ea8faaed16c6cb2ce979d28a9">CAN_F1R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga28e355feec329b328d200ea79a3c4e73">CAN_F1R2_FB9_Msk</a></td></tr>
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<tr class="separator:gab3e5769ea8faaed16c6cb2ce979d28a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4282afc9cf64def8be2dfe7cab903113" id="r_ga4282afc9cf64def8be2dfe7cab903113"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4282afc9cf64def8be2dfe7cab903113">CAN_F1R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga4282afc9cf64def8be2dfe7cab903113"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4fa9a6d11d4066ce8cbed7772e5c4c1" id="r_gac4fa9a6d11d4066ce8cbed7772e5c4c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4fa9a6d11d4066ce8cbed7772e5c4c1">CAN_F1R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4282afc9cf64def8be2dfe7cab903113">CAN_F1R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:gac4fa9a6d11d4066ce8cbed7772e5c4c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga915236a6b5081c2c30bd4d49144bc463" id="r_ga915236a6b5081c2c30bd4d49144bc463"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga915236a6b5081c2c30bd4d49144bc463">CAN_F1R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fa9a6d11d4066ce8cbed7772e5c4c1">CAN_F1R2_FB10_Msk</a></td></tr>
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<tr class="separator:ga915236a6b5081c2c30bd4d49144bc463"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga796f12ffae3a26f7e0211f55db51da75" id="r_ga796f12ffae3a26f7e0211f55db51da75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga796f12ffae3a26f7e0211f55db51da75">CAN_F1R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga796f12ffae3a26f7e0211f55db51da75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1aef88c920add1bcec693ba43f890cf" id="r_gaa1aef88c920add1bcec693ba43f890cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1aef88c920add1bcec693ba43f890cf">CAN_F1R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga796f12ffae3a26f7e0211f55db51da75">CAN_F1R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:gaa1aef88c920add1bcec693ba43f890cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf1aa2e62d4eede199196f81795d309c" id="r_gabf1aa2e62d4eede199196f81795d309c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf1aa2e62d4eede199196f81795d309c">CAN_F1R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1aef88c920add1bcec693ba43f890cf">CAN_F1R2_FB11_Msk</a></td></tr>
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<tr class="separator:gabf1aa2e62d4eede199196f81795d309c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4000100330d542f8d6375d4ccd450d6d" id="r_ga4000100330d542f8d6375d4ccd450d6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4000100330d542f8d6375d4ccd450d6d">CAN_F1R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga4000100330d542f8d6375d4ccd450d6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4486004019a70c1c41822611cfbc24a7" id="r_ga4486004019a70c1c41822611cfbc24a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4486004019a70c1c41822611cfbc24a7">CAN_F1R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4000100330d542f8d6375d4ccd450d6d">CAN_F1R2_FB12_Pos</a>)</td></tr>
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<tr class="separator:ga4486004019a70c1c41822611cfbc24a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7db0ae3dcaab35e4c496c8a800b5c994" id="r_ga7db0ae3dcaab35e4c496c8a800b5c994"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7db0ae3dcaab35e4c496c8a800b5c994">CAN_F1R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4486004019a70c1c41822611cfbc24a7">CAN_F1R2_FB12_Msk</a></td></tr>
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<tr class="separator:ga7db0ae3dcaab35e4c496c8a800b5c994"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadc9998290934d01441ce5d05b335868" id="r_gaadc9998290934d01441ce5d05b335868"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadc9998290934d01441ce5d05b335868">CAN_F1R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaadc9998290934d01441ce5d05b335868"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32ef2954ebc503eaf6c44eb4ec9a593e" id="r_ga32ef2954ebc503eaf6c44eb4ec9a593e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32ef2954ebc503eaf6c44eb4ec9a593e">CAN_F1R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaadc9998290934d01441ce5d05b335868">CAN_F1R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga32ef2954ebc503eaf6c44eb4ec9a593e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02cdb71c56a5d9994ecd2dee668c7184" id="r_ga02cdb71c56a5d9994ecd2dee668c7184"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02cdb71c56a5d9994ecd2dee668c7184">CAN_F1R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga32ef2954ebc503eaf6c44eb4ec9a593e">CAN_F1R2_FB13_Msk</a></td></tr>
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<tr class="separator:ga02cdb71c56a5d9994ecd2dee668c7184"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga412671533d237ac1b2abce675e53e41e" id="r_ga412671533d237ac1b2abce675e53e41e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga412671533d237ac1b2abce675e53e41e">CAN_F1R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga412671533d237ac1b2abce675e53e41e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace28daab139f94dc2ed7e388fd1b9b59" id="r_gace28daab139f94dc2ed7e388fd1b9b59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace28daab139f94dc2ed7e388fd1b9b59">CAN_F1R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga412671533d237ac1b2abce675e53e41e">CAN_F1R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:gace28daab139f94dc2ed7e388fd1b9b59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac66691ca840db6c861460d311a942a87" id="r_gac66691ca840db6c861460d311a942a87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac66691ca840db6c861460d311a942a87">CAN_F1R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gace28daab139f94dc2ed7e388fd1b9b59">CAN_F1R2_FB14_Msk</a></td></tr>
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<tr class="separator:gac66691ca840db6c861460d311a942a87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2face19f24a4459fc7aff4ca49fcb300" id="r_ga2face19f24a4459fc7aff4ca49fcb300"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2face19f24a4459fc7aff4ca49fcb300">CAN_F1R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga2face19f24a4459fc7aff4ca49fcb300"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbb0a0b5dd87d593fc1cf8b9269bf365" id="r_gadbb0a0b5dd87d593fc1cf8b9269bf365"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbb0a0b5dd87d593fc1cf8b9269bf365">CAN_F1R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2face19f24a4459fc7aff4ca49fcb300">CAN_F1R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:gadbb0a0b5dd87d593fc1cf8b9269bf365"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabcdd57022e26859db1f81f2df08c8725" id="r_gabcdd57022e26859db1f81f2df08c8725"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabcdd57022e26859db1f81f2df08c8725">CAN_F1R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadbb0a0b5dd87d593fc1cf8b9269bf365">CAN_F1R2_FB15_Msk</a></td></tr>
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<tr class="separator:gabcdd57022e26859db1f81f2df08c8725"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4e63a8d7f11fab2b9970eb9402164a1" id="r_gaf4e63a8d7f11fab2b9970eb9402164a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4e63a8d7f11fab2b9970eb9402164a1">CAN_F1R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaf4e63a8d7f11fab2b9970eb9402164a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga427c05edd87c70fb5bfede3ece583106" id="r_ga427c05edd87c70fb5bfede3ece583106"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga427c05edd87c70fb5bfede3ece583106">CAN_F1R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4e63a8d7f11fab2b9970eb9402164a1">CAN_F1R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga427c05edd87c70fb5bfede3ece583106"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga211795b36769a0b87044f0d82a7a72b1" id="r_ga211795b36769a0b87044f0d82a7a72b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga211795b36769a0b87044f0d82a7a72b1">CAN_F1R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga427c05edd87c70fb5bfede3ece583106">CAN_F1R2_FB16_Msk</a></td></tr>
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<tr class="separator:ga211795b36769a0b87044f0d82a7a72b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5972a3d5d5b18772e834e3f56e6d3b1" id="r_gac5972a3d5d5b18772e834e3f56e6d3b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5972a3d5d5b18772e834e3f56e6d3b1">CAN_F1R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gac5972a3d5d5b18772e834e3f56e6d3b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e7423c9dd0740125ba2dc7a9068c449" id="r_ga4e7423c9dd0740125ba2dc7a9068c449"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e7423c9dd0740125ba2dc7a9068c449">CAN_F1R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac5972a3d5d5b18772e834e3f56e6d3b1">CAN_F1R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga4e7423c9dd0740125ba2dc7a9068c449"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc8c427731f33c76fad0873bb29a4b4c" id="r_gabc8c427731f33c76fad0873bb29a4b4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc8c427731f33c76fad0873bb29a4b4c">CAN_F1R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e7423c9dd0740125ba2dc7a9068c449">CAN_F1R2_FB17_Msk</a></td></tr>
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<tr class="separator:gabc8c427731f33c76fad0873bb29a4b4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5916963935ba1112457ff7f497a3105" id="r_gab5916963935ba1112457ff7f497a3105"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5916963935ba1112457ff7f497a3105">CAN_F1R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:gab5916963935ba1112457ff7f497a3105"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcea3b8cd42bcc687c67e62a0ccf7471" id="r_gadcea3b8cd42bcc687c67e62a0ccf7471"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcea3b8cd42bcc687c67e62a0ccf7471">CAN_F1R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5916963935ba1112457ff7f497a3105">CAN_F1R2_FB18_Pos</a>)</td></tr>
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<tr class="memitem:ga10a3e6be9968b8007562e7afe6b3b342" id="r_ga10a3e6be9968b8007562e7afe6b3b342"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10a3e6be9968b8007562e7afe6b3b342">CAN_F1R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadcea3b8cd42bcc687c67e62a0ccf7471">CAN_F1R2_FB18_Msk</a></td></tr>
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<tr class="separator:ga10a3e6be9968b8007562e7afe6b3b342"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga925a99e3a206a826cc1abf0bd4adb42f" id="r_ga925a99e3a206a826cc1abf0bd4adb42f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga925a99e3a206a826cc1abf0bd4adb42f">CAN_F1R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga925a99e3a206a826cc1abf0bd4adb42f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3e119637508ebc998e04873befdea02" id="r_gae3e119637508ebc998e04873befdea02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3e119637508ebc998e04873befdea02">CAN_F1R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga925a99e3a206a826cc1abf0bd4adb42f">CAN_F1R2_FB19_Pos</a>)</td></tr>
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<tr class="memitem:ga4aac6ab4bd4cdeecbe621adf1d11b95a" id="r_ga4aac6ab4bd4cdeecbe621adf1d11b95a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4aac6ab4bd4cdeecbe621adf1d11b95a">CAN_F1R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3e119637508ebc998e04873befdea02">CAN_F1R2_FB19_Msk</a></td></tr>
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<tr class="separator:ga4aac6ab4bd4cdeecbe621adf1d11b95a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fe55799241f27062746e57409e2e9f4" id="r_ga9fe55799241f27062746e57409e2e9f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fe55799241f27062746e57409e2e9f4">CAN_F1R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga9fe55799241f27062746e57409e2e9f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6adb312018dfbe719072be0d6444b62a" id="r_ga6adb312018dfbe719072be0d6444b62a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6adb312018dfbe719072be0d6444b62a">CAN_F1R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9fe55799241f27062746e57409e2e9f4">CAN_F1R2_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga6adb312018dfbe719072be0d6444b62a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30140ced3da0d0a526c4f4f5881987c1" id="r_ga30140ced3da0d0a526c4f4f5881987c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30140ced3da0d0a526c4f4f5881987c1">CAN_F1R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6adb312018dfbe719072be0d6444b62a">CAN_F1R2_FB20_Msk</a></td></tr>
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<tr class="separator:ga30140ced3da0d0a526c4f4f5881987c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfa97c392ee8e456dd9ffd6498590c11" id="r_gacfa97c392ee8e456dd9ffd6498590c11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfa97c392ee8e456dd9ffd6498590c11">CAN_F1R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gacfa97c392ee8e456dd9ffd6498590c11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23a75816e8e01c5c9a90d7b2afa4716f" id="r_ga23a75816e8e01c5c9a90d7b2afa4716f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23a75816e8e01c5c9a90d7b2afa4716f">CAN_F1R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacfa97c392ee8e456dd9ffd6498590c11">CAN_F1R2_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga23a75816e8e01c5c9a90d7b2afa4716f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49f36aec2e851ed18c5a382a0708bbcb" id="r_ga49f36aec2e851ed18c5a382a0708bbcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49f36aec2e851ed18c5a382a0708bbcb">CAN_F1R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga23a75816e8e01c5c9a90d7b2afa4716f">CAN_F1R2_FB21_Msk</a></td></tr>
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<tr class="separator:ga49f36aec2e851ed18c5a382a0708bbcb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga948b363bcf4905731e758e1353c58bde" id="r_ga948b363bcf4905731e758e1353c58bde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga948b363bcf4905731e758e1353c58bde">CAN_F1R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga948b363bcf4905731e758e1353c58bde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace263ed2b1dcb26232c8be718c733490" id="r_gace263ed2b1dcb26232c8be718c733490"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace263ed2b1dcb26232c8be718c733490">CAN_F1R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga948b363bcf4905731e758e1353c58bde">CAN_F1R2_FB22_Pos</a>)</td></tr>
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<tr class="separator:gace263ed2b1dcb26232c8be718c733490"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99ccab06a8a97616a2fc3e026f36351d" id="r_ga99ccab06a8a97616a2fc3e026f36351d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99ccab06a8a97616a2fc3e026f36351d">CAN_F1R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gace263ed2b1dcb26232c8be718c733490">CAN_F1R2_FB22_Msk</a></td></tr>
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<tr class="separator:ga99ccab06a8a97616a2fc3e026f36351d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga166035cac78d72360b8019ede0ec3bf7" id="r_ga166035cac78d72360b8019ede0ec3bf7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga166035cac78d72360b8019ede0ec3bf7">CAN_F1R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga166035cac78d72360b8019ede0ec3bf7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15089c114f7120bd834ecddd74795989" id="r_ga15089c114f7120bd834ecddd74795989"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15089c114f7120bd834ecddd74795989">CAN_F1R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga166035cac78d72360b8019ede0ec3bf7">CAN_F1R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga15089c114f7120bd834ecddd74795989"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa408889ff6478d6558d4c53c9114bde" id="r_gaaa408889ff6478d6558d4c53c9114bde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa408889ff6478d6558d4c53c9114bde">CAN_F1R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga15089c114f7120bd834ecddd74795989">CAN_F1R2_FB23_Msk</a></td></tr>
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<tr class="separator:gaaa408889ff6478d6558d4c53c9114bde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b63bc70f339f5773288cb786e9c4459" id="r_ga6b63bc70f339f5773288cb786e9c4459"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b63bc70f339f5773288cb786e9c4459">CAN_F1R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga6b63bc70f339f5773288cb786e9c4459"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga256936e5e1dc313a5846bcdb38746940" id="r_ga256936e5e1dc313a5846bcdb38746940"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga256936e5e1dc313a5846bcdb38746940">CAN_F1R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b63bc70f339f5773288cb786e9c4459">CAN_F1R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga256936e5e1dc313a5846bcdb38746940"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga032dd8dc11aa9013cc0e824e31932951" id="r_ga032dd8dc11aa9013cc0e824e31932951"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga032dd8dc11aa9013cc0e824e31932951">CAN_F1R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga256936e5e1dc313a5846bcdb38746940">CAN_F1R2_FB24_Msk</a></td></tr>
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<tr class="separator:ga032dd8dc11aa9013cc0e824e31932951"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5bd608220a283001eb3e0739c4b9971" id="r_gab5bd608220a283001eb3e0739c4b9971"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5bd608220a283001eb3e0739c4b9971">CAN_F1R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gab5bd608220a283001eb3e0739c4b9971"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8861d429f3e5a4cf24015dd24d1035a2" id="r_ga8861d429f3e5a4cf24015dd24d1035a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8861d429f3e5a4cf24015dd24d1035a2">CAN_F1R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5bd608220a283001eb3e0739c4b9971">CAN_F1R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga8861d429f3e5a4cf24015dd24d1035a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76f29020524ec6403a40de4e260a2ea8" id="r_ga76f29020524ec6403a40de4e260a2ea8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76f29020524ec6403a40de4e260a2ea8">CAN_F1R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8861d429f3e5a4cf24015dd24d1035a2">CAN_F1R2_FB25_Msk</a></td></tr>
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<tr class="separator:ga76f29020524ec6403a40de4e260a2ea8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga244707ad262266c922ff70945babc147" id="r_ga244707ad262266c922ff70945babc147"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga244707ad262266c922ff70945babc147">CAN_F1R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga244707ad262266c922ff70945babc147"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaca03affd919dc4618d7e47f545714fe" id="r_gaaca03affd919dc4618d7e47f545714fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaca03affd919dc4618d7e47f545714fe">CAN_F1R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga244707ad262266c922ff70945babc147">CAN_F1R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:gaaca03affd919dc4618d7e47f545714fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bb51cd27fea671be51a59ce7a83008e" id="r_ga0bb51cd27fea671be51a59ce7a83008e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bb51cd27fea671be51a59ce7a83008e">CAN_F1R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaca03affd919dc4618d7e47f545714fe">CAN_F1R2_FB26_Msk</a></td></tr>
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<tr class="separator:ga0bb51cd27fea671be51a59ce7a83008e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cee8ad67d0accf75e5808747e189153" id="r_ga3cee8ad67d0accf75e5808747e189153"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cee8ad67d0accf75e5808747e189153">CAN_F1R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga3cee8ad67d0accf75e5808747e189153"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4685d281238d461eb78b7f846411f6f3" id="r_ga4685d281238d461eb78b7f846411f6f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4685d281238d461eb78b7f846411f6f3">CAN_F1R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cee8ad67d0accf75e5808747e189153">CAN_F1R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga4685d281238d461eb78b7f846411f6f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga085c38b511aa4895b6c939a06070c916" id="r_ga085c38b511aa4895b6c939a06070c916"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga085c38b511aa4895b6c939a06070c916">CAN_F1R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4685d281238d461eb78b7f846411f6f3">CAN_F1R2_FB27_Msk</a></td></tr>
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<tr class="separator:ga085c38b511aa4895b6c939a06070c916"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28c98f10f41c0d71c4d462d4d12dfa66" id="r_ga28c98f10f41c0d71c4d462d4d12dfa66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28c98f10f41c0d71c4d462d4d12dfa66">CAN_F1R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga28c98f10f41c0d71c4d462d4d12dfa66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a6e9dc7e9d061ce75e04aceae3cfd6b" id="r_ga2a6e9dc7e9d061ce75e04aceae3cfd6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a6e9dc7e9d061ce75e04aceae3cfd6b">CAN_F1R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga28c98f10f41c0d71c4d462d4d12dfa66">CAN_F1R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:ga2a6e9dc7e9d061ce75e04aceae3cfd6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe299378c771da8d7d8e72a6f6e41f7f" id="r_gabe299378c771da8d7d8e72a6f6e41f7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe299378c771da8d7d8e72a6f6e41f7f">CAN_F1R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a6e9dc7e9d061ce75e04aceae3cfd6b">CAN_F1R2_FB28_Msk</a></td></tr>
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<tr class="separator:gabe299378c771da8d7d8e72a6f6e41f7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae336a2f0d44c4ca3a991014f28c2bdff" id="r_gae336a2f0d44c4ca3a991014f28c2bdff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae336a2f0d44c4ca3a991014f28c2bdff">CAN_F1R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:gae336a2f0d44c4ca3a991014f28c2bdff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7fee7c49b899c8af5ae4b60d47461ea2" id="r_ga7fee7c49b899c8af5ae4b60d47461ea2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fee7c49b899c8af5ae4b60d47461ea2">CAN_F1R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae336a2f0d44c4ca3a991014f28c2bdff">CAN_F1R2_FB29_Pos</a>)</td></tr>
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<tr class="memitem:gaabc8bef79b09bcfcb0df6ba467ed906b" id="r_gaabc8bef79b09bcfcb0df6ba467ed906b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabc8bef79b09bcfcb0df6ba467ed906b">CAN_F1R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7fee7c49b899c8af5ae4b60d47461ea2">CAN_F1R2_FB29_Msk</a></td></tr>
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<tr class="memitem:ga461e28c08af3e31dacf1b1cd7b8ffcc4" id="r_ga461e28c08af3e31dacf1b1cd7b8ffcc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga461e28c08af3e31dacf1b1cd7b8ffcc4">CAN_F1R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="memitem:gab87ec718cd11264085752c85b44e6ef3" id="r_gab87ec718cd11264085752c85b44e6ef3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab87ec718cd11264085752c85b44e6ef3">CAN_F1R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga461e28c08af3e31dacf1b1cd7b8ffcc4">CAN_F1R2_FB30_Pos</a>)</td></tr>
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<tr class="memitem:gabc4aba2c95f27229987d9eb4cda9890c" id="r_gabc4aba2c95f27229987d9eb4cda9890c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc4aba2c95f27229987d9eb4cda9890c">CAN_F1R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab87ec718cd11264085752c85b44e6ef3">CAN_F1R2_FB30_Msk</a></td></tr>
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<tr class="separator:gabc4aba2c95f27229987d9eb4cda9890c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe23be59ff4543be1a357b9bc235ac6e" id="r_gafe23be59ff4543be1a357b9bc235ac6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe23be59ff4543be1a357b9bc235ac6e">CAN_F1R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:gafe23be59ff4543be1a357b9bc235ac6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9cebad85393ecc2a9214f9788b77c676" id="r_ga9cebad85393ecc2a9214f9788b77c676"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cebad85393ecc2a9214f9788b77c676">CAN_F1R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafe23be59ff4543be1a357b9bc235ac6e">CAN_F1R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga9cebad85393ecc2a9214f9788b77c676"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21cbfc217d67062d265753964c871065" id="r_ga21cbfc217d67062d265753964c871065"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21cbfc217d67062d265753964c871065">CAN_F1R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9cebad85393ecc2a9214f9788b77c676">CAN_F1R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga21cbfc217d67062d265753964c871065"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf63fb260c0953b77b1c331f22f38ba67" id="r_gaf63fb260c0953b77b1c331f22f38ba67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf63fb260c0953b77b1c331f22f38ba67">CAN_F2R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf63fb260c0953b77b1c331f22f38ba67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4399948716780ec8c4dd96270469843" id="r_gaf4399948716780ec8c4dd96270469843"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4399948716780ec8c4dd96270469843">CAN_F2R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf63fb260c0953b77b1c331f22f38ba67">CAN_F2R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:gaf4399948716780ec8c4dd96270469843"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36964e4bf6aa10467b3d95781da56814" id="r_ga36964e4bf6aa10467b3d95781da56814"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36964e4bf6aa10467b3d95781da56814">CAN_F2R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4399948716780ec8c4dd96270469843">CAN_F2R2_FB0_Msk</a></td></tr>
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<tr class="memitem:gab8f29d00c90b617c2336012358753e59" id="r_gab8f29d00c90b617c2336012358753e59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8f29d00c90b617c2336012358753e59">CAN_F2R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gab8f29d00c90b617c2336012358753e59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad77d91c1c72f554e0e99650a3f47e737" id="r_gad77d91c1c72f554e0e99650a3f47e737"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad77d91c1c72f554e0e99650a3f47e737">CAN_F2R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8f29d00c90b617c2336012358753e59">CAN_F2R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:gad77d91c1c72f554e0e99650a3f47e737"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d0541eb1a4f8ae0afe429ac0757de6a" id="r_ga0d0541eb1a4f8ae0afe429ac0757de6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d0541eb1a4f8ae0afe429ac0757de6a">CAN_F2R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad77d91c1c72f554e0e99650a3f47e737">CAN_F2R2_FB1_Msk</a></td></tr>
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<tr class="separator:ga0d0541eb1a4f8ae0afe429ac0757de6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ac519efc7774827b8a0acf9c6d84d6e" id="r_ga3ac519efc7774827b8a0acf9c6d84d6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ac519efc7774827b8a0acf9c6d84d6e">CAN_F2R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga3ac519efc7774827b8a0acf9c6d84d6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96dff14e0209cd48bf0c29dc53ede26b" id="r_ga96dff14e0209cd48bf0c29dc53ede26b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96dff14e0209cd48bf0c29dc53ede26b">CAN_F2R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ac519efc7774827b8a0acf9c6d84d6e">CAN_F2R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga96dff14e0209cd48bf0c29dc53ede26b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14fd5aff8767df509b396190ddf7fa28" id="r_ga14fd5aff8767df509b396190ddf7fa28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14fd5aff8767df509b396190ddf7fa28">CAN_F2R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga96dff14e0209cd48bf0c29dc53ede26b">CAN_F2R2_FB2_Msk</a></td></tr>
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<tr class="separator:ga14fd5aff8767df509b396190ddf7fa28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace335e7b5360756df41deae31f2abe97" id="r_gace335e7b5360756df41deae31f2abe97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace335e7b5360756df41deae31f2abe97">CAN_F2R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gace335e7b5360756df41deae31f2abe97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f3b7ec530ba7d4f3effd0c42ab49ca9" id="r_ga4f3b7ec530ba7d4f3effd0c42ab49ca9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f3b7ec530ba7d4f3effd0c42ab49ca9">CAN_F2R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gace335e7b5360756df41deae31f2abe97">CAN_F2R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga4f3b7ec530ba7d4f3effd0c42ab49ca9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7283e2a71983078144fa9a8e5ae563a9" id="r_ga7283e2a71983078144fa9a8e5ae563a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7283e2a71983078144fa9a8e5ae563a9">CAN_F2R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f3b7ec530ba7d4f3effd0c42ab49ca9">CAN_F2R2_FB3_Msk</a></td></tr>
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<tr class="separator:ga7283e2a71983078144fa9a8e5ae563a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac0ff06cee35fcd839c589a9354debd14" id="r_gac0ff06cee35fcd839c589a9354debd14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0ff06cee35fcd839c589a9354debd14">CAN_F2R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gac0ff06cee35fcd839c589a9354debd14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbcaf819adc61da902e94fc549c5eca7" id="r_gafbcaf819adc61da902e94fc549c5eca7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbcaf819adc61da902e94fc549c5eca7">CAN_F2R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac0ff06cee35fcd839c589a9354debd14">CAN_F2R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:gafbcaf819adc61da902e94fc549c5eca7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeba1324d32b084c477a0ece7b904a4cd" id="r_gaeba1324d32b084c477a0ece7b904a4cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeba1324d32b084c477a0ece7b904a4cd">CAN_F2R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafbcaf819adc61da902e94fc549c5eca7">CAN_F2R2_FB4_Msk</a></td></tr>
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<tr class="separator:gaeba1324d32b084c477a0ece7b904a4cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff548790426c82595b210472f7962e60" id="r_gaff548790426c82595b210472f7962e60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff548790426c82595b210472f7962e60">CAN_F2R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaff548790426c82595b210472f7962e60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb028302ad008b6326533727d4fb75b0" id="r_gafb028302ad008b6326533727d4fb75b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb028302ad008b6326533727d4fb75b0">CAN_F2R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaff548790426c82595b210472f7962e60">CAN_F2R2_FB5_Pos</a>)</td></tr>
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<tr class="memitem:ga1a367cf9f2f7e604e9f5e30b5ed30779" id="r_ga1a367cf9f2f7e604e9f5e30b5ed30779"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a367cf9f2f7e604e9f5e30b5ed30779">CAN_F2R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb028302ad008b6326533727d4fb75b0">CAN_F2R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga1a367cf9f2f7e604e9f5e30b5ed30779"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8d334bdd60f7c353f3be0e0f43ab068" id="r_gab8d334bdd60f7c353f3be0e0f43ab068"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8d334bdd60f7c353f3be0e0f43ab068">CAN_F2R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gab8d334bdd60f7c353f3be0e0f43ab068"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d23fc25f4bfb50a6f590e31e11c4838" id="r_ga8d23fc25f4bfb50a6f590e31e11c4838"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d23fc25f4bfb50a6f590e31e11c4838">CAN_F2R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8d334bdd60f7c353f3be0e0f43ab068">CAN_F2R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga8d23fc25f4bfb50a6f590e31e11c4838"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b92ac9785e2f7c890130e9b7d792c79" id="r_ga6b92ac9785e2f7c890130e9b7d792c79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b92ac9785e2f7c890130e9b7d792c79">CAN_F2R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d23fc25f4bfb50a6f590e31e11c4838">CAN_F2R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga6b92ac9785e2f7c890130e9b7d792c79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f1f47aa543e3b89fd13f489408ca8a4" id="r_ga7f1f47aa543e3b89fd13f489408ca8a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f1f47aa543e3b89fd13f489408ca8a4">CAN_F2R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga7f1f47aa543e3b89fd13f489408ca8a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42c27ede1b3c0ad55b1d3ceeb774abbd" id="r_ga42c27ede1b3c0ad55b1d3ceeb774abbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42c27ede1b3c0ad55b1d3ceeb774abbd">CAN_F2R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f1f47aa543e3b89fd13f489408ca8a4">CAN_F2R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga42c27ede1b3c0ad55b1d3ceeb774abbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac969a33d20353d5cd7fb317f5fa71138" id="r_gac969a33d20353d5cd7fb317f5fa71138"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac969a33d20353d5cd7fb317f5fa71138">CAN_F2R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga42c27ede1b3c0ad55b1d3ceeb774abbd">CAN_F2R2_FB7_Msk</a></td></tr>
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<tr class="separator:gac969a33d20353d5cd7fb317f5fa71138"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3338bc9837ac1f00d007a2ae6d79f27f" id="r_ga3338bc9837ac1f00d007a2ae6d79f27f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3338bc9837ac1f00d007a2ae6d79f27f">CAN_F2R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga3338bc9837ac1f00d007a2ae6d79f27f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaace122156ecd18b6abea1a5f23e1cfce" id="r_gaace122156ecd18b6abea1a5f23e1cfce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaace122156ecd18b6abea1a5f23e1cfce">CAN_F2R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3338bc9837ac1f00d007a2ae6d79f27f">CAN_F2R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:gaace122156ecd18b6abea1a5f23e1cfce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafeaac84fa5eec0173c531e9940327f86" id="r_gafeaac84fa5eec0173c531e9940327f86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafeaac84fa5eec0173c531e9940327f86">CAN_F2R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaace122156ecd18b6abea1a5f23e1cfce">CAN_F2R2_FB8_Msk</a></td></tr>
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<tr class="separator:gafeaac84fa5eec0173c531e9940327f86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c4389614bb6ca7bd50b0a72d6e6dd90" id="r_ga7c4389614bb6ca7bd50b0a72d6e6dd90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c4389614bb6ca7bd50b0a72d6e6dd90">CAN_F2R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga7c4389614bb6ca7bd50b0a72d6e6dd90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95a5442d9fc437bc2acdf878279cf7c6" id="r_ga95a5442d9fc437bc2acdf878279cf7c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95a5442d9fc437bc2acdf878279cf7c6">CAN_F2R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c4389614bb6ca7bd50b0a72d6e6dd90">CAN_F2R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga95a5442d9fc437bc2acdf878279cf7c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga532413ea309fa031e65397a5b31ac92c" id="r_ga532413ea309fa031e65397a5b31ac92c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga532413ea309fa031e65397a5b31ac92c">CAN_F2R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga95a5442d9fc437bc2acdf878279cf7c6">CAN_F2R2_FB9_Msk</a></td></tr>
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<tr class="separator:ga532413ea309fa031e65397a5b31ac92c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5fd8ddf4d48ae6b4b8375791a9fe081" id="r_gac5fd8ddf4d48ae6b4b8375791a9fe081"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5fd8ddf4d48ae6b4b8375791a9fe081">CAN_F2R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gac5fd8ddf4d48ae6b4b8375791a9fe081"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebf3a00b21dc2a665b2e8e7b99cefaae" id="r_gaebf3a00b21dc2a665b2e8e7b99cefaae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebf3a00b21dc2a665b2e8e7b99cefaae">CAN_F2R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac5fd8ddf4d48ae6b4b8375791a9fe081">CAN_F2R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:gaebf3a00b21dc2a665b2e8e7b99cefaae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga360e02860472400a9000ef2fc8ba7bb1" id="r_ga360e02860472400a9000ef2fc8ba7bb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga360e02860472400a9000ef2fc8ba7bb1">CAN_F2R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaebf3a00b21dc2a665b2e8e7b99cefaae">CAN_F2R2_FB10_Msk</a></td></tr>
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<tr class="separator:ga360e02860472400a9000ef2fc8ba7bb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62d108467a53b2dd5992d6bde9ed771e" id="r_ga62d108467a53b2dd5992d6bde9ed771e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62d108467a53b2dd5992d6bde9ed771e">CAN_F2R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga62d108467a53b2dd5992d6bde9ed771e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb77bebe0b062fe55efc6304cf8840b4" id="r_gadb77bebe0b062fe55efc6304cf8840b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb77bebe0b062fe55efc6304cf8840b4">CAN_F2R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga62d108467a53b2dd5992d6bde9ed771e">CAN_F2R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:gadb77bebe0b062fe55efc6304cf8840b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c917a5b5e1a010229caaa5b3a41d7a6" id="r_ga4c917a5b5e1a010229caaa5b3a41d7a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c917a5b5e1a010229caaa5b3a41d7a6">CAN_F2R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadb77bebe0b062fe55efc6304cf8840b4">CAN_F2R2_FB11_Msk</a></td></tr>
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<tr class="separator:ga4c917a5b5e1a010229caaa5b3a41d7a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga831b9df6d417ca891d10d42826a7412d" id="r_ga831b9df6d417ca891d10d42826a7412d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga831b9df6d417ca891d10d42826a7412d">CAN_F2R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga831b9df6d417ca891d10d42826a7412d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04dd0cb91d888b98351e33516a4547e1" id="r_ga04dd0cb91d888b98351e33516a4547e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04dd0cb91d888b98351e33516a4547e1">CAN_F2R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga831b9df6d417ca891d10d42826a7412d">CAN_F2R2_FB12_Pos</a>)</td></tr>
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<tr class="separator:ga04dd0cb91d888b98351e33516a4547e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0956873246e63b41c0a640bc8d117319" id="r_ga0956873246e63b41c0a640bc8d117319"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0956873246e63b41c0a640bc8d117319">CAN_F2R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga04dd0cb91d888b98351e33516a4547e1">CAN_F2R2_FB12_Msk</a></td></tr>
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<tr class="separator:ga0956873246e63b41c0a640bc8d117319"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a22208eb5078a7bfc81c4d9425d3768" id="r_ga0a22208eb5078a7bfc81c4d9425d3768"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a22208eb5078a7bfc81c4d9425d3768">CAN_F2R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0a22208eb5078a7bfc81c4d9425d3768"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f6af8fc2890a6b457435f0ab29908e4" id="r_ga7f6af8fc2890a6b457435f0ab29908e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f6af8fc2890a6b457435f0ab29908e4">CAN_F2R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a22208eb5078a7bfc81c4d9425d3768">CAN_F2R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga7f6af8fc2890a6b457435f0ab29908e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53202218de27d073d577c27427fe0cbe" id="r_ga53202218de27d073d577c27427fe0cbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53202218de27d073d577c27427fe0cbe">CAN_F2R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f6af8fc2890a6b457435f0ab29908e4">CAN_F2R2_FB13_Msk</a></td></tr>
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<tr class="separator:ga53202218de27d073d577c27427fe0cbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa084d675b30eec4c52eda4e06ef7e79" id="r_gafa084d675b30eec4c52eda4e06ef7e79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa084d675b30eec4c52eda4e06ef7e79">CAN_F2R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gafa084d675b30eec4c52eda4e06ef7e79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7f01b289ae8ae3eecedd8a29ddc1eb1" id="r_gac7f01b289ae8ae3eecedd8a29ddc1eb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7f01b289ae8ae3eecedd8a29ddc1eb1">CAN_F2R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafa084d675b30eec4c52eda4e06ef7e79">CAN_F2R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:gac7f01b289ae8ae3eecedd8a29ddc1eb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga960a1ffd4b153168494d91df69e30742" id="r_ga960a1ffd4b153168494d91df69e30742"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga960a1ffd4b153168494d91df69e30742">CAN_F2R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac7f01b289ae8ae3eecedd8a29ddc1eb1">CAN_F2R2_FB14_Msk</a></td></tr>
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<tr class="separator:ga960a1ffd4b153168494d91df69e30742"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga956077f7bdb372a7bf0c608b13c8f7f8" id="r_ga956077f7bdb372a7bf0c608b13c8f7f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga956077f7bdb372a7bf0c608b13c8f7f8">CAN_F2R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga956077f7bdb372a7bf0c608b13c8f7f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c79b4445a4d0eb87b2121d58c73d9bc" id="r_ga1c79b4445a4d0eb87b2121d58c73d9bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c79b4445a4d0eb87b2121d58c73d9bc">CAN_F2R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga956077f7bdb372a7bf0c608b13c8f7f8">CAN_F2R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga1c79b4445a4d0eb87b2121d58c73d9bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc81e9ab9ab926d1ca30c5b6060a126b" id="r_gafc81e9ab9ab926d1ca30c5b6060a126b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc81e9ab9ab926d1ca30c5b6060a126b">CAN_F2R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c79b4445a4d0eb87b2121d58c73d9bc">CAN_F2R2_FB15_Msk</a></td></tr>
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<tr class="separator:gafc81e9ab9ab926d1ca30c5b6060a126b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcb245f4a5552692ce95229e29c99b1d" id="r_gadcb245f4a5552692ce95229e29c99b1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcb245f4a5552692ce95229e29c99b1d">CAN_F2R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:gadcb245f4a5552692ce95229e29c99b1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ae7788f7206aca6e83ba0cd081af5b2" id="r_ga3ae7788f7206aca6e83ba0cd081af5b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ae7788f7206aca6e83ba0cd081af5b2">CAN_F2R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadcb245f4a5552692ce95229e29c99b1d">CAN_F2R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga3ae7788f7206aca6e83ba0cd081af5b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5f9a5279398454a3a2493b3e1783f52" id="r_gaa5f9a5279398454a3a2493b3e1783f52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5f9a5279398454a3a2493b3e1783f52">CAN_F2R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ae7788f7206aca6e83ba0cd081af5b2">CAN_F2R2_FB16_Msk</a></td></tr>
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<tr class="separator:gaa5f9a5279398454a3a2493b3e1783f52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e7149f9b6d387983aa9cfddda59c1ac" id="r_ga3e7149f9b6d387983aa9cfddda59c1ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e7149f9b6d387983aa9cfddda59c1ac">CAN_F2R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga3e7149f9b6d387983aa9cfddda59c1ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0d302da92dc7ff48bfb3935a739c56f" id="r_gaa0d302da92dc7ff48bfb3935a739c56f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0d302da92dc7ff48bfb3935a739c56f">CAN_F2R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e7149f9b6d387983aa9cfddda59c1ac">CAN_F2R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:gaa0d302da92dc7ff48bfb3935a739c56f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0275ec7527a223a33289118f9e0a2edd" id="r_ga0275ec7527a223a33289118f9e0a2edd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0275ec7527a223a33289118f9e0a2edd">CAN_F2R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0d302da92dc7ff48bfb3935a739c56f">CAN_F2R2_FB17_Msk</a></td></tr>
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<tr class="separator:ga0275ec7527a223a33289118f9e0a2edd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67d39926ab846913f9cc5a077ab2451a" id="r_ga67d39926ab846913f9cc5a077ab2451a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67d39926ab846913f9cc5a077ab2451a">CAN_F2R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga67d39926ab846913f9cc5a077ab2451a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ee8abd5207088cb6f59a3fd5af3b89a" id="r_ga7ee8abd5207088cb6f59a3fd5af3b89a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ee8abd5207088cb6f59a3fd5af3b89a">CAN_F2R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67d39926ab846913f9cc5a077ab2451a">CAN_F2R2_FB18_Pos</a>)</td></tr>
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<tr class="separator:ga7ee8abd5207088cb6f59a3fd5af3b89a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34028a240868ca7dd365ce98e31e84ca" id="r_ga34028a240868ca7dd365ce98e31e84ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34028a240868ca7dd365ce98e31e84ca">CAN_F2R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ee8abd5207088cb6f59a3fd5af3b89a">CAN_F2R2_FB18_Msk</a></td></tr>
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<tr class="separator:ga34028a240868ca7dd365ce98e31e84ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga711201f0da7b487c7111c4e587f84d12" id="r_ga711201f0da7b487c7111c4e587f84d12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga711201f0da7b487c7111c4e587f84d12">CAN_F2R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga711201f0da7b487c7111c4e587f84d12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab6ad53d41a895d341e102901c2e4113b" id="r_gab6ad53d41a895d341e102901c2e4113b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6ad53d41a895d341e102901c2e4113b">CAN_F2R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga711201f0da7b487c7111c4e587f84d12">CAN_F2R2_FB19_Pos</a>)</td></tr>
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<tr class="memitem:ga807cfa122b6c74d85fdab233dd9ed502" id="r_ga807cfa122b6c74d85fdab233dd9ed502"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga807cfa122b6c74d85fdab233dd9ed502">CAN_F2R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab6ad53d41a895d341e102901c2e4113b">CAN_F2R2_FB19_Msk</a></td></tr>
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<tr class="memitem:ga2664848f3b5f6f02d916a85c2995377e" id="r_ga2664848f3b5f6f02d916a85c2995377e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2664848f3b5f6f02d916a85c2995377e">CAN_F2R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="memitem:gae6b747f768a440c5e8fe08febc1d0683" id="r_gae6b747f768a440c5e8fe08febc1d0683"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6b747f768a440c5e8fe08febc1d0683">CAN_F2R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2664848f3b5f6f02d916a85c2995377e">CAN_F2R2_FB20_Pos</a>)</td></tr>
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<tr class="separator:gae6b747f768a440c5e8fe08febc1d0683"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1187f1ab7514c90af34b44eff80858fa" id="r_ga1187f1ab7514c90af34b44eff80858fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1187f1ab7514c90af34b44eff80858fa">CAN_F2R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae6b747f768a440c5e8fe08febc1d0683">CAN_F2R2_FB20_Msk</a></td></tr>
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<tr class="separator:ga1187f1ab7514c90af34b44eff80858fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga803f8529db84971c2b5c425cf5ece37b" id="r_ga803f8529db84971c2b5c425cf5ece37b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga803f8529db84971c2b5c425cf5ece37b">CAN_F2R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga803f8529db84971c2b5c425cf5ece37b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc046157f775cb1a2c5b2b90aa15d745" id="r_gafc046157f775cb1a2c5b2b90aa15d745"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc046157f775cb1a2c5b2b90aa15d745">CAN_F2R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga803f8529db84971c2b5c425cf5ece37b">CAN_F2R2_FB21_Pos</a>)</td></tr>
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<tr class="separator:gafc046157f775cb1a2c5b2b90aa15d745"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacecb18e779a44989b724901f6c2af84f" id="r_gacecb18e779a44989b724901f6c2af84f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacecb18e779a44989b724901f6c2af84f">CAN_F2R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafc046157f775cb1a2c5b2b90aa15d745">CAN_F2R2_FB21_Msk</a></td></tr>
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<tr class="separator:gacecb18e779a44989b724901f6c2af84f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga007e6dcd0caab8184192fb9780535e88" id="r_ga007e6dcd0caab8184192fb9780535e88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga007e6dcd0caab8184192fb9780535e88">CAN_F2R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga007e6dcd0caab8184192fb9780535e88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23fdd1fa55e6729712aad51a2ce62834" id="r_ga23fdd1fa55e6729712aad51a2ce62834"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23fdd1fa55e6729712aad51a2ce62834">CAN_F2R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga007e6dcd0caab8184192fb9780535e88">CAN_F2R2_FB22_Pos</a>)</td></tr>
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<tr class="memitem:ga3f2a6017895d8d139dcbc3d0e6e69e69" id="r_ga3f2a6017895d8d139dcbc3d0e6e69e69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f2a6017895d8d139dcbc3d0e6e69e69">CAN_F2R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga23fdd1fa55e6729712aad51a2ce62834">CAN_F2R2_FB22_Msk</a></td></tr>
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<tr class="separator:ga3f2a6017895d8d139dcbc3d0e6e69e69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ed215ff7fa7ffdb6fe61431c3634a53" id="r_ga5ed215ff7fa7ffdb6fe61431c3634a53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ed215ff7fa7ffdb6fe61431c3634a53">CAN_F2R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga5ed215ff7fa7ffdb6fe61431c3634a53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4508040a17ba6d514e9c5db40131a196" id="r_ga4508040a17ba6d514e9c5db40131a196"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4508040a17ba6d514e9c5db40131a196">CAN_F2R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ed215ff7fa7ffdb6fe61431c3634a53">CAN_F2R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga4508040a17ba6d514e9c5db40131a196"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaceff2f283cbd4935ec5d45ceaa18efe0" id="r_gaceff2f283cbd4935ec5d45ceaa18efe0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaceff2f283cbd4935ec5d45ceaa18efe0">CAN_F2R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4508040a17ba6d514e9c5db40131a196">CAN_F2R2_FB23_Msk</a></td></tr>
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<tr class="separator:gaceff2f283cbd4935ec5d45ceaa18efe0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga838adce88b9370f7a2559bbb2ce268ce" id="r_ga838adce88b9370f7a2559bbb2ce268ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga838adce88b9370f7a2559bbb2ce268ce">CAN_F2R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga838adce88b9370f7a2559bbb2ce268ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae17fde946459dc3fc90da9e8809d6d05" id="r_gae17fde946459dc3fc90da9e8809d6d05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae17fde946459dc3fc90da9e8809d6d05">CAN_F2R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga838adce88b9370f7a2559bbb2ce268ce">CAN_F2R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:gae17fde946459dc3fc90da9e8809d6d05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3086667a209f91ed6d6b496b83111044" id="r_ga3086667a209f91ed6d6b496b83111044"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3086667a209f91ed6d6b496b83111044">CAN_F2R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae17fde946459dc3fc90da9e8809d6d05">CAN_F2R2_FB24_Msk</a></td></tr>
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<tr class="separator:ga3086667a209f91ed6d6b496b83111044"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93be5f2dee61eb1a67711f9037864725" id="r_ga93be5f2dee61eb1a67711f9037864725"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93be5f2dee61eb1a67711f9037864725">CAN_F2R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga93be5f2dee61eb1a67711f9037864725"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03da1089ea38abbe1093471a67a971fa" id="r_ga03da1089ea38abbe1093471a67a971fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03da1089ea38abbe1093471a67a971fa">CAN_F2R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga93be5f2dee61eb1a67711f9037864725">CAN_F2R2_FB25_Pos</a>)</td></tr>
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<tr class="memitem:ga5c8c7b240bb0dd2a3ec8b6c4c25af7ba" id="r_ga5c8c7b240bb0dd2a3ec8b6c4c25af7ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c8c7b240bb0dd2a3ec8b6c4c25af7ba">CAN_F2R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga03da1089ea38abbe1093471a67a971fa">CAN_F2R2_FB25_Msk</a></td></tr>
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<tr class="separator:ga5c8c7b240bb0dd2a3ec8b6c4c25af7ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b2487dff59abf0a4aff74d5a8e5bf85" id="r_ga3b2487dff59abf0a4aff74d5a8e5bf85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b2487dff59abf0a4aff74d5a8e5bf85">CAN_F2R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga3b2487dff59abf0a4aff74d5a8e5bf85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacef46477e39c33367b4cc071c1e3fc69" id="r_gacef46477e39c33367b4cc071c1e3fc69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacef46477e39c33367b4cc071c1e3fc69">CAN_F2R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b2487dff59abf0a4aff74d5a8e5bf85">CAN_F2R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:gacef46477e39c33367b4cc071c1e3fc69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51498379a1e3b81a83bf8d164c4f7e5e" id="r_ga51498379a1e3b81a83bf8d164c4f7e5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51498379a1e3b81a83bf8d164c4f7e5e">CAN_F2R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacef46477e39c33367b4cc071c1e3fc69">CAN_F2R2_FB26_Msk</a></td></tr>
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<tr class="separator:ga51498379a1e3b81a83bf8d164c4f7e5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7470e371f95c91d7222c919e63d3c92f" id="r_ga7470e371f95c91d7222c919e63d3c92f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7470e371f95c91d7222c919e63d3c92f">CAN_F2R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga7470e371f95c91d7222c919e63d3c92f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga833458f427d74480b7a400ace687432e" id="r_ga833458f427d74480b7a400ace687432e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga833458f427d74480b7a400ace687432e">CAN_F2R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7470e371f95c91d7222c919e63d3c92f">CAN_F2R2_FB27_Pos</a>)</td></tr>
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<tr class="memitem:gaa1f78e7c530a3ef26d44b9353fa9ee36" id="r_gaa1f78e7c530a3ef26d44b9353fa9ee36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1f78e7c530a3ef26d44b9353fa9ee36">CAN_F2R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga833458f427d74480b7a400ace687432e">CAN_F2R2_FB27_Msk</a></td></tr>
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<tr class="separator:gaa1f78e7c530a3ef26d44b9353fa9ee36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7bc089024482b8555fc44374c3ff5bc" id="r_gab7bc089024482b8555fc44374c3ff5bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7bc089024482b8555fc44374c3ff5bc">CAN_F2R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:gab7bc089024482b8555fc44374c3ff5bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc909d367700acef6e2bf8954fcbed1c" id="r_gafc909d367700acef6e2bf8954fcbed1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc909d367700acef6e2bf8954fcbed1c">CAN_F2R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab7bc089024482b8555fc44374c3ff5bc">CAN_F2R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:gafc909d367700acef6e2bf8954fcbed1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e30d0e50fca346ca8cb427a6c85f9dc" id="r_ga7e30d0e50fca346ca8cb427a6c85f9dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e30d0e50fca346ca8cb427a6c85f9dc">CAN_F2R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafc909d367700acef6e2bf8954fcbed1c">CAN_F2R2_FB28_Msk</a></td></tr>
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<tr class="separator:ga7e30d0e50fca346ca8cb427a6c85f9dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae76e0f99ff3d94336ea5da68bcd0761a" id="r_gae76e0f99ff3d94336ea5da68bcd0761a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae76e0f99ff3d94336ea5da68bcd0761a">CAN_F2R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:gae76e0f99ff3d94336ea5da68bcd0761a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac030b2a517b48686820ece2c433e2f13" id="r_gac030b2a517b48686820ece2c433e2f13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac030b2a517b48686820ece2c433e2f13">CAN_F2R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae76e0f99ff3d94336ea5da68bcd0761a">CAN_F2R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:gac030b2a517b48686820ece2c433e2f13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77586d252cad5a0a866b1d9deb6835ba" id="r_ga77586d252cad5a0a866b1d9deb6835ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77586d252cad5a0a866b1d9deb6835ba">CAN_F2R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac030b2a517b48686820ece2c433e2f13">CAN_F2R2_FB29_Msk</a></td></tr>
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<tr class="memitem:ga13dcafb2960be76467f3aa3f5e11c9cd" id="r_ga13dcafb2960be76467f3aa3f5e11c9cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13dcafb2960be76467f3aa3f5e11c9cd">CAN_F2R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga13dcafb2960be76467f3aa3f5e11c9cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1fbf050f9c8c01df6dd11938eb663221" id="r_ga1fbf050f9c8c01df6dd11938eb663221"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fbf050f9c8c01df6dd11938eb663221">CAN_F2R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga13dcafb2960be76467f3aa3f5e11c9cd">CAN_F2R2_FB30_Pos</a>)</td></tr>
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<tr class="memitem:ga6a10903e507b35b7425b3ae98a8c6800" id="r_ga6a10903e507b35b7425b3ae98a8c6800"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a10903e507b35b7425b3ae98a8c6800">CAN_F2R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fbf050f9c8c01df6dd11938eb663221">CAN_F2R2_FB30_Msk</a></td></tr>
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<tr class="separator:ga6a10903e507b35b7425b3ae98a8c6800"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e2628938146647cf456f8800cc4c6cc" id="r_ga1e2628938146647cf456f8800cc4c6cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e2628938146647cf456f8800cc4c6cc">CAN_F2R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="memitem:ga38b5f7d56afc77679c64cc8559c9637c" id="r_ga38b5f7d56afc77679c64cc8559c9637c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38b5f7d56afc77679c64cc8559c9637c">CAN_F2R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e2628938146647cf456f8800cc4c6cc">CAN_F2R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga38b5f7d56afc77679c64cc8559c9637c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac34bca92730b6f7cd0de8af1a2d0014f" id="r_gac34bca92730b6f7cd0de8af1a2d0014f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac34bca92730b6f7cd0de8af1a2d0014f">CAN_F2R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38b5f7d56afc77679c64cc8559c9637c">CAN_F2R2_FB31_Msk</a></td></tr>
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<tr class="memitem:ga3e56069f9e4901fdf5d593117c00f56c" id="r_ga3e56069f9e4901fdf5d593117c00f56c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e56069f9e4901fdf5d593117c00f56c">CAN_F3R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3e56069f9e4901fdf5d593117c00f56c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa00bc043a80895a2364fdb9e51b3c110" id="r_gaa00bc043a80895a2364fdb9e51b3c110"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa00bc043a80895a2364fdb9e51b3c110">CAN_F3R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e56069f9e4901fdf5d593117c00f56c">CAN_F3R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:gaa00bc043a80895a2364fdb9e51b3c110"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46730b7e64aa771087b6c9d5deb273e1" id="r_ga46730b7e64aa771087b6c9d5deb273e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46730b7e64aa771087b6c9d5deb273e1">CAN_F3R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa00bc043a80895a2364fdb9e51b3c110">CAN_F3R2_FB0_Msk</a></td></tr>
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<tr class="separator:ga46730b7e64aa771087b6c9d5deb273e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67bcdd4d126db81bcece2a81de89c904" id="r_ga67bcdd4d126db81bcece2a81de89c904"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67bcdd4d126db81bcece2a81de89c904">CAN_F3R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga67bcdd4d126db81bcece2a81de89c904"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9f4626256cd6e806d02f8ddd1abc6d6" id="r_gaa9f4626256cd6e806d02f8ddd1abc6d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9f4626256cd6e806d02f8ddd1abc6d6">CAN_F3R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67bcdd4d126db81bcece2a81de89c904">CAN_F3R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:gaa9f4626256cd6e806d02f8ddd1abc6d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb12b61624912b90382a4ad95281e7f4" id="r_gaeb12b61624912b90382a4ad95281e7f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb12b61624912b90382a4ad95281e7f4">CAN_F3R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9f4626256cd6e806d02f8ddd1abc6d6">CAN_F3R2_FB1_Msk</a></td></tr>
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<tr class="separator:gaeb12b61624912b90382a4ad95281e7f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2560be72957af6d4f7449908671d8b46" id="r_ga2560be72957af6d4f7449908671d8b46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2560be72957af6d4f7449908671d8b46">CAN_F3R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga2560be72957af6d4f7449908671d8b46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d2e95083cd9cba8a5e1dea50a2647b5" id="r_ga9d2e95083cd9cba8a5e1dea50a2647b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d2e95083cd9cba8a5e1dea50a2647b5">CAN_F3R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2560be72957af6d4f7449908671d8b46">CAN_F3R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga9d2e95083cd9cba8a5e1dea50a2647b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6621759dddc575c01f5bbaab43d1f04e" id="r_ga6621759dddc575c01f5bbaab43d1f04e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6621759dddc575c01f5bbaab43d1f04e">CAN_F3R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d2e95083cd9cba8a5e1dea50a2647b5">CAN_F3R2_FB2_Msk</a></td></tr>
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<tr class="separator:ga6621759dddc575c01f5bbaab43d1f04e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabda68247678b28226021fdfad9efab7a" id="r_gabda68247678b28226021fdfad9efab7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabda68247678b28226021fdfad9efab7a">CAN_F3R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gabda68247678b28226021fdfad9efab7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1586ad1b9e7dc5ea9060b11c91c64df" id="r_gaa1586ad1b9e7dc5ea9060b11c91c64df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1586ad1b9e7dc5ea9060b11c91c64df">CAN_F3R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabda68247678b28226021fdfad9efab7a">CAN_F3R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:gaa1586ad1b9e7dc5ea9060b11c91c64df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29d052fc2597171767d8cf5d72388ad5" id="r_ga29d052fc2597171767d8cf5d72388ad5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29d052fc2597171767d8cf5d72388ad5">CAN_F3R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1586ad1b9e7dc5ea9060b11c91c64df">CAN_F3R2_FB3_Msk</a></td></tr>
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<tr class="separator:ga29d052fc2597171767d8cf5d72388ad5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d8222da6dc5c339fc0b0f189a25cc49" id="r_ga3d8222da6dc5c339fc0b0f189a25cc49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d8222da6dc5c339fc0b0f189a25cc49">CAN_F3R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga3d8222da6dc5c339fc0b0f189a25cc49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e602cc571c125a4b0a37ef41a35944b" id="r_ga6e602cc571c125a4b0a37ef41a35944b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e602cc571c125a4b0a37ef41a35944b">CAN_F3R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d8222da6dc5c339fc0b0f189a25cc49">CAN_F3R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga6e602cc571c125a4b0a37ef41a35944b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga731e9949d77054ba176340652083ad46" id="r_ga731e9949d77054ba176340652083ad46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga731e9949d77054ba176340652083ad46">CAN_F3R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e602cc571c125a4b0a37ef41a35944b">CAN_F3R2_FB4_Msk</a></td></tr>
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<tr class="separator:ga731e9949d77054ba176340652083ad46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55736898b14b121dec11e82b5aefe05c" id="r_ga55736898b14b121dec11e82b5aefe05c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55736898b14b121dec11e82b5aefe05c">CAN_F3R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga55736898b14b121dec11e82b5aefe05c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb8c785ed06bbd1d49756b36134e7acb" id="r_gafb8c785ed06bbd1d49756b36134e7acb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb8c785ed06bbd1d49756b36134e7acb">CAN_F3R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55736898b14b121dec11e82b5aefe05c">CAN_F3R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:gafb8c785ed06bbd1d49756b36134e7acb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93c52f51fe9eefe7f0cf094522a592b6" id="r_ga93c52f51fe9eefe7f0cf094522a592b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93c52f51fe9eefe7f0cf094522a592b6">CAN_F3R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb8c785ed06bbd1d49756b36134e7acb">CAN_F3R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga93c52f51fe9eefe7f0cf094522a592b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11e7b32a226938156cb9f39271523da5" id="r_ga11e7b32a226938156cb9f39271523da5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11e7b32a226938156cb9f39271523da5">CAN_F3R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga11e7b32a226938156cb9f39271523da5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf8497045acac1d2e6704dcefa92d3b0" id="r_gaaf8497045acac1d2e6704dcefa92d3b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf8497045acac1d2e6704dcefa92d3b0">CAN_F3R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11e7b32a226938156cb9f39271523da5">CAN_F3R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:gaaf8497045acac1d2e6704dcefa92d3b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad675c2d3f72d8bc42e0f3088ddbcc3c9" id="r_gad675c2d3f72d8bc42e0f3088ddbcc3c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad675c2d3f72d8bc42e0f3088ddbcc3c9">CAN_F3R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf8497045acac1d2e6704dcefa92d3b0">CAN_F3R2_FB6_Msk</a></td></tr>
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<tr class="separator:gad675c2d3f72d8bc42e0f3088ddbcc3c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6117333279671f33e6cb91c69434711e" id="r_ga6117333279671f33e6cb91c69434711e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6117333279671f33e6cb91c69434711e">CAN_F3R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga6117333279671f33e6cb91c69434711e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga655169f5704760518f05c635259c7177" id="r_ga655169f5704760518f05c635259c7177"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga655169f5704760518f05c635259c7177">CAN_F3R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6117333279671f33e6cb91c69434711e">CAN_F3R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga655169f5704760518f05c635259c7177"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1734cf6a5a72d403cd043eb704246c85" id="r_ga1734cf6a5a72d403cd043eb704246c85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1734cf6a5a72d403cd043eb704246c85">CAN_F3R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga655169f5704760518f05c635259c7177">CAN_F3R2_FB7_Msk</a></td></tr>
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<tr class="memitem:ga927026c4212e401f403b68ed66b2c1c3" id="r_ga927026c4212e401f403b68ed66b2c1c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga927026c4212e401f403b68ed66b2c1c3">CAN_F3R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga927026c4212e401f403b68ed66b2c1c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafad82eee295a8a2858712b7a8e78b2a0" id="r_gafad82eee295a8a2858712b7a8e78b2a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafad82eee295a8a2858712b7a8e78b2a0">CAN_F3R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga927026c4212e401f403b68ed66b2c1c3">CAN_F3R2_FB8_Pos</a>)</td></tr>
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<tr class="memitem:ga97d82554ce38567e44cd87ed99175928" id="r_ga97d82554ce38567e44cd87ed99175928"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97d82554ce38567e44cd87ed99175928">CAN_F3R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafad82eee295a8a2858712b7a8e78b2a0">CAN_F3R2_FB8_Msk</a></td></tr>
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<tr class="separator:ga97d82554ce38567e44cd87ed99175928"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga931d7f76fa1e6a1a49faaf5338829448" id="r_ga931d7f76fa1e6a1a49faaf5338829448"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga931d7f76fa1e6a1a49faaf5338829448">CAN_F3R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga931d7f76fa1e6a1a49faaf5338829448"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13711889ff55a6b01f7141db5f702c7a" id="r_ga13711889ff55a6b01f7141db5f702c7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13711889ff55a6b01f7141db5f702c7a">CAN_F3R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga931d7f76fa1e6a1a49faaf5338829448">CAN_F3R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga13711889ff55a6b01f7141db5f702c7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga505f85fadba4397e6d9a241bbc9229bc" id="r_ga505f85fadba4397e6d9a241bbc9229bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga505f85fadba4397e6d9a241bbc9229bc">CAN_F3R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga13711889ff55a6b01f7141db5f702c7a">CAN_F3R2_FB9_Msk</a></td></tr>
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<tr class="separator:ga505f85fadba4397e6d9a241bbc9229bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c8ef622ab70278942e2dff25afb0ed6" id="r_ga4c8ef622ab70278942e2dff25afb0ed6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c8ef622ab70278942e2dff25afb0ed6">CAN_F3R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga4c8ef622ab70278942e2dff25afb0ed6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbdde33568809be7611190d6b1b81012" id="r_gafbdde33568809be7611190d6b1b81012"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbdde33568809be7611190d6b1b81012">CAN_F3R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c8ef622ab70278942e2dff25afb0ed6">CAN_F3R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:gafbdde33568809be7611190d6b1b81012"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb635843951fb42ffeb776d8564d7e14" id="r_gabb635843951fb42ffeb776d8564d7e14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb635843951fb42ffeb776d8564d7e14">CAN_F3R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafbdde33568809be7611190d6b1b81012">CAN_F3R2_FB10_Msk</a></td></tr>
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<tr class="memitem:ga6ceab55d83e6190c4b159baffae431a1" id="r_ga6ceab55d83e6190c4b159baffae431a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ceab55d83e6190c4b159baffae431a1">CAN_F3R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga6ceab55d83e6190c4b159baffae431a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaed31d50f1d71f70a49a880e2c743663" id="r_gaaed31d50f1d71f70a49a880e2c743663"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaed31d50f1d71f70a49a880e2c743663">CAN_F3R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ceab55d83e6190c4b159baffae431a1">CAN_F3R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:gaaed31d50f1d71f70a49a880e2c743663"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5db557239646008004286de15847ced4" id="r_ga5db557239646008004286de15847ced4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5db557239646008004286de15847ced4">CAN_F3R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaed31d50f1d71f70a49a880e2c743663">CAN_F3R2_FB11_Msk</a></td></tr>
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<tr class="separator:ga5db557239646008004286de15847ced4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae836a910f4fa7d303000f82a1eef47ab" id="r_gae836a910f4fa7d303000f82a1eef47ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae836a910f4fa7d303000f82a1eef47ab">CAN_F3R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gae836a910f4fa7d303000f82a1eef47ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66fcb0196d04b5e606b1c4a2287a3f36" id="r_ga66fcb0196d04b5e606b1c4a2287a3f36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66fcb0196d04b5e606b1c4a2287a3f36">CAN_F3R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae836a910f4fa7d303000f82a1eef47ab">CAN_F3R2_FB12_Pos</a>)</td></tr>
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<tr class="separator:ga66fcb0196d04b5e606b1c4a2287a3f36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga118b2044dae4c93c66aaa4f28c5b695c" id="r_ga118b2044dae4c93c66aaa4f28c5b695c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga118b2044dae4c93c66aaa4f28c5b695c">CAN_F3R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga66fcb0196d04b5e606b1c4a2287a3f36">CAN_F3R2_FB12_Msk</a></td></tr>
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<tr class="separator:ga118b2044dae4c93c66aaa4f28c5b695c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8a1b5f346de27041c6dcf3d30239664" id="r_gaf8a1b5f346de27041c6dcf3d30239664"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8a1b5f346de27041c6dcf3d30239664">CAN_F3R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaf8a1b5f346de27041c6dcf3d30239664"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7c0fc4c6e615f3274c846c5f63319bb" id="r_gae7c0fc4c6e615f3274c846c5f63319bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7c0fc4c6e615f3274c846c5f63319bb">CAN_F3R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8a1b5f346de27041c6dcf3d30239664">CAN_F3R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:gae7c0fc4c6e615f3274c846c5f63319bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c041a2b8162a8055a1894d0a0b3d682" id="r_ga8c041a2b8162a8055a1894d0a0b3d682"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c041a2b8162a8055a1894d0a0b3d682">CAN_F3R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae7c0fc4c6e615f3274c846c5f63319bb">CAN_F3R2_FB13_Msk</a></td></tr>
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<tr class="separator:ga8c041a2b8162a8055a1894d0a0b3d682"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a4239e4164239d1ec1f6fa7e378f245" id="r_ga1a4239e4164239d1ec1f6fa7e378f245"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a4239e4164239d1ec1f6fa7e378f245">CAN_F3R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga1a4239e4164239d1ec1f6fa7e378f245"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7318a2aa45622bb3ff2067b295c89839" id="r_ga7318a2aa45622bb3ff2067b295c89839"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7318a2aa45622bb3ff2067b295c89839">CAN_F3R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a4239e4164239d1ec1f6fa7e378f245">CAN_F3R2_FB14_Pos</a>)</td></tr>
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<tr class="memitem:gafb6e0947fcb7594d12dcbca38d60c9f8" id="r_gafb6e0947fcb7594d12dcbca38d60c9f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb6e0947fcb7594d12dcbca38d60c9f8">CAN_F3R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7318a2aa45622bb3ff2067b295c89839">CAN_F3R2_FB14_Msk</a></td></tr>
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<tr class="memitem:ga0abb9b1be5c5538b70b95c29f5f8feb0" id="r_ga0abb9b1be5c5538b70b95c29f5f8feb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0abb9b1be5c5538b70b95c29f5f8feb0">CAN_F3R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga0abb9b1be5c5538b70b95c29f5f8feb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdf5ab40d21a35f3bd2330139043b4c6" id="r_gacdf5ab40d21a35f3bd2330139043b4c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdf5ab40d21a35f3bd2330139043b4c6">CAN_F3R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0abb9b1be5c5538b70b95c29f5f8feb0">CAN_F3R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:gacdf5ab40d21a35f3bd2330139043b4c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1dae8addc6fa59e824e1a67fc8c91ddd" id="r_ga1dae8addc6fa59e824e1a67fc8c91ddd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1dae8addc6fa59e824e1a67fc8c91ddd">CAN_F3R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacdf5ab40d21a35f3bd2330139043b4c6">CAN_F3R2_FB15_Msk</a></td></tr>
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<tr class="separator:ga1dae8addc6fa59e824e1a67fc8c91ddd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3ee39cb4edc55608b96077047dc790a" id="r_gaf3ee39cb4edc55608b96077047dc790a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3ee39cb4edc55608b96077047dc790a">CAN_F3R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaf3ee39cb4edc55608b96077047dc790a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae505ba19e3d139a3e51aa661927c2f79" id="r_gae505ba19e3d139a3e51aa661927c2f79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae505ba19e3d139a3e51aa661927c2f79">CAN_F3R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3ee39cb4edc55608b96077047dc790a">CAN_F3R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:gae505ba19e3d139a3e51aa661927c2f79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga992795c5e0b3b8a8c5d4d6e9eceb7366" id="r_ga992795c5e0b3b8a8c5d4d6e9eceb7366"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga992795c5e0b3b8a8c5d4d6e9eceb7366">CAN_F3R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae505ba19e3d139a3e51aa661927c2f79">CAN_F3R2_FB16_Msk</a></td></tr>
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<tr class="separator:ga992795c5e0b3b8a8c5d4d6e9eceb7366"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe35a463b0df8233fd2c252d9e476671" id="r_gabe35a463b0df8233fd2c252d9e476671"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe35a463b0df8233fd2c252d9e476671">CAN_F3R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gabe35a463b0df8233fd2c252d9e476671"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45fcd762f60b60e56fe4bd937ac7950b" id="r_ga45fcd762f60b60e56fe4bd937ac7950b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45fcd762f60b60e56fe4bd937ac7950b">CAN_F3R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabe35a463b0df8233fd2c252d9e476671">CAN_F3R2_FB17_Pos</a>)</td></tr>
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<tr class="memitem:ga1637eff70416eb85d5d2a54e1f5d412e" id="r_ga1637eff70416eb85d5d2a54e1f5d412e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1637eff70416eb85d5d2a54e1f5d412e">CAN_F3R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45fcd762f60b60e56fe4bd937ac7950b">CAN_F3R2_FB17_Msk</a></td></tr>
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<tr class="separator:ga1637eff70416eb85d5d2a54e1f5d412e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa713ee3afe34a389483703fe9f8246da" id="r_gaa713ee3afe34a389483703fe9f8246da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa713ee3afe34a389483703fe9f8246da">CAN_F3R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga347cadef74e15229097c45f255cdeb8e" id="r_ga347cadef74e15229097c45f255cdeb8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga347cadef74e15229097c45f255cdeb8e">CAN_F3R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa713ee3afe34a389483703fe9f8246da">CAN_F3R2_FB18_Pos</a>)</td></tr>
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<tr class="memitem:ga7bbfdfa29b84ea60e67d41f775c6ffc6" id="r_ga7bbfdfa29b84ea60e67d41f775c6ffc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7bbfdfa29b84ea60e67d41f775c6ffc6">CAN_F3R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga347cadef74e15229097c45f255cdeb8e">CAN_F3R2_FB18_Msk</a></td></tr>
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<tr class="memitem:ga79eb2b7440516e0a76367dc2fa83bad5" id="r_ga79eb2b7440516e0a76367dc2fa83bad5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79eb2b7440516e0a76367dc2fa83bad5">CAN_F3R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="memitem:ga31404c72668cd4b409b16a1335a73dae" id="r_ga31404c72668cd4b409b16a1335a73dae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31404c72668cd4b409b16a1335a73dae">CAN_F3R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga79eb2b7440516e0a76367dc2fa83bad5">CAN_F3R2_FB19_Pos</a>)</td></tr>
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<tr class="memitem:ga827747e8cc66e4dcd22498c59e45c776" id="r_ga827747e8cc66e4dcd22498c59e45c776"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga827747e8cc66e4dcd22498c59e45c776">CAN_F3R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31404c72668cd4b409b16a1335a73dae">CAN_F3R2_FB19_Msk</a></td></tr>
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<tr class="separator:ga827747e8cc66e4dcd22498c59e45c776"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga464afddcd2bbd06df0bb2ee572a9cfd4" id="r_ga464afddcd2bbd06df0bb2ee572a9cfd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga464afddcd2bbd06df0bb2ee572a9cfd4">CAN_F3R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga464afddcd2bbd06df0bb2ee572a9cfd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd69af5b3822a2a480bb9041a8011074" id="r_gafd69af5b3822a2a480bb9041a8011074"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd69af5b3822a2a480bb9041a8011074">CAN_F3R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga464afddcd2bbd06df0bb2ee572a9cfd4">CAN_F3R2_FB20_Pos</a>)</td></tr>
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<tr class="separator:gafd69af5b3822a2a480bb9041a8011074"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe0bb6919615ec6311e8c39f62bca618" id="r_gabe0bb6919615ec6311e8c39f62bca618"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe0bb6919615ec6311e8c39f62bca618">CAN_F3R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafd69af5b3822a2a480bb9041a8011074">CAN_F3R2_FB20_Msk</a></td></tr>
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<tr class="separator:gabe0bb6919615ec6311e8c39f62bca618"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8770034c4717ac38141892bd84b23079" id="r_ga8770034c4717ac38141892bd84b23079"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8770034c4717ac38141892bd84b23079">CAN_F3R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga8770034c4717ac38141892bd84b23079"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab102b108170e7865f895d7ca6c40f12e" id="r_gab102b108170e7865f895d7ca6c40f12e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab102b108170e7865f895d7ca6c40f12e">CAN_F3R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8770034c4717ac38141892bd84b23079">CAN_F3R2_FB21_Pos</a>)</td></tr>
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<tr class="separator:gab102b108170e7865f895d7ca6c40f12e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c3e4716d3e52ec99451a942dceb59de" id="r_ga3c3e4716d3e52ec99451a942dceb59de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c3e4716d3e52ec99451a942dceb59de">CAN_F3R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab102b108170e7865f895d7ca6c40f12e">CAN_F3R2_FB21_Msk</a></td></tr>
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<tr class="separator:ga3c3e4716d3e52ec99451a942dceb59de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga033a69b00a00cef04f5526c727bad275" id="r_ga033a69b00a00cef04f5526c727bad275"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga033a69b00a00cef04f5526c727bad275">CAN_F3R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga033a69b00a00cef04f5526c727bad275"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22a42411bd3d2c7a7dc3e41bd40777ae" id="r_ga22a42411bd3d2c7a7dc3e41bd40777ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22a42411bd3d2c7a7dc3e41bd40777ae">CAN_F3R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga033a69b00a00cef04f5526c727bad275">CAN_F3R2_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga22a42411bd3d2c7a7dc3e41bd40777ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffefb44a948d36dcd94248f63aa68d2b" id="r_gaffefb44a948d36dcd94248f63aa68d2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffefb44a948d36dcd94248f63aa68d2b">CAN_F3R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga22a42411bd3d2c7a7dc3e41bd40777ae">CAN_F3R2_FB22_Msk</a></td></tr>
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<tr class="separator:gaffefb44a948d36dcd94248f63aa68d2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03beb9a7aeb8179ceed1d97083e28bbd" id="r_ga03beb9a7aeb8179ceed1d97083e28bbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03beb9a7aeb8179ceed1d97083e28bbd">CAN_F3R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga03beb9a7aeb8179ceed1d97083e28bbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5cae3507194258095f48d348f1307b0" id="r_gaf5cae3507194258095f48d348f1307b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5cae3507194258095f48d348f1307b0">CAN_F3R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga03beb9a7aeb8179ceed1d97083e28bbd">CAN_F3R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:gaf5cae3507194258095f48d348f1307b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79ce25d44a38f520b4a93384d6f5ac40" id="r_ga79ce25d44a38f520b4a93384d6f5ac40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79ce25d44a38f520b4a93384d6f5ac40">CAN_F3R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5cae3507194258095f48d348f1307b0">CAN_F3R2_FB23_Msk</a></td></tr>
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<tr class="separator:ga79ce25d44a38f520b4a93384d6f5ac40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7099835a0d2250cc0cbd274f7f4390ff" id="r_ga7099835a0d2250cc0cbd274f7f4390ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7099835a0d2250cc0cbd274f7f4390ff">CAN_F3R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga7099835a0d2250cc0cbd274f7f4390ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9218c367ef6f00e60b093f3f23a7a0b9" id="r_ga9218c367ef6f00e60b093f3f23a7a0b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9218c367ef6f00e60b093f3f23a7a0b9">CAN_F3R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7099835a0d2250cc0cbd274f7f4390ff">CAN_F3R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga9218c367ef6f00e60b093f3f23a7a0b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3fe1ced752dc811f9418181275c8c3fe" id="r_ga3fe1ced752dc811f9418181275c8c3fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3fe1ced752dc811f9418181275c8c3fe">CAN_F3R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9218c367ef6f00e60b093f3f23a7a0b9">CAN_F3R2_FB24_Msk</a></td></tr>
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<tr class="separator:ga3fe1ced752dc811f9418181275c8c3fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac02382c65073c2552fc97fae6cf64b23" id="r_gac02382c65073c2552fc97fae6cf64b23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac02382c65073c2552fc97fae6cf64b23">CAN_F3R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gac02382c65073c2552fc97fae6cf64b23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f46cde0b8517ab5b9625a614ea3d922" id="r_ga3f46cde0b8517ab5b9625a614ea3d922"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f46cde0b8517ab5b9625a614ea3d922">CAN_F3R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac02382c65073c2552fc97fae6cf64b23">CAN_F3R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga3f46cde0b8517ab5b9625a614ea3d922"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fb2f469246193f6fc9e4ade42192d28" id="r_ga9fb2f469246193f6fc9e4ade42192d28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fb2f469246193f6fc9e4ade42192d28">CAN_F3R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f46cde0b8517ab5b9625a614ea3d922">CAN_F3R2_FB25_Msk</a></td></tr>
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<tr class="separator:ga9fb2f469246193f6fc9e4ade42192d28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5cce1ce749c1341320ab27c5ccaf9c7" id="r_gae5cce1ce749c1341320ab27c5ccaf9c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5cce1ce749c1341320ab27c5ccaf9c7">CAN_F3R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:gae5cce1ce749c1341320ab27c5ccaf9c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab13acbfad9a6174945e4b814d2b3e5a8" id="r_gab13acbfad9a6174945e4b814d2b3e5a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab13acbfad9a6174945e4b814d2b3e5a8">CAN_F3R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5cce1ce749c1341320ab27c5ccaf9c7">CAN_F3R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:gab13acbfad9a6174945e4b814d2b3e5a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae85be7f7d7a9ddb8a60edb30d2a5727" id="r_gaae85be7f7d7a9ddb8a60edb30d2a5727"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae85be7f7d7a9ddb8a60edb30d2a5727">CAN_F3R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab13acbfad9a6174945e4b814d2b3e5a8">CAN_F3R2_FB26_Msk</a></td></tr>
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<tr class="separator:gaae85be7f7d7a9ddb8a60edb30d2a5727"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8bda0fbf28a49b2b7513f6d6810d9979" id="r_ga8bda0fbf28a49b2b7513f6d6810d9979"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8bda0fbf28a49b2b7513f6d6810d9979">CAN_F3R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga8bda0fbf28a49b2b7513f6d6810d9979"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb6f5115c365c1103bfb0c2e447de450" id="r_gaeb6f5115c365c1103bfb0c2e447de450"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb6f5115c365c1103bfb0c2e447de450">CAN_F3R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8bda0fbf28a49b2b7513f6d6810d9979">CAN_F3R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:gaeb6f5115c365c1103bfb0c2e447de450"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga850c21b26100c68b9cb57608c0249543" id="r_ga850c21b26100c68b9cb57608c0249543"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga850c21b26100c68b9cb57608c0249543">CAN_F3R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb6f5115c365c1103bfb0c2e447de450">CAN_F3R2_FB27_Msk</a></td></tr>
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<tr class="separator:ga850c21b26100c68b9cb57608c0249543"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77eba2b30abdf4a2a9b5ecb3f8616519" id="r_ga77eba2b30abdf4a2a9b5ecb3f8616519"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77eba2b30abdf4a2a9b5ecb3f8616519">CAN_F3R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga77eba2b30abdf4a2a9b5ecb3f8616519"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga969752803fe126111b3cd5149859c94e" id="r_ga969752803fe126111b3cd5149859c94e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga969752803fe126111b3cd5149859c94e">CAN_F3R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga77eba2b30abdf4a2a9b5ecb3f8616519">CAN_F3R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:ga969752803fe126111b3cd5149859c94e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82ec6ad2ad1b6115496adcb3e66fae25" id="r_ga82ec6ad2ad1b6115496adcb3e66fae25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82ec6ad2ad1b6115496adcb3e66fae25">CAN_F3R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga969752803fe126111b3cd5149859c94e">CAN_F3R2_FB28_Msk</a></td></tr>
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<tr class="separator:ga82ec6ad2ad1b6115496adcb3e66fae25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59cecf28681a17397c201f6ee9dc450f" id="r_ga59cecf28681a17397c201f6ee9dc450f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59cecf28681a17397c201f6ee9dc450f">CAN_F3R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga59cecf28681a17397c201f6ee9dc450f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83e06415202aa98552793b9fa28ee9a7" id="r_ga83e06415202aa98552793b9fa28ee9a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83e06415202aa98552793b9fa28ee9a7">CAN_F3R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga59cecf28681a17397c201f6ee9dc450f">CAN_F3R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:ga83e06415202aa98552793b9fa28ee9a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4fa34cc998edfdd1b3db93395ee6500" id="r_gaf4fa34cc998edfdd1b3db93395ee6500"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4fa34cc998edfdd1b3db93395ee6500">CAN_F3R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga83e06415202aa98552793b9fa28ee9a7">CAN_F3R2_FB29_Msk</a></td></tr>
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<tr class="memitem:ga0238173e08b65c4ddffb5f300616bbd5" id="r_ga0238173e08b65c4ddffb5f300616bbd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0238173e08b65c4ddffb5f300616bbd5">CAN_F3R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="memitem:ga367133e3ee7501aef9513944565cea6f" id="r_ga367133e3ee7501aef9513944565cea6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga367133e3ee7501aef9513944565cea6f">CAN_F3R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0238173e08b65c4ddffb5f300616bbd5">CAN_F3R2_FB30_Pos</a>)</td></tr>
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<tr class="memitem:ga7f4fea5ecec28e7f47647067b75cb24e" id="r_ga7f4fea5ecec28e7f47647067b75cb24e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f4fea5ecec28e7f47647067b75cb24e">CAN_F3R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga367133e3ee7501aef9513944565cea6f">CAN_F3R2_FB30_Msk</a></td></tr>
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<tr class="separator:ga7f4fea5ecec28e7f47647067b75cb24e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacda1d6cbc1ba76b6fbf6b69d5b805969" id="r_gacda1d6cbc1ba76b6fbf6b69d5b805969"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacda1d6cbc1ba76b6fbf6b69d5b805969">CAN_F3R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="memitem:ga994e84701ba2b7c21cdc7392a46e9d80" id="r_ga994e84701ba2b7c21cdc7392a46e9d80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga994e84701ba2b7c21cdc7392a46e9d80">CAN_F3R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacda1d6cbc1ba76b6fbf6b69d5b805969">CAN_F3R2_FB31_Pos</a>)</td></tr>
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<tr class="memitem:ga58a154f4d0cb787f23429b3f7cf70fd6" id="r_ga58a154f4d0cb787f23429b3f7cf70fd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58a154f4d0cb787f23429b3f7cf70fd6">CAN_F3R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga994e84701ba2b7c21cdc7392a46e9d80">CAN_F3R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga58a154f4d0cb787f23429b3f7cf70fd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1419ddd39b1b989b7bd57df584d40e93" id="r_ga1419ddd39b1b989b7bd57df584d40e93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1419ddd39b1b989b7bd57df584d40e93">CAN_F4R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga1419ddd39b1b989b7bd57df584d40e93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f9048515e8f37041f6aff9999aff569" id="r_ga0f9048515e8f37041f6aff9999aff569"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f9048515e8f37041f6aff9999aff569">CAN_F4R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1419ddd39b1b989b7bd57df584d40e93">CAN_F4R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga0f9048515e8f37041f6aff9999aff569"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97250d3eed2504846f39c50dce71c9d0" id="r_ga97250d3eed2504846f39c50dce71c9d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97250d3eed2504846f39c50dce71c9d0">CAN_F4R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f9048515e8f37041f6aff9999aff569">CAN_F4R2_FB0_Msk</a></td></tr>
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<tr class="separator:ga97250d3eed2504846f39c50dce71c9d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga960af74ce166416ac55bc7c945adaec8" id="r_ga960af74ce166416ac55bc7c945adaec8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga960af74ce166416ac55bc7c945adaec8">CAN_F4R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga960af74ce166416ac55bc7c945adaec8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63b07509549c3a1b2559040dd01c9a0e" id="r_ga63b07509549c3a1b2559040dd01c9a0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63b07509549c3a1b2559040dd01c9a0e">CAN_F4R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga960af74ce166416ac55bc7c945adaec8">CAN_F4R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga63b07509549c3a1b2559040dd01c9a0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga145e11678ee6062df5164894ad8f80b1" id="r_ga145e11678ee6062df5164894ad8f80b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga145e11678ee6062df5164894ad8f80b1">CAN_F4R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63b07509549c3a1b2559040dd01c9a0e">CAN_F4R2_FB1_Msk</a></td></tr>
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<tr class="separator:ga145e11678ee6062df5164894ad8f80b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b9fe6bf1b80f4cc053b9e9f8bddb224" id="r_ga6b9fe6bf1b80f4cc053b9e9f8bddb224"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b9fe6bf1b80f4cc053b9e9f8bddb224">CAN_F4R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga6b9fe6bf1b80f4cc053b9e9f8bddb224"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f84ea90801ae445733a36c8f10ec608" id="r_ga5f84ea90801ae445733a36c8f10ec608"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f84ea90801ae445733a36c8f10ec608">CAN_F4R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b9fe6bf1b80f4cc053b9e9f8bddb224">CAN_F4R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga5f84ea90801ae445733a36c8f10ec608"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d19193baf5412ec2e38822d062196b8" id="r_ga9d19193baf5412ec2e38822d062196b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d19193baf5412ec2e38822d062196b8">CAN_F4R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f84ea90801ae445733a36c8f10ec608">CAN_F4R2_FB2_Msk</a></td></tr>
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<tr class="separator:ga9d19193baf5412ec2e38822d062196b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81bfbead828bc1a65eee77e210a82107" id="r_ga81bfbead828bc1a65eee77e210a82107"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81bfbead828bc1a65eee77e210a82107">CAN_F4R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga81bfbead828bc1a65eee77e210a82107"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c4fe680c0484c7757d15d939a50e8b1" id="r_ga4c4fe680c0484c7757d15d939a50e8b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c4fe680c0484c7757d15d939a50e8b1">CAN_F4R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga81bfbead828bc1a65eee77e210a82107">CAN_F4R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga4c4fe680c0484c7757d15d939a50e8b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94b8b1428b640932aced6446f8b41f83" id="r_ga94b8b1428b640932aced6446f8b41f83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94b8b1428b640932aced6446f8b41f83">CAN_F4R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c4fe680c0484c7757d15d939a50e8b1">CAN_F4R2_FB3_Msk</a></td></tr>
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<tr class="separator:ga94b8b1428b640932aced6446f8b41f83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84bb4ceedefb72e55d9b84543e1e7996" id="r_ga84bb4ceedefb72e55d9b84543e1e7996"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84bb4ceedefb72e55d9b84543e1e7996">CAN_F4R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga84bb4ceedefb72e55d9b84543e1e7996"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91056080450f8e5f68b3120ed7b609fb" id="r_ga91056080450f8e5f68b3120ed7b609fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91056080450f8e5f68b3120ed7b609fb">CAN_F4R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84bb4ceedefb72e55d9b84543e1e7996">CAN_F4R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga91056080450f8e5f68b3120ed7b609fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93164ec00412eb5eed168e8a30557f25" id="r_ga93164ec00412eb5eed168e8a30557f25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93164ec00412eb5eed168e8a30557f25">CAN_F4R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga91056080450f8e5f68b3120ed7b609fb">CAN_F4R2_FB4_Msk</a></td></tr>
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<tr class="separator:ga93164ec00412eb5eed168e8a30557f25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74b468294e8df41868bf3c06bdf481bd" id="r_ga74b468294e8df41868bf3c06bdf481bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74b468294e8df41868bf3c06bdf481bd">CAN_F4R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga74b468294e8df41868bf3c06bdf481bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96484b04cb3e058e3f70b722713990dc" id="r_ga96484b04cb3e058e3f70b722713990dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96484b04cb3e058e3f70b722713990dc">CAN_F4R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga74b468294e8df41868bf3c06bdf481bd">CAN_F4R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga96484b04cb3e058e3f70b722713990dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04e44c5a14e44c20f3b81044a915db13" id="r_ga04e44c5a14e44c20f3b81044a915db13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04e44c5a14e44c20f3b81044a915db13">CAN_F4R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga96484b04cb3e058e3f70b722713990dc">CAN_F4R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga04e44c5a14e44c20f3b81044a915db13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad305c1f3555c0dc3ccdf8da5bc775504" id="r_gad305c1f3555c0dc3ccdf8da5bc775504"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad305c1f3555c0dc3ccdf8da5bc775504">CAN_F4R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gad305c1f3555c0dc3ccdf8da5bc775504"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacde7359de773b8b427dddca91f99a3c2" id="r_gacde7359de773b8b427dddca91f99a3c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacde7359de773b8b427dddca91f99a3c2">CAN_F4R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad305c1f3555c0dc3ccdf8da5bc775504">CAN_F4R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:gacde7359de773b8b427dddca91f99a3c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37e57dec99c33f462a2dbb6273df2f57" id="r_ga37e57dec99c33f462a2dbb6273df2f57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37e57dec99c33f462a2dbb6273df2f57">CAN_F4R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacde7359de773b8b427dddca91f99a3c2">CAN_F4R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga37e57dec99c33f462a2dbb6273df2f57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74a2c4a85e2ced48f8e8c14e28e8a527" id="r_ga74a2c4a85e2ced48f8e8c14e28e8a527"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74a2c4a85e2ced48f8e8c14e28e8a527">CAN_F4R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga74a2c4a85e2ced48f8e8c14e28e8a527"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87bfab19292dba8c2e7c6f6d366f1490" id="r_ga87bfab19292dba8c2e7c6f6d366f1490"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87bfab19292dba8c2e7c6f6d366f1490">CAN_F4R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga74a2c4a85e2ced48f8e8c14e28e8a527">CAN_F4R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga87bfab19292dba8c2e7c6f6d366f1490"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6c7d3ec0375e356192583142f7fccca" id="r_gaf6c7d3ec0375e356192583142f7fccca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6c7d3ec0375e356192583142f7fccca">CAN_F4R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga87bfab19292dba8c2e7c6f6d366f1490">CAN_F4R2_FB7_Msk</a></td></tr>
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<tr class="separator:gaf6c7d3ec0375e356192583142f7fccca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0e0dd86f16cceefbb63044d48a7f4ae" id="r_gaf0e0dd86f16cceefbb63044d48a7f4ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0e0dd86f16cceefbb63044d48a7f4ae">CAN_F4R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaf0e0dd86f16cceefbb63044d48a7f4ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad82667269e283535191eb3439f4ad6a2" id="r_gad82667269e283535191eb3439f4ad6a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad82667269e283535191eb3439f4ad6a2">CAN_F4R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0e0dd86f16cceefbb63044d48a7f4ae">CAN_F4R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:gad82667269e283535191eb3439f4ad6a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad33f7d788aea161826a86bc2c5567450" id="r_gad33f7d788aea161826a86bc2c5567450"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad33f7d788aea161826a86bc2c5567450">CAN_F4R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad82667269e283535191eb3439f4ad6a2">CAN_F4R2_FB8_Msk</a></td></tr>
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<tr class="separator:gad33f7d788aea161826a86bc2c5567450"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad6bc30c3c453102c6ff321a9b74ff94" id="r_gaad6bc30c3c453102c6ff321a9b74ff94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad6bc30c3c453102c6ff321a9b74ff94">CAN_F4R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaad6bc30c3c453102c6ff321a9b74ff94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae060ee50f1193b9e8a2b2ad84789eed7" id="r_gae060ee50f1193b9e8a2b2ad84789eed7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae060ee50f1193b9e8a2b2ad84789eed7">CAN_F4R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaad6bc30c3c453102c6ff321a9b74ff94">CAN_F4R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:gae060ee50f1193b9e8a2b2ad84789eed7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab998448b0bd20ff6384c26ad9e6baaf" id="r_gaab998448b0bd20ff6384c26ad9e6baaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab998448b0bd20ff6384c26ad9e6baaf">CAN_F4R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae060ee50f1193b9e8a2b2ad84789eed7">CAN_F4R2_FB9_Msk</a></td></tr>
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<tr class="separator:gaab998448b0bd20ff6384c26ad9e6baaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30c085eaa270c21b83fb471ae334e59f" id="r_ga30c085eaa270c21b83fb471ae334e59f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30c085eaa270c21b83fb471ae334e59f">CAN_F4R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga30c085eaa270c21b83fb471ae334e59f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3152ad433d216935b86e5014dd69626e" id="r_ga3152ad433d216935b86e5014dd69626e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3152ad433d216935b86e5014dd69626e">CAN_F4R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30c085eaa270c21b83fb471ae334e59f">CAN_F4R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga3152ad433d216935b86e5014dd69626e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8794112fcbb0dca0c7d0316ac8725e8" id="r_gad8794112fcbb0dca0c7d0316ac8725e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8794112fcbb0dca0c7d0316ac8725e8">CAN_F4R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3152ad433d216935b86e5014dd69626e">CAN_F4R2_FB10_Msk</a></td></tr>
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<tr class="separator:gad8794112fcbb0dca0c7d0316ac8725e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a4b0466c13c7c8259301cd2f23cc8de" id="r_ga0a4b0466c13c7c8259301cd2f23cc8de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a4b0466c13c7c8259301cd2f23cc8de">CAN_F4R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga0a4b0466c13c7c8259301cd2f23cc8de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabc14b1315fea6d9b3948d9f00f07de7" id="r_gaabc14b1315fea6d9b3948d9f00f07de7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabc14b1315fea6d9b3948d9f00f07de7">CAN_F4R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a4b0466c13c7c8259301cd2f23cc8de">CAN_F4R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:gaabc14b1315fea6d9b3948d9f00f07de7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d22e782a9ca087f99ab9f53b2626aed" id="r_ga0d22e782a9ca087f99ab9f53b2626aed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d22e782a9ca087f99ab9f53b2626aed">CAN_F4R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaabc14b1315fea6d9b3948d9f00f07de7">CAN_F4R2_FB11_Msk</a></td></tr>
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<tr class="separator:ga0d22e782a9ca087f99ab9f53b2626aed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e89e50734d1ff90c8246f14bcb4d83a" id="r_ga6e89e50734d1ff90c8246f14bcb4d83a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e89e50734d1ff90c8246f14bcb4d83a">CAN_F4R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga6e89e50734d1ff90c8246f14bcb4d83a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8d1eae74bfd099a0512f44a4bd928c9" id="r_gaa8d1eae74bfd099a0512f44a4bd928c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8d1eae74bfd099a0512f44a4bd928c9">CAN_F4R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e89e50734d1ff90c8246f14bcb4d83a">CAN_F4R2_FB12_Pos</a>)</td></tr>
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<tr class="separator:gaa8d1eae74bfd099a0512f44a4bd928c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa8d5c2635a62bdfa6e3a5a12b127fc8" id="r_gaaa8d5c2635a62bdfa6e3a5a12b127fc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa8d5c2635a62bdfa6e3a5a12b127fc8">CAN_F4R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8d1eae74bfd099a0512f44a4bd928c9">CAN_F4R2_FB12_Msk</a></td></tr>
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<tr class="separator:gaaa8d5c2635a62bdfa6e3a5a12b127fc8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7394fbd307de3a0701d41b984658940" id="r_gae7394fbd307de3a0701d41b984658940"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7394fbd307de3a0701d41b984658940">CAN_F4R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga6ad9d3c7bbf0cf276350b00a04b43c37" id="r_ga6ad9d3c7bbf0cf276350b00a04b43c37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad9d3c7bbf0cf276350b00a04b43c37">CAN_F4R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae7394fbd307de3a0701d41b984658940">CAN_F4R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga6ad9d3c7bbf0cf276350b00a04b43c37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad491689799985f0c8f17b270cd8873c4" id="r_gad491689799985f0c8f17b270cd8873c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad491689799985f0c8f17b270cd8873c4">CAN_F4R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad9d3c7bbf0cf276350b00a04b43c37">CAN_F4R2_FB13_Msk</a></td></tr>
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<tr class="separator:gad491689799985f0c8f17b270cd8873c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedcf4b945f92674309ef9535166dc473" id="r_gaedcf4b945f92674309ef9535166dc473"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedcf4b945f92674309ef9535166dc473">CAN_F4R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gaedcf4b945f92674309ef9535166dc473"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31079d3271fc34363eed112cb9a3ed23" id="r_ga31079d3271fc34363eed112cb9a3ed23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31079d3271fc34363eed112cb9a3ed23">CAN_F4R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaedcf4b945f92674309ef9535166dc473">CAN_F4R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:ga31079d3271fc34363eed112cb9a3ed23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1b80d40d87204de4687735de852f47f" id="r_gab1b80d40d87204de4687735de852f47f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1b80d40d87204de4687735de852f47f">CAN_F4R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31079d3271fc34363eed112cb9a3ed23">CAN_F4R2_FB14_Msk</a></td></tr>
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<tr class="separator:gab1b80d40d87204de4687735de852f47f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc517c539daa4ed10cd59739b5eac588" id="r_gadc517c539daa4ed10cd59739b5eac588"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc517c539daa4ed10cd59739b5eac588">CAN_F4R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gadc517c539daa4ed10cd59739b5eac588"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd57e61b87f3e1e9632ad2075732fa5a" id="r_gacd57e61b87f3e1e9632ad2075732fa5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd57e61b87f3e1e9632ad2075732fa5a">CAN_F4R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadc517c539daa4ed10cd59739b5eac588">CAN_F4R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:gacd57e61b87f3e1e9632ad2075732fa5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0994b341ba8a73b950f01d83d012780d" id="r_ga0994b341ba8a73b950f01d83d012780d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0994b341ba8a73b950f01d83d012780d">CAN_F4R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacd57e61b87f3e1e9632ad2075732fa5a">CAN_F4R2_FB15_Msk</a></td></tr>
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<tr class="separator:ga0994b341ba8a73b950f01d83d012780d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f7127ca82dc78b93a37e7cf80a5ceb8" id="r_ga3f7127ca82dc78b93a37e7cf80a5ceb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f7127ca82dc78b93a37e7cf80a5ceb8">CAN_F4R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga3f7127ca82dc78b93a37e7cf80a5ceb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac24f6b4c83f05dfbd05e15c128ad6fbf" id="r_gac24f6b4c83f05dfbd05e15c128ad6fbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac24f6b4c83f05dfbd05e15c128ad6fbf">CAN_F4R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f7127ca82dc78b93a37e7cf80a5ceb8">CAN_F4R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:gac24f6b4c83f05dfbd05e15c128ad6fbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ae8b77d791ba7403618989a77e62922" id="r_ga6ae8b77d791ba7403618989a77e62922"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ae8b77d791ba7403618989a77e62922">CAN_F4R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac24f6b4c83f05dfbd05e15c128ad6fbf">CAN_F4R2_FB16_Msk</a></td></tr>
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<tr class="separator:ga6ae8b77d791ba7403618989a77e62922"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0189abc764580a8777fff47521d38303" id="r_ga0189abc764580a8777fff47521d38303"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0189abc764580a8777fff47521d38303">CAN_F4R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga0189abc764580a8777fff47521d38303"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga973be88ab5b27952acbdb24e0b817d78" id="r_ga973be88ab5b27952acbdb24e0b817d78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga973be88ab5b27952acbdb24e0b817d78">CAN_F4R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0189abc764580a8777fff47521d38303">CAN_F4R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga973be88ab5b27952acbdb24e0b817d78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc116988117a7e7fabc722855351d257" id="r_gabc116988117a7e7fabc722855351d257"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc116988117a7e7fabc722855351d257">CAN_F4R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga973be88ab5b27952acbdb24e0b817d78">CAN_F4R2_FB17_Msk</a></td></tr>
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<tr class="separator:gabc116988117a7e7fabc722855351d257"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad6a2d9360b2d898f9f52098f68ea290" id="r_gaad6a2d9360b2d898f9f52098f68ea290"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad6a2d9360b2d898f9f52098f68ea290">CAN_F4R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:gaad6a2d9360b2d898f9f52098f68ea290"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf85749ab4396b250aac41526571cecf3" id="r_gaf85749ab4396b250aac41526571cecf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf85749ab4396b250aac41526571cecf3">CAN_F4R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaad6a2d9360b2d898f9f52098f68ea290">CAN_F4R2_FB18_Pos</a>)</td></tr>
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<tr class="separator:gaf85749ab4396b250aac41526571cecf3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07b1fc6ee0dc4cc892d69ed496b59007" id="r_ga07b1fc6ee0dc4cc892d69ed496b59007"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07b1fc6ee0dc4cc892d69ed496b59007">CAN_F4R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf85749ab4396b250aac41526571cecf3">CAN_F4R2_FB18_Msk</a></td></tr>
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<tr class="separator:ga07b1fc6ee0dc4cc892d69ed496b59007"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga610320557b86dc3210d49af3a2ff476b" id="r_ga610320557b86dc3210d49af3a2ff476b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga610320557b86dc3210d49af3a2ff476b">CAN_F4R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga610320557b86dc3210d49af3a2ff476b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab74002038e0de0bebc00117c89343be6" id="r_gab74002038e0de0bebc00117c89343be6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab74002038e0de0bebc00117c89343be6">CAN_F4R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga610320557b86dc3210d49af3a2ff476b">CAN_F4R2_FB19_Pos</a>)</td></tr>
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<tr class="memitem:gaa58785812f0d3e73a657426b81f0b78b" id="r_gaa58785812f0d3e73a657426b81f0b78b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa58785812f0d3e73a657426b81f0b78b">CAN_F4R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab74002038e0de0bebc00117c89343be6">CAN_F4R2_FB19_Msk</a></td></tr>
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<tr class="memitem:ga338e34091813fe910437c7f4b07f4a15" id="r_ga338e34091813fe910437c7f4b07f4a15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga338e34091813fe910437c7f4b07f4a15">CAN_F4R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga814015c75ef6ae829af165ba84aa7692" id="r_ga814015c75ef6ae829af165ba84aa7692"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga814015c75ef6ae829af165ba84aa7692">CAN_F4R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga338e34091813fe910437c7f4b07f4a15">CAN_F4R2_FB20_Pos</a>)</td></tr>
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<tr class="memitem:ga363da353073d7ee6421cf171688ef52b" id="r_ga363da353073d7ee6421cf171688ef52b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga363da353073d7ee6421cf171688ef52b">CAN_F4R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga814015c75ef6ae829af165ba84aa7692">CAN_F4R2_FB20_Msk</a></td></tr>
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<tr class="memitem:gab3b436d0a50503f95b84d596659fb1a4" id="r_gab3b436d0a50503f95b84d596659fb1a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3b436d0a50503f95b84d596659fb1a4">CAN_F4R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gab3b436d0a50503f95b84d596659fb1a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7d83298755e6833a20617ab15f8712d" id="r_gac7d83298755e6833a20617ab15f8712d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7d83298755e6833a20617ab15f8712d">CAN_F4R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3b436d0a50503f95b84d596659fb1a4">CAN_F4R2_FB21_Pos</a>)</td></tr>
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<tr class="memitem:ga4f22695359aa9a1b07763aef44a9a1c4" id="r_ga4f22695359aa9a1b07763aef44a9a1c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f22695359aa9a1b07763aef44a9a1c4">CAN_F4R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac7d83298755e6833a20617ab15f8712d">CAN_F4R2_FB21_Msk</a></td></tr>
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<tr class="separator:ga4f22695359aa9a1b07763aef44a9a1c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2906d67400ef4a87ffb17a1f26d6ae7b" id="r_ga2906d67400ef4a87ffb17a1f26d6ae7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2906d67400ef4a87ffb17a1f26d6ae7b">CAN_F4R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga2906d67400ef4a87ffb17a1f26d6ae7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac94ecf7d43f6a018320c3d25bc9b46c2" id="r_gac94ecf7d43f6a018320c3d25bc9b46c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac94ecf7d43f6a018320c3d25bc9b46c2">CAN_F4R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2906d67400ef4a87ffb17a1f26d6ae7b">CAN_F4R2_FB22_Pos</a>)</td></tr>
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<tr class="memitem:gac0f8c1ef382225198407474f2b7fa073" id="r_gac0f8c1ef382225198407474f2b7fa073"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0f8c1ef382225198407474f2b7fa073">CAN_F4R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac94ecf7d43f6a018320c3d25bc9b46c2">CAN_F4R2_FB22_Msk</a></td></tr>
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<tr class="memitem:gaa3b071adef809e00edf9cb9d891d6d44" id="r_gaa3b071adef809e00edf9cb9d891d6d44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3b071adef809e00edf9cb9d891d6d44">CAN_F4R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gaa3b071adef809e00edf9cb9d891d6d44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55e657b91bf8789bccd4f52b8f865b2d" id="r_ga55e657b91bf8789bccd4f52b8f865b2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55e657b91bf8789bccd4f52b8f865b2d">CAN_F4R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3b071adef809e00edf9cb9d891d6d44">CAN_F4R2_FB23_Pos</a>)</td></tr>
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<tr class="memitem:ga9476c54044db3182ee789e9df1d1aa19" id="r_ga9476c54044db3182ee789e9df1d1aa19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9476c54044db3182ee789e9df1d1aa19">CAN_F4R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga55e657b91bf8789bccd4f52b8f865b2d">CAN_F4R2_FB23_Msk</a></td></tr>
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<tr class="separator:ga9476c54044db3182ee789e9df1d1aa19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5da4e3d58f6f15b8c756e0bb38be4cc4" id="r_ga5da4e3d58f6f15b8c756e0bb38be4cc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5da4e3d58f6f15b8c756e0bb38be4cc4">CAN_F4R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga5da4e3d58f6f15b8c756e0bb38be4cc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1696522c0eecd85f864be345e40a29ea" id="r_ga1696522c0eecd85f864be345e40a29ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1696522c0eecd85f864be345e40a29ea">CAN_F4R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5da4e3d58f6f15b8c756e0bb38be4cc4">CAN_F4R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga1696522c0eecd85f864be345e40a29ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73158a3669d2ef96db84e4f196d040bf" id="r_ga73158a3669d2ef96db84e4f196d040bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73158a3669d2ef96db84e4f196d040bf">CAN_F4R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1696522c0eecd85f864be345e40a29ea">CAN_F4R2_FB24_Msk</a></td></tr>
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<tr class="memitem:ga4f7d61b349c5bca004c6af7eaaee0a05" id="r_ga4f7d61b349c5bca004c6af7eaaee0a05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f7d61b349c5bca004c6af7eaaee0a05">CAN_F4R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga4f7d61b349c5bca004c6af7eaaee0a05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92bfc25c457c753a6e6635781a348471" id="r_ga92bfc25c457c753a6e6635781a348471"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92bfc25c457c753a6e6635781a348471">CAN_F4R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f7d61b349c5bca004c6af7eaaee0a05">CAN_F4R2_FB25_Pos</a>)</td></tr>
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<tr class="memitem:ga17d36fcf8e08c76597a7b2c05e831f98" id="r_ga17d36fcf8e08c76597a7b2c05e831f98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17d36fcf8e08c76597a7b2c05e831f98">CAN_F4R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga92bfc25c457c753a6e6635781a348471">CAN_F4R2_FB25_Msk</a></td></tr>
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<tr class="memitem:ga6ad5b4c8debdf28b0c25c49b678ea058" id="r_ga6ad5b4c8debdf28b0c25c49b678ea058"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad5b4c8debdf28b0c25c49b678ea058">CAN_F4R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga6ad5b4c8debdf28b0c25c49b678ea058"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03b9b82299251b22f45b8ead71dc2675" id="r_ga03b9b82299251b22f45b8ead71dc2675"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03b9b82299251b22f45b8ead71dc2675">CAN_F4R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad5b4c8debdf28b0c25c49b678ea058">CAN_F4R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga03b9b82299251b22f45b8ead71dc2675"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa683635426f418ead45032c25e0179ee" id="r_gaa683635426f418ead45032c25e0179ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa683635426f418ead45032c25e0179ee">CAN_F4R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga03b9b82299251b22f45b8ead71dc2675">CAN_F4R2_FB26_Msk</a></td></tr>
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<tr class="memitem:gacaf248d9dc1f65a0536fa18819437aea" id="r_gacaf248d9dc1f65a0536fa18819437aea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacaf248d9dc1f65a0536fa18819437aea">CAN_F4R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:gacaf248d9dc1f65a0536fa18819437aea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9295be11108120ae840e8c0f12f0ed5" id="r_gad9295be11108120ae840e8c0f12f0ed5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9295be11108120ae840e8c0f12f0ed5">CAN_F4R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacaf248d9dc1f65a0536fa18819437aea">CAN_F4R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:gad9295be11108120ae840e8c0f12f0ed5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23c77145ea84805a785b49c0a7f31774" id="r_ga23c77145ea84805a785b49c0a7f31774"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23c77145ea84805a785b49c0a7f31774">CAN_F4R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad9295be11108120ae840e8c0f12f0ed5">CAN_F4R2_FB27_Msk</a></td></tr>
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<tr class="separator:ga23c77145ea84805a785b49c0a7f31774"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga380250b4976a40ee70fbe9f86f566de1" id="r_ga380250b4976a40ee70fbe9f86f566de1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga380250b4976a40ee70fbe9f86f566de1">CAN_F4R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga380250b4976a40ee70fbe9f86f566de1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9d7545d55253cd33e9bc8a186692071" id="r_gad9d7545d55253cd33e9bc8a186692071"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9d7545d55253cd33e9bc8a186692071">CAN_F4R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga380250b4976a40ee70fbe9f86f566de1">CAN_F4R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:gad9d7545d55253cd33e9bc8a186692071"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18492e954ec07174a1b140104062f941" id="r_ga18492e954ec07174a1b140104062f941"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18492e954ec07174a1b140104062f941">CAN_F4R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad9d7545d55253cd33e9bc8a186692071">CAN_F4R2_FB28_Msk</a></td></tr>
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<tr class="separator:ga18492e954ec07174a1b140104062f941"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98aa4a050c05406a714f4046fc7e7461" id="r_ga98aa4a050c05406a714f4046fc7e7461"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98aa4a050c05406a714f4046fc7e7461">CAN_F4R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga98aa4a050c05406a714f4046fc7e7461"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9db3158da58bb55ec0b8e038214bf57c" id="r_ga9db3158da58bb55ec0b8e038214bf57c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9db3158da58bb55ec0b8e038214bf57c">CAN_F4R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98aa4a050c05406a714f4046fc7e7461">CAN_F4R2_FB29_Pos</a>)</td></tr>
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<tr class="memitem:gaaf94626a8450c20e241ad6298660ec23" id="r_gaaf94626a8450c20e241ad6298660ec23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf94626a8450c20e241ad6298660ec23">CAN_F4R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9db3158da58bb55ec0b8e038214bf57c">CAN_F4R2_FB29_Msk</a></td></tr>
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<tr class="memitem:ga1c597a7985c16b24ef4cca5c0a14e60b" id="r_ga1c597a7985c16b24ef4cca5c0a14e60b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c597a7985c16b24ef4cca5c0a14e60b">CAN_F4R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="memitem:ga172377c09e98ed68359ffe7bb49f556c" id="r_ga172377c09e98ed68359ffe7bb49f556c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga172377c09e98ed68359ffe7bb49f556c">CAN_F4R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c597a7985c16b24ef4cca5c0a14e60b">CAN_F4R2_FB30_Pos</a>)</td></tr>
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<tr class="memitem:ga4d7da9aa234705aff3ddc9845b1589d4" id="r_ga4d7da9aa234705aff3ddc9845b1589d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d7da9aa234705aff3ddc9845b1589d4">CAN_F4R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga172377c09e98ed68359ffe7bb49f556c">CAN_F4R2_FB30_Msk</a></td></tr>
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<tr class="separator:ga4d7da9aa234705aff3ddc9845b1589d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43fc86c148a9c62cf94e0c4b1827b4ad" id="r_ga43fc86c148a9c62cf94e0c4b1827b4ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43fc86c148a9c62cf94e0c4b1827b4ad">CAN_F4R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga43fc86c148a9c62cf94e0c4b1827b4ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a9da9f03b531cb1019a2a401e9177d6" id="r_ga1a9da9f03b531cb1019a2a401e9177d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a9da9f03b531cb1019a2a401e9177d6">CAN_F4R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga43fc86c148a9c62cf94e0c4b1827b4ad">CAN_F4R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga1a9da9f03b531cb1019a2a401e9177d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70293ff8a71e353d84a3da134eb427d9" id="r_ga70293ff8a71e353d84a3da134eb427d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70293ff8a71e353d84a3da134eb427d9">CAN_F4R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a9da9f03b531cb1019a2a401e9177d6">CAN_F4R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga70293ff8a71e353d84a3da134eb427d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31ac96e599e5acbc734ad3ae742ba942" id="r_ga31ac96e599e5acbc734ad3ae742ba942"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31ac96e599e5acbc734ad3ae742ba942">CAN_F5R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga31ac96e599e5acbc734ad3ae742ba942"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab01f1756425341377c80a011da4cfcb1" id="r_gab01f1756425341377c80a011da4cfcb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab01f1756425341377c80a011da4cfcb1">CAN_F5R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga31ac96e599e5acbc734ad3ae742ba942">CAN_F5R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:gab01f1756425341377c80a011da4cfcb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17b264aaa84a3c6ab5a35014eb5dfb09" id="r_ga17b264aaa84a3c6ab5a35014eb5dfb09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17b264aaa84a3c6ab5a35014eb5dfb09">CAN_F5R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab01f1756425341377c80a011da4cfcb1">CAN_F5R2_FB0_Msk</a></td></tr>
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<tr class="separator:ga17b264aaa84a3c6ab5a35014eb5dfb09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf76834e934a1e6431cc7d604747050e1" id="r_gaf76834e934a1e6431cc7d604747050e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf76834e934a1e6431cc7d604747050e1">CAN_F5R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaf76834e934a1e6431cc7d604747050e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa669537bb8f8adf60f0d40d76f5d9fb9" id="r_gaa669537bb8f8adf60f0d40d76f5d9fb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa669537bb8f8adf60f0d40d76f5d9fb9">CAN_F5R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf76834e934a1e6431cc7d604747050e1">CAN_F5R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:gaa669537bb8f8adf60f0d40d76f5d9fb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa871f5bc692996efc8c1bad1d08b43c5" id="r_gaa871f5bc692996efc8c1bad1d08b43c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa871f5bc692996efc8c1bad1d08b43c5">CAN_F5R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa669537bb8f8adf60f0d40d76f5d9fb9">CAN_F5R2_FB1_Msk</a></td></tr>
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<tr class="separator:gaa871f5bc692996efc8c1bad1d08b43c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8245d1c94d1b1b37f88fbb8361d0995" id="r_gab8245d1c94d1b1b37f88fbb8361d0995"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8245d1c94d1b1b37f88fbb8361d0995">CAN_F5R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gab8245d1c94d1b1b37f88fbb8361d0995"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa81eadbcd56cc52d9c0b7435ba5b40e9" id="r_gaa81eadbcd56cc52d9c0b7435ba5b40e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa81eadbcd56cc52d9c0b7435ba5b40e9">CAN_F5R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8245d1c94d1b1b37f88fbb8361d0995">CAN_F5R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:gaa81eadbcd56cc52d9c0b7435ba5b40e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf44a72156023a5889a1c22d77e188e2e" id="r_gaf44a72156023a5889a1c22d77e188e2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf44a72156023a5889a1c22d77e188e2e">CAN_F5R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa81eadbcd56cc52d9c0b7435ba5b40e9">CAN_F5R2_FB2_Msk</a></td></tr>
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<tr class="separator:gaf44a72156023a5889a1c22d77e188e2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53e88ec5a445a1a06d1106bb8d306ef6" id="r_ga53e88ec5a445a1a06d1106bb8d306ef6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53e88ec5a445a1a06d1106bb8d306ef6">CAN_F5R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga53e88ec5a445a1a06d1106bb8d306ef6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4271ce693ee149054334055f32083514" id="r_ga4271ce693ee149054334055f32083514"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4271ce693ee149054334055f32083514">CAN_F5R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga53e88ec5a445a1a06d1106bb8d306ef6">CAN_F5R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga4271ce693ee149054334055f32083514"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d8828885a79299bc65c2011f71240e2" id="r_ga3d8828885a79299bc65c2011f71240e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d8828885a79299bc65c2011f71240e2">CAN_F5R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4271ce693ee149054334055f32083514">CAN_F5R2_FB3_Msk</a></td></tr>
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<tr class="separator:ga3d8828885a79299bc65c2011f71240e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4516eaeaa55e303db71ed3ae9babff88" id="r_ga4516eaeaa55e303db71ed3ae9babff88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4516eaeaa55e303db71ed3ae9babff88">CAN_F5R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga4516eaeaa55e303db71ed3ae9babff88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4dd49575e4657b373fd5cdc67067e0d" id="r_gac4dd49575e4657b373fd5cdc67067e0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4dd49575e4657b373fd5cdc67067e0d">CAN_F5R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4516eaeaa55e303db71ed3ae9babff88">CAN_F5R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:gac4dd49575e4657b373fd5cdc67067e0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadfa978108927c827e3021499a20d0372" id="r_gadfa978108927c827e3021499a20d0372"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfa978108927c827e3021499a20d0372">CAN_F5R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4dd49575e4657b373fd5cdc67067e0d">CAN_F5R2_FB4_Msk</a></td></tr>
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<tr class="separator:gadfa978108927c827e3021499a20d0372"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4cd2ba17430db1908a126f95f8b3811" id="r_gaa4cd2ba17430db1908a126f95f8b3811"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4cd2ba17430db1908a126f95f8b3811">CAN_F5R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaa4cd2ba17430db1908a126f95f8b3811"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac14329fcf8b7c680e02b7967e8cb98ea" id="r_gac14329fcf8b7c680e02b7967e8cb98ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac14329fcf8b7c680e02b7967e8cb98ea">CAN_F5R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4cd2ba17430db1908a126f95f8b3811">CAN_F5R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:gac14329fcf8b7c680e02b7967e8cb98ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3b3c48011935170a9bd120b724030fe" id="r_gaf3b3c48011935170a9bd120b724030fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3b3c48011935170a9bd120b724030fe">CAN_F5R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac14329fcf8b7c680e02b7967e8cb98ea">CAN_F5R2_FB5_Msk</a></td></tr>
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<tr class="separator:gaf3b3c48011935170a9bd120b724030fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9c07be713f85a6784c934880b47fac6" id="r_gab9c07be713f85a6784c934880b47fac6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9c07be713f85a6784c934880b47fac6">CAN_F5R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gab9c07be713f85a6784c934880b47fac6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga119d967c2b9dff5291f892ed55650722" id="r_ga119d967c2b9dff5291f892ed55650722"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga119d967c2b9dff5291f892ed55650722">CAN_F5R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9c07be713f85a6784c934880b47fac6">CAN_F5R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga119d967c2b9dff5291f892ed55650722"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56cf7f6d0bf48847f3d8f72777774e58" id="r_ga56cf7f6d0bf48847f3d8f72777774e58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56cf7f6d0bf48847f3d8f72777774e58">CAN_F5R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga119d967c2b9dff5291f892ed55650722">CAN_F5R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga56cf7f6d0bf48847f3d8f72777774e58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0853bd11144bb38e99488b1bb31899a" id="r_gaa0853bd11144bb38e99488b1bb31899a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0853bd11144bb38e99488b1bb31899a">CAN_F5R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaa0853bd11144bb38e99488b1bb31899a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae72af802de3283727835678b4d783b7e" id="r_gae72af802de3283727835678b4d783b7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae72af802de3283727835678b4d783b7e">CAN_F5R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0853bd11144bb38e99488b1bb31899a">CAN_F5R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:gae72af802de3283727835678b4d783b7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cb8a5551d90c8d79b09b4d82f3f59c2" id="r_ga2cb8a5551d90c8d79b09b4d82f3f59c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cb8a5551d90c8d79b09b4d82f3f59c2">CAN_F5R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae72af802de3283727835678b4d783b7e">CAN_F5R2_FB7_Msk</a></td></tr>
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<tr class="separator:ga2cb8a5551d90c8d79b09b4d82f3f59c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafef8fdd804993ad8b9cbce7223f888c8" id="r_gafef8fdd804993ad8b9cbce7223f888c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafef8fdd804993ad8b9cbce7223f888c8">CAN_F5R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gafef8fdd804993ad8b9cbce7223f888c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa770d4e9ecd17918854fc97a3d96bdfd" id="r_gaa770d4e9ecd17918854fc97a3d96bdfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa770d4e9ecd17918854fc97a3d96bdfd">CAN_F5R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafef8fdd804993ad8b9cbce7223f888c8">CAN_F5R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:gaa770d4e9ecd17918854fc97a3d96bdfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga423b7b77bfd5dd6791f1b1dd16e9807a" id="r_ga423b7b77bfd5dd6791f1b1dd16e9807a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga423b7b77bfd5dd6791f1b1dd16e9807a">CAN_F5R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa770d4e9ecd17918854fc97a3d96bdfd">CAN_F5R2_FB8_Msk</a></td></tr>
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<tr class="separator:ga423b7b77bfd5dd6791f1b1dd16e9807a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6eed4d57ced26b73f1b76bdfbabfe980" id="r_ga6eed4d57ced26b73f1b76bdfbabfe980"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6eed4d57ced26b73f1b76bdfbabfe980">CAN_F5R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="memitem:gab4d4e4451476d46716de06cef008beb1" id="r_gab4d4e4451476d46716de06cef008beb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4d4e4451476d46716de06cef008beb1">CAN_F5R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6eed4d57ced26b73f1b76bdfbabfe980">CAN_F5R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:gab4d4e4451476d46716de06cef008beb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c50420a128a70341e63ad23b0bedba5" id="r_ga9c50420a128a70341e63ad23b0bedba5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c50420a128a70341e63ad23b0bedba5">CAN_F5R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab4d4e4451476d46716de06cef008beb1">CAN_F5R2_FB9_Msk</a></td></tr>
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<tr class="separator:ga9c50420a128a70341e63ad23b0bedba5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef3f52dc2809f93b4bc777b1ef062556" id="r_gaef3f52dc2809f93b4bc777b1ef062556"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef3f52dc2809f93b4bc777b1ef062556">CAN_F5R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaef3f52dc2809f93b4bc777b1ef062556"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga860f7fadc560b00fe1878226c9a847be" id="r_ga860f7fadc560b00fe1878226c9a847be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga860f7fadc560b00fe1878226c9a847be">CAN_F5R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef3f52dc2809f93b4bc777b1ef062556">CAN_F5R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga860f7fadc560b00fe1878226c9a847be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga392844657c800d2e16e7916ed5fb9891" id="r_ga392844657c800d2e16e7916ed5fb9891"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga392844657c800d2e16e7916ed5fb9891">CAN_F5R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga860f7fadc560b00fe1878226c9a847be">CAN_F5R2_FB10_Msk</a></td></tr>
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<tr class="separator:ga392844657c800d2e16e7916ed5fb9891"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga998e4248e08394cf031b6d25a909a654" id="r_ga998e4248e08394cf031b6d25a909a654"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga998e4248e08394cf031b6d25a909a654">CAN_F5R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga998e4248e08394cf031b6d25a909a654"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3cf1650e026cc5bb83c111dc8e9ce5e" id="r_gab3cf1650e026cc5bb83c111dc8e9ce5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf1650e026cc5bb83c111dc8e9ce5e">CAN_F5R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga998e4248e08394cf031b6d25a909a654">CAN_F5R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:gab3cf1650e026cc5bb83c111dc8e9ce5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb35a3bbc447c46929643115490e250d" id="r_gabb35a3bbc447c46929643115490e250d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb35a3bbc447c46929643115490e250d">CAN_F5R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf1650e026cc5bb83c111dc8e9ce5e">CAN_F5R2_FB11_Msk</a></td></tr>
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<tr class="separator:gabb35a3bbc447c46929643115490e250d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bf1445ca1ebcf7eed420cf412e07f05" id="r_ga1bf1445ca1ebcf7eed420cf412e07f05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bf1445ca1ebcf7eed420cf412e07f05">CAN_F5R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga1bf1445ca1ebcf7eed420cf412e07f05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed02925c42bc722b25c350bc00ec815f" id="r_gaed02925c42bc722b25c350bc00ec815f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed02925c42bc722b25c350bc00ec815f">CAN_F5R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1bf1445ca1ebcf7eed420cf412e07f05">CAN_F5R2_FB12_Pos</a>)</td></tr>
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<tr class="separator:gaed02925c42bc722b25c350bc00ec815f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga974bae58f9819eee0377d709c985bcbe" id="r_ga974bae58f9819eee0377d709c985bcbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga974bae58f9819eee0377d709c985bcbe">CAN_F5R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaed02925c42bc722b25c350bc00ec815f">CAN_F5R2_FB12_Msk</a></td></tr>
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<tr class="separator:ga974bae58f9819eee0377d709c985bcbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80ab623333a37c66175f1b9b239cce27" id="r_ga80ab623333a37c66175f1b9b239cce27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80ab623333a37c66175f1b9b239cce27">CAN_F5R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga80ab623333a37c66175f1b9b239cce27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6a2dbe8f45f7a844a2dd0dcf07786d6" id="r_gaf6a2dbe8f45f7a844a2dd0dcf07786d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6a2dbe8f45f7a844a2dd0dcf07786d6">CAN_F5R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80ab623333a37c66175f1b9b239cce27">CAN_F5R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:gaf6a2dbe8f45f7a844a2dd0dcf07786d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2823bb25e138cc52d11b154456947ab7" id="r_ga2823bb25e138cc52d11b154456947ab7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2823bb25e138cc52d11b154456947ab7">CAN_F5R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6a2dbe8f45f7a844a2dd0dcf07786d6">CAN_F5R2_FB13_Msk</a></td></tr>
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<tr class="separator:ga2823bb25e138cc52d11b154456947ab7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga019a3a59115f5994ef92a14ea8373bef" id="r_ga019a3a59115f5994ef92a14ea8373bef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga019a3a59115f5994ef92a14ea8373bef">CAN_F5R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga019a3a59115f5994ef92a14ea8373bef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6d471b7cf1edcabeba6eb8af6a2ca83" id="r_gac6d471b7cf1edcabeba6eb8af6a2ca83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6d471b7cf1edcabeba6eb8af6a2ca83">CAN_F5R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga019a3a59115f5994ef92a14ea8373bef">CAN_F5R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:gac6d471b7cf1edcabeba6eb8af6a2ca83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98cf223bdcc1a106f7573b57f836f9ed" id="r_ga98cf223bdcc1a106f7573b57f836f9ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98cf223bdcc1a106f7573b57f836f9ed">CAN_F5R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac6d471b7cf1edcabeba6eb8af6a2ca83">CAN_F5R2_FB14_Msk</a></td></tr>
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<tr class="separator:ga98cf223bdcc1a106f7573b57f836f9ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9dac6309c6bf54e66e6fdae4771190ad" id="r_ga9dac6309c6bf54e66e6fdae4771190ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9dac6309c6bf54e66e6fdae4771190ad">CAN_F5R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga9dac6309c6bf54e66e6fdae4771190ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3dde50a6686b9be1d26d3d855e85f7c" id="r_gab3dde50a6686b9be1d26d3d855e85f7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3dde50a6686b9be1d26d3d855e85f7c">CAN_F5R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9dac6309c6bf54e66e6fdae4771190ad">CAN_F5R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:gab3dde50a6686b9be1d26d3d855e85f7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26bfd14720495dd180f1524f2fdb3743" id="r_ga26bfd14720495dd180f1524f2fdb3743"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26bfd14720495dd180f1524f2fdb3743">CAN_F5R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab3dde50a6686b9be1d26d3d855e85f7c">CAN_F5R2_FB15_Msk</a></td></tr>
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<tr class="separator:ga26bfd14720495dd180f1524f2fdb3743"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f6cb58d414c1819c65d080328db8044" id="r_ga2f6cb58d414c1819c65d080328db8044"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f6cb58d414c1819c65d080328db8044">CAN_F5R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga2f6cb58d414c1819c65d080328db8044"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ee326307cb31cf3cc82c36765a14f5f" id="r_ga0ee326307cb31cf3cc82c36765a14f5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ee326307cb31cf3cc82c36765a14f5f">CAN_F5R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f6cb58d414c1819c65d080328db8044">CAN_F5R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga0ee326307cb31cf3cc82c36765a14f5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41b457c721dc855d05b2f353c22a83a7" id="r_ga41b457c721dc855d05b2f353c22a83a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41b457c721dc855d05b2f353c22a83a7">CAN_F5R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ee326307cb31cf3cc82c36765a14f5f">CAN_F5R2_FB16_Msk</a></td></tr>
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<tr class="separator:ga41b457c721dc855d05b2f353c22a83a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5c8011137b67c4ad3a51b1139a3e0ed" id="r_gaf5c8011137b67c4ad3a51b1139a3e0ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5c8011137b67c4ad3a51b1139a3e0ed">CAN_F5R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gaf5c8011137b67c4ad3a51b1139a3e0ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4d64f35fb861a436083a675a4d55087" id="r_gae4d64f35fb861a436083a675a4d55087"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4d64f35fb861a436083a675a4d55087">CAN_F5R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5c8011137b67c4ad3a51b1139a3e0ed">CAN_F5R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:gae4d64f35fb861a436083a675a4d55087"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bc89534aaf3f810a2151b04b0086717" id="r_ga1bc89534aaf3f810a2151b04b0086717"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc89534aaf3f810a2151b04b0086717">CAN_F5R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae4d64f35fb861a436083a675a4d55087">CAN_F5R2_FB17_Msk</a></td></tr>
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<tr class="separator:ga1bc89534aaf3f810a2151b04b0086717"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96dcca6b4fa2e2cf12ffe3af72a1b679" id="r_ga96dcca6b4fa2e2cf12ffe3af72a1b679"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96dcca6b4fa2e2cf12ffe3af72a1b679">CAN_F5R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga96dcca6b4fa2e2cf12ffe3af72a1b679"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae05e7364c82e1f610e927785ec039d6a" id="r_gae05e7364c82e1f610e927785ec039d6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae05e7364c82e1f610e927785ec039d6a">CAN_F5R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96dcca6b4fa2e2cf12ffe3af72a1b679">CAN_F5R2_FB18_Pos</a>)</td></tr>
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<tr class="separator:gae05e7364c82e1f610e927785ec039d6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga070940536728fad3c0e5336926131b4b" id="r_ga070940536728fad3c0e5336926131b4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga070940536728fad3c0e5336926131b4b">CAN_F5R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae05e7364c82e1f610e927785ec039d6a">CAN_F5R2_FB18_Msk</a></td></tr>
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<tr class="separator:ga070940536728fad3c0e5336926131b4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60046c4ebf351deeaf74223758d53675" id="r_ga60046c4ebf351deeaf74223758d53675"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60046c4ebf351deeaf74223758d53675">CAN_F5R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga60046c4ebf351deeaf74223758d53675"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac707fb2bec18e9152234fc5c58b5cbc9" id="r_gac707fb2bec18e9152234fc5c58b5cbc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac707fb2bec18e9152234fc5c58b5cbc9">CAN_F5R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga60046c4ebf351deeaf74223758d53675">CAN_F5R2_FB19_Pos</a>)</td></tr>
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<tr class="separator:gac707fb2bec18e9152234fc5c58b5cbc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaddf2e4aa8107150a86d37ce03a0e1c0e" id="r_gaddf2e4aa8107150a86d37ce03a0e1c0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddf2e4aa8107150a86d37ce03a0e1c0e">CAN_F5R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac707fb2bec18e9152234fc5c58b5cbc9">CAN_F5R2_FB19_Msk</a></td></tr>
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<tr class="memitem:gae3ae858c989b3736de3373c42fac5775" id="r_gae3ae858c989b3736de3373c42fac5775"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3ae858c989b3736de3373c42fac5775">CAN_F5R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga543013c958dcfd0719772fcea3ec7442" id="r_ga543013c958dcfd0719772fcea3ec7442"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga543013c958dcfd0719772fcea3ec7442">CAN_F5R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3ae858c989b3736de3373c42fac5775">CAN_F5R2_FB20_Pos</a>)</td></tr>
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<tr class="memitem:ga1788704faad47f1d45017df41a35f053" id="r_ga1788704faad47f1d45017df41a35f053"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1788704faad47f1d45017df41a35f053">CAN_F5R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga543013c958dcfd0719772fcea3ec7442">CAN_F5R2_FB20_Msk</a></td></tr>
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<tr class="separator:ga1788704faad47f1d45017df41a35f053"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb635f8a3ff310a99ae6ef459d681ac6" id="r_gafb635f8a3ff310a99ae6ef459d681ac6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb635f8a3ff310a99ae6ef459d681ac6">CAN_F5R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="memitem:gab64136662c15ae221d5a0c1a5dd54b08" id="r_gab64136662c15ae221d5a0c1a5dd54b08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab64136662c15ae221d5a0c1a5dd54b08">CAN_F5R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafb635f8a3ff310a99ae6ef459d681ac6">CAN_F5R2_FB21_Pos</a>)</td></tr>
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<tr class="separator:gab64136662c15ae221d5a0c1a5dd54b08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11c4aeffb6646643c412e19e6f5cc015" id="r_ga11c4aeffb6646643c412e19e6f5cc015"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11c4aeffb6646643c412e19e6f5cc015">CAN_F5R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab64136662c15ae221d5a0c1a5dd54b08">CAN_F5R2_FB21_Msk</a></td></tr>
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<tr class="separator:ga11c4aeffb6646643c412e19e6f5cc015"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga684958cea52e6120dcdc40a55c1442e2" id="r_ga684958cea52e6120dcdc40a55c1442e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga684958cea52e6120dcdc40a55c1442e2">CAN_F5R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga684958cea52e6120dcdc40a55c1442e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61b1a77cc46c59213948b974f622090d" id="r_ga61b1a77cc46c59213948b974f622090d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61b1a77cc46c59213948b974f622090d">CAN_F5R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga684958cea52e6120dcdc40a55c1442e2">CAN_F5R2_FB22_Pos</a>)</td></tr>
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<tr class="memitem:gaef348c2d37f96f5e5324368f90c80d42" id="r_gaef348c2d37f96f5e5324368f90c80d42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef348c2d37f96f5e5324368f90c80d42">CAN_F5R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga61b1a77cc46c59213948b974f622090d">CAN_F5R2_FB22_Msk</a></td></tr>
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<tr class="separator:gaef348c2d37f96f5e5324368f90c80d42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8ecdc64db223884f8a2a539045a52a2" id="r_gaa8ecdc64db223884f8a2a539045a52a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8ecdc64db223884f8a2a539045a52a2">CAN_F5R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gaa8ecdc64db223884f8a2a539045a52a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99c053ca550685ca82a4068cb35dcf1e" id="r_ga99c053ca550685ca82a4068cb35dcf1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99c053ca550685ca82a4068cb35dcf1e">CAN_F5R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8ecdc64db223884f8a2a539045a52a2">CAN_F5R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga99c053ca550685ca82a4068cb35dcf1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga398d842cfcb2d441d999e1407fc54f83" id="r_ga398d842cfcb2d441d999e1407fc54f83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga398d842cfcb2d441d999e1407fc54f83">CAN_F5R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga99c053ca550685ca82a4068cb35dcf1e">CAN_F5R2_FB23_Msk</a></td></tr>
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<tr class="memitem:gab98edeba8a885855d8ab39e4da3b2a23" id="r_gab98edeba8a885855d8ab39e4da3b2a23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab98edeba8a885855d8ab39e4da3b2a23">CAN_F5R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:gab98edeba8a885855d8ab39e4da3b2a23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95a78f8f2aa15cad8513b89355533e9c" id="r_ga95a78f8f2aa15cad8513b89355533e9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95a78f8f2aa15cad8513b89355533e9c">CAN_F5R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab98edeba8a885855d8ab39e4da3b2a23">CAN_F5R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga95a78f8f2aa15cad8513b89355533e9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6575f8d4d154e2e8342b3f88352a9d52" id="r_ga6575f8d4d154e2e8342b3f88352a9d52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6575f8d4d154e2e8342b3f88352a9d52">CAN_F5R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga95a78f8f2aa15cad8513b89355533e9c">CAN_F5R2_FB24_Msk</a></td></tr>
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<tr class="separator:ga6575f8d4d154e2e8342b3f88352a9d52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a4842fb46f7a105bbd49413c6eee911" id="r_ga0a4842fb46f7a105bbd49413c6eee911"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a4842fb46f7a105bbd49413c6eee911">CAN_F5R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga0a4842fb46f7a105bbd49413c6eee911"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga008957461f388566b56639ecbc17cebb" id="r_ga008957461f388566b56639ecbc17cebb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga008957461f388566b56639ecbc17cebb">CAN_F5R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a4842fb46f7a105bbd49413c6eee911">CAN_F5R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga008957461f388566b56639ecbc17cebb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9e6ad77b1d8ac7303e920658aceb354" id="r_gae9e6ad77b1d8ac7303e920658aceb354"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9e6ad77b1d8ac7303e920658aceb354">CAN_F5R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga008957461f388566b56639ecbc17cebb">CAN_F5R2_FB25_Msk</a></td></tr>
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<tr class="separator:gae9e6ad77b1d8ac7303e920658aceb354"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7170d32e10c78e3fc54d039496f53506" id="r_ga7170d32e10c78e3fc54d039496f53506"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7170d32e10c78e3fc54d039496f53506">CAN_F5R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga7170d32e10c78e3fc54d039496f53506"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga933f9591f9dd20f70ba06053f261fac2" id="r_ga933f9591f9dd20f70ba06053f261fac2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga933f9591f9dd20f70ba06053f261fac2">CAN_F5R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7170d32e10c78e3fc54d039496f53506">CAN_F5R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga933f9591f9dd20f70ba06053f261fac2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga911ade78e30d1a037d35dda5eb7cbd4b" id="r_ga911ade78e30d1a037d35dda5eb7cbd4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga911ade78e30d1a037d35dda5eb7cbd4b">CAN_F5R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga933f9591f9dd20f70ba06053f261fac2">CAN_F5R2_FB26_Msk</a></td></tr>
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<tr class="separator:ga911ade78e30d1a037d35dda5eb7cbd4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36212c15d8fb9e6fd90221aa199ce898" id="r_ga36212c15d8fb9e6fd90221aa199ce898"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36212c15d8fb9e6fd90221aa199ce898">CAN_F5R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga36212c15d8fb9e6fd90221aa199ce898"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb9d77aef830c128d7c7582c5b05799b" id="r_gadb9d77aef830c128d7c7582c5b05799b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb9d77aef830c128d7c7582c5b05799b">CAN_F5R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga36212c15d8fb9e6fd90221aa199ce898">CAN_F5R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:gadb9d77aef830c128d7c7582c5b05799b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49542b9334bc4917e25d6808c78787d1" id="r_ga49542b9334bc4917e25d6808c78787d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49542b9334bc4917e25d6808c78787d1">CAN_F5R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadb9d77aef830c128d7c7582c5b05799b">CAN_F5R2_FB27_Msk</a></td></tr>
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<tr class="separator:ga49542b9334bc4917e25d6808c78787d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe87106ef6da9830afb1aa98c5e65823" id="r_gafe87106ef6da9830afb1aa98c5e65823"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe87106ef6da9830afb1aa98c5e65823">CAN_F5R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:gafe87106ef6da9830afb1aa98c5e65823"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28c9aaa77d535cf3323afecae54f2014" id="r_ga28c9aaa77d535cf3323afecae54f2014"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28c9aaa77d535cf3323afecae54f2014">CAN_F5R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafe87106ef6da9830afb1aa98c5e65823">CAN_F5R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:ga28c9aaa77d535cf3323afecae54f2014"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga255da64f4a66ff888f6633d6e51658c6" id="r_ga255da64f4a66ff888f6633d6e51658c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga255da64f4a66ff888f6633d6e51658c6">CAN_F5R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga28c9aaa77d535cf3323afecae54f2014">CAN_F5R2_FB28_Msk</a></td></tr>
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<tr class="separator:ga255da64f4a66ff888f6633d6e51658c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae96aac0fb32c68c6803fa56115592c4d" id="r_gae96aac0fb32c68c6803fa56115592c4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae96aac0fb32c68c6803fa56115592c4d">CAN_F5R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:gae96aac0fb32c68c6803fa56115592c4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3a0ff1fd4b5ea4e84e5ef7c11553ac6" id="r_gae3a0ff1fd4b5ea4e84e5ef7c11553ac6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3a0ff1fd4b5ea4e84e5ef7c11553ac6">CAN_F5R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae96aac0fb32c68c6803fa56115592c4d">CAN_F5R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:gae3a0ff1fd4b5ea4e84e5ef7c11553ac6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8335d23f9fd156f40dc7fd63ba6783cb" id="r_ga8335d23f9fd156f40dc7fd63ba6783cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8335d23f9fd156f40dc7fd63ba6783cb">CAN_F5R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3a0ff1fd4b5ea4e84e5ef7c11553ac6">CAN_F5R2_FB29_Msk</a></td></tr>
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<tr class="separator:ga8335d23f9fd156f40dc7fd63ba6783cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e488b1f7932407cda7b439bf69df464" id="r_ga1e488b1f7932407cda7b439bf69df464"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e488b1f7932407cda7b439bf69df464">CAN_F5R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga1e488b1f7932407cda7b439bf69df464"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3d4abd59ef329e2a4cdacd80450b71e" id="r_gae3d4abd59ef329e2a4cdacd80450b71e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3d4abd59ef329e2a4cdacd80450b71e">CAN_F5R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e488b1f7932407cda7b439bf69df464">CAN_F5R2_FB30_Pos</a>)</td></tr>
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<tr class="separator:gae3d4abd59ef329e2a4cdacd80450b71e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf81786b7519b39f705729de2c55e4faa" id="r_gaf81786b7519b39f705729de2c55e4faa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf81786b7519b39f705729de2c55e4faa">CAN_F5R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3d4abd59ef329e2a4cdacd80450b71e">CAN_F5R2_FB30_Msk</a></td></tr>
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<tr class="memitem:gabb423f7f26c55460925e1d1a7e5a073d" id="r_gabb423f7f26c55460925e1d1a7e5a073d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb423f7f26c55460925e1d1a7e5a073d">CAN_F5R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:gabb423f7f26c55460925e1d1a7e5a073d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga872287cb1dc75d841a74fef1df7d04c4" id="r_ga872287cb1dc75d841a74fef1df7d04c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga872287cb1dc75d841a74fef1df7d04c4">CAN_F5R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb423f7f26c55460925e1d1a7e5a073d">CAN_F5R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga872287cb1dc75d841a74fef1df7d04c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f7122b0ad8cb4fc1797d0dbecbb4a05" id="r_ga4f7122b0ad8cb4fc1797d0dbecbb4a05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f7122b0ad8cb4fc1797d0dbecbb4a05">CAN_F5R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga872287cb1dc75d841a74fef1df7d04c4">CAN_F5R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga4f7122b0ad8cb4fc1797d0dbecbb4a05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20cc3ea8010fbf026315233056de5b0d" id="r_ga20cc3ea8010fbf026315233056de5b0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20cc3ea8010fbf026315233056de5b0d">CAN_F6R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga20cc3ea8010fbf026315233056de5b0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f57610bbf8a5efd029417aae54d4bbb" id="r_ga3f57610bbf8a5efd029417aae54d4bbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f57610bbf8a5efd029417aae54d4bbb">CAN_F6R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20cc3ea8010fbf026315233056de5b0d">CAN_F6R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga3f57610bbf8a5efd029417aae54d4bbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71ad6452660daed3d6c436533a25efc2" id="r_ga71ad6452660daed3d6c436533a25efc2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71ad6452660daed3d6c436533a25efc2">CAN_F6R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f57610bbf8a5efd029417aae54d4bbb">CAN_F6R2_FB0_Msk</a></td></tr>
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<tr class="separator:ga71ad6452660daed3d6c436533a25efc2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57ea3c021bd5598a314a2dc310b2c242" id="r_ga57ea3c021bd5598a314a2dc310b2c242"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57ea3c021bd5598a314a2dc310b2c242">CAN_F6R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga57ea3c021bd5598a314a2dc310b2c242"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b30db0682c6a7847de91680b2532808" id="r_ga6b30db0682c6a7847de91680b2532808"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b30db0682c6a7847de91680b2532808">CAN_F6R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57ea3c021bd5598a314a2dc310b2c242">CAN_F6R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga6b30db0682c6a7847de91680b2532808"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9e24abd8d2f0775661415b6565f4f6d" id="r_gac9e24abd8d2f0775661415b6565f4f6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9e24abd8d2f0775661415b6565f4f6d">CAN_F6R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b30db0682c6a7847de91680b2532808">CAN_F6R2_FB1_Msk</a></td></tr>
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<tr class="separator:gac9e24abd8d2f0775661415b6565f4f6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb418d7998996d8fbbbe6a7f9f81a6d3" id="r_gadb418d7998996d8fbbbe6a7f9f81a6d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb418d7998996d8fbbbe6a7f9f81a6d3">CAN_F6R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gadb418d7998996d8fbbbe6a7f9f81a6d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa901630470057df2e214f14994a714aa" id="r_gaa901630470057df2e214f14994a714aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa901630470057df2e214f14994a714aa">CAN_F6R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb418d7998996d8fbbbe6a7f9f81a6d3">CAN_F6R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:gaa901630470057df2e214f14994a714aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6dc3f6ce4dde435743aadbe17cc78b9" id="r_gaf6dc3f6ce4dde435743aadbe17cc78b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6dc3f6ce4dde435743aadbe17cc78b9">CAN_F6R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa901630470057df2e214f14994a714aa">CAN_F6R2_FB2_Msk</a></td></tr>
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<tr class="separator:gaf6dc3f6ce4dde435743aadbe17cc78b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a70af83c83018fdb987a9121ef6bba7" id="r_ga2a70af83c83018fdb987a9121ef6bba7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a70af83c83018fdb987a9121ef6bba7">CAN_F6R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga2a70af83c83018fdb987a9121ef6bba7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0d1bbfb93db519a92310ca7074289e7" id="r_gaa0d1bbfb93db519a92310ca7074289e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0d1bbfb93db519a92310ca7074289e7">CAN_F6R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a70af83c83018fdb987a9121ef6bba7">CAN_F6R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:gaa0d1bbfb93db519a92310ca7074289e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1f5163490dffe1f4d7c635458359c2f" id="r_gae1f5163490dffe1f4d7c635458359c2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1f5163490dffe1f4d7c635458359c2f">CAN_F6R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0d1bbfb93db519a92310ca7074289e7">CAN_F6R2_FB3_Msk</a></td></tr>
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<tr class="separator:gae1f5163490dffe1f4d7c635458359c2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaff0bb055714dfce4422592cc05805c2" id="r_gaaff0bb055714dfce4422592cc05805c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaff0bb055714dfce4422592cc05805c2">CAN_F6R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaaff0bb055714dfce4422592cc05805c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga747c01d82b012765a96bf20ae2d1e614" id="r_ga747c01d82b012765a96bf20ae2d1e614"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga747c01d82b012765a96bf20ae2d1e614">CAN_F6R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaff0bb055714dfce4422592cc05805c2">CAN_F6R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga747c01d82b012765a96bf20ae2d1e614"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89e9191d214d05f4d90fbcd38daa73e1" id="r_ga89e9191d214d05f4d90fbcd38daa73e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89e9191d214d05f4d90fbcd38daa73e1">CAN_F6R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga747c01d82b012765a96bf20ae2d1e614">CAN_F6R2_FB4_Msk</a></td></tr>
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<tr class="separator:ga89e9191d214d05f4d90fbcd38daa73e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69724e09645446cfec63ef3720f3424e" id="r_ga69724e09645446cfec63ef3720f3424e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69724e09645446cfec63ef3720f3424e">CAN_F6R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga69724e09645446cfec63ef3720f3424e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga731205c17b0265b0aed17e7335d665f1" id="r_ga731205c17b0265b0aed17e7335d665f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga731205c17b0265b0aed17e7335d665f1">CAN_F6R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69724e09645446cfec63ef3720f3424e">CAN_F6R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga731205c17b0265b0aed17e7335d665f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97d29588281c546d98e09760cc5ef593" id="r_ga97d29588281c546d98e09760cc5ef593"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97d29588281c546d98e09760cc5ef593">CAN_F6R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga731205c17b0265b0aed17e7335d665f1">CAN_F6R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga97d29588281c546d98e09760cc5ef593"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cee5f9332b40105e0594c546910a2e2" id="r_ga3cee5f9332b40105e0594c546910a2e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cee5f9332b40105e0594c546910a2e2">CAN_F6R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga3cee5f9332b40105e0594c546910a2e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab107baf898c53eca495a0cec40383c4a" id="r_gab107baf898c53eca495a0cec40383c4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab107baf898c53eca495a0cec40383c4a">CAN_F6R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cee5f9332b40105e0594c546910a2e2">CAN_F6R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:gab107baf898c53eca495a0cec40383c4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53f5717aca9932255049b133661765bf" id="r_ga53f5717aca9932255049b133661765bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53f5717aca9932255049b133661765bf">CAN_F6R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab107baf898c53eca495a0cec40383c4a">CAN_F6R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga53f5717aca9932255049b133661765bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4ca498cfaea259d91ac4f15692a3bcc" id="r_gac4ca498cfaea259d91ac4f15692a3bcc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4ca498cfaea259d91ac4f15692a3bcc">CAN_F6R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gac4ca498cfaea259d91ac4f15692a3bcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacec3cbdfadb57b83f4a10629f5ff93a6" id="r_gacec3cbdfadb57b83f4a10629f5ff93a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacec3cbdfadb57b83f4a10629f5ff93a6">CAN_F6R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4ca498cfaea259d91ac4f15692a3bcc">CAN_F6R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:gacec3cbdfadb57b83f4a10629f5ff93a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ec93958e936379d891bc3450dba3d1d" id="r_ga7ec93958e936379d891bc3450dba3d1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ec93958e936379d891bc3450dba3d1d">CAN_F6R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacec3cbdfadb57b83f4a10629f5ff93a6">CAN_F6R2_FB7_Msk</a></td></tr>
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<tr class="separator:ga7ec93958e936379d891bc3450dba3d1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f8b7c262d5a1e51c7cd479cf7a47719" id="r_ga3f8b7c262d5a1e51c7cd479cf7a47719"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f8b7c262d5a1e51c7cd479cf7a47719">CAN_F6R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga3f8b7c262d5a1e51c7cd479cf7a47719"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaecb8cf6a22127fde7bbef7da331362fa" id="r_gaecb8cf6a22127fde7bbef7da331362fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecb8cf6a22127fde7bbef7da331362fa">CAN_F6R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f8b7c262d5a1e51c7cd479cf7a47719">CAN_F6R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:gaecb8cf6a22127fde7bbef7da331362fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f97c7eb9d6e69d589db38d745ae321c" id="r_ga8f97c7eb9d6e69d589db38d745ae321c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f97c7eb9d6e69d589db38d745ae321c">CAN_F6R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaecb8cf6a22127fde7bbef7da331362fa">CAN_F6R2_FB8_Msk</a></td></tr>
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<tr class="separator:ga8f97c7eb9d6e69d589db38d745ae321c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2541190f9817b863fcaea7925a9ab152" id="r_ga2541190f9817b863fcaea7925a9ab152"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2541190f9817b863fcaea7925a9ab152">CAN_F6R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga2541190f9817b863fcaea7925a9ab152"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1625345e2205b59ee47e4522833a023f" id="r_ga1625345e2205b59ee47e4522833a023f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1625345e2205b59ee47e4522833a023f">CAN_F6R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2541190f9817b863fcaea7925a9ab152">CAN_F6R2_FB9_Pos</a>)</td></tr>
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<tr class="memitem:ga372ebb5d42d147d41688f7c0fcf467d2" id="r_ga372ebb5d42d147d41688f7c0fcf467d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga372ebb5d42d147d41688f7c0fcf467d2">CAN_F6R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1625345e2205b59ee47e4522833a023f">CAN_F6R2_FB9_Msk</a></td></tr>
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<tr class="separator:ga372ebb5d42d147d41688f7c0fcf467d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga681ae7ccefdd04ea0b9fac2b6d8ce2c7" id="r_ga681ae7ccefdd04ea0b9fac2b6d8ce2c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga681ae7ccefdd04ea0b9fac2b6d8ce2c7">CAN_F6R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga681ae7ccefdd04ea0b9fac2b6d8ce2c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6ee3ac5a1ecd2c3e5a1805bbcfe6611" id="r_gaf6ee3ac5a1ecd2c3e5a1805bbcfe6611"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6ee3ac5a1ecd2c3e5a1805bbcfe6611">CAN_F6R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga681ae7ccefdd04ea0b9fac2b6d8ce2c7">CAN_F6R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:gaf6ee3ac5a1ecd2c3e5a1805bbcfe6611"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47baa2c9c05c7c422a49994b8f80016f" id="r_ga47baa2c9c05c7c422a49994b8f80016f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47baa2c9c05c7c422a49994b8f80016f">CAN_F6R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6ee3ac5a1ecd2c3e5a1805bbcfe6611">CAN_F6R2_FB10_Msk</a></td></tr>
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<tr class="separator:ga47baa2c9c05c7c422a49994b8f80016f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a088bdcb4c43b019ccc2916cefc597c" id="r_ga9a088bdcb4c43b019ccc2916cefc597c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a088bdcb4c43b019ccc2916cefc597c">CAN_F6R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga9a088bdcb4c43b019ccc2916cefc597c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacbaa9f91a1fc5474ecf6e149dbd309d" id="r_gaacbaa9f91a1fc5474ecf6e149dbd309d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacbaa9f91a1fc5474ecf6e149dbd309d">CAN_F6R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a088bdcb4c43b019ccc2916cefc597c">CAN_F6R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:gaacbaa9f91a1fc5474ecf6e149dbd309d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55d7665b118e98586c2a9b1900ce7292" id="r_ga55d7665b118e98586c2a9b1900ce7292"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55d7665b118e98586c2a9b1900ce7292">CAN_F6R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaacbaa9f91a1fc5474ecf6e149dbd309d">CAN_F6R2_FB11_Msk</a></td></tr>
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<tr class="separator:ga55d7665b118e98586c2a9b1900ce7292"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1041051f130d6cccb3b866a899bbd865" id="r_ga1041051f130d6cccb3b866a899bbd865"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1041051f130d6cccb3b866a899bbd865">CAN_F6R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga1041051f130d6cccb3b866a899bbd865"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7899cda2b27c9f78f33a3050f975a22" id="r_gaf7899cda2b27c9f78f33a3050f975a22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7899cda2b27c9f78f33a3050f975a22">CAN_F6R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1041051f130d6cccb3b866a899bbd865">CAN_F6R2_FB12_Pos</a>)</td></tr>
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<tr class="separator:gaf7899cda2b27c9f78f33a3050f975a22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5095a203d07244e75dd6deca125b4468" id="r_ga5095a203d07244e75dd6deca125b4468"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5095a203d07244e75dd6deca125b4468">CAN_F6R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7899cda2b27c9f78f33a3050f975a22">CAN_F6R2_FB12_Msk</a></td></tr>
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<tr class="separator:ga5095a203d07244e75dd6deca125b4468"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf408b8462d783790125f047604eb7201" id="r_gaf408b8462d783790125f047604eb7201"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf408b8462d783790125f047604eb7201">CAN_F6R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaf408b8462d783790125f047604eb7201"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae07a6c5c781e5f858d27a824a3228ad6" id="r_gae07a6c5c781e5f858d27a824a3228ad6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae07a6c5c781e5f858d27a824a3228ad6">CAN_F6R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf408b8462d783790125f047604eb7201">CAN_F6R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:gae07a6c5c781e5f858d27a824a3228ad6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga533dbb10e8fce9aa6ec23573fb49c339" id="r_ga533dbb10e8fce9aa6ec23573fb49c339"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga533dbb10e8fce9aa6ec23573fb49c339">CAN_F6R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae07a6c5c781e5f858d27a824a3228ad6">CAN_F6R2_FB13_Msk</a></td></tr>
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<tr class="separator:ga533dbb10e8fce9aa6ec23573fb49c339"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga116e5b298af1faddc25c9a2be1c0f2bf" id="r_ga116e5b298af1faddc25c9a2be1c0f2bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga116e5b298af1faddc25c9a2be1c0f2bf">CAN_F6R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga116e5b298af1faddc25c9a2be1c0f2bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada5ad2ab34322414451520650bf405b8" id="r_gada5ad2ab34322414451520650bf405b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada5ad2ab34322414451520650bf405b8">CAN_F6R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga116e5b298af1faddc25c9a2be1c0f2bf">CAN_F6R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:gada5ad2ab34322414451520650bf405b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b95be922291e534609302c0c833f1f7" id="r_ga8b95be922291e534609302c0c833f1f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b95be922291e534609302c0c833f1f7">CAN_F6R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada5ad2ab34322414451520650bf405b8">CAN_F6R2_FB14_Msk</a></td></tr>
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<tr class="separator:ga8b95be922291e534609302c0c833f1f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac87bd58b70908b22b5fd39b0a62a95a3" id="r_gac87bd58b70908b22b5fd39b0a62a95a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac87bd58b70908b22b5fd39b0a62a95a3">CAN_F6R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gac87bd58b70908b22b5fd39b0a62a95a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8109424b373ae93010f98f0c7ad80e5c" id="r_ga8109424b373ae93010f98f0c7ad80e5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8109424b373ae93010f98f0c7ad80e5c">CAN_F6R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac87bd58b70908b22b5fd39b0a62a95a3">CAN_F6R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga8109424b373ae93010f98f0c7ad80e5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17301d50c7b6ad30ffc05ee2c63f6171" id="r_ga17301d50c7b6ad30ffc05ee2c63f6171"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17301d50c7b6ad30ffc05ee2c63f6171">CAN_F6R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8109424b373ae93010f98f0c7ad80e5c">CAN_F6R2_FB15_Msk</a></td></tr>
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<tr class="separator:ga17301d50c7b6ad30ffc05ee2c63f6171"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2636cde6a4bc3ba023bc4c0fe5de75b4" id="r_ga2636cde6a4bc3ba023bc4c0fe5de75b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2636cde6a4bc3ba023bc4c0fe5de75b4">CAN_F6R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga2636cde6a4bc3ba023bc4c0fe5de75b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5a59865040cac5815a6a4099e72e0e4" id="r_gaf5a59865040cac5815a6a4099e72e0e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5a59865040cac5815a6a4099e72e0e4">CAN_F6R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2636cde6a4bc3ba023bc4c0fe5de75b4">CAN_F6R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:gaf5a59865040cac5815a6a4099e72e0e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf23dfb03247544122ed01472b8a31b4d" id="r_gaf23dfb03247544122ed01472b8a31b4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf23dfb03247544122ed01472b8a31b4d">CAN_F6R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5a59865040cac5815a6a4099e72e0e4">CAN_F6R2_FB16_Msk</a></td></tr>
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<tr class="separator:gaf23dfb03247544122ed01472b8a31b4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab93f20ff2225a03f65492b6e5d499ddb" id="r_gab93f20ff2225a03f65492b6e5d499ddb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab93f20ff2225a03f65492b6e5d499ddb">CAN_F6R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gab93f20ff2225a03f65492b6e5d499ddb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd1ca2f91f8ea1af952b18ebd27dc725" id="r_gadd1ca2f91f8ea1af952b18ebd27dc725"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd1ca2f91f8ea1af952b18ebd27dc725">CAN_F6R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab93f20ff2225a03f65492b6e5d499ddb">CAN_F6R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:gadd1ca2f91f8ea1af952b18ebd27dc725"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf8d35fbfa677fc446da68f4043b633e" id="r_gadf8d35fbfa677fc446da68f4043b633e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf8d35fbfa677fc446da68f4043b633e">CAN_F6R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadd1ca2f91f8ea1af952b18ebd27dc725">CAN_F6R2_FB17_Msk</a></td></tr>
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<tr class="separator:gadf8d35fbfa677fc446da68f4043b633e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga362d1f3ea3b3bfb78fc3ccb70b813de0" id="r_ga362d1f3ea3b3bfb78fc3ccb70b813de0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga362d1f3ea3b3bfb78fc3ccb70b813de0">CAN_F6R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga362d1f3ea3b3bfb78fc3ccb70b813de0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3c4bcd69ad9af4bd97c63269e95278a" id="r_gaa3c4bcd69ad9af4bd97c63269e95278a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3c4bcd69ad9af4bd97c63269e95278a">CAN_F6R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga362d1f3ea3b3bfb78fc3ccb70b813de0">CAN_F6R2_FB18_Pos</a>)</td></tr>
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<tr class="separator:gaa3c4bcd69ad9af4bd97c63269e95278a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c81a1972ec8d87421c6113bb9747c3e" id="r_ga6c81a1972ec8d87421c6113bb9747c3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c81a1972ec8d87421c6113bb9747c3e">CAN_F6R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3c4bcd69ad9af4bd97c63269e95278a">CAN_F6R2_FB18_Msk</a></td></tr>
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<tr class="separator:ga6c81a1972ec8d87421c6113bb9747c3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a05fd66da3b0a785893d7e4ae4c38ec" id="r_ga2a05fd66da3b0a785893d7e4ae4c38ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a05fd66da3b0a785893d7e4ae4c38ec">CAN_F6R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga2a05fd66da3b0a785893d7e4ae4c38ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b19c8600e4c828eab5759dae7cf2fc5" id="r_ga8b19c8600e4c828eab5759dae7cf2fc5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b19c8600e4c828eab5759dae7cf2fc5">CAN_F6R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a05fd66da3b0a785893d7e4ae4c38ec">CAN_F6R2_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga8b19c8600e4c828eab5759dae7cf2fc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11ea1bd4bae8b27a5fd73d210eb83d39" id="r_ga11ea1bd4bae8b27a5fd73d210eb83d39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11ea1bd4bae8b27a5fd73d210eb83d39">CAN_F6R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b19c8600e4c828eab5759dae7cf2fc5">CAN_F6R2_FB19_Msk</a></td></tr>
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<tr class="separator:ga11ea1bd4bae8b27a5fd73d210eb83d39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga126bec7490158480e1c8011828bc900b" id="r_ga126bec7490158480e1c8011828bc900b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga126bec7490158480e1c8011828bc900b">CAN_F6R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga126bec7490158480e1c8011828bc900b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21e7a0134b94773f327e99d20877707b" id="r_ga21e7a0134b94773f327e99d20877707b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21e7a0134b94773f327e99d20877707b">CAN_F6R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga126bec7490158480e1c8011828bc900b">CAN_F6R2_FB20_Pos</a>)</td></tr>
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<tr class="memitem:ga4c48dcd1ac5e23827813ed695bdff0d1" id="r_ga4c48dcd1ac5e23827813ed695bdff0d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c48dcd1ac5e23827813ed695bdff0d1">CAN_F6R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga21e7a0134b94773f327e99d20877707b">CAN_F6R2_FB20_Msk</a></td></tr>
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<tr class="memitem:ga003e56f189cb2d03ceb4d86ebbfb1a96" id="r_ga003e56f189cb2d03ceb4d86ebbfb1a96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga003e56f189cb2d03ceb4d86ebbfb1a96">CAN_F6R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga003e56f189cb2d03ceb4d86ebbfb1a96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga049c4c90a51a7370af5575dd2ce43b25" id="r_ga049c4c90a51a7370af5575dd2ce43b25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga049c4c90a51a7370af5575dd2ce43b25">CAN_F6R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga003e56f189cb2d03ceb4d86ebbfb1a96">CAN_F6R2_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga049c4c90a51a7370af5575dd2ce43b25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd115d29d9f0a8fddc13a32c013af26b" id="r_gacd115d29d9f0a8fddc13a32c013af26b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd115d29d9f0a8fddc13a32c013af26b">CAN_F6R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga049c4c90a51a7370af5575dd2ce43b25">CAN_F6R2_FB21_Msk</a></td></tr>
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<tr class="separator:gacd115d29d9f0a8fddc13a32c013af26b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga178f147b77209ef59f0d73059ff40734" id="r_ga178f147b77209ef59f0d73059ff40734"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga178f147b77209ef59f0d73059ff40734">CAN_F6R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="memitem:ga70456f1faf630198eb6a6aa9d014465b" id="r_ga70456f1faf630198eb6a6aa9d014465b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70456f1faf630198eb6a6aa9d014465b">CAN_F6R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga178f147b77209ef59f0d73059ff40734">CAN_F6R2_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga70456f1faf630198eb6a6aa9d014465b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3f116b2e31dd40bcdd6617fee83907e" id="r_gaa3f116b2e31dd40bcdd6617fee83907e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3f116b2e31dd40bcdd6617fee83907e">CAN_F6R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga70456f1faf630198eb6a6aa9d014465b">CAN_F6R2_FB22_Msk</a></td></tr>
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<tr class="separator:gaa3f116b2e31dd40bcdd6617fee83907e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga252f65a784a6e484323ecbb340a06540" id="r_ga252f65a784a6e484323ecbb340a06540"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga252f65a784a6e484323ecbb340a06540">CAN_F6R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="memitem:ga1523937cea2319fb9c692056b8599861" id="r_ga1523937cea2319fb9c692056b8599861"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1523937cea2319fb9c692056b8599861">CAN_F6R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga252f65a784a6e484323ecbb340a06540">CAN_F6R2_FB23_Pos</a>)</td></tr>
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<tr class="memitem:ga090da76d2d9379dbfc54f7c3fcf69fe4" id="r_ga090da76d2d9379dbfc54f7c3fcf69fe4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga090da76d2d9379dbfc54f7c3fcf69fe4">CAN_F6R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1523937cea2319fb9c692056b8599861">CAN_F6R2_FB23_Msk</a></td></tr>
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<tr class="separator:ga090da76d2d9379dbfc54f7c3fcf69fe4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e75f6bf8e5658bb7539704812be0267" id="r_ga1e75f6bf8e5658bb7539704812be0267"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e75f6bf8e5658bb7539704812be0267">CAN_F6R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga1e75f6bf8e5658bb7539704812be0267"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b080d0ae18594e56bc64fa67e298d6d" id="r_ga1b080d0ae18594e56bc64fa67e298d6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b080d0ae18594e56bc64fa67e298d6d">CAN_F6R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e75f6bf8e5658bb7539704812be0267">CAN_F6R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga1b080d0ae18594e56bc64fa67e298d6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9c8a59a8065400f4a75be49a78e2a9e" id="r_gae9c8a59a8065400f4a75be49a78e2a9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9c8a59a8065400f4a75be49a78e2a9e">CAN_F6R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b080d0ae18594e56bc64fa67e298d6d">CAN_F6R2_FB24_Msk</a></td></tr>
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<tr class="separator:gae9c8a59a8065400f4a75be49a78e2a9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac10f8f8e4e72fae0d0b8f910c1fe96d9" id="r_gac10f8f8e4e72fae0d0b8f910c1fe96d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac10f8f8e4e72fae0d0b8f910c1fe96d9">CAN_F6R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gac10f8f8e4e72fae0d0b8f910c1fe96d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb8abbda99bc68f0dcfe984ee985bd5d" id="r_gacb8abbda99bc68f0dcfe984ee985bd5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb8abbda99bc68f0dcfe984ee985bd5d">CAN_F6R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac10f8f8e4e72fae0d0b8f910c1fe96d9">CAN_F6R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:gacb8abbda99bc68f0dcfe984ee985bd5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3854a1a11c72e64d3c4722494f463421" id="r_ga3854a1a11c72e64d3c4722494f463421"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3854a1a11c72e64d3c4722494f463421">CAN_F6R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacb8abbda99bc68f0dcfe984ee985bd5d">CAN_F6R2_FB25_Msk</a></td></tr>
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<tr class="separator:ga3854a1a11c72e64d3c4722494f463421"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga266f93b0c8f656140718c98f2c93d0bd" id="r_ga266f93b0c8f656140718c98f2c93d0bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga266f93b0c8f656140718c98f2c93d0bd">CAN_F6R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga266f93b0c8f656140718c98f2c93d0bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5cf38e7dad669f04679189c848749f3" id="r_gab5cf38e7dad669f04679189c848749f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5cf38e7dad669f04679189c848749f3">CAN_F6R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga266f93b0c8f656140718c98f2c93d0bd">CAN_F6R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:gab5cf38e7dad669f04679189c848749f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b5ceb9d7ae0c6e34490b8d8659919c9" id="r_ga7b5ceb9d7ae0c6e34490b8d8659919c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b5ceb9d7ae0c6e34490b8d8659919c9">CAN_F6R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab5cf38e7dad669f04679189c848749f3">CAN_F6R2_FB26_Msk</a></td></tr>
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<tr class="separator:ga7b5ceb9d7ae0c6e34490b8d8659919c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ef9ca5e08378882d65e1f754e8b197c" id="r_ga5ef9ca5e08378882d65e1f754e8b197c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ef9ca5e08378882d65e1f754e8b197c">CAN_F6R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga5ef9ca5e08378882d65e1f754e8b197c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga607397b46ace68583b5b13f6d6f23cb7" id="r_ga607397b46ace68583b5b13f6d6f23cb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga607397b46ace68583b5b13f6d6f23cb7">CAN_F6R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ef9ca5e08378882d65e1f754e8b197c">CAN_F6R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga607397b46ace68583b5b13f6d6f23cb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac01a4accedd624ceccf8f8976a043177" id="r_gac01a4accedd624ceccf8f8976a043177"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac01a4accedd624ceccf8f8976a043177">CAN_F6R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga607397b46ace68583b5b13f6d6f23cb7">CAN_F6R2_FB27_Msk</a></td></tr>
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<tr class="separator:gac01a4accedd624ceccf8f8976a043177"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea647666f32db62170873fb233f9eeda" id="r_gaea647666f32db62170873fb233f9eeda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea647666f32db62170873fb233f9eeda">CAN_F6R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:gaea647666f32db62170873fb233f9eeda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed265f9447716d0d3bc7dad1a295630c" id="r_gaed265f9447716d0d3bc7dad1a295630c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed265f9447716d0d3bc7dad1a295630c">CAN_F6R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea647666f32db62170873fb233f9eeda">CAN_F6R2_FB28_Pos</a>)</td></tr>
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<tr class="memitem:gacc2d754207055a5a87696eb1bb7d8cae" id="r_gacc2d754207055a5a87696eb1bb7d8cae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc2d754207055a5a87696eb1bb7d8cae">CAN_F6R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaed265f9447716d0d3bc7dad1a295630c">CAN_F6R2_FB28_Msk</a></td></tr>
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<tr class="separator:gacc2d754207055a5a87696eb1bb7d8cae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68de26372621969702f54818909e3d45" id="r_ga68de26372621969702f54818909e3d45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68de26372621969702f54818909e3d45">CAN_F6R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga68de26372621969702f54818909e3d45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61e13bb0d4c0c6e131e3989c5a5d88b0" id="r_ga61e13bb0d4c0c6e131e3989c5a5d88b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61e13bb0d4c0c6e131e3989c5a5d88b0">CAN_F6R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68de26372621969702f54818909e3d45">CAN_F6R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:ga61e13bb0d4c0c6e131e3989c5a5d88b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga471631ee112af3bde77d848c22d743ef" id="r_ga471631ee112af3bde77d848c22d743ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga471631ee112af3bde77d848c22d743ef">CAN_F6R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga61e13bb0d4c0c6e131e3989c5a5d88b0">CAN_F6R2_FB29_Msk</a></td></tr>
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<tr class="separator:ga471631ee112af3bde77d848c22d743ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e57f1bffaa844b03cdb0743f9b78c2b" id="r_ga5e57f1bffaa844b03cdb0743f9b78c2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e57f1bffaa844b03cdb0743f9b78c2b">CAN_F6R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga5e57f1bffaa844b03cdb0743f9b78c2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ef6901cea91b3ea9b40c0d40980f554" id="r_ga9ef6901cea91b3ea9b40c0d40980f554"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ef6901cea91b3ea9b40c0d40980f554">CAN_F6R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e57f1bffaa844b03cdb0743f9b78c2b">CAN_F6R2_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga9ef6901cea91b3ea9b40c0d40980f554"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9574ec7dddcea6b80368778c01f62598" id="r_ga9574ec7dddcea6b80368778c01f62598"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9574ec7dddcea6b80368778c01f62598">CAN_F6R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ef6901cea91b3ea9b40c0d40980f554">CAN_F6R2_FB30_Msk</a></td></tr>
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<tr class="memitem:ga245979ba9e0a5c2d545fae929eb99892" id="r_ga245979ba9e0a5c2d545fae929eb99892"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga245979ba9e0a5c2d545fae929eb99892">CAN_F6R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga245979ba9e0a5c2d545fae929eb99892"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf6098323e8ea2d82b3dd9b355977d6b" id="r_gaaf6098323e8ea2d82b3dd9b355977d6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf6098323e8ea2d82b3dd9b355977d6b">CAN_F6R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga245979ba9e0a5c2d545fae929eb99892">CAN_F6R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:gaaf6098323e8ea2d82b3dd9b355977d6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64bcb159347ad8e2a2609ce89ed030df" id="r_ga64bcb159347ad8e2a2609ce89ed030df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64bcb159347ad8e2a2609ce89ed030df">CAN_F6R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf6098323e8ea2d82b3dd9b355977d6b">CAN_F6R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga64bcb159347ad8e2a2609ce89ed030df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f4317b3af8e10a0d4b70433d705208f" id="r_ga5f4317b3af8e10a0d4b70433d705208f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f4317b3af8e10a0d4b70433d705208f">CAN_F7R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5f4317b3af8e10a0d4b70433d705208f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7e6ac71d87a53fb60da7f7d7bb4a31c" id="r_gaa7e6ac71d87a53fb60da7f7d7bb4a31c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e6ac71d87a53fb60da7f7d7bb4a31c">CAN_F7R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f4317b3af8e10a0d4b70433d705208f">CAN_F7R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:gaa7e6ac71d87a53fb60da7f7d7bb4a31c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec0803330590bf9aba9d09342034b2c1" id="r_gaec0803330590bf9aba9d09342034b2c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec0803330590bf9aba9d09342034b2c1">CAN_F7R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e6ac71d87a53fb60da7f7d7bb4a31c">CAN_F7R2_FB0_Msk</a></td></tr>
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<tr class="separator:gaec0803330590bf9aba9d09342034b2c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24c69591a6d5b2f86f6e57027640dd73" id="r_ga24c69591a6d5b2f86f6e57027640dd73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24c69591a6d5b2f86f6e57027640dd73">CAN_F7R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga24c69591a6d5b2f86f6e57027640dd73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac046be844d45ddd93b750c2b3fdeffb5" id="r_gac046be844d45ddd93b750c2b3fdeffb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac046be844d45ddd93b750c2b3fdeffb5">CAN_F7R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24c69591a6d5b2f86f6e57027640dd73">CAN_F7R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:gac046be844d45ddd93b750c2b3fdeffb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c633d4cbfdf79f09ae1df5e75c98439" id="r_ga8c633d4cbfdf79f09ae1df5e75c98439"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c633d4cbfdf79f09ae1df5e75c98439">CAN_F7R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac046be844d45ddd93b750c2b3fdeffb5">CAN_F7R2_FB1_Msk</a></td></tr>
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<tr class="separator:ga8c633d4cbfdf79f09ae1df5e75c98439"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91c5dc8630c3f5d987bdbd9000dbde85" id="r_ga91c5dc8630c3f5d987bdbd9000dbde85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91c5dc8630c3f5d987bdbd9000dbde85">CAN_F7R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga91c5dc8630c3f5d987bdbd9000dbde85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae222910542a55154e8b02affd43c1bb1" id="r_gae222910542a55154e8b02affd43c1bb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae222910542a55154e8b02affd43c1bb1">CAN_F7R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga91c5dc8630c3f5d987bdbd9000dbde85">CAN_F7R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:gae222910542a55154e8b02affd43c1bb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31a0c4ece8b73760ad295344b8558ddb" id="r_ga31a0c4ece8b73760ad295344b8558ddb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31a0c4ece8b73760ad295344b8558ddb">CAN_F7R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae222910542a55154e8b02affd43c1bb1">CAN_F7R2_FB2_Msk</a></td></tr>
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<tr class="separator:ga31a0c4ece8b73760ad295344b8558ddb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86e2b7893638f3661915edb722d2adde" id="r_ga86e2b7893638f3661915edb722d2adde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86e2b7893638f3661915edb722d2adde">CAN_F7R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga86e2b7893638f3661915edb722d2adde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf47bc62b248184ab11796b147fd12fa4" id="r_gaf47bc62b248184ab11796b147fd12fa4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf47bc62b248184ab11796b147fd12fa4">CAN_F7R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga86e2b7893638f3661915edb722d2adde">CAN_F7R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:gaf47bc62b248184ab11796b147fd12fa4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe2fc15309540b87538ea3e8460d8d11" id="r_gafe2fc15309540b87538ea3e8460d8d11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe2fc15309540b87538ea3e8460d8d11">CAN_F7R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf47bc62b248184ab11796b147fd12fa4">CAN_F7R2_FB3_Msk</a></td></tr>
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<tr class="separator:gafe2fc15309540b87538ea3e8460d8d11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8f96b4a3fa62b12e2529a91b67f1f4c" id="r_gaf8f96b4a3fa62b12e2529a91b67f1f4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8f96b4a3fa62b12e2529a91b67f1f4c">CAN_F7R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaf8f96b4a3fa62b12e2529a91b67f1f4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6532dbd923dbc1ae43394d64065b01f9" id="r_ga6532dbd923dbc1ae43394d64065b01f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6532dbd923dbc1ae43394d64065b01f9">CAN_F7R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8f96b4a3fa62b12e2529a91b67f1f4c">CAN_F7R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga6532dbd923dbc1ae43394d64065b01f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac81d4c021f4579021ddf9485472a84f5" id="r_gac81d4c021f4579021ddf9485472a84f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac81d4c021f4579021ddf9485472a84f5">CAN_F7R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6532dbd923dbc1ae43394d64065b01f9">CAN_F7R2_FB4_Msk</a></td></tr>
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<tr class="separator:gac81d4c021f4579021ddf9485472a84f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga996bd937bc577755b88acdaee8493640" id="r_ga996bd937bc577755b88acdaee8493640"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga996bd937bc577755b88acdaee8493640">CAN_F7R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga996bd937bc577755b88acdaee8493640"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga791664168f6ee37eea4331bf0f17f878" id="r_ga791664168f6ee37eea4331bf0f17f878"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga791664168f6ee37eea4331bf0f17f878">CAN_F7R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga996bd937bc577755b88acdaee8493640">CAN_F7R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga791664168f6ee37eea4331bf0f17f878"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5dd6a00bb403a3e19e66c68f5ee308e2" id="r_ga5dd6a00bb403a3e19e66c68f5ee308e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5dd6a00bb403a3e19e66c68f5ee308e2">CAN_F7R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga791664168f6ee37eea4331bf0f17f878">CAN_F7R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga5dd6a00bb403a3e19e66c68f5ee308e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7fcf07c4563ff3e099d9d88926d135d5" id="r_ga7fcf07c4563ff3e099d9d88926d135d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fcf07c4563ff3e099d9d88926d135d5">CAN_F7R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga7fcf07c4563ff3e099d9d88926d135d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f12b37158633c7274a01feacbf342c6" id="r_ga4f12b37158633c7274a01feacbf342c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f12b37158633c7274a01feacbf342c6">CAN_F7R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7fcf07c4563ff3e099d9d88926d135d5">CAN_F7R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga4f12b37158633c7274a01feacbf342c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b5eaf37458d0426fd7f847775fd41e9" id="r_ga9b5eaf37458d0426fd7f847775fd41e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b5eaf37458d0426fd7f847775fd41e9">CAN_F7R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f12b37158633c7274a01feacbf342c6">CAN_F7R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga9b5eaf37458d0426fd7f847775fd41e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe34ced987191e7acda093c4b726148d" id="r_gafe34ced987191e7acda093c4b726148d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe34ced987191e7acda093c4b726148d">CAN_F7R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gafe34ced987191e7acda093c4b726148d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae323bdff49096a4afee6dec3d9d9aebd" id="r_gae323bdff49096a4afee6dec3d9d9aebd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae323bdff49096a4afee6dec3d9d9aebd">CAN_F7R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafe34ced987191e7acda093c4b726148d">CAN_F7R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:gae323bdff49096a4afee6dec3d9d9aebd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga780440ce173cde12fd117b519419424c" id="r_ga780440ce173cde12fd117b519419424c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga780440ce173cde12fd117b519419424c">CAN_F7R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae323bdff49096a4afee6dec3d9d9aebd">CAN_F7R2_FB7_Msk</a></td></tr>
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<tr class="separator:ga780440ce173cde12fd117b519419424c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c5cd0875fa5ecc52ab306eb47020388" id="r_ga1c5cd0875fa5ecc52ab306eb47020388"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c5cd0875fa5ecc52ab306eb47020388">CAN_F7R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga1c5cd0875fa5ecc52ab306eb47020388"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ec8c5b0a88b30a17f9afb284bcc95c1" id="r_ga5ec8c5b0a88b30a17f9afb284bcc95c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec8c5b0a88b30a17f9afb284bcc95c1">CAN_F7R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c5cd0875fa5ecc52ab306eb47020388">CAN_F7R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga5ec8c5b0a88b30a17f9afb284bcc95c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99ae0e27d14b42fef4551d83ee88b4ac" id="r_ga99ae0e27d14b42fef4551d83ee88b4ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99ae0e27d14b42fef4551d83ee88b4ac">CAN_F7R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec8c5b0a88b30a17f9afb284bcc95c1">CAN_F7R2_FB8_Msk</a></td></tr>
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<tr class="separator:ga99ae0e27d14b42fef4551d83ee88b4ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae07c159d533af5bd5d2a6733db52e400" id="r_gae07c159d533af5bd5d2a6733db52e400"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae07c159d533af5bd5d2a6733db52e400">CAN_F7R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gae07c159d533af5bd5d2a6733db52e400"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf18ed7d215a3e4a3ebbca297626877c" id="r_gaaf18ed7d215a3e4a3ebbca297626877c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf18ed7d215a3e4a3ebbca297626877c">CAN_F7R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae07c159d533af5bd5d2a6733db52e400">CAN_F7R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:gaaf18ed7d215a3e4a3ebbca297626877c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace90c0624446480421fac233739413dc" id="r_gace90c0624446480421fac233739413dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace90c0624446480421fac233739413dc">CAN_F7R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf18ed7d215a3e4a3ebbca297626877c">CAN_F7R2_FB9_Msk</a></td></tr>
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<tr class="memitem:ga1bc252c24c4748c4596a5fbd9bcff7b1" id="r_ga1bc252c24c4748c4596a5fbd9bcff7b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc252c24c4748c4596a5fbd9bcff7b1">CAN_F7R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="memitem:ga81766a9d745aeadd4ba0a34d3ded18e7" id="r_ga81766a9d745aeadd4ba0a34d3ded18e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81766a9d745aeadd4ba0a34d3ded18e7">CAN_F7R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc252c24c4748c4596a5fbd9bcff7b1">CAN_F7R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga81766a9d745aeadd4ba0a34d3ded18e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae60d566699df87580584ed496681562" id="r_gaae60d566699df87580584ed496681562"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae60d566699df87580584ed496681562">CAN_F7R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga81766a9d745aeadd4ba0a34d3ded18e7">CAN_F7R2_FB10_Msk</a></td></tr>
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<tr class="separator:gaae60d566699df87580584ed496681562"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14f3c2bf58159e154369752dae336477" id="r_ga14f3c2bf58159e154369752dae336477"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14f3c2bf58159e154369752dae336477">CAN_F7R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga33730db505f710ba327f8c6c1f04da4f" id="r_ga33730db505f710ba327f8c6c1f04da4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33730db505f710ba327f8c6c1f04da4f">CAN_F7R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14f3c2bf58159e154369752dae336477">CAN_F7R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga33730db505f710ba327f8c6c1f04da4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6325b37cc369b92b2334e482dbe3bf06" id="r_ga6325b37cc369b92b2334e482dbe3bf06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6325b37cc369b92b2334e482dbe3bf06">CAN_F7R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga33730db505f710ba327f8c6c1f04da4f">CAN_F7R2_FB11_Msk</a></td></tr>
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<tr class="separator:ga6325b37cc369b92b2334e482dbe3bf06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1f505ec544d393c5f905b294bce4401" id="r_gaf1f505ec544d393c5f905b294bce4401"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1f505ec544d393c5f905b294bce4401">CAN_F7R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaf1f505ec544d393c5f905b294bce4401"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02c278c9bfd9314c34ac6da260c08403" id="r_ga02c278c9bfd9314c34ac6da260c08403"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02c278c9bfd9314c34ac6da260c08403">CAN_F7R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1f505ec544d393c5f905b294bce4401">CAN_F7R2_FB12_Pos</a>)</td></tr>
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<tr class="memitem:gace846d293ac11d535ee2aad17cf099bc" id="r_gace846d293ac11d535ee2aad17cf099bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace846d293ac11d535ee2aad17cf099bc">CAN_F7R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c278c9bfd9314c34ac6da260c08403">CAN_F7R2_FB12_Msk</a></td></tr>
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<tr class="separator:gace846d293ac11d535ee2aad17cf099bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac30df90b8299022e421c729f7088cf11" id="r_gac30df90b8299022e421c729f7088cf11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac30df90b8299022e421c729f7088cf11">CAN_F7R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga40fec0160eec943f81f05ad9d48ce9b2" id="r_ga40fec0160eec943f81f05ad9d48ce9b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40fec0160eec943f81f05ad9d48ce9b2">CAN_F7R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac30df90b8299022e421c729f7088cf11">CAN_F7R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga40fec0160eec943f81f05ad9d48ce9b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91b26397a75fc4c0124e84903d31221e" id="r_ga91b26397a75fc4c0124e84903d31221e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91b26397a75fc4c0124e84903d31221e">CAN_F7R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga40fec0160eec943f81f05ad9d48ce9b2">CAN_F7R2_FB13_Msk</a></td></tr>
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<tr class="memitem:gad8eb41c28b8059b9d0f25f05341cff65" id="r_gad8eb41c28b8059b9d0f25f05341cff65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8eb41c28b8059b9d0f25f05341cff65">CAN_F7R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="memitem:ga906faed52246a867bbe9675b588c2fe0" id="r_ga906faed52246a867bbe9675b588c2fe0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga906faed52246a867bbe9675b588c2fe0">CAN_F7R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad8eb41c28b8059b9d0f25f05341cff65">CAN_F7R2_FB14_Pos</a>)</td></tr>
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<tr class="memitem:gada2e01c05c216ba6ff4756d043297c0e" id="r_gada2e01c05c216ba6ff4756d043297c0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada2e01c05c216ba6ff4756d043297c0e">CAN_F7R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga906faed52246a867bbe9675b588c2fe0">CAN_F7R2_FB14_Msk</a></td></tr>
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<tr class="separator:gada2e01c05c216ba6ff4756d043297c0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66ab5a2d62ff7650618d15f893046efa" id="r_ga66ab5a2d62ff7650618d15f893046efa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66ab5a2d62ff7650618d15f893046efa">CAN_F7R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga66ab5a2d62ff7650618d15f893046efa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf54c82654d230ba010300b9b879f606" id="r_gacf54c82654d230ba010300b9b879f606"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf54c82654d230ba010300b9b879f606">CAN_F7R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66ab5a2d62ff7650618d15f893046efa">CAN_F7R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:gacf54c82654d230ba010300b9b879f606"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeef08aa6565ff24bd9863b4b8a9c2ff5" id="r_gaeef08aa6565ff24bd9863b4b8a9c2ff5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeef08aa6565ff24bd9863b4b8a9c2ff5">CAN_F7R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacf54c82654d230ba010300b9b879f606">CAN_F7R2_FB15_Msk</a></td></tr>
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<tr class="separator:gaeef08aa6565ff24bd9863b4b8a9c2ff5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14b6874b4f61096d8e2f21efddb07831" id="r_ga14b6874b4f61096d8e2f21efddb07831"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14b6874b4f61096d8e2f21efddb07831">CAN_F7R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga14b6874b4f61096d8e2f21efddb07831"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac23ba211219c2ece524f3867e2b1cc4e" id="r_gac23ba211219c2ece524f3867e2b1cc4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac23ba211219c2ece524f3867e2b1cc4e">CAN_F7R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b6874b4f61096d8e2f21efddb07831">CAN_F7R2_FB16_Pos</a>)</td></tr>
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<tr class="memitem:ga16c3ccb033b9541b57c338b9737f18dd" id="r_ga16c3ccb033b9541b57c338b9737f18dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16c3ccb033b9541b57c338b9737f18dd">CAN_F7R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac23ba211219c2ece524f3867e2b1cc4e">CAN_F7R2_FB16_Msk</a></td></tr>
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<tr class="memitem:ga9070f003ab14a0a9e619c82acc6d357f" id="r_ga9070f003ab14a0a9e619c82acc6d357f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9070f003ab14a0a9e619c82acc6d357f">CAN_F7R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga9070f003ab14a0a9e619c82acc6d357f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga714ba087c8c662749a5e1db9f82af81d" id="r_ga714ba087c8c662749a5e1db9f82af81d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga714ba087c8c662749a5e1db9f82af81d">CAN_F7R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9070f003ab14a0a9e619c82acc6d357f">CAN_F7R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga714ba087c8c662749a5e1db9f82af81d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad898ca382f57efb1842884d46217245c" id="r_gad898ca382f57efb1842884d46217245c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad898ca382f57efb1842884d46217245c">CAN_F7R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga714ba087c8c662749a5e1db9f82af81d">CAN_F7R2_FB17_Msk</a></td></tr>
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<tr class="memitem:ga69277e05f3cfeb8c75d9b008c7db5d37" id="r_ga69277e05f3cfeb8c75d9b008c7db5d37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69277e05f3cfeb8c75d9b008c7db5d37">CAN_F7R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga69277e05f3cfeb8c75d9b008c7db5d37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga228a38b1060b3ff498d35aed4e128917" id="r_ga228a38b1060b3ff498d35aed4e128917"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga228a38b1060b3ff498d35aed4e128917">CAN_F7R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69277e05f3cfeb8c75d9b008c7db5d37">CAN_F7R2_FB18_Pos</a>)</td></tr>
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<tr class="memitem:gaf419938e132cc1a0bf59a6c058e2c7c5" id="r_gaf419938e132cc1a0bf59a6c058e2c7c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf419938e132cc1a0bf59a6c058e2c7c5">CAN_F7R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga228a38b1060b3ff498d35aed4e128917">CAN_F7R2_FB18_Msk</a></td></tr>
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<tr class="separator:gaf419938e132cc1a0bf59a6c058e2c7c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab6251821d862bf793711e13753c7ae5a" id="r_gab6251821d862bf793711e13753c7ae5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6251821d862bf793711e13753c7ae5a">CAN_F7R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="memitem:gaa4893f06f2a927a5e1a38e9faf3edb90" id="r_gaa4893f06f2a927a5e1a38e9faf3edb90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4893f06f2a927a5e1a38e9faf3edb90">CAN_F7R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab6251821d862bf793711e13753c7ae5a">CAN_F7R2_FB19_Pos</a>)</td></tr>
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<tr class="separator:gaa4893f06f2a927a5e1a38e9faf3edb90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae991abb6f2e64443be7e39633f192aba" id="r_gae991abb6f2e64443be7e39633f192aba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae991abb6f2e64443be7e39633f192aba">CAN_F7R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4893f06f2a927a5e1a38e9faf3edb90">CAN_F7R2_FB19_Msk</a></td></tr>
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<tr class="memitem:gacb34c2b052df01aa362473d670d42ed0" id="r_gacb34c2b052df01aa362473d670d42ed0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb34c2b052df01aa362473d670d42ed0">CAN_F7R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gacb34c2b052df01aa362473d670d42ed0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9074bda7aca4edf2e11e8125a57cbc5a" id="r_ga9074bda7aca4edf2e11e8125a57cbc5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9074bda7aca4edf2e11e8125a57cbc5a">CAN_F7R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacb34c2b052df01aa362473d670d42ed0">CAN_F7R2_FB20_Pos</a>)</td></tr>
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<tr class="memitem:ga3738a42e2767c928de21a2f784ce6bce" id="r_ga3738a42e2767c928de21a2f784ce6bce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3738a42e2767c928de21a2f784ce6bce">CAN_F7R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9074bda7aca4edf2e11e8125a57cbc5a">CAN_F7R2_FB20_Msk</a></td></tr>
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<tr class="separator:ga3738a42e2767c928de21a2f784ce6bce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d955eb8acf2decac2bd58e6746fd407" id="r_ga2d955eb8acf2decac2bd58e6746fd407"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d955eb8acf2decac2bd58e6746fd407">CAN_F7R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga2d955eb8acf2decac2bd58e6746fd407"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8dacdf1e167c8a3f7509e4ddf5757e1" id="r_gaa8dacdf1e167c8a3f7509e4ddf5757e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8dacdf1e167c8a3f7509e4ddf5757e1">CAN_F7R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d955eb8acf2decac2bd58e6746fd407">CAN_F7R2_FB21_Pos</a>)</td></tr>
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<tr class="separator:gaa8dacdf1e167c8a3f7509e4ddf5757e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5cb252582e6b7bd706b37447f71d6cd" id="r_gae5cb252582e6b7bd706b37447f71d6cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5cb252582e6b7bd706b37447f71d6cd">CAN_F7R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8dacdf1e167c8a3f7509e4ddf5757e1">CAN_F7R2_FB21_Msk</a></td></tr>
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<tr class="separator:gae5cb252582e6b7bd706b37447f71d6cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade58525a8af1d2246aea9a8f494dc3a7" id="r_gade58525a8af1d2246aea9a8f494dc3a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade58525a8af1d2246aea9a8f494dc3a7">CAN_F7R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gade58525a8af1d2246aea9a8f494dc3a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad37f85aab2fa384e5d0643b17eae8440" id="r_gad37f85aab2fa384e5d0643b17eae8440"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad37f85aab2fa384e5d0643b17eae8440">CAN_F7R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade58525a8af1d2246aea9a8f494dc3a7">CAN_F7R2_FB22_Pos</a>)</td></tr>
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<tr class="separator:gad37f85aab2fa384e5d0643b17eae8440"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae616e53b9d961571eea4ff2df31f8399" id="r_gae616e53b9d961571eea4ff2df31f8399"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae616e53b9d961571eea4ff2df31f8399">CAN_F7R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad37f85aab2fa384e5d0643b17eae8440">CAN_F7R2_FB22_Msk</a></td></tr>
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<tr class="separator:gae616e53b9d961571eea4ff2df31f8399"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa07aee43f61765d654ba4f1a965c3d15" id="r_gaa07aee43f61765d654ba4f1a965c3d15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa07aee43f61765d654ba4f1a965c3d15">CAN_F7R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gaa07aee43f61765d654ba4f1a965c3d15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad01aed48c87877406fcd8a0da994b8b6" id="r_gad01aed48c87877406fcd8a0da994b8b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad01aed48c87877406fcd8a0da994b8b6">CAN_F7R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa07aee43f61765d654ba4f1a965c3d15">CAN_F7R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:gad01aed48c87877406fcd8a0da994b8b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2049c9bb27af3cde01334b1901aa417" id="r_gab2049c9bb27af3cde01334b1901aa417"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2049c9bb27af3cde01334b1901aa417">CAN_F7R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad01aed48c87877406fcd8a0da994b8b6">CAN_F7R2_FB23_Msk</a></td></tr>
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<tr class="separator:gab2049c9bb27af3cde01334b1901aa417"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed455c42e4814928236cee53101a2863" id="r_gaed455c42e4814928236cee53101a2863"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed455c42e4814928236cee53101a2863">CAN_F7R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaed455c42e4814928236cee53101a2863"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3274b8fc32c7104c1ae6015fe725c63b" id="r_ga3274b8fc32c7104c1ae6015fe725c63b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3274b8fc32c7104c1ae6015fe725c63b">CAN_F7R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed455c42e4814928236cee53101a2863">CAN_F7R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga3274b8fc32c7104c1ae6015fe725c63b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e69c2fd32e2c523c9e939df825fc605" id="r_ga8e69c2fd32e2c523c9e939df825fc605"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e69c2fd32e2c523c9e939df825fc605">CAN_F7R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3274b8fc32c7104c1ae6015fe725c63b">CAN_F7R2_FB24_Msk</a></td></tr>
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<tr class="separator:ga8e69c2fd32e2c523c9e939df825fc605"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebdd728474eecad67ed5816c533f575b" id="r_gaebdd728474eecad67ed5816c533f575b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebdd728474eecad67ed5816c533f575b">CAN_F7R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gaebdd728474eecad67ed5816c533f575b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ee9ad1b18fe010798526b61b23773b7" id="r_ga9ee9ad1b18fe010798526b61b23773b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ee9ad1b18fe010798526b61b23773b7">CAN_F7R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaebdd728474eecad67ed5816c533f575b">CAN_F7R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga9ee9ad1b18fe010798526b61b23773b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga659cc84b9186e279c37e88b94e1c9829" id="r_ga659cc84b9186e279c37e88b94e1c9829"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga659cc84b9186e279c37e88b94e1c9829">CAN_F7R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ee9ad1b18fe010798526b61b23773b7">CAN_F7R2_FB25_Msk</a></td></tr>
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<tr class="separator:ga659cc84b9186e279c37e88b94e1c9829"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68cc77bf1d501625c5e639909e29c118" id="r_ga68cc77bf1d501625c5e639909e29c118"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68cc77bf1d501625c5e639909e29c118">CAN_F7R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga68cc77bf1d501625c5e639909e29c118"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga649a2979cf8c968b94a82ade9eb7aa77" id="r_ga649a2979cf8c968b94a82ade9eb7aa77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga649a2979cf8c968b94a82ade9eb7aa77">CAN_F7R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68cc77bf1d501625c5e639909e29c118">CAN_F7R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga649a2979cf8c968b94a82ade9eb7aa77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43c9da5ad4c2d261858f73b779cc3dae" id="r_ga43c9da5ad4c2d261858f73b779cc3dae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43c9da5ad4c2d261858f73b779cc3dae">CAN_F7R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga649a2979cf8c968b94a82ade9eb7aa77">CAN_F7R2_FB26_Msk</a></td></tr>
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<tr class="separator:ga43c9da5ad4c2d261858f73b779cc3dae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d61a9597fe302aa59b1bf6944f69aad" id="r_ga5d61a9597fe302aa59b1bf6944f69aad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d61a9597fe302aa59b1bf6944f69aad">CAN_F7R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga5d61a9597fe302aa59b1bf6944f69aad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga005b8dfa3d1f6eb19c33deed337fab12" id="r_ga005b8dfa3d1f6eb19c33deed337fab12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga005b8dfa3d1f6eb19c33deed337fab12">CAN_F7R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5d61a9597fe302aa59b1bf6944f69aad">CAN_F7R2_FB27_Pos</a>)</td></tr>
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<tr class="memitem:ga0a1ea8d66ada6cea7268fba151c00d91" id="r_ga0a1ea8d66ada6cea7268fba151c00d91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a1ea8d66ada6cea7268fba151c00d91">CAN_F7R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga005b8dfa3d1f6eb19c33deed337fab12">CAN_F7R2_FB27_Msk</a></td></tr>
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<tr class="separator:ga0a1ea8d66ada6cea7268fba151c00d91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga317154057e36bcfb50408ffa8c106559" id="r_ga317154057e36bcfb50408ffa8c106559"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga317154057e36bcfb50408ffa8c106559">CAN_F7R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga317154057e36bcfb50408ffa8c106559"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadaa906c94d6d83a7a5c1d8645e814fa3" id="r_gadaa906c94d6d83a7a5c1d8645e814fa3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadaa906c94d6d83a7a5c1d8645e814fa3">CAN_F7R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga317154057e36bcfb50408ffa8c106559">CAN_F7R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:gadaa906c94d6d83a7a5c1d8645e814fa3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabbd6032652515423412ad73b8a004bbb" id="r_gabbd6032652515423412ad73b8a004bbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbd6032652515423412ad73b8a004bbb">CAN_F7R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadaa906c94d6d83a7a5c1d8645e814fa3">CAN_F7R2_FB28_Msk</a></td></tr>
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<tr class="separator:gabbd6032652515423412ad73b8a004bbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ed2a1e8330f343d50d3ead9b7426715" id="r_ga5ed2a1e8330f343d50d3ead9b7426715"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ed2a1e8330f343d50d3ead9b7426715">CAN_F7R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga5ed2a1e8330f343d50d3ead9b7426715"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd1f2f87a2de3ef977b9f042559110f7" id="r_gabd1f2f87a2de3ef977b9f042559110f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd1f2f87a2de3ef977b9f042559110f7">CAN_F7R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ed2a1e8330f343d50d3ead9b7426715">CAN_F7R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:gabd1f2f87a2de3ef977b9f042559110f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a991a0bb5a81748b091d6b96c59fc37" id="r_ga3a991a0bb5a81748b091d6b96c59fc37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a991a0bb5a81748b091d6b96c59fc37">CAN_F7R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd1f2f87a2de3ef977b9f042559110f7">CAN_F7R2_FB29_Msk</a></td></tr>
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<tr class="separator:ga3a991a0bb5a81748b091d6b96c59fc37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa60296ad3c0c0597363499038128c431" id="r_gaa60296ad3c0c0597363499038128c431"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa60296ad3c0c0597363499038128c431">CAN_F7R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:gaa60296ad3c0c0597363499038128c431"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac67c413d3294aa6762edf76c05352d13" id="r_gac67c413d3294aa6762edf76c05352d13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac67c413d3294aa6762edf76c05352d13">CAN_F7R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa60296ad3c0c0597363499038128c431">CAN_F7R2_FB30_Pos</a>)</td></tr>
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<tr class="memitem:gaedae5e816af0dd734311bf44be7571f2" id="r_gaedae5e816af0dd734311bf44be7571f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedae5e816af0dd734311bf44be7571f2">CAN_F7R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac67c413d3294aa6762edf76c05352d13">CAN_F7R2_FB30_Msk</a></td></tr>
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<tr class="memitem:ga0b8852c12eaf0286767bf738087f5774" id="r_ga0b8852c12eaf0286767bf738087f5774"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b8852c12eaf0286767bf738087f5774">CAN_F7R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga0b8852c12eaf0286767bf738087f5774"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d0df32a1bad3f616506614c53de9a18" id="r_ga0d0df32a1bad3f616506614c53de9a18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d0df32a1bad3f616506614c53de9a18">CAN_F7R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b8852c12eaf0286767bf738087f5774">CAN_F7R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga0d0df32a1bad3f616506614c53de9a18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f88a239b8a39ff3343b1cfe70b06139" id="r_ga2f88a239b8a39ff3343b1cfe70b06139"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f88a239b8a39ff3343b1cfe70b06139">CAN_F7R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d0df32a1bad3f616506614c53de9a18">CAN_F7R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga2f88a239b8a39ff3343b1cfe70b06139"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga272fec3946dc588a9c312573c358a162" id="r_ga272fec3946dc588a9c312573c358a162"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga272fec3946dc588a9c312573c358a162">CAN_F8R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga272fec3946dc588a9c312573c358a162"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a5424a898996971be642271b0cb305d" id="r_ga8a5424a898996971be642271b0cb305d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a5424a898996971be642271b0cb305d">CAN_F8R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga272fec3946dc588a9c312573c358a162">CAN_F8R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga8a5424a898996971be642271b0cb305d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cfe399fb494ff6ab1d5b91258c42764" id="r_ga3cfe399fb494ff6ab1d5b91258c42764"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cfe399fb494ff6ab1d5b91258c42764">CAN_F8R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a5424a898996971be642271b0cb305d">CAN_F8R2_FB0_Msk</a></td></tr>
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<tr class="separator:ga3cfe399fb494ff6ab1d5b91258c42764"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d5a712e64c1b04b7114f562f2605e87" id="r_ga4d5a712e64c1b04b7114f562f2605e87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d5a712e64c1b04b7114f562f2605e87">CAN_F8R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga4d5a712e64c1b04b7114f562f2605e87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4bdeb68c24f386e0181eb04937cf109" id="r_gad4bdeb68c24f386e0181eb04937cf109"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4bdeb68c24f386e0181eb04937cf109">CAN_F8R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d5a712e64c1b04b7114f562f2605e87">CAN_F8R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:gad4bdeb68c24f386e0181eb04937cf109"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ca04b514b4d6a3b19619932513b8953" id="r_ga9ca04b514b4d6a3b19619932513b8953"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ca04b514b4d6a3b19619932513b8953">CAN_F8R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad4bdeb68c24f386e0181eb04937cf109">CAN_F8R2_FB1_Msk</a></td></tr>
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<tr class="separator:ga9ca04b514b4d6a3b19619932513b8953"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5cead607181f44f52c174e67034ea71" id="r_gaa5cead607181f44f52c174e67034ea71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5cead607181f44f52c174e67034ea71">CAN_F8R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaa5cead607181f44f52c174e67034ea71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad180babb8dfebb2d725c57d12ee6c434" id="r_gad180babb8dfebb2d725c57d12ee6c434"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad180babb8dfebb2d725c57d12ee6c434">CAN_F8R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5cead607181f44f52c174e67034ea71">CAN_F8R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:gad180babb8dfebb2d725c57d12ee6c434"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4c3c099bf7db702b7bf5f71cddaaec2" id="r_gac4c3c099bf7db702b7bf5f71cddaaec2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4c3c099bf7db702b7bf5f71cddaaec2">CAN_F8R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad180babb8dfebb2d725c57d12ee6c434">CAN_F8R2_FB2_Msk</a></td></tr>
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<tr class="separator:gac4c3c099bf7db702b7bf5f71cddaaec2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b2a97e11174175e038a5e49de693d81" id="r_ga2b2a97e11174175e038a5e49de693d81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b2a97e11174175e038a5e49de693d81">CAN_F8R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga2b2a97e11174175e038a5e49de693d81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b411230765103ce07b48d181683a8ff" id="r_ga4b411230765103ce07b48d181683a8ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b411230765103ce07b48d181683a8ff">CAN_F8R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b2a97e11174175e038a5e49de693d81">CAN_F8R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga4b411230765103ce07b48d181683a8ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1e53037e7f7171d8a7358590f0e7420" id="r_gae1e53037e7f7171d8a7358590f0e7420"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1e53037e7f7171d8a7358590f0e7420">CAN_F8R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b411230765103ce07b48d181683a8ff">CAN_F8R2_FB3_Msk</a></td></tr>
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<tr class="separator:gae1e53037e7f7171d8a7358590f0e7420"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08ad27ee47d20cf06c110a7a921f6bb1" id="r_ga08ad27ee47d20cf06c110a7a921f6bb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08ad27ee47d20cf06c110a7a921f6bb1">CAN_F8R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga08ad27ee47d20cf06c110a7a921f6bb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f5f223e200cbe85d62785c1c1411780" id="r_ga6f5f223e200cbe85d62785c1c1411780"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f5f223e200cbe85d62785c1c1411780">CAN_F8R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga08ad27ee47d20cf06c110a7a921f6bb1">CAN_F8R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga6f5f223e200cbe85d62785c1c1411780"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51e2af45725e06538c4d09ad07296316" id="r_ga51e2af45725e06538c4d09ad07296316"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51e2af45725e06538c4d09ad07296316">CAN_F8R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f5f223e200cbe85d62785c1c1411780">CAN_F8R2_FB4_Msk</a></td></tr>
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<tr class="separator:ga51e2af45725e06538c4d09ad07296316"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga102d50c9df36acfccfadb2129cc7e933" id="r_ga102d50c9df36acfccfadb2129cc7e933"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga102d50c9df36acfccfadb2129cc7e933">CAN_F8R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga102d50c9df36acfccfadb2129cc7e933"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga715b276f569abd0659cef3d6041ca97f" id="r_ga715b276f569abd0659cef3d6041ca97f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga715b276f569abd0659cef3d6041ca97f">CAN_F8R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga102d50c9df36acfccfadb2129cc7e933">CAN_F8R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga715b276f569abd0659cef3d6041ca97f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ee5e9d68190f0d41a5b8603d1933922" id="r_ga2ee5e9d68190f0d41a5b8603d1933922"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ee5e9d68190f0d41a5b8603d1933922">CAN_F8R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga715b276f569abd0659cef3d6041ca97f">CAN_F8R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga2ee5e9d68190f0d41a5b8603d1933922"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5650f6465760671e23d1ba17e7d1a9fb" id="r_ga5650f6465760671e23d1ba17e7d1a9fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5650f6465760671e23d1ba17e7d1a9fb">CAN_F8R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga5650f6465760671e23d1ba17e7d1a9fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bc83f8b713c699af6c4a058d97a0212" id="r_ga3bc83f8b713c699af6c4a058d97a0212"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bc83f8b713c699af6c4a058d97a0212">CAN_F8R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5650f6465760671e23d1ba17e7d1a9fb">CAN_F8R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga3bc83f8b713c699af6c4a058d97a0212"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66c636150cfad43a32652dba3ded8383" id="r_ga66c636150cfad43a32652dba3ded8383"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66c636150cfad43a32652dba3ded8383">CAN_F8R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bc83f8b713c699af6c4a058d97a0212">CAN_F8R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga66c636150cfad43a32652dba3ded8383"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6913723330621f154c8c69d67fc8eabf" id="r_ga6913723330621f154c8c69d67fc8eabf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6913723330621f154c8c69d67fc8eabf">CAN_F8R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga6913723330621f154c8c69d67fc8eabf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b34be24a3201f24c3c5fb3e4518496a" id="r_ga1b34be24a3201f24c3c5fb3e4518496a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b34be24a3201f24c3c5fb3e4518496a">CAN_F8R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6913723330621f154c8c69d67fc8eabf">CAN_F8R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga1b34be24a3201f24c3c5fb3e4518496a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fc81a4ee32f76ce3a6fdbb3fc49425c" id="r_ga0fc81a4ee32f76ce3a6fdbb3fc49425c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fc81a4ee32f76ce3a6fdbb3fc49425c">CAN_F8R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b34be24a3201f24c3c5fb3e4518496a">CAN_F8R2_FB7_Msk</a></td></tr>
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<tr class="separator:ga0fc81a4ee32f76ce3a6fdbb3fc49425c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e6f7d79c9bcd9461cca14ea772df10e" id="r_ga1e6f7d79c9bcd9461cca14ea772df10e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e6f7d79c9bcd9461cca14ea772df10e">CAN_F8R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga1e6f7d79c9bcd9461cca14ea772df10e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga246521830f06fc6e78fa76e3460c0c90" id="r_ga246521830f06fc6e78fa76e3460c0c90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga246521830f06fc6e78fa76e3460c0c90">CAN_F8R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e6f7d79c9bcd9461cca14ea772df10e">CAN_F8R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga246521830f06fc6e78fa76e3460c0c90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68a36336242e8259c779f1c8f4544737" id="r_ga68a36336242e8259c779f1c8f4544737"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68a36336242e8259c779f1c8f4544737">CAN_F8R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga246521830f06fc6e78fa76e3460c0c90">CAN_F8R2_FB8_Msk</a></td></tr>
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<tr class="separator:ga68a36336242e8259c779f1c8f4544737"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9ccf2f0df421c8136a57c0c60a28bd9" id="r_gab9ccf2f0df421c8136a57c0c60a28bd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9ccf2f0df421c8136a57c0c60a28bd9">CAN_F8R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gab9ccf2f0df421c8136a57c0c60a28bd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga109bccb45d80c850a1753d91810b17e6" id="r_ga109bccb45d80c850a1753d91810b17e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga109bccb45d80c850a1753d91810b17e6">CAN_F8R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9ccf2f0df421c8136a57c0c60a28bd9">CAN_F8R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga109bccb45d80c850a1753d91810b17e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0014717b3c4c65afb7542308980803d" id="r_gad0014717b3c4c65afb7542308980803d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0014717b3c4c65afb7542308980803d">CAN_F8R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga109bccb45d80c850a1753d91810b17e6">CAN_F8R2_FB9_Msk</a></td></tr>
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<tr class="separator:gad0014717b3c4c65afb7542308980803d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9536c00d19421f818bf61a281ca53852" id="r_ga9536c00d19421f818bf61a281ca53852"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9536c00d19421f818bf61a281ca53852">CAN_F8R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="memitem:gab4781d01da4573f59d5bf3d87e3f55c3" id="r_gab4781d01da4573f59d5bf3d87e3f55c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4781d01da4573f59d5bf3d87e3f55c3">CAN_F8R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9536c00d19421f818bf61a281ca53852">CAN_F8R2_FB10_Pos</a>)</td></tr>
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<tr class="memitem:ga315a7e30b95c05db01b7f56f4d825e62" id="r_ga315a7e30b95c05db01b7f56f4d825e62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga315a7e30b95c05db01b7f56f4d825e62">CAN_F8R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab4781d01da4573f59d5bf3d87e3f55c3">CAN_F8R2_FB10_Msk</a></td></tr>
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<tr class="memitem:gab2c8b3acb216b4a20646195872c91cc3" id="r_gab2c8b3acb216b4a20646195872c91cc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2c8b3acb216b4a20646195872c91cc3">CAN_F8R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga34eab8d93d53237b1f29ca2989602250" id="r_ga34eab8d93d53237b1f29ca2989602250"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34eab8d93d53237b1f29ca2989602250">CAN_F8R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab2c8b3acb216b4a20646195872c91cc3">CAN_F8R2_FB11_Pos</a>)</td></tr>
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<tr class="memitem:ga353aad2279bf6b72bd861f6c79253635" id="r_ga353aad2279bf6b72bd861f6c79253635"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga353aad2279bf6b72bd861f6c79253635">CAN_F8R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34eab8d93d53237b1f29ca2989602250">CAN_F8R2_FB11_Msk</a></td></tr>
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<tr class="memitem:ga35aa0762c3b9e705075fb629b92f3d52" id="r_ga35aa0762c3b9e705075fb629b92f3d52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35aa0762c3b9e705075fb629b92f3d52">CAN_F8R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="memitem:gaee44ebdb7cb153d4776813386c72d379" id="r_gaee44ebdb7cb153d4776813386c72d379"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee44ebdb7cb153d4776813386c72d379">CAN_F8R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga35aa0762c3b9e705075fb629b92f3d52">CAN_F8R2_FB12_Pos</a>)</td></tr>
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<tr class="memitem:ga25193c4b44d05db08ba40f0e0f2c45e1" id="r_ga25193c4b44d05db08ba40f0e0f2c45e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25193c4b44d05db08ba40f0e0f2c45e1">CAN_F8R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaee44ebdb7cb153d4776813386c72d379">CAN_F8R2_FB12_Msk</a></td></tr>
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<tr class="memitem:ga0af605c2d87e6f02f3bfee167a40b818" id="r_ga0af605c2d87e6f02f3bfee167a40b818"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0af605c2d87e6f02f3bfee167a40b818">CAN_F8R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0af605c2d87e6f02f3bfee167a40b818"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a533bc42a75cb20b6d2225af3259335" id="r_ga6a533bc42a75cb20b6d2225af3259335"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a533bc42a75cb20b6d2225af3259335">CAN_F8R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0af605c2d87e6f02f3bfee167a40b818">CAN_F8R2_FB13_Pos</a>)</td></tr>
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<tr class="memitem:ga4469bfc90525f84d9d04d3a4996997e6" id="r_ga4469bfc90525f84d9d04d3a4996997e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4469bfc90525f84d9d04d3a4996997e6">CAN_F8R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a533bc42a75cb20b6d2225af3259335">CAN_F8R2_FB13_Msk</a></td></tr>
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<tr class="memitem:ga52e8448ddc34d6068dad3607d6485056" id="r_ga52e8448ddc34d6068dad3607d6485056"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52e8448ddc34d6068dad3607d6485056">CAN_F8R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gaf5d8dd791898a26610ad5c99e04c7b85" id="r_gaf5d8dd791898a26610ad5c99e04c7b85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5d8dd791898a26610ad5c99e04c7b85">CAN_F8R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52e8448ddc34d6068dad3607d6485056">CAN_F8R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:gaf5d8dd791898a26610ad5c99e04c7b85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b17ebf3dd1e53d8417f955ebcf743b3" id="r_ga3b17ebf3dd1e53d8417f955ebcf743b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b17ebf3dd1e53d8417f955ebcf743b3">CAN_F8R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5d8dd791898a26610ad5c99e04c7b85">CAN_F8R2_FB14_Msk</a></td></tr>
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<tr class="separator:ga3b17ebf3dd1e53d8417f955ebcf743b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f802cc15926cffb97f3a6bc7642501d" id="r_ga0f802cc15926cffb97f3a6bc7642501d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f802cc15926cffb97f3a6bc7642501d">CAN_F8R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga0f802cc15926cffb97f3a6bc7642501d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9a10d9b3c535b4c04f30d1976a74003" id="r_gab9a10d9b3c535b4c04f30d1976a74003"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9a10d9b3c535b4c04f30d1976a74003">CAN_F8R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f802cc15926cffb97f3a6bc7642501d">CAN_F8R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:gab9a10d9b3c535b4c04f30d1976a74003"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6db6c2262434fc76213a441d8ce2edf1" id="r_ga6db6c2262434fc76213a441d8ce2edf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6db6c2262434fc76213a441d8ce2edf1">CAN_F8R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9a10d9b3c535b4c04f30d1976a74003">CAN_F8R2_FB15_Msk</a></td></tr>
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<tr class="memitem:ga7064892926519c2643608a52959b7d19" id="r_ga7064892926519c2643608a52959b7d19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7064892926519c2643608a52959b7d19">CAN_F8R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga79a44278629e098fdeefef5c6e699a21" id="r_ga79a44278629e098fdeefef5c6e699a21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79a44278629e098fdeefef5c6e699a21">CAN_F8R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7064892926519c2643608a52959b7d19">CAN_F8R2_FB16_Pos</a>)</td></tr>
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<tr class="memitem:ga8a1e1e9aa84af36845402d19236c1214" id="r_ga8a1e1e9aa84af36845402d19236c1214"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a1e1e9aa84af36845402d19236c1214">CAN_F8R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga79a44278629e098fdeefef5c6e699a21">CAN_F8R2_FB16_Msk</a></td></tr>
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<tr class="separator:ga8a1e1e9aa84af36845402d19236c1214"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7b91a4fcae3e6ffb8acace86ba3106a" id="r_gac7b91a4fcae3e6ffb8acace86ba3106a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7b91a4fcae3e6ffb8acace86ba3106a">CAN_F8R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="memitem:ga743f3fc9128154a5e10a49378b39dde0" id="r_ga743f3fc9128154a5e10a49378b39dde0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga743f3fc9128154a5e10a49378b39dde0">CAN_F8R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac7b91a4fcae3e6ffb8acace86ba3106a">CAN_F8R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga743f3fc9128154a5e10a49378b39dde0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0a9ee665444a6b42e98e0f988d1ba7a" id="r_gae0a9ee665444a6b42e98e0f988d1ba7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0a9ee665444a6b42e98e0f988d1ba7a">CAN_F8R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga743f3fc9128154a5e10a49378b39dde0">CAN_F8R2_FB17_Msk</a></td></tr>
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<tr class="separator:gae0a9ee665444a6b42e98e0f988d1ba7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49483e1f9418b80826fb30374977b711" id="r_ga49483e1f9418b80826fb30374977b711"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49483e1f9418b80826fb30374977b711">CAN_F8R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga6355102db61d562b19aea995401360f5" id="r_ga6355102db61d562b19aea995401360f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6355102db61d562b19aea995401360f5">CAN_F8R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga49483e1f9418b80826fb30374977b711">CAN_F8R2_FB18_Pos</a>)</td></tr>
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<tr class="memitem:ga16cde37565a3d3ec3a8c41013df6f6f1" id="r_ga16cde37565a3d3ec3a8c41013df6f6f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16cde37565a3d3ec3a8c41013df6f6f1">CAN_F8R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6355102db61d562b19aea995401360f5">CAN_F8R2_FB18_Msk</a></td></tr>
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<tr class="separator:ga16cde37565a3d3ec3a8c41013df6f6f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac0718c73bddee55cbf8c17f5e5393982" id="r_gac0718c73bddee55cbf8c17f5e5393982"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0718c73bddee55cbf8c17f5e5393982">CAN_F8R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="memitem:ga7fd103af2e8859f67477580800625162" id="r_ga7fd103af2e8859f67477580800625162"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fd103af2e8859f67477580800625162">CAN_F8R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac0718c73bddee55cbf8c17f5e5393982">CAN_F8R2_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga7fd103af2e8859f67477580800625162"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57ca000fea3be225ddf5f295437b6e36" id="r_ga57ca000fea3be225ddf5f295437b6e36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57ca000fea3be225ddf5f295437b6e36">CAN_F8R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7fd103af2e8859f67477580800625162">CAN_F8R2_FB19_Msk</a></td></tr>
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<tr class="separator:ga57ca000fea3be225ddf5f295437b6e36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c8ae876dd909a399bd06bca0e991f9d" id="r_ga5c8ae876dd909a399bd06bca0e991f9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c8ae876dd909a399bd06bca0e991f9d">CAN_F8R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga5c8ae876dd909a399bd06bca0e991f9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac32a8af72eea61e6976bb97fdff7fe51" id="r_gac32a8af72eea61e6976bb97fdff7fe51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac32a8af72eea61e6976bb97fdff7fe51">CAN_F8R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c8ae876dd909a399bd06bca0e991f9d">CAN_F8R2_FB20_Pos</a>)</td></tr>
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<tr class="memitem:gad60ee9ebdce23be6d2adca113ca918e8" id="r_gad60ee9ebdce23be6d2adca113ca918e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad60ee9ebdce23be6d2adca113ca918e8">CAN_F8R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac32a8af72eea61e6976bb97fdff7fe51">CAN_F8R2_FB20_Msk</a></td></tr>
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<tr class="memitem:ga36935ee8104559d55726f7a19ccc510e" id="r_ga36935ee8104559d55726f7a19ccc510e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36935ee8104559d55726f7a19ccc510e">CAN_F8R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="memitem:ga47bb6e52fcfdf43778db13faf53a6591" id="r_ga47bb6e52fcfdf43778db13faf53a6591"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47bb6e52fcfdf43778db13faf53a6591">CAN_F8R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga36935ee8104559d55726f7a19ccc510e">CAN_F8R2_FB21_Pos</a>)</td></tr>
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<tr class="memitem:gae186c9794783eb47b460532801afe43a" id="r_gae186c9794783eb47b460532801afe43a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae186c9794783eb47b460532801afe43a">CAN_F8R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47bb6e52fcfdf43778db13faf53a6591">CAN_F8R2_FB21_Msk</a></td></tr>
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<tr class="separator:gae186c9794783eb47b460532801afe43a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad26f6f6f8960a65ceac0a9ffb52c075" id="r_gaad26f6f6f8960a65ceac0a9ffb52c075"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad26f6f6f8960a65ceac0a9ffb52c075">CAN_F8R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gaad26f6f6f8960a65ceac0a9ffb52c075"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d5d496538d2bf3157c80523c0c5fb45" id="r_ga1d5d496538d2bf3157c80523c0c5fb45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d5d496538d2bf3157c80523c0c5fb45">CAN_F8R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaad26f6f6f8960a65ceac0a9ffb52c075">CAN_F8R2_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga1d5d496538d2bf3157c80523c0c5fb45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga106a5e5b8ae8d683fcec85b076688f34" id="r_ga106a5e5b8ae8d683fcec85b076688f34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga106a5e5b8ae8d683fcec85b076688f34">CAN_F8R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d5d496538d2bf3157c80523c0c5fb45">CAN_F8R2_FB22_Msk</a></td></tr>
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<tr class="separator:ga106a5e5b8ae8d683fcec85b076688f34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6a23988caae50f093de7fd6ee0442fa" id="r_gaa6a23988caae50f093de7fd6ee0442fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6a23988caae50f093de7fd6ee0442fa">CAN_F8R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gaa6a23988caae50f093de7fd6ee0442fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa768932cd5eef5a2ee54bfe8a0ac41ea" id="r_gaa768932cd5eef5a2ee54bfe8a0ac41ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa768932cd5eef5a2ee54bfe8a0ac41ea">CAN_F8R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6a23988caae50f093de7fd6ee0442fa">CAN_F8R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:gaa768932cd5eef5a2ee54bfe8a0ac41ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1643a77c219a9b2706f438c5123bccc8" id="r_ga1643a77c219a9b2706f438c5123bccc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1643a77c219a9b2706f438c5123bccc8">CAN_F8R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa768932cd5eef5a2ee54bfe8a0ac41ea">CAN_F8R2_FB23_Msk</a></td></tr>
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<tr class="separator:ga1643a77c219a9b2706f438c5123bccc8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3064ef4c61853f56528fb7649e723d4f" id="r_ga3064ef4c61853f56528fb7649e723d4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3064ef4c61853f56528fb7649e723d4f">CAN_F8R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga3064ef4c61853f56528fb7649e723d4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0989578ce3e5a1a533853538f3b649ff" id="r_ga0989578ce3e5a1a533853538f3b649ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0989578ce3e5a1a533853538f3b649ff">CAN_F8R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3064ef4c61853f56528fb7649e723d4f">CAN_F8R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga0989578ce3e5a1a533853538f3b649ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab21aa6ed09bed09347e07dbcbd0e9e93" id="r_gab21aa6ed09bed09347e07dbcbd0e9e93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab21aa6ed09bed09347e07dbcbd0e9e93">CAN_F8R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0989578ce3e5a1a533853538f3b649ff">CAN_F8R2_FB24_Msk</a></td></tr>
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<tr class="separator:gab21aa6ed09bed09347e07dbcbd0e9e93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a918c2c68e3e3a6ed3208377e7eb11c" id="r_ga1a918c2c68e3e3a6ed3208377e7eb11c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a918c2c68e3e3a6ed3208377e7eb11c">CAN_F8R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga1a918c2c68e3e3a6ed3208377e7eb11c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5a4af539b9ed1e260226c5a2f4c8242" id="r_gab5a4af539b9ed1e260226c5a2f4c8242"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5a4af539b9ed1e260226c5a2f4c8242">CAN_F8R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a918c2c68e3e3a6ed3208377e7eb11c">CAN_F8R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:gab5a4af539b9ed1e260226c5a2f4c8242"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8267e4cdc484abd75634469f9b255c5" id="r_gab8267e4cdc484abd75634469f9b255c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8267e4cdc484abd75634469f9b255c5">CAN_F8R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab5a4af539b9ed1e260226c5a2f4c8242">CAN_F8R2_FB25_Msk</a></td></tr>
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<tr class="separator:gab8267e4cdc484abd75634469f9b255c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a749b77630a78e7ab323f7f7fcd1930" id="r_ga8a749b77630a78e7ab323f7f7fcd1930"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a749b77630a78e7ab323f7f7fcd1930">CAN_F8R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga8a749b77630a78e7ab323f7f7fcd1930"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d064f4e04559c8ceeb38759b0332381" id="r_ga2d064f4e04559c8ceeb38759b0332381"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d064f4e04559c8ceeb38759b0332381">CAN_F8R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a749b77630a78e7ab323f7f7fcd1930">CAN_F8R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga2d064f4e04559c8ceeb38759b0332381"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga697d286473e81666c91f28e853aab4ad" id="r_ga697d286473e81666c91f28e853aab4ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga697d286473e81666c91f28e853aab4ad">CAN_F8R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d064f4e04559c8ceeb38759b0332381">CAN_F8R2_FB26_Msk</a></td></tr>
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<tr class="separator:ga697d286473e81666c91f28e853aab4ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cdc04f6f8ebf42d24d0ea4ad895205e" id="r_ga6cdc04f6f8ebf42d24d0ea4ad895205e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cdc04f6f8ebf42d24d0ea4ad895205e">CAN_F8R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga6cdc04f6f8ebf42d24d0ea4ad895205e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11bcaf39d0176157117636c373492ded" id="r_ga11bcaf39d0176157117636c373492ded"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11bcaf39d0176157117636c373492ded">CAN_F8R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cdc04f6f8ebf42d24d0ea4ad895205e">CAN_F8R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga11bcaf39d0176157117636c373492ded"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga295c26638700a849ee3c6504caf6ceab" id="r_ga295c26638700a849ee3c6504caf6ceab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga295c26638700a849ee3c6504caf6ceab">CAN_F8R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga11bcaf39d0176157117636c373492ded">CAN_F8R2_FB27_Msk</a></td></tr>
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<tr class="separator:ga295c26638700a849ee3c6504caf6ceab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb1387b35a958f97ce27f663dfe35c06" id="r_gadb1387b35a958f97ce27f663dfe35c06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb1387b35a958f97ce27f663dfe35c06">CAN_F8R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:gadb1387b35a958f97ce27f663dfe35c06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b60416465405bc628ede32f1ca22221" id="r_ga2b60416465405bc628ede32f1ca22221"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b60416465405bc628ede32f1ca22221">CAN_F8R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb1387b35a958f97ce27f663dfe35c06">CAN_F8R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:ga2b60416465405bc628ede32f1ca22221"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f8469008983b405bfc5855258f4f6e6" id="r_ga0f8469008983b405bfc5855258f4f6e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f8469008983b405bfc5855258f4f6e6">CAN_F8R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b60416465405bc628ede32f1ca22221">CAN_F8R2_FB28_Msk</a></td></tr>
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<tr class="separator:ga0f8469008983b405bfc5855258f4f6e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga910e2428c8fa737c1779f3536d97bff1" id="r_ga910e2428c8fa737c1779f3536d97bff1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga910e2428c8fa737c1779f3536d97bff1">CAN_F8R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga910e2428c8fa737c1779f3536d97bff1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae62518d43230d7fe0907da3068092020" id="r_gae62518d43230d7fe0907da3068092020"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae62518d43230d7fe0907da3068092020">CAN_F8R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga910e2428c8fa737c1779f3536d97bff1">CAN_F8R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:gae62518d43230d7fe0907da3068092020"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad18d894a75ebe73c0185d905cfb81dbf" id="r_gad18d894a75ebe73c0185d905cfb81dbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad18d894a75ebe73c0185d905cfb81dbf">CAN_F8R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae62518d43230d7fe0907da3068092020">CAN_F8R2_FB29_Msk</a></td></tr>
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<tr class="separator:gad18d894a75ebe73c0185d905cfb81dbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae383ae7f7183c4fe7ce61ffb0e90b8aa" id="r_gae383ae7f7183c4fe7ce61ffb0e90b8aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae383ae7f7183c4fe7ce61ffb0e90b8aa">CAN_F8R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:gae383ae7f7183c4fe7ce61ffb0e90b8aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1cd28b7dd676bb4df664b0f4c886dba" id="r_gaf1cd28b7dd676bb4df664b0f4c886dba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1cd28b7dd676bb4df664b0f4c886dba">CAN_F8R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae383ae7f7183c4fe7ce61ffb0e90b8aa">CAN_F8R2_FB30_Pos</a>)</td></tr>
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<tr class="separator:gaf1cd28b7dd676bb4df664b0f4c886dba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccdf92a69572b56641ddd2967c034a7a" id="r_gaccdf92a69572b56641ddd2967c034a7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccdf92a69572b56641ddd2967c034a7a">CAN_F8R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1cd28b7dd676bb4df664b0f4c886dba">CAN_F8R2_FB30_Msk</a></td></tr>
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<tr class="separator:gaccdf92a69572b56641ddd2967c034a7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45effc10b4b4f084d64ee099dee2537d" id="r_ga45effc10b4b4f084d64ee099dee2537d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45effc10b4b4f084d64ee099dee2537d">CAN_F8R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga45effc10b4b4f084d64ee099dee2537d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cdbb1cd26bdd6c1690ac3b208a27898" id="r_ga3cdbb1cd26bdd6c1690ac3b208a27898"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cdbb1cd26bdd6c1690ac3b208a27898">CAN_F8R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga45effc10b4b4f084d64ee099dee2537d">CAN_F8R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga3cdbb1cd26bdd6c1690ac3b208a27898"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0636c9c9fd84e5e8d12e78f236f2a56c" id="r_ga0636c9c9fd84e5e8d12e78f236f2a56c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0636c9c9fd84e5e8d12e78f236f2a56c">CAN_F8R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cdbb1cd26bdd6c1690ac3b208a27898">CAN_F8R2_FB31_Msk</a></td></tr>
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<tr class="memitem:ga71fb77883884a56d1b3e9d2029007d02" id="r_ga71fb77883884a56d1b3e9d2029007d02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71fb77883884a56d1b3e9d2029007d02">CAN_F9R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga47309fd6134f2abe4e3b1b496093d9be" id="r_ga47309fd6134f2abe4e3b1b496093d9be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47309fd6134f2abe4e3b1b496093d9be">CAN_F9R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71fb77883884a56d1b3e9d2029007d02">CAN_F9R2_FB0_Pos</a>)</td></tr>
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<tr class="memitem:gaa1209cec0d1199b7f74bb2e2b1cca424" id="r_gaa1209cec0d1199b7f74bb2e2b1cca424"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1209cec0d1199b7f74bb2e2b1cca424">CAN_F9R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47309fd6134f2abe4e3b1b496093d9be">CAN_F9R2_FB0_Msk</a></td></tr>
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<tr class="separator:gaa1209cec0d1199b7f74bb2e2b1cca424"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1b8c8d47bf8d4009b79c69e629106d8" id="r_gaa1b8c8d47bf8d4009b79c69e629106d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1b8c8d47bf8d4009b79c69e629106d8">CAN_F9R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="memitem:gadfe55444ba47900acdea02a8e64db98b" id="r_gadfe55444ba47900acdea02a8e64db98b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfe55444ba47900acdea02a8e64db98b">CAN_F9R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1b8c8d47bf8d4009b79c69e629106d8">CAN_F9R2_FB1_Pos</a>)</td></tr>
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<tr class="memitem:ga9fd983be0f74b7f183261f21cd2f6910" id="r_ga9fd983be0f74b7f183261f21cd2f6910"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fd983be0f74b7f183261f21cd2f6910">CAN_F9R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadfe55444ba47900acdea02a8e64db98b">CAN_F9R2_FB1_Msk</a></td></tr>
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<tr class="separator:ga9fd983be0f74b7f183261f21cd2f6910"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36e5b680c042a6052bfd32e8ae58b221" id="r_ga36e5b680c042a6052bfd32e8ae58b221"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36e5b680c042a6052bfd32e8ae58b221">CAN_F9R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga36e5b680c042a6052bfd32e8ae58b221"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e3aeaa699aed8591a458dbdb8fd3358" id="r_ga5e3aeaa699aed8591a458dbdb8fd3358"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e3aeaa699aed8591a458dbdb8fd3358">CAN_F9R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga36e5b680c042a6052bfd32e8ae58b221">CAN_F9R2_FB2_Pos</a>)</td></tr>
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<tr class="memitem:ga2e363da951c1191e733a8bc603cda3f5" id="r_ga2e363da951c1191e733a8bc603cda3f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e363da951c1191e733a8bc603cda3f5">CAN_F9R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e3aeaa699aed8591a458dbdb8fd3358">CAN_F9R2_FB2_Msk</a></td></tr>
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<tr class="separator:ga2e363da951c1191e733a8bc603cda3f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c3e1cc66212316557b21298d3852b22" id="r_ga2c3e1cc66212316557b21298d3852b22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c3e1cc66212316557b21298d3852b22">CAN_F9R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga2c3e1cc66212316557b21298d3852b22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9bf0ad567bc6a89528616adb3d30cc0" id="r_gac9bf0ad567bc6a89528616adb3d30cc0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9bf0ad567bc6a89528616adb3d30cc0">CAN_F9R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c3e1cc66212316557b21298d3852b22">CAN_F9R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:gac9bf0ad567bc6a89528616adb3d30cc0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabab5a59d405ae1684853988e95ab9844" id="r_gabab5a59d405ae1684853988e95ab9844"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabab5a59d405ae1684853988e95ab9844">CAN_F9R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9bf0ad567bc6a89528616adb3d30cc0">CAN_F9R2_FB3_Msk</a></td></tr>
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<tr class="memitem:gadc1f6b4960d803c1e388f0f6a7525736" id="r_gadc1f6b4960d803c1e388f0f6a7525736"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc1f6b4960d803c1e388f0f6a7525736">CAN_F9R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gadc1f6b4960d803c1e388f0f6a7525736"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5010d303de1ed187fcf3d663cc5b7b3a" id="r_ga5010d303de1ed187fcf3d663cc5b7b3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5010d303de1ed187fcf3d663cc5b7b3a">CAN_F9R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadc1f6b4960d803c1e388f0f6a7525736">CAN_F9R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga5010d303de1ed187fcf3d663cc5b7b3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b5b46878001f43618c726b3429e4b50" id="r_ga4b5b46878001f43618c726b3429e4b50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b5b46878001f43618c726b3429e4b50">CAN_F9R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5010d303de1ed187fcf3d663cc5b7b3a">CAN_F9R2_FB4_Msk</a></td></tr>
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<tr class="separator:ga4b5b46878001f43618c726b3429e4b50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9555447cbcc79096f5ae9e132455e2c6" id="r_ga9555447cbcc79096f5ae9e132455e2c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9555447cbcc79096f5ae9e132455e2c6">CAN_F9R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga9555447cbcc79096f5ae9e132455e2c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga596e424fe2e4186174d148aeef611074" id="r_ga596e424fe2e4186174d148aeef611074"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga596e424fe2e4186174d148aeef611074">CAN_F9R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9555447cbcc79096f5ae9e132455e2c6">CAN_F9R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga596e424fe2e4186174d148aeef611074"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga582895a48cfeb8d7ecf6c9757ba0aa39" id="r_ga582895a48cfeb8d7ecf6c9757ba0aa39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga582895a48cfeb8d7ecf6c9757ba0aa39">CAN_F9R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga596e424fe2e4186174d148aeef611074">CAN_F9R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga582895a48cfeb8d7ecf6c9757ba0aa39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0961df6b41382621852dc673c9101f39" id="r_ga0961df6b41382621852dc673c9101f39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0961df6b41382621852dc673c9101f39">CAN_F9R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga0961df6b41382621852dc673c9101f39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga652ee4940983c9766b517598ad270e1f" id="r_ga652ee4940983c9766b517598ad270e1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga652ee4940983c9766b517598ad270e1f">CAN_F9R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0961df6b41382621852dc673c9101f39">CAN_F9R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga652ee4940983c9766b517598ad270e1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe18a44ac1a9c4cf2a6e94bb946af17f" id="r_gafe18a44ac1a9c4cf2a6e94bb946af17f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe18a44ac1a9c4cf2a6e94bb946af17f">CAN_F9R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga652ee4940983c9766b517598ad270e1f">CAN_F9R2_FB6_Msk</a></td></tr>
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<tr class="separator:gafe18a44ac1a9c4cf2a6e94bb946af17f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f7b07d1129f4ea3727306744500577a" id="r_ga2f7b07d1129f4ea3727306744500577a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f7b07d1129f4ea3727306744500577a">CAN_F9R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga2f7b07d1129f4ea3727306744500577a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed416d6141752c65110daae0c617859a" id="r_gaed416d6141752c65110daae0c617859a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed416d6141752c65110daae0c617859a">CAN_F9R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f7b07d1129f4ea3727306744500577a">CAN_F9R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:gaed416d6141752c65110daae0c617859a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae497ffa0ef246a52e57a394fa57e616d" id="r_gae497ffa0ef246a52e57a394fa57e616d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae497ffa0ef246a52e57a394fa57e616d">CAN_F9R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaed416d6141752c65110daae0c617859a">CAN_F9R2_FB7_Msk</a></td></tr>
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<tr class="separator:gae497ffa0ef246a52e57a394fa57e616d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff37f998935141f0cb7203a5b74baeea" id="r_gaff37f998935141f0cb7203a5b74baeea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff37f998935141f0cb7203a5b74baeea">CAN_F9R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaff37f998935141f0cb7203a5b74baeea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad301a470b47c85751c573fc3579d91a9" id="r_gad301a470b47c85751c573fc3579d91a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad301a470b47c85751c573fc3579d91a9">CAN_F9R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaff37f998935141f0cb7203a5b74baeea">CAN_F9R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:gad301a470b47c85751c573fc3579d91a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4eedc431183ceae7240d11afc05bacfa" id="r_ga4eedc431183ceae7240d11afc05bacfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4eedc431183ceae7240d11afc05bacfa">CAN_F9R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad301a470b47c85751c573fc3579d91a9">CAN_F9R2_FB8_Msk</a></td></tr>
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<tr class="separator:ga4eedc431183ceae7240d11afc05bacfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga232ef1a0d6455d0f6afe6ae0f7c5a911" id="r_ga232ef1a0d6455d0f6afe6ae0f7c5a911"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga232ef1a0d6455d0f6afe6ae0f7c5a911">CAN_F9R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga232ef1a0d6455d0f6afe6ae0f7c5a911"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa912a018c3cc0adcbeacd61b6e5871a6" id="r_gaa912a018c3cc0adcbeacd61b6e5871a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa912a018c3cc0adcbeacd61b6e5871a6">CAN_F9R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga232ef1a0d6455d0f6afe6ae0f7c5a911">CAN_F9R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:gaa912a018c3cc0adcbeacd61b6e5871a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71d1294050a77f52ecd4b00568cd7477" id="r_ga71d1294050a77f52ecd4b00568cd7477"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71d1294050a77f52ecd4b00568cd7477">CAN_F9R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa912a018c3cc0adcbeacd61b6e5871a6">CAN_F9R2_FB9_Msk</a></td></tr>
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<tr class="separator:ga71d1294050a77f52ecd4b00568cd7477"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91dd86a4bf1da1e33c7b56503eebbd52" id="r_ga91dd86a4bf1da1e33c7b56503eebbd52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91dd86a4bf1da1e33c7b56503eebbd52">CAN_F9R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga91dd86a4bf1da1e33c7b56503eebbd52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0f169b5d13d9d6d69d89d99c8451ebd" id="r_gaf0f169b5d13d9d6d69d89d99c8451ebd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0f169b5d13d9d6d69d89d99c8451ebd">CAN_F9R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga91dd86a4bf1da1e33c7b56503eebbd52">CAN_F9R2_FB10_Pos</a>)</td></tr>
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<tr class="memitem:ga5adc0ffeba391461d887f5d176a9b5bd" id="r_ga5adc0ffeba391461d887f5d176a9b5bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5adc0ffeba391461d887f5d176a9b5bd">CAN_F9R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0f169b5d13d9d6d69d89d99c8451ebd">CAN_F9R2_FB10_Msk</a></td></tr>
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<tr class="separator:ga5adc0ffeba391461d887f5d176a9b5bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae624263208ca55d8690f216d3a4dfb78" id="r_gae624263208ca55d8690f216d3a4dfb78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae624263208ca55d8690f216d3a4dfb78">CAN_F9R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga5b87e7eba6f9fbe4a1e390599703e4ea" id="r_ga5b87e7eba6f9fbe4a1e390599703e4ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b87e7eba6f9fbe4a1e390599703e4ea">CAN_F9R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae624263208ca55d8690f216d3a4dfb78">CAN_F9R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga5b87e7eba6f9fbe4a1e390599703e4ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga989f1dea5a35e78b08649ac699955563" id="r_ga989f1dea5a35e78b08649ac699955563"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga989f1dea5a35e78b08649ac699955563">CAN_F9R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b87e7eba6f9fbe4a1e390599703e4ea">CAN_F9R2_FB11_Msk</a></td></tr>
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<tr class="separator:ga989f1dea5a35e78b08649ac699955563"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6860cb0d3b72432d7e35b0ade6a3d05" id="r_gad6860cb0d3b72432d7e35b0ade6a3d05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6860cb0d3b72432d7e35b0ade6a3d05">CAN_F9R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gad6860cb0d3b72432d7e35b0ade6a3d05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b961aa158542f370fd755e37e3ebbf7" id="r_ga9b961aa158542f370fd755e37e3ebbf7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b961aa158542f370fd755e37e3ebbf7">CAN_F9R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad6860cb0d3b72432d7e35b0ade6a3d05">CAN_F9R2_FB12_Pos</a>)</td></tr>
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<tr class="separator:ga9b961aa158542f370fd755e37e3ebbf7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b71e1b7db02ef8c5853534921b33aee" id="r_ga0b71e1b7db02ef8c5853534921b33aee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b71e1b7db02ef8c5853534921b33aee">CAN_F9R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b961aa158542f370fd755e37e3ebbf7">CAN_F9R2_FB12_Msk</a></td></tr>
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<tr class="separator:ga0b71e1b7db02ef8c5853534921b33aee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5031b931df96b65727ccbb5298e678c1" id="r_ga5031b931df96b65727ccbb5298e678c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5031b931df96b65727ccbb5298e678c1">CAN_F9R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga5031b931df96b65727ccbb5298e678c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01e88250b1d9d44f23df2ddc46397574" id="r_ga01e88250b1d9d44f23df2ddc46397574"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01e88250b1d9d44f23df2ddc46397574">CAN_F9R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5031b931df96b65727ccbb5298e678c1">CAN_F9R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga01e88250b1d9d44f23df2ddc46397574"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48cff2713910823bbf9c8aeb399d6695" id="r_ga48cff2713910823bbf9c8aeb399d6695"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48cff2713910823bbf9c8aeb399d6695">CAN_F9R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga01e88250b1d9d44f23df2ddc46397574">CAN_F9R2_FB13_Msk</a></td></tr>
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<tr class="separator:ga48cff2713910823bbf9c8aeb399d6695"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88f67bd4804724913a1ace948970d584" id="r_ga88f67bd4804724913a1ace948970d584"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88f67bd4804724913a1ace948970d584">CAN_F9R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga88f67bd4804724913a1ace948970d584"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2659b21a47fe2b7475163ef583622c7" id="r_gaa2659b21a47fe2b7475163ef583622c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2659b21a47fe2b7475163ef583622c7">CAN_F9R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga88f67bd4804724913a1ace948970d584">CAN_F9R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:gaa2659b21a47fe2b7475163ef583622c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9e0057c4eb0f7238d2ec98ae0702ff3" id="r_gab9e0057c4eb0f7238d2ec98ae0702ff3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9e0057c4eb0f7238d2ec98ae0702ff3">CAN_F9R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2659b21a47fe2b7475163ef583622c7">CAN_F9R2_FB14_Msk</a></td></tr>
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<tr class="separator:gab9e0057c4eb0f7238d2ec98ae0702ff3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69a42974dfe7527cbb7e2db8d402393b" id="r_ga69a42974dfe7527cbb7e2db8d402393b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69a42974dfe7527cbb7e2db8d402393b">CAN_F9R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga69a42974dfe7527cbb7e2db8d402393b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga034e40bc2fcebd32d4d77b2b38c68dda" id="r_ga034e40bc2fcebd32d4d77b2b38c68dda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga034e40bc2fcebd32d4d77b2b38c68dda">CAN_F9R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69a42974dfe7527cbb7e2db8d402393b">CAN_F9R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga034e40bc2fcebd32d4d77b2b38c68dda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc16f71c9ee3bc56be17f7488c1df807" id="r_gacc16f71c9ee3bc56be17f7488c1df807"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc16f71c9ee3bc56be17f7488c1df807">CAN_F9R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga034e40bc2fcebd32d4d77b2b38c68dda">CAN_F9R2_FB15_Msk</a></td></tr>
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<tr class="separator:gacc16f71c9ee3bc56be17f7488c1df807"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f2ba5f0426b80b58ec6842414929185" id="r_ga3f2ba5f0426b80b58ec6842414929185"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f2ba5f0426b80b58ec6842414929185">CAN_F9R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga3f2ba5f0426b80b58ec6842414929185"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacae78b5a3198b22b6590676496caa801" id="r_gacae78b5a3198b22b6590676496caa801"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacae78b5a3198b22b6590676496caa801">CAN_F9R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f2ba5f0426b80b58ec6842414929185">CAN_F9R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:gacae78b5a3198b22b6590676496caa801"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3909a33262113171b7d4dc11fcf8c3b1" id="r_ga3909a33262113171b7d4dc11fcf8c3b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3909a33262113171b7d4dc11fcf8c3b1">CAN_F9R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacae78b5a3198b22b6590676496caa801">CAN_F9R2_FB16_Msk</a></td></tr>
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<tr class="separator:ga3909a33262113171b7d4dc11fcf8c3b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e3fde8ece69886d20cd8e258f981645" id="r_ga5e3fde8ece69886d20cd8e258f981645"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e3fde8ece69886d20cd8e258f981645">CAN_F9R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga5e3fde8ece69886d20cd8e258f981645"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30db50cc21514e923c0bf91374491e91" id="r_ga30db50cc21514e923c0bf91374491e91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30db50cc21514e923c0bf91374491e91">CAN_F9R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e3fde8ece69886d20cd8e258f981645">CAN_F9R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga30db50cc21514e923c0bf91374491e91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cead3f8d10075aa34c9446859356e2d" id="r_ga8cead3f8d10075aa34c9446859356e2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cead3f8d10075aa34c9446859356e2d">CAN_F9R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga30db50cc21514e923c0bf91374491e91">CAN_F9R2_FB17_Msk</a></td></tr>
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<tr class="separator:ga8cead3f8d10075aa34c9446859356e2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17263ecd2c5f80d8c32b697f375bff23" id="r_ga17263ecd2c5f80d8c32b697f375bff23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17263ecd2c5f80d8c32b697f375bff23">CAN_F9R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga17263ecd2c5f80d8c32b697f375bff23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac07c3cc02fa2a02058063f3fed95f97c" id="r_gac07c3cc02fa2a02058063f3fed95f97c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac07c3cc02fa2a02058063f3fed95f97c">CAN_F9R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17263ecd2c5f80d8c32b697f375bff23">CAN_F9R2_FB18_Pos</a>)</td></tr>
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<tr class="separator:gac07c3cc02fa2a02058063f3fed95f97c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7730d43a2cf07a1568ed738a4f69692" id="r_gaf7730d43a2cf07a1568ed738a4f69692"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7730d43a2cf07a1568ed738a4f69692">CAN_F9R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac07c3cc02fa2a02058063f3fed95f97c">CAN_F9R2_FB18_Msk</a></td></tr>
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<tr class="separator:gaf7730d43a2cf07a1568ed738a4f69692"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19083a2e70e921dcb5e560c236c19b97" id="r_ga19083a2e70e921dcb5e560c236c19b97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19083a2e70e921dcb5e560c236c19b97">CAN_F9R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga19083a2e70e921dcb5e560c236c19b97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga280fd7273494894b41cf8b3e05a94423" id="r_ga280fd7273494894b41cf8b3e05a94423"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga280fd7273494894b41cf8b3e05a94423">CAN_F9R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga19083a2e70e921dcb5e560c236c19b97">CAN_F9R2_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga280fd7273494894b41cf8b3e05a94423"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b2f5ba8403cbd679694cf9665e2690f" id="r_ga6b2f5ba8403cbd679694cf9665e2690f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b2f5ba8403cbd679694cf9665e2690f">CAN_F9R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga280fd7273494894b41cf8b3e05a94423">CAN_F9R2_FB19_Msk</a></td></tr>
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<tr class="separator:ga6b2f5ba8403cbd679694cf9665e2690f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcd8dc4d422b78b03a7190665e89fc7d" id="r_gafcd8dc4d422b78b03a7190665e89fc7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcd8dc4d422b78b03a7190665e89fc7d">CAN_F9R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gafcd8dc4d422b78b03a7190665e89fc7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ebf7e69a5cbb23be0d72df90d938455" id="r_ga5ebf7e69a5cbb23be0d72df90d938455"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ebf7e69a5cbb23be0d72df90d938455">CAN_F9R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcd8dc4d422b78b03a7190665e89fc7d">CAN_F9R2_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga5ebf7e69a5cbb23be0d72df90d938455"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca5a17ed59696ed0572b80767c4bef81" id="r_gaca5a17ed59696ed0572b80767c4bef81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca5a17ed59696ed0572b80767c4bef81">CAN_F9R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ebf7e69a5cbb23be0d72df90d938455">CAN_F9R2_FB20_Msk</a></td></tr>
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<tr class="separator:gaca5a17ed59696ed0572b80767c4bef81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ee45801f88c81aa88d1dcb0cb13da8d" id="r_ga7ee45801f88c81aa88d1dcb0cb13da8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ee45801f88c81aa88d1dcb0cb13da8d">CAN_F9R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga7ee45801f88c81aa88d1dcb0cb13da8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29e80a00a8a175f05ccec5b2465f707f" id="r_ga29e80a00a8a175f05ccec5b2465f707f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29e80a00a8a175f05ccec5b2465f707f">CAN_F9R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ee45801f88c81aa88d1dcb0cb13da8d">CAN_F9R2_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga29e80a00a8a175f05ccec5b2465f707f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac318672024cefb98843d473cbb2d46b2" id="r_gac318672024cefb98843d473cbb2d46b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac318672024cefb98843d473cbb2d46b2">CAN_F9R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga29e80a00a8a175f05ccec5b2465f707f">CAN_F9R2_FB21_Msk</a></td></tr>
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<tr class="separator:gac318672024cefb98843d473cbb2d46b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a828c3ecaa65b06ed7262618009f645" id="r_ga0a828c3ecaa65b06ed7262618009f645"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a828c3ecaa65b06ed7262618009f645">CAN_F9R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga0a828c3ecaa65b06ed7262618009f645"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae2e762f3d91189614712c5f708c13ec" id="r_gaae2e762f3d91189614712c5f708c13ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae2e762f3d91189614712c5f708c13ec">CAN_F9R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a828c3ecaa65b06ed7262618009f645">CAN_F9R2_FB22_Pos</a>)</td></tr>
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<tr class="separator:gaae2e762f3d91189614712c5f708c13ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3523d55c8cf0a308fea4837b00f89abb" id="r_ga3523d55c8cf0a308fea4837b00f89abb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3523d55c8cf0a308fea4837b00f89abb">CAN_F9R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae2e762f3d91189614712c5f708c13ec">CAN_F9R2_FB22_Msk</a></td></tr>
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<tr class="separator:ga3523d55c8cf0a308fea4837b00f89abb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac77e06fc859440775bed41060185f84d" id="r_gac77e06fc859440775bed41060185f84d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac77e06fc859440775bed41060185f84d">CAN_F9R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gac77e06fc859440775bed41060185f84d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6411880c098bbbe9e746ae660f1d3643" id="r_ga6411880c098bbbe9e746ae660f1d3643"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6411880c098bbbe9e746ae660f1d3643">CAN_F9R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac77e06fc859440775bed41060185f84d">CAN_F9R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga6411880c098bbbe9e746ae660f1d3643"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21d8d812323030dd39f417318c36b8dc" id="r_ga21d8d812323030dd39f417318c36b8dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21d8d812323030dd39f417318c36b8dc">CAN_F9R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6411880c098bbbe9e746ae660f1d3643">CAN_F9R2_FB23_Msk</a></td></tr>
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<tr class="separator:ga21d8d812323030dd39f417318c36b8dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e3da3cb77f9bab0b9688ee8ac1ead87" id="r_ga5e3da3cb77f9bab0b9688ee8ac1ead87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e3da3cb77f9bab0b9688ee8ac1ead87">CAN_F9R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga5e3da3cb77f9bab0b9688ee8ac1ead87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9112971db909b1bf0bd272c687ca44ba" id="r_ga9112971db909b1bf0bd272c687ca44ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9112971db909b1bf0bd272c687ca44ba">CAN_F9R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e3da3cb77f9bab0b9688ee8ac1ead87">CAN_F9R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga9112971db909b1bf0bd272c687ca44ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga065bba6dde8a5b81b42c2618204bf0be" id="r_ga065bba6dde8a5b81b42c2618204bf0be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga065bba6dde8a5b81b42c2618204bf0be">CAN_F9R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9112971db909b1bf0bd272c687ca44ba">CAN_F9R2_FB24_Msk</a></td></tr>
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<tr class="separator:ga065bba6dde8a5b81b42c2618204bf0be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga784ec53e7bab49da60d9ede528c85b17" id="r_ga784ec53e7bab49da60d9ede528c85b17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga784ec53e7bab49da60d9ede528c85b17">CAN_F9R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga784ec53e7bab49da60d9ede528c85b17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a276cb2e015ee7b075eec7a16686ac3" id="r_ga0a276cb2e015ee7b075eec7a16686ac3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a276cb2e015ee7b075eec7a16686ac3">CAN_F9R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga784ec53e7bab49da60d9ede528c85b17">CAN_F9R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga0a276cb2e015ee7b075eec7a16686ac3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade5290535026c192f7e94a4cb98e48b4" id="r_gade5290535026c192f7e94a4cb98e48b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade5290535026c192f7e94a4cb98e48b4">CAN_F9R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a276cb2e015ee7b075eec7a16686ac3">CAN_F9R2_FB25_Msk</a></td></tr>
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<tr class="separator:gade5290535026c192f7e94a4cb98e48b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4802401202cdadbd984547f05b09fd1b" id="r_ga4802401202cdadbd984547f05b09fd1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4802401202cdadbd984547f05b09fd1b">CAN_F9R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga4802401202cdadbd984547f05b09fd1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga664cbbe2443064efe7fb3129550c226b" id="r_ga664cbbe2443064efe7fb3129550c226b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga664cbbe2443064efe7fb3129550c226b">CAN_F9R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4802401202cdadbd984547f05b09fd1b">CAN_F9R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga664cbbe2443064efe7fb3129550c226b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac7e7544d60c3084da344ee20ab6a760" id="r_gaac7e7544d60c3084da344ee20ab6a760"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac7e7544d60c3084da344ee20ab6a760">CAN_F9R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga664cbbe2443064efe7fb3129550c226b">CAN_F9R2_FB26_Msk</a></td></tr>
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<tr class="separator:gaac7e7544d60c3084da344ee20ab6a760"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f56af8f8de74632465471450552f8d5" id="r_ga8f56af8f8de74632465471450552f8d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f56af8f8de74632465471450552f8d5">CAN_F9R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga8f56af8f8de74632465471450552f8d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21473aad3bbd0a024b0e714c9bbf4e47" id="r_ga21473aad3bbd0a024b0e714c9bbf4e47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21473aad3bbd0a024b0e714c9bbf4e47">CAN_F9R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f56af8f8de74632465471450552f8d5">CAN_F9R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga21473aad3bbd0a024b0e714c9bbf4e47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae965845f1e45d1f45831be60829e63bc" id="r_gae965845f1e45d1f45831be60829e63bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae965845f1e45d1f45831be60829e63bc">CAN_F9R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga21473aad3bbd0a024b0e714c9bbf4e47">CAN_F9R2_FB27_Msk</a></td></tr>
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<tr class="separator:gae965845f1e45d1f45831be60829e63bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d4d14753760fee8b7edf9c281f43bfa" id="r_ga9d4d14753760fee8b7edf9c281f43bfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d4d14753760fee8b7edf9c281f43bfa">CAN_F9R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga9d4d14753760fee8b7edf9c281f43bfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23124d9ac50f080e32aebae3449ee1a0" id="r_ga23124d9ac50f080e32aebae3449ee1a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23124d9ac50f080e32aebae3449ee1a0">CAN_F9R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d4d14753760fee8b7edf9c281f43bfa">CAN_F9R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:ga23124d9ac50f080e32aebae3449ee1a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63bbecf009bf6bd61dc9e8fe0603da73" id="r_ga63bbecf009bf6bd61dc9e8fe0603da73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63bbecf009bf6bd61dc9e8fe0603da73">CAN_F9R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga23124d9ac50f080e32aebae3449ee1a0">CAN_F9R2_FB28_Msk</a></td></tr>
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<tr class="separator:ga63bbecf009bf6bd61dc9e8fe0603da73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9834ba7e7b11eff8cca5d8ad9845f03" id="r_gac9834ba7e7b11eff8cca5d8ad9845f03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9834ba7e7b11eff8cca5d8ad9845f03">CAN_F9R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:gac9834ba7e7b11eff8cca5d8ad9845f03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c149f89a9b7f6a847fc01fe55304dd2" id="r_ga5c149f89a9b7f6a847fc01fe55304dd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c149f89a9b7f6a847fc01fe55304dd2">CAN_F9R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9834ba7e7b11eff8cca5d8ad9845f03">CAN_F9R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:ga5c149f89a9b7f6a847fc01fe55304dd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga834cf606ef4b69b0c459b8cb9e836a9b" id="r_ga834cf606ef4b69b0c459b8cb9e836a9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga834cf606ef4b69b0c459b8cb9e836a9b">CAN_F9R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c149f89a9b7f6a847fc01fe55304dd2">CAN_F9R2_FB29_Msk</a></td></tr>
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<tr class="separator:ga834cf606ef4b69b0c459b8cb9e836a9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1765e9fda5089f19109be26e678e6e2d" id="r_ga1765e9fda5089f19109be26e678e6e2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1765e9fda5089f19109be26e678e6e2d">CAN_F9R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga1765e9fda5089f19109be26e678e6e2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76d278d95612c8049d4ade5a1a30fabe" id="r_ga76d278d95612c8049d4ade5a1a30fabe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76d278d95612c8049d4ade5a1a30fabe">CAN_F9R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1765e9fda5089f19109be26e678e6e2d">CAN_F9R2_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga76d278d95612c8049d4ade5a1a30fabe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c833e07b7a842ba7425291f628c9a11" id="r_ga9c833e07b7a842ba7425291f628c9a11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c833e07b7a842ba7425291f628c9a11">CAN_F9R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga76d278d95612c8049d4ade5a1a30fabe">CAN_F9R2_FB30_Msk</a></td></tr>
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<tr class="separator:ga9c833e07b7a842ba7425291f628c9a11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e51a4af2c6e972bfd49080723c0ac48" id="r_ga0e51a4af2c6e972bfd49080723c0ac48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e51a4af2c6e972bfd49080723c0ac48">CAN_F9R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga0e51a4af2c6e972bfd49080723c0ac48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3863b24c5580c3f1dcf4dcfccb08796f" id="r_ga3863b24c5580c3f1dcf4dcfccb08796f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3863b24c5580c3f1dcf4dcfccb08796f">CAN_F9R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e51a4af2c6e972bfd49080723c0ac48">CAN_F9R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga3863b24c5580c3f1dcf4dcfccb08796f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18ef7c7bae75406a267e6a333c549a9f" id="r_ga18ef7c7bae75406a267e6a333c549a9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18ef7c7bae75406a267e6a333c549a9f">CAN_F9R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3863b24c5580c3f1dcf4dcfccb08796f">CAN_F9R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga18ef7c7bae75406a267e6a333c549a9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga067cb17fa931fc8ec805a317221d553f" id="r_ga067cb17fa931fc8ec805a317221d553f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga067cb17fa931fc8ec805a317221d553f">CAN_F10R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gac774a841f16adc00aaa2ec9fc7e19fcb" id="r_gac774a841f16adc00aaa2ec9fc7e19fcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac774a841f16adc00aaa2ec9fc7e19fcb">CAN_F10R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga067cb17fa931fc8ec805a317221d553f">CAN_F10R2_FB0_Pos</a>)</td></tr>
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<tr class="memitem:ga616898121d5befed0eb5ab61492872f2" id="r_ga616898121d5befed0eb5ab61492872f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga616898121d5befed0eb5ab61492872f2">CAN_F10R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac774a841f16adc00aaa2ec9fc7e19fcb">CAN_F10R2_FB0_Msk</a></td></tr>
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<tr class="memitem:ga742179253216598663252628f54678a8" id="r_ga742179253216598663252628f54678a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga742179253216598663252628f54678a8">CAN_F10R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga6a4ed750a26abda88304eac5be92b6a5" id="r_ga6a4ed750a26abda88304eac5be92b6a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a4ed750a26abda88304eac5be92b6a5">CAN_F10R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga742179253216598663252628f54678a8">CAN_F10R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga6a4ed750a26abda88304eac5be92b6a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa24b6ba1e723098e55e4affc793558c5" id="r_gaa24b6ba1e723098e55e4affc793558c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa24b6ba1e723098e55e4affc793558c5">CAN_F10R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a4ed750a26abda88304eac5be92b6a5">CAN_F10R2_FB1_Msk</a></td></tr>
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<tr class="separator:gaa24b6ba1e723098e55e4affc793558c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36eff8cda50911988d0a0d6d36d8c267" id="r_ga36eff8cda50911988d0a0d6d36d8c267"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36eff8cda50911988d0a0d6d36d8c267">CAN_F10R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga36eff8cda50911988d0a0d6d36d8c267"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf87f405ddb1abb90958df292c6fc0a4a" id="r_gaf87f405ddb1abb90958df292c6fc0a4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf87f405ddb1abb90958df292c6fc0a4a">CAN_F10R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga36eff8cda50911988d0a0d6d36d8c267">CAN_F10R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:gaf87f405ddb1abb90958df292c6fc0a4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b7fc9db4e77e216f37bf088d7b7703c" id="r_ga1b7fc9db4e77e216f37bf088d7b7703c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b7fc9db4e77e216f37bf088d7b7703c">CAN_F10R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf87f405ddb1abb90958df292c6fc0a4a">CAN_F10R2_FB2_Msk</a></td></tr>
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<tr class="separator:ga1b7fc9db4e77e216f37bf088d7b7703c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae61032600bc3bbd5751c1883555311ae" id="r_gae61032600bc3bbd5751c1883555311ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae61032600bc3bbd5751c1883555311ae">CAN_F10R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gae61032600bc3bbd5751c1883555311ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fd1293748da16cb1139224b528082c4" id="r_ga0fd1293748da16cb1139224b528082c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fd1293748da16cb1139224b528082c4">CAN_F10R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae61032600bc3bbd5751c1883555311ae">CAN_F10R2_FB3_Pos</a>)</td></tr>
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<tr class="memitem:ga2348cdfff622628147e2c1df0a35363c" id="r_ga2348cdfff622628147e2c1df0a35363c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2348cdfff622628147e2c1df0a35363c">CAN_F10R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0fd1293748da16cb1139224b528082c4">CAN_F10R2_FB3_Msk</a></td></tr>
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<tr class="memitem:ga3bde5e4239f61759d51e0eda6b788e7e" id="r_ga3bde5e4239f61759d51e0eda6b788e7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bde5e4239f61759d51e0eda6b788e7e">CAN_F10R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga3bde5e4239f61759d51e0eda6b788e7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga445fedfbaf84b454483c73e6b72bedfe" id="r_ga445fedfbaf84b454483c73e6b72bedfe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga445fedfbaf84b454483c73e6b72bedfe">CAN_F10R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bde5e4239f61759d51e0eda6b788e7e">CAN_F10R2_FB4_Pos</a>)</td></tr>
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<tr class="memitem:gaebde0ea1e0aaf38fdcf1584e9c9b2063" id="r_gaebde0ea1e0aaf38fdcf1584e9c9b2063"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebde0ea1e0aaf38fdcf1584e9c9b2063">CAN_F10R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga445fedfbaf84b454483c73e6b72bedfe">CAN_F10R2_FB4_Msk</a></td></tr>
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<tr class="separator:gaebde0ea1e0aaf38fdcf1584e9c9b2063"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdd558b92af16682b2ebd3b573a1a07b" id="r_gabdd558b92af16682b2ebd3b573a1a07b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdd558b92af16682b2ebd3b573a1a07b">CAN_F10R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gabdd558b92af16682b2ebd3b573a1a07b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26b37e77455ba2d98eee41464c2fe039" id="r_ga26b37e77455ba2d98eee41464c2fe039"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26b37e77455ba2d98eee41464c2fe039">CAN_F10R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabdd558b92af16682b2ebd3b573a1a07b">CAN_F10R2_FB5_Pos</a>)</td></tr>
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<tr class="memitem:ga3b5b32b71c86c6dc7040b3044be61af7" id="r_ga3b5b32b71c86c6dc7040b3044be61af7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b5b32b71c86c6dc7040b3044be61af7">CAN_F10R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga26b37e77455ba2d98eee41464c2fe039">CAN_F10R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga3b5b32b71c86c6dc7040b3044be61af7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7351a6a4b667479d490e6146b8cd9b41" id="r_ga7351a6a4b667479d490e6146b8cd9b41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7351a6a4b667479d490e6146b8cd9b41">CAN_F10R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga7351a6a4b667479d490e6146b8cd9b41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42f57e8c16bb81bb9291c5ebb4a04b1a" id="r_ga42f57e8c16bb81bb9291c5ebb4a04b1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42f57e8c16bb81bb9291c5ebb4a04b1a">CAN_F10R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7351a6a4b667479d490e6146b8cd9b41">CAN_F10R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga42f57e8c16bb81bb9291c5ebb4a04b1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9df7daa799c7c73d9a56de5f92285aca" id="r_ga9df7daa799c7c73d9a56de5f92285aca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9df7daa799c7c73d9a56de5f92285aca">CAN_F10R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga42f57e8c16bb81bb9291c5ebb4a04b1a">CAN_F10R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga9df7daa799c7c73d9a56de5f92285aca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga061fd86dd7cab205318a1b63c443c0f9" id="r_ga061fd86dd7cab205318a1b63c443c0f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga061fd86dd7cab205318a1b63c443c0f9">CAN_F10R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga061fd86dd7cab205318a1b63c443c0f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6d86237a0fff09a8f49360d47f28d05" id="r_gac6d86237a0fff09a8f49360d47f28d05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6d86237a0fff09a8f49360d47f28d05">CAN_F10R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga061fd86dd7cab205318a1b63c443c0f9">CAN_F10R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:gac6d86237a0fff09a8f49360d47f28d05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed755173b9d4375b40d73cab90396adc" id="r_gaed755173b9d4375b40d73cab90396adc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed755173b9d4375b40d73cab90396adc">CAN_F10R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac6d86237a0fff09a8f49360d47f28d05">CAN_F10R2_FB7_Msk</a></td></tr>
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<tr class="separator:gaed755173b9d4375b40d73cab90396adc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31ba127731d0de563aabf8397b0011ac" id="r_ga31ba127731d0de563aabf8397b0011ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31ba127731d0de563aabf8397b0011ac">CAN_F10R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga31ba127731d0de563aabf8397b0011ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad459c18ab4e613bb142e5c1f78691bb8" id="r_gad459c18ab4e613bb142e5c1f78691bb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad459c18ab4e613bb142e5c1f78691bb8">CAN_F10R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga31ba127731d0de563aabf8397b0011ac">CAN_F10R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:gad459c18ab4e613bb142e5c1f78691bb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a8d08fea6e7307f6d1d602e113a6d27" id="r_ga8a8d08fea6e7307f6d1d602e113a6d27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a8d08fea6e7307f6d1d602e113a6d27">CAN_F10R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad459c18ab4e613bb142e5c1f78691bb8">CAN_F10R2_FB8_Msk</a></td></tr>
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<tr class="separator:ga8a8d08fea6e7307f6d1d602e113a6d27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d043efe65c029bd4849d543b3d5b9c4" id="r_ga3d043efe65c029bd4849d543b3d5b9c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d043efe65c029bd4849d543b3d5b9c4">CAN_F10R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga3d043efe65c029bd4849d543b3d5b9c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5ac6067a7226de096a846276a7770e9" id="r_gae5ac6067a7226de096a846276a7770e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5ac6067a7226de096a846276a7770e9">CAN_F10R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d043efe65c029bd4849d543b3d5b9c4">CAN_F10R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:gae5ac6067a7226de096a846276a7770e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6aecdda55a484aa0e96c89f5d0f42aba" id="r_ga6aecdda55a484aa0e96c89f5d0f42aba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6aecdda55a484aa0e96c89f5d0f42aba">CAN_F10R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae5ac6067a7226de096a846276a7770e9">CAN_F10R2_FB9_Msk</a></td></tr>
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<tr class="separator:ga6aecdda55a484aa0e96c89f5d0f42aba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e968d8513a58a5be0ce2cbce6cd7642" id="r_ga1e968d8513a58a5be0ce2cbce6cd7642"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e968d8513a58a5be0ce2cbce6cd7642">CAN_F10R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga1e968d8513a58a5be0ce2cbce6cd7642"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bb490d175c5c7ea273dc5a2ed089028" id="r_ga2bb490d175c5c7ea273dc5a2ed089028"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bb490d175c5c7ea273dc5a2ed089028">CAN_F10R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e968d8513a58a5be0ce2cbce6cd7642">CAN_F10R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga2bb490d175c5c7ea273dc5a2ed089028"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4da658bf0a044b327c5efcc592e0ebe1" id="r_ga4da658bf0a044b327c5efcc592e0ebe1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4da658bf0a044b327c5efcc592e0ebe1">CAN_F10R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2bb490d175c5c7ea273dc5a2ed089028">CAN_F10R2_FB10_Msk</a></td></tr>
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<tr class="separator:ga4da658bf0a044b327c5efcc592e0ebe1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb10c3617ae2bd30b86196797e26ecba" id="r_gafb10c3617ae2bd30b86196797e26ecba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb10c3617ae2bd30b86196797e26ecba">CAN_F10R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga898eafb1c345981f1feaa3e1750f7c32" id="r_ga898eafb1c345981f1feaa3e1750f7c32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga898eafb1c345981f1feaa3e1750f7c32">CAN_F10R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafb10c3617ae2bd30b86196797e26ecba">CAN_F10R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga898eafb1c345981f1feaa3e1750f7c32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6ec91db97da763ae1da98ef3a3f7fea" id="r_gae6ec91db97da763ae1da98ef3a3f7fea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6ec91db97da763ae1da98ef3a3f7fea">CAN_F10R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga898eafb1c345981f1feaa3e1750f7c32">CAN_F10R2_FB11_Msk</a></td></tr>
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<tr class="separator:gae6ec91db97da763ae1da98ef3a3f7fea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafedb8df9e02ae3bbe23bba2d1afb8e2e" id="r_gafedb8df9e02ae3bbe23bba2d1afb8e2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafedb8df9e02ae3bbe23bba2d1afb8e2e">CAN_F10R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gafedb8df9e02ae3bbe23bba2d1afb8e2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0d87b23898f43c4c310c9e9098e78b9" id="r_gae0d87b23898f43c4c310c9e9098e78b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0d87b23898f43c4c310c9e9098e78b9">CAN_F10R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafedb8df9e02ae3bbe23bba2d1afb8e2e">CAN_F10R2_FB12_Pos</a>)</td></tr>
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<tr class="separator:gae0d87b23898f43c4c310c9e9098e78b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62bba82d177602a29448acf481a7f691" id="r_ga62bba82d177602a29448acf481a7f691"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62bba82d177602a29448acf481a7f691">CAN_F10R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae0d87b23898f43c4c310c9e9098e78b9">CAN_F10R2_FB12_Msk</a></td></tr>
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<tr class="separator:ga62bba82d177602a29448acf481a7f691"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabec06c12b62b4aa0ee4391e6e663ced3" id="r_gabec06c12b62b4aa0ee4391e6e663ced3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabec06c12b62b4aa0ee4391e6e663ced3">CAN_F10R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gabec06c12b62b4aa0ee4391e6e663ced3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7044a16f8b7a80cfaeaca7c1c8b244f" id="r_gad7044a16f8b7a80cfaeaca7c1c8b244f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7044a16f8b7a80cfaeaca7c1c8b244f">CAN_F10R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabec06c12b62b4aa0ee4391e6e663ced3">CAN_F10R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:gad7044a16f8b7a80cfaeaca7c1c8b244f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ce79aa37f7a175695fb910f986b7d81" id="r_ga6ce79aa37f7a175695fb910f986b7d81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ce79aa37f7a175695fb910f986b7d81">CAN_F10R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad7044a16f8b7a80cfaeaca7c1c8b244f">CAN_F10R2_FB13_Msk</a></td></tr>
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<tr class="separator:ga6ce79aa37f7a175695fb910f986b7d81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50210bdcea0f100cf7bb58790cdace47" id="r_ga50210bdcea0f100cf7bb58790cdace47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50210bdcea0f100cf7bb58790cdace47">CAN_F10R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gaccaaa620579ebfb8e1d78f1c3a0960c8" id="r_gaccaaa620579ebfb8e1d78f1c3a0960c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccaaa620579ebfb8e1d78f1c3a0960c8">CAN_F10R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga50210bdcea0f100cf7bb58790cdace47">CAN_F10R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:gaccaaa620579ebfb8e1d78f1c3a0960c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf31488587e33ea32b60a5c21f3e3aff" id="r_gadf31488587e33ea32b60a5c21f3e3aff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf31488587e33ea32b60a5c21f3e3aff">CAN_F10R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaccaaa620579ebfb8e1d78f1c3a0960c8">CAN_F10R2_FB14_Msk</a></td></tr>
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<tr class="separator:gadf31488587e33ea32b60a5c21f3e3aff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fe557c8dc9f510fed958662e88e3e7a" id="r_ga5fe557c8dc9f510fed958662e88e3e7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe557c8dc9f510fed958662e88e3e7a">CAN_F10R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga5fe557c8dc9f510fed958662e88e3e7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad44ba649751e52a75f36d5279ae51668" id="r_gad44ba649751e52a75f36d5279ae51668"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad44ba649751e52a75f36d5279ae51668">CAN_F10R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe557c8dc9f510fed958662e88e3e7a">CAN_F10R2_FB15_Pos</a>)</td></tr>
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<tr class="memitem:gad8c7c289c07afb023bb3eedfe4d5a9b1" id="r_gad8c7c289c07afb023bb3eedfe4d5a9b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8c7c289c07afb023bb3eedfe4d5a9b1">CAN_F10R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad44ba649751e52a75f36d5279ae51668">CAN_F10R2_FB15_Msk</a></td></tr>
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<tr class="separator:gad8c7c289c07afb023bb3eedfe4d5a9b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae18123a344ee82992f3a7af5e7f901fa" id="r_gae18123a344ee82992f3a7af5e7f901fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae18123a344ee82992f3a7af5e7f901fa">CAN_F10R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga4b8427af5b1aa6b8275902848c766a6a" id="r_ga4b8427af5b1aa6b8275902848c766a6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b8427af5b1aa6b8275902848c766a6a">CAN_F10R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae18123a344ee82992f3a7af5e7f901fa">CAN_F10R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga4b8427af5b1aa6b8275902848c766a6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74258ab493246fefc21ddc475dcfda4a" id="r_ga74258ab493246fefc21ddc475dcfda4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74258ab493246fefc21ddc475dcfda4a">CAN_F10R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b8427af5b1aa6b8275902848c766a6a">CAN_F10R2_FB16_Msk</a></td></tr>
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<tr class="memitem:ga3ae29a19824d47f5c97c8ccbd6f6b663" id="r_ga3ae29a19824d47f5c97c8ccbd6f6b663"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ae29a19824d47f5c97c8ccbd6f6b663">CAN_F10R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga3ae29a19824d47f5c97c8ccbd6f6b663"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bc510b54127fe09c9fc93d265f197fd" id="r_ga3bc510b54127fe09c9fc93d265f197fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bc510b54127fe09c9fc93d265f197fd">CAN_F10R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ae29a19824d47f5c97c8ccbd6f6b663">CAN_F10R2_FB17_Pos</a>)</td></tr>
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<tr class="memitem:gabcf9f2daaa27f340a8cd4e64533f5caf" id="r_gabcf9f2daaa27f340a8cd4e64533f5caf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabcf9f2daaa27f340a8cd4e64533f5caf">CAN_F10R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bc510b54127fe09c9fc93d265f197fd">CAN_F10R2_FB17_Msk</a></td></tr>
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<tr class="separator:gabcf9f2daaa27f340a8cd4e64533f5caf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac05d35a5ccbe652b9d4c5d8ac19a3188" id="r_gac05d35a5ccbe652b9d4c5d8ac19a3188"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac05d35a5ccbe652b9d4c5d8ac19a3188">CAN_F10R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:gac05d35a5ccbe652b9d4c5d8ac19a3188"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15818be97fc1df403386e5fa3791f02f" id="r_ga15818be97fc1df403386e5fa3791f02f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15818be97fc1df403386e5fa3791f02f">CAN_F10R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac05d35a5ccbe652b9d4c5d8ac19a3188">CAN_F10R2_FB18_Pos</a>)</td></tr>
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<tr class="memitem:ga2b8ad53931f4cb3bebb3f557d8686066" id="r_ga2b8ad53931f4cb3bebb3f557d8686066"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b8ad53931f4cb3bebb3f557d8686066">CAN_F10R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga15818be97fc1df403386e5fa3791f02f">CAN_F10R2_FB18_Msk</a></td></tr>
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<tr class="separator:ga2b8ad53931f4cb3bebb3f557d8686066"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8425c341a53e4648190d86ea2c452fa7" id="r_ga8425c341a53e4648190d86ea2c452fa7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8425c341a53e4648190d86ea2c452fa7">CAN_F10R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga8425c341a53e4648190d86ea2c452fa7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdc7ed5a571a970931be36e0883c9821" id="r_gabdc7ed5a571a970931be36e0883c9821"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdc7ed5a571a970931be36e0883c9821">CAN_F10R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8425c341a53e4648190d86ea2c452fa7">CAN_F10R2_FB19_Pos</a>)</td></tr>
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<tr class="separator:gabdc7ed5a571a970931be36e0883c9821"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f0b00c508bddf59fd290091e738a340" id="r_ga9f0b00c508bddf59fd290091e738a340"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f0b00c508bddf59fd290091e738a340">CAN_F10R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabdc7ed5a571a970931be36e0883c9821">CAN_F10R2_FB19_Msk</a></td></tr>
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<tr class="separator:ga9f0b00c508bddf59fd290091e738a340"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf22b16751fb337af287331048cfcae91" id="r_gaf22b16751fb337af287331048cfcae91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf22b16751fb337af287331048cfcae91">CAN_F10R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga31df60197cdd2e5914c14a7dd75e026b" id="r_ga31df60197cdd2e5914c14a7dd75e026b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31df60197cdd2e5914c14a7dd75e026b">CAN_F10R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf22b16751fb337af287331048cfcae91">CAN_F10R2_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga31df60197cdd2e5914c14a7dd75e026b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb9db852d4bf1332f748a0cfc0063364" id="r_gadb9db852d4bf1332f748a0cfc0063364"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb9db852d4bf1332f748a0cfc0063364">CAN_F10R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31df60197cdd2e5914c14a7dd75e026b">CAN_F10R2_FB20_Msk</a></td></tr>
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<tr class="separator:gadb9db852d4bf1332f748a0cfc0063364"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f49963bc7d859f4d79f5f9f55649013" id="r_ga0f49963bc7d859f4d79f5f9f55649013"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f49963bc7d859f4d79f5f9f55649013">CAN_F10R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga0f49963bc7d859f4d79f5f9f55649013"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19dd43ea7d9942f810f2d93169ff5ca6" id="r_ga19dd43ea7d9942f810f2d93169ff5ca6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19dd43ea7d9942f810f2d93169ff5ca6">CAN_F10R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f49963bc7d859f4d79f5f9f55649013">CAN_F10R2_FB21_Pos</a>)</td></tr>
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<tr class="memitem:ga616164fcd20341e4eed5b10a8fd2837c" id="r_ga616164fcd20341e4eed5b10a8fd2837c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga616164fcd20341e4eed5b10a8fd2837c">CAN_F10R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga19dd43ea7d9942f810f2d93169ff5ca6">CAN_F10R2_FB21_Msk</a></td></tr>
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<tr class="separator:ga616164fcd20341e4eed5b10a8fd2837c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb17a1d300b8ffde0b9ef278aead2bbc" id="r_gabb17a1d300b8ffde0b9ef278aead2bbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb17a1d300b8ffde0b9ef278aead2bbc">CAN_F10R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gabb17a1d300b8ffde0b9ef278aead2bbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace06a38396f56ff90887b648c8683acc" id="r_gace06a38396f56ff90887b648c8683acc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace06a38396f56ff90887b648c8683acc">CAN_F10R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb17a1d300b8ffde0b9ef278aead2bbc">CAN_F10R2_FB22_Pos</a>)</td></tr>
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<tr class="separator:gace06a38396f56ff90887b648c8683acc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae70893925ea53547e9ce780c0480587b" id="r_gae70893925ea53547e9ce780c0480587b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae70893925ea53547e9ce780c0480587b">CAN_F10R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gace06a38396f56ff90887b648c8683acc">CAN_F10R2_FB22_Msk</a></td></tr>
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<tr class="separator:gae70893925ea53547e9ce780c0480587b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55d1af80d3c1e3fa6474ccf0509abf83" id="r_ga55d1af80d3c1e3fa6474ccf0509abf83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55d1af80d3c1e3fa6474ccf0509abf83">CAN_F10R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga55d1af80d3c1e3fa6474ccf0509abf83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2806783fb4a13314098d247596f8ac9c" id="r_ga2806783fb4a13314098d247596f8ac9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2806783fb4a13314098d247596f8ac9c">CAN_F10R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55d1af80d3c1e3fa6474ccf0509abf83">CAN_F10R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga2806783fb4a13314098d247596f8ac9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed74e80c74c6c5e12d26abbc0d923787" id="r_gaed74e80c74c6c5e12d26abbc0d923787"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed74e80c74c6c5e12d26abbc0d923787">CAN_F10R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2806783fb4a13314098d247596f8ac9c">CAN_F10R2_FB23_Msk</a></td></tr>
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<tr class="separator:gaed74e80c74c6c5e12d26abbc0d923787"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga869fa5f46955a937b321cdc30d0c08b1" id="r_ga869fa5f46955a937b321cdc30d0c08b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga869fa5f46955a937b321cdc30d0c08b1">CAN_F10R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga869fa5f46955a937b321cdc30d0c08b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad57d7ec2281a4b5a7ecd3db7a80110ba" id="r_gad57d7ec2281a4b5a7ecd3db7a80110ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad57d7ec2281a4b5a7ecd3db7a80110ba">CAN_F10R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga869fa5f46955a937b321cdc30d0c08b1">CAN_F10R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:gad57d7ec2281a4b5a7ecd3db7a80110ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaecb5b90d073107f3c5612379aaffa7ce" id="r_gaecb5b90d073107f3c5612379aaffa7ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecb5b90d073107f3c5612379aaffa7ce">CAN_F10R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad57d7ec2281a4b5a7ecd3db7a80110ba">CAN_F10R2_FB24_Msk</a></td></tr>
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<tr class="separator:gaecb5b90d073107f3c5612379aaffa7ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8dc7dc1019cca26cba0b729119ba43b1" id="r_ga8dc7dc1019cca26cba0b729119ba43b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8dc7dc1019cca26cba0b729119ba43b1">CAN_F10R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga8dc7dc1019cca26cba0b729119ba43b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b18d4f50852e67f214d2c885ab1d96b" id="r_ga9b18d4f50852e67f214d2c885ab1d96b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b18d4f50852e67f214d2c885ab1d96b">CAN_F10R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8dc7dc1019cca26cba0b729119ba43b1">CAN_F10R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga9b18d4f50852e67f214d2c885ab1d96b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga678702522f87f63edfcad21194be3c53" id="r_ga678702522f87f63edfcad21194be3c53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga678702522f87f63edfcad21194be3c53">CAN_F10R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b18d4f50852e67f214d2c885ab1d96b">CAN_F10R2_FB25_Msk</a></td></tr>
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<tr class="separator:ga678702522f87f63edfcad21194be3c53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cc3ae2b65d3e4aca044242f0f8b4a29" id="r_ga1cc3ae2b65d3e4aca044242f0f8b4a29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc3ae2b65d3e4aca044242f0f8b4a29">CAN_F10R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga1cc3ae2b65d3e4aca044242f0f8b4a29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac022d750541154d1c25ae0b342ff3c8d" id="r_gac022d750541154d1c25ae0b342ff3c8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac022d750541154d1c25ae0b342ff3c8d">CAN_F10R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc3ae2b65d3e4aca044242f0f8b4a29">CAN_F10R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:gac022d750541154d1c25ae0b342ff3c8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4523c34e7f333636fade643b895b8f5" id="r_gaf4523c34e7f333636fade643b895b8f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4523c34e7f333636fade643b895b8f5">CAN_F10R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac022d750541154d1c25ae0b342ff3c8d">CAN_F10R2_FB26_Msk</a></td></tr>
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<tr class="separator:gaf4523c34e7f333636fade643b895b8f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3aa23672b58bce5c01c0964f8588e5bd" id="r_ga3aa23672b58bce5c01c0964f8588e5bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3aa23672b58bce5c01c0964f8588e5bd">CAN_F10R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga3aa23672b58bce5c01c0964f8588e5bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga441739ed3bdd065bee7417d50afc96ab" id="r_ga441739ed3bdd065bee7417d50afc96ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga441739ed3bdd065bee7417d50afc96ab">CAN_F10R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3aa23672b58bce5c01c0964f8588e5bd">CAN_F10R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga441739ed3bdd065bee7417d50afc96ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf0e55fcb496970abe8fea481561f886" id="r_gacf0e55fcb496970abe8fea481561f886"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf0e55fcb496970abe8fea481561f886">CAN_F10R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga441739ed3bdd065bee7417d50afc96ab">CAN_F10R2_FB27_Msk</a></td></tr>
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<tr class="separator:gacf0e55fcb496970abe8fea481561f886"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0b2954975958605274276c9ae1ea7a6" id="r_gab0b2954975958605274276c9ae1ea7a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0b2954975958605274276c9ae1ea7a6">CAN_F10R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:gab0b2954975958605274276c9ae1ea7a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga906bacdcf21c6bffaa9d45fa6746f80e" id="r_ga906bacdcf21c6bffaa9d45fa6746f80e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga906bacdcf21c6bffaa9d45fa6746f80e">CAN_F10R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab0b2954975958605274276c9ae1ea7a6">CAN_F10R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:ga906bacdcf21c6bffaa9d45fa6746f80e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e4683223d46d60897b2c46b02addec5" id="r_ga4e4683223d46d60897b2c46b02addec5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e4683223d46d60897b2c46b02addec5">CAN_F10R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga906bacdcf21c6bffaa9d45fa6746f80e">CAN_F10R2_FB28_Msk</a></td></tr>
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<tr class="separator:ga4e4683223d46d60897b2c46b02addec5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga382e8caf7bca3cea6323f83220c5f04c" id="r_ga382e8caf7bca3cea6323f83220c5f04c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga382e8caf7bca3cea6323f83220c5f04c">CAN_F10R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga382e8caf7bca3cea6323f83220c5f04c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe8c560adab03768e49cad994a71cccb" id="r_gafe8c560adab03768e49cad994a71cccb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe8c560adab03768e49cad994a71cccb">CAN_F10R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga382e8caf7bca3cea6323f83220c5f04c">CAN_F10R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:gafe8c560adab03768e49cad994a71cccb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6df50371abf968f0638faf7e0bf76cc8" id="r_ga6df50371abf968f0638faf7e0bf76cc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6df50371abf968f0638faf7e0bf76cc8">CAN_F10R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafe8c560adab03768e49cad994a71cccb">CAN_F10R2_FB29_Msk</a></td></tr>
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<tr class="separator:ga6df50371abf968f0638faf7e0bf76cc8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20abbd298e588db3094637ad1b76b0fb" id="r_ga20abbd298e588db3094637ad1b76b0fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20abbd298e588db3094637ad1b76b0fb">CAN_F10R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga20abbd298e588db3094637ad1b76b0fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d7ed61987ecdd8236e5236edc35946f" id="r_ga9d7ed61987ecdd8236e5236edc35946f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d7ed61987ecdd8236e5236edc35946f">CAN_F10R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20abbd298e588db3094637ad1b76b0fb">CAN_F10R2_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga9d7ed61987ecdd8236e5236edc35946f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab294aa73a3fdfc60672b206bd57a1e08" id="r_gab294aa73a3fdfc60672b206bd57a1e08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab294aa73a3fdfc60672b206bd57a1e08">CAN_F10R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d7ed61987ecdd8236e5236edc35946f">CAN_F10R2_FB30_Msk</a></td></tr>
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<tr class="separator:gab294aa73a3fdfc60672b206bd57a1e08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c0d5f4f54822978cc2fb6d8e46d532f" id="r_ga1c0d5f4f54822978cc2fb6d8e46d532f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c0d5f4f54822978cc2fb6d8e46d532f">CAN_F10R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga1c0d5f4f54822978cc2fb6d8e46d532f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6278728b6cc74ad7d4bc41d6014839f3" id="r_ga6278728b6cc74ad7d4bc41d6014839f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6278728b6cc74ad7d4bc41d6014839f3">CAN_F10R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c0d5f4f54822978cc2fb6d8e46d532f">CAN_F10R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga6278728b6cc74ad7d4bc41d6014839f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2de1906dc4119b37b29bbe25e3e6dbe0" id="r_ga2de1906dc4119b37b29bbe25e3e6dbe0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2de1906dc4119b37b29bbe25e3e6dbe0">CAN_F10R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6278728b6cc74ad7d4bc41d6014839f3">CAN_F10R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga2de1906dc4119b37b29bbe25e3e6dbe0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad70c5d7ca84956020778f4467b9e66ba" id="r_gad70c5d7ca84956020778f4467b9e66ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad70c5d7ca84956020778f4467b9e66ba">CAN_F11R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad70c5d7ca84956020778f4467b9e66ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga756b9a7f35ddb243019a737cc9c5d4aa" id="r_ga756b9a7f35ddb243019a737cc9c5d4aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga756b9a7f35ddb243019a737cc9c5d4aa">CAN_F11R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad70c5d7ca84956020778f4467b9e66ba">CAN_F11R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga756b9a7f35ddb243019a737cc9c5d4aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacad6560088b586891d446952bbd8fbbe" id="r_gacad6560088b586891d446952bbd8fbbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacad6560088b586891d446952bbd8fbbe">CAN_F11R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga756b9a7f35ddb243019a737cc9c5d4aa">CAN_F11R2_FB0_Msk</a></td></tr>
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<tr class="separator:gacad6560088b586891d446952bbd8fbbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa225421da3627c8bf8e836c516c36ff9" id="r_gaa225421da3627c8bf8e836c516c36ff9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa225421da3627c8bf8e836c516c36ff9">CAN_F11R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaa225421da3627c8bf8e836c516c36ff9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73175a30063e3781dd1b5ee2b9ff5c7c" id="r_ga73175a30063e3781dd1b5ee2b9ff5c7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73175a30063e3781dd1b5ee2b9ff5c7c">CAN_F11R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa225421da3627c8bf8e836c516c36ff9">CAN_F11R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga73175a30063e3781dd1b5ee2b9ff5c7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac81bc667cb0c63aa0448f6e0eb1d105d" id="r_gac81bc667cb0c63aa0448f6e0eb1d105d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac81bc667cb0c63aa0448f6e0eb1d105d">CAN_F11R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga73175a30063e3781dd1b5ee2b9ff5c7c">CAN_F11R2_FB1_Msk</a></td></tr>
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<tr class="separator:gac81bc667cb0c63aa0448f6e0eb1d105d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70986cdccec7c3a2997094e5a026ea7d" id="r_ga70986cdccec7c3a2997094e5a026ea7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70986cdccec7c3a2997094e5a026ea7d">CAN_F11R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga70986cdccec7c3a2997094e5a026ea7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43042d452e6efb4e24fecc0ef71f0b53" id="r_ga43042d452e6efb4e24fecc0ef71f0b53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43042d452e6efb4e24fecc0ef71f0b53">CAN_F11R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70986cdccec7c3a2997094e5a026ea7d">CAN_F11R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:ga43042d452e6efb4e24fecc0ef71f0b53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8dab8868637d6d6fb707b6a37a5989b5" id="r_ga8dab8868637d6d6fb707b6a37a5989b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8dab8868637d6d6fb707b6a37a5989b5">CAN_F11R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga43042d452e6efb4e24fecc0ef71f0b53">CAN_F11R2_FB2_Msk</a></td></tr>
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<tr class="separator:ga8dab8868637d6d6fb707b6a37a5989b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4404f58525379b7462074c1f4d94abc" id="r_gae4404f58525379b7462074c1f4d94abc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4404f58525379b7462074c1f4d94abc">CAN_F11R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gae4404f58525379b7462074c1f4d94abc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga603a033a522647ec072b27204f411c27" id="r_ga603a033a522647ec072b27204f411c27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga603a033a522647ec072b27204f411c27">CAN_F11R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4404f58525379b7462074c1f4d94abc">CAN_F11R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga603a033a522647ec072b27204f411c27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga559246cfa4658a5adaa282e4a3b35dd5" id="r_ga559246cfa4658a5adaa282e4a3b35dd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga559246cfa4658a5adaa282e4a3b35dd5">CAN_F11R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga603a033a522647ec072b27204f411c27">CAN_F11R2_FB3_Msk</a></td></tr>
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<tr class="separator:ga559246cfa4658a5adaa282e4a3b35dd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83a62db93a855fc670d041db3f95f7ce" id="r_ga83a62db93a855fc670d041db3f95f7ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83a62db93a855fc670d041db3f95f7ce">CAN_F11R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga83a62db93a855fc670d041db3f95f7ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7f3cc6f8734688ffd55f0eae6d8a3e1" id="r_gaf7f3cc6f8734688ffd55f0eae6d8a3e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7f3cc6f8734688ffd55f0eae6d8a3e1">CAN_F11R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83a62db93a855fc670d041db3f95f7ce">CAN_F11R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:gaf7f3cc6f8734688ffd55f0eae6d8a3e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga499aebdfc0c14b9c399698e28fde3e50" id="r_ga499aebdfc0c14b9c399698e28fde3e50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga499aebdfc0c14b9c399698e28fde3e50">CAN_F11R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7f3cc6f8734688ffd55f0eae6d8a3e1">CAN_F11R2_FB4_Msk</a></td></tr>
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<tr class="separator:ga499aebdfc0c14b9c399698e28fde3e50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24cd2b60689ccae14ae3254487a564b9" id="r_ga24cd2b60689ccae14ae3254487a564b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24cd2b60689ccae14ae3254487a564b9">CAN_F11R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga24cd2b60689ccae14ae3254487a564b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga100d5a8929cac40dc2d8d6bfaf2effb0" id="r_ga100d5a8929cac40dc2d8d6bfaf2effb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga100d5a8929cac40dc2d8d6bfaf2effb0">CAN_F11R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24cd2b60689ccae14ae3254487a564b9">CAN_F11R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga100d5a8929cac40dc2d8d6bfaf2effb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1613d097fe5b7107ff36f97a9263bd38" id="r_ga1613d097fe5b7107ff36f97a9263bd38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1613d097fe5b7107ff36f97a9263bd38">CAN_F11R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga100d5a8929cac40dc2d8d6bfaf2effb0">CAN_F11R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga1613d097fe5b7107ff36f97a9263bd38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga595220fc83b10a19867b00b7bc58221f" id="r_ga595220fc83b10a19867b00b7bc58221f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga595220fc83b10a19867b00b7bc58221f">CAN_F11R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga595220fc83b10a19867b00b7bc58221f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2541f8510aa2f59dd2b2cfbf1bc99c1" id="r_gab2541f8510aa2f59dd2b2cfbf1bc99c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2541f8510aa2f59dd2b2cfbf1bc99c1">CAN_F11R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga595220fc83b10a19867b00b7bc58221f">CAN_F11R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:gab2541f8510aa2f59dd2b2cfbf1bc99c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9db1830185822d66619059a644d86ffe" id="r_ga9db1830185822d66619059a644d86ffe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9db1830185822d66619059a644d86ffe">CAN_F11R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab2541f8510aa2f59dd2b2cfbf1bc99c1">CAN_F11R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga9db1830185822d66619059a644d86ffe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga196fb045bc38774e8d3b9c18345f799e" id="r_ga196fb045bc38774e8d3b9c18345f799e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga196fb045bc38774e8d3b9c18345f799e">CAN_F11R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga196fb045bc38774e8d3b9c18345f799e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2739365d7644847c2b2e9424b5361782" id="r_ga2739365d7644847c2b2e9424b5361782"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2739365d7644847c2b2e9424b5361782">CAN_F11R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga196fb045bc38774e8d3b9c18345f799e">CAN_F11R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga2739365d7644847c2b2e9424b5361782"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab35bedade0c9f71455abfbbac2edee14" id="r_gab35bedade0c9f71455abfbbac2edee14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab35bedade0c9f71455abfbbac2edee14">CAN_F11R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2739365d7644847c2b2e9424b5361782">CAN_F11R2_FB7_Msk</a></td></tr>
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<tr class="separator:gab35bedade0c9f71455abfbbac2edee14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94ab78b385a77559abd1bc055656fa5a" id="r_ga94ab78b385a77559abd1bc055656fa5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94ab78b385a77559abd1bc055656fa5a">CAN_F11R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga94ab78b385a77559abd1bc055656fa5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7159e2db436359c52f6db1dda067a7c2" id="r_ga7159e2db436359c52f6db1dda067a7c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7159e2db436359c52f6db1dda067a7c2">CAN_F11R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga94ab78b385a77559abd1bc055656fa5a">CAN_F11R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga7159e2db436359c52f6db1dda067a7c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac79ac007ffed536eedddffdd2615c5f7" id="r_gac79ac007ffed536eedddffdd2615c5f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac79ac007ffed536eedddffdd2615c5f7">CAN_F11R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7159e2db436359c52f6db1dda067a7c2">CAN_F11R2_FB8_Msk</a></td></tr>
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<tr class="separator:gac79ac007ffed536eedddffdd2615c5f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga818a9cf4d1a1ebfc566869487c5ede4e" id="r_ga818a9cf4d1a1ebfc566869487c5ede4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga818a9cf4d1a1ebfc566869487c5ede4e">CAN_F11R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga818a9cf4d1a1ebfc566869487c5ede4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2d8d29dcf8047b47275915562036f6e" id="r_gad2d8d29dcf8047b47275915562036f6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2d8d29dcf8047b47275915562036f6e">CAN_F11R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga818a9cf4d1a1ebfc566869487c5ede4e">CAN_F11R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:gad2d8d29dcf8047b47275915562036f6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5900c2273c405ce35b9bd52b189c102" id="r_gad5900c2273c405ce35b9bd52b189c102"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5900c2273c405ce35b9bd52b189c102">CAN_F11R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad2d8d29dcf8047b47275915562036f6e">CAN_F11R2_FB9_Msk</a></td></tr>
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<tr class="separator:gad5900c2273c405ce35b9bd52b189c102"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cda459a8f36d3ebc3b572df16998ad2" id="r_ga3cda459a8f36d3ebc3b572df16998ad2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cda459a8f36d3ebc3b572df16998ad2">CAN_F11R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga3cda459a8f36d3ebc3b572df16998ad2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d867bbf2aeec0751fb8d9bc028a3e20" id="r_ga3d867bbf2aeec0751fb8d9bc028a3e20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d867bbf2aeec0751fb8d9bc028a3e20">CAN_F11R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cda459a8f36d3ebc3b572df16998ad2">CAN_F11R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:ga3d867bbf2aeec0751fb8d9bc028a3e20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9dad5ea347a6a928997a0a1c149369ce" id="r_ga9dad5ea347a6a928997a0a1c149369ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9dad5ea347a6a928997a0a1c149369ce">CAN_F11R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d867bbf2aeec0751fb8d9bc028a3e20">CAN_F11R2_FB10_Msk</a></td></tr>
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<tr class="separator:ga9dad5ea347a6a928997a0a1c149369ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9aed466e0487ccf8da142590ea6a0c9" id="r_gae9aed466e0487ccf8da142590ea6a0c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9aed466e0487ccf8da142590ea6a0c9">CAN_F11R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga6f02c0270c8560877a6849dc3ec12734" id="r_ga6f02c0270c8560877a6849dc3ec12734"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f02c0270c8560877a6849dc3ec12734">CAN_F11R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9aed466e0487ccf8da142590ea6a0c9">CAN_F11R2_FB11_Pos</a>)</td></tr>
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<tr class="memitem:ga9285109080a523012f27b3bdbabc6949" id="r_ga9285109080a523012f27b3bdbabc6949"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9285109080a523012f27b3bdbabc6949">CAN_F11R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f02c0270c8560877a6849dc3ec12734">CAN_F11R2_FB11_Msk</a></td></tr>
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<tr class="memitem:gac9f6c874f151de08d9e16f7f25e69519" id="r_gac9f6c874f151de08d9e16f7f25e69519"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9f6c874f151de08d9e16f7f25e69519">CAN_F11R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gac9f6c874f151de08d9e16f7f25e69519"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f27deb61d7cecd98a3707baeee44c33" id="r_ga7f27deb61d7cecd98a3707baeee44c33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f27deb61d7cecd98a3707baeee44c33">CAN_F11R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9f6c874f151de08d9e16f7f25e69519">CAN_F11R2_FB12_Pos</a>)</td></tr>
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<tr class="memitem:ga65cdf759738f8b0cb8c4c3231453aad8" id="r_ga65cdf759738f8b0cb8c4c3231453aad8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65cdf759738f8b0cb8c4c3231453aad8">CAN_F11R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f27deb61d7cecd98a3707baeee44c33">CAN_F11R2_FB12_Msk</a></td></tr>
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<tr class="separator:ga65cdf759738f8b0cb8c4c3231453aad8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga466d8e9611e69bfd911aeab18a24f790" id="r_ga466d8e9611e69bfd911aeab18a24f790"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga466d8e9611e69bfd911aeab18a24f790">CAN_F11R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga4e89abf41152c9c443eec298c3c4ee0a" id="r_ga4e89abf41152c9c443eec298c3c4ee0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e89abf41152c9c443eec298c3c4ee0a">CAN_F11R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga466d8e9611e69bfd911aeab18a24f790">CAN_F11R2_FB13_Pos</a>)</td></tr>
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<tr class="memitem:ga24a40efa6debcdcfef0f7ab6d8b3eb04" id="r_ga24a40efa6debcdcfef0f7ab6d8b3eb04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24a40efa6debcdcfef0f7ab6d8b3eb04">CAN_F11R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e89abf41152c9c443eec298c3c4ee0a">CAN_F11R2_FB13_Msk</a></td></tr>
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<tr class="separator:ga24a40efa6debcdcfef0f7ab6d8b3eb04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06aa722740f4a12a01fcec5930b44e4e" id="r_ga06aa722740f4a12a01fcec5930b44e4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06aa722740f4a12a01fcec5930b44e4e">CAN_F11R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga06aa722740f4a12a01fcec5930b44e4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf385990b78e0ad2903adf8ca5d31592d" id="r_gaf385990b78e0ad2903adf8ca5d31592d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf385990b78e0ad2903adf8ca5d31592d">CAN_F11R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga06aa722740f4a12a01fcec5930b44e4e">CAN_F11R2_FB14_Pos</a>)</td></tr>
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<tr class="memitem:gaa923634a3432436c4c84e65be1fd39d6" id="r_gaa923634a3432436c4c84e65be1fd39d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa923634a3432436c4c84e65be1fd39d6">CAN_F11R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf385990b78e0ad2903adf8ca5d31592d">CAN_F11R2_FB14_Msk</a></td></tr>
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<tr class="memitem:ga1084133f89fd1b056a0001b496010b9e" id="r_ga1084133f89fd1b056a0001b496010b9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1084133f89fd1b056a0001b496010b9e">CAN_F11R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="memitem:gac617eb6a2c9da89608e9a1fd20bedb05" id="r_gac617eb6a2c9da89608e9a1fd20bedb05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac617eb6a2c9da89608e9a1fd20bedb05">CAN_F11R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1084133f89fd1b056a0001b496010b9e">CAN_F11R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:gac617eb6a2c9da89608e9a1fd20bedb05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65bae4ee01f83fe051acee8ee4c8a10e" id="r_ga65bae4ee01f83fe051acee8ee4c8a10e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65bae4ee01f83fe051acee8ee4c8a10e">CAN_F11R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac617eb6a2c9da89608e9a1fd20bedb05">CAN_F11R2_FB15_Msk</a></td></tr>
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<tr class="separator:ga65bae4ee01f83fe051acee8ee4c8a10e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c28a61b0bd631ca5fe08c4aa30f9567" id="r_ga7c28a61b0bd631ca5fe08c4aa30f9567"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c28a61b0bd631ca5fe08c4aa30f9567">CAN_F11R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga7c28a61b0bd631ca5fe08c4aa30f9567"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f7a12de16318eca8c069f7a4a107ba4" id="r_ga2f7a12de16318eca8c069f7a4a107ba4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f7a12de16318eca8c069f7a4a107ba4">CAN_F11R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c28a61b0bd631ca5fe08c4aa30f9567">CAN_F11R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga2f7a12de16318eca8c069f7a4a107ba4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b6762f3642ce7a06fff58270ac9f53f" id="r_ga7b6762f3642ce7a06fff58270ac9f53f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b6762f3642ce7a06fff58270ac9f53f">CAN_F11R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f7a12de16318eca8c069f7a4a107ba4">CAN_F11R2_FB16_Msk</a></td></tr>
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<tr class="separator:ga7b6762f3642ce7a06fff58270ac9f53f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4a696446a3ba4010fe43d401efc22b8" id="r_gae4a696446a3ba4010fe43d401efc22b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4a696446a3ba4010fe43d401efc22b8">CAN_F11R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gae4a696446a3ba4010fe43d401efc22b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6194082f1b79eacc5490d6c4571f2993" id="r_ga6194082f1b79eacc5490d6c4571f2993"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6194082f1b79eacc5490d6c4571f2993">CAN_F11R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4a696446a3ba4010fe43d401efc22b8">CAN_F11R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga6194082f1b79eacc5490d6c4571f2993"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69c7d6a41708543278980035b64bd31b" id="r_ga69c7d6a41708543278980035b64bd31b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69c7d6a41708543278980035b64bd31b">CAN_F11R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6194082f1b79eacc5490d6c4571f2993">CAN_F11R2_FB17_Msk</a></td></tr>
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<tr class="separator:ga69c7d6a41708543278980035b64bd31b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87528786c246818857315a7728117d16" id="r_ga87528786c246818857315a7728117d16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87528786c246818857315a7728117d16">CAN_F11R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga578e9b0b0fc78522d232926aa5a474b4" id="r_ga578e9b0b0fc78522d232926aa5a474b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga578e9b0b0fc78522d232926aa5a474b4">CAN_F11R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga87528786c246818857315a7728117d16">CAN_F11R2_FB18_Pos</a>)</td></tr>
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<tr class="separator:ga578e9b0b0fc78522d232926aa5a474b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88d6d67020cbc5a4d5f0b7c5dc488aa6" id="r_ga88d6d67020cbc5a4d5f0b7c5dc488aa6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88d6d67020cbc5a4d5f0b7c5dc488aa6">CAN_F11R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga578e9b0b0fc78522d232926aa5a474b4">CAN_F11R2_FB18_Msk</a></td></tr>
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<tr class="separator:ga88d6d67020cbc5a4d5f0b7c5dc488aa6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb57ae932a28d7bae3af99c7cc73d6f0" id="r_gaeb57ae932a28d7bae3af99c7cc73d6f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb57ae932a28d7bae3af99c7cc73d6f0">CAN_F11R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:gaeb57ae932a28d7bae3af99c7cc73d6f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4aa7935ffacb2eb500c03e6f297c9abf" id="r_ga4aa7935ffacb2eb500c03e6f297c9abf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4aa7935ffacb2eb500c03e6f297c9abf">CAN_F11R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb57ae932a28d7bae3af99c7cc73d6f0">CAN_F11R2_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga4aa7935ffacb2eb500c03e6f297c9abf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07f4a8d606f2063be35b52e1fc5e4b58" id="r_ga07f4a8d606f2063be35b52e1fc5e4b58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07f4a8d606f2063be35b52e1fc5e4b58">CAN_F11R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4aa7935ffacb2eb500c03e6f297c9abf">CAN_F11R2_FB19_Msk</a></td></tr>
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<tr class="separator:ga07f4a8d606f2063be35b52e1fc5e4b58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac77f12ec2cab52d721629fe0ae73c093" id="r_gac77f12ec2cab52d721629fe0ae73c093"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac77f12ec2cab52d721629fe0ae73c093">CAN_F11R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gac77f12ec2cab52d721629fe0ae73c093"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaecca1f88d1ccfd94c942c1dba195f566" id="r_gaecca1f88d1ccfd94c942c1dba195f566"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecca1f88d1ccfd94c942c1dba195f566">CAN_F11R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac77f12ec2cab52d721629fe0ae73c093">CAN_F11R2_FB20_Pos</a>)</td></tr>
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<tr class="separator:gaecca1f88d1ccfd94c942c1dba195f566"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58c6e5b0076c31b7bee1c9aea94e11fb" id="r_ga58c6e5b0076c31b7bee1c9aea94e11fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58c6e5b0076c31b7bee1c9aea94e11fb">CAN_F11R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaecca1f88d1ccfd94c942c1dba195f566">CAN_F11R2_FB20_Msk</a></td></tr>
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<tr class="separator:ga58c6e5b0076c31b7bee1c9aea94e11fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabbc3adfab5e37044e4b71efcd3e045c3" id="r_gabbc3adfab5e37044e4b71efcd3e045c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbc3adfab5e37044e4b71efcd3e045c3">CAN_F11R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gabbc3adfab5e37044e4b71efcd3e045c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26b076a8a45e423f12d66b72888a62c1" id="r_ga26b076a8a45e423f12d66b72888a62c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26b076a8a45e423f12d66b72888a62c1">CAN_F11R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabbc3adfab5e37044e4b71efcd3e045c3">CAN_F11R2_FB21_Pos</a>)</td></tr>
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<tr class="memitem:ga93bf815d462dc3a40725f73e107e11f5" id="r_ga93bf815d462dc3a40725f73e107e11f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93bf815d462dc3a40725f73e107e11f5">CAN_F11R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga26b076a8a45e423f12d66b72888a62c1">CAN_F11R2_FB21_Msk</a></td></tr>
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<tr class="memitem:gabfb18cb42280379ea211f97dda828964" id="r_gabfb18cb42280379ea211f97dda828964"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfb18cb42280379ea211f97dda828964">CAN_F11R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="memitem:ga69a3601ecccef7d68dceacf69694f57c" id="r_ga69a3601ecccef7d68dceacf69694f57c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69a3601ecccef7d68dceacf69694f57c">CAN_F11R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabfb18cb42280379ea211f97dda828964">CAN_F11R2_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga69a3601ecccef7d68dceacf69694f57c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeebe934727476f5fde11c888c424c417" id="r_gaeebe934727476f5fde11c888c424c417"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeebe934727476f5fde11c888c424c417">CAN_F11R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga69a3601ecccef7d68dceacf69694f57c">CAN_F11R2_FB22_Msk</a></td></tr>
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<tr class="separator:gaeebe934727476f5fde11c888c424c417"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56baa11c41451f4e27adb7df35046d74" id="r_ga56baa11c41451f4e27adb7df35046d74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56baa11c41451f4e27adb7df35046d74">CAN_F11R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga56baa11c41451f4e27adb7df35046d74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9acb53490837c29f03538f37e92ab7b0" id="r_ga9acb53490837c29f03538f37e92ab7b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9acb53490837c29f03538f37e92ab7b0">CAN_F11R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga56baa11c41451f4e27adb7df35046d74">CAN_F11R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga9acb53490837c29f03538f37e92ab7b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8324877e56a61c15119f2ebf929894cc" id="r_ga8324877e56a61c15119f2ebf929894cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8324877e56a61c15119f2ebf929894cc">CAN_F11R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9acb53490837c29f03538f37e92ab7b0">CAN_F11R2_FB23_Msk</a></td></tr>
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<tr class="separator:ga8324877e56a61c15119f2ebf929894cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09624fe67ae7144c103e70325bb4bbd9" id="r_ga09624fe67ae7144c103e70325bb4bbd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09624fe67ae7144c103e70325bb4bbd9">CAN_F11R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga09624fe67ae7144c103e70325bb4bbd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54d08ee868e97a722b5e25b145581435" id="r_ga54d08ee868e97a722b5e25b145581435"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54d08ee868e97a722b5e25b145581435">CAN_F11R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga09624fe67ae7144c103e70325bb4bbd9">CAN_F11R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga54d08ee868e97a722b5e25b145581435"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadfd994c36da11529ac494df973b5759c" id="r_gadfd994c36da11529ac494df973b5759c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfd994c36da11529ac494df973b5759c">CAN_F11R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga54d08ee868e97a722b5e25b145581435">CAN_F11R2_FB24_Msk</a></td></tr>
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<tr class="separator:gadfd994c36da11529ac494df973b5759c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadeeb62a3987c1ad5b7bd6ed7424c4a1b" id="r_gadeeb62a3987c1ad5b7bd6ed7424c4a1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadeeb62a3987c1ad5b7bd6ed7424c4a1b">CAN_F11R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gadeeb62a3987c1ad5b7bd6ed7424c4a1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e9aaac92b7b5c524dfd488651f66d1b" id="r_ga1e9aaac92b7b5c524dfd488651f66d1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e9aaac92b7b5c524dfd488651f66d1b">CAN_F11R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadeeb62a3987c1ad5b7bd6ed7424c4a1b">CAN_F11R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:ga1e9aaac92b7b5c524dfd488651f66d1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f3e9d272b625f7d6269057aee5d7761" id="r_ga8f3e9d272b625f7d6269057aee5d7761"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f3e9d272b625f7d6269057aee5d7761">CAN_F11R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e9aaac92b7b5c524dfd488651f66d1b">CAN_F11R2_FB25_Msk</a></td></tr>
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<tr class="separator:ga8f3e9d272b625f7d6269057aee5d7761"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa50568c5112b9d364a4a1a6a7d668ba2" id="r_gaa50568c5112b9d364a4a1a6a7d668ba2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa50568c5112b9d364a4a1a6a7d668ba2">CAN_F11R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:gaa50568c5112b9d364a4a1a6a7d668ba2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga769efd27c8d450433589d3a59e4b49b7" id="r_ga769efd27c8d450433589d3a59e4b49b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga769efd27c8d450433589d3a59e4b49b7">CAN_F11R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa50568c5112b9d364a4a1a6a7d668ba2">CAN_F11R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga769efd27c8d450433589d3a59e4b49b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5da4d794a9797d14536197679b7b2b14" id="r_ga5da4d794a9797d14536197679b7b2b14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5da4d794a9797d14536197679b7b2b14">CAN_F11R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga769efd27c8d450433589d3a59e4b49b7">CAN_F11R2_FB26_Msk</a></td></tr>
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<tr class="separator:ga5da4d794a9797d14536197679b7b2b14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc07b263056b681c3834e366c8cb060e" id="r_gabc07b263056b681c3834e366c8cb060e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc07b263056b681c3834e366c8cb060e">CAN_F11R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:gabc07b263056b681c3834e366c8cb060e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38daca04f9249b41d451122bfcb63b2d" id="r_ga38daca04f9249b41d451122bfcb63b2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38daca04f9249b41d451122bfcb63b2d">CAN_F11R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc07b263056b681c3834e366c8cb060e">CAN_F11R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga38daca04f9249b41d451122bfcb63b2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9b9a815f36e7c2929f4313ca424c83a" id="r_gad9b9a815f36e7c2929f4313ca424c83a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9b9a815f36e7c2929f4313ca424c83a">CAN_F11R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38daca04f9249b41d451122bfcb63b2d">CAN_F11R2_FB27_Msk</a></td></tr>
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<tr class="separator:gad9b9a815f36e7c2929f4313ca424c83a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70db281007bc66b283e8bb8f0dc05af4" id="r_ga70db281007bc66b283e8bb8f0dc05af4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70db281007bc66b283e8bb8f0dc05af4">CAN_F11R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga70db281007bc66b283e8bb8f0dc05af4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb214fcb4208a4d5db09465c5260d5e4" id="r_gadb214fcb4208a4d5db09465c5260d5e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb214fcb4208a4d5db09465c5260d5e4">CAN_F11R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70db281007bc66b283e8bb8f0dc05af4">CAN_F11R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:gadb214fcb4208a4d5db09465c5260d5e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf162471f4c070d13fa409d44467373fc" id="r_gaf162471f4c070d13fa409d44467373fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf162471f4c070d13fa409d44467373fc">CAN_F11R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadb214fcb4208a4d5db09465c5260d5e4">CAN_F11R2_FB28_Msk</a></td></tr>
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<tr class="separator:gaf162471f4c070d13fa409d44467373fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga111f04007588ff775bbd03d30f7e1bb7" id="r_ga111f04007588ff775bbd03d30f7e1bb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga111f04007588ff775bbd03d30f7e1bb7">CAN_F11R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga111f04007588ff775bbd03d30f7e1bb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10d6ff5e482dc1d88d0f39a0e2329427" id="r_ga10d6ff5e482dc1d88d0f39a0e2329427"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10d6ff5e482dc1d88d0f39a0e2329427">CAN_F11R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga111f04007588ff775bbd03d30f7e1bb7">CAN_F11R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:ga10d6ff5e482dc1d88d0f39a0e2329427"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c301fd37e3fa27d3bd28a1f3f553e77" id="r_ga2c301fd37e3fa27d3bd28a1f3f553e77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c301fd37e3fa27d3bd28a1f3f553e77">CAN_F11R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga10d6ff5e482dc1d88d0f39a0e2329427">CAN_F11R2_FB29_Msk</a></td></tr>
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<tr class="separator:ga2c301fd37e3fa27d3bd28a1f3f553e77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga537283f338bc941c2749698732cba679" id="r_ga537283f338bc941c2749698732cba679"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga537283f338bc941c2749698732cba679">CAN_F11R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga537283f338bc941c2749698732cba679"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7be4778f941b5287fcc39a5ce3724e71" id="r_ga7be4778f941b5287fcc39a5ce3724e71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7be4778f941b5287fcc39a5ce3724e71">CAN_F11R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga537283f338bc941c2749698732cba679">CAN_F11R2_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga7be4778f941b5287fcc39a5ce3724e71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bdc4ba1d0e44ba4d7a03cfd3197b687" id="r_ga2bdc4ba1d0e44ba4d7a03cfd3197b687"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bdc4ba1d0e44ba4d7a03cfd3197b687">CAN_F11R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7be4778f941b5287fcc39a5ce3724e71">CAN_F11R2_FB30_Msk</a></td></tr>
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<tr class="separator:ga2bdc4ba1d0e44ba4d7a03cfd3197b687"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7120051826cab6e84712aafd60e7f0e" id="r_gaa7120051826cab6e84712aafd60e7f0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7120051826cab6e84712aafd60e7f0e">CAN_F11R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:gaa7120051826cab6e84712aafd60e7f0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f08f45859f87d045ab080dd511302bd" id="r_ga4f08f45859f87d045ab080dd511302bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f08f45859f87d045ab080dd511302bd">CAN_F11R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7120051826cab6e84712aafd60e7f0e">CAN_F11R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga4f08f45859f87d045ab080dd511302bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6525c1ff364a229c9ea1b353b11be8c3" id="r_ga6525c1ff364a229c9ea1b353b11be8c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6525c1ff364a229c9ea1b353b11be8c3">CAN_F11R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f08f45859f87d045ab080dd511302bd">CAN_F11R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga6525c1ff364a229c9ea1b353b11be8c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga761234dc8a340812052ad359ca15346e" id="r_ga761234dc8a340812052ad359ca15346e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga761234dc8a340812052ad359ca15346e">CAN_F12R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga761234dc8a340812052ad359ca15346e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8707c57f295a01f74ba15708f138c27" id="r_gab8707c57f295a01f74ba15708f138c27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8707c57f295a01f74ba15708f138c27">CAN_F12R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga761234dc8a340812052ad359ca15346e">CAN_F12R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:gab8707c57f295a01f74ba15708f138c27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5fd095552b3108c685514e78e43e52d" id="r_gac5fd095552b3108c685514e78e43e52d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5fd095552b3108c685514e78e43e52d">CAN_F12R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab8707c57f295a01f74ba15708f138c27">CAN_F12R2_FB0_Msk</a></td></tr>
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<tr class="memitem:ga30aeb440ddfed5b394b5d2a24e3ae6a9" id="r_ga30aeb440ddfed5b394b5d2a24e3ae6a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30aeb440ddfed5b394b5d2a24e3ae6a9">CAN_F12R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga9c445b90087e01550b4d69a41d01920b" id="r_ga9c445b90087e01550b4d69a41d01920b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c445b90087e01550b4d69a41d01920b">CAN_F12R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30aeb440ddfed5b394b5d2a24e3ae6a9">CAN_F12R2_FB1_Pos</a>)</td></tr>
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<tr class="separator:ga9c445b90087e01550b4d69a41d01920b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga450e88e19b2e478e73cbc5eef74a72d2" id="r_ga450e88e19b2e478e73cbc5eef74a72d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga450e88e19b2e478e73cbc5eef74a72d2">CAN_F12R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c445b90087e01550b4d69a41d01920b">CAN_F12R2_FB1_Msk</a></td></tr>
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<tr class="separator:ga450e88e19b2e478e73cbc5eef74a72d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga453ef335bb8ebc552ac07085c3c1787b" id="r_ga453ef335bb8ebc552ac07085c3c1787b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga453ef335bb8ebc552ac07085c3c1787b">CAN_F12R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga453ef335bb8ebc552ac07085c3c1787b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae07ef8899e2a3d28d760dfd1ecc26534" id="r_gae07ef8899e2a3d28d760dfd1ecc26534"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae07ef8899e2a3d28d760dfd1ecc26534">CAN_F12R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga453ef335bb8ebc552ac07085c3c1787b">CAN_F12R2_FB2_Pos</a>)</td></tr>
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<tr class="separator:gae07ef8899e2a3d28d760dfd1ecc26534"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17875db304b98c38e627f7d7db339136" id="r_ga17875db304b98c38e627f7d7db339136"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17875db304b98c38e627f7d7db339136">CAN_F12R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae07ef8899e2a3d28d760dfd1ecc26534">CAN_F12R2_FB2_Msk</a></td></tr>
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<tr class="separator:ga17875db304b98c38e627f7d7db339136"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaac55989758901512f579aef6dc250d5" id="r_gaaac55989758901512f579aef6dc250d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaac55989758901512f579aef6dc250d5">CAN_F12R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaaac55989758901512f579aef6dc250d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5918b1d48e5c6e30363e5f5274428f6f" id="r_ga5918b1d48e5c6e30363e5f5274428f6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5918b1d48e5c6e30363e5f5274428f6f">CAN_F12R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaac55989758901512f579aef6dc250d5">CAN_F12R2_FB3_Pos</a>)</td></tr>
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<tr class="separator:ga5918b1d48e5c6e30363e5f5274428f6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2960fee8bc56574e1b51975da7d2f041" id="r_ga2960fee8bc56574e1b51975da7d2f041"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2960fee8bc56574e1b51975da7d2f041">CAN_F12R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5918b1d48e5c6e30363e5f5274428f6f">CAN_F12R2_FB3_Msk</a></td></tr>
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<tr class="separator:ga2960fee8bc56574e1b51975da7d2f041"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0582dd4f64bdf4f05d1049191cd0ead5" id="r_ga0582dd4f64bdf4f05d1049191cd0ead5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0582dd4f64bdf4f05d1049191cd0ead5">CAN_F12R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga0582dd4f64bdf4f05d1049191cd0ead5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7278ef3ee9707ed890c9fe0e6100898e" id="r_ga7278ef3ee9707ed890c9fe0e6100898e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7278ef3ee9707ed890c9fe0e6100898e">CAN_F12R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0582dd4f64bdf4f05d1049191cd0ead5">CAN_F12R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga7278ef3ee9707ed890c9fe0e6100898e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b3b6f518fae0cb1123aa187138d90b6" id="r_ga6b3b6f518fae0cb1123aa187138d90b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b3b6f518fae0cb1123aa187138d90b6">CAN_F12R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7278ef3ee9707ed890c9fe0e6100898e">CAN_F12R2_FB4_Msk</a></td></tr>
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<tr class="separator:ga6b3b6f518fae0cb1123aa187138d90b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50ff5f436b22533d9c3d008b3b5ad936" id="r_ga50ff5f436b22533d9c3d008b3b5ad936"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50ff5f436b22533d9c3d008b3b5ad936">CAN_F12R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga50ff5f436b22533d9c3d008b3b5ad936"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9db42645316b7d12f6761201dde5266e" id="r_ga9db42645316b7d12f6761201dde5266e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9db42645316b7d12f6761201dde5266e">CAN_F12R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga50ff5f436b22533d9c3d008b3b5ad936">CAN_F12R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:ga9db42645316b7d12f6761201dde5266e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39cedc414fa80ef987825daf32e11ac4" id="r_ga39cedc414fa80ef987825daf32e11ac4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39cedc414fa80ef987825daf32e11ac4">CAN_F12R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9db42645316b7d12f6761201dde5266e">CAN_F12R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga39cedc414fa80ef987825daf32e11ac4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f48821b5d51b30776a550c461e9f39e" id="r_ga1f48821b5d51b30776a550c461e9f39e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f48821b5d51b30776a550c461e9f39e">CAN_F12R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga1f48821b5d51b30776a550c461e9f39e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga105d22692de0996a549d7381117a9343" id="r_ga105d22692de0996a549d7381117a9343"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga105d22692de0996a549d7381117a9343">CAN_F12R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f48821b5d51b30776a550c461e9f39e">CAN_F12R2_FB6_Pos</a>)</td></tr>
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<tr class="separator:ga105d22692de0996a549d7381117a9343"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10aa07474c2e7cf7f2845d0d2b2bd383" id="r_ga10aa07474c2e7cf7f2845d0d2b2bd383"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10aa07474c2e7cf7f2845d0d2b2bd383">CAN_F12R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga105d22692de0996a549d7381117a9343">CAN_F12R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga10aa07474c2e7cf7f2845d0d2b2bd383"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3bda5bd0a94bb8f667f350b5d1bd575" id="r_gaa3bda5bd0a94bb8f667f350b5d1bd575"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3bda5bd0a94bb8f667f350b5d1bd575">CAN_F12R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaa3bda5bd0a94bb8f667f350b5d1bd575"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ef9a09cde9defbbef26f0fdb18e2eab" id="r_ga7ef9a09cde9defbbef26f0fdb18e2eab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ef9a09cde9defbbef26f0fdb18e2eab">CAN_F12R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3bda5bd0a94bb8f667f350b5d1bd575">CAN_F12R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga7ef9a09cde9defbbef26f0fdb18e2eab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga227ef5f36f6e03969cd952d62a3bc0a9" id="r_ga227ef5f36f6e03969cd952d62a3bc0a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga227ef5f36f6e03969cd952d62a3bc0a9">CAN_F12R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ef9a09cde9defbbef26f0fdb18e2eab">CAN_F12R2_FB7_Msk</a></td></tr>
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<tr class="separator:ga227ef5f36f6e03969cd952d62a3bc0a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c35633aeeaa4b60f618d6b59d5450d1" id="r_ga5c35633aeeaa4b60f618d6b59d5450d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c35633aeeaa4b60f618d6b59d5450d1">CAN_F12R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga5c35633aeeaa4b60f618d6b59d5450d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga997778eae60bd7c86e4ac5f512cf37d1" id="r_ga997778eae60bd7c86e4ac5f512cf37d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga997778eae60bd7c86e4ac5f512cf37d1">CAN_F12R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c35633aeeaa4b60f618d6b59d5450d1">CAN_F12R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga997778eae60bd7c86e4ac5f512cf37d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a946c991cee617b322ff9a372af3512" id="r_ga7a946c991cee617b322ff9a372af3512"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a946c991cee617b322ff9a372af3512">CAN_F12R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga997778eae60bd7c86e4ac5f512cf37d1">CAN_F12R2_FB8_Msk</a></td></tr>
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<tr class="separator:ga7a946c991cee617b322ff9a372af3512"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab378df5d0ef5f7b73f9cc93d9deb28d" id="r_gaab378df5d0ef5f7b73f9cc93d9deb28d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab378df5d0ef5f7b73f9cc93d9deb28d">CAN_F12R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaab378df5d0ef5f7b73f9cc93d9deb28d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d597dd76bca430d66ce6cdc1dab0039" id="r_ga0d597dd76bca430d66ce6cdc1dab0039"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d597dd76bca430d66ce6cdc1dab0039">CAN_F12R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab378df5d0ef5f7b73f9cc93d9deb28d">CAN_F12R2_FB9_Pos</a>)</td></tr>
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<tr class="separator:ga0d597dd76bca430d66ce6cdc1dab0039"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0ab582743e96fcd36662a9434b875bd" id="r_gad0ab582743e96fcd36662a9434b875bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0ab582743e96fcd36662a9434b875bd">CAN_F12R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d597dd76bca430d66ce6cdc1dab0039">CAN_F12R2_FB9_Msk</a></td></tr>
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<tr class="separator:gad0ab582743e96fcd36662a9434b875bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf3a83fdb8ed55330b72d88624d3eeca" id="r_gabf3a83fdb8ed55330b72d88624d3eeca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf3a83fdb8ed55330b72d88624d3eeca">CAN_F12R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gabf3a83fdb8ed55330b72d88624d3eeca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2fe14171ea2823a2cc42bd77f8285f5" id="r_gab2fe14171ea2823a2cc42bd77f8285f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2fe14171ea2823a2cc42bd77f8285f5">CAN_F12R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf3a83fdb8ed55330b72d88624d3eeca">CAN_F12R2_FB10_Pos</a>)</td></tr>
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<tr class="separator:gab2fe14171ea2823a2cc42bd77f8285f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga854c2b7108e33d263cc8269648f8bbbe" id="r_ga854c2b7108e33d263cc8269648f8bbbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga854c2b7108e33d263cc8269648f8bbbe">CAN_F12R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab2fe14171ea2823a2cc42bd77f8285f5">CAN_F12R2_FB10_Msk</a></td></tr>
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<tr class="separator:ga854c2b7108e33d263cc8269648f8bbbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7506fa1356769f671cc4ac661aca30df" id="r_ga7506fa1356769f671cc4ac661aca30df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7506fa1356769f671cc4ac661aca30df">CAN_F12R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga7506fa1356769f671cc4ac661aca30df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf995048a494eef63803ad6d1ee208669" id="r_gaf995048a494eef63803ad6d1ee208669"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf995048a494eef63803ad6d1ee208669">CAN_F12R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7506fa1356769f671cc4ac661aca30df">CAN_F12R2_FB11_Pos</a>)</td></tr>
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<tr class="memitem:ga2ed3de0039e458bac5530d08c2e9af51" id="r_ga2ed3de0039e458bac5530d08c2e9af51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ed3de0039e458bac5530d08c2e9af51">CAN_F12R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf995048a494eef63803ad6d1ee208669">CAN_F12R2_FB11_Msk</a></td></tr>
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<tr class="memitem:ga842fb02b43bc973392d1befc14475398" id="r_ga842fb02b43bc973392d1befc14475398"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga842fb02b43bc973392d1befc14475398">CAN_F12R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="memitem:ga2b1c705252d4dda9fc1e08a83bf44014" id="r_ga2b1c705252d4dda9fc1e08a83bf44014"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b1c705252d4dda9fc1e08a83bf44014">CAN_F12R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga842fb02b43bc973392d1befc14475398">CAN_F12R2_FB12_Pos</a>)</td></tr>
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<tr class="separator:ga2b1c705252d4dda9fc1e08a83bf44014"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadad0db6fe916794156f773e98b524b07" id="r_gadad0db6fe916794156f773e98b524b07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadad0db6fe916794156f773e98b524b07">CAN_F12R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b1c705252d4dda9fc1e08a83bf44014">CAN_F12R2_FB12_Msk</a></td></tr>
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<tr class="separator:gadad0db6fe916794156f773e98b524b07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga584c1f14c88da55dfb8846e31b6fad4f" id="r_ga584c1f14c88da55dfb8846e31b6fad4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga584c1f14c88da55dfb8846e31b6fad4f">CAN_F12R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga584c1f14c88da55dfb8846e31b6fad4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a5720bd6028451390e7e09643a959eb" id="r_ga8a5720bd6028451390e7e09643a959eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a5720bd6028451390e7e09643a959eb">CAN_F12R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga584c1f14c88da55dfb8846e31b6fad4f">CAN_F12R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga8a5720bd6028451390e7e09643a959eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7a50bd0de8b4e85d9e90c1f48ef7bc8" id="r_gaa7a50bd0de8b4e85d9e90c1f48ef7bc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7a50bd0de8b4e85d9e90c1f48ef7bc8">CAN_F12R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a5720bd6028451390e7e09643a959eb">CAN_F12R2_FB13_Msk</a></td></tr>
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<tr class="separator:gaa7a50bd0de8b4e85d9e90c1f48ef7bc8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga199bffabf961f45cd68a0cafcc4be3e4" id="r_ga199bffabf961f45cd68a0cafcc4be3e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga199bffabf961f45cd68a0cafcc4be3e4">CAN_F12R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga199bffabf961f45cd68a0cafcc4be3e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac46f9e9d46f1bebfa7abcb094e87536" id="r_gaac46f9e9d46f1bebfa7abcb094e87536"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac46f9e9d46f1bebfa7abcb094e87536">CAN_F12R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga199bffabf961f45cd68a0cafcc4be3e4">CAN_F12R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:gaac46f9e9d46f1bebfa7abcb094e87536"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c5558cc37c62c5570a5e2716e30ed99" id="r_ga2c5558cc37c62c5570a5e2716e30ed99"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c5558cc37c62c5570a5e2716e30ed99">CAN_F12R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac46f9e9d46f1bebfa7abcb094e87536">CAN_F12R2_FB14_Msk</a></td></tr>
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<tr class="separator:ga2c5558cc37c62c5570a5e2716e30ed99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba0f51aaeeb7e039aa521f88a20bacd6" id="r_gaba0f51aaeeb7e039aa521f88a20bacd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba0f51aaeeb7e039aa521f88a20bacd6">CAN_F12R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaba0f51aaeeb7e039aa521f88a20bacd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1114ed600ca719c7df01b6e0ebd1b46e" id="r_ga1114ed600ca719c7df01b6e0ebd1b46e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1114ed600ca719c7df01b6e0ebd1b46e">CAN_F12R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba0f51aaeeb7e039aa521f88a20bacd6">CAN_F12R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga1114ed600ca719c7df01b6e0ebd1b46e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fa511d56f90a2ee10e44e56e378f7ed" id="r_ga9fa511d56f90a2ee10e44e56e378f7ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fa511d56f90a2ee10e44e56e378f7ed">CAN_F12R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1114ed600ca719c7df01b6e0ebd1b46e">CAN_F12R2_FB15_Msk</a></td></tr>
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<tr class="separator:ga9fa511d56f90a2ee10e44e56e378f7ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02f84ccd7431b78532fed1e1b219cc5f" id="r_ga02f84ccd7431b78532fed1e1b219cc5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02f84ccd7431b78532fed1e1b219cc5f">CAN_F12R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga02f84ccd7431b78532fed1e1b219cc5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94b484b519e43973af447f5f39fa9ea6" id="r_ga94b484b519e43973af447f5f39fa9ea6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94b484b519e43973af447f5f39fa9ea6">CAN_F12R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02f84ccd7431b78532fed1e1b219cc5f">CAN_F12R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga94b484b519e43973af447f5f39fa9ea6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77ae08ea078773a1aecbf74e89dc2a5d" id="r_ga77ae08ea078773a1aecbf74e89dc2a5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77ae08ea078773a1aecbf74e89dc2a5d">CAN_F12R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga94b484b519e43973af447f5f39fa9ea6">CAN_F12R2_FB16_Msk</a></td></tr>
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<tr class="separator:ga77ae08ea078773a1aecbf74e89dc2a5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2dd4b026306377b126988db6f40b925b" id="r_ga2dd4b026306377b126988db6f40b925b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dd4b026306377b126988db6f40b925b">CAN_F12R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga2dd4b026306377b126988db6f40b925b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a2460e4afab4b8dc064ffc0342f4d9d" id="r_ga0a2460e4afab4b8dc064ffc0342f4d9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a2460e4afab4b8dc064ffc0342f4d9d">CAN_F12R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2dd4b026306377b126988db6f40b925b">CAN_F12R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga0a2460e4afab4b8dc064ffc0342f4d9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a94ac3d4ba5c16a98fc04144ae3bb86" id="r_ga3a94ac3d4ba5c16a98fc04144ae3bb86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a94ac3d4ba5c16a98fc04144ae3bb86">CAN_F12R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a2460e4afab4b8dc064ffc0342f4d9d">CAN_F12R2_FB17_Msk</a></td></tr>
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<tr class="separator:ga3a94ac3d4ba5c16a98fc04144ae3bb86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b9aaf58c37cc1c397c235b6f3359a8e" id="r_ga6b9aaf58c37cc1c397c235b6f3359a8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b9aaf58c37cc1c397c235b6f3359a8e">CAN_F12R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga6b9aaf58c37cc1c397c235b6f3359a8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae63f4ec2056e1d8cee09e7582dd0cc4f" id="r_gae63f4ec2056e1d8cee09e7582dd0cc4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae63f4ec2056e1d8cee09e7582dd0cc4f">CAN_F12R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b9aaf58c37cc1c397c235b6f3359a8e">CAN_F12R2_FB18_Pos</a>)</td></tr>
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<tr class="separator:gae63f4ec2056e1d8cee09e7582dd0cc4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9070c9b9eec5dea6b5c4cdbaa1d5918" id="r_gae9070c9b9eec5dea6b5c4cdbaa1d5918"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9070c9b9eec5dea6b5c4cdbaa1d5918">CAN_F12R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae63f4ec2056e1d8cee09e7582dd0cc4f">CAN_F12R2_FB18_Msk</a></td></tr>
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<tr class="separator:gae9070c9b9eec5dea6b5c4cdbaa1d5918"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b87a32833eb49ae6e9d6016b23f1a77" id="r_ga7b87a32833eb49ae6e9d6016b23f1a77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b87a32833eb49ae6e9d6016b23f1a77">CAN_F12R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga7b87a32833eb49ae6e9d6016b23f1a77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17513f0a12a63dd49ef869f7f69c89b0" id="r_ga17513f0a12a63dd49ef869f7f69c89b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17513f0a12a63dd49ef869f7f69c89b0">CAN_F12R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b87a32833eb49ae6e9d6016b23f1a77">CAN_F12R2_FB19_Pos</a>)</td></tr>
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<tr class="separator:ga17513f0a12a63dd49ef869f7f69c89b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga758cacc8b96577bb3663da1fae36040b" id="r_ga758cacc8b96577bb3663da1fae36040b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga758cacc8b96577bb3663da1fae36040b">CAN_F12R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga17513f0a12a63dd49ef869f7f69c89b0">CAN_F12R2_FB19_Msk</a></td></tr>
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<tr class="separator:ga758cacc8b96577bb3663da1fae36040b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9723713bf9c96c6e2a843cc4c8851512" id="r_ga9723713bf9c96c6e2a843cc4c8851512"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9723713bf9c96c6e2a843cc4c8851512">CAN_F12R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga9723713bf9c96c6e2a843cc4c8851512"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98344bb2606581ffe2826c660c129f8b" id="r_ga98344bb2606581ffe2826c660c129f8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98344bb2606581ffe2826c660c129f8b">CAN_F12R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9723713bf9c96c6e2a843cc4c8851512">CAN_F12R2_FB20_Pos</a>)</td></tr>
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<tr class="separator:ga98344bb2606581ffe2826c660c129f8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80db4704807d6df4aaee2eebfcf5210a" id="r_ga80db4704807d6df4aaee2eebfcf5210a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80db4704807d6df4aaee2eebfcf5210a">CAN_F12R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga98344bb2606581ffe2826c660c129f8b">CAN_F12R2_FB20_Msk</a></td></tr>
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<tr class="separator:ga80db4704807d6df4aaee2eebfcf5210a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e7ede0dcef51b6f58598345d03231b2" id="r_ga1e7ede0dcef51b6f58598345d03231b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e7ede0dcef51b6f58598345d03231b2">CAN_F12R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga1e7ede0dcef51b6f58598345d03231b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27369d641bde06fff00068460db1fad7" id="r_ga27369d641bde06fff00068460db1fad7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27369d641bde06fff00068460db1fad7">CAN_F12R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e7ede0dcef51b6f58598345d03231b2">CAN_F12R2_FB21_Pos</a>)</td></tr>
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<tr class="separator:ga27369d641bde06fff00068460db1fad7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3d3fb3a9b4b6b90139024bef933bc3d" id="r_gac3d3fb3a9b4b6b90139024bef933bc3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3d3fb3a9b4b6b90139024bef933bc3d">CAN_F12R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga27369d641bde06fff00068460db1fad7">CAN_F12R2_FB21_Msk</a></td></tr>
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<tr class="separator:gac3d3fb3a9b4b6b90139024bef933bc3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafda2d00458700d6f0d9bc992032c143a" id="r_gafda2d00458700d6f0d9bc992032c143a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafda2d00458700d6f0d9bc992032c143a">CAN_F12R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gafda2d00458700d6f0d9bc992032c143a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0293d477ec5d1c58228b05da05d5ab9a" id="r_ga0293d477ec5d1c58228b05da05d5ab9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0293d477ec5d1c58228b05da05d5ab9a">CAN_F12R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafda2d00458700d6f0d9bc992032c143a">CAN_F12R2_FB22_Pos</a>)</td></tr>
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<tr class="separator:ga0293d477ec5d1c58228b05da05d5ab9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24e87973f51235e81195d84f78489cb0" id="r_ga24e87973f51235e81195d84f78489cb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24e87973f51235e81195d84f78489cb0">CAN_F12R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0293d477ec5d1c58228b05da05d5ab9a">CAN_F12R2_FB22_Msk</a></td></tr>
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<tr class="separator:ga24e87973f51235e81195d84f78489cb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f0bf90c297ea4e534fa8dc777f84308" id="r_ga6f0bf90c297ea4e534fa8dc777f84308"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f0bf90c297ea4e534fa8dc777f84308">CAN_F12R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga6f0bf90c297ea4e534fa8dc777f84308"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bb02cff06985ebc935cd0c71033e309" id="r_ga9bb02cff06985ebc935cd0c71033e309"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bb02cff06985ebc935cd0c71033e309">CAN_F12R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f0bf90c297ea4e534fa8dc777f84308">CAN_F12R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga9bb02cff06985ebc935cd0c71033e309"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e917f2a362569d86a75a34eddce636c" id="r_ga4e917f2a362569d86a75a34eddce636c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e917f2a362569d86a75a34eddce636c">CAN_F12R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9bb02cff06985ebc935cd0c71033e309">CAN_F12R2_FB23_Msk</a></td></tr>
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<tr class="separator:ga4e917f2a362569d86a75a34eddce636c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d42baff6206f76c15caec946f2e163f" id="r_ga0d42baff6206f76c15caec946f2e163f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d42baff6206f76c15caec946f2e163f">CAN_F12R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga0d42baff6206f76c15caec946f2e163f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5942038c40cb69a4523cf59d41addaf" id="r_gae5942038c40cb69a4523cf59d41addaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5942038c40cb69a4523cf59d41addaf">CAN_F12R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d42baff6206f76c15caec946f2e163f">CAN_F12R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:gae5942038c40cb69a4523cf59d41addaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6e5f2c5de8981fbfc152926fc8fb057" id="r_gad6e5f2c5de8981fbfc152926fc8fb057"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6e5f2c5de8981fbfc152926fc8fb057">CAN_F12R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae5942038c40cb69a4523cf59d41addaf">CAN_F12R2_FB24_Msk</a></td></tr>
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<tr class="separator:gad6e5f2c5de8981fbfc152926fc8fb057"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf89410be942af8dd01a4a82d2419ebc" id="r_gacf89410be942af8dd01a4a82d2419ebc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf89410be942af8dd01a4a82d2419ebc">CAN_F12R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:gacf89410be942af8dd01a4a82d2419ebc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab77c232170c49225690370bd7b94cc34" id="r_gab77c232170c49225690370bd7b94cc34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab77c232170c49225690370bd7b94cc34">CAN_F12R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf89410be942af8dd01a4a82d2419ebc">CAN_F12R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:gab77c232170c49225690370bd7b94cc34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaad1149501e8f926a247aa532405c0b9" id="r_gaaad1149501e8f926a247aa532405c0b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaad1149501e8f926a247aa532405c0b9">CAN_F12R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab77c232170c49225690370bd7b94cc34">CAN_F12R2_FB25_Msk</a></td></tr>
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<tr class="separator:gaaad1149501e8f926a247aa532405c0b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga099dae9dd45974395166a31031a7a9a4" id="r_ga099dae9dd45974395166a31031a7a9a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga099dae9dd45974395166a31031a7a9a4">CAN_F12R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga099dae9dd45974395166a31031a7a9a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga051ec82cb86668c1907e9091bf7db162" id="r_ga051ec82cb86668c1907e9091bf7db162"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga051ec82cb86668c1907e9091bf7db162">CAN_F12R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga099dae9dd45974395166a31031a7a9a4">CAN_F12R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga051ec82cb86668c1907e9091bf7db162"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53538969afd7e43cc7fed4c400ab6f5a" id="r_ga53538969afd7e43cc7fed4c400ab6f5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53538969afd7e43cc7fed4c400ab6f5a">CAN_F12R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga051ec82cb86668c1907e9091bf7db162">CAN_F12R2_FB26_Msk</a></td></tr>
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<tr class="separator:ga53538969afd7e43cc7fed4c400ab6f5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ed6233846959dbe830448c085f9895d" id="r_ga5ed6233846959dbe830448c085f9895d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ed6233846959dbe830448c085f9895d">CAN_F12R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga5ed6233846959dbe830448c085f9895d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1eb6cc6be0e68041cb7e72b9ef73e22" id="r_gae1eb6cc6be0e68041cb7e72b9ef73e22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1eb6cc6be0e68041cb7e72b9ef73e22">CAN_F12R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ed6233846959dbe830448c085f9895d">CAN_F12R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:gae1eb6cc6be0e68041cb7e72b9ef73e22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74e04fa5d17a7cc7687c0ca40dd571ce" id="r_ga74e04fa5d17a7cc7687c0ca40dd571ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74e04fa5d17a7cc7687c0ca40dd571ce">CAN_F12R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae1eb6cc6be0e68041cb7e72b9ef73e22">CAN_F12R2_FB27_Msk</a></td></tr>
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<tr class="separator:ga74e04fa5d17a7cc7687c0ca40dd571ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefa74afb06c20c7d6fdfadd641e55047" id="r_gaefa74afb06c20c7d6fdfadd641e55047"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefa74afb06c20c7d6fdfadd641e55047">CAN_F12R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:gaefa74afb06c20c7d6fdfadd641e55047"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c63cc29f569c165a9b93cb0cb2d7557" id="r_ga2c63cc29f569c165a9b93cb0cb2d7557"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c63cc29f569c165a9b93cb0cb2d7557">CAN_F12R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaefa74afb06c20c7d6fdfadd641e55047">CAN_F12R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:ga2c63cc29f569c165a9b93cb0cb2d7557"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc1d97354c1649fa5ddc46f4271297d9" id="r_gadc1d97354c1649fa5ddc46f4271297d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc1d97354c1649fa5ddc46f4271297d9">CAN_F12R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c63cc29f569c165a9b93cb0cb2d7557">CAN_F12R2_FB28_Msk</a></td></tr>
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<tr class="separator:gadc1d97354c1649fa5ddc46f4271297d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2d97a557450fc2f40af9032f9e6c123" id="r_gab2d97a557450fc2f40af9032f9e6c123"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2d97a557450fc2f40af9032f9e6c123">CAN_F12R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:gab2d97a557450fc2f40af9032f9e6c123"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa58b7118e577b7ea51f92ed3d6a86a56" id="r_gaa58b7118e577b7ea51f92ed3d6a86a56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa58b7118e577b7ea51f92ed3d6a86a56">CAN_F12R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab2d97a557450fc2f40af9032f9e6c123">CAN_F12R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:gaa58b7118e577b7ea51f92ed3d6a86a56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71b870003e469dcb24979e835a2f81a4" id="r_ga71b870003e469dcb24979e835a2f81a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71b870003e469dcb24979e835a2f81a4">CAN_F12R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa58b7118e577b7ea51f92ed3d6a86a56">CAN_F12R2_FB29_Msk</a></td></tr>
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<tr class="separator:ga71b870003e469dcb24979e835a2f81a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87899a68fb53be2c0c66183254f8e74c" id="r_ga87899a68fb53be2c0c66183254f8e74c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87899a68fb53be2c0c66183254f8e74c">CAN_F12R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga87899a68fb53be2c0c66183254f8e74c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1fe16c8a9c44110d181e931e96458cee" id="r_ga1fe16c8a9c44110d181e931e96458cee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fe16c8a9c44110d181e931e96458cee">CAN_F12R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga87899a68fb53be2c0c66183254f8e74c">CAN_F12R2_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga1fe16c8a9c44110d181e931e96458cee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2894b732a9683d32620fb90b06ba9f62" id="r_ga2894b732a9683d32620fb90b06ba9f62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2894b732a9683d32620fb90b06ba9f62">CAN_F12R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fe16c8a9c44110d181e931e96458cee">CAN_F12R2_FB30_Msk</a></td></tr>
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<tr class="separator:ga2894b732a9683d32620fb90b06ba9f62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6180d0787f865b2a5da3c308dc9df3ee" id="r_ga6180d0787f865b2a5da3c308dc9df3ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6180d0787f865b2a5da3c308dc9df3ee">CAN_F12R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga6180d0787f865b2a5da3c308dc9df3ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga677ce6a45ad5da29fbe4b3674294c356" id="r_ga677ce6a45ad5da29fbe4b3674294c356"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga677ce6a45ad5da29fbe4b3674294c356">CAN_F12R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6180d0787f865b2a5da3c308dc9df3ee">CAN_F12R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga677ce6a45ad5da29fbe4b3674294c356"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab11cddebcb4e1ab70b7222a999d0c58a" id="r_gab11cddebcb4e1ab70b7222a999d0c58a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab11cddebcb4e1ab70b7222a999d0c58a">CAN_F12R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga677ce6a45ad5da29fbe4b3674294c356">CAN_F12R2_FB31_Msk</a></td></tr>
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<tr class="separator:gab11cddebcb4e1ab70b7222a999d0c58a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf65fd29198dc6498a41e5fc67ab0092c" id="r_gaf65fd29198dc6498a41e5fc67ab0092c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf65fd29198dc6498a41e5fc67ab0092c">CAN_F13R2_FB0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf65fd29198dc6498a41e5fc67ab0092c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5829958d09421fd61fcf0b77d51d2da9" id="r_ga5829958d09421fd61fcf0b77d51d2da9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5829958d09421fd61fcf0b77d51d2da9">CAN_F13R2_FB0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf65fd29198dc6498a41e5fc67ab0092c">CAN_F13R2_FB0_Pos</a>)</td></tr>
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<tr class="separator:ga5829958d09421fd61fcf0b77d51d2da9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b6865be0c757b49a250a537d73ae85e" id="r_ga0b6865be0c757b49a250a537d73ae85e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b6865be0c757b49a250a537d73ae85e">CAN_F13R2_FB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5829958d09421fd61fcf0b77d51d2da9">CAN_F13R2_FB0_Msk</a></td></tr>
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<tr class="separator:ga0b6865be0c757b49a250a537d73ae85e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44b45587e81d3899b99a4292ef37ea94" id="r_ga44b45587e81d3899b99a4292ef37ea94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44b45587e81d3899b99a4292ef37ea94">CAN_F13R2_FB1_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga5d158b5eebb1632e54e5be5d97c8ac26" id="r_ga5d158b5eebb1632e54e5be5d97c8ac26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d158b5eebb1632e54e5be5d97c8ac26">CAN_F13R2_FB1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga44b45587e81d3899b99a4292ef37ea94">CAN_F13R2_FB1_Pos</a>)</td></tr>
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<tr class="memitem:gaf18df9b2fd549b8991fdd9f8f94e7cbb" id="r_gaf18df9b2fd549b8991fdd9f8f94e7cbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf18df9b2fd549b8991fdd9f8f94e7cbb">CAN_F13R2_FB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5d158b5eebb1632e54e5be5d97c8ac26">CAN_F13R2_FB1_Msk</a></td></tr>
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<tr class="memitem:ga16867534ce37ae3319f3e8a5cf087cb8" id="r_ga16867534ce37ae3319f3e8a5cf087cb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16867534ce37ae3319f3e8a5cf087cb8">CAN_F13R2_FB2_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga4433c9b9f1466001eaf2305aa5abcf88" id="r_ga4433c9b9f1466001eaf2305aa5abcf88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4433c9b9f1466001eaf2305aa5abcf88">CAN_F13R2_FB2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16867534ce37ae3319f3e8a5cf087cb8">CAN_F13R2_FB2_Pos</a>)</td></tr>
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<tr class="memitem:ga034e8f5b7675ce34eb2792531c7e174d" id="r_ga034e8f5b7675ce34eb2792531c7e174d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga034e8f5b7675ce34eb2792531c7e174d">CAN_F13R2_FB2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4433c9b9f1466001eaf2305aa5abcf88">CAN_F13R2_FB2_Msk</a></td></tr>
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<tr class="separator:ga034e8f5b7675ce34eb2792531c7e174d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed05bb756f656fb754091e64b176bd78" id="r_gaed05bb756f656fb754091e64b176bd78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed05bb756f656fb754091e64b176bd78">CAN_F13R2_FB3_Pos</a>   (3U)</td></tr>
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<tr class="memitem:gaab05ac64cc9be63004a672f439a7ab70" id="r_gaab05ac64cc9be63004a672f439a7ab70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab05ac64cc9be63004a672f439a7ab70">CAN_F13R2_FB3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed05bb756f656fb754091e64b176bd78">CAN_F13R2_FB3_Pos</a>)</td></tr>
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<tr class="memitem:gaf19767c0892dffb6eff8c5a3b0e254f5" id="r_gaf19767c0892dffb6eff8c5a3b0e254f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf19767c0892dffb6eff8c5a3b0e254f5">CAN_F13R2_FB3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaab05ac64cc9be63004a672f439a7ab70">CAN_F13R2_FB3_Msk</a></td></tr>
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<tr class="memitem:ga44666780046b34e5f5b14ba31f39cefc" id="r_ga44666780046b34e5f5b14ba31f39cefc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44666780046b34e5f5b14ba31f39cefc">CAN_F13R2_FB4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga44666780046b34e5f5b14ba31f39cefc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b936b6b027a2936ab21bd3f46c830aa" id="r_ga0b936b6b027a2936ab21bd3f46c830aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b936b6b027a2936ab21bd3f46c830aa">CAN_F13R2_FB4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga44666780046b34e5f5b14ba31f39cefc">CAN_F13R2_FB4_Pos</a>)</td></tr>
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<tr class="separator:ga0b936b6b027a2936ab21bd3f46c830aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad03b0ab4d686a1ad858f1ba4b679fff9" id="r_gad03b0ab4d686a1ad858f1ba4b679fff9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad03b0ab4d686a1ad858f1ba4b679fff9">CAN_F13R2_FB4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b936b6b027a2936ab21bd3f46c830aa">CAN_F13R2_FB4_Msk</a></td></tr>
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<tr class="separator:gad03b0ab4d686a1ad858f1ba4b679fff9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa84e2ee25ea5266c9ebc55eb15b232ce" id="r_gaa84e2ee25ea5266c9ebc55eb15b232ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa84e2ee25ea5266c9ebc55eb15b232ce">CAN_F13R2_FB5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaa84e2ee25ea5266c9ebc55eb15b232ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff4ab0ef27b2b9cc09019b73f3cffed1" id="r_gaff4ab0ef27b2b9cc09019b73f3cffed1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff4ab0ef27b2b9cc09019b73f3cffed1">CAN_F13R2_FB5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa84e2ee25ea5266c9ebc55eb15b232ce">CAN_F13R2_FB5_Pos</a>)</td></tr>
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<tr class="separator:gaff4ab0ef27b2b9cc09019b73f3cffed1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e37522978ae2e88c27f5604c5517d42" id="r_ga8e37522978ae2e88c27f5604c5517d42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e37522978ae2e88c27f5604c5517d42">CAN_F13R2_FB5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaff4ab0ef27b2b9cc09019b73f3cffed1">CAN_F13R2_FB5_Msk</a></td></tr>
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<tr class="separator:ga8e37522978ae2e88c27f5604c5517d42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf66b4b2eff656482af6adcf8afc007b" id="r_gabf66b4b2eff656482af6adcf8afc007b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf66b4b2eff656482af6adcf8afc007b">CAN_F13R2_FB6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gabf66b4b2eff656482af6adcf8afc007b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf96e3c22df9a1af249c91056375c24dc" id="r_gaf96e3c22df9a1af249c91056375c24dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf96e3c22df9a1af249c91056375c24dc">CAN_F13R2_FB6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf66b4b2eff656482af6adcf8afc007b">CAN_F13R2_FB6_Pos</a>)</td></tr>
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<tr class="memitem:ga2bf6fff2ca4adf6e093a13b2db77adbb" id="r_ga2bf6fff2ca4adf6e093a13b2db77adbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf6fff2ca4adf6e093a13b2db77adbb">CAN_F13R2_FB6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf96e3c22df9a1af249c91056375c24dc">CAN_F13R2_FB6_Msk</a></td></tr>
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<tr class="separator:ga2bf6fff2ca4adf6e093a13b2db77adbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa23426711b2a872dc4c34147415f101c" id="r_gaa23426711b2a872dc4c34147415f101c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa23426711b2a872dc4c34147415f101c">CAN_F13R2_FB7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaa23426711b2a872dc4c34147415f101c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d3accaea73cb0bb14c61c8327adff66" id="r_ga2d3accaea73cb0bb14c61c8327adff66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d3accaea73cb0bb14c61c8327adff66">CAN_F13R2_FB7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa23426711b2a872dc4c34147415f101c">CAN_F13R2_FB7_Pos</a>)</td></tr>
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<tr class="separator:ga2d3accaea73cb0bb14c61c8327adff66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabca970c306c9c9b576ef3424f686f324" id="r_gabca970c306c9c9b576ef3424f686f324"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabca970c306c9c9b576ef3424f686f324">CAN_F13R2_FB7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d3accaea73cb0bb14c61c8327adff66">CAN_F13R2_FB7_Msk</a></td></tr>
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<tr class="memitem:ga3559eca84f9b7d1f99f2a7aee2e4393c" id="r_ga3559eca84f9b7d1f99f2a7aee2e4393c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3559eca84f9b7d1f99f2a7aee2e4393c">CAN_F13R2_FB8_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga5134cad65b0825f53f4f4e78f0c8e11c" id="r_ga5134cad65b0825f53f4f4e78f0c8e11c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5134cad65b0825f53f4f4e78f0c8e11c">CAN_F13R2_FB8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3559eca84f9b7d1f99f2a7aee2e4393c">CAN_F13R2_FB8_Pos</a>)</td></tr>
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<tr class="separator:ga5134cad65b0825f53f4f4e78f0c8e11c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae44e1d120c773c9dc26f418acf3cb6de" id="r_gae44e1d120c773c9dc26f418acf3cb6de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae44e1d120c773c9dc26f418acf3cb6de">CAN_F13R2_FB8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5134cad65b0825f53f4f4e78f0c8e11c">CAN_F13R2_FB8_Msk</a></td></tr>
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<tr class="separator:gae44e1d120c773c9dc26f418acf3cb6de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c54a85b5280816543e0e415fbc96d09" id="r_ga1c54a85b5280816543e0e415fbc96d09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c54a85b5280816543e0e415fbc96d09">CAN_F13R2_FB9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga1c54a85b5280816543e0e415fbc96d09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf13c3a79fcb1bc2bb884dcda8e10ffd0" id="r_gaf13c3a79fcb1bc2bb884dcda8e10ffd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf13c3a79fcb1bc2bb884dcda8e10ffd0">CAN_F13R2_FB9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c54a85b5280816543e0e415fbc96d09">CAN_F13R2_FB9_Pos</a>)</td></tr>
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<tr class="memitem:ga891d1d97e1a57c4cfa1a714b61b083eb" id="r_ga891d1d97e1a57c4cfa1a714b61b083eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga891d1d97e1a57c4cfa1a714b61b083eb">CAN_F13R2_FB9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf13c3a79fcb1bc2bb884dcda8e10ffd0">CAN_F13R2_FB9_Msk</a></td></tr>
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<tr class="separator:ga891d1d97e1a57c4cfa1a714b61b083eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c9c5a2239ce7d523894181eacd0a52e" id="r_ga7c9c5a2239ce7d523894181eacd0a52e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c9c5a2239ce7d523894181eacd0a52e">CAN_F13R2_FB10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga7c9c5a2239ce7d523894181eacd0a52e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ad8207a0741ab38136b3b5c3b1d3d91" id="r_ga7ad8207a0741ab38136b3b5c3b1d3d91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ad8207a0741ab38136b3b5c3b1d3d91">CAN_F13R2_FB10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c9c5a2239ce7d523894181eacd0a52e">CAN_F13R2_FB10_Pos</a>)</td></tr>
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<tr class="memitem:gafb4be9c1da46b251c43c0aafe7b04497" id="r_gafb4be9c1da46b251c43c0aafe7b04497"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb4be9c1da46b251c43c0aafe7b04497">CAN_F13R2_FB10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ad8207a0741ab38136b3b5c3b1d3d91">CAN_F13R2_FB10_Msk</a></td></tr>
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<tr class="separator:gafb4be9c1da46b251c43c0aafe7b04497"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9228d8f828f658636990f7cd5896ccf4" id="r_ga9228d8f828f658636990f7cd5896ccf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9228d8f828f658636990f7cd5896ccf4">CAN_F13R2_FB11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga9228d8f828f658636990f7cd5896ccf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga001860328be3ee22113d0c10f4d3cf23" id="r_ga001860328be3ee22113d0c10f4d3cf23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga001860328be3ee22113d0c10f4d3cf23">CAN_F13R2_FB11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9228d8f828f658636990f7cd5896ccf4">CAN_F13R2_FB11_Pos</a>)</td></tr>
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<tr class="separator:ga001860328be3ee22113d0c10f4d3cf23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47f5215de00574378a489f90eb11eff4" id="r_ga47f5215de00574378a489f90eb11eff4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47f5215de00574378a489f90eb11eff4">CAN_F13R2_FB11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga001860328be3ee22113d0c10f4d3cf23">CAN_F13R2_FB11_Msk</a></td></tr>
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<tr class="memitem:gae031e0a0fe7facb0d7d56c7efd3aa2ea" id="r_gae031e0a0fe7facb0d7d56c7efd3aa2ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae031e0a0fe7facb0d7d56c7efd3aa2ea">CAN_F13R2_FB12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gae031e0a0fe7facb0d7d56c7efd3aa2ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd232459994d381a778abd4aa43bbb70" id="r_gadd232459994d381a778abd4aa43bbb70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd232459994d381a778abd4aa43bbb70">CAN_F13R2_FB12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae031e0a0fe7facb0d7d56c7efd3aa2ea">CAN_F13R2_FB12_Pos</a>)</td></tr>
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<tr class="memitem:gac3bbd5350aeb18966e2a40e2dc4223e3" id="r_gac3bbd5350aeb18966e2a40e2dc4223e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3bbd5350aeb18966e2a40e2dc4223e3">CAN_F13R2_FB12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadd232459994d381a778abd4aa43bbb70">CAN_F13R2_FB12_Msk</a></td></tr>
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<tr class="separator:gac3bbd5350aeb18966e2a40e2dc4223e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5bd52b9aa672bbd50a4a60f2e01c2d1" id="r_gac5bd52b9aa672bbd50a4a60f2e01c2d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5bd52b9aa672bbd50a4a60f2e01c2d1">CAN_F13R2_FB13_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga078d3a3cfba178ef1d8b0499e04326e1" id="r_ga078d3a3cfba178ef1d8b0499e04326e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga078d3a3cfba178ef1d8b0499e04326e1">CAN_F13R2_FB13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac5bd52b9aa672bbd50a4a60f2e01c2d1">CAN_F13R2_FB13_Pos</a>)</td></tr>
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<tr class="separator:ga078d3a3cfba178ef1d8b0499e04326e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2d97199e363dd56cd9a455aec75ef1c" id="r_gab2d97199e363dd56cd9a455aec75ef1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2d97199e363dd56cd9a455aec75ef1c">CAN_F13R2_FB13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga078d3a3cfba178ef1d8b0499e04326e1">CAN_F13R2_FB13_Msk</a></td></tr>
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<tr class="separator:gab2d97199e363dd56cd9a455aec75ef1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab32e372353ed3e56c1aad445b2616c58" id="r_gab32e372353ed3e56c1aad445b2616c58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab32e372353ed3e56c1aad445b2616c58">CAN_F13R2_FB14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gab32e372353ed3e56c1aad445b2616c58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47b3e370df1a4ec6f8a69cd648a823cb" id="r_ga47b3e370df1a4ec6f8a69cd648a823cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47b3e370df1a4ec6f8a69cd648a823cb">CAN_F13R2_FB14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab32e372353ed3e56c1aad445b2616c58">CAN_F13R2_FB14_Pos</a>)</td></tr>
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<tr class="separator:ga47b3e370df1a4ec6f8a69cd648a823cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0731f4e60125130bebf88d33fd4ae3ca" id="r_ga0731f4e60125130bebf88d33fd4ae3ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0731f4e60125130bebf88d33fd4ae3ca">CAN_F13R2_FB14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47b3e370df1a4ec6f8a69cd648a823cb">CAN_F13R2_FB14_Msk</a></td></tr>
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<tr class="separator:ga0731f4e60125130bebf88d33fd4ae3ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb6696be0087357ad560cf24aa616021" id="r_gacb6696be0087357ad560cf24aa616021"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb6696be0087357ad560cf24aa616021">CAN_F13R2_FB15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gacb6696be0087357ad560cf24aa616021"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga760672a8bb29f0054fbef52bc3b71c0a" id="r_ga760672a8bb29f0054fbef52bc3b71c0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga760672a8bb29f0054fbef52bc3b71c0a">CAN_F13R2_FB15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacb6696be0087357ad560cf24aa616021">CAN_F13R2_FB15_Pos</a>)</td></tr>
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<tr class="separator:ga760672a8bb29f0054fbef52bc3b71c0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1683c0cc3b3143a919f4dd59243eba9f" id="r_ga1683c0cc3b3143a919f4dd59243eba9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1683c0cc3b3143a919f4dd59243eba9f">CAN_F13R2_FB15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga760672a8bb29f0054fbef52bc3b71c0a">CAN_F13R2_FB15_Msk</a></td></tr>
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<tr class="separator:ga1683c0cc3b3143a919f4dd59243eba9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83eca0eb5bea5956eeb4ab174c366f75" id="r_ga83eca0eb5bea5956eeb4ab174c366f75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83eca0eb5bea5956eeb4ab174c366f75">CAN_F13R2_FB16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga83eca0eb5bea5956eeb4ab174c366f75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ce486f2da389ec7cf80e6d102b7bc56" id="r_ga2ce486f2da389ec7cf80e6d102b7bc56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ce486f2da389ec7cf80e6d102b7bc56">CAN_F13R2_FB16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83eca0eb5bea5956eeb4ab174c366f75">CAN_F13R2_FB16_Pos</a>)</td></tr>
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<tr class="separator:ga2ce486f2da389ec7cf80e6d102b7bc56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2ed74a0929c6d397c14f49f114f13bf" id="r_gad2ed74a0929c6d397c14f49f114f13bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2ed74a0929c6d397c14f49f114f13bf">CAN_F13R2_FB16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ce486f2da389ec7cf80e6d102b7bc56">CAN_F13R2_FB16_Msk</a></td></tr>
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<tr class="separator:gad2ed74a0929c6d397c14f49f114f13bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8db0458a7ddad624a4fe50458f06ebe7" id="r_ga8db0458a7ddad624a4fe50458f06ebe7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8db0458a7ddad624a4fe50458f06ebe7">CAN_F13R2_FB17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga8db0458a7ddad624a4fe50458f06ebe7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d552599612053845141e0db3c89ca86" id="r_ga9d552599612053845141e0db3c89ca86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d552599612053845141e0db3c89ca86">CAN_F13R2_FB17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8db0458a7ddad624a4fe50458f06ebe7">CAN_F13R2_FB17_Pos</a>)</td></tr>
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<tr class="separator:ga9d552599612053845141e0db3c89ca86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafde6cdff22bf29d31b5be1b309fe4dde" id="r_gafde6cdff22bf29d31b5be1b309fe4dde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafde6cdff22bf29d31b5be1b309fe4dde">CAN_F13R2_FB17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d552599612053845141e0db3c89ca86">CAN_F13R2_FB17_Msk</a></td></tr>
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<tr class="separator:gafde6cdff22bf29d31b5be1b309fe4dde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga041ea608c1e920eca8e6b12027331761" id="r_ga041ea608c1e920eca8e6b12027331761"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga041ea608c1e920eca8e6b12027331761">CAN_F13R2_FB18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga041ea608c1e920eca8e6b12027331761"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34fcf71e30ba700e1b975c6273a99de5" id="r_ga34fcf71e30ba700e1b975c6273a99de5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34fcf71e30ba700e1b975c6273a99de5">CAN_F13R2_FB18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga041ea608c1e920eca8e6b12027331761">CAN_F13R2_FB18_Pos</a>)</td></tr>
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<tr class="separator:ga34fcf71e30ba700e1b975c6273a99de5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb873fa1c32fbf6c5a2f3be93ba2f2e6" id="r_gabb873fa1c32fbf6c5a2f3be93ba2f2e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb873fa1c32fbf6c5a2f3be93ba2f2e6">CAN_F13R2_FB18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34fcf71e30ba700e1b975c6273a99de5">CAN_F13R2_FB18_Msk</a></td></tr>
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<tr class="separator:gabb873fa1c32fbf6c5a2f3be93ba2f2e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7e96e3beea2a3c1bffb610cebf01012" id="r_gac7e96e3beea2a3c1bffb610cebf01012"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7e96e3beea2a3c1bffb610cebf01012">CAN_F13R2_FB19_Pos</a>   (19U)</td></tr>
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<tr class="separator:gac7e96e3beea2a3c1bffb610cebf01012"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5b5c1ede34327d024575f334f3895b7" id="r_gaa5b5c1ede34327d024575f334f3895b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5b5c1ede34327d024575f334f3895b7">CAN_F13R2_FB19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac7e96e3beea2a3c1bffb610cebf01012">CAN_F13R2_FB19_Pos</a>)</td></tr>
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<tr class="separator:gaa5b5c1ede34327d024575f334f3895b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf82a4dfd4d3c7a13232479be997ed1f9" id="r_gaf82a4dfd4d3c7a13232479be997ed1f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf82a4dfd4d3c7a13232479be997ed1f9">CAN_F13R2_FB19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5b5c1ede34327d024575f334f3895b7">CAN_F13R2_FB19_Msk</a></td></tr>
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<tr class="separator:gaf82a4dfd4d3c7a13232479be997ed1f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa79bef1cef0cab3783a6351067a28670" id="r_gaa79bef1cef0cab3783a6351067a28670"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa79bef1cef0cab3783a6351067a28670">CAN_F13R2_FB20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gaa79bef1cef0cab3783a6351067a28670"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae823f61c39d0a97b05947308792e122" id="r_gaae823f61c39d0a97b05947308792e122"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae823f61c39d0a97b05947308792e122">CAN_F13R2_FB20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa79bef1cef0cab3783a6351067a28670">CAN_F13R2_FB20_Pos</a>)</td></tr>
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<tr class="separator:gaae823f61c39d0a97b05947308792e122"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7bf4384e44f002392339a71bc9c912c" id="r_gaa7bf4384e44f002392339a71bc9c912c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7bf4384e44f002392339a71bc9c912c">CAN_F13R2_FB20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae823f61c39d0a97b05947308792e122">CAN_F13R2_FB20_Msk</a></td></tr>
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<tr class="separator:gaa7bf4384e44f002392339a71bc9c912c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c135cf4d4773022ff4a284d13672082" id="r_ga6c135cf4d4773022ff4a284d13672082"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c135cf4d4773022ff4a284d13672082">CAN_F13R2_FB21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga6c135cf4d4773022ff4a284d13672082"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabea7b7f481ba0bc31d2909460e0bc54e" id="r_gabea7b7f481ba0bc31d2909460e0bc54e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabea7b7f481ba0bc31d2909460e0bc54e">CAN_F13R2_FB21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c135cf4d4773022ff4a284d13672082">CAN_F13R2_FB21_Pos</a>)</td></tr>
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<tr class="separator:gabea7b7f481ba0bc31d2909460e0bc54e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7023986be02dd8f736e04e658844061" id="r_gaa7023986be02dd8f736e04e658844061"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7023986be02dd8f736e04e658844061">CAN_F13R2_FB21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabea7b7f481ba0bc31d2909460e0bc54e">CAN_F13R2_FB21_Msk</a></td></tr>
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<tr class="separator:gaa7023986be02dd8f736e04e658844061"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06db7af2bea27dea18c2c36b0ff73afa" id="r_ga06db7af2bea27dea18c2c36b0ff73afa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06db7af2bea27dea18c2c36b0ff73afa">CAN_F13R2_FB22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga06db7af2bea27dea18c2c36b0ff73afa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66fb2f382a4967515fa63a8454131fb9" id="r_ga66fb2f382a4967515fa63a8454131fb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66fb2f382a4967515fa63a8454131fb9">CAN_F13R2_FB22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga06db7af2bea27dea18c2c36b0ff73afa">CAN_F13R2_FB22_Pos</a>)</td></tr>
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<tr class="memitem:gafd059121f2a882342a409ebef8a96999" id="r_gafd059121f2a882342a409ebef8a96999"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd059121f2a882342a409ebef8a96999">CAN_F13R2_FB22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga66fb2f382a4967515fa63a8454131fb9">CAN_F13R2_FB22_Msk</a></td></tr>
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<tr class="separator:gafd059121f2a882342a409ebef8a96999"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb354c4f61952c7a85f0ef302163b0e9" id="r_gaeb354c4f61952c7a85f0ef302163b0e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb354c4f61952c7a85f0ef302163b0e9">CAN_F13R2_FB23_Pos</a>   (23U)</td></tr>
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<tr class="separator:gaeb354c4f61952c7a85f0ef302163b0e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bee64a9c633df1a34f5435406103085" id="r_ga2bee64a9c633df1a34f5435406103085"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bee64a9c633df1a34f5435406103085">CAN_F13R2_FB23_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb354c4f61952c7a85f0ef302163b0e9">CAN_F13R2_FB23_Pos</a>)</td></tr>
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<tr class="separator:ga2bee64a9c633df1a34f5435406103085"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ef57f88bf1e6e34b0096013278926c0" id="r_ga5ef57f88bf1e6e34b0096013278926c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ef57f88bf1e6e34b0096013278926c0">CAN_F13R2_FB23</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2bee64a9c633df1a34f5435406103085">CAN_F13R2_FB23_Msk</a></td></tr>
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<tr class="separator:ga5ef57f88bf1e6e34b0096013278926c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b46be4b9570584370ce39342df1d8c5" id="r_ga7b46be4b9570584370ce39342df1d8c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b46be4b9570584370ce39342df1d8c5">CAN_F13R2_FB24_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga7b46be4b9570584370ce39342df1d8c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b4176f0f14ef22173c436763a6c483e" id="r_ga0b4176f0f14ef22173c436763a6c483e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b4176f0f14ef22173c436763a6c483e">CAN_F13R2_FB24_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b46be4b9570584370ce39342df1d8c5">CAN_F13R2_FB24_Pos</a>)</td></tr>
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<tr class="separator:ga0b4176f0f14ef22173c436763a6c483e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4847de9f5b54fc5ce00e0fba69564d2d" id="r_ga4847de9f5b54fc5ce00e0fba69564d2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4847de9f5b54fc5ce00e0fba69564d2d">CAN_F13R2_FB24</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b4176f0f14ef22173c436763a6c483e">CAN_F13R2_FB24_Msk</a></td></tr>
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<tr class="separator:ga4847de9f5b54fc5ce00e0fba69564d2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d1923954a761ac8ae84432354317806" id="r_ga0d1923954a761ac8ae84432354317806"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d1923954a761ac8ae84432354317806">CAN_F13R2_FB25_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga0d1923954a761ac8ae84432354317806"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad55a497a172eeaeb711d04f5cc81f411" id="r_gad55a497a172eeaeb711d04f5cc81f411"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad55a497a172eeaeb711d04f5cc81f411">CAN_F13R2_FB25_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d1923954a761ac8ae84432354317806">CAN_F13R2_FB25_Pos</a>)</td></tr>
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<tr class="separator:gad55a497a172eeaeb711d04f5cc81f411"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c415fa87c556bd8a4fc0f680d25f160" id="r_ga2c415fa87c556bd8a4fc0f680d25f160"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c415fa87c556bd8a4fc0f680d25f160">CAN_F13R2_FB25</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad55a497a172eeaeb711d04f5cc81f411">CAN_F13R2_FB25_Msk</a></td></tr>
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<tr class="separator:ga2c415fa87c556bd8a4fc0f680d25f160"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27b86a7f094043e077a15a6b36cab7fe" id="r_ga27b86a7f094043e077a15a6b36cab7fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27b86a7f094043e077a15a6b36cab7fe">CAN_F13R2_FB26_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga27b86a7f094043e077a15a6b36cab7fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga117bfac3184445e41ca1709495cd1603" id="r_ga117bfac3184445e41ca1709495cd1603"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga117bfac3184445e41ca1709495cd1603">CAN_F13R2_FB26_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27b86a7f094043e077a15a6b36cab7fe">CAN_F13R2_FB26_Pos</a>)</td></tr>
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<tr class="separator:ga117bfac3184445e41ca1709495cd1603"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20487222c41a08fe68b9ce58dfd52fff" id="r_ga20487222c41a08fe68b9ce58dfd52fff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20487222c41a08fe68b9ce58dfd52fff">CAN_F13R2_FB26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga117bfac3184445e41ca1709495cd1603">CAN_F13R2_FB26_Msk</a></td></tr>
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<tr class="separator:ga20487222c41a08fe68b9ce58dfd52fff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e7f1c6169d847c9acf1cc737ecf4e6f" id="r_ga4e7f1c6169d847c9acf1cc737ecf4e6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e7f1c6169d847c9acf1cc737ecf4e6f">CAN_F13R2_FB27_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga4e7f1c6169d847c9acf1cc737ecf4e6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2716a8a28de7a05f7f448d6b581928fe" id="r_ga2716a8a28de7a05f7f448d6b581928fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2716a8a28de7a05f7f448d6b581928fe">CAN_F13R2_FB27_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e7f1c6169d847c9acf1cc737ecf4e6f">CAN_F13R2_FB27_Pos</a>)</td></tr>
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<tr class="separator:ga2716a8a28de7a05f7f448d6b581928fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0d5ca021778a6e84fd3c0ad8981255d" id="r_gaa0d5ca021778a6e84fd3c0ad8981255d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0d5ca021778a6e84fd3c0ad8981255d">CAN_F13R2_FB27</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2716a8a28de7a05f7f448d6b581928fe">CAN_F13R2_FB27_Msk</a></td></tr>
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<tr class="separator:gaa0d5ca021778a6e84fd3c0ad8981255d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63a19687e787196f324bf380130defc4" id="r_ga63a19687e787196f324bf380130defc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63a19687e787196f324bf380130defc4">CAN_F13R2_FB28_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga63a19687e787196f324bf380130defc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf9c86580fedab6d11c0e935e787fd31" id="r_gabf9c86580fedab6d11c0e935e787fd31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf9c86580fedab6d11c0e935e787fd31">CAN_F13R2_FB28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga63a19687e787196f324bf380130defc4">CAN_F13R2_FB28_Pos</a>)</td></tr>
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<tr class="separator:gabf9c86580fedab6d11c0e935e787fd31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f0c8c09be20a14f29ab46d53dd712ba" id="r_ga2f0c8c09be20a14f29ab46d53dd712ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f0c8c09be20a14f29ab46d53dd712ba">CAN_F13R2_FB28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabf9c86580fedab6d11c0e935e787fd31">CAN_F13R2_FB28_Msk</a></td></tr>
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<tr class="separator:ga2f0c8c09be20a14f29ab46d53dd712ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6229421e0e7697e0210ab0281c949f45" id="r_ga6229421e0e7697e0210ab0281c949f45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6229421e0e7697e0210ab0281c949f45">CAN_F13R2_FB29_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga6229421e0e7697e0210ab0281c949f45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabed854c540fda686a9c51d21cf45cff3" id="r_gabed854c540fda686a9c51d21cf45cff3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabed854c540fda686a9c51d21cf45cff3">CAN_F13R2_FB29_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6229421e0e7697e0210ab0281c949f45">CAN_F13R2_FB29_Pos</a>)</td></tr>
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<tr class="separator:gabed854c540fda686a9c51d21cf45cff3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26161b84a5fc507f959b620c8e380703" id="r_ga26161b84a5fc507f959b620c8e380703"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26161b84a5fc507f959b620c8e380703">CAN_F13R2_FB29</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabed854c540fda686a9c51d21cf45cff3">CAN_F13R2_FB29_Msk</a></td></tr>
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<tr class="separator:ga26161b84a5fc507f959b620c8e380703"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36f10ded80a4a78d7cf92f8b6f3ed078" id="r_ga36f10ded80a4a78d7cf92f8b6f3ed078"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36f10ded80a4a78d7cf92f8b6f3ed078">CAN_F13R2_FB30_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga36f10ded80a4a78d7cf92f8b6f3ed078"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga812a202cba22a21b94811b815cc57611" id="r_ga812a202cba22a21b94811b815cc57611"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga812a202cba22a21b94811b815cc57611">CAN_F13R2_FB30_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga36f10ded80a4a78d7cf92f8b6f3ed078">CAN_F13R2_FB30_Pos</a>)</td></tr>
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<tr class="separator:ga812a202cba22a21b94811b815cc57611"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e753550a0a8547c7f64346e22925012" id="r_ga1e753550a0a8547c7f64346e22925012"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e753550a0a8547c7f64346e22925012">CAN_F13R2_FB30</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga812a202cba22a21b94811b815cc57611">CAN_F13R2_FB30_Msk</a></td></tr>
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<tr class="separator:ga1e753550a0a8547c7f64346e22925012"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6af7dbbe2d835ab3d050971ac07a0ea3" id="r_ga6af7dbbe2d835ab3d050971ac07a0ea3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6af7dbbe2d835ab3d050971ac07a0ea3">CAN_F13R2_FB31_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga6af7dbbe2d835ab3d050971ac07a0ea3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6eceafce3dabadee19db4afd0e0884d6" id="r_ga6eceafce3dabadee19db4afd0e0884d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6eceafce3dabadee19db4afd0e0884d6">CAN_F13R2_FB31_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6af7dbbe2d835ab3d050971ac07a0ea3">CAN_F13R2_FB31_Pos</a>)</td></tr>
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<tr class="separator:ga6eceafce3dabadee19db4afd0e0884d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga305ac04b1c5198a4f82c78c570ce7f97" id="r_ga305ac04b1c5198a4f82c78c570ce7f97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga305ac04b1c5198a4f82c78c570ce7f97">CAN_F13R2_FB31</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6eceafce3dabadee19db4afd0e0884d6">CAN_F13R2_FB31_Msk</a></td></tr>
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<tr class="separator:ga305ac04b1c5198a4f82c78c570ce7f97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3deebcf1cf5fae1957476154502b1fb5" id="r_ga3deebcf1cf5fae1957476154502b1fb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3deebcf1cf5fae1957476154502b1fb5">CRC_DR_DR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3deebcf1cf5fae1957476154502b1fb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd43c14689d281daa4e9a32bf8ec89e1" id="r_gadd43c14689d281daa4e9a32bf8ec89e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd43c14689d281daa4e9a32bf8ec89e1">CRC_DR_DR_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3deebcf1cf5fae1957476154502b1fb5">CRC_DR_DR_Pos</a>)</td></tr>
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<tr class="separator:gadd43c14689d281daa4e9a32bf8ec89e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bf4701d3b15924e657942ce3caa4105" id="r_ga2bf4701d3b15924e657942ce3caa4105"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf4701d3b15924e657942ce3caa4105">CRC_DR_DR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadd43c14689d281daa4e9a32bf8ec89e1">CRC_DR_DR_Msk</a></td></tr>
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<tr class="separator:ga2bf4701d3b15924e657942ce3caa4105"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab63759809b1cd1cfdf46d92becc60f85" id="r_gab63759809b1cd1cfdf46d92becc60f85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab63759809b1cd1cfdf46d92becc60f85">CRC_IDR_IDR_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab63759809b1cd1cfdf46d92becc60f85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga306789258d5416a44e545aa2ad6b2f7a" id="r_ga306789258d5416a44e545aa2ad6b2f7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga306789258d5416a44e545aa2ad6b2f7a">CRC_IDR_IDR_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab63759809b1cd1cfdf46d92becc60f85">CRC_IDR_IDR_Pos</a>)</td></tr>
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<tr class="memitem:gae9a0feb3cf1d8c5871e663ca4a174cc0" id="r_gae9a0feb3cf1d8c5871e663ca4a174cc0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9a0feb3cf1d8c5871e663ca4a174cc0">CRC_IDR_IDR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga306789258d5416a44e545aa2ad6b2f7a">CRC_IDR_IDR_Msk</a></td></tr>
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<tr class="memitem:ga7a12ab5306d6320069e08e63cd9a56f1" id="r_ga7a12ab5306d6320069e08e63cd9a56f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a12ab5306d6320069e08e63cd9a56f1">CRC_CR_RESET_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7a12ab5306d6320069e08e63cd9a56f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04d46dadb6b31660c4ef0af2b00053f5" id="r_ga04d46dadb6b31660c4ef0af2b00053f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04d46dadb6b31660c4ef0af2b00053f5">CRC_CR_RESET_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a12ab5306d6320069e08e63cd9a56f1">CRC_CR_RESET_Pos</a>)</td></tr>
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<tr class="memitem:ga7d57481fb891a0964b40f721354c56d7" id="r_ga7d57481fb891a0964b40f721354c56d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d57481fb891a0964b40f721354c56d7">CRC_CR_RESET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga04d46dadb6b31660c4ef0af2b00053f5">CRC_CR_RESET_Msk</a></td></tr>
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<tr class="memitem:ga88aaf7e89ddcd648227fd514315c9838" id="r_ga88aaf7e89ddcd648227fd514315c9838"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88aaf7e89ddcd648227fd514315c9838">DAC_CHANNEL2_SUPPORT</a></td></tr>
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<tr class="memitem:ga7663eb8440e12383fc88241acbfc99cf" id="r_ga7663eb8440e12383fc88241acbfc99cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7663eb8440e12383fc88241acbfc99cf">DAC_CR_EN1_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gaa4462abe77801be4a752c73aa2ff9a70" id="r_gaa4462abe77801be4a752c73aa2ff9a70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4462abe77801be4a752c73aa2ff9a70">DAC_CR_EN1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7663eb8440e12383fc88241acbfc99cf">DAC_CR_EN1_Pos</a>)</td></tr>
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<tr class="memitem:gabd8cedbb3dda03d56ac0ba92d2d9cefd" id="r_gabd8cedbb3dda03d56ac0ba92d2d9cefd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd8cedbb3dda03d56ac0ba92d2d9cefd">DAC_CR_EN1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4462abe77801be4a752c73aa2ff9a70">DAC_CR_EN1_Msk</a></td></tr>
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<tr class="memitem:ga9f43af44fba93c50bf4765608ec6d902" id="r_ga9f43af44fba93c50bf4765608ec6d902"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f43af44fba93c50bf4765608ec6d902">DAC_CR_BOFF1_Pos</a>   (1U)</td></tr>
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<tr class="memitem:gad4cba0a69210b9ccb8566cfb83196e6f" id="r_gad4cba0a69210b9ccb8566cfb83196e6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4cba0a69210b9ccb8566cfb83196e6f">DAC_CR_BOFF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f43af44fba93c50bf4765608ec6d902">DAC_CR_BOFF1_Pos</a>)</td></tr>
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<tr class="memitem:ga0b1e2b83ae1ab889cb1e34a99746c9d8" id="r_ga0b1e2b83ae1ab889cb1e34a99746c9d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b1e2b83ae1ab889cb1e34a99746c9d8">DAC_CR_BOFF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad4cba0a69210b9ccb8566cfb83196e6f">DAC_CR_BOFF1_Msk</a></td></tr>
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<tr class="memitem:ga6ef4ab719505604c7a41e31c27fd05dd" id="r_ga6ef4ab719505604c7a41e31c27fd05dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ef4ab719505604c7a41e31c27fd05dd">DAC_CR_TEN1_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga1be7eb4a830047b463d611c2c813f437" id="r_ga1be7eb4a830047b463d611c2c813f437"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1be7eb4a830047b463d611c2c813f437">DAC_CR_TEN1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ef4ab719505604c7a41e31c27fd05dd">DAC_CR_TEN1_Pos</a>)</td></tr>
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<tr class="separator:ga1be7eb4a830047b463d611c2c813f437"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga998aa4fd791ea2f4626df6ddc8fc7109" id="r_ga998aa4fd791ea2f4626df6ddc8fc7109"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga998aa4fd791ea2f4626df6ddc8fc7109">DAC_CR_TEN1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1be7eb4a830047b463d611c2c813f437">DAC_CR_TEN1_Msk</a></td></tr>
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<tr class="memitem:gadc5baf43a193c631ad3c05eb24b97a7b" id="r_gadc5baf43a193c631ad3c05eb24b97a7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc5baf43a193c631ad3c05eb24b97a7b">DAC_CR_TSEL1_Pos</a>   (3U)</td></tr>
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<tr class="separator:gadc5baf43a193c631ad3c05eb24b97a7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ca56925c2b1f9c7662c850146bec7bd" id="r_ga0ca56925c2b1f9c7662c850146bec7bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ca56925c2b1f9c7662c850146bec7bd">DAC_CR_TSEL1_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadc5baf43a193c631ad3c05eb24b97a7b">DAC_CR_TSEL1_Pos</a>)</td></tr>
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<tr class="memitem:gaf951c1a57a1a19e356df57d908f09c6c" id="r_gaf951c1a57a1a19e356df57d908f09c6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf951c1a57a1a19e356df57d908f09c6c">DAC_CR_TSEL1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ca56925c2b1f9c7662c850146bec7bd">DAC_CR_TSEL1_Msk</a></td></tr>
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<tr class="separator:gaf951c1a57a1a19e356df57d908f09c6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8dfa13ec123c583136e24b7890add45b" id="r_ga8dfa13ec123c583136e24b7890add45b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8dfa13ec123c583136e24b7890add45b">DAC_CR_TSEL1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadc5baf43a193c631ad3c05eb24b97a7b">DAC_CR_TSEL1_Pos</a>)</td></tr>
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<tr class="memitem:ga265e32c4fc43310acdf3ebea01376766" id="r_ga265e32c4fc43310acdf3ebea01376766"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga265e32c4fc43310acdf3ebea01376766">DAC_CR_TSEL1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadc5baf43a193c631ad3c05eb24b97a7b">DAC_CR_TSEL1_Pos</a>)</td></tr>
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<tr class="memitem:gaa625d7638422e90a616ac93edd4bf408" id="r_gaa625d7638422e90a616ac93edd4bf408"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa625d7638422e90a616ac93edd4bf408">DAC_CR_TSEL1_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadc5baf43a193c631ad3c05eb24b97a7b">DAC_CR_TSEL1_Pos</a>)</td></tr>
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<tr class="memitem:ga16a0202d6e3295400dc21b2088d333e1" id="r_ga16a0202d6e3295400dc21b2088d333e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16a0202d6e3295400dc21b2088d333e1">DAC_CR_WAVE1_Pos</a>   (6U)</td></tr>
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<tr class="memitem:ga8d85e9d75f265088a37b911f573e7dd3" id="r_ga8d85e9d75f265088a37b911f573e7dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d85e9d75f265088a37b911f573e7dd3">DAC_CR_WAVE1_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16a0202d6e3295400dc21b2088d333e1">DAC_CR_WAVE1_Pos</a>)</td></tr>
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<tr class="separator:ga8d85e9d75f265088a37b911f573e7dd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90491f31219d07175629eecdcdc9271e" id="r_ga90491f31219d07175629eecdcdc9271e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90491f31219d07175629eecdcdc9271e">DAC_CR_WAVE1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d85e9d75f265088a37b911f573e7dd3">DAC_CR_WAVE1_Msk</a></td></tr>
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<tr class="separator:ga90491f31219d07175629eecdcdc9271e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0871e6466e3a7378103c431832ae525a" id="r_ga0871e6466e3a7378103c431832ae525a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0871e6466e3a7378103c431832ae525a">DAC_CR_WAVE1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16a0202d6e3295400dc21b2088d333e1">DAC_CR_WAVE1_Pos</a>)</td></tr>
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<tr class="memitem:ga48e167ae02d2ad5bc9fd30c2f8ea5b37" id="r_ga48e167ae02d2ad5bc9fd30c2f8ea5b37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48e167ae02d2ad5bc9fd30c2f8ea5b37">DAC_CR_WAVE1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16a0202d6e3295400dc21b2088d333e1">DAC_CR_WAVE1_Pos</a>)</td></tr>
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<tr class="separator:ga48e167ae02d2ad5bc9fd30c2f8ea5b37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga018b4d24c02a803f2efb996745f49015" id="r_ga018b4d24c02a803f2efb996745f49015"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga018b4d24c02a803f2efb996745f49015">DAC_CR_MAMP1_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga7f4fc31ff760aaa38ad85da8c4f1918a" id="r_ga7f4fc31ff760aaa38ad85da8c4f1918a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f4fc31ff760aaa38ad85da8c4f1918a">DAC_CR_MAMP1_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga018b4d24c02a803f2efb996745f49015">DAC_CR_MAMP1_Pos</a>)</td></tr>
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<tr class="memitem:ga3bcf611b2f0b975513325895bf16e085" id="r_ga3bcf611b2f0b975513325895bf16e085"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bcf611b2f0b975513325895bf16e085">DAC_CR_MAMP1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f4fc31ff760aaa38ad85da8c4f1918a">DAC_CR_MAMP1_Msk</a></td></tr>
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<tr class="memitem:ga4225dcce22b440fcd3a8ad96c5f2baec" id="r_ga4225dcce22b440fcd3a8ad96c5f2baec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4225dcce22b440fcd3a8ad96c5f2baec">DAC_CR_MAMP1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga018b4d24c02a803f2efb996745f49015">DAC_CR_MAMP1_Pos</a>)</td></tr>
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<tr class="separator:ga4225dcce22b440fcd3a8ad96c5f2baec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cc15817842cb7992d449c448684f68d" id="r_ga6cc15817842cb7992d449c448684f68d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cc15817842cb7992d449c448684f68d">DAC_CR_MAMP1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga018b4d24c02a803f2efb996745f49015">DAC_CR_MAMP1_Pos</a>)</td></tr>
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<tr class="memitem:ga0fefef1d798a2685b03e44bd9fdac06b" id="r_ga0fefef1d798a2685b03e44bd9fdac06b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fefef1d798a2685b03e44bd9fdac06b">DAC_CR_MAMP1_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga018b4d24c02a803f2efb996745f49015">DAC_CR_MAMP1_Pos</a>)</td></tr>
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<tr class="memitem:gafdc83b4feb742c632ba66f55d102432b" id="r_gafdc83b4feb742c632ba66f55d102432b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdc83b4feb742c632ba66f55d102432b">DAC_CR_MAMP1_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga018b4d24c02a803f2efb996745f49015">DAC_CR_MAMP1_Pos</a>)</td></tr>
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<tr class="memitem:gac1caf9621895f2a99c4b33a0908247b6" id="r_gac1caf9621895f2a99c4b33a0908247b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1caf9621895f2a99c4b33a0908247b6">DAC_CR_DMAEN1_Pos</a>   (12U)</td></tr>
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<tr class="memitem:ga6509ff097fb987e9f1c592d6d5869356" id="r_ga6509ff097fb987e9f1c592d6d5869356"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6509ff097fb987e9f1c592d6d5869356">DAC_CR_DMAEN1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac1caf9621895f2a99c4b33a0908247b6">DAC_CR_DMAEN1_Pos</a>)</td></tr>
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<tr class="separator:ga6509ff097fb987e9f1c592d6d5869356"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga995c19d8c8de9ee09057ec6151154e17" id="r_ga995c19d8c8de9ee09057ec6151154e17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga995c19d8c8de9ee09057ec6151154e17">DAC_CR_DMAEN1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6509ff097fb987e9f1c592d6d5869356">DAC_CR_DMAEN1_Msk</a></td></tr>
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<tr class="separator:ga995c19d8c8de9ee09057ec6151154e17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a11a25b89aa18648594cb72bf3918bf" id="r_ga8a11a25b89aa18648594cb72bf3918bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a11a25b89aa18648594cb72bf3918bf">DAC_CR_DMAUDRIE1_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga8a11a25b89aa18648594cb72bf3918bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ad8aa68545055eac63ab43cc5d3da91" id="r_ga8ad8aa68545055eac63ab43cc5d3da91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ad8aa68545055eac63ab43cc5d3da91">DAC_CR_DMAUDRIE1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a11a25b89aa18648594cb72bf3918bf">DAC_CR_DMAUDRIE1_Pos</a>)</td></tr>
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<tr class="separator:ga8ad8aa68545055eac63ab43cc5d3da91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbb0585e1053abf18cd129ad76a66bea" id="r_gacbb0585e1053abf18cd129ad76a66bea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbb0585e1053abf18cd129ad76a66bea">DAC_CR_DMAUDRIE1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ad8aa68545055eac63ab43cc5d3da91">DAC_CR_DMAUDRIE1_Msk</a></td></tr>
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<tr class="separator:gacbb0585e1053abf18cd129ad76a66bea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2dbea8c55239069a24139f398785af4" id="r_gaf2dbea8c55239069a24139f398785af4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2dbea8c55239069a24139f398785af4">DAC_CR_EN2_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaf2dbea8c55239069a24139f398785af4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84b276403310ffa2407b8c57996456e7" id="r_ga84b276403310ffa2407b8c57996456e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84b276403310ffa2407b8c57996456e7">DAC_CR_EN2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2dbea8c55239069a24139f398785af4">DAC_CR_EN2_Pos</a>)</td></tr>
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<tr class="separator:ga84b276403310ffa2407b8c57996456e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa65db2420e02fc6813842f57134d898f" id="r_gaa65db2420e02fc6813842f57134d898f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa65db2420e02fc6813842f57134d898f">DAC_CR_EN2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga84b276403310ffa2407b8c57996456e7">DAC_CR_EN2_Msk</a></td></tr>
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<tr class="separator:gaa65db2420e02fc6813842f57134d898f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb3eb9eaa48220ba7cac6204c4637b75" id="r_gabb3eb9eaa48220ba7cac6204c4637b75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb3eb9eaa48220ba7cac6204c4637b75">DAC_CR_BOFF2_Pos</a>   (17U)</td></tr>
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<tr class="separator:gabb3eb9eaa48220ba7cac6204c4637b75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga088fea2fa6ece1301af6818b836469f3" id="r_ga088fea2fa6ece1301af6818b836469f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga088fea2fa6ece1301af6818b836469f3">DAC_CR_BOFF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb3eb9eaa48220ba7cac6204c4637b75">DAC_CR_BOFF2_Pos</a>)</td></tr>
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<tr class="separator:ga088fea2fa6ece1301af6818b836469f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd6f660a5f15262beca06b9098a559e9" id="r_gadd6f660a5f15262beca06b9098a559e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd6f660a5f15262beca06b9098a559e9">DAC_CR_BOFF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga088fea2fa6ece1301af6818b836469f3">DAC_CR_BOFF2_Msk</a></td></tr>
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<tr class="separator:gadd6f660a5f15262beca06b9098a559e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2ef8fa2150330a16a2b19f17caa051e" id="r_gaa2ef8fa2150330a16a2b19f17caa051e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2ef8fa2150330a16a2b19f17caa051e">DAC_CR_TEN2_Pos</a>   (18U)</td></tr>
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<tr class="separator:gaa2ef8fa2150330a16a2b19f17caa051e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac16d129b7793ddcfef47bd642478d1df" id="r_gac16d129b7793ddcfef47bd642478d1df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac16d129b7793ddcfef47bd642478d1df">DAC_CR_TEN2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2ef8fa2150330a16a2b19f17caa051e">DAC_CR_TEN2_Pos</a>)</td></tr>
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<tr class="separator:gac16d129b7793ddcfef47bd642478d1df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8fc527f6ddb787123da09d2085b772f" id="r_gab8fc527f6ddb787123da09d2085b772f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8fc527f6ddb787123da09d2085b772f">DAC_CR_TEN2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac16d129b7793ddcfef47bd642478d1df">DAC_CR_TEN2_Msk</a></td></tr>
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<tr class="separator:gab8fc527f6ddb787123da09d2085b772f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80a933188591c4fbcad260c256105277" id="r_ga80a933188591c4fbcad260c256105277"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80a933188591c4fbcad260c256105277">DAC_CR_TSEL2_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga80a933188591c4fbcad260c256105277"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c9339a1dc175b09378d1168ab514333" id="r_ga0c9339a1dc175b09378d1168ab514333"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c9339a1dc175b09378d1168ab514333">DAC_CR_TSEL2_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80a933188591c4fbcad260c256105277">DAC_CR_TSEL2_Pos</a>)</td></tr>
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<tr class="separator:ga0c9339a1dc175b09378d1168ab514333"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73b4d0ccff78f7c3862903e7b0e66302" id="r_ga73b4d0ccff78f7c3862903e7b0e66302"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73b4d0ccff78f7c3862903e7b0e66302">DAC_CR_TSEL2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c9339a1dc175b09378d1168ab514333">DAC_CR_TSEL2_Msk</a></td></tr>
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<tr class="separator:ga73b4d0ccff78f7c3862903e7b0e66302"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9753b87f31e7106ecf77b2f01a99b237" id="r_ga9753b87f31e7106ecf77b2f01a99b237"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9753b87f31e7106ecf77b2f01a99b237">DAC_CR_TSEL2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80a933188591c4fbcad260c256105277">DAC_CR_TSEL2_Pos</a>)</td></tr>
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<tr class="separator:ga9753b87f31e7106ecf77b2f01a99b237"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac79323a6c81bfa5c8239b23cd3db737a" id="r_gac79323a6c81bfa5c8239b23cd3db737a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac79323a6c81bfa5c8239b23cd3db737a">DAC_CR_TSEL2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80a933188591c4fbcad260c256105277">DAC_CR_TSEL2_Pos</a>)</td></tr>
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<tr class="separator:gac79323a6c81bfa5c8239b23cd3db737a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ad3da8a9c5fe9566d8ffe38916caaff" id="r_ga9ad3da8a9c5fe9566d8ffe38916caaff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ad3da8a9c5fe9566d8ffe38916caaff">DAC_CR_TSEL2_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80a933188591c4fbcad260c256105277">DAC_CR_TSEL2_Pos</a>)</td></tr>
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<tr class="separator:ga9ad3da8a9c5fe9566d8ffe38916caaff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7795c9de47dc6747045ee7e2e6fb8ba9" id="r_ga7795c9de47dc6747045ee7e2e6fb8ba9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7795c9de47dc6747045ee7e2e6fb8ba9">DAC_CR_WAVE2_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga7795c9de47dc6747045ee7e2e6fb8ba9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0420dd10713d50b05ab6c477ab502893" id="r_ga0420dd10713d50b05ab6c477ab502893"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0420dd10713d50b05ab6c477ab502893">DAC_CR_WAVE2_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7795c9de47dc6747045ee7e2e6fb8ba9">DAC_CR_WAVE2_Pos</a>)</td></tr>
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<tr class="separator:ga0420dd10713d50b05ab6c477ab502893"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf24e48cf288db4a4643057dd09e3a7b" id="r_gacf24e48cf288db4a4643057dd09e3a7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf24e48cf288db4a4643057dd09e3a7b">DAC_CR_WAVE2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0420dd10713d50b05ab6c477ab502893">DAC_CR_WAVE2_Msk</a></td></tr>
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<tr class="separator:gacf24e48cf288db4a4643057dd09e3a7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55d97d8bcbfdd72d5aeb9e9fbc0d592d" id="r_ga55d97d8bcbfdd72d5aeb9e9fbc0d592d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55d97d8bcbfdd72d5aeb9e9fbc0d592d">DAC_CR_WAVE2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7795c9de47dc6747045ee7e2e6fb8ba9">DAC_CR_WAVE2_Pos</a>)</td></tr>
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<tr class="separator:ga55d97d8bcbfdd72d5aeb9e9fbc0d592d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4798bf254010b442b4ac4288c2f1b65f" id="r_ga4798bf254010b442b4ac4288c2f1b65f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4798bf254010b442b4ac4288c2f1b65f">DAC_CR_WAVE2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7795c9de47dc6747045ee7e2e6fb8ba9">DAC_CR_WAVE2_Pos</a>)</td></tr>
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<tr class="separator:ga4798bf254010b442b4ac4288c2f1b65f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cccefc999aeab6622afaf662c7c8c50" id="r_ga7cccefc999aeab6622afaf662c7c8c50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cccefc999aeab6622afaf662c7c8c50">DAC_CR_MAMP2_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga7cccefc999aeab6622afaf662c7c8c50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace1bce6cad4004ab884396a1d73a1725" id="r_gace1bce6cad4004ab884396a1d73a1725"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace1bce6cad4004ab884396a1d73a1725">DAC_CR_MAMP2_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cccefc999aeab6622afaf662c7c8c50">DAC_CR_MAMP2_Pos</a>)</td></tr>
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<tr class="memitem:ga7cf03fe2359cb0f11c33f793c2e92bdd" id="r_ga7cf03fe2359cb0f11c33f793c2e92bdd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cf03fe2359cb0f11c33f793c2e92bdd">DAC_CR_MAMP2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gace1bce6cad4004ab884396a1d73a1725">DAC_CR_MAMP2_Msk</a></td></tr>
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<tr class="separator:ga7cf03fe2359cb0f11c33f793c2e92bdd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8d952192721dbdcea8d707d43096454" id="r_gae8d952192721dbdcea8d707d43096454"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8d952192721dbdcea8d707d43096454">DAC_CR_MAMP2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cccefc999aeab6622afaf662c7c8c50">DAC_CR_MAMP2_Pos</a>)</td></tr>
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<tr class="memitem:ga860032e8196838cd36a655c1749139d6" id="r_ga860032e8196838cd36a655c1749139d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga860032e8196838cd36a655c1749139d6">DAC_CR_MAMP2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cccefc999aeab6622afaf662c7c8c50">DAC_CR_MAMP2_Pos</a>)</td></tr>
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<tr class="memitem:ga2147ffa3282e9ff22475e5d6040f269e" id="r_ga2147ffa3282e9ff22475e5d6040f269e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2147ffa3282e9ff22475e5d6040f269e">DAC_CR_MAMP2_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cccefc999aeab6622afaf662c7c8c50">DAC_CR_MAMP2_Pos</a>)</td></tr>
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<tr class="memitem:gaa0fe77a2029873111cbe723a5cba9c57" id="r_gaa0fe77a2029873111cbe723a5cba9c57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0fe77a2029873111cbe723a5cba9c57">DAC_CR_MAMP2_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cccefc999aeab6622afaf662c7c8c50">DAC_CR_MAMP2_Pos</a>)</td></tr>
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<tr class="separator:gaa0fe77a2029873111cbe723a5cba9c57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga264e3d328584463c5164a7cca726cabb" id="r_ga264e3d328584463c5164a7cca726cabb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga264e3d328584463c5164a7cca726cabb">DAC_CR_DMAEN2_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga264e3d328584463c5164a7cca726cabb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa85027944d9eddc64c42ee2ed98611f4" id="r_gaa85027944d9eddc64c42ee2ed98611f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa85027944d9eddc64c42ee2ed98611f4">DAC_CR_DMAEN2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga264e3d328584463c5164a7cca726cabb">DAC_CR_DMAEN2_Pos</a>)</td></tr>
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<tr class="separator:gaa85027944d9eddc64c42ee2ed98611f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f905c2ac89f976df6c4beffdde58b53" id="r_ga6f905c2ac89f976df6c4beffdde58b53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f905c2ac89f976df6c4beffdde58b53">DAC_CR_DMAEN2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa85027944d9eddc64c42ee2ed98611f4">DAC_CR_DMAEN2_Msk</a></td></tr>
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<tr class="separator:ga6f905c2ac89f976df6c4beffdde58b53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6bf1e308092f2ef72387eb0fc5a8412" id="r_gad6bf1e308092f2ef72387eb0fc5a8412"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6bf1e308092f2ef72387eb0fc5a8412">DAC_CR_DMAUDRIE2_Pos</a>   (29U)</td></tr>
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<tr class="separator:gad6bf1e308092f2ef72387eb0fc5a8412"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga239ab4f68c1a74d0e9423bbf6c98c5da" id="r_ga239ab4f68c1a74d0e9423bbf6c98c5da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga239ab4f68c1a74d0e9423bbf6c98c5da">DAC_CR_DMAUDRIE2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad6bf1e308092f2ef72387eb0fc5a8412">DAC_CR_DMAUDRIE2_Pos</a>)</td></tr>
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<tr class="separator:ga239ab4f68c1a74d0e9423bbf6c98c5da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga803e3bae78ced744b93aa76615303e15" id="r_ga803e3bae78ced744b93aa76615303e15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga803e3bae78ced744b93aa76615303e15">DAC_CR_DMAUDRIE2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga239ab4f68c1a74d0e9423bbf6c98c5da">DAC_CR_DMAUDRIE2_Msk</a></td></tr>
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<tr class="separator:ga803e3bae78ced744b93aa76615303e15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32d8b5dafe7a5f4963e5f12656e48ee1" id="r_ga32d8b5dafe7a5f4963e5f12656e48ee1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32d8b5dafe7a5f4963e5f12656e48ee1">DAC_SWTRIGR_SWTRIG1_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga32d8b5dafe7a5f4963e5f12656e48ee1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga819696c72cca7dd861aa7a3d9081e425" id="r_ga819696c72cca7dd861aa7a3d9081e425"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga819696c72cca7dd861aa7a3d9081e425">DAC_SWTRIGR_SWTRIG1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga32d8b5dafe7a5f4963e5f12656e48ee1">DAC_SWTRIGR_SWTRIG1_Pos</a>)</td></tr>
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<tr class="separator:ga819696c72cca7dd861aa7a3d9081e425"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga970ef02dffaceb35ff1dd7aceb67acdd" id="r_ga970ef02dffaceb35ff1dd7aceb67acdd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga970ef02dffaceb35ff1dd7aceb67acdd">DAC_SWTRIGR_SWTRIG1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga819696c72cca7dd861aa7a3d9081e425">DAC_SWTRIGR_SWTRIG1_Msk</a></td></tr>
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<tr class="separator:ga970ef02dffaceb35ff1dd7aceb67acdd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb85dac71ddd76ce877fad49a47634b5" id="r_gadb85dac71ddd76ce877fad49a47634b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb85dac71ddd76ce877fad49a47634b5">DAC_SWTRIGR_SWTRIG2_Pos</a>   (1U)</td></tr>
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<tr class="separator:gadb85dac71ddd76ce877fad49a47634b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga107859f1c6bd2dc30bf632941121bb05" id="r_ga107859f1c6bd2dc30bf632941121bb05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga107859f1c6bd2dc30bf632941121bb05">DAC_SWTRIGR_SWTRIG2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb85dac71ddd76ce877fad49a47634b5">DAC_SWTRIGR_SWTRIG2_Pos</a>)</td></tr>
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<tr class="separator:ga107859f1c6bd2dc30bf632941121bb05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0e53585b505d21f5c457476bd5a18f8" id="r_gaf0e53585b505d21f5c457476bd5a18f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0e53585b505d21f5c457476bd5a18f8">DAC_SWTRIGR_SWTRIG2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga107859f1c6bd2dc30bf632941121bb05">DAC_SWTRIGR_SWTRIG2_Msk</a></td></tr>
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<tr class="separator:gaf0e53585b505d21f5c457476bd5a18f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3250ec13530e0e363f0ab92c149774f" id="r_gab3250ec13530e0e363f0ab92c149774f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3250ec13530e0e363f0ab92c149774f">DAC_DHR12R1_DACC1DHR_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab3250ec13530e0e363f0ab92c149774f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga203fee3fe672b7468231c91ce8a55e4b" id="r_ga203fee3fe672b7468231c91ce8a55e4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga203fee3fe672b7468231c91ce8a55e4b">DAC_DHR12R1_DACC1DHR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3250ec13530e0e363f0ab92c149774f">DAC_DHR12R1_DACC1DHR_Pos</a>)</td></tr>
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<tr class="separator:ga203fee3fe672b7468231c91ce8a55e4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5295b5cb7f5d71ed2e8a310deb00013d" id="r_ga5295b5cb7f5d71ed2e8a310deb00013d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5295b5cb7f5d71ed2e8a310deb00013d">DAC_DHR12R1_DACC1DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga203fee3fe672b7468231c91ce8a55e4b">DAC_DHR12R1_DACC1DHR_Msk</a></td></tr>
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<tr class="separator:ga5295b5cb7f5d71ed2e8a310deb00013d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1dcdc73fc338b3548cddcf84fb0c951" id="r_gac1dcdc73fc338b3548cddcf84fb0c951"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1dcdc73fc338b3548cddcf84fb0c951">DAC_DHR12L1_DACC1DHR_Pos</a>   (4U)</td></tr>
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<tr class="separator:gac1dcdc73fc338b3548cddcf84fb0c951"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga065dab2c8181ab7e3ff6cb43a86400c4" id="r_ga065dab2c8181ab7e3ff6cb43a86400c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga065dab2c8181ab7e3ff6cb43a86400c4">DAC_DHR12L1_DACC1DHR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac1dcdc73fc338b3548cddcf84fb0c951">DAC_DHR12L1_DACC1DHR_Pos</a>)</td></tr>
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<tr class="separator:ga065dab2c8181ab7e3ff6cb43a86400c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d34667f8f4b753689c8c936c28471c5" id="r_ga0d34667f8f4b753689c8c936c28471c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d34667f8f4b753689c8c936c28471c5">DAC_DHR12L1_DACC1DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga065dab2c8181ab7e3ff6cb43a86400c4">DAC_DHR12L1_DACC1DHR_Msk</a></td></tr>
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<tr class="separator:ga0d34667f8f4b753689c8c936c28471c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b874c02d121c755a1d4523f2e39134e" id="r_ga6b874c02d121c755a1d4523f2e39134e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b874c02d121c755a1d4523f2e39134e">DAC_DHR8R1_DACC1DHR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga6b874c02d121c755a1d4523f2e39134e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacde0062be02bb512e2bdc5ee84b4f17f" id="r_gacde0062be02bb512e2bdc5ee84b4f17f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacde0062be02bb512e2bdc5ee84b4f17f">DAC_DHR8R1_DACC1DHR_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b874c02d121c755a1d4523f2e39134e">DAC_DHR8R1_DACC1DHR_Pos</a>)</td></tr>
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<tr class="separator:gacde0062be02bb512e2bdc5ee84b4f17f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1fc9f022fe4a08f67c51646177b26cb" id="r_gae1fc9f022fe4a08f67c51646177b26cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1fc9f022fe4a08f67c51646177b26cb">DAC_DHR8R1_DACC1DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacde0062be02bb512e2bdc5ee84b4f17f">DAC_DHR8R1_DACC1DHR_Msk</a></td></tr>
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<tr class="separator:gae1fc9f022fe4a08f67c51646177b26cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd13752ec5bc912023c608426e47908e" id="r_gadd13752ec5bc912023c608426e47908e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd13752ec5bc912023c608426e47908e">DAC_DHR12R2_DACC2DHR_Pos</a>   (0U)</td></tr>
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<tr class="separator:gadd13752ec5bc912023c608426e47908e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3cf4f31c9248dc74d00b813c1f2b2e0" id="r_gad3cf4f31c9248dc74d00b813c1f2b2e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3cf4f31c9248dc74d00b813c1f2b2e0">DAC_DHR12R2_DACC2DHR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadd13752ec5bc912023c608426e47908e">DAC_DHR12R2_DACC2DHR_Pos</a>)</td></tr>
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<tr class="separator:gad3cf4f31c9248dc74d00b813c1f2b2e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7506e369b37d55826042b540b10e44c7" id="r_ga7506e369b37d55826042b540b10e44c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7506e369b37d55826042b540b10e44c7">DAC_DHR12R2_DACC2DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad3cf4f31c9248dc74d00b813c1f2b2e0">DAC_DHR12R2_DACC2DHR_Msk</a></td></tr>
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<tr class="separator:ga7506e369b37d55826042b540b10e44c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fe559f6278c4abd3b5db6277e82925b" id="r_ga8fe559f6278c4abd3b5db6277e82925b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fe559f6278c4abd3b5db6277e82925b">DAC_DHR12L2_DACC2DHR_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga8fe559f6278c4abd3b5db6277e82925b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40a67db51971c777b7ee75c4da5bc8e8" id="r_ga40a67db51971c777b7ee75c4da5bc8e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40a67db51971c777b7ee75c4da5bc8e8">DAC_DHR12L2_DACC2DHR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fe559f6278c4abd3b5db6277e82925b">DAC_DHR12L2_DACC2DHR_Pos</a>)</td></tr>
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<tr class="separator:ga40a67db51971c777b7ee75c4da5bc8e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f66bd794202221e1a55547673b7abab" id="r_ga0f66bd794202221e1a55547673b7abab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f66bd794202221e1a55547673b7abab">DAC_DHR12L2_DACC2DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga40a67db51971c777b7ee75c4da5bc8e8">DAC_DHR12L2_DACC2DHR_Msk</a></td></tr>
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<tr class="separator:ga0f66bd794202221e1a55547673b7abab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a8082de99f7eef453237a409763718b" id="r_ga4a8082de99f7eef453237a409763718b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a8082de99f7eef453237a409763718b">DAC_DHR8R2_DACC2DHR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4a8082de99f7eef453237a409763718b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf3e9e86edc54f83e02d2a0d3f486658" id="r_gabf3e9e86edc54f83e02d2a0d3f486658"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf3e9e86edc54f83e02d2a0d3f486658">DAC_DHR8R2_DACC2DHR_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a8082de99f7eef453237a409763718b">DAC_DHR8R2_DACC2DHR_Pos</a>)</td></tr>
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<tr class="separator:gabf3e9e86edc54f83e02d2a0d3f486658"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7da94dc053e6637efb9ccb57b7ae481c" id="r_ga7da94dc053e6637efb9ccb57b7ae481c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7da94dc053e6637efb9ccb57b7ae481c">DAC_DHR8R2_DACC2DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabf3e9e86edc54f83e02d2a0d3f486658">DAC_DHR8R2_DACC2DHR_Msk</a></td></tr>
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<tr class="separator:ga7da94dc053e6637efb9ccb57b7ae481c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d1a7b56cdc34694e1aa032be202e79d" id="r_ga6d1a7b56cdc34694e1aa032be202e79d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d1a7b56cdc34694e1aa032be202e79d">DAC_DHR12RD_DACC1DHR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga6d1a7b56cdc34694e1aa032be202e79d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cf050c1d3f7c651b461b463c8ae659e" id="r_ga7cf050c1d3f7c651b461b463c8ae659e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cf050c1d3f7c651b461b463c8ae659e">DAC_DHR12RD_DACC1DHR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d1a7b56cdc34694e1aa032be202e79d">DAC_DHR12RD_DACC1DHR_Pos</a>)</td></tr>
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<tr class="separator:ga7cf050c1d3f7c651b461b463c8ae659e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca45719f3d365c9495bdcf6364ae59f8" id="r_gaca45719f3d365c9495bdcf6364ae59f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca45719f3d365c9495bdcf6364ae59f8">DAC_DHR12RD_DACC1DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cf050c1d3f7c651b461b463c8ae659e">DAC_DHR12RD_DACC1DHR_Msk</a></td></tr>
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<tr class="separator:gaca45719f3d365c9495bdcf6364ae59f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae522220c8b02ab4bcf82f122a45997d3" id="r_gae522220c8b02ab4bcf82f122a45997d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae522220c8b02ab4bcf82f122a45997d3">DAC_DHR12RD_DACC2DHR_Pos</a>   (16U)</td></tr>
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<tr class="separator:gae522220c8b02ab4bcf82f122a45997d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0ae28d5d855fd8fe53de3d5fc2ee437" id="r_gaa0ae28d5d855fd8fe53de3d5fc2ee437"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0ae28d5d855fd8fe53de3d5fc2ee437">DAC_DHR12RD_DACC2DHR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae522220c8b02ab4bcf82f122a45997d3">DAC_DHR12RD_DACC2DHR_Pos</a>)</td></tr>
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<tr class="separator:gaa0ae28d5d855fd8fe53de3d5fc2ee437"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3edd68db1697af93027e05f6b764c540" id="r_ga3edd68db1697af93027e05f6b764c540"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3edd68db1697af93027e05f6b764c540">DAC_DHR12RD_DACC2DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0ae28d5d855fd8fe53de3d5fc2ee437">DAC_DHR12RD_DACC2DHR_Msk</a></td></tr>
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<tr class="separator:ga3edd68db1697af93027e05f6b764c540"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa367fe7ed3f9b2d5114dcc46ccab7468" id="r_gaa367fe7ed3f9b2d5114dcc46ccab7468"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa367fe7ed3f9b2d5114dcc46ccab7468">DAC_DHR12LD_DACC1DHR_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaa367fe7ed3f9b2d5114dcc46ccab7468"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabbf9e7bb591e9c954f648ce36f5f9f90" id="r_gabbf9e7bb591e9c954f648ce36f5f9f90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbf9e7bb591e9c954f648ce36f5f9f90">DAC_DHR12LD_DACC1DHR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa367fe7ed3f9b2d5114dcc46ccab7468">DAC_DHR12LD_DACC1DHR_Pos</a>)</td></tr>
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<tr class="separator:gabbf9e7bb591e9c954f648ce36f5f9f90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga203db656bfef6fedee17b99fb77b1bdd" id="r_ga203db656bfef6fedee17b99fb77b1bdd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga203db656bfef6fedee17b99fb77b1bdd">DAC_DHR12LD_DACC1DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabbf9e7bb591e9c954f648ce36f5f9f90">DAC_DHR12LD_DACC1DHR_Msk</a></td></tr>
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<tr class="separator:ga203db656bfef6fedee17b99fb77b1bdd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade1db665f01f9d179045057d0e857da0" id="r_gade1db665f01f9d179045057d0e857da0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade1db665f01f9d179045057d0e857da0">DAC_DHR12LD_DACC2DHR_Pos</a>   (20U)</td></tr>
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<tr class="separator:gade1db665f01f9d179045057d0e857da0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c6a0375af61a42378851c55436f0e23" id="r_ga0c6a0375af61a42378851c55436f0e23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c6a0375af61a42378851c55436f0e23">DAC_DHR12LD_DACC2DHR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade1db665f01f9d179045057d0e857da0">DAC_DHR12LD_DACC2DHR_Pos</a>)</td></tr>
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<tr class="separator:ga0c6a0375af61a42378851c55436f0e23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8421d613b182aab8d6c58592bcda6c17" id="r_ga8421d613b182aab8d6c58592bcda6c17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8421d613b182aab8d6c58592bcda6c17">DAC_DHR12LD_DACC2DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c6a0375af61a42378851c55436f0e23">DAC_DHR12LD_DACC2DHR_Msk</a></td></tr>
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<tr class="separator:ga8421d613b182aab8d6c58592bcda6c17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac004fb7fdc93225fb835b27e39229a57" id="r_gac004fb7fdc93225fb835b27e39229a57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac004fb7fdc93225fb835b27e39229a57">DAC_DHR8RD_DACC1DHR_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac004fb7fdc93225fb835b27e39229a57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1b85c14a79ef230c7771336ab683678" id="r_gae1b85c14a79ef230c7771336ab683678"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1b85c14a79ef230c7771336ab683678">DAC_DHR8RD_DACC1DHR_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac004fb7fdc93225fb835b27e39229a57">DAC_DHR8RD_DACC1DHR_Pos</a>)</td></tr>
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<tr class="separator:gae1b85c14a79ef230c7771336ab683678"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9aee01ad181fa5b541864ed62907d70d" id="r_ga9aee01ad181fa5b541864ed62907d70d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9aee01ad181fa5b541864ed62907d70d">DAC_DHR8RD_DACC1DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae1b85c14a79ef230c7771336ab683678">DAC_DHR8RD_DACC1DHR_Msk</a></td></tr>
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<tr class="separator:ga9aee01ad181fa5b541864ed62907d70d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf849d0278349997f891d987def91224" id="r_gabf849d0278349997f891d987def91224"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf849d0278349997f891d987def91224">DAC_DHR8RD_DACC2DHR_Pos</a>   (8U)</td></tr>
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<tr class="separator:gabf849d0278349997f891d987def91224"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3520456f0013e51d3d2c3694d86488b6" id="r_ga3520456f0013e51d3d2c3694d86488b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3520456f0013e51d3d2c3694d86488b6">DAC_DHR8RD_DACC2DHR_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf849d0278349997f891d987def91224">DAC_DHR8RD_DACC2DHR_Pos</a>)</td></tr>
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<tr class="separator:ga3520456f0013e51d3d2c3694d86488b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae31631eaac76ebecb059918c351ef3c9" id="r_gae31631eaac76ebecb059918c351ef3c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae31631eaac76ebecb059918c351ef3c9">DAC_DHR8RD_DACC2DHR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3520456f0013e51d3d2c3694d86488b6">DAC_DHR8RD_DACC2DHR_Msk</a></td></tr>
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<tr class="separator:gae31631eaac76ebecb059918c351ef3c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacef98a0af264fa6b23a187e74d7c82d" id="r_gaacef98a0af264fa6b23a187e74d7c82d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacef98a0af264fa6b23a187e74d7c82d">DAC_DOR1_DACC1DOR_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaacef98a0af264fa6b23a187e74d7c82d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae11b4b811ab6ba4e981ee60318f7d1a4" id="r_gae11b4b811ab6ba4e981ee60318f7d1a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae11b4b811ab6ba4e981ee60318f7d1a4">DAC_DOR1_DACC1DOR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaacef98a0af264fa6b23a187e74d7c82d">DAC_DOR1_DACC1DOR_Pos</a>)</td></tr>
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<tr class="separator:gae11b4b811ab6ba4e981ee60318f7d1a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b4192938e039dc25a7df8fcc5f3932a" id="r_ga5b4192938e039dc25a7df8fcc5f3932a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b4192938e039dc25a7df8fcc5f3932a">DAC_DOR1_DACC1DOR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae11b4b811ab6ba4e981ee60318f7d1a4">DAC_DOR1_DACC1DOR_Msk</a></td></tr>
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<tr class="separator:ga5b4192938e039dc25a7df8fcc5f3932a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17aa70d42a524b2dd911326fa65630f1" id="r_ga17aa70d42a524b2dd911326fa65630f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17aa70d42a524b2dd911326fa65630f1">DAC_DOR2_DACC2DOR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga17aa70d42a524b2dd911326fa65630f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a6d4d4b3b48221d195a3acb51ad6fbe" id="r_ga4a6d4d4b3b48221d195a3acb51ad6fbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a6d4d4b3b48221d195a3acb51ad6fbe">DAC_DOR2_DACC2DOR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17aa70d42a524b2dd911326fa65630f1">DAC_DOR2_DACC2DOR_Pos</a>)</td></tr>
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<tr class="separator:ga4a6d4d4b3b48221d195a3acb51ad6fbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacaaa39c1e82279918918b072fd56db04" id="r_gacaaa39c1e82279918918b072fd56db04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacaaa39c1e82279918918b072fd56db04">DAC_DOR2_DACC2DOR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a6d4d4b3b48221d195a3acb51ad6fbe">DAC_DOR2_DACC2DOR_Msk</a></td></tr>
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<tr class="separator:gacaaa39c1e82279918918b072fd56db04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadeeefee596334ca7c00e9dfa12cfdd83" id="r_gadeeefee596334ca7c00e9dfa12cfdd83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadeeefee596334ca7c00e9dfa12cfdd83">DAC_SR_DMAUDR1_Pos</a>   (13U)</td></tr>
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<tr class="separator:gadeeefee596334ca7c00e9dfa12cfdd83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75ded00bd7866ed6e38c52beb4854d64" id="r_ga75ded00bd7866ed6e38c52beb4854d64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75ded00bd7866ed6e38c52beb4854d64">DAC_SR_DMAUDR1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadeeefee596334ca7c00e9dfa12cfdd83">DAC_SR_DMAUDR1_Pos</a>)</td></tr>
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<tr class="separator:ga75ded00bd7866ed6e38c52beb4854d64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d2048d6b521fb0946dc8c4e577a49c0" id="r_ga7d2048d6b521fb0946dc8c4e577a49c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d2048d6b521fb0946dc8c4e577a49c0">DAC_SR_DMAUDR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga75ded00bd7866ed6e38c52beb4854d64">DAC_SR_DMAUDR1_Msk</a></td></tr>
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<tr class="separator:ga7d2048d6b521fb0946dc8c4e577a49c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa918fd0130e9edc2b4a21ff4ba17aa5e" id="r_gaa918fd0130e9edc2b4a21ff4ba17aa5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa918fd0130e9edc2b4a21ff4ba17aa5e">DAC_SR_DMAUDR2_Pos</a>   (29U)</td></tr>
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<tr class="separator:gaa918fd0130e9edc2b4a21ff4ba17aa5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccadc59668f44b530b866ebcce6f0c74" id="r_gaccadc59668f44b530b866ebcce6f0c74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccadc59668f44b530b866ebcce6f0c74">DAC_SR_DMAUDR2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa918fd0130e9edc2b4a21ff4ba17aa5e">DAC_SR_DMAUDR2_Pos</a>)</td></tr>
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<tr class="separator:gaccadc59668f44b530b866ebcce6f0c74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf16e48ab85d9261c5b599c56b14aea5d" id="r_gaf16e48ab85d9261c5b599c56b14aea5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf16e48ab85d9261c5b599c56b14aea5d">DAC_SR_DMAUDR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaccadc59668f44b530b866ebcce6f0c74">DAC_SR_DMAUDR2_Msk</a></td></tr>
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<tr class="separator:gaf16e48ab85d9261c5b599c56b14aea5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa3a454c9236fd257a8bfb17071637dc" id="r_gafa3a454c9236fd257a8bfb17071637dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa3a454c9236fd257a8bfb17071637dc">DCMI_CR_CAPTURE_Pos</a>   (0U)</td></tr>
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<tr class="separator:gafa3a454c9236fd257a8bfb17071637dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15f2c325d001c3d3d5a1939106584fb3" id="r_ga15f2c325d001c3d3d5a1939106584fb3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15f2c325d001c3d3d5a1939106584fb3">DCMI_CR_CAPTURE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafa3a454c9236fd257a8bfb17071637dc">DCMI_CR_CAPTURE_Pos</a>)</td></tr>
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<tr class="separator:ga15f2c325d001c3d3d5a1939106584fb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f8b54f16f7e17b3da807b6dae1d649e" id="r_ga7f8b54f16f7e17b3da807b6dae1d649e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f8b54f16f7e17b3da807b6dae1d649e">DCMI_CR_CAPTURE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga15f2c325d001c3d3d5a1939106584fb3">DCMI_CR_CAPTURE_Msk</a></td></tr>
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<tr class="memitem:gade41604d334508afeb14b82e21f421be" id="r_gade41604d334508afeb14b82e21f421be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade41604d334508afeb14b82e21f421be">DCMI_CR_CM_Pos</a>   (1U)</td></tr>
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<tr class="separator:gade41604d334508afeb14b82e21f421be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9213d50a3270e1e2df73b73a97300b0" id="r_gaa9213d50a3270e1e2df73b73a97300b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9213d50a3270e1e2df73b73a97300b0">DCMI_CR_CM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade41604d334508afeb14b82e21f421be">DCMI_CR_CM_Pos</a>)</td></tr>
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<tr class="separator:gaa9213d50a3270e1e2df73b73a97300b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47bacab13c750dc0ecc9aaf935d1f435" id="r_ga47bacab13c750dc0ecc9aaf935d1f435"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47bacab13c750dc0ecc9aaf935d1f435">DCMI_CR_CM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9213d50a3270e1e2df73b73a97300b0">DCMI_CR_CM_Msk</a></td></tr>
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<tr class="separator:ga47bacab13c750dc0ecc9aaf935d1f435"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cd43899ca78a773ae0132b07b795b73" id="r_ga6cd43899ca78a773ae0132b07b795b73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cd43899ca78a773ae0132b07b795b73">DCMI_CR_CROP_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga6cd43899ca78a773ae0132b07b795b73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45cccbefdbcefa8f1b4effbd30e4fd57" id="r_ga45cccbefdbcefa8f1b4effbd30e4fd57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45cccbefdbcefa8f1b4effbd30e4fd57">DCMI_CR_CROP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cd43899ca78a773ae0132b07b795b73">DCMI_CR_CROP_Pos</a>)</td></tr>
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<tr class="separator:ga45cccbefdbcefa8f1b4effbd30e4fd57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bb929e7d3b4ea62e80ba66c7bc5c216" id="r_ga5bb929e7d3b4ea62e80ba66c7bc5c216"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bb929e7d3b4ea62e80ba66c7bc5c216">DCMI_CR_CROP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45cccbefdbcefa8f1b4effbd30e4fd57">DCMI_CR_CROP_Msk</a></td></tr>
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<tr class="separator:ga5bb929e7d3b4ea62e80ba66c7bc5c216"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab93600cf87f62ab21c0270966eb49853" id="r_gab93600cf87f62ab21c0270966eb49853"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab93600cf87f62ab21c0270966eb49853">DCMI_CR_JPEG_Pos</a>   (3U)</td></tr>
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<tr class="separator:gab93600cf87f62ab21c0270966eb49853"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef4bc80edc936ebf381a4c2149a9aa9c" id="r_gaef4bc80edc936ebf381a4c2149a9aa9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef4bc80edc936ebf381a4c2149a9aa9c">DCMI_CR_JPEG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab93600cf87f62ab21c0270966eb49853">DCMI_CR_JPEG_Pos</a>)</td></tr>
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<tr class="separator:gaef4bc80edc936ebf381a4c2149a9aa9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd10a1f9c5a588f468e550bb56051b03" id="r_gafd10a1f9c5a588f468e550bb56051b03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd10a1f9c5a588f468e550bb56051b03">DCMI_CR_JPEG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaef4bc80edc936ebf381a4c2149a9aa9c">DCMI_CR_JPEG_Msk</a></td></tr>
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<tr class="separator:gafd10a1f9c5a588f468e550bb56051b03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02f02e4a058fb7854a3e9c5f79cb6fb3" id="r_ga02f02e4a058fb7854a3e9c5f79cb6fb3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02f02e4a058fb7854a3e9c5f79cb6fb3">DCMI_CR_ESS_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga02f02e4a058fb7854a3e9c5f79cb6fb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd4f4d68488cc78decac4e7fe8838655" id="r_gafd4f4d68488cc78decac4e7fe8838655"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd4f4d68488cc78decac4e7fe8838655">DCMI_CR_ESS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02f02e4a058fb7854a3e9c5f79cb6fb3">DCMI_CR_ESS_Pos</a>)</td></tr>
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<tr class="separator:gafd4f4d68488cc78decac4e7fe8838655"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46851e2b6011a84ecdfc5218a855ad78" id="r_ga46851e2b6011a84ecdfc5218a855ad78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46851e2b6011a84ecdfc5218a855ad78">DCMI_CR_ESS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafd4f4d68488cc78decac4e7fe8838655">DCMI_CR_ESS_Msk</a></td></tr>
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<tr class="separator:ga46851e2b6011a84ecdfc5218a855ad78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3929ea65cd626b5f7d472af5d21f4c1b" id="r_ga3929ea65cd626b5f7d472af5d21f4c1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3929ea65cd626b5f7d472af5d21f4c1b">DCMI_CR_PCKPOL_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga3929ea65cd626b5f7d472af5d21f4c1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09ec8d81a49c61ae9fd02cc5de658f8c" id="r_ga09ec8d81a49c61ae9fd02cc5de658f8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09ec8d81a49c61ae9fd02cc5de658f8c">DCMI_CR_PCKPOL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3929ea65cd626b5f7d472af5d21f4c1b">DCMI_CR_PCKPOL_Pos</a>)</td></tr>
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<tr class="separator:ga09ec8d81a49c61ae9fd02cc5de658f8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00769f93cbcc2693c8fd42f0e8aa31ad" id="r_ga00769f93cbcc2693c8fd42f0e8aa31ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00769f93cbcc2693c8fd42f0e8aa31ad">DCMI_CR_PCKPOL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga09ec8d81a49c61ae9fd02cc5de658f8c">DCMI_CR_PCKPOL_Msk</a></td></tr>
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<tr class="separator:ga00769f93cbcc2693c8fd42f0e8aa31ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fd28eb0687c6a1704733a53c08dd797" id="r_ga0fd28eb0687c6a1704733a53c08dd797"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fd28eb0687c6a1704733a53c08dd797">DCMI_CR_HSPOL_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga0fd28eb0687c6a1704733a53c08dd797"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c027a03833f80bfddbf2205d092769e" id="r_ga0c027a03833f80bfddbf2205d092769e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c027a03833f80bfddbf2205d092769e">DCMI_CR_HSPOL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0fd28eb0687c6a1704733a53c08dd797">DCMI_CR_HSPOL_Pos</a>)</td></tr>
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<tr class="separator:ga0c027a03833f80bfddbf2205d092769e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2042d3da2719b7c9c6708e0566e46c5" id="r_gac2042d3da2719b7c9c6708e0566e46c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2042d3da2719b7c9c6708e0566e46c5">DCMI_CR_HSPOL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c027a03833f80bfddbf2205d092769e">DCMI_CR_HSPOL_Msk</a></td></tr>
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<tr class="separator:gac2042d3da2719b7c9c6708e0566e46c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c2656a42de18085bf84a731e82df2a7" id="r_ga2c2656a42de18085bf84a731e82df2a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c2656a42de18085bf84a731e82df2a7">DCMI_CR_VSPOL_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga2c2656a42de18085bf84a731e82df2a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3ac7d448956eaddaa8f416598662089" id="r_gab3ac7d448956eaddaa8f416598662089"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3ac7d448956eaddaa8f416598662089">DCMI_CR_VSPOL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c2656a42de18085bf84a731e82df2a7">DCMI_CR_VSPOL_Pos</a>)</td></tr>
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<tr class="separator:gab3ac7d448956eaddaa8f416598662089"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga497c7c4bf6fcc842ffc45eedc876ffdb" id="r_ga497c7c4bf6fcc842ffc45eedc876ffdb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga497c7c4bf6fcc842ffc45eedc876ffdb">DCMI_CR_VSPOL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab3ac7d448956eaddaa8f416598662089">DCMI_CR_VSPOL_Msk</a></td></tr>
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<tr class="separator:ga497c7c4bf6fcc842ffc45eedc876ffdb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13263970b396f75e00278ff7b78b313d" id="r_ga13263970b396f75e00278ff7b78b313d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13263970b396f75e00278ff7b78b313d">DCMI_CR_FCRC_0</a>   0x00000100U</td></tr>
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<tr class="separator:ga13263970b396f75e00278ff7b78b313d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1658bed43e7d0c3579151498104d5747" id="r_ga1658bed43e7d0c3579151498104d5747"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1658bed43e7d0c3579151498104d5747">DCMI_CR_FCRC_1</a>   0x00000200U</td></tr>
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<tr class="separator:ga1658bed43e7d0c3579151498104d5747"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9efa61252be662ff473d14156f09d32c" id="r_ga9efa61252be662ff473d14156f09d32c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9efa61252be662ff473d14156f09d32c">DCMI_CR_EDM_0</a>   0x00000400U</td></tr>
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<tr class="separator:ga9efa61252be662ff473d14156f09d32c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga884b51a3e5bf0d615944f46b1751a97c" id="r_ga884b51a3e5bf0d615944f46b1751a97c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga884b51a3e5bf0d615944f46b1751a97c">DCMI_CR_EDM_1</a>   0x00000800U</td></tr>
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<tr class="separator:ga884b51a3e5bf0d615944f46b1751a97c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57ff97d20c4f41748dda19d71f7da8d9" id="r_ga57ff97d20c4f41748dda19d71f7da8d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57ff97d20c4f41748dda19d71f7da8d9">DCMI_CR_CRE_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga57ff97d20c4f41748dda19d71f7da8d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3810273d9f0eeae0f5b8e3d3b5a14b3a" id="r_ga3810273d9f0eeae0f5b8e3d3b5a14b3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3810273d9f0eeae0f5b8e3d3b5a14b3a">DCMI_CR_CRE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57ff97d20c4f41748dda19d71f7da8d9">DCMI_CR_CRE_Pos</a>)</td></tr>
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<tr class="separator:ga3810273d9f0eeae0f5b8e3d3b5a14b3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79e4190a772dc07958573a110106db69" id="r_ga79e4190a772dc07958573a110106db69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79e4190a772dc07958573a110106db69">DCMI_CR_CRE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3810273d9f0eeae0f5b8e3d3b5a14b3a">DCMI_CR_CRE_Msk</a></td></tr>
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<tr class="separator:ga79e4190a772dc07958573a110106db69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef22c09278ab657cc3af24dcbff864be" id="r_gaef22c09278ab657cc3af24dcbff864be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef22c09278ab657cc3af24dcbff864be">DCMI_CR_ENABLE_Pos</a>   (14U)</td></tr>
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<tr class="separator:gaef22c09278ab657cc3af24dcbff864be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38f1b2217a7ae182f5cb6739fd28c0cc" id="r_ga38f1b2217a7ae182f5cb6739fd28c0cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38f1b2217a7ae182f5cb6739fd28c0cc">DCMI_CR_ENABLE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef22c09278ab657cc3af24dcbff864be">DCMI_CR_ENABLE_Pos</a>)</td></tr>
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<tr class="separator:ga38f1b2217a7ae182f5cb6739fd28c0cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1fa2461ca2f0629c2ddd77fea94bbd06" id="r_ga1fa2461ca2f0629c2ddd77fea94bbd06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fa2461ca2f0629c2ddd77fea94bbd06">DCMI_CR_ENABLE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38f1b2217a7ae182f5cb6739fd28c0cc">DCMI_CR_ENABLE_Msk</a></td></tr>
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<tr class="separator:ga1fa2461ca2f0629c2ddd77fea94bbd06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5e7fd85cd8977bbd867cacd10016b9a" id="r_gaa5e7fd85cd8977bbd867cacd10016b9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5e7fd85cd8977bbd867cacd10016b9a">DCMI_SR_HSYNC_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa5e7fd85cd8977bbd867cacd10016b9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52a8a170e5bc418b043e712c65852121" id="r_ga52a8a170e5bc418b043e712c65852121"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52a8a170e5bc418b043e712c65852121">DCMI_SR_HSYNC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5e7fd85cd8977bbd867cacd10016b9a">DCMI_SR_HSYNC_Pos</a>)</td></tr>
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<tr class="memitem:gafb10174e5a89c32d6413ecf77e6610a0" id="r_gafb10174e5a89c32d6413ecf77e6610a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb10174e5a89c32d6413ecf77e6610a0">DCMI_SR_HSYNC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga52a8a170e5bc418b043e712c65852121">DCMI_SR_HSYNC_Msk</a></td></tr>
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<tr class="separator:gafb10174e5a89c32d6413ecf77e6610a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8518f9299351064b5d42d297d3337e9a" id="r_ga8518f9299351064b5d42d297d3337e9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8518f9299351064b5d42d297d3337e9a">DCMI_SR_VSYNC_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga8518f9299351064b5d42d297d3337e9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae563614237e37f375f3a0cea5d01d272" id="r_gae563614237e37f375f3a0cea5d01d272"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae563614237e37f375f3a0cea5d01d272">DCMI_SR_VSYNC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8518f9299351064b5d42d297d3337e9a">DCMI_SR_VSYNC_Pos</a>)</td></tr>
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<tr class="separator:gae563614237e37f375f3a0cea5d01d272"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9608c2fdd5feb3c8c022545f8d7e6adf" id="r_ga9608c2fdd5feb3c8c022545f8d7e6adf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9608c2fdd5feb3c8c022545f8d7e6adf">DCMI_SR_VSYNC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae563614237e37f375f3a0cea5d01d272">DCMI_SR_VSYNC_Msk</a></td></tr>
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<tr class="separator:ga9608c2fdd5feb3c8c022545f8d7e6adf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4425f4dfb86dbb4249d27b92b90caafe" id="r_ga4425f4dfb86dbb4249d27b92b90caafe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4425f4dfb86dbb4249d27b92b90caafe">DCMI_SR_FNE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga4425f4dfb86dbb4249d27b92b90caafe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad19357d2286c9647ce0fce32c8b0578c" id="r_gad19357d2286c9647ce0fce32c8b0578c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad19357d2286c9647ce0fce32c8b0578c">DCMI_SR_FNE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4425f4dfb86dbb4249d27b92b90caafe">DCMI_SR_FNE_Pos</a>)</td></tr>
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<tr class="separator:gad19357d2286c9647ce0fce32c8b0578c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga990aaedf052bc3b9ebd115f06aa43ab2" id="r_ga990aaedf052bc3b9ebd115f06aa43ab2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga990aaedf052bc3b9ebd115f06aa43ab2">DCMI_SR_FNE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad19357d2286c9647ce0fce32c8b0578c">DCMI_SR_FNE_Msk</a></td></tr>
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<tr class="separator:ga990aaedf052bc3b9ebd115f06aa43ab2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dd9257e83488a0c5a4f22d1b687227e" id="r_ga4dd9257e83488a0c5a4f22d1b687227e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dd9257e83488a0c5a4f22d1b687227e">DCMI_RIS_FRAME_RIS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4dd9257e83488a0c5a4f22d1b687227e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28f7059f0838e9089197abd09dbb1773" id="r_ga28f7059f0838e9089197abd09dbb1773"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28f7059f0838e9089197abd09dbb1773">DCMI_RIS_FRAME_RIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4dd9257e83488a0c5a4f22d1b687227e">DCMI_RIS_FRAME_RIS_Pos</a>)</td></tr>
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<tr class="memitem:ga188d7dafa72efe56f8363ffee4b0662b" id="r_ga188d7dafa72efe56f8363ffee4b0662b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga188d7dafa72efe56f8363ffee4b0662b">DCMI_RIS_FRAME_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga28f7059f0838e9089197abd09dbb1773">DCMI_RIS_FRAME_RIS_Msk</a></td></tr>
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<tr class="separator:ga188d7dafa72efe56f8363ffee4b0662b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace86e6047cb5cae4000378626d291678" id="r_gace86e6047cb5cae4000378626d291678"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace86e6047cb5cae4000378626d291678">DCMI_RIS_OVR_RIS_Pos</a>   (1U)</td></tr>
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<tr class="separator:gace86e6047cb5cae4000378626d291678"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8bf3ee23039b601106d1d91e9acced53" id="r_ga8bf3ee23039b601106d1d91e9acced53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8bf3ee23039b601106d1d91e9acced53">DCMI_RIS_OVR_RIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gace86e6047cb5cae4000378626d291678">DCMI_RIS_OVR_RIS_Pos</a>)</td></tr>
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<tr class="separator:ga8bf3ee23039b601106d1d91e9acced53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaeb2e93438e3aa6b72a2f897c3ed86bc" id="r_gaaeb2e93438e3aa6b72a2f897c3ed86bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaeb2e93438e3aa6b72a2f897c3ed86bc">DCMI_RIS_OVR_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8bf3ee23039b601106d1d91e9acced53">DCMI_RIS_OVR_RIS_Msk</a></td></tr>
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<tr class="separator:gaaeb2e93438e3aa6b72a2f897c3ed86bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae917e074e286a7a44b7d192d540eb367" id="r_gae917e074e286a7a44b7d192d540eb367"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae917e074e286a7a44b7d192d540eb367">DCMI_RIS_ERR_RIS_Pos</a>   (2U)</td></tr>
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<tr class="separator:gae917e074e286a7a44b7d192d540eb367"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92f212d4ebfc932e28a9a190f96e1861" id="r_ga92f212d4ebfc932e28a9a190f96e1861"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92f212d4ebfc932e28a9a190f96e1861">DCMI_RIS_ERR_RIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae917e074e286a7a44b7d192d540eb367">DCMI_RIS_ERR_RIS_Pos</a>)</td></tr>
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<tr class="separator:ga92f212d4ebfc932e28a9a190f96e1861"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60312c64ac11224348e6817b16b38ace" id="r_ga60312c64ac11224348e6817b16b38ace"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60312c64ac11224348e6817b16b38ace">DCMI_RIS_ERR_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga92f212d4ebfc932e28a9a190f96e1861">DCMI_RIS_ERR_RIS_Msk</a></td></tr>
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<tr class="separator:ga60312c64ac11224348e6817b16b38ace"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b953f571921dbaecbf126b7768ce9e0" id="r_ga2b953f571921dbaecbf126b7768ce9e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b953f571921dbaecbf126b7768ce9e0">DCMI_RIS_VSYNC_RIS_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga2b953f571921dbaecbf126b7768ce9e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf2902c19b9063c83d8e269f83428a6d" id="r_gaaf2902c19b9063c83d8e269f83428a6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf2902c19b9063c83d8e269f83428a6d">DCMI_RIS_VSYNC_RIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b953f571921dbaecbf126b7768ce9e0">DCMI_RIS_VSYNC_RIS_Pos</a>)</td></tr>
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<tr class="separator:gaaf2902c19b9063c83d8e269f83428a6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57777e4dfeb6df63ffc1eee8e1fd51e9" id="r_ga57777e4dfeb6df63ffc1eee8e1fd51e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57777e4dfeb6df63ffc1eee8e1fd51e9">DCMI_RIS_VSYNC_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf2902c19b9063c83d8e269f83428a6d">DCMI_RIS_VSYNC_RIS_Msk</a></td></tr>
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<tr class="separator:ga57777e4dfeb6df63ffc1eee8e1fd51e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab6c35d6c01b791049b926e626703a043" id="r_gab6c35d6c01b791049b926e626703a043"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6c35d6c01b791049b926e626703a043">DCMI_RIS_LINE_RIS_Pos</a>   (4U)</td></tr>
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<tr class="separator:gab6c35d6c01b791049b926e626703a043"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga143c2c95deb861fb392953a15b99c174" id="r_ga143c2c95deb861fb392953a15b99c174"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga143c2c95deb861fb392953a15b99c174">DCMI_RIS_LINE_RIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab6c35d6c01b791049b926e626703a043">DCMI_RIS_LINE_RIS_Pos</a>)</td></tr>
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<tr class="memitem:ga7df083b857fd655d11a90a7a1ee94d66" id="r_ga7df083b857fd655d11a90a7a1ee94d66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7df083b857fd655d11a90a7a1ee94d66">DCMI_RIS_LINE_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga143c2c95deb861fb392953a15b99c174">DCMI_RIS_LINE_RIS_Msk</a></td></tr>
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<tr class="separator:ga7df083b857fd655d11a90a7a1ee94d66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99308f49b63dd49db671a2a26d0d07fa" id="r_ga99308f49b63dd49db671a2a26d0d07fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99308f49b63dd49db671a2a26d0d07fa">DCMI_RISR_FRAME_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga188d7dafa72efe56f8363ffee4b0662b">DCMI_RIS_FRAME_RIS</a></td></tr>
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<tr class="separator:ga99308f49b63dd49db671a2a26d0d07fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae893218ce7d16540e5af7c3afb03bc98" id="r_gae893218ce7d16540e5af7c3afb03bc98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae893218ce7d16540e5af7c3afb03bc98">DCMI_RISR_OVR_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaeb2e93438e3aa6b72a2f897c3ed86bc">DCMI_RIS_OVR_RIS</a></td></tr>
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<tr class="separator:gae893218ce7d16540e5af7c3afb03bc98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf03ca1f0e5e1a7868c07c8237d7e33a3" id="r_gaf03ca1f0e5e1a7868c07c8237d7e33a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf03ca1f0e5e1a7868c07c8237d7e33a3">DCMI_RISR_ERR_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga60312c64ac11224348e6817b16b38ace">DCMI_RIS_ERR_RIS</a></td></tr>
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<tr class="separator:gaf03ca1f0e5e1a7868c07c8237d7e33a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08625c101d8419ca58cc7032f4a936ec" id="r_ga08625c101d8419ca58cc7032f4a936ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08625c101d8419ca58cc7032f4a936ec">DCMI_RISR_VSYNC_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57777e4dfeb6df63ffc1eee8e1fd51e9">DCMI_RIS_VSYNC_RIS</a></td></tr>
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<tr class="separator:ga08625c101d8419ca58cc7032f4a936ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf06b386a61d97e046a7f0546478b91b8" id="r_gaf06b386a61d97e046a7f0546478b91b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf06b386a61d97e046a7f0546478b91b8">DCMI_RISR_LINE_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7df083b857fd655d11a90a7a1ee94d66">DCMI_RIS_LINE_RIS</a></td></tr>
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<tr class="separator:gaf06b386a61d97e046a7f0546478b91b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga510c3f423fdddf8a41b6b69d55b6c66d" id="r_ga510c3f423fdddf8a41b6b69d55b6c66d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga510c3f423fdddf8a41b6b69d55b6c66d">DCMI_RISR_OVF_RIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaeb2e93438e3aa6b72a2f897c3ed86bc">DCMI_RIS_OVR_RIS</a></td></tr>
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<tr class="separator:ga510c3f423fdddf8a41b6b69d55b6c66d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8bd2b1d1f6d0b24c0871bd617f0fcca8" id="r_ga8bd2b1d1f6d0b24c0871bd617f0fcca8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8bd2b1d1f6d0b24c0871bd617f0fcca8">DCMI_IER_FRAME_IE_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8bd2b1d1f6d0b24c0871bd617f0fcca8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f620e3f5ac8a334cda95e761e7e410b" id="r_ga3f620e3f5ac8a334cda95e761e7e410b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f620e3f5ac8a334cda95e761e7e410b">DCMI_IER_FRAME_IE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8bd2b1d1f6d0b24c0871bd617f0fcca8">DCMI_IER_FRAME_IE_Pos</a>)</td></tr>
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<tr class="separator:ga3f620e3f5ac8a334cda95e761e7e410b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78d30c219bf7b5ebe0f8ee74cbdae61d" id="r_ga78d30c219bf7b5ebe0f8ee74cbdae61d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78d30c219bf7b5ebe0f8ee74cbdae61d">DCMI_IER_FRAME_IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f620e3f5ac8a334cda95e761e7e410b">DCMI_IER_FRAME_IE_Msk</a></td></tr>
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<tr class="separator:ga78d30c219bf7b5ebe0f8ee74cbdae61d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e618e53a00804740c96a6a87fe4eb5d" id="r_ga4e618e53a00804740c96a6a87fe4eb5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e618e53a00804740c96a6a87fe4eb5d">DCMI_IER_OVR_IE_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga0b10a920924f2a6b2fbc3a29e1dfab62" id="r_ga0b10a920924f2a6b2fbc3a29e1dfab62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b10a920924f2a6b2fbc3a29e1dfab62">DCMI_IER_OVR_IE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e618e53a00804740c96a6a87fe4eb5d">DCMI_IER_OVR_IE_Pos</a>)</td></tr>
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<tr class="memitem:ga3526fa00f78f05a35551294374134d81" id="r_ga3526fa00f78f05a35551294374134d81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3526fa00f78f05a35551294374134d81">DCMI_IER_OVR_IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b10a920924f2a6b2fbc3a29e1dfab62">DCMI_IER_OVR_IE_Msk</a></td></tr>
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<tr class="memitem:ga71ba0a7a3bdbddd9117d28170b69f043" id="r_ga71ba0a7a3bdbddd9117d28170b69f043"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71ba0a7a3bdbddd9117d28170b69f043">DCMI_IER_ERR_IE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga71ba0a7a3bdbddd9117d28170b69f043"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3fdbc46256c696cc52602dbb3c275090" id="r_ga3fdbc46256c696cc52602dbb3c275090"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3fdbc46256c696cc52602dbb3c275090">DCMI_IER_ERR_IE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71ba0a7a3bdbddd9117d28170b69f043">DCMI_IER_ERR_IE_Pos</a>)</td></tr>
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<tr class="separator:ga3fdbc46256c696cc52602dbb3c275090"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc9d64d6edc4e8ff9452db0065c12831" id="r_gacc9d64d6edc4e8ff9452db0065c12831"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc9d64d6edc4e8ff9452db0065c12831">DCMI_IER_ERR_IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3fdbc46256c696cc52602dbb3c275090">DCMI_IER_ERR_IE_Msk</a></td></tr>
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<tr class="memitem:ga8e02ca273e7458bbdb7e204666748b19" id="r_ga8e02ca273e7458bbdb7e204666748b19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e02ca273e7458bbdb7e204666748b19">DCMI_IER_VSYNC_IE_Pos</a>   (3U)</td></tr>
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<tr class="memitem:gae8df43e41d5ffd5f74e8ab0e892a5eb9" id="r_gae8df43e41d5ffd5f74e8ab0e892a5eb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8df43e41d5ffd5f74e8ab0e892a5eb9">DCMI_IER_VSYNC_IE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e02ca273e7458bbdb7e204666748b19">DCMI_IER_VSYNC_IE_Pos</a>)</td></tr>
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<tr class="memitem:gad2f335c69d18e49ffb5314e85ac1f4fc" id="r_gad2f335c69d18e49ffb5314e85ac1f4fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2f335c69d18e49ffb5314e85ac1f4fc">DCMI_IER_VSYNC_IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae8df43e41d5ffd5f74e8ab0e892a5eb9">DCMI_IER_VSYNC_IE_Msk</a></td></tr>
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<tr class="separator:gad2f335c69d18e49ffb5314e85ac1f4fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8afd81592f141ee1f028a7e65f4418d1" id="r_ga8afd81592f141ee1f028a7e65f4418d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8afd81592f141ee1f028a7e65f4418d1">DCMI_IER_LINE_IE_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga8afd81592f141ee1f028a7e65f4418d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61b024ef7c45524af9a733769c453ee4" id="r_ga61b024ef7c45524af9a733769c453ee4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61b024ef7c45524af9a733769c453ee4">DCMI_IER_LINE_IE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8afd81592f141ee1f028a7e65f4418d1">DCMI_IER_LINE_IE_Pos</a>)</td></tr>
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<tr class="memitem:ga4a06c700c5e779551834862a2d14612e" id="r_ga4a06c700c5e779551834862a2d14612e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a06c700c5e779551834862a2d14612e">DCMI_IER_LINE_IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga61b024ef7c45524af9a733769c453ee4">DCMI_IER_LINE_IE_Msk</a></td></tr>
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<tr class="separator:ga4a06c700c5e779551834862a2d14612e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f313352a86f6b09726e63f89e161187" id="r_ga4f313352a86f6b09726e63f89e161187"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f313352a86f6b09726e63f89e161187">DCMI_IER_OVF_IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3526fa00f78f05a35551294374134d81">DCMI_IER_OVR_IE</a></td></tr>
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<tr class="memitem:gaf50f1645c609ecf4c86539214559b13a" id="r_gaf50f1645c609ecf4c86539214559b13a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf50f1645c609ecf4c86539214559b13a">DCMI_MIS_FRAME_MIS_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf50f1645c609ecf4c86539214559b13a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bccb72ae32d9e1af338767329728ecf" id="r_ga1bccb72ae32d9e1af338767329728ecf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bccb72ae32d9e1af338767329728ecf">DCMI_MIS_FRAME_MIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf50f1645c609ecf4c86539214559b13a">DCMI_MIS_FRAME_MIS_Pos</a>)</td></tr>
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<tr class="memitem:ga941155c6f476426df918e806a0f32e4e" id="r_ga941155c6f476426df918e806a0f32e4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga941155c6f476426df918e806a0f32e4e">DCMI_MIS_FRAME_MIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1bccb72ae32d9e1af338767329728ecf">DCMI_MIS_FRAME_MIS_Msk</a></td></tr>
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<tr class="separator:ga941155c6f476426df918e806a0f32e4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac62263a4027c8db50c73af02ce4c61f1" id="r_gac62263a4027c8db50c73af02ce4c61f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac62263a4027c8db50c73af02ce4c61f1">DCMI_MIS_OVR_MIS_Pos</a>   (1U)</td></tr>
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<tr class="separator:gac62263a4027c8db50c73af02ce4c61f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56960bc01ad1ed046aab7db0fc2d0a5e" id="r_ga56960bc01ad1ed046aab7db0fc2d0a5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56960bc01ad1ed046aab7db0fc2d0a5e">DCMI_MIS_OVR_MIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac62263a4027c8db50c73af02ce4c61f1">DCMI_MIS_OVR_MIS_Pos</a>)</td></tr>
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<tr class="memitem:ga2bf479b833da567f2ee940d570a54517" id="r_ga2bf479b833da567f2ee940d570a54517"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf479b833da567f2ee940d570a54517">DCMI_MIS_OVR_MIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga56960bc01ad1ed046aab7db0fc2d0a5e">DCMI_MIS_OVR_MIS_Msk</a></td></tr>
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<tr class="separator:ga2bf479b833da567f2ee940d570a54517"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga794cffd7108134514729d69dc29e3adc" id="r_ga794cffd7108134514729d69dc29e3adc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga794cffd7108134514729d69dc29e3adc">DCMI_MIS_ERR_MIS_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga794cffd7108134514729d69dc29e3adc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae49e11fcd9d6e779c0f03fb206ba50dd" id="r_gae49e11fcd9d6e779c0f03fb206ba50dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae49e11fcd9d6e779c0f03fb206ba50dd">DCMI_MIS_ERR_MIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga794cffd7108134514729d69dc29e3adc">DCMI_MIS_ERR_MIS_Pos</a>)</td></tr>
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<tr class="separator:gae49e11fcd9d6e779c0f03fb206ba50dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46deae49ce6acb93a2c9827b7de125ed" id="r_ga46deae49ce6acb93a2c9827b7de125ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46deae49ce6acb93a2c9827b7de125ed">DCMI_MIS_ERR_MIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae49e11fcd9d6e779c0f03fb206ba50dd">DCMI_MIS_ERR_MIS_Msk</a></td></tr>
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<tr class="separator:ga46deae49ce6acb93a2c9827b7de125ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6e09a3ece4317ea262cd9f5e0e5a2a7" id="r_gad6e09a3ece4317ea262cd9f5e0e5a2a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6e09a3ece4317ea262cd9f5e0e5a2a7">DCMI_MIS_VSYNC_MIS_Pos</a>   (3U)</td></tr>
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<tr class="separator:gad6e09a3ece4317ea262cd9f5e0e5a2a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4ff5663b22aac5464b75cb3514f262e" id="r_gaf4ff5663b22aac5464b75cb3514f262e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4ff5663b22aac5464b75cb3514f262e">DCMI_MIS_VSYNC_MIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad6e09a3ece4317ea262cd9f5e0e5a2a7">DCMI_MIS_VSYNC_MIS_Pos</a>)</td></tr>
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<tr class="separator:gaf4ff5663b22aac5464b75cb3514f262e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8559771f71aa7c77eec58339c628f26a" id="r_ga8559771f71aa7c77eec58339c628f26a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8559771f71aa7c77eec58339c628f26a">DCMI_MIS_VSYNC_MIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4ff5663b22aac5464b75cb3514f262e">DCMI_MIS_VSYNC_MIS_Msk</a></td></tr>
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<tr class="memitem:ga88e5fa975bd3ac9ba03ef27f9647c916" id="r_ga88e5fa975bd3ac9ba03ef27f9647c916"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88e5fa975bd3ac9ba03ef27f9647c916">DCMI_MIS_LINE_MIS_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga88e5fa975bd3ac9ba03ef27f9647c916"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06dbeaf099a326aa55f1ea65dd821af4" id="r_ga06dbeaf099a326aa55f1ea65dd821af4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06dbeaf099a326aa55f1ea65dd821af4">DCMI_MIS_LINE_MIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga88e5fa975bd3ac9ba03ef27f9647c916">DCMI_MIS_LINE_MIS_Pos</a>)</td></tr>
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<tr class="separator:ga06dbeaf099a326aa55f1ea65dd821af4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga340adf786e70c8b9ebc2deef9aa30ced" id="r_ga340adf786e70c8b9ebc2deef9aa30ced"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga340adf786e70c8b9ebc2deef9aa30ced">DCMI_MIS_LINE_MIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06dbeaf099a326aa55f1ea65dd821af4">DCMI_MIS_LINE_MIS_Msk</a></td></tr>
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<tr class="separator:ga340adf786e70c8b9ebc2deef9aa30ced"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73b7d7359389df61668089920ed5b28e" id="r_ga73b7d7359389df61668089920ed5b28e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73b7d7359389df61668089920ed5b28e">DCMI_MISR_FRAME_MIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga941155c6f476426df918e806a0f32e4e">DCMI_MIS_FRAME_MIS</a></td></tr>
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<tr class="separator:ga73b7d7359389df61668089920ed5b28e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacaced5931c5790bdf6fc9ede4591496" id="r_gaacaced5931c5790bdf6fc9ede4591496"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacaced5931c5790bdf6fc9ede4591496">DCMI_MISR_OVF_MIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf479b833da567f2ee940d570a54517">DCMI_MIS_OVR_MIS</a></td></tr>
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<tr class="separator:gaacaced5931c5790bdf6fc9ede4591496"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga117dd3b10b1c7a03016fce867a6a8281" id="r_ga117dd3b10b1c7a03016fce867a6a8281"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga117dd3b10b1c7a03016fce867a6a8281">DCMI_MISR_ERR_MIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga46deae49ce6acb93a2c9827b7de125ed">DCMI_MIS_ERR_MIS</a></td></tr>
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<tr class="separator:ga117dd3b10b1c7a03016fce867a6a8281"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a02749de4576d3631cf35dbb4e4bf5c" id="r_ga1a02749de4576d3631cf35dbb4e4bf5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a02749de4576d3631cf35dbb4e4bf5c">DCMI_MISR_VSYNC_MIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8559771f71aa7c77eec58339c628f26a">DCMI_MIS_VSYNC_MIS</a></td></tr>
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<tr class="memitem:ga77aad6389ea95913c34b2ba3a14cfdca" id="r_ga77aad6389ea95913c34b2ba3a14cfdca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77aad6389ea95913c34b2ba3a14cfdca">DCMI_MISR_LINE_MIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga340adf786e70c8b9ebc2deef9aa30ced">DCMI_MIS_LINE_MIS</a></td></tr>
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<tr class="separator:ga77aad6389ea95913c34b2ba3a14cfdca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa522718b7f9eeec5df1dc941c4caa092" id="r_gaa522718b7f9eeec5df1dc941c4caa092"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa522718b7f9eeec5df1dc941c4caa092">DCMI_ICR_FRAME_ISC_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa522718b7f9eeec5df1dc941c4caa092"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bc8bd2a6b5de3b723915ab6fbfc9603" id="r_ga6bc8bd2a6b5de3b723915ab6fbfc9603"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bc8bd2a6b5de3b723915ab6fbfc9603">DCMI_ICR_FRAME_ISC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa522718b7f9eeec5df1dc941c4caa092">DCMI_ICR_FRAME_ISC_Pos</a>)</td></tr>
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<tr class="separator:ga6bc8bd2a6b5de3b723915ab6fbfc9603"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ce2decf4166be0a5376ea2810403030" id="r_ga7ce2decf4166be0a5376ea2810403030"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ce2decf4166be0a5376ea2810403030">DCMI_ICR_FRAME_ISC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6bc8bd2a6b5de3b723915ab6fbfc9603">DCMI_ICR_FRAME_ISC_Msk</a></td></tr>
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<tr class="separator:ga7ce2decf4166be0a5376ea2810403030"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03be33d65b8a9c6c9c2ed69ba286f387" id="r_ga03be33d65b8a9c6c9c2ed69ba286f387"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03be33d65b8a9c6c9c2ed69ba286f387">DCMI_ICR_OVR_ISC_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga03be33d65b8a9c6c9c2ed69ba286f387"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63ef3349d85e073e5a212e523ad1ac50" id="r_ga63ef3349d85e073e5a212e523ad1ac50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63ef3349d85e073e5a212e523ad1ac50">DCMI_ICR_OVR_ISC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga03be33d65b8a9c6c9c2ed69ba286f387">DCMI_ICR_OVR_ISC_Pos</a>)</td></tr>
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<tr class="separator:ga63ef3349d85e073e5a212e523ad1ac50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9d9f8083bf587a6e6d6f5470fb29a88" id="r_gaf9d9f8083bf587a6e6d6f5470fb29a88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9d9f8083bf587a6e6d6f5470fb29a88">DCMI_ICR_OVR_ISC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63ef3349d85e073e5a212e523ad1ac50">DCMI_ICR_OVR_ISC_Msk</a></td></tr>
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<tr class="separator:gaf9d9f8083bf587a6e6d6f5470fb29a88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef56d07e9430cebe51d917c96a46bd4a" id="r_gaef56d07e9430cebe51d917c96a46bd4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef56d07e9430cebe51d917c96a46bd4a">DCMI_ICR_ERR_ISC_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaef56d07e9430cebe51d917c96a46bd4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab819f4eb028d0bce638a7fc5aac68e1e" id="r_gab819f4eb028d0bce638a7fc5aac68e1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab819f4eb028d0bce638a7fc5aac68e1e">DCMI_ICR_ERR_ISC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef56d07e9430cebe51d917c96a46bd4a">DCMI_ICR_ERR_ISC_Pos</a>)</td></tr>
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<tr class="separator:gab819f4eb028d0bce638a7fc5aac68e1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8da69cdd9d4f4c280279fa05fdf235bc" id="r_ga8da69cdd9d4f4c280279fa05fdf235bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8da69cdd9d4f4c280279fa05fdf235bc">DCMI_ICR_ERR_ISC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab819f4eb028d0bce638a7fc5aac68e1e">DCMI_ICR_ERR_ISC_Msk</a></td></tr>
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<tr class="separator:ga8da69cdd9d4f4c280279fa05fdf235bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0087c275317c3692ea9ba74b5792f2a" id="r_gad0087c275317c3692ea9ba74b5792f2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0087c275317c3692ea9ba74b5792f2a">DCMI_ICR_VSYNC_ISC_Pos</a>   (3U)</td></tr>
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<tr class="separator:gad0087c275317c3692ea9ba74b5792f2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f7f889d6c3a2e1f6300618333b54b78" id="r_ga5f7f889d6c3a2e1f6300618333b54b78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f7f889d6c3a2e1f6300618333b54b78">DCMI_ICR_VSYNC_ISC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad0087c275317c3692ea9ba74b5792f2a">DCMI_ICR_VSYNC_ISC_Pos</a>)</td></tr>
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<tr class="separator:ga5f7f889d6c3a2e1f6300618333b54b78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedd101bdda4f13c30d7af5a85156a047" id="r_gaedd101bdda4f13c30d7af5a85156a047"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedd101bdda4f13c30d7af5a85156a047">DCMI_ICR_VSYNC_ISC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f7f889d6c3a2e1f6300618333b54b78">DCMI_ICR_VSYNC_ISC_Msk</a></td></tr>
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<tr class="separator:gaedd101bdda4f13c30d7af5a85156a047"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga166cd5d629e51a08b20b7fd3ceb8739a" id="r_ga166cd5d629e51a08b20b7fd3ceb8739a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga166cd5d629e51a08b20b7fd3ceb8739a">DCMI_ICR_LINE_ISC_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga166cd5d629e51a08b20b7fd3ceb8739a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdca5913b4eae2aeb02469e77434d557" id="r_gafdca5913b4eae2aeb02469e77434d557"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdca5913b4eae2aeb02469e77434d557">DCMI_ICR_LINE_ISC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga166cd5d629e51a08b20b7fd3ceb8739a">DCMI_ICR_LINE_ISC_Pos</a>)</td></tr>
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<tr class="separator:gafdca5913b4eae2aeb02469e77434d557"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae64182a042ceb8275c54819458b1ca9c" id="r_gae64182a042ceb8275c54819458b1ca9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae64182a042ceb8275c54819458b1ca9c">DCMI_ICR_LINE_ISC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafdca5913b4eae2aeb02469e77434d557">DCMI_ICR_LINE_ISC_Msk</a></td></tr>
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<tr class="separator:gae64182a042ceb8275c54819458b1ca9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0318fb46a8594834640d08a9ae06f79e" id="r_ga0318fb46a8594834640d08a9ae06f79e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0318fb46a8594834640d08a9ae06f79e">DCMI_ICR_OVF_ISC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9d9f8083bf587a6e6d6f5470fb29a88">DCMI_ICR_OVR_ISC</a></td></tr>
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<tr class="separator:ga0318fb46a8594834640d08a9ae06f79e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga606ebaec78811eb133a2adef912d16ee" id="r_ga606ebaec78811eb133a2adef912d16ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga606ebaec78811eb133a2adef912d16ee">DCMI_ESCR_FSC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga606ebaec78811eb133a2adef912d16ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ce58bb8ea8ca57dc51016be5eadb2d6" id="r_ga3ce58bb8ea8ca57dc51016be5eadb2d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ce58bb8ea8ca57dc51016be5eadb2d6">DCMI_ESCR_FSC_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga606ebaec78811eb133a2adef912d16ee">DCMI_ESCR_FSC_Pos</a>)</td></tr>
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<tr class="separator:ga3ce58bb8ea8ca57dc51016be5eadb2d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga822e9340b78048f18504488c6af07b17" id="r_ga822e9340b78048f18504488c6af07b17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga822e9340b78048f18504488c6af07b17">DCMI_ESCR_FSC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ce58bb8ea8ca57dc51016be5eadb2d6">DCMI_ESCR_FSC_Msk</a></td></tr>
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<tr class="separator:ga822e9340b78048f18504488c6af07b17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2a19d08646392458bfc5b1db2fcd401" id="r_gaa2a19d08646392458bfc5b1db2fcd401"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a19d08646392458bfc5b1db2fcd401">DCMI_ESCR_LSC_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaa2a19d08646392458bfc5b1db2fcd401"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70700ed96c539f193ff3dde57c41e414" id="r_ga70700ed96c539f193ff3dde57c41e414"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70700ed96c539f193ff3dde57c41e414">DCMI_ESCR_LSC_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a19d08646392458bfc5b1db2fcd401">DCMI_ESCR_LSC_Pos</a>)</td></tr>
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<tr class="separator:ga70700ed96c539f193ff3dde57c41e414"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f673b3dfe4d73c36ec941780cc91ce5" id="r_ga2f673b3dfe4d73c36ec941780cc91ce5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f673b3dfe4d73c36ec941780cc91ce5">DCMI_ESCR_LSC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga70700ed96c539f193ff3dde57c41e414">DCMI_ESCR_LSC_Msk</a></td></tr>
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<tr class="separator:ga2f673b3dfe4d73c36ec941780cc91ce5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ae8266875df6979d97b6f2ef0bf9dfd" id="r_ga7ae8266875df6979d97b6f2ef0bf9dfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ae8266875df6979d97b6f2ef0bf9dfd">DCMI_ESCR_LEC_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga7ae8266875df6979d97b6f2ef0bf9dfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab48737db683e9eb6c654fb009eccd7be" id="r_gab48737db683e9eb6c654fb009eccd7be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab48737db683e9eb6c654fb009eccd7be">DCMI_ESCR_LEC_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ae8266875df6979d97b6f2ef0bf9dfd">DCMI_ESCR_LEC_Pos</a>)</td></tr>
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<tr class="separator:gab48737db683e9eb6c654fb009eccd7be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga174d7f3b7ae442fa4fa8a95bc551d7fe" id="r_ga174d7f3b7ae442fa4fa8a95bc551d7fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga174d7f3b7ae442fa4fa8a95bc551d7fe">DCMI_ESCR_LEC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab48737db683e9eb6c654fb009eccd7be">DCMI_ESCR_LEC_Msk</a></td></tr>
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<tr class="separator:ga174d7f3b7ae442fa4fa8a95bc551d7fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8fa0ea70437313587a37aa718f1b2be" id="r_gac8fa0ea70437313587a37aa718f1b2be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8fa0ea70437313587a37aa718f1b2be">DCMI_ESCR_FEC_Pos</a>   (24U)</td></tr>
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<tr class="separator:gac8fa0ea70437313587a37aa718f1b2be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79ae393fc1fb2182bdf482cc4a1f5ff3" id="r_ga79ae393fc1fb2182bdf482cc4a1f5ff3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79ae393fc1fb2182bdf482cc4a1f5ff3">DCMI_ESCR_FEC_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8fa0ea70437313587a37aa718f1b2be">DCMI_ESCR_FEC_Pos</a>)</td></tr>
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<tr class="separator:ga79ae393fc1fb2182bdf482cc4a1f5ff3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab398e0b4ccde3ef98da25a420ad0d47d" id="r_gab398e0b4ccde3ef98da25a420ad0d47d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab398e0b4ccde3ef98da25a420ad0d47d">DCMI_ESCR_FEC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga79ae393fc1fb2182bdf482cc4a1f5ff3">DCMI_ESCR_FEC_Msk</a></td></tr>
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<tr class="separator:gab398e0b4ccde3ef98da25a420ad0d47d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8ab290d57eea4b8ee06ab5d5be8260c" id="r_gab8ab290d57eea4b8ee06ab5d5be8260c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8ab290d57eea4b8ee06ab5d5be8260c">DCMI_ESUR_FSU_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab8ab290d57eea4b8ee06ab5d5be8260c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga036205fd064f7ac796af221a5c01d719" id="r_ga036205fd064f7ac796af221a5c01d719"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga036205fd064f7ac796af221a5c01d719">DCMI_ESUR_FSU_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8ab290d57eea4b8ee06ab5d5be8260c">DCMI_ESUR_FSU_Pos</a>)</td></tr>
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<tr class="separator:ga036205fd064f7ac796af221a5c01d719"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07da26e3445ad620bf9f79853f521985" id="r_ga07da26e3445ad620bf9f79853f521985"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07da26e3445ad620bf9f79853f521985">DCMI_ESUR_FSU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga036205fd064f7ac796af221a5c01d719">DCMI_ESUR_FSU_Msk</a></td></tr>
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<tr class="memitem:gad05dbef1970d3d226f390de22b5f9e36" id="r_gad05dbef1970d3d226f390de22b5f9e36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad05dbef1970d3d226f390de22b5f9e36">DCMI_ESUR_LSU_Pos</a>   (8U)</td></tr>
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<tr class="separator:gad05dbef1970d3d226f390de22b5f9e36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28f623ee4d63d33aa7ffba98e4eb56d2" id="r_ga28f623ee4d63d33aa7ffba98e4eb56d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28f623ee4d63d33aa7ffba98e4eb56d2">DCMI_ESUR_LSU_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad05dbef1970d3d226f390de22b5f9e36">DCMI_ESUR_LSU_Pos</a>)</td></tr>
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<tr class="separator:ga28f623ee4d63d33aa7ffba98e4eb56d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef06107788d6ef1164cca2eec17ccd82" id="r_gaef06107788d6ef1164cca2eec17ccd82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef06107788d6ef1164cca2eec17ccd82">DCMI_ESUR_LSU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga28f623ee4d63d33aa7ffba98e4eb56d2">DCMI_ESUR_LSU_Msk</a></td></tr>
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<tr class="separator:gaef06107788d6ef1164cca2eec17ccd82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67c976e3d9e4b572622087768cd82438" id="r_ga67c976e3d9e4b572622087768cd82438"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67c976e3d9e4b572622087768cd82438">DCMI_ESUR_LEU_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga67c976e3d9e4b572622087768cd82438"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa57fa1027141af3c9cbca28d364bfff6" id="r_gaa57fa1027141af3c9cbca28d364bfff6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa57fa1027141af3c9cbca28d364bfff6">DCMI_ESUR_LEU_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67c976e3d9e4b572622087768cd82438">DCMI_ESUR_LEU_Pos</a>)</td></tr>
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<tr class="separator:gaa57fa1027141af3c9cbca28d364bfff6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65e5d6c1fa10262d9deb97e557fd294c" id="r_ga65e5d6c1fa10262d9deb97e557fd294c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65e5d6c1fa10262d9deb97e557fd294c">DCMI_ESUR_LEU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa57fa1027141af3c9cbca28d364bfff6">DCMI_ESUR_LEU_Msk</a></td></tr>
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<tr class="separator:ga65e5d6c1fa10262d9deb97e557fd294c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc1a3b6739ae97c70421d9e43fc190c7" id="r_gadc1a3b6739ae97c70421d9e43fc190c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc1a3b6739ae97c70421d9e43fc190c7">DCMI_ESUR_FEU_Pos</a>   (24U)</td></tr>
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<tr class="separator:gadc1a3b6739ae97c70421d9e43fc190c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9324fdd6bc3877df9bc3bdc2adecb6c" id="r_gad9324fdd6bc3877df9bc3bdc2adecb6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9324fdd6bc3877df9bc3bdc2adecb6c">DCMI_ESUR_FEU_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadc1a3b6739ae97c70421d9e43fc190c7">DCMI_ESUR_FEU_Pos</a>)</td></tr>
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<tr class="separator:gad9324fdd6bc3877df9bc3bdc2adecb6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71824df64b1b6626e66e5a83d4663a6e" id="r_ga71824df64b1b6626e66e5a83d4663a6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71824df64b1b6626e66e5a83d4663a6e">DCMI_ESUR_FEU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad9324fdd6bc3877df9bc3bdc2adecb6c">DCMI_ESUR_FEU_Msk</a></td></tr>
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<tr class="separator:ga71824df64b1b6626e66e5a83d4663a6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9a493eb26260002c069a0a548cf3fd2" id="r_gad9a493eb26260002c069a0a548cf3fd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9a493eb26260002c069a0a548cf3fd2">DCMI_CWSTRT_HOFFCNT_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad9a493eb26260002c069a0a548cf3fd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0fae460ad5a360aada91b734fa3ba57" id="r_gaf0fae460ad5a360aada91b734fa3ba57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0fae460ad5a360aada91b734fa3ba57">DCMI_CWSTRT_HOFFCNT_Msk</a>   (0x3FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9a493eb26260002c069a0a548cf3fd2">DCMI_CWSTRT_HOFFCNT_Pos</a>)</td></tr>
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<tr class="separator:gaf0fae460ad5a360aada91b734fa3ba57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae099a5f83a683df21addd2efd2d9400a" id="r_gae099a5f83a683df21addd2efd2d9400a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae099a5f83a683df21addd2efd2d9400a">DCMI_CWSTRT_HOFFCNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0fae460ad5a360aada91b734fa3ba57">DCMI_CWSTRT_HOFFCNT_Msk</a></td></tr>
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<tr class="separator:gae099a5f83a683df21addd2efd2d9400a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4f2d38ccf4538602e4b0fd463d978ae" id="r_gaa4f2d38ccf4538602e4b0fd463d978ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4f2d38ccf4538602e4b0fd463d978ae">DCMI_CWSTRT_VST_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaa4f2d38ccf4538602e4b0fd463d978ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1652ad176cc9fbdcec26e5ee24e1f90" id="r_gaa1652ad176cc9fbdcec26e5ee24e1f90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1652ad176cc9fbdcec26e5ee24e1f90">DCMI_CWSTRT_VST_Msk</a>   (0x1FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4f2d38ccf4538602e4b0fd463d978ae">DCMI_CWSTRT_VST_Pos</a>)</td></tr>
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<tr class="separator:gaa1652ad176cc9fbdcec26e5ee24e1f90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1f7a07e86f5331bd024197bf986f7fb" id="r_gaf1f7a07e86f5331bd024197bf986f7fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1f7a07e86f5331bd024197bf986f7fb">DCMI_CWSTRT_VST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1652ad176cc9fbdcec26e5ee24e1f90">DCMI_CWSTRT_VST_Msk</a></td></tr>
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<tr class="separator:gaf1f7a07e86f5331bd024197bf986f7fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga909bd8775d484d961f2e95e832ccda6d" id="r_ga909bd8775d484d961f2e95e832ccda6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga909bd8775d484d961f2e95e832ccda6d">DCMI_CWSIZE_CAPCNT_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga909bd8775d484d961f2e95e832ccda6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad530930a69892f9cd7ad4ff52a92b133" id="r_gad530930a69892f9cd7ad4ff52a92b133"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad530930a69892f9cd7ad4ff52a92b133">DCMI_CWSIZE_CAPCNT_Msk</a>   (0x3FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga909bd8775d484d961f2e95e832ccda6d">DCMI_CWSIZE_CAPCNT_Pos</a>)</td></tr>
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<tr class="separator:gad530930a69892f9cd7ad4ff52a92b133"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c31745cc8efc121ae47c30cc42b384f" id="r_ga6c31745cc8efc121ae47c30cc42b384f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c31745cc8efc121ae47c30cc42b384f">DCMI_CWSIZE_CAPCNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad530930a69892f9cd7ad4ff52a92b133">DCMI_CWSIZE_CAPCNT_Msk</a></td></tr>
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<tr class="separator:ga6c31745cc8efc121ae47c30cc42b384f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab47763252d37347f698b9f1d6b459448" id="r_gab47763252d37347f698b9f1d6b459448"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab47763252d37347f698b9f1d6b459448">DCMI_CWSIZE_VLINE_Pos</a>   (16U)</td></tr>
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<tr class="separator:gab47763252d37347f698b9f1d6b459448"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga628637bf9713da908eca5a53e0f42d4b" id="r_ga628637bf9713da908eca5a53e0f42d4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga628637bf9713da908eca5a53e0f42d4b">DCMI_CWSIZE_VLINE_Msk</a>   (0x3FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab47763252d37347f698b9f1d6b459448">DCMI_CWSIZE_VLINE_Pos</a>)</td></tr>
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<tr class="separator:ga628637bf9713da908eca5a53e0f42d4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11c87e423cc974fce1a8a50213e47af8" id="r_ga11c87e423cc974fce1a8a50213e47af8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11c87e423cc974fce1a8a50213e47af8">DCMI_CWSIZE_VLINE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga628637bf9713da908eca5a53e0f42d4b">DCMI_CWSIZE_VLINE_Msk</a></td></tr>
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<tr class="separator:ga11c87e423cc974fce1a8a50213e47af8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac71db8315705b6ed05cf43460426e159" id="r_gac71db8315705b6ed05cf43460426e159"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac71db8315705b6ed05cf43460426e159">DCMI_DR_BYTE0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga07c270f5e6d112768db06c11b2cc6e56" id="r_ga07c270f5e6d112768db06c11b2cc6e56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07c270f5e6d112768db06c11b2cc6e56">DCMI_DR_BYTE0_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac71db8315705b6ed05cf43460426e159">DCMI_DR_BYTE0_Pos</a>)</td></tr>
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<tr class="memitem:gac0910a5a593672f96d201adc561a04b9" id="r_gac0910a5a593672f96d201adc561a04b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0910a5a593672f96d201adc561a04b9">DCMI_DR_BYTE0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga07c270f5e6d112768db06c11b2cc6e56">DCMI_DR_BYTE0_Msk</a></td></tr>
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<tr class="separator:gac0910a5a593672f96d201adc561a04b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5763f364e81aa40dd960d40ba88fa6a" id="r_gad5763f364e81aa40dd960d40ba88fa6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5763f364e81aa40dd960d40ba88fa6a">DCMI_DR_BYTE1_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gab17364d3900caed76aecc643774c54bc" id="r_gab17364d3900caed76aecc643774c54bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab17364d3900caed76aecc643774c54bc">DCMI_DR_BYTE1_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad5763f364e81aa40dd960d40ba88fa6a">DCMI_DR_BYTE1_Pos</a>)</td></tr>
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<tr class="memitem:gab01aefc5cd095660ac49a2b7b9180c82" id="r_gab01aefc5cd095660ac49a2b7b9180c82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab01aefc5cd095660ac49a2b7b9180c82">DCMI_DR_BYTE1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab17364d3900caed76aecc643774c54bc">DCMI_DR_BYTE1_Msk</a></td></tr>
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<tr class="memitem:gafbc045a35af6103ab0f7fc88ff6ba02d" id="r_gafbc045a35af6103ab0f7fc88ff6ba02d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbc045a35af6103ab0f7fc88ff6ba02d">DCMI_DR_BYTE2_Pos</a>   (16U)</td></tr>
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<tr class="separator:gafbc045a35af6103ab0f7fc88ff6ba02d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ee34bf9dabcdca52c0cbf44f25d9c5a" id="r_ga8ee34bf9dabcdca52c0cbf44f25d9c5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ee34bf9dabcdca52c0cbf44f25d9c5a">DCMI_DR_BYTE2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafbc045a35af6103ab0f7fc88ff6ba02d">DCMI_DR_BYTE2_Pos</a>)</td></tr>
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<tr class="separator:ga8ee34bf9dabcdca52c0cbf44f25d9c5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1bfbeeca97efa76992487f3c22d6aff" id="r_gab1bfbeeca97efa76992487f3c22d6aff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1bfbeeca97efa76992487f3c22d6aff">DCMI_DR_BYTE2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ee34bf9dabcdca52c0cbf44f25d9c5a">DCMI_DR_BYTE2_Msk</a></td></tr>
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<tr class="memitem:ga2bc8e1dc5f89d3476b28267f4b84a8ce" id="r_ga2bc8e1dc5f89d3476b28267f4b84a8ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bc8e1dc5f89d3476b28267f4b84a8ce">DCMI_DR_BYTE3_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga2bc8e1dc5f89d3476b28267f4b84a8ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa294b6ac2643ebf5c1492257ad79f45d" id="r_gaa294b6ac2643ebf5c1492257ad79f45d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa294b6ac2643ebf5c1492257ad79f45d">DCMI_DR_BYTE3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2bc8e1dc5f89d3476b28267f4b84a8ce">DCMI_DR_BYTE3_Pos</a>)</td></tr>
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<tr class="memitem:gaaa63e80a5e9f30b03e3b01b0c597a5cf" id="r_gaaa63e80a5e9f30b03e3b01b0c597a5cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa63e80a5e9f30b03e3b01b0c597a5cf">DCMI_DR_BYTE3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa294b6ac2643ebf5c1492257ad79f45d">DCMI_DR_BYTE3_Msk</a></td></tr>
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<tr class="memitem:ga79fe8c72b18021aec9a18b68b9df324c" id="r_ga79fe8c72b18021aec9a18b68b9df324c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79fe8c72b18021aec9a18b68b9df324c">DMA_SxCR_CHSEL_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga79fe8c72b18021aec9a18b68b9df324c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27c7e607fbf7db7b5515bacbb9070346" id="r_ga27c7e607fbf7db7b5515bacbb9070346"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27c7e607fbf7db7b5515bacbb9070346">DMA_SxCR_CHSEL_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga79fe8c72b18021aec9a18b68b9df324c">DMA_SxCR_CHSEL_Pos</a>)</td></tr>
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<tr class="separator:ga27c7e607fbf7db7b5515bacbb9070346"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf353426d72702c7801416ba36d53dc6" id="r_gadf353426d72702c7801416ba36d53dc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf353426d72702c7801416ba36d53dc6">DMA_SxCR_CHSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga27c7e607fbf7db7b5515bacbb9070346">DMA_SxCR_CHSEL_Msk</a></td></tr>
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<tr class="separator:gadf353426d72702c7801416ba36d53dc6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17d34dad5c7bdb97fdcadaebfed80d90" id="r_ga17d34dad5c7bdb97fdcadaebfed80d90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17d34dad5c7bdb97fdcadaebfed80d90">DMA_SxCR_CHSEL_0</a>   0x02000000U</td></tr>
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<tr class="separator:ga17d34dad5c7bdb97fdcadaebfed80d90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa59d7ef4d7e0895f18ca4ef1210edae" id="r_gafa59d7ef4d7e0895f18ca4ef1210edae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa59d7ef4d7e0895f18ca4ef1210edae">DMA_SxCR_CHSEL_1</a>   0x04000000U</td></tr>
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<tr class="separator:gafa59d7ef4d7e0895f18ca4ef1210edae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae001e60d3fd84c18bb5e2f96b695af38" id="r_gae001e60d3fd84c18bb5e2f96b695af38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae001e60d3fd84c18bb5e2f96b695af38">DMA_SxCR_CHSEL_2</a>   0x08000000U</td></tr>
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<tr class="separator:gae001e60d3fd84c18bb5e2f96b695af38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9bf6407dc86ae23902425ed20d90421" id="r_gaf9bf6407dc86ae23902425ed20d90421"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9bf6407dc86ae23902425ed20d90421">DMA_SxCR_MBURST_Pos</a>   (23U)</td></tr>
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<tr class="memitem:gaa451942408f8a368a57eb9c45e43e7c8" id="r_gaa451942408f8a368a57eb9c45e43e7c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa451942408f8a368a57eb9c45e43e7c8">DMA_SxCR_MBURST_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9bf6407dc86ae23902425ed20d90421">DMA_SxCR_MBURST_Pos</a>)</td></tr>
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<tr class="separator:gaa451942408f8a368a57eb9c45e43e7c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c1174bff38faf5d87b71521bce8f84f" id="r_ga5c1174bff38faf5d87b71521bce8f84f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c1174bff38faf5d87b71521bce8f84f">DMA_SxCR_MBURST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa451942408f8a368a57eb9c45e43e7c8">DMA_SxCR_MBURST_Msk</a></td></tr>
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<tr class="separator:ga5c1174bff38faf5d87b71521bce8f84f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e3931a8f14ffe008b8717e1b3232fca" id="r_ga1e3931a8f14ffe008b8717e1b3232fca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e3931a8f14ffe008b8717e1b3232fca">DMA_SxCR_MBURST_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9bf6407dc86ae23902425ed20d90421">DMA_SxCR_MBURST_Pos</a>)</td></tr>
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<tr class="separator:ga1e3931a8f14ffe008b8717e1b3232fca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf28eac7212392083bbf1b3d475022b74" id="r_gaf28eac7212392083bbf1b3d475022b74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf28eac7212392083bbf1b3d475022b74">DMA_SxCR_MBURST_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9bf6407dc86ae23902425ed20d90421">DMA_SxCR_MBURST_Pos</a>)</td></tr>
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<tr class="separator:gaf28eac7212392083bbf1b3d475022b74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga596bbd1719434d9b94dc57641788484e" id="r_ga596bbd1719434d9b94dc57641788484e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga596bbd1719434d9b94dc57641788484e">DMA_SxCR_PBURST_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga596bbd1719434d9b94dc57641788484e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0522a557e1c258b7973e76da59cb7bbb" id="r_ga0522a557e1c258b7973e76da59cb7bbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0522a557e1c258b7973e76da59cb7bbb">DMA_SxCR_PBURST_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga596bbd1719434d9b94dc57641788484e">DMA_SxCR_PBURST_Pos</a>)</td></tr>
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<tr class="separator:ga0522a557e1c258b7973e76da59cb7bbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga502380abb155eb3b37a2ca9359e2da2e" id="r_ga502380abb155eb3b37a2ca9359e2da2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga502380abb155eb3b37a2ca9359e2da2e">DMA_SxCR_PBURST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0522a557e1c258b7973e76da59cb7bbb">DMA_SxCR_PBURST_Msk</a></td></tr>
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<tr class="separator:ga502380abb155eb3b37a2ca9359e2da2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf0eee1ad1788868a194f95107057a16" id="r_gadf0eee1ad1788868a194f95107057a16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf0eee1ad1788868a194f95107057a16">DMA_SxCR_PBURST_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga596bbd1719434d9b94dc57641788484e">DMA_SxCR_PBURST_Pos</a>)</td></tr>
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<tr class="separator:gadf0eee1ad1788868a194f95107057a16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga061207b2c654a0dd62e40187c9557eda" id="r_ga061207b2c654a0dd62e40187c9557eda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga061207b2c654a0dd62e40187c9557eda">DMA_SxCR_PBURST_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga596bbd1719434d9b94dc57641788484e">DMA_SxCR_PBURST_Pos</a>)</td></tr>
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<tr class="separator:ga061207b2c654a0dd62e40187c9557eda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ae631c89765d8c92dde7eece6b28c58" id="r_ga5ae631c89765d8c92dde7eece6b28c58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ae631c89765d8c92dde7eece6b28c58">DMA_SxCR_CT_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga5ae631c89765d8c92dde7eece6b28c58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3ef149321f19c6fdda5eea2d622b78e" id="r_gaa3ef149321f19c6fdda5eea2d622b78e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3ef149321f19c6fdda5eea2d622b78e">DMA_SxCR_CT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ae631c89765d8c92dde7eece6b28c58">DMA_SxCR_CT_Pos</a>)</td></tr>
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<tr class="separator:gaa3ef149321f19c6fdda5eea2d622b78e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd36c677ee53f56dc408cd549e64cf7d" id="r_gadd36c677ee53f56dc408cd549e64cf7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd36c677ee53f56dc408cd549e64cf7d">DMA_SxCR_CT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3ef149321f19c6fdda5eea2d622b78e">DMA_SxCR_CT_Msk</a></td></tr>
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<tr class="separator:gadd36c677ee53f56dc408cd549e64cf7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d74a7510babe49319a47e4fccaceba7" id="r_ga9d74a7510babe49319a47e4fccaceba7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d74a7510babe49319a47e4fccaceba7">DMA_SxCR_DBM_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga9d74a7510babe49319a47e4fccaceba7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga460b7d274a9e54d2ddabddc9832425b4" id="r_ga460b7d274a9e54d2ddabddc9832425b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga460b7d274a9e54d2ddabddc9832425b4">DMA_SxCR_DBM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d74a7510babe49319a47e4fccaceba7">DMA_SxCR_DBM_Pos</a>)</td></tr>
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<tr class="separator:ga460b7d274a9e54d2ddabddc9832425b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53a1cde736b2afc5a394a67849f0c497" id="r_ga53a1cde736b2afc5a394a67849f0c497"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53a1cde736b2afc5a394a67849f0c497">DMA_SxCR_DBM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga460b7d274a9e54d2ddabddc9832425b4">DMA_SxCR_DBM_Msk</a></td></tr>
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<tr class="separator:ga53a1cde736b2afc5a394a67849f0c497"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0df2c0e1e3fa3614d74ee91cefa8173" id="r_gaf0df2c0e1e3fa3614d74ee91cefa8173"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0df2c0e1e3fa3614d74ee91cefa8173">DMA_SxCR_PL_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaf0df2c0e1e3fa3614d74ee91cefa8173"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3dc66d05a0b6c646926e155f584c2164" id="r_ga3dc66d05a0b6c646926e155f584c2164"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3dc66d05a0b6c646926e155f584c2164">DMA_SxCR_PL_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0df2c0e1e3fa3614d74ee91cefa8173">DMA_SxCR_PL_Pos</a>)</td></tr>
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<tr class="separator:ga3dc66d05a0b6c646926e155f584c2164"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14c115d71a4e3b3c4da360108288154c" id="r_ga14c115d71a4e3b3c4da360108288154c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14c115d71a4e3b3c4da360108288154c">DMA_SxCR_PL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3dc66d05a0b6c646926e155f584c2164">DMA_SxCR_PL_Msk</a></td></tr>
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<tr class="separator:ga14c115d71a4e3b3c4da360108288154c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41b1b2f7bd6f0af932ff0fb7df9336b6" id="r_ga41b1b2f7bd6f0af932ff0fb7df9336b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41b1b2f7bd6f0af932ff0fb7df9336b6">DMA_SxCR_PL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0df2c0e1e3fa3614d74ee91cefa8173">DMA_SxCR_PL_Pos</a>)</td></tr>
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<tr class="separator:ga41b1b2f7bd6f0af932ff0fb7df9336b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81817adc8c0ee54dea0f67a1a9e8eb77" id="r_ga81817adc8c0ee54dea0f67a1a9e8eb77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81817adc8c0ee54dea0f67a1a9e8eb77">DMA_SxCR_PL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0df2c0e1e3fa3614d74ee91cefa8173">DMA_SxCR_PL_Pos</a>)</td></tr>
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<tr class="separator:ga81817adc8c0ee54dea0f67a1a9e8eb77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e2c688c88288e3f899e47c4d11ca4fa" id="r_ga5e2c688c88288e3f899e47c4d11ca4fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e2c688c88288e3f899e47c4d11ca4fa">DMA_SxCR_PINCOS_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga5e2c688c88288e3f899e47c4d11ca4fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78df7ff746fecc4afaa5e980f11de4d6" id="r_ga78df7ff746fecc4afaa5e980f11de4d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78df7ff746fecc4afaa5e980f11de4d6">DMA_SxCR_PINCOS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e2c688c88288e3f899e47c4d11ca4fa">DMA_SxCR_PINCOS_Pos</a>)</td></tr>
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<tr class="separator:ga78df7ff746fecc4afaa5e980f11de4d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb929908d2e7fdef2136c20c93377c70" id="r_gaeb929908d2e7fdef2136c20c93377c70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb929908d2e7fdef2136c20c93377c70">DMA_SxCR_PINCOS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga78df7ff746fecc4afaa5e980f11de4d6">DMA_SxCR_PINCOS_Msk</a></td></tr>
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<tr class="separator:gaeb929908d2e7fdef2136c20c93377c70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55693651f2994a1c09f7b47455638a6a" id="r_ga55693651f2994a1c09f7b47455638a6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55693651f2994a1c09f7b47455638a6a">DMA_SxCR_MSIZE_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga769dd95d6aa84f0bc0080891094cd5bd" id="r_ga769dd95d6aa84f0bc0080891094cd5bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga769dd95d6aa84f0bc0080891094cd5bd">DMA_SxCR_MSIZE_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55693651f2994a1c09f7b47455638a6a">DMA_SxCR_MSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga769dd95d6aa84f0bc0080891094cd5bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9a98cb706a722d726d8ec6e9fe4a773" id="r_gae9a98cb706a722d726d8ec6e9fe4a773"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9a98cb706a722d726d8ec6e9fe4a773">DMA_SxCR_MSIZE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga769dd95d6aa84f0bc0080891094cd5bd">DMA_SxCR_MSIZE_Msk</a></td></tr>
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<tr class="separator:gae9a98cb706a722d726d8ec6e9fe4a773"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39adb60b3394b61366691b45b8c2b80f" id="r_ga39adb60b3394b61366691b45b8c2b80f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39adb60b3394b61366691b45b8c2b80f">DMA_SxCR_MSIZE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55693651f2994a1c09f7b47455638a6a">DMA_SxCR_MSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga39adb60b3394b61366691b45b8c2b80f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5c2ef08ab52de52b4e1fd785f60e263" id="r_gaa5c2ef08ab52de52b4e1fd785f60e263"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5c2ef08ab52de52b4e1fd785f60e263">DMA_SxCR_MSIZE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55693651f2994a1c09f7b47455638a6a">DMA_SxCR_MSIZE_Pos</a>)</td></tr>
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<tr class="separator:gaa5c2ef08ab52de52b4e1fd785f60e263"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56479851c087f5fe7ea9656862ad35e1" id="r_ga56479851c087f5fe7ea9656862ad35e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56479851c087f5fe7ea9656862ad35e1">DMA_SxCR_PSIZE_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga56479851c087f5fe7ea9656862ad35e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ddb21769dcff3c41c4bb61e66d8459a" id="r_ga1ddb21769dcff3c41c4bb61e66d8459a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ddb21769dcff3c41c4bb61e66d8459a">DMA_SxCR_PSIZE_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga56479851c087f5fe7ea9656862ad35e1">DMA_SxCR_PSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga1ddb21769dcff3c41c4bb61e66d8459a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea0808f979c27b7b68d79ad511e95ea0" id="r_gaea0808f979c27b7b68d79ad511e95ea0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea0808f979c27b7b68d79ad511e95ea0">DMA_SxCR_PSIZE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ddb21769dcff3c41c4bb61e66d8459a">DMA_SxCR_PSIZE_Msk</a></td></tr>
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<tr class="separator:gaea0808f979c27b7b68d79ad511e95ea0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab05cf3e3f7c9edae5c70d59b3b75b14f" id="r_gab05cf3e3f7c9edae5c70d59b3b75b14f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab05cf3e3f7c9edae5c70d59b3b75b14f">DMA_SxCR_PSIZE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga56479851c087f5fe7ea9656862ad35e1">DMA_SxCR_PSIZE_Pos</a>)</td></tr>
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<tr class="separator:gab05cf3e3f7c9edae5c70d59b3b75b14f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f376d0900380a3045cbeadd6a037302" id="r_ga8f376d0900380a3045cbeadd6a037302"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f376d0900380a3045cbeadd6a037302">DMA_SxCR_PSIZE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga56479851c087f5fe7ea9656862ad35e1">DMA_SxCR_PSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga8f376d0900380a3045cbeadd6a037302"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11d90925c956a5196f58cf3fc89aa56f" id="r_ga11d90925c956a5196f58cf3fc89aa56f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11d90925c956a5196f58cf3fc89aa56f">DMA_SxCR_MINC_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga11d90925c956a5196f58cf3fc89aa56f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b9b94c796c25b6dac673c711f74eb48" id="r_ga3b9b94c796c25b6dac673c711f74eb48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b9b94c796c25b6dac673c711f74eb48">DMA_SxCR_MINC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11d90925c956a5196f58cf3fc89aa56f">DMA_SxCR_MINC_Pos</a>)</td></tr>
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<tr class="separator:ga3b9b94c796c25b6dac673c711f74eb48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga771a295832a584a3777ede523a691719" id="r_ga771a295832a584a3777ede523a691719"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga771a295832a584a3777ede523a691719">DMA_SxCR_MINC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b9b94c796c25b6dac673c711f74eb48">DMA_SxCR_MINC_Msk</a></td></tr>
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<tr class="separator:ga771a295832a584a3777ede523a691719"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f2a2143daf87c92d37da6503762f7c5" id="r_ga6f2a2143daf87c92d37da6503762f7c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f2a2143daf87c92d37da6503762f7c5">DMA_SxCR_PINC_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga6f2a2143daf87c92d37da6503762f7c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0829e862db027069781244f9820113ab" id="r_ga0829e862db027069781244f9820113ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0829e862db027069781244f9820113ab">DMA_SxCR_PINC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f2a2143daf87c92d37da6503762f7c5">DMA_SxCR_PINC_Pos</a>)</td></tr>
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<tr class="separator:ga0829e862db027069781244f9820113ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29c5d5c559dd14646fdc170e74f1f03b" id="r_ga29c5d5c559dd14646fdc170e74f1f03b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29c5d5c559dd14646fdc170e74f1f03b">DMA_SxCR_PINC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0829e862db027069781244f9820113ab">DMA_SxCR_PINC_Msk</a></td></tr>
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<tr class="separator:ga29c5d5c559dd14646fdc170e74f1f03b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34774d3e38a7f910c9eb723208457a83" id="r_ga34774d3e38a7f910c9eb723208457a83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34774d3e38a7f910c9eb723208457a83">DMA_SxCR_CIRC_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga34774d3e38a7f910c9eb723208457a83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga873f1581fb2b88c20d6621143a5751ac" id="r_ga873f1581fb2b88c20d6621143a5751ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga873f1581fb2b88c20d6621143a5751ac">DMA_SxCR_CIRC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34774d3e38a7f910c9eb723208457a83">DMA_SxCR_CIRC_Pos</a>)</td></tr>
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<tr class="separator:ga873f1581fb2b88c20d6621143a5751ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc248dbc519cc580621cdadcdd8741fb" id="r_gadc248dbc519cc580621cdadcdd8741fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc248dbc519cc580621cdadcdd8741fb">DMA_SxCR_CIRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga873f1581fb2b88c20d6621143a5751ac">DMA_SxCR_CIRC_Msk</a></td></tr>
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<tr class="separator:gadc248dbc519cc580621cdadcdd8741fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8302200753a3788a5b45462513a84b6b" id="r_ga8302200753a3788a5b45462513a84b6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8302200753a3788a5b45462513a84b6b">DMA_SxCR_DIR_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga8302200753a3788a5b45462513a84b6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab6c4f77554490fc06ecbd63e0e81a696" id="r_gab6c4f77554490fc06ecbd63e0e81a696"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6c4f77554490fc06ecbd63e0e81a696">DMA_SxCR_DIR_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8302200753a3788a5b45462513a84b6b">DMA_SxCR_DIR_Pos</a>)</td></tr>
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<tr class="separator:gab6c4f77554490fc06ecbd63e0e81a696"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16bc78076551c42cbdc084e9d0006bd4" id="r_ga16bc78076551c42cbdc084e9d0006bd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16bc78076551c42cbdc084e9d0006bd4">DMA_SxCR_DIR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab6c4f77554490fc06ecbd63e0e81a696">DMA_SxCR_DIR_Msk</a></td></tr>
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<tr class="memitem:gadca9547536f3d2f76577275964b4875e" id="r_gadca9547536f3d2f76577275964b4875e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadca9547536f3d2f76577275964b4875e">DMA_SxCR_DIR_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8302200753a3788a5b45462513a84b6b">DMA_SxCR_DIR_Pos</a>)</td></tr>
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<tr class="separator:gadca9547536f3d2f76577275964b4875e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac52c8d6ecad03bfe531867fa7457f2ae" id="r_gac52c8d6ecad03bfe531867fa7457f2ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac52c8d6ecad03bfe531867fa7457f2ae">DMA_SxCR_DIR_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8302200753a3788a5b45462513a84b6b">DMA_SxCR_DIR_Pos</a>)</td></tr>
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<tr class="separator:gac52c8d6ecad03bfe531867fa7457f2ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9b6e1601b8fe4d4315dabeb21d87871" id="r_gac9b6e1601b8fe4d4315dabeb21d87871"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9b6e1601b8fe4d4315dabeb21d87871">DMA_SxCR_PFCTRL_Pos</a>   (5U)</td></tr>
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<tr class="separator:gac9b6e1601b8fe4d4315dabeb21d87871"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab67e3396d4689bc81191afda92e1864c" id="r_gab67e3396d4689bc81191afda92e1864c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab67e3396d4689bc81191afda92e1864c">DMA_SxCR_PFCTRL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9b6e1601b8fe4d4315dabeb21d87871">DMA_SxCR_PFCTRL_Pos</a>)</td></tr>
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<tr class="separator:gab67e3396d4689bc81191afda92e1864c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11f412d256043bec3e01ceef7f2099f2" id="r_ga11f412d256043bec3e01ceef7f2099f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11f412d256043bec3e01ceef7f2099f2">DMA_SxCR_PFCTRL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab67e3396d4689bc81191afda92e1864c">DMA_SxCR_PFCTRL_Msk</a></td></tr>
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<tr class="separator:ga11f412d256043bec3e01ceef7f2099f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04d5934cc3988e035dcb1bf40f6e755a" id="r_ga04d5934cc3988e035dcb1bf40f6e755a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04d5934cc3988e035dcb1bf40f6e755a">DMA_SxCR_TCIE_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga04d5934cc3988e035dcb1bf40f6e755a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86e6592b451e33103e1d6d119046a5e3" id="r_ga86e6592b451e33103e1d6d119046a5e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86e6592b451e33103e1d6d119046a5e3">DMA_SxCR_TCIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga04d5934cc3988e035dcb1bf40f6e755a">DMA_SxCR_TCIE_Pos</a>)</td></tr>
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<tr class="separator:ga86e6592b451e33103e1d6d119046a5e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ae47cc2cd2e985d29cb6b0bb65da1d7" id="r_ga6ae47cc2cd2e985d29cb6b0bb65da1d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ae47cc2cd2e985d29cb6b0bb65da1d7">DMA_SxCR_TCIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86e6592b451e33103e1d6d119046a5e3">DMA_SxCR_TCIE_Msk</a></td></tr>
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<tr class="separator:ga6ae47cc2cd2e985d29cb6b0bb65da1d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ed0223ba349ffb6e55d16415be0a92e" id="r_ga7ed0223ba349ffb6e55d16415be0a92e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ed0223ba349ffb6e55d16415be0a92e">DMA_SxCR_HTIE_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga7ed0223ba349ffb6e55d16415be0a92e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b2b5b47a0da93f112effd85edf7e27b" id="r_ga1b2b5b47a0da93f112effd85edf7e27b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b2b5b47a0da93f112effd85edf7e27b">DMA_SxCR_HTIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ed0223ba349ffb6e55d16415be0a92e">DMA_SxCR_HTIE_Pos</a>)</td></tr>
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<tr class="separator:ga1b2b5b47a0da93f112effd85edf7e27b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13a7fe097608bc5031d42ba69effed20" id="r_ga13a7fe097608bc5031d42ba69effed20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13a7fe097608bc5031d42ba69effed20">DMA_SxCR_HTIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b2b5b47a0da93f112effd85edf7e27b">DMA_SxCR_HTIE_Msk</a></td></tr>
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<tr class="memitem:ga3416da006a6a698c8f95f91e0b9b4b5f" id="r_ga3416da006a6a698c8f95f91e0b9b4b5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3416da006a6a698c8f95f91e0b9b4b5f">DMA_SxCR_TEIE_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga7e7331240fc8545d3dba92568b243039" id="r_ga7e7331240fc8545d3dba92568b243039"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e7331240fc8545d3dba92568b243039">DMA_SxCR_TEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3416da006a6a698c8f95f91e0b9b4b5f">DMA_SxCR_TEIE_Pos</a>)</td></tr>
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<tr class="memitem:gaeee99c36ba3ea56cdb4f73a0b01fb602" id="r_gaeee99c36ba3ea56cdb4f73a0b01fb602"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeee99c36ba3ea56cdb4f73a0b01fb602">DMA_SxCR_TEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e7331240fc8545d3dba92568b243039">DMA_SxCR_TEIE_Msk</a></td></tr>
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<tr class="memitem:ga90d77b99e19ffb0ce8533726db577011" id="r_ga90d77b99e19ffb0ce8533726db577011"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90d77b99e19ffb0ce8533726db577011">DMA_SxCR_DMEIE_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga640f196b45fc4e81ac468cbc3503148b" id="r_ga640f196b45fc4e81ac468cbc3503148b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga640f196b45fc4e81ac468cbc3503148b">DMA_SxCR_DMEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga90d77b99e19ffb0ce8533726db577011">DMA_SxCR_DMEIE_Pos</a>)</td></tr>
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<tr class="memitem:gacaecc56f94a9af756d077cf7df1b6c41" id="r_gacaecc56f94a9af756d077cf7df1b6c41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacaecc56f94a9af756d077cf7df1b6c41">DMA_SxCR_DMEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga640f196b45fc4e81ac468cbc3503148b">DMA_SxCR_DMEIE_Msk</a></td></tr>
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<tr class="separator:gacaecc56f94a9af756d077cf7df1b6c41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ae3e4666ee54b89bca73e5ce40032a8" id="r_ga0ae3e4666ee54b89bca73e5ce40032a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ae3e4666ee54b89bca73e5ce40032a8">DMA_SxCR_EN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0ae3e4666ee54b89bca73e5ce40032a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga038999913cf4b5608f4b06bde0f5b6f1" id="r_ga038999913cf4b5608f4b06bde0f5b6f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga038999913cf4b5608f4b06bde0f5b6f1">DMA_SxCR_EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ae3e4666ee54b89bca73e5ce40032a8">DMA_SxCR_EN_Pos</a>)</td></tr>
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<tr class="separator:ga038999913cf4b5608f4b06bde0f5b6f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabf69fe92e9a44167535365b0fe4ea9e" id="r_gaabf69fe92e9a44167535365b0fe4ea9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabf69fe92e9a44167535365b0fe4ea9e">DMA_SxCR_EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga038999913cf4b5608f4b06bde0f5b6f1">DMA_SxCR_EN_Msk</a></td></tr>
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<tr class="separator:gaabf69fe92e9a44167535365b0fe4ea9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4c9d3fe3ecd436e1e33bf246a8a1d81" id="r_gad4c9d3fe3ecd436e1e33bf246a8a1d81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4c9d3fe3ecd436e1e33bf246a8a1d81">DMA_SxCR_ACK_Pos</a>   (20U)</td></tr>
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<tr class="memitem:gae03b6c12b1fc9d635ce6abac4b15006e" id="r_gae03b6c12b1fc9d635ce6abac4b15006e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae03b6c12b1fc9d635ce6abac4b15006e">DMA_SxCR_ACK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad4c9d3fe3ecd436e1e33bf246a8a1d81">DMA_SxCR_ACK_Pos</a>)</td></tr>
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<tr class="separator:gae03b6c12b1fc9d635ce6abac4b15006e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f597f58faf86d2b78ad931079f57305" id="r_ga4f597f58faf86d2b78ad931079f57305"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f597f58faf86d2b78ad931079f57305">DMA_SxCR_ACK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae03b6c12b1fc9d635ce6abac4b15006e">DMA_SxCR_ACK_Msk</a></td></tr>
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<tr class="separator:ga4f597f58faf86d2b78ad931079f57305"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba02a9fd02f498e258e93837b511cdd1" id="r_gaba02a9fd02f498e258e93837b511cdd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gad9525ced3fadc78d4d5bb8234d226a52" id="r_gad9525ced3fadc78d4d5bb8234d226a52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9525ced3fadc78d4d5bb8234d226a52">DMA_SxNDT_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:gad9525ced3fadc78d4d5bb8234d226a52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62e0e1a1121885de705e618855ba83b0" id="r_ga62e0e1a1121885de705e618855ba83b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62e0e1a1121885de705e618855ba83b0">DMA_SxNDT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad9525ced3fadc78d4d5bb8234d226a52">DMA_SxNDT_Msk</a></td></tr>
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<tr class="separator:ga62e0e1a1121885de705e618855ba83b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ae52f0e22e621d60861143ca6027852" id="r_ga9ae52f0e22e621d60861143ca6027852"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ae52f0e22e621d60861143ca6027852">DMA_SxNDT_0</a>   (0x0001UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="memitem:ga4c4223f0a871ccfee403988befa42d94" id="r_ga4c4223f0a871ccfee403988befa42d94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c4223f0a871ccfee403988befa42d94">DMA_SxNDT_1</a>   (0x0002UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="memitem:ga4766cc41262f7b530351ecc5939fc222" id="r_ga4766cc41262f7b530351ecc5939fc222"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4766cc41262f7b530351ecc5939fc222">DMA_SxNDT_2</a>   (0x0004UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:ga4766cc41262f7b530351ecc5939fc222"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa43d96546fce4a436e4478a99ac0394" id="r_gaaa43d96546fce4a436e4478a99ac0394"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa43d96546fce4a436e4478a99ac0394">DMA_SxNDT_3</a>   (0x0008UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="memitem:ga81412c27b9d192be6c8c251b3a750e3c" id="r_ga81412c27b9d192be6c8c251b3a750e3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81412c27b9d192be6c8c251b3a750e3c">DMA_SxNDT_4</a>   (0x0010UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:ga81412c27b9d192be6c8c251b3a750e3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeff6beaa117fca4b6d1bbd87de34f674" id="r_gaeff6beaa117fca4b6d1bbd87de34f674"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeff6beaa117fca4b6d1bbd87de34f674">DMA_SxNDT_5</a>   (0x0020UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:gaeff6beaa117fca4b6d1bbd87de34f674"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7533a77655a960f82d08edfd2f4bf7ee" id="r_ga7533a77655a960f82d08edfd2f4bf7ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7533a77655a960f82d08edfd2f4bf7ee">DMA_SxNDT_6</a>   (0x0040UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:ga7533a77655a960f82d08edfd2f4bf7ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b2791b19fcf8586ffd28204bab2f2b4" id="r_ga4b2791b19fcf8586ffd28204bab2f2b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b2791b19fcf8586ffd28204bab2f2b4">DMA_SxNDT_7</a>   (0x0080UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:ga4b2791b19fcf8586ffd28204bab2f2b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6d77fc0aa9e027fc906f70f8e6a4aca" id="r_gaa6d77fc0aa9e027fc906f70f8e6a4aca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6d77fc0aa9e027fc906f70f8e6a4aca">DMA_SxNDT_8</a>   (0x0100UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:gaa6d77fc0aa9e027fc906f70f8e6a4aca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b4f096ed9b7f778e5b6beec36ca9698" id="r_ga4b4f096ed9b7f778e5b6beec36ca9698"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b4f096ed9b7f778e5b6beec36ca9698">DMA_SxNDT_9</a>   (0x0200UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:ga4b4f096ed9b7f778e5b6beec36ca9698"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64a0c2548db60b344bbbda72b53089ca" id="r_ga64a0c2548db60b344bbbda72b53089ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64a0c2548db60b344bbbda72b53089ca">DMA_SxNDT_10</a>   (0x0400UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:ga64a0c2548db60b344bbbda72b53089ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e37fe0da3a0c2e6ac94f999c8455187" id="r_ga6e37fe0da3a0c2e6ac94f999c8455187"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e37fe0da3a0c2e6ac94f999c8455187">DMA_SxNDT_11</a>   (0x0800UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:ga6e37fe0da3a0c2e6ac94f999c8455187"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa27c8ece8e904ef16ea45be9f7733103" id="r_gaa27c8ece8e904ef16ea45be9f7733103"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa27c8ece8e904ef16ea45be9f7733103">DMA_SxNDT_12</a>   (0x1000UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:gaa27c8ece8e904ef16ea45be9f7733103"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f320a375482fe097d3f1579925013bb" id="r_ga8f320a375482fe097d3f1579925013bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f320a375482fe097d3f1579925013bb">DMA_SxNDT_13</a>   (0x2000UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:ga8f320a375482fe097d3f1579925013bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8882d292259d683b075bf6c4e009b3ae" id="r_ga8882d292259d683b075bf6c4e009b3ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8882d292259d683b075bf6c4e009b3ae">DMA_SxNDT_14</a>   (0x4000UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:ga8882d292259d683b075bf6c4e009b3ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga386a1a2048a470bed80654cd548dea65" id="r_ga386a1a2048a470bed80654cd548dea65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga386a1a2048a470bed80654cd548dea65">DMA_SxNDT_15</a>   (0x8000UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1">DMA_SxNDT_Pos</a>)</td></tr>
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<tr class="separator:ga386a1a2048a470bed80654cd548dea65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10b0f3097f54eff7dd2d43bb1c31f736" id="r_ga10b0f3097f54eff7dd2d43bb1c31f736"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10b0f3097f54eff7dd2d43bb1c31f736">DMA_SxFCR_FEIE_Pos</a>   (7U)</td></tr>
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<tr class="memitem:gadff36ebec91293d8106a40bbf580be00" id="r_gadff36ebec91293d8106a40bbf580be00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadff36ebec91293d8106a40bbf580be00">DMA_SxFCR_FEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga10b0f3097f54eff7dd2d43bb1c31f736">DMA_SxFCR_FEIE_Pos</a>)</td></tr>
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<tr class="memitem:gaba9ca2264bc381abe0f4183729ab1fb1" id="r_gaba9ca2264bc381abe0f4183729ab1fb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba9ca2264bc381abe0f4183729ab1fb1">DMA_SxFCR_FEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadff36ebec91293d8106a40bbf580be00">DMA_SxFCR_FEIE_Msk</a></td></tr>
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<tr class="memitem:ga6719968db5f4e50b30015434339db896" id="r_ga6719968db5f4e50b30015434339db896"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6719968db5f4e50b30015434339db896">DMA_SxFCR_FS_Pos</a>   (3U)</td></tr>
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<tr class="memitem:ga46ecd57c9b56be53a38263c02d25c50f" id="r_ga46ecd57c9b56be53a38263c02d25c50f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46ecd57c9b56be53a38263c02d25c50f">DMA_SxFCR_FS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6719968db5f4e50b30015434339db896">DMA_SxFCR_FS_Pos</a>)</td></tr>
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<tr class="memitem:ga56094479dc9b173b00ccfb199d8a2853" id="r_ga56094479dc9b173b00ccfb199d8a2853"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56094479dc9b173b00ccfb199d8a2853">DMA_SxFCR_FS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga46ecd57c9b56be53a38263c02d25c50f">DMA_SxFCR_FS_Msk</a></td></tr>
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<tr class="memitem:gaccf0cb1a99fb8265535b15fc6a428060" id="r_gaccf0cb1a99fb8265535b15fc6a428060"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccf0cb1a99fb8265535b15fc6a428060">DMA_SxFCR_FS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6719968db5f4e50b30015434339db896">DMA_SxFCR_FS_Pos</a>)</td></tr>
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<tr class="memitem:ga6b5dd8e40fe393762866522caa0ab842" id="r_ga6b5dd8e40fe393762866522caa0ab842"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b5dd8e40fe393762866522caa0ab842">DMA_SxFCR_FS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6719968db5f4e50b30015434339db896">DMA_SxFCR_FS_Pos</a>)</td></tr>
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<tr class="memitem:ga51558a53d17a6deeed3937c15787361c" id="r_ga51558a53d17a6deeed3937c15787361c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51558a53d17a6deeed3937c15787361c">DMA_SxFCR_FS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6719968db5f4e50b30015434339db896">DMA_SxFCR_FS_Pos</a>)</td></tr>
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<tr class="memitem:ga562b4b1bcd309931c42bfe7793044e91" id="r_ga562b4b1bcd309931c42bfe7793044e91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga562b4b1bcd309931c42bfe7793044e91">DMA_SxFCR_DMDIS_Pos</a>   (2U)</td></tr>
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<tr class="memitem:gadedd400be2f182737e484d52be6b80c1" id="r_gadedd400be2f182737e484d52be6b80c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadedd400be2f182737e484d52be6b80c1">DMA_SxFCR_DMDIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga562b4b1bcd309931c42bfe7793044e91">DMA_SxFCR_DMDIS_Pos</a>)</td></tr>
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<tr class="memitem:ga89406bb954742665691c0ac2f8d95ec9" id="r_ga89406bb954742665691c0ac2f8d95ec9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89406bb954742665691c0ac2f8d95ec9">DMA_SxFCR_DMDIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadedd400be2f182737e484d52be6b80c1">DMA_SxFCR_DMDIS_Msk</a></td></tr>
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<tr class="memitem:gae6876e8621d30962774d2b72dbc720ec" id="r_gae6876e8621d30962774d2b72dbc720ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6876e8621d30962774d2b72dbc720ec">DMA_SxFCR_FTH_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga5e436952c24ada5a0c553043092285e7" id="r_ga5e436952c24ada5a0c553043092285e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e436952c24ada5a0c553043092285e7">DMA_SxFCR_FTH_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae6876e8621d30962774d2b72dbc720ec">DMA_SxFCR_FTH_Pos</a>)</td></tr>
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<tr class="memitem:ga44c16978164026a81f5b07280e800e7f" id="r_ga44c16978164026a81f5b07280e800e7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44c16978164026a81f5b07280e800e7f">DMA_SxFCR_FTH</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e436952c24ada5a0c553043092285e7">DMA_SxFCR_FTH_Msk</a></td></tr>
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<tr class="separator:ga44c16978164026a81f5b07280e800e7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63716e11d34bca95927671055aa63fe8" id="r_ga63716e11d34bca95927671055aa63fe8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63716e11d34bca95927671055aa63fe8">DMA_SxFCR_FTH_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae6876e8621d30962774d2b72dbc720ec">DMA_SxFCR_FTH_Pos</a>)</td></tr>
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<tr class="memitem:gae3d780fc1222a183071c73e62a0524a1" id="r_gae3d780fc1222a183071c73e62a0524a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3d780fc1222a183071c73e62a0524a1">DMA_SxFCR_FTH_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae6876e8621d30962774d2b72dbc720ec">DMA_SxFCR_FTH_Pos</a>)</td></tr>
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<tr class="memitem:ga1917ec61d4f0b063c4d63c94d00f104c" id="r_ga1917ec61d4f0b063c4d63c94d00f104c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1917ec61d4f0b063c4d63c94d00f104c">DMA_LISR_TCIF3_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga1917ec61d4f0b063c4d63c94d00f104c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fcbb22f764dbcd84f9f7679ba140fd8" id="r_ga9fcbb22f764dbcd84f9f7679ba140fd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fcbb22f764dbcd84f9f7679ba140fd8">DMA_LISR_TCIF3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1917ec61d4f0b063c4d63c94d00f104c">DMA_LISR_TCIF3_Pos</a>)</td></tr>
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<tr class="separator:ga9fcbb22f764dbcd84f9f7679ba140fd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44e5bf8adbb2646d325cba8d5dd670d8" id="r_ga44e5bf8adbb2646d325cba8d5dd670d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44e5bf8adbb2646d325cba8d5dd670d8">DMA_LISR_TCIF3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9fcbb22f764dbcd84f9f7679ba140fd8">DMA_LISR_TCIF3_Msk</a></td></tr>
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<tr class="memitem:gabc365b9d116f7bf0fb0bdb4a36b025f0" id="r_gabc365b9d116f7bf0fb0bdb4a36b025f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc365b9d116f7bf0fb0bdb4a36b025f0">DMA_LISR_HTIF3_Pos</a>   (26U)</td></tr>
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<tr class="separator:gabc365b9d116f7bf0fb0bdb4a36b025f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga202e6ae73e145494851e4c40f5c2eb2e" id="r_ga202e6ae73e145494851e4c40f5c2eb2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga202e6ae73e145494851e4c40f5c2eb2e">DMA_LISR_HTIF3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc365b9d116f7bf0fb0bdb4a36b025f0">DMA_LISR_HTIF3_Pos</a>)</td></tr>
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<tr class="separator:ga202e6ae73e145494851e4c40f5c2eb2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa10c891ee2ec333b7f87eea5886d574f" id="r_gaa10c891ee2ec333b7f87eea5886d574f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa10c891ee2ec333b7f87eea5886d574f">DMA_LISR_HTIF3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga202e6ae73e145494851e4c40f5c2eb2e">DMA_LISR_HTIF3_Msk</a></td></tr>
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<tr class="separator:gaa10c891ee2ec333b7f87eea5886d574f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3eb3514f45c12c124807ea04b5e5206d" id="r_ga3eb3514f45c12c124807ea04b5e5206d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3eb3514f45c12c124807ea04b5e5206d">DMA_LISR_TEIF3_Pos</a>   (25U)</td></tr>
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<tr class="memitem:ga770b6645dff14ef5d2950aff2995ec72" id="r_ga770b6645dff14ef5d2950aff2995ec72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga770b6645dff14ef5d2950aff2995ec72">DMA_LISR_TEIF3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3eb3514f45c12c124807ea04b5e5206d">DMA_LISR_TEIF3_Pos</a>)</td></tr>
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<tr class="memitem:ga5dfaba3a5db7cdcbddf9ee5974b44c2f" id="r_ga5dfaba3a5db7cdcbddf9ee5974b44c2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5dfaba3a5db7cdcbddf9ee5974b44c2f">DMA_LISR_TEIF3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga770b6645dff14ef5d2950aff2995ec72">DMA_LISR_TEIF3_Msk</a></td></tr>
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<tr class="memitem:ga9f039fe3193408bc81d812149996ea9f" id="r_ga9f039fe3193408bc81d812149996ea9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f039fe3193408bc81d812149996ea9f">DMA_LISR_DMEIF3_Pos</a>   (24U)</td></tr>
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<tr class="memitem:gad4331e1ec530a0dc0cbee400d5950b3a" id="r_gad4331e1ec530a0dc0cbee400d5950b3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4331e1ec530a0dc0cbee400d5950b3a">DMA_LISR_DMEIF3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f039fe3193408bc81d812149996ea9f">DMA_LISR_DMEIF3_Pos</a>)</td></tr>
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<tr class="separator:gad4331e1ec530a0dc0cbee400d5950b3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01fd1397b41221f5bdf6f107cb92e196" id="r_ga01fd1397b41221f5bdf6f107cb92e196"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01fd1397b41221f5bdf6f107cb92e196">DMA_LISR_DMEIF3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad4331e1ec530a0dc0cbee400d5950b3a">DMA_LISR_DMEIF3_Msk</a></td></tr>
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<tr class="memitem:gace4ae0196dace02aceafe1fe77b6e6d7" id="r_gace4ae0196dace02aceafe1fe77b6e6d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace4ae0196dace02aceafe1fe77b6e6d7">DMA_LISR_FEIF3_Pos</a>   (22U)</td></tr>
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<tr class="memitem:ga46bd312d438cb54d4b68b189cf120fd1" id="r_ga46bd312d438cb54d4b68b189cf120fd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46bd312d438cb54d4b68b189cf120fd1">DMA_LISR_FEIF3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gace4ae0196dace02aceafe1fe77b6e6d7">DMA_LISR_FEIF3_Pos</a>)</td></tr>
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<tr class="memitem:ga5367443a1378eef82aed62ca22763952" id="r_ga5367443a1378eef82aed62ca22763952"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5367443a1378eef82aed62ca22763952">DMA_LISR_FEIF3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga46bd312d438cb54d4b68b189cf120fd1">DMA_LISR_FEIF3_Msk</a></td></tr>
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<tr class="memitem:ga7d0716b2ad4127572e8b69fb92652f19" id="r_ga7d0716b2ad4127572e8b69fb92652f19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d0716b2ad4127572e8b69fb92652f19">DMA_LISR_TCIF2_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga7d0716b2ad4127572e8b69fb92652f19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae271580139c8f7d241532d0c833afe06" id="r_gae271580139c8f7d241532d0c833afe06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae271580139c8f7d241532d0c833afe06">DMA_LISR_TCIF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d0716b2ad4127572e8b69fb92652f19">DMA_LISR_TCIF2_Pos</a>)</td></tr>
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<tr class="separator:gae271580139c8f7d241532d0c833afe06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf21350cce8c4cb5d7c6fcf5edc930cf8" id="r_gaf21350cce8c4cb5d7c6fcf5edc930cf8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf21350cce8c4cb5d7c6fcf5edc930cf8">DMA_LISR_TCIF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae271580139c8f7d241532d0c833afe06">DMA_LISR_TCIF2_Msk</a></td></tr>
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<tr class="separator:gaf21350cce8c4cb5d7c6fcf5edc930cf8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2700c5fdeaa7186a38c920f5ec85ea49" id="r_ga2700c5fdeaa7186a38c920f5ec85ea49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2700c5fdeaa7186a38c920f5ec85ea49">DMA_LISR_HTIF2_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga2700c5fdeaa7186a38c920f5ec85ea49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83c87fe2679a6130003dd72b363e9c53" id="r_ga83c87fe2679a6130003dd72b363e9c53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83c87fe2679a6130003dd72b363e9c53">DMA_LISR_HTIF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2700c5fdeaa7186a38c920f5ec85ea49">DMA_LISR_HTIF2_Pos</a>)</td></tr>
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<tr class="separator:ga83c87fe2679a6130003dd72b363e9c53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ca25185d14a1f0c208ec8ceadc787a6" id="r_ga6ca25185d14a1f0c208ec8ceadc787a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ca25185d14a1f0c208ec8ceadc787a6">DMA_LISR_HTIF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga83c87fe2679a6130003dd72b363e9c53">DMA_LISR_HTIF2_Msk</a></td></tr>
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<tr class="separator:ga6ca25185d14a1f0c208ec8ceadc787a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac01bf79870cef24f0875200fba8ab778" id="r_gac01bf79870cef24f0875200fba8ab778"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac01bf79870cef24f0875200fba8ab778">DMA_LISR_TEIF2_Pos</a>   (19U)</td></tr>
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<tr class="separator:gac01bf79870cef24f0875200fba8ab778"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64f9f609e2612044dd911f853c401ce9" id="r_ga64f9f609e2612044dd911f853c401ce9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64f9f609e2612044dd911f853c401ce9">DMA_LISR_TEIF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac01bf79870cef24f0875200fba8ab778">DMA_LISR_TEIF2_Pos</a>)</td></tr>
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<tr class="separator:ga64f9f609e2612044dd911f853c401ce9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74d540802cadde42bdd6debae5d8ab89" id="r_ga74d540802cadde42bdd6debae5d8ab89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74d540802cadde42bdd6debae5d8ab89">DMA_LISR_TEIF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64f9f609e2612044dd911f853c401ce9">DMA_LISR_TEIF2_Msk</a></td></tr>
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<tr class="separator:ga74d540802cadde42bdd6debae5d8ab89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad852ffba4cb1b34e1cc77ba3f5075c03" id="r_gad852ffba4cb1b34e1cc77ba3f5075c03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad852ffba4cb1b34e1cc77ba3f5075c03">DMA_LISR_DMEIF2_Pos</a>   (18U)</td></tr>
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<tr class="separator:gad852ffba4cb1b34e1cc77ba3f5075c03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f7a3d352057475b51e9627d497bf8d5" id="r_ga6f7a3d352057475b51e9627d497bf8d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f7a3d352057475b51e9627d497bf8d5">DMA_LISR_DMEIF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad852ffba4cb1b34e1cc77ba3f5075c03">DMA_LISR_DMEIF2_Pos</a>)</td></tr>
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<tr class="separator:ga6f7a3d352057475b51e9627d497bf8d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc7edcd7404f0dcf19a724dfad22026a" id="r_gabc7edcd7404f0dcf19a724dfad22026a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc7edcd7404f0dcf19a724dfad22026a">DMA_LISR_DMEIF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f7a3d352057475b51e9627d497bf8d5">DMA_LISR_DMEIF2_Msk</a></td></tr>
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<tr class="separator:gabc7edcd7404f0dcf19a724dfad22026a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53433f2c39d945b72231cff33c0b6ccb" id="r_ga53433f2c39d945b72231cff33c0b6ccb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53433f2c39d945b72231cff33c0b6ccb">DMA_LISR_FEIF2_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga53433f2c39d945b72231cff33c0b6ccb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d4c97aa0bf50b5ff36e271bde6b2285" id="r_ga2d4c97aa0bf50b5ff36e271bde6b2285"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d4c97aa0bf50b5ff36e271bde6b2285">DMA_LISR_FEIF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga53433f2c39d945b72231cff33c0b6ccb">DMA_LISR_FEIF2_Pos</a>)</td></tr>
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<tr class="separator:ga2d4c97aa0bf50b5ff36e271bde6b2285"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99c42b194213872753460ef9b7745213" id="r_ga99c42b194213872753460ef9b7745213"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99c42b194213872753460ef9b7745213">DMA_LISR_FEIF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d4c97aa0bf50b5ff36e271bde6b2285">DMA_LISR_FEIF2_Msk</a></td></tr>
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<tr class="separator:ga99c42b194213872753460ef9b7745213"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03abe37d6a707015bd502285aa4ab71c" id="r_ga03abe37d6a707015bd502285aa4ab71c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03abe37d6a707015bd502285aa4ab71c">DMA_LISR_TCIF1_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga03abe37d6a707015bd502285aa4ab71c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga338a63d76a175d0ef90bd5469232cc69" id="r_ga338a63d76a175d0ef90bd5469232cc69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga338a63d76a175d0ef90bd5469232cc69">DMA_LISR_TCIF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga03abe37d6a707015bd502285aa4ab71c">DMA_LISR_TCIF1_Pos</a>)</td></tr>
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<tr class="separator:ga338a63d76a175d0ef90bd5469232cc69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae02aec39ded937b3ce816d3df4520d9b" id="r_gae02aec39ded937b3ce816d3df4520d9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae02aec39ded937b3ce816d3df4520d9b">DMA_LISR_TCIF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga338a63d76a175d0ef90bd5469232cc69">DMA_LISR_TCIF1_Msk</a></td></tr>
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<tr class="separator:gae02aec39ded937b3ce816d3df4520d9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00c7637307de891e63bc8ca8cb7750f4" id="r_ga00c7637307de891e63bc8ca8cb7750f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00c7637307de891e63bc8ca8cb7750f4">DMA_LISR_HTIF1_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga00c7637307de891e63bc8ca8cb7750f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c9343cd010bd919a13bf32f9a8d998f" id="r_ga3c9343cd010bd919a13bf32f9a8d998f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c9343cd010bd919a13bf32f9a8d998f">DMA_LISR_HTIF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga00c7637307de891e63bc8ca8cb7750f4">DMA_LISR_HTIF1_Pos</a>)</td></tr>
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<tr class="separator:ga3c9343cd010bd919a13bf32f9a8d998f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04304a9f8891e325247c0aaa4c9fac72" id="r_ga04304a9f8891e325247c0aaa4c9fac72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04304a9f8891e325247c0aaa4c9fac72">DMA_LISR_HTIF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c9343cd010bd919a13bf32f9a8d998f">DMA_LISR_HTIF1_Msk</a></td></tr>
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<tr class="separator:ga04304a9f8891e325247c0aaa4c9fac72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81e7b142424b2a4901007ea232482931" id="r_ga81e7b142424b2a4901007ea232482931"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81e7b142424b2a4901007ea232482931">DMA_LISR_TEIF1_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga81e7b142424b2a4901007ea232482931"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga014420a4087c5f7fa521536fed95a57b" id="r_ga014420a4087c5f7fa521536fed95a57b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga014420a4087c5f7fa521536fed95a57b">DMA_LISR_TEIF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga81e7b142424b2a4901007ea232482931">DMA_LISR_TEIF1_Pos</a>)</td></tr>
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<tr class="separator:ga014420a4087c5f7fa521536fed95a57b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cd826db0b9ea5544d1a93beb90f8972" id="r_ga0cd826db0b9ea5544d1a93beb90f8972"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cd826db0b9ea5544d1a93beb90f8972">DMA_LISR_TEIF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga014420a4087c5f7fa521536fed95a57b">DMA_LISR_TEIF1_Msk</a></td></tr>
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<tr class="separator:ga0cd826db0b9ea5544d1a93beb90f8972"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga863200d27b1112aa53312c17b3130fb9" id="r_ga863200d27b1112aa53312c17b3130fb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga863200d27b1112aa53312c17b3130fb9">DMA_LISR_DMEIF1_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga863200d27b1112aa53312c17b3130fb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71ddcdc61bbf235161b59b2fa356fa3b" id="r_ga71ddcdc61bbf235161b59b2fa356fa3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71ddcdc61bbf235161b59b2fa356fa3b">DMA_LISR_DMEIF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga863200d27b1112aa53312c17b3130fb9">DMA_LISR_DMEIF1_Pos</a>)</td></tr>
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<tr class="separator:ga71ddcdc61bbf235161b59b2fa356fa3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4903814bfc12dd6193416374fbddf8c" id="r_gaa4903814bfc12dd6193416374fbddf8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4903814bfc12dd6193416374fbddf8c">DMA_LISR_DMEIF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71ddcdc61bbf235161b59b2fa356fa3b">DMA_LISR_DMEIF1_Msk</a></td></tr>
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<tr class="separator:gaa4903814bfc12dd6193416374fbddf8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f8b90ddc0ba4459e396755e1fcc156f" id="r_ga4f8b90ddc0ba4459e396755e1fcc156f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f8b90ddc0ba4459e396755e1fcc156f">DMA_LISR_FEIF1_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga4f8b90ddc0ba4459e396755e1fcc156f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa932a51d97ae0952a1cf37b876ac9cbc" id="r_gaa932a51d97ae0952a1cf37b876ac9cbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa932a51d97ae0952a1cf37b876ac9cbc">DMA_LISR_FEIF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f8b90ddc0ba4459e396755e1fcc156f">DMA_LISR_FEIF1_Pos</a>)</td></tr>
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<tr class="separator:gaa932a51d97ae0952a1cf37b876ac9cbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbc4fecde60c09e12f10113a156bb922" id="r_gafbc4fecde60c09e12f10113a156bb922"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbc4fecde60c09e12f10113a156bb922">DMA_LISR_FEIF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa932a51d97ae0952a1cf37b876ac9cbc">DMA_LISR_FEIF1_Msk</a></td></tr>
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<tr class="separator:gafbc4fecde60c09e12f10113a156bb922"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ca6a950eb06d3526feab88473965afe" id="r_ga7ca6a950eb06d3526feab88473965afe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ca6a950eb06d3526feab88473965afe">DMA_LISR_TCIF0_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga7ca6a950eb06d3526feab88473965afe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0a6dc2ab51b3f572bf7dba9ee25354b" id="r_gae0a6dc2ab51b3f572bf7dba9ee25354b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0a6dc2ab51b3f572bf7dba9ee25354b">DMA_LISR_TCIF0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ca6a950eb06d3526feab88473965afe">DMA_LISR_TCIF0_Pos</a>)</td></tr>
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<tr class="separator:gae0a6dc2ab51b3f572bf7dba9ee25354b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbc3f7e52c0688bed4b71fa37666901d" id="r_gadbc3f7e52c0688bed4b71fa37666901d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbc3f7e52c0688bed4b71fa37666901d">DMA_LISR_TCIF0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae0a6dc2ab51b3f572bf7dba9ee25354b">DMA_LISR_TCIF0_Msk</a></td></tr>
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<tr class="separator:gadbc3f7e52c0688bed4b71fa37666901d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e84488e6b41b533d99b63e3a08008da" id="r_ga3e84488e6b41b533d99b63e3a08008da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e84488e6b41b533d99b63e3a08008da">DMA_LISR_HTIF0_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga8c5a05c426a6fc95eee5f6b387139293" id="r_ga8c5a05c426a6fc95eee5f6b387139293"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c5a05c426a6fc95eee5f6b387139293">DMA_LISR_HTIF0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e84488e6b41b533d99b63e3a08008da">DMA_LISR_HTIF0_Pos</a>)</td></tr>
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<tr class="separator:ga8c5a05c426a6fc95eee5f6b387139293"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6181727d13abbc46283ff22ce359e3b9" id="r_ga6181727d13abbc46283ff22ce359e3b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6181727d13abbc46283ff22ce359e3b9">DMA_LISR_HTIF0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c5a05c426a6fc95eee5f6b387139293">DMA_LISR_HTIF0_Msk</a></td></tr>
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<tr class="memitem:gae0ce7d8c40ff5bece107011e99d86e16" id="r_gae0ce7d8c40ff5bece107011e99d86e16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0ce7d8c40ff5bece107011e99d86e16">DMA_LISR_TEIF0_Pos</a>   (3U)</td></tr>
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<tr class="separator:gae0ce7d8c40ff5bece107011e99d86e16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8213385927a3d6b07c3e035b331fead4" id="r_ga8213385927a3d6b07c3e035b331fead4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8213385927a3d6b07c3e035b331fead4">DMA_LISR_TEIF0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae0ce7d8c40ff5bece107011e99d86e16">DMA_LISR_TEIF0_Pos</a>)</td></tr>
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<tr class="separator:ga8213385927a3d6b07c3e035b331fead4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad43cdafa5acfcd683b7a2ee8976dd8ba" id="r_gad43cdafa5acfcd683b7a2ee8976dd8ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad43cdafa5acfcd683b7a2ee8976dd8ba">DMA_LISR_TEIF0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8213385927a3d6b07c3e035b331fead4">DMA_LISR_TEIF0_Msk</a></td></tr>
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<tr class="separator:gad43cdafa5acfcd683b7a2ee8976dd8ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga143abdc2acba3fb3ff2e3bc76f8cbf9d" id="r_ga143abdc2acba3fb3ff2e3bc76f8cbf9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga143abdc2acba3fb3ff2e3bc76f8cbf9d">DMA_LISR_DMEIF0_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga143abdc2acba3fb3ff2e3bc76f8cbf9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66347e1824698903c1533784c2413f84" id="r_ga66347e1824698903c1533784c2413f84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66347e1824698903c1533784c2413f84">DMA_LISR_DMEIF0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga143abdc2acba3fb3ff2e3bc76f8cbf9d">DMA_LISR_DMEIF0_Pos</a>)</td></tr>
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<tr class="separator:ga66347e1824698903c1533784c2413f84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72de97ebc9d063dceb38bada91c44878" id="r_ga72de97ebc9d063dceb38bada91c44878"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72de97ebc9d063dceb38bada91c44878">DMA_LISR_DMEIF0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga66347e1824698903c1533784c2413f84">DMA_LISR_DMEIF0_Msk</a></td></tr>
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<tr class="separator:ga72de97ebc9d063dceb38bada91c44878"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0b4469def09a256f7ce049de364650a" id="r_gaf0b4469def09a256f7ce049de364650a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0b4469def09a256f7ce049de364650a">DMA_LISR_FEIF0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf0b4469def09a256f7ce049de364650a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4ecaf3690c72bee4bd08746779615dd" id="r_gac4ecaf3690c72bee4bd08746779615dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4ecaf3690c72bee4bd08746779615dd">DMA_LISR_FEIF0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0b4469def09a256f7ce049de364650a">DMA_LISR_FEIF0_Pos</a>)</td></tr>
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<tr class="separator:gac4ecaf3690c72bee4bd08746779615dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79bcc3f8e773206a66aba95c6f889d6f" id="r_ga79bcc3f8e773206a66aba95c6f889d6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79bcc3f8e773206a66aba95c6f889d6f">DMA_LISR_FEIF0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4ecaf3690c72bee4bd08746779615dd">DMA_LISR_FEIF0_Msk</a></td></tr>
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<tr class="separator:ga79bcc3f8e773206a66aba95c6f889d6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6de32d4d0c47fc9ee420f6f94e02f275" id="r_ga6de32d4d0c47fc9ee420f6f94e02f275"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6de32d4d0c47fc9ee420f6f94e02f275">DMA_HISR_TCIF7_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga6de32d4d0c47fc9ee420f6f94e02f275"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cecdf83cc7589761412e00b3d71e657" id="r_ga7cecdf83cc7589761412e00b3d71e657"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cecdf83cc7589761412e00b3d71e657">DMA_HISR_TCIF7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6de32d4d0c47fc9ee420f6f94e02f275">DMA_HISR_TCIF7_Pos</a>)</td></tr>
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<tr class="separator:ga7cecdf83cc7589761412e00b3d71e657"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad20a0a5e103def436d4e329fc0888482" id="r_gad20a0a5e103def436d4e329fc0888482"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad20a0a5e103def436d4e329fc0888482">DMA_HISR_TCIF7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cecdf83cc7589761412e00b3d71e657">DMA_HISR_TCIF7_Msk</a></td></tr>
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<tr class="separator:gad20a0a5e103def436d4e329fc0888482"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d1b08aa592736655c679f9f57275ecd" id="r_ga2d1b08aa592736655c679f9f57275ecd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d1b08aa592736655c679f9f57275ecd">DMA_HISR_HTIF7_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga2d1b08aa592736655c679f9f57275ecd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32a223400ca195866f036f2a3cdf2029" id="r_ga32a223400ca195866f036f2a3cdf2029"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32a223400ca195866f036f2a3cdf2029">DMA_HISR_HTIF7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d1b08aa592736655c679f9f57275ecd">DMA_HISR_HTIF7_Pos</a>)</td></tr>
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<tr class="separator:ga32a223400ca195866f036f2a3cdf2029"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf535d1a3209d2e2e0e616e2d7501525d" id="r_gaf535d1a3209d2e2e0e616e2d7501525d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf535d1a3209d2e2e0e616e2d7501525d">DMA_HISR_HTIF7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga32a223400ca195866f036f2a3cdf2029">DMA_HISR_HTIF7_Msk</a></td></tr>
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<tr class="separator:gaf535d1a3209d2e2e0e616e2d7501525d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9f7912fe43718644df70d92495a2fe8" id="r_gac9f7912fe43718644df70d92495a2fe8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9f7912fe43718644df70d92495a2fe8">DMA_HISR_TEIF7_Pos</a>   (25U)</td></tr>
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<tr class="separator:gac9f7912fe43718644df70d92495a2fe8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2754f465bbced1dec2e45bbb8fc9a3c4" id="r_ga2754f465bbced1dec2e45bbb8fc9a3c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2754f465bbced1dec2e45bbb8fc9a3c4">DMA_HISR_TEIF7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9f7912fe43718644df70d92495a2fe8">DMA_HISR_TEIF7_Pos</a>)</td></tr>
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<tr class="separator:ga2754f465bbced1dec2e45bbb8fc9a3c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga960f094539b5afc7f9d5e45b7909afe6" id="r_ga960f094539b5afc7f9d5e45b7909afe6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga960f094539b5afc7f9d5e45b7909afe6">DMA_HISR_TEIF7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2754f465bbced1dec2e45bbb8fc9a3c4">DMA_HISR_TEIF7_Msk</a></td></tr>
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<tr class="separator:ga960f094539b5afc7f9d5e45b7909afe6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e3c0b6526917df4addd70f13f7b9417" id="r_ga9e3c0b6526917df4addd70f13f7b9417"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e3c0b6526917df4addd70f13f7b9417">DMA_HISR_DMEIF7_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga9e3c0b6526917df4addd70f13f7b9417"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c027560b6bf31fb7926439500c32d6c" id="r_ga6c027560b6bf31fb7926439500c32d6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c027560b6bf31fb7926439500c32d6c">DMA_HISR_DMEIF7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e3c0b6526917df4addd70f13f7b9417">DMA_HISR_DMEIF7_Pos</a>)</td></tr>
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<tr class="separator:ga6c027560b6bf31fb7926439500c32d6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bb23848f8a022a47ab4abd5aa9b7d39" id="r_ga3bb23848f8a022a47ab4abd5aa9b7d39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bb23848f8a022a47ab4abd5aa9b7d39">DMA_HISR_DMEIF7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c027560b6bf31fb7926439500c32d6c">DMA_HISR_DMEIF7_Msk</a></td></tr>
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<tr class="separator:ga3bb23848f8a022a47ab4abd5aa9b7d39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga419c7042fb7439840a04e5fd445731d2" id="r_ga419c7042fb7439840a04e5fd445731d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga419c7042fb7439840a04e5fd445731d2">DMA_HISR_FEIF7_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga419c7042fb7439840a04e5fd445731d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fe1e3a74167419160edbbc759ca3789" id="r_ga4fe1e3a74167419160edbbc759ca3789"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fe1e3a74167419160edbbc759ca3789">DMA_HISR_FEIF7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga419c7042fb7439840a04e5fd445731d2">DMA_HISR_FEIF7_Pos</a>)</td></tr>
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<tr class="separator:ga4fe1e3a74167419160edbbc759ca3789"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadea53385fca360f16c4474db1cf18bc1" id="r_gadea53385fca360f16c4474db1cf18bc1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadea53385fca360f16c4474db1cf18bc1">DMA_HISR_FEIF7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4fe1e3a74167419160edbbc759ca3789">DMA_HISR_FEIF7_Msk</a></td></tr>
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<tr class="separator:gadea53385fca360f16c4474db1cf18bc1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d6ca1e8f590dcd64fae7d0aab508111" id="r_ga9d6ca1e8f590dcd64fae7d0aab508111"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d6ca1e8f590dcd64fae7d0aab508111">DMA_HISR_TCIF6_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga9d6ca1e8f590dcd64fae7d0aab508111"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8504bd4d44054ecc0974a59578f6f6ce" id="r_ga8504bd4d44054ecc0974a59578f6f6ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8504bd4d44054ecc0974a59578f6f6ce">DMA_HISR_TCIF6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d6ca1e8f590dcd64fae7d0aab508111">DMA_HISR_TCIF6_Pos</a>)</td></tr>
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<tr class="separator:ga8504bd4d44054ecc0974a59578f6f6ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad29468aa609150e241d9ae62c477cf45" id="r_gad29468aa609150e241d9ae62c477cf45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad29468aa609150e241d9ae62c477cf45">DMA_HISR_TCIF6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8504bd4d44054ecc0974a59578f6f6ce">DMA_HISR_TCIF6_Msk</a></td></tr>
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<tr class="separator:gad29468aa609150e241d9ae62c477cf45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27460df561ea71167eb046d7993a3763" id="r_ga27460df561ea71167eb046d7993a3763"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27460df561ea71167eb046d7993a3763">DMA_HISR_HTIF6_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga27460df561ea71167eb046d7993a3763"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga722b24166ff10769a7f325a6bda26272" id="r_ga722b24166ff10769a7f325a6bda26272"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga722b24166ff10769a7f325a6bda26272">DMA_HISR_HTIF6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27460df561ea71167eb046d7993a3763">DMA_HISR_HTIF6_Pos</a>)</td></tr>
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<tr class="separator:ga722b24166ff10769a7f325a6bda26272"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d39c14138e9ff216c203b288137144b" id="r_ga0d39c14138e9ff216c203b288137144b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d39c14138e9ff216c203b288137144b">DMA_HISR_HTIF6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga722b24166ff10769a7f325a6bda26272">DMA_HISR_HTIF6_Msk</a></td></tr>
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<tr class="separator:ga0d39c14138e9ff216c203b288137144b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83a1443bc4b15ef4c44d26611688b2d4" id="r_ga83a1443bc4b15ef4c44d26611688b2d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83a1443bc4b15ef4c44d26611688b2d4">DMA_HISR_TEIF6_Pos</a>   (19U)</td></tr>
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<tr class="memitem:gac6d3a65ce374edd183b14be4f40356e2" id="r_gac6d3a65ce374edd183b14be4f40356e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6d3a65ce374edd183b14be4f40356e2">DMA_HISR_TEIF6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83a1443bc4b15ef4c44d26611688b2d4">DMA_HISR_TEIF6_Pos</a>)</td></tr>
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<tr class="memitem:ga1a7ec01955fb504a5aa4f9f16a9ac52c" id="r_ga1a7ec01955fb504a5aa4f9f16a9ac52c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a7ec01955fb504a5aa4f9f16a9ac52c">DMA_HISR_TEIF6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac6d3a65ce374edd183b14be4f40356e2">DMA_HISR_TEIF6_Msk</a></td></tr>
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<tr class="memitem:gaf94b5e23736cdcfd2980ed8339ea346c" id="r_gaf94b5e23736cdcfd2980ed8339ea346c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf94b5e23736cdcfd2980ed8339ea346c">DMA_HISR_DMEIF6_Pos</a>   (18U)</td></tr>
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<tr class="memitem:ga903b58a651a1aaf08e3058d9aefb2e76" id="r_ga903b58a651a1aaf08e3058d9aefb2e76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga903b58a651a1aaf08e3058d9aefb2e76">DMA_HISR_DMEIF6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf94b5e23736cdcfd2980ed8339ea346c">DMA_HISR_DMEIF6_Pos</a>)</td></tr>
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<tr class="memitem:gab7b58e7ba316d3fc296f4433b3e62c38" id="r_gab7b58e7ba316d3fc296f4433b3e62c38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7b58e7ba316d3fc296f4433b3e62c38">DMA_HISR_DMEIF6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga903b58a651a1aaf08e3058d9aefb2e76">DMA_HISR_DMEIF6_Msk</a></td></tr>
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<tr class="separator:gab7b58e7ba316d3fc296f4433b3e62c38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5e631133a8a3dbcdad903d73cccb160" id="r_gaa5e631133a8a3dbcdad903d73cccb160"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5e631133a8a3dbcdad903d73cccb160">DMA_HISR_FEIF6_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gaa1736288bfd961d56e8571bdc91bd65b" id="r_gaa1736288bfd961d56e8571bdc91bd65b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1736288bfd961d56e8571bdc91bd65b">DMA_HISR_FEIF6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5e631133a8a3dbcdad903d73cccb160">DMA_HISR_FEIF6_Pos</a>)</td></tr>
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<tr class="separator:gaa1736288bfd961d56e8571bdc91bd65b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb297f94bde8d1aea580683d466ca8ca" id="r_gafb297f94bde8d1aea580683d466ca8ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb297f94bde8d1aea580683d466ca8ca">DMA_HISR_FEIF6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1736288bfd961d56e8571bdc91bd65b">DMA_HISR_FEIF6_Msk</a></td></tr>
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<tr class="memitem:gad9ec95df27557b62d73eb337ef879433" id="r_gad9ec95df27557b62d73eb337ef879433"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9ec95df27557b62d73eb337ef879433">DMA_HISR_TCIF5_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga57c25c3b163cfb7c292d5ebce785a2b7" id="r_ga57c25c3b163cfb7c292d5ebce785a2b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57c25c3b163cfb7c292d5ebce785a2b7">DMA_HISR_TCIF5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9ec95df27557b62d73eb337ef879433">DMA_HISR_TCIF5_Pos</a>)</td></tr>
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<tr class="separator:ga57c25c3b163cfb7c292d5ebce785a2b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64f15eaf1dd30450d1d35ee517507321" id="r_ga64f15eaf1dd30450d1d35ee517507321"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64f15eaf1dd30450d1d35ee517507321">DMA_HISR_TCIF5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57c25c3b163cfb7c292d5ebce785a2b7">DMA_HISR_TCIF5_Msk</a></td></tr>
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<tr class="memitem:ga922891bcfc085c0d080ce473b8515655" id="r_ga922891bcfc085c0d080ce473b8515655"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga922891bcfc085c0d080ce473b8515655">DMA_HISR_HTIF5_Pos</a>   (10U)</td></tr>
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<tr class="memitem:gad021f5ec7b128f0493f3f0989ad154ce" id="r_gad021f5ec7b128f0493f3f0989ad154ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad021f5ec7b128f0493f3f0989ad154ce">DMA_HISR_HTIF5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga922891bcfc085c0d080ce473b8515655">DMA_HISR_HTIF5_Pos</a>)</td></tr>
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<tr class="separator:gad021f5ec7b128f0493f3f0989ad154ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8617bf8160d1027879ffd354e04908d9" id="r_ga8617bf8160d1027879ffd354e04908d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8617bf8160d1027879ffd354e04908d9">DMA_HISR_HTIF5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad021f5ec7b128f0493f3f0989ad154ce">DMA_HISR_HTIF5_Msk</a></td></tr>
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<tr class="memitem:gaa6e505b2a29cc145b957dd8ea1c9c63f" id="r_gaa6e505b2a29cc145b957dd8ea1c9c63f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e505b2a29cc145b957dd8ea1c9c63f">DMA_HISR_TEIF5_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaa6e505b2a29cc145b957dd8ea1c9c63f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga706c81ee1877cd6f10dd96fd1668d0f8" id="r_ga706c81ee1877cd6f10dd96fd1668d0f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga706c81ee1877cd6f10dd96fd1668d0f8">DMA_HISR_TEIF5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e505b2a29cc145b957dd8ea1c9c63f">DMA_HISR_TEIF5_Pos</a>)</td></tr>
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<tr class="separator:ga706c81ee1877cd6f10dd96fd1668d0f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf16fb0e5d87f704c89824f961bfb7637" id="r_gaf16fb0e5d87f704c89824f961bfb7637"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf16fb0e5d87f704c89824f961bfb7637">DMA_HISR_TEIF5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga706c81ee1877cd6f10dd96fd1668d0f8">DMA_HISR_TEIF5_Msk</a></td></tr>
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<tr class="separator:gaf16fb0e5d87f704c89824f961bfb7637"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga327eb55ab7770ef13a50436627bc5edf" id="r_ga327eb55ab7770ef13a50436627bc5edf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga327eb55ab7770ef13a50436627bc5edf">DMA_HISR_DMEIF5_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga327eb55ab7770ef13a50436627bc5edf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae170cce8a55fc679cc5a50b1b947969d" id="r_gae170cce8a55fc679cc5a50b1b947969d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae170cce8a55fc679cc5a50b1b947969d">DMA_HISR_DMEIF5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga327eb55ab7770ef13a50436627bc5edf">DMA_HISR_DMEIF5_Pos</a>)</td></tr>
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<tr class="separator:gae170cce8a55fc679cc5a50b1b947969d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5ee964eee9c88fa28d32ce3ea6478f2" id="r_gac5ee964eee9c88fa28d32ce3ea6478f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5ee964eee9c88fa28d32ce3ea6478f2">DMA_HISR_DMEIF5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae170cce8a55fc679cc5a50b1b947969d">DMA_HISR_DMEIF5_Msk</a></td></tr>
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<tr class="separator:gac5ee964eee9c88fa28d32ce3ea6478f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24d536ac56c423089622de3d22968843" id="r_ga24d536ac56c423089622de3d22968843"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24d536ac56c423089622de3d22968843">DMA_HISR_FEIF5_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga24d536ac56c423089622de3d22968843"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bc4fff852e4fcf19079f79234caf9ae" id="r_ga0bc4fff852e4fcf19079f79234caf9ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bc4fff852e4fcf19079f79234caf9ae">DMA_HISR_FEIF5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24d536ac56c423089622de3d22968843">DMA_HISR_FEIF5_Pos</a>)</td></tr>
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<tr class="memitem:ga0d62494b31bb830433ddd683f4872519" id="r_ga0d62494b31bb830433ddd683f4872519"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d62494b31bb830433ddd683f4872519">DMA_HISR_FEIF5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bc4fff852e4fcf19079f79234caf9ae">DMA_HISR_FEIF5_Msk</a></td></tr>
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<tr class="memitem:ga98b35dac75c8a374912b8e99af926c97" id="r_ga98b35dac75c8a374912b8e99af926c97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98b35dac75c8a374912b8e99af926c97">DMA_HISR_TCIF4_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga98b35dac75c8a374912b8e99af926c97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0436cbb07d44b1049a8c9ff1e5438c48" id="r_ga0436cbb07d44b1049a8c9ff1e5438c48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0436cbb07d44b1049a8c9ff1e5438c48">DMA_HISR_TCIF4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98b35dac75c8a374912b8e99af926c97">DMA_HISR_TCIF4_Pos</a>)</td></tr>
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<tr class="separator:ga0436cbb07d44b1049a8c9ff1e5438c48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcce25c245499f9e62cb757e1871d973" id="r_gafcce25c245499f9e62cb757e1871d973"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcce25c245499f9e62cb757e1871d973">DMA_HISR_TCIF4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0436cbb07d44b1049a8c9ff1e5438c48">DMA_HISR_TCIF4_Msk</a></td></tr>
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<tr class="separator:gafcce25c245499f9e62cb757e1871d973"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf39dc71e13779a10a6855de4801528a2" id="r_gaf39dc71e13779a10a6855de4801528a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf39dc71e13779a10a6855de4801528a2">DMA_HISR_HTIF4_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga6117628ef3e354f4e6ce4ac3656bcd70" id="r_ga6117628ef3e354f4e6ce4ac3656bcd70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6117628ef3e354f4e6ce4ac3656bcd70">DMA_HISR_HTIF4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf39dc71e13779a10a6855de4801528a2">DMA_HISR_HTIF4_Pos</a>)</td></tr>
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<tr class="separator:ga6117628ef3e354f4e6ce4ac3656bcd70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadba8d24329c676d70560eda0b8c1e5b0" id="r_gadba8d24329c676d70560eda0b8c1e5b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadba8d24329c676d70560eda0b8c1e5b0">DMA_HISR_HTIF4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6117628ef3e354f4e6ce4ac3656bcd70">DMA_HISR_HTIF4_Msk</a></td></tr>
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<tr class="memitem:ga792ee749e2d12f4aa0cf3daca6b35057" id="r_ga792ee749e2d12f4aa0cf3daca6b35057"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga792ee749e2d12f4aa0cf3daca6b35057">DMA_HISR_TEIF4_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga792ee749e2d12f4aa0cf3daca6b35057"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac851827ca11788591231f3d29f4ecc1c" id="r_gac851827ca11788591231f3d29f4ecc1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac851827ca11788591231f3d29f4ecc1c">DMA_HISR_TEIF4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga792ee749e2d12f4aa0cf3daca6b35057">DMA_HISR_TEIF4_Pos</a>)</td></tr>
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<tr class="separator:gac851827ca11788591231f3d29f4ecc1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9005d4b958193fbd701c879eede467c1" id="r_ga9005d4b958193fbd701c879eede467c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9005d4b958193fbd701c879eede467c1">DMA_HISR_TEIF4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac851827ca11788591231f3d29f4ecc1c">DMA_HISR_TEIF4_Msk</a></td></tr>
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<tr class="memitem:ga88c83f6ccfd101de6926df1d9112fb4a" id="r_ga88c83f6ccfd101de6926df1d9112fb4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88c83f6ccfd101de6926df1d9112fb4a">DMA_HISR_DMEIF4_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga88c83f6ccfd101de6926df1d9112fb4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3bcb3c175f9e00b37de22d0d5cc041d" id="r_gae3bcb3c175f9e00b37de22d0d5cc041d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3bcb3c175f9e00b37de22d0d5cc041d">DMA_HISR_DMEIF4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga88c83f6ccfd101de6926df1d9112fb4a">DMA_HISR_DMEIF4_Pos</a>)</td></tr>
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<tr class="separator:gae3bcb3c175f9e00b37de22d0d5cc041d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf716f1bc12ea70f49802d84fb77646e8" id="r_gaf716f1bc12ea70f49802d84fb77646e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf716f1bc12ea70f49802d84fb77646e8">DMA_HISR_DMEIF4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3bcb3c175f9e00b37de22d0d5cc041d">DMA_HISR_DMEIF4_Msk</a></td></tr>
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<tr class="memitem:ga7d7e45dd9031bcf619e6ca233a56a2db" id="r_ga7d7e45dd9031bcf619e6ca233a56a2db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d7e45dd9031bcf619e6ca233a56a2db">DMA_HISR_FEIF4_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7d7e45dd9031bcf619e6ca233a56a2db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2dd4eb12e7b05343a0bddd0dd413ba4c" id="r_ga2dd4eb12e7b05343a0bddd0dd413ba4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dd4eb12e7b05343a0bddd0dd413ba4c">DMA_HISR_FEIF4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d7e45dd9031bcf619e6ca233a56a2db">DMA_HISR_FEIF4_Pos</a>)</td></tr>
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<tr class="separator:ga2dd4eb12e7b05343a0bddd0dd413ba4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacab90057201b1da9774308ff3fb6cfa1" id="r_gacab90057201b1da9774308ff3fb6cfa1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacab90057201b1da9774308ff3fb6cfa1">DMA_HISR_FEIF4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2dd4eb12e7b05343a0bddd0dd413ba4c">DMA_HISR_FEIF4_Msk</a></td></tr>
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<tr class="separator:gacab90057201b1da9774308ff3fb6cfa1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2297c4815dff938a02b0af13da8c42cd" id="r_ga2297c4815dff938a02b0af13da8c42cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2297c4815dff938a02b0af13da8c42cd">DMA_LIFCR_CTCIF3_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga2297c4815dff938a02b0af13da8c42cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ae2b6bed517a5d5f1f39e8fdd5ff18a" id="r_ga9ae2b6bed517a5d5f1f39e8fdd5ff18a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ae2b6bed517a5d5f1f39e8fdd5ff18a">DMA_LIFCR_CTCIF3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2297c4815dff938a02b0af13da8c42cd">DMA_LIFCR_CTCIF3_Pos</a>)</td></tr>
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<tr class="separator:ga9ae2b6bed517a5d5f1f39e8fdd5ff18a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5210736d34dc24eb9507975921233137" id="r_ga5210736d34dc24eb9507975921233137"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5210736d34dc24eb9507975921233137">DMA_LIFCR_CTCIF3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ae2b6bed517a5d5f1f39e8fdd5ff18a">DMA_LIFCR_CTCIF3_Msk</a></td></tr>
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<tr class="separator:ga5210736d34dc24eb9507975921233137"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga879918dd49c563c83d9b0baf39f608c8" id="r_ga879918dd49c563c83d9b0baf39f608c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga879918dd49c563c83d9b0baf39f608c8">DMA_LIFCR_CHTIF3_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga879918dd49c563c83d9b0baf39f608c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36f893f7c820962403289cc0f05e58bd" id="r_ga36f893f7c820962403289cc0f05e58bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36f893f7c820962403289cc0f05e58bd">DMA_LIFCR_CHTIF3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga879918dd49c563c83d9b0baf39f608c8">DMA_LIFCR_CHTIF3_Pos</a>)</td></tr>
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<tr class="separator:ga36f893f7c820962403289cc0f05e58bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ed3ab4e5d7975f985eb25dc65f99be3" id="r_ga0ed3ab4e5d7975f985eb25dc65f99be3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ed3ab4e5d7975f985eb25dc65f99be3">DMA_LIFCR_CHTIF3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36f893f7c820962403289cc0f05e58bd">DMA_LIFCR_CHTIF3_Msk</a></td></tr>
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<tr class="separator:ga0ed3ab4e5d7975f985eb25dc65f99be3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga200a4cd37d937325c0f891cd99b879a5" id="r_ga200a4cd37d937325c0f891cd99b879a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga200a4cd37d937325c0f891cd99b879a5">DMA_LIFCR_CTEIF3_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga200a4cd37d937325c0f891cd99b879a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafeab970135917ddac9a49e5c5d246188" id="r_gafeab970135917ddac9a49e5c5d246188"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafeab970135917ddac9a49e5c5d246188">DMA_LIFCR_CTEIF3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga200a4cd37d937325c0f891cd99b879a5">DMA_LIFCR_CTEIF3_Pos</a>)</td></tr>
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<tr class="separator:gafeab970135917ddac9a49e5c5d246188"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a51c601387d1ae49333d5ace8ae86ee" id="r_ga0a51c601387d1ae49333d5ace8ae86ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a51c601387d1ae49333d5ace8ae86ee">DMA_LIFCR_CTEIF3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafeab970135917ddac9a49e5c5d246188">DMA_LIFCR_CTEIF3_Msk</a></td></tr>
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<tr class="separator:ga0a51c601387d1ae49333d5ace8ae86ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5766d430a30ebb01d926b73c4838ee7" id="r_gae5766d430a30ebb01d926b73c4838ee7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5766d430a30ebb01d926b73c4838ee7">DMA_LIFCR_CDMEIF3_Pos</a>   (24U)</td></tr>
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<tr class="separator:gae5766d430a30ebb01d926b73c4838ee7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87881333fb961788c6b31d08a9705cc5" id="r_ga87881333fb961788c6b31d08a9705cc5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87881333fb961788c6b31d08a9705cc5">DMA_LIFCR_CDMEIF3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5766d430a30ebb01d926b73c4838ee7">DMA_LIFCR_CDMEIF3_Pos</a>)</td></tr>
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<tr class="separator:ga87881333fb961788c6b31d08a9705cc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabea10cdf2d3b0773b4e6b7fc9422f361" id="r_gabea10cdf2d3b0773b4e6b7fc9422f361"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabea10cdf2d3b0773b4e6b7fc9422f361">DMA_LIFCR_CDMEIF3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga87881333fb961788c6b31d08a9705cc5">DMA_LIFCR_CDMEIF3_Msk</a></td></tr>
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<tr class="separator:gabea10cdf2d3b0773b4e6b7fc9422f361"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ce98c26903f04095ebeb872ab8599e2" id="r_ga6ce98c26903f04095ebeb872ab8599e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ce98c26903f04095ebeb872ab8599e2">DMA_LIFCR_CFEIF3_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga6ce98c26903f04095ebeb872ab8599e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1733762b49e7da8c32a4d27044966872" id="r_ga1733762b49e7da8c32a4d27044966872"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1733762b49e7da8c32a4d27044966872">DMA_LIFCR_CFEIF3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ce98c26903f04095ebeb872ab8599e2">DMA_LIFCR_CFEIF3_Pos</a>)</td></tr>
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<tr class="separator:ga1733762b49e7da8c32a4d27044966872"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9432964145dc55af9186aea425e9963" id="r_gad9432964145dc55af9186aea425e9963"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9432964145dc55af9186aea425e9963">DMA_LIFCR_CFEIF3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1733762b49e7da8c32a4d27044966872">DMA_LIFCR_CFEIF3_Msk</a></td></tr>
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<tr class="separator:gad9432964145dc55af9186aea425e9963"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80de3a47390cdc24fdbb7a1c101d52df" id="r_ga80de3a47390cdc24fdbb7a1c101d52df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80de3a47390cdc24fdbb7a1c101d52df">DMA_LIFCR_CTCIF2_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga80de3a47390cdc24fdbb7a1c101d52df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19e090383d9196956fa52d732415263d" id="r_ga19e090383d9196956fa52d732415263d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19e090383d9196956fa52d732415263d">DMA_LIFCR_CTCIF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80de3a47390cdc24fdbb7a1c101d52df">DMA_LIFCR_CTCIF2_Pos</a>)</td></tr>
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<tr class="separator:ga19e090383d9196956fa52d732415263d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52d6df2b5ab2b43da273a702fe139b59" id="r_ga52d6df2b5ab2b43da273a702fe139b59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52d6df2b5ab2b43da273a702fe139b59">DMA_LIFCR_CTCIF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga19e090383d9196956fa52d732415263d">DMA_LIFCR_CTCIF2_Msk</a></td></tr>
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<tr class="separator:ga52d6df2b5ab2b43da273a702fe139b59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54fe74158bbf9ebfc8905b256c16b1aa" id="r_ga54fe74158bbf9ebfc8905b256c16b1aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54fe74158bbf9ebfc8905b256c16b1aa">DMA_LIFCR_CHTIF2_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga54fe74158bbf9ebfc8905b256c16b1aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac756f07e62c4b7f720924d67b42b9af7" id="r_gac756f07e62c4b7f720924d67b42b9af7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac756f07e62c4b7f720924d67b42b9af7">DMA_LIFCR_CHTIF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga54fe74158bbf9ebfc8905b256c16b1aa">DMA_LIFCR_CHTIF2_Pos</a>)</td></tr>
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<tr class="separator:gac756f07e62c4b7f720924d67b42b9af7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae19254e8ad726a73c6edc01bc7cf2cfa" id="r_gae19254e8ad726a73c6edc01bc7cf2cfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae19254e8ad726a73c6edc01bc7cf2cfa">DMA_LIFCR_CHTIF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac756f07e62c4b7f720924d67b42b9af7">DMA_LIFCR_CHTIF2_Msk</a></td></tr>
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<tr class="separator:gae19254e8ad726a73c6edc01bc7cf2cfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e4b3f5d3bbfba08a7716e8e14c7c7b2" id="r_ga8e4b3f5d3bbfba08a7716e8e14c7c7b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e4b3f5d3bbfba08a7716e8e14c7c7b2">DMA_LIFCR_CTEIF2_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga8e4b3f5d3bbfba08a7716e8e14c7c7b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27d209fe8a4bec205b32f36435895a3a" id="r_ga27d209fe8a4bec205b32f36435895a3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27d209fe8a4bec205b32f36435895a3a">DMA_LIFCR_CTEIF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e4b3f5d3bbfba08a7716e8e14c7c7b2">DMA_LIFCR_CTEIF2_Pos</a>)</td></tr>
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<tr class="separator:ga27d209fe8a4bec205b32f36435895a3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9d761752657a3d268da5434a04c6c6a" id="r_gaa9d761752657a3d268da5434a04c6c6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9d761752657a3d268da5434a04c6c6a">DMA_LIFCR_CTEIF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga27d209fe8a4bec205b32f36435895a3a">DMA_LIFCR_CTEIF2_Msk</a></td></tr>
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<tr class="separator:gaa9d761752657a3d268da5434a04c6c6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefc5081ac74c4a7cd7b9294d8be92251" id="r_gaefc5081ac74c4a7cd7b9294d8be92251"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefc5081ac74c4a7cd7b9294d8be92251">DMA_LIFCR_CDMEIF2_Pos</a>   (18U)</td></tr>
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<tr class="separator:gaefc5081ac74c4a7cd7b9294d8be92251"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacac8f0e26e7170255fb9d9fd31b1ccbe" id="r_gacac8f0e26e7170255fb9d9fd31b1ccbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacac8f0e26e7170255fb9d9fd31b1ccbe">DMA_LIFCR_CDMEIF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaefc5081ac74c4a7cd7b9294d8be92251">DMA_LIFCR_CDMEIF2_Pos</a>)</td></tr>
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<tr class="separator:gacac8f0e26e7170255fb9d9fd31b1ccbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7680fc5f5e6c0032044f1d8ab7766de8" id="r_ga7680fc5f5e6c0032044f1d8ab7766de8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7680fc5f5e6c0032044f1d8ab7766de8">DMA_LIFCR_CDMEIF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacac8f0e26e7170255fb9d9fd31b1ccbe">DMA_LIFCR_CDMEIF2_Msk</a></td></tr>
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<tr class="separator:ga7680fc5f5e6c0032044f1d8ab7766de8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cf455eeb40c690897a63399e06b980a" id="r_ga5cf455eeb40c690897a63399e06b980a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5cf455eeb40c690897a63399e06b980a">DMA_LIFCR_CFEIF2_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga117212472340bb8a793f05a4dcb98f03" id="r_ga117212472340bb8a793f05a4dcb98f03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga117212472340bb8a793f05a4dcb98f03">DMA_LIFCR_CFEIF2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cf455eeb40c690897a63399e06b980a">DMA_LIFCR_CFEIF2_Pos</a>)</td></tr>
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<tr class="separator:ga117212472340bb8a793f05a4dcb98f03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0f58173c721a4cee3f3885b352fa2a3" id="r_gae0f58173c721a4cee3f3885b352fa2a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0f58173c721a4cee3f3885b352fa2a3">DMA_LIFCR_CFEIF2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga117212472340bb8a793f05a4dcb98f03">DMA_LIFCR_CFEIF2_Msk</a></td></tr>
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<tr class="separator:gae0f58173c721a4cee3f3885b352fa2a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2be6c298222759f49d71995f225a9c8" id="r_gab2be6c298222759f49d71995f225a9c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2be6c298222759f49d71995f225a9c8">DMA_LIFCR_CTCIF1_Pos</a>   (11U)</td></tr>
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<tr class="separator:gab2be6c298222759f49d71995f225a9c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81fc3bbc2471af2fc722698c394b5595" id="r_ga81fc3bbc2471af2fc722698c394b5595"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81fc3bbc2471af2fc722698c394b5595">DMA_LIFCR_CTCIF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab2be6c298222759f49d71995f225a9c8">DMA_LIFCR_CTCIF1_Pos</a>)</td></tr>
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<tr class="separator:ga81fc3bbc2471af2fc722698c394b5595"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7494c54901b8f5bcb4894d20b8cfafed" id="r_ga7494c54901b8f5bcb4894d20b8cfafed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7494c54901b8f5bcb4894d20b8cfafed">DMA_LIFCR_CTCIF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga81fc3bbc2471af2fc722698c394b5595">DMA_LIFCR_CTCIF1_Msk</a></td></tr>
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<tr class="separator:ga7494c54901b8f5bcb4894d20b8cfafed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cceed053af9c55ee130b9cac3dfa40f" id="r_ga2cceed053af9c55ee130b9cac3dfa40f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cceed053af9c55ee130b9cac3dfa40f">DMA_LIFCR_CHTIF1_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga2cceed053af9c55ee130b9cac3dfa40f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c3edca2d07701c0b50a844454593d54" id="r_ga4c3edca2d07701c0b50a844454593d54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c3edca2d07701c0b50a844454593d54">DMA_LIFCR_CHTIF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cceed053af9c55ee130b9cac3dfa40f">DMA_LIFCR_CHTIF1_Pos</a>)</td></tr>
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<tr class="separator:ga4c3edca2d07701c0b50a844454593d54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2f38b0c141a9afb3943276dacdcb969" id="r_gad2f38b0c141a9afb3943276dacdcb969"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2f38b0c141a9afb3943276dacdcb969">DMA_LIFCR_CHTIF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c3edca2d07701c0b50a844454593d54">DMA_LIFCR_CHTIF1_Msk</a></td></tr>
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<tr class="separator:gad2f38b0c141a9afb3943276dacdcb969"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e5563a90f78b2aa62d4cc65fd2ea2e8" id="r_ga4e5563a90f78b2aa62d4cc65fd2ea2e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e5563a90f78b2aa62d4cc65fd2ea2e8">DMA_LIFCR_CTEIF1_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga4e5563a90f78b2aa62d4cc65fd2ea2e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf08b5acf028d011d3ccf519066f4e58e" id="r_gaf08b5acf028d011d3ccf519066f4e58e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf08b5acf028d011d3ccf519066f4e58e">DMA_LIFCR_CTEIF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e5563a90f78b2aa62d4cc65fd2ea2e8">DMA_LIFCR_CTEIF1_Pos</a>)</td></tr>
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<tr class="separator:gaf08b5acf028d011d3ccf519066f4e58e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6d8adf52567aee2969492db65d448d4" id="r_gaf6d8adf52567aee2969492db65d448d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6d8adf52567aee2969492db65d448d4">DMA_LIFCR_CTEIF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf08b5acf028d011d3ccf519066f4e58e">DMA_LIFCR_CTEIF1_Msk</a></td></tr>
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<tr class="separator:gaf6d8adf52567aee2969492db65d448d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7f3844824818f2a180921ec71e10165" id="r_gaf7f3844824818f2a180921ec71e10165"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7f3844824818f2a180921ec71e10165">DMA_LIFCR_CDMEIF1_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaf7f3844824818f2a180921ec71e10165"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d5941929a8582fdaf1e413063b56728" id="r_ga4d5941929a8582fdaf1e413063b56728"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d5941929a8582fdaf1e413063b56728">DMA_LIFCR_CDMEIF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7f3844824818f2a180921ec71e10165">DMA_LIFCR_CDMEIF1_Pos</a>)</td></tr>
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<tr class="separator:ga4d5941929a8582fdaf1e413063b56728"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a5aea54a390886f7de82e87e6dfc936" id="r_ga9a5aea54a390886f7de82e87e6dfc936"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a5aea54a390886f7de82e87e6dfc936">DMA_LIFCR_CDMEIF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d5941929a8582fdaf1e413063b56728">DMA_LIFCR_CDMEIF1_Msk</a></td></tr>
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<tr class="separator:ga9a5aea54a390886f7de82e87e6dfc936"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7449839b8ccb071b0297c04b3f308374" id="r_ga7449839b8ccb071b0297c04b3f308374"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7449839b8ccb071b0297c04b3f308374">DMA_LIFCR_CFEIF1_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga7449839b8ccb071b0297c04b3f308374"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0809a566feea19caa99820c0beb7593a" id="r_ga0809a566feea19caa99820c0beb7593a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0809a566feea19caa99820c0beb7593a">DMA_LIFCR_CFEIF1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7449839b8ccb071b0297c04b3f308374">DMA_LIFCR_CFEIF1_Pos</a>)</td></tr>
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<tr class="separator:ga0809a566feea19caa99820c0beb7593a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96cea0049553ab806bbc956f52528c37" id="r_ga96cea0049553ab806bbc956f52528c37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96cea0049553ab806bbc956f52528c37">DMA_LIFCR_CFEIF1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0809a566feea19caa99820c0beb7593a">DMA_LIFCR_CFEIF1_Msk</a></td></tr>
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<tr class="separator:ga96cea0049553ab806bbc956f52528c37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafee1c266c0c7d8ae75506988c24f197a" id="r_gafee1c266c0c7d8ae75506988c24f197a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafee1c266c0c7d8ae75506988c24f197a">DMA_LIFCR_CTCIF0_Pos</a>   (5U)</td></tr>
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<tr class="separator:gafee1c266c0c7d8ae75506988c24f197a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a99e08422f2f1ab8858824e873f0a5d" id="r_ga5a99e08422f2f1ab8858824e873f0a5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a99e08422f2f1ab8858824e873f0a5d">DMA_LIFCR_CTCIF0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafee1c266c0c7d8ae75506988c24f197a">DMA_LIFCR_CTCIF0_Pos</a>)</td></tr>
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<tr class="separator:ga5a99e08422f2f1ab8858824e873f0a5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7a0b2cc41c63504195714614e59dc8e" id="r_gab7a0b2cc41c63504195714614e59dc8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7a0b2cc41c63504195714614e59dc8e">DMA_LIFCR_CTCIF0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a99e08422f2f1ab8858824e873f0a5d">DMA_LIFCR_CTCIF0_Msk</a></td></tr>
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<tr class="separator:gab7a0b2cc41c63504195714614e59dc8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4745b0ea4d34ffb750b377de2865dee" id="r_gae4745b0ea4d34ffb750b377de2865dee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4745b0ea4d34ffb750b377de2865dee">DMA_LIFCR_CHTIF0_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae4745b0ea4d34ffb750b377de2865dee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca0f3b2beb4ae475024f013bfbe7813e" id="r_gaca0f3b2beb4ae475024f013bfbe7813e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca0f3b2beb4ae475024f013bfbe7813e">DMA_LIFCR_CHTIF0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4745b0ea4d34ffb750b377de2865dee">DMA_LIFCR_CHTIF0_Pos</a>)</td></tr>
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<tr class="separator:gaca0f3b2beb4ae475024f013bfbe7813e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44f83ba08feb98240a553403d977b8d1" id="r_ga44f83ba08feb98240a553403d977b8d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44f83ba08feb98240a553403d977b8d1">DMA_LIFCR_CHTIF0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaca0f3b2beb4ae475024f013bfbe7813e">DMA_LIFCR_CHTIF0_Msk</a></td></tr>
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<tr class="separator:ga44f83ba08feb98240a553403d977b8d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac20301e14197382e7e5f532fe6d3c21f" id="r_gac20301e14197382e7e5f532fe6d3c21f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac20301e14197382e7e5f532fe6d3c21f">DMA_LIFCR_CTEIF0_Pos</a>   (3U)</td></tr>
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<tr class="separator:gac20301e14197382e7e5f532fe6d3c21f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e2bd6764a2c823750659f82e6ab82e4" id="r_ga1e2bd6764a2c823750659f82e6ab82e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e2bd6764a2c823750659f82e6ab82e4">DMA_LIFCR_CTEIF0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac20301e14197382e7e5f532fe6d3c21f">DMA_LIFCR_CTEIF0_Pos</a>)</td></tr>
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<tr class="separator:ga1e2bd6764a2c823750659f82e6ab82e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5824a64683ce2039260c952d989bf420" id="r_ga5824a64683ce2039260c952d989bf420"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5824a64683ce2039260c952d989bf420">DMA_LIFCR_CTEIF0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e2bd6764a2c823750659f82e6ab82e4">DMA_LIFCR_CTEIF0_Msk</a></td></tr>
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<tr class="separator:ga5824a64683ce2039260c952d989bf420"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9328d47385259284470fe88126f161c1" id="r_ga9328d47385259284470fe88126f161c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9328d47385259284470fe88126f161c1">DMA_LIFCR_CDMEIF0_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga9328d47385259284470fe88126f161c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad09384dd4e933d5ae8490599f09b60f" id="r_gaad09384dd4e933d5ae8490599f09b60f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad09384dd4e933d5ae8490599f09b60f">DMA_LIFCR_CDMEIF0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9328d47385259284470fe88126f161c1">DMA_LIFCR_CDMEIF0_Pos</a>)</td></tr>
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<tr class="separator:gaad09384dd4e933d5ae8490599f09b60f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe80a122bf0537e8c95877ccf2b7b6d9" id="r_gafe80a122bf0537e8c95877ccf2b7b6d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe80a122bf0537e8c95877ccf2b7b6d9">DMA_LIFCR_CDMEIF0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaad09384dd4e933d5ae8490599f09b60f">DMA_LIFCR_CDMEIF0_Msk</a></td></tr>
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<tr class="separator:gafe80a122bf0537e8c95877ccf2b7b6d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89140d2a2a82950d5cbd470e264fb525" id="r_ga89140d2a2a82950d5cbd470e264fb525"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89140d2a2a82950d5cbd470e264fb525">DMA_LIFCR_CFEIF0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga89140d2a2a82950d5cbd470e264fb525"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5e3b1026a57f00f382879e844835e95" id="r_gac5e3b1026a57f00f382879e844835e95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5e3b1026a57f00f382879e844835e95">DMA_LIFCR_CFEIF0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga89140d2a2a82950d5cbd470e264fb525">DMA_LIFCR_CFEIF0_Pos</a>)</td></tr>
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<tr class="separator:gac5e3b1026a57f00f382879e844835e95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf6b8892189f3779f7fecf529ed87c74" id="r_gadf6b8892189f3779f7fecf529ed87c74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf6b8892189f3779f7fecf529ed87c74">DMA_LIFCR_CFEIF0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac5e3b1026a57f00f382879e844835e95">DMA_LIFCR_CFEIF0_Msk</a></td></tr>
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<tr class="separator:gadf6b8892189f3779f7fecf529ed87c74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42d3e6cfd2eef1e3d12e677af584447e" id="r_ga42d3e6cfd2eef1e3d12e677af584447e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42d3e6cfd2eef1e3d12e677af584447e">DMA_HIFCR_CTCIF7_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga42d3e6cfd2eef1e3d12e677af584447e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade1f557e9a94cd3841f22f0955ab2a43" id="r_gade1f557e9a94cd3841f22f0955ab2a43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade1f557e9a94cd3841f22f0955ab2a43">DMA_HIFCR_CTCIF7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga42d3e6cfd2eef1e3d12e677af584447e">DMA_HIFCR_CTCIF7_Pos</a>)</td></tr>
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<tr class="separator:gade1f557e9a94cd3841f22f0955ab2a43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf8056629f4948fb236b4339e213cc69" id="r_gadf8056629f4948fb236b4339e213cc69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf8056629f4948fb236b4339e213cc69">DMA_HIFCR_CTCIF7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gade1f557e9a94cd3841f22f0955ab2a43">DMA_HIFCR_CTCIF7_Msk</a></td></tr>
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<tr class="separator:gadf8056629f4948fb236b4339e213cc69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade6f40f4c574d22ec8527d8c27e78b58" id="r_gade6f40f4c574d22ec8527d8c27e78b58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade6f40f4c574d22ec8527d8c27e78b58">DMA_HIFCR_CHTIF7_Pos</a>   (26U)</td></tr>
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<tr class="separator:gade6f40f4c574d22ec8527d8c27e78b58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga256a0e76673c186a39f9f717af2e2287" id="r_ga256a0e76673c186a39f9f717af2e2287"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga256a0e76673c186a39f9f717af2e2287">DMA_HIFCR_CHTIF7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade6f40f4c574d22ec8527d8c27e78b58">DMA_HIFCR_CHTIF7_Pos</a>)</td></tr>
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<tr class="separator:ga256a0e76673c186a39f9f717af2e2287"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95e9989cbd70b18d833bb4cfcb8afce9" id="r_ga95e9989cbd70b18d833bb4cfcb8afce9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95e9989cbd70b18d833bb4cfcb8afce9">DMA_HIFCR_CHTIF7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga256a0e76673c186a39f9f717af2e2287">DMA_HIFCR_CHTIF7_Msk</a></td></tr>
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<tr class="separator:ga95e9989cbd70b18d833bb4cfcb8afce9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafae9da1fff2402f645b428368a4aea14" id="r_gafae9da1fff2402f645b428368a4aea14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafae9da1fff2402f645b428368a4aea14">DMA_HIFCR_CTEIF7_Pos</a>   (25U)</td></tr>
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<tr class="separator:gafae9da1fff2402f645b428368a4aea14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08c1daec30b9644c55db577867afe491" id="r_ga08c1daec30b9644c55db577867afe491"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08c1daec30b9644c55db577867afe491">DMA_HIFCR_CTEIF7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafae9da1fff2402f645b428368a4aea14">DMA_HIFCR_CTEIF7_Pos</a>)</td></tr>
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<tr class="separator:ga08c1daec30b9644c55db577867afe491"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84ab215e0b217547745beefb65dfefdf" id="r_ga84ab215e0b217547745beefb65dfefdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84ab215e0b217547745beefb65dfefdf">DMA_HIFCR_CTEIF7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga08c1daec30b9644c55db577867afe491">DMA_HIFCR_CTEIF7_Msk</a></td></tr>
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<tr class="separator:ga84ab215e0b217547745beefb65dfefdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f4cf4a690ee458370ce8482e3a9b1b9" id="r_ga6f4cf4a690ee458370ce8482e3a9b1b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f4cf4a690ee458370ce8482e3a9b1b9">DMA_HIFCR_CDMEIF7_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga6f4cf4a690ee458370ce8482e3a9b1b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb5c753438fac42cee45e0e9a34fab6c" id="r_gabb5c753438fac42cee45e0e9a34fab6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb5c753438fac42cee45e0e9a34fab6c">DMA_HIFCR_CDMEIF7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f4cf4a690ee458370ce8482e3a9b1b9">DMA_HIFCR_CDMEIF7_Pos</a>)</td></tr>
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<tr class="separator:gabb5c753438fac42cee45e0e9a34fab6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad70bf852fd8c24d79fcc104c950a589f" id="r_gad70bf852fd8c24d79fcc104c950a589f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad70bf852fd8c24d79fcc104c950a589f">DMA_HIFCR_CDMEIF7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabb5c753438fac42cee45e0e9a34fab6c">DMA_HIFCR_CDMEIF7_Msk</a></td></tr>
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<tr class="separator:gad70bf852fd8c24d79fcc104c950a589f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga913da2290fb4ba8484a69b34e71840c7" id="r_ga913da2290fb4ba8484a69b34e71840c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga913da2290fb4ba8484a69b34e71840c7">DMA_HIFCR_CFEIF7_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga913da2290fb4ba8484a69b34e71840c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga962da3b48acc29b53beae6ae483f5331" id="r_ga962da3b48acc29b53beae6ae483f5331"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga962da3b48acc29b53beae6ae483f5331">DMA_HIFCR_CFEIF7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga913da2290fb4ba8484a69b34e71840c7">DMA_HIFCR_CFEIF7_Pos</a>)</td></tr>
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<tr class="separator:ga962da3b48acc29b53beae6ae483f5331"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50332abe2e7b5a4f9cffd65d9a29382a" id="r_ga50332abe2e7b5a4f9cffd65d9a29382a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50332abe2e7b5a4f9cffd65d9a29382a">DMA_HIFCR_CFEIF7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga962da3b48acc29b53beae6ae483f5331">DMA_HIFCR_CFEIF7_Msk</a></td></tr>
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<tr class="separator:ga50332abe2e7b5a4f9cffd65d9a29382a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga194f6a4be6fd796e114fb77ea2f15220" id="r_ga194f6a4be6fd796e114fb77ea2f15220"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga194f6a4be6fd796e114fb77ea2f15220">DMA_HIFCR_CTCIF6_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga194f6a4be6fd796e114fb77ea2f15220"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8367ef52cfc4bb3dd4e1bbf8c01fc189" id="r_ga8367ef52cfc4bb3dd4e1bbf8c01fc189"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8367ef52cfc4bb3dd4e1bbf8c01fc189">DMA_HIFCR_CTCIF6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga194f6a4be6fd796e114fb77ea2f15220">DMA_HIFCR_CTCIF6_Pos</a>)</td></tr>
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<tr class="separator:ga8367ef52cfc4bb3dd4e1bbf8c01fc189"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd88be16962491e41e586f5109014bc6" id="r_gacd88be16962491e41e586f5109014bc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd88be16962491e41e586f5109014bc6">DMA_HIFCR_CTCIF6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8367ef52cfc4bb3dd4e1bbf8c01fc189">DMA_HIFCR_CTCIF6_Msk</a></td></tr>
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<tr class="separator:gacd88be16962491e41e586f5109014bc6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4768327967dc957b842d2433d2cc5c2" id="r_gae4768327967dc957b842d2433d2cc5c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4768327967dc957b842d2433d2cc5c2">DMA_HIFCR_CHTIF6_Pos</a>   (20U)</td></tr>
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<tr class="separator:gae4768327967dc957b842d2433d2cc5c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6464e076a7b905e1b4a73e367fb4488e" id="r_ga6464e076a7b905e1b4a73e367fb4488e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6464e076a7b905e1b4a73e367fb4488e">DMA_HIFCR_CHTIF6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4768327967dc957b842d2433d2cc5c2">DMA_HIFCR_CHTIF6_Pos</a>)</td></tr>
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<tr class="separator:ga6464e076a7b905e1b4a73e367fb4488e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed7cbbbc0602d00e101e3f57aa3b696a" id="r_gaed7cbbbc0602d00e101e3f57aa3b696a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed7cbbbc0602d00e101e3f57aa3b696a">DMA_HIFCR_CHTIF6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6464e076a7b905e1b4a73e367fb4488e">DMA_HIFCR_CHTIF6_Msk</a></td></tr>
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<tr class="separator:gaed7cbbbc0602d00e101e3f57aa3b696a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e0f6b1fd4902396d59d0d9865bd329e" id="r_ga8e0f6b1fd4902396d59d0d9865bd329e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e0f6b1fd4902396d59d0d9865bd329e">DMA_HIFCR_CTEIF6_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga8e0f6b1fd4902396d59d0d9865bd329e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4328c04dd38fc2360b7333d6e22d8f73" id="r_ga4328c04dd38fc2360b7333d6e22d8f73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4328c04dd38fc2360b7333d6e22d8f73">DMA_HIFCR_CTEIF6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e0f6b1fd4902396d59d0d9865bd329e">DMA_HIFCR_CTEIF6_Pos</a>)</td></tr>
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<tr class="separator:ga4328c04dd38fc2360b7333d6e22d8f73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69e01e2f6a5cd1c800321e4121f8e788" id="r_ga69e01e2f6a5cd1c800321e4121f8e788"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69e01e2f6a5cd1c800321e4121f8e788">DMA_HIFCR_CTEIF6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4328c04dd38fc2360b7333d6e22d8f73">DMA_HIFCR_CTEIF6_Msk</a></td></tr>
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<tr class="separator:ga69e01e2f6a5cd1c800321e4121f8e788"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a658f3e303a31be475cb1ea9957dc2e" id="r_ga2a658f3e303a31be475cb1ea9957dc2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a658f3e303a31be475cb1ea9957dc2e">DMA_HIFCR_CDMEIF6_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga2a658f3e303a31be475cb1ea9957dc2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga798be301c7de50d3015965037a8ec2bd" id="r_ga798be301c7de50d3015965037a8ec2bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga798be301c7de50d3015965037a8ec2bd">DMA_HIFCR_CDMEIF6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a658f3e303a31be475cb1ea9957dc2e">DMA_HIFCR_CDMEIF6_Pos</a>)</td></tr>
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<tr class="separator:ga798be301c7de50d3015965037a8ec2bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f73fa93a4e01fbf279e920eca139807" id="r_ga7f73fa93a4e01fbf279e920eca139807"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f73fa93a4e01fbf279e920eca139807">DMA_HIFCR_CDMEIF6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga798be301c7de50d3015965037a8ec2bd">DMA_HIFCR_CDMEIF6_Msk</a></td></tr>
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<tr class="separator:ga7f73fa93a4e01fbf279e920eca139807"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cbdd122358aad1b832dcc0a7a4405af" id="r_ga1cbdd122358aad1b832dcc0a7a4405af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cbdd122358aad1b832dcc0a7a4405af">DMA_HIFCR_CFEIF6_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga1cbdd122358aad1b832dcc0a7a4405af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4bb45a54e669718435808019bd2b9fb" id="r_gaf4bb45a54e669718435808019bd2b9fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4bb45a54e669718435808019bd2b9fb">DMA_HIFCR_CFEIF6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1cbdd122358aad1b832dcc0a7a4405af">DMA_HIFCR_CFEIF6_Pos</a>)</td></tr>
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<tr class="separator:gaf4bb45a54e669718435808019bd2b9fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39a0a7f42498f71dedae8140483b7ced" id="r_ga39a0a7f42498f71dedae8140483b7ced"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39a0a7f42498f71dedae8140483b7ced">DMA_HIFCR_CFEIF6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4bb45a54e669718435808019bd2b9fb">DMA_HIFCR_CFEIF6_Msk</a></td></tr>
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<tr class="memitem:ga9e2ab5fecba1f2673c14bc21e9052dc9" id="r_ga9e2ab5fecba1f2673c14bc21e9052dc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e2ab5fecba1f2673c14bc21e9052dc9">DMA_HIFCR_CTCIF5_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga9e2ab5fecba1f2673c14bc21e9052dc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bec2f8ae9244ef971aed8aa9253f7fe" id="r_ga0bec2f8ae9244ef971aed8aa9253f7fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bec2f8ae9244ef971aed8aa9253f7fe">DMA_HIFCR_CTCIF5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e2ab5fecba1f2673c14bc21e9052dc9">DMA_HIFCR_CTCIF5_Pos</a>)</td></tr>
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<tr class="separator:ga0bec2f8ae9244ef971aed8aa9253f7fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa55d19705147a6ee16effe9ec1012a72" id="r_gaa55d19705147a6ee16effe9ec1012a72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa55d19705147a6ee16effe9ec1012a72">DMA_HIFCR_CTCIF5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bec2f8ae9244ef971aed8aa9253f7fe">DMA_HIFCR_CTCIF5_Msk</a></td></tr>
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<tr class="separator:gaa55d19705147a6ee16effe9ec1012a72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f5d41d4856f8ff464ce01e96e9f6e3f" id="r_ga3f5d41d4856f8ff464ce01e96e9f6e3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f5d41d4856f8ff464ce01e96e9f6e3f">DMA_HIFCR_CHTIF5_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga3f5d41d4856f8ff464ce01e96e9f6e3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1ff3abfbb813d2e7c030d9b16786d00" id="r_gaa1ff3abfbb813d2e7c030d9b16786d00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1ff3abfbb813d2e7c030d9b16786d00">DMA_HIFCR_CHTIF5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f5d41d4856f8ff464ce01e96e9f6e3f">DMA_HIFCR_CHTIF5_Pos</a>)</td></tr>
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<tr class="separator:gaa1ff3abfbb813d2e7c030d9b16786d00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cef7eeccd11737c1ebf5735284046cc" id="r_ga2cef7eeccd11737c1ebf5735284046cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cef7eeccd11737c1ebf5735284046cc">DMA_HIFCR_CHTIF5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1ff3abfbb813d2e7c030d9b16786d00">DMA_HIFCR_CHTIF5_Msk</a></td></tr>
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<tr class="separator:ga2cef7eeccd11737c1ebf5735284046cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42493eb990d42aa17c178842ecef08bd" id="r_ga42493eb990d42aa17c178842ecef08bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42493eb990d42aa17c178842ecef08bd">DMA_HIFCR_CTEIF5_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga42493eb990d42aa17c178842ecef08bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca104c26dd5e9190434023a88d0dc4ac" id="r_gaca104c26dd5e9190434023a88d0dc4ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca104c26dd5e9190434023a88d0dc4ac">DMA_HIFCR_CTEIF5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga42493eb990d42aa17c178842ecef08bd">DMA_HIFCR_CTEIF5_Pos</a>)</td></tr>
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<tr class="separator:gaca104c26dd5e9190434023a88d0dc4ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33394fe20a3567c8baaeb15ad9aab586" id="r_ga33394fe20a3567c8baaeb15ad9aab586"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33394fe20a3567c8baaeb15ad9aab586">DMA_HIFCR_CTEIF5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaca104c26dd5e9190434023a88d0dc4ac">DMA_HIFCR_CTEIF5_Msk</a></td></tr>
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<tr class="separator:ga33394fe20a3567c8baaeb15ad9aab586"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f259d0788bd3ae21521c574d0d1a00b" id="r_ga1f259d0788bd3ae21521c574d0d1a00b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f259d0788bd3ae21521c574d0d1a00b">DMA_HIFCR_CDMEIF5_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga1f259d0788bd3ae21521c574d0d1a00b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b99d7b4f3c6346ccafa79d425ee6873" id="r_ga3b99d7b4f3c6346ccafa79d425ee6873"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b99d7b4f3c6346ccafa79d425ee6873">DMA_HIFCR_CDMEIF5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f259d0788bd3ae21521c574d0d1a00b">DMA_HIFCR_CDMEIF5_Pos</a>)</td></tr>
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<tr class="separator:ga3b99d7b4f3c6346ccafa79d425ee6873"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15b404d9e1601cf3627cbf0163b50221" id="r_ga15b404d9e1601cf3627cbf0163b50221"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15b404d9e1601cf3627cbf0163b50221">DMA_HIFCR_CDMEIF5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b99d7b4f3c6346ccafa79d425ee6873">DMA_HIFCR_CDMEIF5_Msk</a></td></tr>
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<tr class="separator:ga15b404d9e1601cf3627cbf0163b50221"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60dbe00935c13e0ef57c08970f711a6a" id="r_ga60dbe00935c13e0ef57c08970f711a6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60dbe00935c13e0ef57c08970f711a6a">DMA_HIFCR_CFEIF5_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga60dbe00935c13e0ef57c08970f711a6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab48755800a0d03cf51f6c69848c6e1ce" id="r_gab48755800a0d03cf51f6c69848c6e1ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab48755800a0d03cf51f6c69848c6e1ce">DMA_HIFCR_CFEIF5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga60dbe00935c13e0ef57c08970f711a6a">DMA_HIFCR_CFEIF5_Pos</a>)</td></tr>
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<tr class="separator:gab48755800a0d03cf51f6c69848c6e1ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a4e90af967fa0a76c842384264e0e52" id="r_ga9a4e90af967fa0a76c842384264e0e52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a4e90af967fa0a76c842384264e0e52">DMA_HIFCR_CFEIF5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab48755800a0d03cf51f6c69848c6e1ce">DMA_HIFCR_CFEIF5_Msk</a></td></tr>
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<tr class="separator:ga9a4e90af967fa0a76c842384264e0e52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeaf0336605023f5db079294ebe4ea822" id="r_gaeaf0336605023f5db079294ebe4ea822"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeaf0336605023f5db079294ebe4ea822">DMA_HIFCR_CTCIF4_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaeaf0336605023f5db079294ebe4ea822"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae02d30716d6c3e975c13073ae65f69e5" id="r_gae02d30716d6c3e975c13073ae65f69e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae02d30716d6c3e975c13073ae65f69e5">DMA_HIFCR_CTCIF4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaf0336605023f5db079294ebe4ea822">DMA_HIFCR_CTCIF4_Pos</a>)</td></tr>
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<tr class="separator:gae02d30716d6c3e975c13073ae65f69e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42e529507a40f0dc4c16da7cc6d659db" id="r_ga42e529507a40f0dc4c16da7cc6d659db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42e529507a40f0dc4c16da7cc6d659db">DMA_HIFCR_CTCIF4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae02d30716d6c3e975c13073ae65f69e5">DMA_HIFCR_CTCIF4_Msk</a></td></tr>
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<tr class="separator:ga42e529507a40f0dc4c16da7cc6d659db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3415c8fd19bcb513fc96363d287784a4" id="r_ga3415c8fd19bcb513fc96363d287784a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3415c8fd19bcb513fc96363d287784a4">DMA_HIFCR_CHTIF4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga3415c8fd19bcb513fc96363d287784a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa1aa9781098072d161c20890c3d1918" id="r_gafa1aa9781098072d161c20890c3d1918"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa1aa9781098072d161c20890c3d1918">DMA_HIFCR_CHTIF4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3415c8fd19bcb513fc96363d287784a4">DMA_HIFCR_CHTIF4_Pos</a>)</td></tr>
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<tr class="separator:gafa1aa9781098072d161c20890c3d1918"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8f0afa9a6526f7f4413766417a56be8" id="r_gaf8f0afa9a6526f7f4413766417a56be8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8f0afa9a6526f7f4413766417a56be8">DMA_HIFCR_CHTIF4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafa1aa9781098072d161c20890c3d1918">DMA_HIFCR_CHTIF4_Msk</a></td></tr>
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<tr class="separator:gaf8f0afa9a6526f7f4413766417a56be8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d1ac1b86e7505eceef920910bd930e2" id="r_ga9d1ac1b86e7505eceef920910bd930e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d1ac1b86e7505eceef920910bd930e2">DMA_HIFCR_CTEIF4_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga9d1ac1b86e7505eceef920910bd930e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5aa004e3db2fb6845a6678bd30d9a604" id="r_ga5aa004e3db2fb6845a6678bd30d9a604"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5aa004e3db2fb6845a6678bd30d9a604">DMA_HIFCR_CTEIF4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d1ac1b86e7505eceef920910bd930e2">DMA_HIFCR_CTEIF4_Pos</a>)</td></tr>
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<tr class="separator:ga5aa004e3db2fb6845a6678bd30d9a604"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e05ff4fc6bace9cc6c0f0d4ec7b3314" id="r_ga9e05ff4fc6bace9cc6c0f0d4ec7b3314"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e05ff4fc6bace9cc6c0f0d4ec7b3314">DMA_HIFCR_CTEIF4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5aa004e3db2fb6845a6678bd30d9a604">DMA_HIFCR_CTEIF4_Msk</a></td></tr>
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<tr class="separator:ga9e05ff4fc6bace9cc6c0f0d4ec7b3314"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga465e500de4458c78f26aa483d8f61ee7" id="r_ga465e500de4458c78f26aa483d8f61ee7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga465e500de4458c78f26aa483d8f61ee7">DMA_HIFCR_CDMEIF4_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga465e500de4458c78f26aa483d8f61ee7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c5757329dbf0633cbe2ff33591b7f2d" id="r_ga3c5757329dbf0633cbe2ff33591b7f2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c5757329dbf0633cbe2ff33591b7f2d">DMA_HIFCR_CDMEIF4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga465e500de4458c78f26aa483d8f61ee7">DMA_HIFCR_CDMEIF4_Pos</a>)</td></tr>
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<tr class="separator:ga3c5757329dbf0633cbe2ff33591b7f2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d70d58a4423ac8973c30ddbc7404b44" id="r_ga0d70d58a4423ac8973c30ddbc7404b44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d70d58a4423ac8973c30ddbc7404b44">DMA_HIFCR_CDMEIF4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c5757329dbf0633cbe2ff33591b7f2d">DMA_HIFCR_CDMEIF4_Msk</a></td></tr>
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<tr class="separator:ga0d70d58a4423ac8973c30ddbc7404b44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga348534b63d5c5d29a3fdd8b080866566" id="r_ga348534b63d5c5d29a3fdd8b080866566"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga348534b63d5c5d29a3fdd8b080866566">DMA_HIFCR_CFEIF4_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga348534b63d5c5d29a3fdd8b080866566"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd6d4a4e8764fa0406a1c9dd1bc4535f" id="r_gadd6d4a4e8764fa0406a1c9dd1bc4535f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd6d4a4e8764fa0406a1c9dd1bc4535f">DMA_HIFCR_CFEIF4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga348534b63d5c5d29a3fdd8b080866566">DMA_HIFCR_CFEIF4_Pos</a>)</td></tr>
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<tr class="separator:gadd6d4a4e8764fa0406a1c9dd1bc4535f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e5ea118900178d4fa2d19656c1b48ff" id="r_ga1e5ea118900178d4fa2d19656c1b48ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5ea118900178d4fa2d19656c1b48ff">DMA_HIFCR_CFEIF4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadd6d4a4e8764fa0406a1c9dd1bc4535f">DMA_HIFCR_CFEIF4_Msk</a></td></tr>
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<tr class="separator:ga1e5ea118900178d4fa2d19656c1b48ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga323024ac58e46cdcb78e207f1749775c" id="r_ga323024ac58e46cdcb78e207f1749775c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga323024ac58e46cdcb78e207f1749775c">DMA_SxPAR_PA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga323024ac58e46cdcb78e207f1749775c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19727ba46d26c121b0133381ceb4b521" id="r_ga19727ba46d26c121b0133381ceb4b521"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19727ba46d26c121b0133381ceb4b521">DMA_SxPAR_PA_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga323024ac58e46cdcb78e207f1749775c">DMA_SxPAR_PA_Pos</a>)</td></tr>
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<tr class="memitem:ga05ea0d30f566ad469a7794e088b93ecf" id="r_ga05ea0d30f566ad469a7794e088b93ecf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05ea0d30f566ad469a7794e088b93ecf">DMA_SxPAR_PA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga19727ba46d26c121b0133381ceb4b521">DMA_SxPAR_PA_Msk</a></td></tr>
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<tr class="separator:ga05ea0d30f566ad469a7794e088b93ecf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade05cbad452eb0b6e0a2627ff70c0145" id="r_gade05cbad452eb0b6e0a2627ff70c0145"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade05cbad452eb0b6e0a2627ff70c0145">DMA_SxM0AR_M0A_Pos</a>   (0U)</td></tr>
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<tr class="separator:gade05cbad452eb0b6e0a2627ff70c0145"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9675f5a5f6306fe441e0ee395b055d36" id="r_ga9675f5a5f6306fe441e0ee395b055d36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9675f5a5f6306fe441e0ee395b055d36">DMA_SxM0AR_M0A_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade05cbad452eb0b6e0a2627ff70c0145">DMA_SxM0AR_M0A_Pos</a>)</td></tr>
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<tr class="separator:ga9675f5a5f6306fe441e0ee395b055d36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad87688b73616d4ff9503421a820f1cf" id="r_gaad87688b73616d4ff9503421a820f1cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad87688b73616d4ff9503421a820f1cf">DMA_SxM0AR_M0A</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9675f5a5f6306fe441e0ee395b055d36">DMA_SxM0AR_M0A_Msk</a></td></tr>
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<tr class="separator:gaad87688b73616d4ff9503421a820f1cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa61888c070a3873c9fb8ee1486772e3a" id="r_gaa61888c070a3873c9fb8ee1486772e3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa61888c070a3873c9fb8ee1486772e3a">DMA_SxM1AR_M1A_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa61888c070a3873c9fb8ee1486772e3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73d1e5bcfadadcb890897b907225cd73" id="r_ga73d1e5bcfadadcb890897b907225cd73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73d1e5bcfadadcb890897b907225cd73">DMA_SxM1AR_M1A_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa61888c070a3873c9fb8ee1486772e3a">DMA_SxM1AR_M1A_Pos</a>)</td></tr>
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<tr class="separator:ga73d1e5bcfadadcb890897b907225cd73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae057bfb6e5d7b553b668a050fcdb152d" id="r_gae057bfb6e5d7b553b668a050fcdb152d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae057bfb6e5d7b553b668a050fcdb152d">DMA_SxM1AR_M1A</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga73d1e5bcfadadcb890897b907225cd73">DMA_SxM1AR_M1A_Msk</a></td></tr>
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<tr class="separator:gae057bfb6e5d7b553b668a050fcdb152d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4702ca255bab973cffa5dd240594a7a3" id="r_ga4702ca255bab973cffa5dd240594a7a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4702ca255bab973cffa5dd240594a7a3">EXTI_IMR_MR0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4702ca255bab973cffa5dd240594a7a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf1117a400c80d740d3dbb7fbea0f8ce" id="r_gaaf1117a400c80d740d3dbb7fbea0f8ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf1117a400c80d740d3dbb7fbea0f8ce">EXTI_IMR_MR0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4702ca255bab973cffa5dd240594a7a3">EXTI_IMR_MR0_Pos</a>)</td></tr>
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<tr class="separator:gaaf1117a400c80d740d3dbb7fbea0f8ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad03b2ba6cde99065627fccabd54ac097" id="r_gad03b2ba6cde99065627fccabd54ac097"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad03b2ba6cde99065627fccabd54ac097">EXTI_IMR_MR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf1117a400c80d740d3dbb7fbea0f8ce">EXTI_IMR_MR0_Msk</a></td></tr>
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<tr class="separator:gad03b2ba6cde99065627fccabd54ac097"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27eb2217e842fa69573590793a1e6b38" id="r_ga27eb2217e842fa69573590793a1e6b38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27eb2217e842fa69573590793a1e6b38">EXTI_IMR_MR1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga27eb2217e842fa69573590793a1e6b38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacadc6566dd71406d2d516785c4b776bd" id="r_gacadc6566dd71406d2d516785c4b776bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacadc6566dd71406d2d516785c4b776bd">EXTI_IMR_MR1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27eb2217e842fa69573590793a1e6b38">EXTI_IMR_MR1_Pos</a>)</td></tr>
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<tr class="separator:gacadc6566dd71406d2d516785c4b776bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaaf3f9a86c620149893db38c83f8ba58" id="r_gaaaf3f9a86c620149893db38c83f8ba58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaaf3f9a86c620149893db38c83f8ba58">EXTI_IMR_MR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacadc6566dd71406d2d516785c4b776bd">EXTI_IMR_MR1_Msk</a></td></tr>
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<tr class="separator:gaaaf3f9a86c620149893db38c83f8ba58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58855e17d769f246e7422b3f875c85a2" id="r_ga58855e17d769f246e7422b3f875c85a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58855e17d769f246e7422b3f875c85a2">EXTI_IMR_MR2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga58855e17d769f246e7422b3f875c85a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga183b9b9663a6aeec66f0238abbbf282f" id="r_ga183b9b9663a6aeec66f0238abbbf282f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga183b9b9663a6aeec66f0238abbbf282f">EXTI_IMR_MR2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58855e17d769f246e7422b3f875c85a2">EXTI_IMR_MR2_Pos</a>)</td></tr>
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<tr class="separator:ga183b9b9663a6aeec66f0238abbbf282f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71604d1c29973c5e2bf69c8e94e89f67" id="r_ga71604d1c29973c5e2bf69c8e94e89f67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71604d1c29973c5e2bf69c8e94e89f67">EXTI_IMR_MR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga183b9b9663a6aeec66f0238abbbf282f">EXTI_IMR_MR2_Msk</a></td></tr>
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<tr class="separator:ga71604d1c29973c5e2bf69c8e94e89f67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0b0d4c04570bfe939843d7cb5bf15f6" id="r_gad0b0d4c04570bfe939843d7cb5bf15f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0b0d4c04570bfe939843d7cb5bf15f6">EXTI_IMR_MR3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gad0b0d4c04570bfe939843d7cb5bf15f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f6badc25c27d6185c0e560454384a90" id="r_ga9f6badc25c27d6185c0e560454384a90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f6badc25c27d6185c0e560454384a90">EXTI_IMR_MR3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad0b0d4c04570bfe939843d7cb5bf15f6">EXTI_IMR_MR3_Pos</a>)</td></tr>
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<tr class="separator:ga9f6badc25c27d6185c0e560454384a90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5edd42f9b2129c18cfa3c3598dcd1134" id="r_ga5edd42f9b2129c18cfa3c3598dcd1134"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5edd42f9b2129c18cfa3c3598dcd1134">EXTI_IMR_MR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f6badc25c27d6185c0e560454384a90">EXTI_IMR_MR3_Msk</a></td></tr>
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<tr class="separator:ga5edd42f9b2129c18cfa3c3598dcd1134"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae18a7ef85db4597309170659c7ff1e6c" id="r_gae18a7ef85db4597309170659c7ff1e6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae18a7ef85db4597309170659c7ff1e6c">EXTI_IMR_MR4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae18a7ef85db4597309170659c7ff1e6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64dbc3def48abe258dd1e1ecce481086" id="r_ga64dbc3def48abe258dd1e1ecce481086"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64dbc3def48abe258dd1e1ecce481086">EXTI_IMR_MR4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae18a7ef85db4597309170659c7ff1e6c">EXTI_IMR_MR4_Pos</a>)</td></tr>
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<tr class="separator:ga64dbc3def48abe258dd1e1ecce481086"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23e920ad334439cd2ad4d683054914e3" id="r_ga23e920ad334439cd2ad4d683054914e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23e920ad334439cd2ad4d683054914e3">EXTI_IMR_MR4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64dbc3def48abe258dd1e1ecce481086">EXTI_IMR_MR4_Msk</a></td></tr>
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<tr class="separator:ga23e920ad334439cd2ad4d683054914e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01f6ecdcfdf234180e99e7d9c02affc7" id="r_ga01f6ecdcfdf234180e99e7d9c02affc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01f6ecdcfdf234180e99e7d9c02affc7">EXTI_IMR_MR5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga01f6ecdcfdf234180e99e7d9c02affc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18ca0d16b43ed78d36f52dd5ab0c21c2" id="r_ga18ca0d16b43ed78d36f52dd5ab0c21c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18ca0d16b43ed78d36f52dd5ab0c21c2">EXTI_IMR_MR5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01f6ecdcfdf234180e99e7d9c02affc7">EXTI_IMR_MR5_Pos</a>)</td></tr>
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<tr class="separator:ga18ca0d16b43ed78d36f52dd5ab0c21c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cd3c5a2e4c4cb9b81e8965fcbf1c3a5" id="r_ga7cd3c5a2e4c4cb9b81e8965fcbf1c3a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cd3c5a2e4c4cb9b81e8965fcbf1c3a5">EXTI_IMR_MR5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga18ca0d16b43ed78d36f52dd5ab0c21c2">EXTI_IMR_MR5_Msk</a></td></tr>
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<tr class="separator:ga7cd3c5a2e4c4cb9b81e8965fcbf1c3a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc6874ec52a6b876dd48842a28d219ba" id="r_gabc6874ec52a6b876dd48842a28d219ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc6874ec52a6b876dd48842a28d219ba">EXTI_IMR_MR6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gabc6874ec52a6b876dd48842a28d219ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6dcc5b70b0a599e944d99f53ac071e1a" id="r_ga6dcc5b70b0a599e944d99f53ac071e1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6dcc5b70b0a599e944d99f53ac071e1a">EXTI_IMR_MR6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc6874ec52a6b876dd48842a28d219ba">EXTI_IMR_MR6_Pos</a>)</td></tr>
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<tr class="separator:ga6dcc5b70b0a599e944d99f53ac071e1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5533c8ec796e3bbc9dc4474376056e06" id="r_ga5533c8ec796e3bbc9dc4474376056e06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5533c8ec796e3bbc9dc4474376056e06">EXTI_IMR_MR6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6dcc5b70b0a599e944d99f53ac071e1a">EXTI_IMR_MR6_Msk</a></td></tr>
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<tr class="separator:ga5533c8ec796e3bbc9dc4474376056e06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1b52dd9408a254ec3ba436ede0e42fa" id="r_gad1b52dd9408a254ec3ba436ede0e42fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1b52dd9408a254ec3ba436ede0e42fa">EXTI_IMR_MR7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gad1b52dd9408a254ec3ba436ede0e42fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae41e117f93d5e426758ee40bd7d45755" id="r_gae41e117f93d5e426758ee40bd7d45755"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae41e117f93d5e426758ee40bd7d45755">EXTI_IMR_MR7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad1b52dd9408a254ec3ba436ede0e42fa">EXTI_IMR_MR7_Pos</a>)</td></tr>
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<tr class="memitem:gab620165d3fea1c564fcf1016805a1a8e" id="r_gab620165d3fea1c564fcf1016805a1a8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab620165d3fea1c564fcf1016805a1a8e">EXTI_IMR_MR7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae41e117f93d5e426758ee40bd7d45755">EXTI_IMR_MR7_Msk</a></td></tr>
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<tr class="separator:gab620165d3fea1c564fcf1016805a1a8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1ad8042623ea52664eb00b43e35dcb7" id="r_gad1ad8042623ea52664eb00b43e35dcb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1ad8042623ea52664eb00b43e35dcb7">EXTI_IMR_MR8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gad1ad8042623ea52664eb00b43e35dcb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02a618dd052d47d30cadf578ee58e416" id="r_ga02a618dd052d47d30cadf578ee58e416"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02a618dd052d47d30cadf578ee58e416">EXTI_IMR_MR8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad1ad8042623ea52664eb00b43e35dcb7">EXTI_IMR_MR8_Pos</a>)</td></tr>
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<tr class="memitem:ga88e8b274e4398fdcb1c68da2b6320d5b" id="r_ga88e8b274e4398fdcb1c68da2b6320d5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88e8b274e4398fdcb1c68da2b6320d5b">EXTI_IMR_MR8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga02a618dd052d47d30cadf578ee58e416">EXTI_IMR_MR8_Msk</a></td></tr>
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<tr class="memitem:ga8b9b5e7500420b3ce5a2b711ed73fa50" id="r_ga8b9b5e7500420b3ce5a2b711ed73fa50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b9b5e7500420b3ce5a2b711ed73fa50">EXTI_IMR_MR9_Pos</a>   (9U)</td></tr>
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<tr class="memitem:ga7433c8c28acd006d4a71e803f6d95de3" id="r_ga7433c8c28acd006d4a71e803f6d95de3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7433c8c28acd006d4a71e803f6d95de3">EXTI_IMR_MR9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b9b5e7500420b3ce5a2b711ed73fa50">EXTI_IMR_MR9_Pos</a>)</td></tr>
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<tr class="memitem:gaf4d177dcf33bb9a34f8590ec509746e8" id="r_gaf4d177dcf33bb9a34f8590ec509746e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4d177dcf33bb9a34f8590ec509746e8">EXTI_IMR_MR9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7433c8c28acd006d4a71e803f6d95de3">EXTI_IMR_MR9_Msk</a></td></tr>
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<tr class="memitem:ga0f8a8f8245716f96dde7049e27435f9a" id="r_ga0f8a8f8245716f96dde7049e27435f9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f8a8f8245716f96dde7049e27435f9a">EXTI_IMR_MR10_Pos</a>   (10U)</td></tr>
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<tr class="memitem:ga530c1c2659363a1edaba4af52c7e6a7d" id="r_ga530c1c2659363a1edaba4af52c7e6a7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga530c1c2659363a1edaba4af52c7e6a7d">EXTI_IMR_MR10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f8a8f8245716f96dde7049e27435f9a">EXTI_IMR_MR10_Pos</a>)</td></tr>
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<tr class="separator:ga530c1c2659363a1edaba4af52c7e6a7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fd7db9a1ce82c152ca7bc6fddf31366" id="r_ga5fd7db9a1ce82c152ca7bc6fddf31366"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fd7db9a1ce82c152ca7bc6fddf31366">EXTI_IMR_MR10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga530c1c2659363a1edaba4af52c7e6a7d">EXTI_IMR_MR10_Msk</a></td></tr>
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<tr class="memitem:ga29cc04d8d5116420b5b63c2f7c6b98e3" id="r_ga29cc04d8d5116420b5b63c2f7c6b98e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29cc04d8d5116420b5b63c2f7c6b98e3">EXTI_IMR_MR11_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga25a00372781fec24bbabb7d2aeca82bd" id="r_ga25a00372781fec24bbabb7d2aeca82bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25a00372781fec24bbabb7d2aeca82bd">EXTI_IMR_MR11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga29cc04d8d5116420b5b63c2f7c6b98e3">EXTI_IMR_MR11_Pos</a>)</td></tr>
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<tr class="memitem:ga68cfe8fe938fcb0fc6925bf493ccfaa7" id="r_ga68cfe8fe938fcb0fc6925bf493ccfaa7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68cfe8fe938fcb0fc6925bf493ccfaa7">EXTI_IMR_MR11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga25a00372781fec24bbabb7d2aeca82bd">EXTI_IMR_MR11_Msk</a></td></tr>
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<tr class="memitem:gaddd5fe4e39d5ff13ad5d3a051ffd2b73" id="r_gaddd5fe4e39d5ff13ad5d3a051ffd2b73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddd5fe4e39d5ff13ad5d3a051ffd2b73">EXTI_IMR_MR12_Pos</a>   (12U)</td></tr>
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<tr class="memitem:ga7c26fd0b40d6d66aec7cc5fff86f6720" id="r_ga7c26fd0b40d6d66aec7cc5fff86f6720"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c26fd0b40d6d66aec7cc5fff86f6720">EXTI_IMR_MR12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaddd5fe4e39d5ff13ad5d3a051ffd2b73">EXTI_IMR_MR12_Pos</a>)</td></tr>
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<tr class="memitem:gad21caf923d2083fb106852493667c16e" id="r_gad21caf923d2083fb106852493667c16e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad21caf923d2083fb106852493667c16e">EXTI_IMR_MR12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c26fd0b40d6d66aec7cc5fff86f6720">EXTI_IMR_MR12_Msk</a></td></tr>
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<tr class="memitem:ga3658584854eb1f7c9ad43934e5cb9f2a" id="r_ga3658584854eb1f7c9ad43934e5cb9f2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3658584854eb1f7c9ad43934e5cb9f2a">EXTI_IMR_MR13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga3658584854eb1f7c9ad43934e5cb9f2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf4095ebf9c75696a62d7bead70cc5cc" id="r_gadf4095ebf9c75696a62d7bead70cc5cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf4095ebf9c75696a62d7bead70cc5cc">EXTI_IMR_MR13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3658584854eb1f7c9ad43934e5cb9f2a">EXTI_IMR_MR13_Pos</a>)</td></tr>
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<tr class="separator:gadf4095ebf9c75696a62d7bead70cc5cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e1938a063c48d7d6504cb32f7965c0e" id="r_ga5e1938a063c48d7d6504cb32f7965c0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e1938a063c48d7d6504cb32f7965c0e">EXTI_IMR_MR13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadf4095ebf9c75696a62d7bead70cc5cc">EXTI_IMR_MR13_Msk</a></td></tr>
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<tr class="separator:ga5e1938a063c48d7d6504cb32f7965c0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05cb292831097d4790e00b89987cf5bb" id="r_ga05cb292831097d4790e00b89987cf5bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05cb292831097d4790e00b89987cf5bb">EXTI_IMR_MR14_Pos</a>   (14U)</td></tr>
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<tr class="memitem:ga052609a42da3b6c6895f006e50c12ab6" id="r_ga052609a42da3b6c6895f006e50c12ab6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga052609a42da3b6c6895f006e50c12ab6">EXTI_IMR_MR14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05cb292831097d4790e00b89987cf5bb">EXTI_IMR_MR14_Pos</a>)</td></tr>
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<tr class="separator:ga052609a42da3b6c6895f006e50c12ab6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8827cee06670f256bc8f6301bea9cab" id="r_gab8827cee06670f256bc8f6301bea9cab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8827cee06670f256bc8f6301bea9cab">EXTI_IMR_MR14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga052609a42da3b6c6895f006e50c12ab6">EXTI_IMR_MR14_Msk</a></td></tr>
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<tr class="memitem:ga84e87a9c94dd2cdf7ea1851c2af7727b" id="r_ga84e87a9c94dd2cdf7ea1851c2af7727b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84e87a9c94dd2cdf7ea1851c2af7727b">EXTI_IMR_MR15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga84e87a9c94dd2cdf7ea1851c2af7727b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27011a5c7488ed0273c821804ef6a27b" id="r_ga27011a5c7488ed0273c821804ef6a27b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27011a5c7488ed0273c821804ef6a27b">EXTI_IMR_MR15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84e87a9c94dd2cdf7ea1851c2af7727b">EXTI_IMR_MR15_Pos</a>)</td></tr>
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<tr class="memitem:ga88d9990be7f8f9e530a9f930a365fa44" id="r_ga88d9990be7f8f9e530a9f930a365fa44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88d9990be7f8f9e530a9f930a365fa44">EXTI_IMR_MR15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga27011a5c7488ed0273c821804ef6a27b">EXTI_IMR_MR15_Msk</a></td></tr>
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<tr class="separator:ga88d9990be7f8f9e530a9f930a365fa44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6fc8dc837cd6326f1fb7fae42e56ef74" id="r_ga6fc8dc837cd6326f1fb7fae42e56ef74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fc8dc837cd6326f1fb7fae42e56ef74">EXTI_IMR_MR16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga6fc8dc837cd6326f1fb7fae42e56ef74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga155179198c3735dd1e35baf733f1542e" id="r_ga155179198c3735dd1e35baf733f1542e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga155179198c3735dd1e35baf733f1542e">EXTI_IMR_MR16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6fc8dc837cd6326f1fb7fae42e56ef74">EXTI_IMR_MR16_Pos</a>)</td></tr>
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<tr class="separator:ga155179198c3735dd1e35baf733f1542e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7419f78ed9044bdd237b452ef49e1b7f" id="r_ga7419f78ed9044bdd237b452ef49e1b7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7419f78ed9044bdd237b452ef49e1b7f">EXTI_IMR_MR16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga155179198c3735dd1e35baf733f1542e">EXTI_IMR_MR16_Msk</a></td></tr>
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<tr class="memitem:gabbc90bbbbc4137c8af29df2fc0162ae5" id="r_gabbc90bbbbc4137c8af29df2fc0162ae5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbc90bbbbc4137c8af29df2fc0162ae5">EXTI_IMR_MR17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gabbc90bbbbc4137c8af29df2fc0162ae5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6eb3bf08d4a51133e62dd719f2e48b8" id="r_gad6eb3bf08d4a51133e62dd719f2e48b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6eb3bf08d4a51133e62dd719f2e48b8">EXTI_IMR_MR17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabbc90bbbbc4137c8af29df2fc0162ae5">EXTI_IMR_MR17_Pos</a>)</td></tr>
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<tr class="separator:gad6eb3bf08d4a51133e62dd719f2e48b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4489fa85d1552b8f40faed93483a5d35" id="r_ga4489fa85d1552b8f40faed93483a5d35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4489fa85d1552b8f40faed93483a5d35">EXTI_IMR_MR17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad6eb3bf08d4a51133e62dd719f2e48b8">EXTI_IMR_MR17_Msk</a></td></tr>
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<tr class="separator:ga4489fa85d1552b8f40faed93483a5d35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9084142db0eac80226038ced74846aa8" id="r_ga9084142db0eac80226038ced74846aa8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9084142db0eac80226038ced74846aa8">EXTI_IMR_MR18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga9084142db0eac80226038ced74846aa8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52a2709f4f9d2ccb8d63c36958517b26" id="r_ga52a2709f4f9d2ccb8d63c36958517b26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52a2709f4f9d2ccb8d63c36958517b26">EXTI_IMR_MR18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9084142db0eac80226038ced74846aa8">EXTI_IMR_MR18_Pos</a>)</td></tr>
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<tr class="memitem:ga05e16f2cda40cca58a45458cc44d510f" id="r_ga05e16f2cda40cca58a45458cc44d510f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05e16f2cda40cca58a45458cc44d510f">EXTI_IMR_MR18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga52a2709f4f9d2ccb8d63c36958517b26">EXTI_IMR_MR18_Msk</a></td></tr>
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<tr class="separator:ga05e16f2cda40cca58a45458cc44d510f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92d1beae3a87cd1515fd1104bb2e0ac5" id="r_ga92d1beae3a87cd1515fd1104bb2e0ac5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92d1beae3a87cd1515fd1104bb2e0ac5">EXTI_IMR_MR19_Pos</a>   (19U)</td></tr>
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<tr class="memitem:gab55fbb64891a3120b3d5c53984abe6ca" id="r_gab55fbb64891a3120b3d5c53984abe6ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab55fbb64891a3120b3d5c53984abe6ca">EXTI_IMR_MR19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92d1beae3a87cd1515fd1104bb2e0ac5">EXTI_IMR_MR19_Pos</a>)</td></tr>
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<tr class="memitem:gad47f7a023cbba165dfb95845d3c8c55c" id="r_gad47f7a023cbba165dfb95845d3c8c55c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad47f7a023cbba165dfb95845d3c8c55c">EXTI_IMR_MR19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab55fbb64891a3120b3d5c53984abe6ca">EXTI_IMR_MR19_Msk</a></td></tr>
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<tr class="separator:gad47f7a023cbba165dfb95845d3c8c55c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8a252b7afd91a453cd613fca4792aed" id="r_gae8a252b7afd91a453cd613fca4792aed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8a252b7afd91a453cd613fca4792aed">EXTI_IMR_MR20_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga8e9bb3e1445d27d46816b0be57cbfbbd" id="r_ga8e9bb3e1445d27d46816b0be57cbfbbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e9bb3e1445d27d46816b0be57cbfbbd">EXTI_IMR_MR20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae8a252b7afd91a453cd613fca4792aed">EXTI_IMR_MR20_Pos</a>)</td></tr>
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<tr class="separator:ga8e9bb3e1445d27d46816b0be57cbfbbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4aee679baf5820e1666b60e48a64cafa" id="r_ga4aee679baf5820e1666b60e48a64cafa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4aee679baf5820e1666b60e48a64cafa">EXTI_IMR_MR20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e9bb3e1445d27d46816b0be57cbfbbd">EXTI_IMR_MR20_Msk</a></td></tr>
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<tr class="memitem:ga777cbe130041b394e728de96fac11175" id="r_ga777cbe130041b394e728de96fac11175"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga777cbe130041b394e728de96fac11175">EXTI_IMR_MR21_Pos</a>   (21U)</td></tr>
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<tr class="memitem:gae66e025fa607e21af5498613c7ec7ebf" id="r_gae66e025fa607e21af5498613c7ec7ebf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae66e025fa607e21af5498613c7ec7ebf">EXTI_IMR_MR21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga777cbe130041b394e728de96fac11175">EXTI_IMR_MR21_Pos</a>)</td></tr>
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<tr class="memitem:ga3cc7e64c45d273ca7396ac1e0ce38c36" id="r_ga3cc7e64c45d273ca7396ac1e0ce38c36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cc7e64c45d273ca7396ac1e0ce38c36">EXTI_IMR_MR21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae66e025fa607e21af5498613c7ec7ebf">EXTI_IMR_MR21_Msk</a></td></tr>
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<tr class="separator:ga3cc7e64c45d273ca7396ac1e0ce38c36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83efcf05bd49c293779334f366a3e342" id="r_ga83efcf05bd49c293779334f366a3e342"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83efcf05bd49c293779334f366a3e342">EXTI_IMR_MR22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga83efcf05bd49c293779334f366a3e342"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20c62ffabf9a216bc5d682fc0f1ad5f6" id="r_ga20c62ffabf9a216bc5d682fc0f1ad5f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20c62ffabf9a216bc5d682fc0f1ad5f6">EXTI_IMR_MR22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83efcf05bd49c293779334f366a3e342">EXTI_IMR_MR22_Pos</a>)</td></tr>
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<tr class="separator:ga20c62ffabf9a216bc5d682fc0f1ad5f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2aec84941d816be18a1607b6ee25acb1" id="r_ga2aec84941d816be18a1607b6ee25acb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2aec84941d816be18a1607b6ee25acb1">EXTI_IMR_MR22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga20c62ffabf9a216bc5d682fc0f1ad5f6">EXTI_IMR_MR22_Msk</a></td></tr>
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<tr class="separator:ga2aec84941d816be18a1607b6ee25acb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae43e6abdba2e7d7b7eaa07b268f288b3" id="r_gae43e6abdba2e7d7b7eaa07b268f288b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae43e6abdba2e7d7b7eaa07b268f288b3">EXTI_IMR_IM0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad03b2ba6cde99065627fccabd54ac097">EXTI_IMR_MR0</a></td></tr>
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<tr class="memitem:ga1498c6a9cb8eb9842b83a2e91b3c290d" id="r_ga1498c6a9cb8eb9842b83a2e91b3c290d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1498c6a9cb8eb9842b83a2e91b3c290d">EXTI_IMR_IM1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaaf3f9a86c620149893db38c83f8ba58">EXTI_IMR_MR1</a></td></tr>
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<tr class="separator:ga1498c6a9cb8eb9842b83a2e91b3c290d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10013221a5de01374bb63623ca68d5a5" id="r_ga10013221a5de01374bb63623ca68d5a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10013221a5de01374bb63623ca68d5a5">EXTI_IMR_IM2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71604d1c29973c5e2bf69c8e94e89f67">EXTI_IMR_MR2</a></td></tr>
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<tr class="memitem:ga7a7e8e899926ae962ae34dc9d143fd09" id="r_ga7a7e8e899926ae962ae34dc9d143fd09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a7e8e899926ae962ae34dc9d143fd09">EXTI_IMR_IM3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5edd42f9b2129c18cfa3c3598dcd1134">EXTI_IMR_MR3</a></td></tr>
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<tr class="separator:ga7a7e8e899926ae962ae34dc9d143fd09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadad3c244ed0a107b5c4f96470a914348" id="r_gadad3c244ed0a107b5c4f96470a914348"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadad3c244ed0a107b5c4f96470a914348">EXTI_IMR_IM4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga23e920ad334439cd2ad4d683054914e3">EXTI_IMR_MR4</a></td></tr>
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<tr class="memitem:ga91070bca3731cbe48e7bc97de97631a5" id="r_ga91070bca3731cbe48e7bc97de97631a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91070bca3731cbe48e7bc97de97631a5">EXTI_IMR_IM5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cd3c5a2e4c4cb9b81e8965fcbf1c3a5">EXTI_IMR_MR5</a></td></tr>
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<tr class="separator:ga91070bca3731cbe48e7bc97de97631a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ab55682980062f57cdb981aa649fbf3" id="r_ga2ab55682980062f57cdb981aa649fbf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ab55682980062f57cdb981aa649fbf3">EXTI_IMR_IM6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5533c8ec796e3bbc9dc4474376056e06">EXTI_IMR_MR6</a></td></tr>
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<tr class="memitem:gabd6ee214b24d450efe0c52d0b1dae0f4" id="r_gabd6ee214b24d450efe0c52d0b1dae0f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd6ee214b24d450efe0c52d0b1dae0f4">EXTI_IMR_IM7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab620165d3fea1c564fcf1016805a1a8e">EXTI_IMR_MR7</a></td></tr>
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<tr class="memitem:gacc41defd6bd026adde49d44ad1e8a5c4" id="r_gacc41defd6bd026adde49d44ad1e8a5c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc41defd6bd026adde49d44ad1e8a5c4">EXTI_IMR_IM8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga88e8b274e4398fdcb1c68da2b6320d5b">EXTI_IMR_MR8</a></td></tr>
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<tr class="memitem:ga0a43b1d5d7f5dabbc44b03bdab7a6c3e" id="r_ga0a43b1d5d7f5dabbc44b03bdab7a6c3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a43b1d5d7f5dabbc44b03bdab7a6c3e">EXTI_IMR_IM9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4d177dcf33bb9a34f8590ec509746e8">EXTI_IMR_MR9</a></td></tr>
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<tr class="separator:ga0a43b1d5d7f5dabbc44b03bdab7a6c3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e31c6dd167542dc8660c7dd6f31e0e9" id="r_ga6e31c6dd167542dc8660c7dd6f31e0e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e31c6dd167542dc8660c7dd6f31e0e9">EXTI_IMR_IM10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fd7db9a1ce82c152ca7bc6fddf31366">EXTI_IMR_MR10</a></td></tr>
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<tr class="separator:ga6e31c6dd167542dc8660c7dd6f31e0e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5441a9f074c104d67a7629467724f3a0" id="r_ga5441a9f074c104d67a7629467724f3a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5441a9f074c104d67a7629467724f3a0">EXTI_IMR_IM11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga68cfe8fe938fcb0fc6925bf493ccfaa7">EXTI_IMR_MR11</a></td></tr>
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<tr class="memitem:gab736b78d54e4ae9b5f1ee0bebbda1e4d" id="r_gab736b78d54e4ae9b5f1ee0bebbda1e4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab736b78d54e4ae9b5f1ee0bebbda1e4d">EXTI_IMR_IM12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad21caf923d2083fb106852493667c16e">EXTI_IMR_MR12</a></td></tr>
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<tr class="memitem:ga1b835eee91599273c334d6bed80bdaca" id="r_ga1b835eee91599273c334d6bed80bdaca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b835eee91599273c334d6bed80bdaca">EXTI_IMR_IM13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e1938a063c48d7d6504cb32f7965c0e">EXTI_IMR_MR13</a></td></tr>
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<tr class="memitem:ga933e1e28d08958b9800cbfbea953b9e6" id="r_ga933e1e28d08958b9800cbfbea953b9e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga933e1e28d08958b9800cbfbea953b9e6">EXTI_IMR_IM14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab8827cee06670f256bc8f6301bea9cab">EXTI_IMR_MR14</a></td></tr>
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<tr class="memitem:ga16ac63565a42896a10eb5b56d45df7f1" id="r_ga16ac63565a42896a10eb5b56d45df7f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16ac63565a42896a10eb5b56d45df7f1">EXTI_IMR_IM15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga88d9990be7f8f9e530a9f930a365fa44">EXTI_IMR_MR15</a></td></tr>
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<tr class="separator:ga16ac63565a42896a10eb5b56d45df7f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33e28d73aacdcc55491fe44c2e840398" id="r_ga33e28d73aacdcc55491fe44c2e840398"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33e28d73aacdcc55491fe44c2e840398">EXTI_IMR_IM16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7419f78ed9044bdd237b452ef49e1b7f">EXTI_IMR_MR16</a></td></tr>
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<tr class="memitem:ga0db46755679e595721057e90574b1434" id="r_ga0db46755679e595721057e90574b1434"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0db46755679e595721057e90574b1434">EXTI_IMR_IM17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4489fa85d1552b8f40faed93483a5d35">EXTI_IMR_MR17</a></td></tr>
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<tr class="memitem:ga0f0a2063e564c44ba51733e0fcf25745" id="r_ga0f0a2063e564c44ba51733e0fcf25745"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f0a2063e564c44ba51733e0fcf25745">EXTI_IMR_IM18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga05e16f2cda40cca58a45458cc44d510f">EXTI_IMR_MR18</a></td></tr>
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<tr class="memitem:ga8cc8bc70fd30f54311218abe6c52c21c" id="r_ga8cc8bc70fd30f54311218abe6c52c21c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cc8bc70fd30f54311218abe6c52c21c">EXTI_IMR_IM19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad47f7a023cbba165dfb95845d3c8c55c">EXTI_IMR_MR19</a></td></tr>
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<tr class="memitem:ga8ec4f917392fcd3b64bfae4d17fe1808" id="r_ga8ec4f917392fcd3b64bfae4d17fe1808"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ec4f917392fcd3b64bfae4d17fe1808">EXTI_IMR_IM20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4aee679baf5820e1666b60e48a64cafa">EXTI_IMR_MR20</a></td></tr>
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<tr class="memitem:ga9539fd6427a262f7cdbd42cd68a10eca" id="r_ga9539fd6427a262f7cdbd42cd68a10eca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9539fd6427a262f7cdbd42cd68a10eca">EXTI_IMR_IM21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cc7e64c45d273ca7396ac1e0ce38c36">EXTI_IMR_MR21</a></td></tr>
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<tr class="memitem:gab05cb948001efcf6d1cf4968160f3aa5" id="r_gab05cb948001efcf6d1cf4968160f3aa5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab05cb948001efcf6d1cf4968160f3aa5">EXTI_IMR_IM22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2aec84941d816be18a1607b6ee25acb1">EXTI_IMR_MR22</a></td></tr>
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<tr class="memitem:ga1fe01103a449e5f81a25c733a3c1a03c" id="r_ga1fe01103a449e5f81a25c733a3c1a03c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fe01103a449e5f81a25c733a3c1a03c">EXTI_IMR_IM_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga06eeb49b799d40a72140618195e6a55d" id="r_ga06eeb49b799d40a72140618195e6a55d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06eeb49b799d40a72140618195e6a55d">EXTI_IMR_IM_Msk</a>   (0x7FFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fe01103a449e5f81a25c733a3c1a03c">EXTI_IMR_IM_Pos</a>)</td></tr>
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<tr class="separator:ga06eeb49b799d40a72140618195e6a55d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4f23236f2d0bb9ed886556064714c50" id="r_gae4f23236f2d0bb9ed886556064714c50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4f23236f2d0bb9ed886556064714c50">EXTI_IMR_IM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06eeb49b799d40a72140618195e6a55d">EXTI_IMR_IM_Msk</a></td></tr>
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<tr class="separator:gae4f23236f2d0bb9ed886556064714c50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf10ad3eba24a4fadc9e58e9b81c17494" id="r_gaf10ad3eba24a4fadc9e58e9b81c17494"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf10ad3eba24a4fadc9e58e9b81c17494">EXTI_EMR_MR0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf10ad3eba24a4fadc9e58e9b81c17494"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga016c23b6c1164758878753e14201fdbc" id="r_ga016c23b6c1164758878753e14201fdbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga016c23b6c1164758878753e14201fdbc">EXTI_EMR_MR0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf10ad3eba24a4fadc9e58e9b81c17494">EXTI_EMR_MR0_Pos</a>)</td></tr>
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<tr class="memitem:ga515c0dc6d2472e06a89e4bb19725e8f3" id="r_ga515c0dc6d2472e06a89e4bb19725e8f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga515c0dc6d2472e06a89e4bb19725e8f3">EXTI_EMR_MR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga016c23b6c1164758878753e14201fdbc">EXTI_EMR_MR0_Msk</a></td></tr>
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<tr class="memitem:gab2891b4a57f827defecd2ebb2cac457b" id="r_gab2891b4a57f827defecd2ebb2cac457b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2891b4a57f827defecd2ebb2cac457b">EXTI_EMR_MR1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gab2891b4a57f827defecd2ebb2cac457b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa419f81a443fd7eac16ac340c971dc63" id="r_gaa419f81a443fd7eac16ac340c971dc63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa419f81a443fd7eac16ac340c971dc63">EXTI_EMR_MR1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab2891b4a57f827defecd2ebb2cac457b">EXTI_EMR_MR1_Pos</a>)</td></tr>
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<tr class="separator:gaa419f81a443fd7eac16ac340c971dc63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d88e7c10e5985fa425ea7ab4fe4c3e5" id="r_ga6d88e7c10e5985fa425ea7ab4fe4c3e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d88e7c10e5985fa425ea7ab4fe4c3e5">EXTI_EMR_MR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa419f81a443fd7eac16ac340c971dc63">EXTI_EMR_MR1_Msk</a></td></tr>
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<tr class="separator:ga6d88e7c10e5985fa425ea7ab4fe4c3e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09e8782d37f1f13cc30d86c2c3a02576" id="r_ga09e8782d37f1f13cc30d86c2c3a02576"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09e8782d37f1f13cc30d86c2c3a02576">EXTI_EMR_MR2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga09e8782d37f1f13cc30d86c2c3a02576"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga546cba14a3e8a8172d5652e670ac9ed3" id="r_ga546cba14a3e8a8172d5652e670ac9ed3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga546cba14a3e8a8172d5652e670ac9ed3">EXTI_EMR_MR2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga09e8782d37f1f13cc30d86c2c3a02576">EXTI_EMR_MR2_Pos</a>)</td></tr>
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<tr class="separator:ga546cba14a3e8a8172d5652e670ac9ed3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga460d5d4c0b53bcc04d5804e1204ded21" id="r_ga460d5d4c0b53bcc04d5804e1204ded21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga460d5d4c0b53bcc04d5804e1204ded21">EXTI_EMR_MR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga546cba14a3e8a8172d5652e670ac9ed3">EXTI_EMR_MR2_Msk</a></td></tr>
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<tr class="separator:ga460d5d4c0b53bcc04d5804e1204ded21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeac760511bc46050ceb4ece479ead54b" id="r_gaeac760511bc46050ceb4ece479ead54b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeac760511bc46050ceb4ece479ead54b">EXTI_EMR_MR3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaeac760511bc46050ceb4ece479ead54b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14290334e49a34a93a3ce229bd5ecf74" id="r_ga14290334e49a34a93a3ce229bd5ecf74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14290334e49a34a93a3ce229bd5ecf74">EXTI_EMR_MR3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeac760511bc46050ceb4ece479ead54b">EXTI_EMR_MR3_Pos</a>)</td></tr>
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<tr class="separator:ga14290334e49a34a93a3ce229bd5ecf74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73944983ce5a6bde9dc172b4f483898c" id="r_ga73944983ce5a6bde9dc172b4f483898c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73944983ce5a6bde9dc172b4f483898c">EXTI_EMR_MR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga14290334e49a34a93a3ce229bd5ecf74">EXTI_EMR_MR3_Msk</a></td></tr>
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<tr class="separator:ga73944983ce5a6bde9dc172b4f483898c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a337713821f1ea29a953eee7a2a6d2f" id="r_ga4a337713821f1ea29a953eee7a2a6d2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a337713821f1ea29a953eee7a2a6d2f">EXTI_EMR_MR4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga4a337713821f1ea29a953eee7a2a6d2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga478ee1f30cf0d4ef71d512507fcb9cb7" id="r_ga478ee1f30cf0d4ef71d512507fcb9cb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga478ee1f30cf0d4ef71d512507fcb9cb7">EXTI_EMR_MR4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a337713821f1ea29a953eee7a2a6d2f">EXTI_EMR_MR4_Pos</a>)</td></tr>
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<tr class="separator:ga478ee1f30cf0d4ef71d512507fcb9cb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab80f809ead83e747677a31c80c6aae03" id="r_gab80f809ead83e747677a31c80c6aae03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab80f809ead83e747677a31c80c6aae03">EXTI_EMR_MR4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga478ee1f30cf0d4ef71d512507fcb9cb7">EXTI_EMR_MR4_Msk</a></td></tr>
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<tr class="separator:gab80f809ead83e747677a31c80c6aae03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79e7760224986ab31fc06f5d84aa3b7f" id="r_ga79e7760224986ab31fc06f5d84aa3b7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79e7760224986ab31fc06f5d84aa3b7f">EXTI_EMR_MR5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga79e7760224986ab31fc06f5d84aa3b7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e60a767b0307626c3cd4cbd01d10304" id="r_ga3e60a767b0307626c3cd4cbd01d10304"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e60a767b0307626c3cd4cbd01d10304">EXTI_EMR_MR5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga79e7760224986ab31fc06f5d84aa3b7f">EXTI_EMR_MR5_Pos</a>)</td></tr>
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<tr class="separator:ga3e60a767b0307626c3cd4cbd01d10304"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65976f75b703f740dea3562ba3b8db59" id="r_ga65976f75b703f740dea3562ba3b8db59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65976f75b703f740dea3562ba3b8db59">EXTI_EMR_MR5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e60a767b0307626c3cd4cbd01d10304">EXTI_EMR_MR5_Msk</a></td></tr>
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<tr class="separator:ga65976f75b703f740dea3562ba3b8db59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3210ae740c584799c07b1e7995e4252" id="r_gaf3210ae740c584799c07b1e7995e4252"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3210ae740c584799c07b1e7995e4252">EXTI_EMR_MR6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaf3210ae740c584799c07b1e7995e4252"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ca40f93d86d921adecd19479b7ab5c6" id="r_ga9ca40f93d86d921adecd19479b7ab5c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ca40f93d86d921adecd19479b7ab5c6">EXTI_EMR_MR6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3210ae740c584799c07b1e7995e4252">EXTI_EMR_MR6_Pos</a>)</td></tr>
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<tr class="separator:ga9ca40f93d86d921adecd19479b7ab5c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea480bd932cd1fa0904f5eb1caee9a12" id="r_gaea480bd932cd1fa0904f5eb1caee9a12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea480bd932cd1fa0904f5eb1caee9a12">EXTI_EMR_MR6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ca40f93d86d921adecd19479b7ab5c6">EXTI_EMR_MR6_Msk</a></td></tr>
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<tr class="separator:gaea480bd932cd1fa0904f5eb1caee9a12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafafbf203c2dae41123f2eaf6565bb2f4" id="r_gafafbf203c2dae41123f2eaf6565bb2f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafafbf203c2dae41123f2eaf6565bb2f4">EXTI_EMR_MR7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gafafbf203c2dae41123f2eaf6565bb2f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace6755a5d4b361648f0b2c76a0b32282" id="r_gace6755a5d4b361648f0b2c76a0b32282"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace6755a5d4b361648f0b2c76a0b32282">EXTI_EMR_MR7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafafbf203c2dae41123f2eaf6565bb2f4">EXTI_EMR_MR7_Pos</a>)</td></tr>
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<tr class="separator:gace6755a5d4b361648f0b2c76a0b32282"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbb27ff8664928994ef96f87052d14be" id="r_gadbb27ff8664928994ef96f87052d14be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbb27ff8664928994ef96f87052d14be">EXTI_EMR_MR7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gace6755a5d4b361648f0b2c76a0b32282">EXTI_EMR_MR7_Msk</a></td></tr>
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<tr class="separator:gadbb27ff8664928994ef96f87052d14be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3349563ae0947ec6c441fe912fb0ede" id="r_gae3349563ae0947ec6c441fe912fb0ede"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3349563ae0947ec6c441fe912fb0ede">EXTI_EMR_MR8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gae3349563ae0947ec6c441fe912fb0ede"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00700896523030015c081b6caa3b72b5" id="r_ga00700896523030015c081b6caa3b72b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00700896523030015c081b6caa3b72b5">EXTI_EMR_MR8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3349563ae0947ec6c441fe912fb0ede">EXTI_EMR_MR8_Pos</a>)</td></tr>
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<tr class="separator:ga00700896523030015c081b6caa3b72b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ed4b371da871ffd0cc12ee00147282f" id="r_ga4ed4b371da871ffd0cc12ee00147282f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ed4b371da871ffd0cc12ee00147282f">EXTI_EMR_MR8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga00700896523030015c081b6caa3b72b5">EXTI_EMR_MR8_Msk</a></td></tr>
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<tr class="memitem:gac42d64759efd55a329c207a31c7e3033" id="r_gac42d64759efd55a329c207a31c7e3033"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac42d64759efd55a329c207a31c7e3033">EXTI_EMR_MR9_Pos</a>   (9U)</td></tr>
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<tr class="memitem:ga47c54d6a078dcc8b9aec22e327785fdd" id="r_ga47c54d6a078dcc8b9aec22e327785fdd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47c54d6a078dcc8b9aec22e327785fdd">EXTI_EMR_MR9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac42d64759efd55a329c207a31c7e3033">EXTI_EMR_MR9_Pos</a>)</td></tr>
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<tr class="separator:ga47c54d6a078dcc8b9aec22e327785fdd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga109af342179fff1fccfdde582834867a" id="r_ga109af342179fff1fccfdde582834867a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga109af342179fff1fccfdde582834867a">EXTI_EMR_MR9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47c54d6a078dcc8b9aec22e327785fdd">EXTI_EMR_MR9_Msk</a></td></tr>
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<tr class="separator:ga109af342179fff1fccfdde582834867a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaead96297678ea28e56765731de3f8511" id="r_gaead96297678ea28e56765731de3f8511"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaead96297678ea28e56765731de3f8511">EXTI_EMR_MR10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaead96297678ea28e56765731de3f8511"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ef7af204b6807cb09f10a11f774889e" id="r_ga3ef7af204b6807cb09f10a11f774889e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ef7af204b6807cb09f10a11f774889e">EXTI_EMR_MR10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaead96297678ea28e56765731de3f8511">EXTI_EMR_MR10_Pos</a>)</td></tr>
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<tr class="memitem:gaf342d34ed1b8e4aa916bf49e30c2a234" id="r_gaf342d34ed1b8e4aa916bf49e30c2a234"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf342d34ed1b8e4aa916bf49e30c2a234">EXTI_EMR_MR10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ef7af204b6807cb09f10a11f774889e">EXTI_EMR_MR10_Msk</a></td></tr>
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<tr class="separator:gaf342d34ed1b8e4aa916bf49e30c2a234"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga744443e18392efb9d31ceeabc2ba9786" id="r_ga744443e18392efb9d31ceeabc2ba9786"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga744443e18392efb9d31ceeabc2ba9786">EXTI_EMR_MR11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga744443e18392efb9d31ceeabc2ba9786"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb1a0c32eb56c845232f07d6e1498633" id="r_gabb1a0c32eb56c845232f07d6e1498633"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb1a0c32eb56c845232f07d6e1498633">EXTI_EMR_MR11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga744443e18392efb9d31ceeabc2ba9786">EXTI_EMR_MR11_Pos</a>)</td></tr>
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<tr class="separator:gabb1a0c32eb56c845232f07d6e1498633"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ec516af1de770c82c3c9c458cbc0172" id="r_ga9ec516af1de770c82c3c9c458cbc0172"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ec516af1de770c82c3c9c458cbc0172">EXTI_EMR_MR11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabb1a0c32eb56c845232f07d6e1498633">EXTI_EMR_MR11_Msk</a></td></tr>
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<tr class="separator:ga9ec516af1de770c82c3c9c458cbc0172"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdf200c3d4abdc44356ff3bfc66c136e" id="r_gacdf200c3d4abdc44356ff3bfc66c136e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdf200c3d4abdc44356ff3bfc66c136e">EXTI_EMR_MR12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gacdf200c3d4abdc44356ff3bfc66c136e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga988ba6ff638ee9d2bc8a2dec8ef8ea32" id="r_ga988ba6ff638ee9d2bc8a2dec8ef8ea32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga988ba6ff638ee9d2bc8a2dec8ef8ea32">EXTI_EMR_MR12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacdf200c3d4abdc44356ff3bfc66c136e">EXTI_EMR_MR12_Pos</a>)</td></tr>
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<tr class="separator:ga988ba6ff638ee9d2bc8a2dec8ef8ea32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15732553e5b0de9f58180a0b024d4cad" id="r_ga15732553e5b0de9f58180a0b024d4cad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15732553e5b0de9f58180a0b024d4cad">EXTI_EMR_MR12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga988ba6ff638ee9d2bc8a2dec8ef8ea32">EXTI_EMR_MR12_Msk</a></td></tr>
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<tr class="separator:ga15732553e5b0de9f58180a0b024d4cad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacf17cbe9663809770d498fe8d28a6e5" id="r_gaacf17cbe9663809770d498fe8d28a6e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacf17cbe9663809770d498fe8d28a6e5">EXTI_EMR_MR13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaacf17cbe9663809770d498fe8d28a6e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06991d09dc3fd7373da2375b7e196452" id="r_ga06991d09dc3fd7373da2375b7e196452"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06991d09dc3fd7373da2375b7e196452">EXTI_EMR_MR13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaacf17cbe9663809770d498fe8d28a6e5">EXTI_EMR_MR13_Pos</a>)</td></tr>
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<tr class="memitem:ga9fd2ec6472e46869956acb28f5e1b55f" id="r_ga9fd2ec6472e46869956acb28f5e1b55f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fd2ec6472e46869956acb28f5e1b55f">EXTI_EMR_MR13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06991d09dc3fd7373da2375b7e196452">EXTI_EMR_MR13_Msk</a></td></tr>
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<tr class="separator:ga9fd2ec6472e46869956acb28f5e1b55f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0dd6f7d71f00964f930cba3e7fc9d14" id="r_gae0dd6f7d71f00964f930cba3e7fc9d14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0dd6f7d71f00964f930cba3e7fc9d14">EXTI_EMR_MR14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gae0dd6f7d71f00964f930cba3e7fc9d14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56cd35406916f89cc00f5c4c153f7f3b" id="r_ga56cd35406916f89cc00f5c4c153f7f3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56cd35406916f89cc00f5c4c153f7f3b">EXTI_EMR_MR14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae0dd6f7d71f00964f930cba3e7fc9d14">EXTI_EMR_MR14_Pos</a>)</td></tr>
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<tr class="separator:ga56cd35406916f89cc00f5c4c153f7f3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaecf5890ea71eea034ec1cd9e96284f89" id="r_gaecf5890ea71eea034ec1cd9e96284f89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecf5890ea71eea034ec1cd9e96284f89">EXTI_EMR_MR14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga56cd35406916f89cc00f5c4c153f7f3b">EXTI_EMR_MR14_Msk</a></td></tr>
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<tr class="separator:gaecf5890ea71eea034ec1cd9e96284f89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ee0004caa46c2946bb05305cd93baa1" id="r_ga4ee0004caa46c2946bb05305cd93baa1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ee0004caa46c2946bb05305cd93baa1">EXTI_EMR_MR15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga4ee0004caa46c2946bb05305cd93baa1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa1778406979e6566a10b085f1146a28" id="r_gaaa1778406979e6566a10b085f1146a28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa1778406979e6566a10b085f1146a28">EXTI_EMR_MR15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ee0004caa46c2946bb05305cd93baa1">EXTI_EMR_MR15_Pos</a>)</td></tr>
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<tr class="separator:gaaa1778406979e6566a10b085f1146a28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a7bacc32351a36aefcd5614abc76ae3" id="r_ga7a7bacc32351a36aefcd5614abc76ae3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a7bacc32351a36aefcd5614abc76ae3">EXTI_EMR_MR15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa1778406979e6566a10b085f1146a28">EXTI_EMR_MR15_Msk</a></td></tr>
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<tr class="separator:ga7a7bacc32351a36aefcd5614abc76ae3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga112b3657ea27bac2cfe0676dfa893157" id="r_ga112b3657ea27bac2cfe0676dfa893157"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga112b3657ea27bac2cfe0676dfa893157">EXTI_EMR_MR16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga112b3657ea27bac2cfe0676dfa893157"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cb43eaaa268ddc9d407c5edcfb05ff4" id="r_ga3cb43eaaa268ddc9d407c5edcfb05ff4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cb43eaaa268ddc9d407c5edcfb05ff4">EXTI_EMR_MR16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga112b3657ea27bac2cfe0676dfa893157">EXTI_EMR_MR16_Pos</a>)</td></tr>
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<tr class="separator:ga3cb43eaaa268ddc9d407c5edcfb05ff4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34b1a6934265da759bc061f73d5d1374" id="r_ga34b1a6934265da759bc061f73d5d1374"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34b1a6934265da759bc061f73d5d1374">EXTI_EMR_MR16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cb43eaaa268ddc9d407c5edcfb05ff4">EXTI_EMR_MR16_Msk</a></td></tr>
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<tr class="separator:ga34b1a6934265da759bc061f73d5d1374"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad853ef0d4af0ed5b68581464a067e1ab" id="r_gad853ef0d4af0ed5b68581464a067e1ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad853ef0d4af0ed5b68581464a067e1ab">EXTI_EMR_MR17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gad853ef0d4af0ed5b68581464a067e1ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga889175528233c464f6c0a5f8a901a06d" id="r_ga889175528233c464f6c0a5f8a901a06d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga889175528233c464f6c0a5f8a901a06d">EXTI_EMR_MR17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad853ef0d4af0ed5b68581464a067e1ab">EXTI_EMR_MR17_Pos</a>)</td></tr>
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<tr class="separator:ga889175528233c464f6c0a5f8a901a06d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a30aa20cf475eecf7e15171e83035e4" id="r_ga6a30aa20cf475eecf7e15171e83035e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a30aa20cf475eecf7e15171e83035e4">EXTI_EMR_MR17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga889175528233c464f6c0a5f8a901a06d">EXTI_EMR_MR17_Msk</a></td></tr>
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<tr class="separator:ga6a30aa20cf475eecf7e15171e83035e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7edb364e6ab767686e3c40b177489f00" id="r_ga7edb364e6ab767686e3c40b177489f00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7edb364e6ab767686e3c40b177489f00">EXTI_EMR_MR18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga7edb364e6ab767686e3c40b177489f00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e6e89686fa4e8fe58365b684331f398" id="r_ga3e6e89686fa4e8fe58365b684331f398"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e6e89686fa4e8fe58365b684331f398">EXTI_EMR_MR18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7edb364e6ab767686e3c40b177489f00">EXTI_EMR_MR18_Pos</a>)</td></tr>
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<tr class="separator:ga3e6e89686fa4e8fe58365b684331f398"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25eee729b57b4c78a0613c184fc539e5" id="r_ga25eee729b57b4c78a0613c184fc539e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25eee729b57b4c78a0613c184fc539e5">EXTI_EMR_MR18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e6e89686fa4e8fe58365b684331f398">EXTI_EMR_MR18_Msk</a></td></tr>
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<tr class="separator:ga25eee729b57b4c78a0613c184fc539e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8990f832c2588cb200a51d52c5dc8c8a" id="r_ga8990f832c2588cb200a51d52c5dc8c8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8990f832c2588cb200a51d52c5dc8c8a">EXTI_EMR_MR19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga8990f832c2588cb200a51d52c5dc8c8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga514f26dc55f8e37ec8ac8bef9dfcadd4" id="r_ga514f26dc55f8e37ec8ac8bef9dfcadd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga514f26dc55f8e37ec8ac8bef9dfcadd4">EXTI_EMR_MR19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8990f832c2588cb200a51d52c5dc8c8a">EXTI_EMR_MR19_Pos</a>)</td></tr>
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<tr class="separator:ga514f26dc55f8e37ec8ac8bef9dfcadd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaeababa85e5ebe6aa93d011d83fd7994" id="r_gaaeababa85e5ebe6aa93d011d83fd7994"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaeababa85e5ebe6aa93d011d83fd7994">EXTI_EMR_MR19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga514f26dc55f8e37ec8ac8bef9dfcadd4">EXTI_EMR_MR19_Msk</a></td></tr>
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<tr class="separator:gaaeababa85e5ebe6aa93d011d83fd7994"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa67b8f9a15a25b5d2bc93d72082652bd" id="r_gaa67b8f9a15a25b5d2bc93d72082652bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa67b8f9a15a25b5d2bc93d72082652bd">EXTI_EMR_MR20_Pos</a>   (20U)</td></tr>
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<tr class="memitem:gae190c58438ea386748cb39b06fc2d62c" id="r_gae190c58438ea386748cb39b06fc2d62c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae190c58438ea386748cb39b06fc2d62c">EXTI_EMR_MR20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa67b8f9a15a25b5d2bc93d72082652bd">EXTI_EMR_MR20_Pos</a>)</td></tr>
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<tr class="memitem:ga047743f042d00f058dd8cf199c92fbfa" id="r_ga047743f042d00f058dd8cf199c92fbfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga047743f042d00f058dd8cf199c92fbfa">EXTI_EMR_MR20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae190c58438ea386748cb39b06fc2d62c">EXTI_EMR_MR20_Msk</a></td></tr>
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<tr class="memitem:ga75a62823a85e5c8543646c7c6b273e2f" id="r_ga75a62823a85e5c8543646c7c6b273e2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75a62823a85e5c8543646c7c6b273e2f">EXTI_EMR_MR21_Pos</a>   (21U)</td></tr>
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<tr class="memitem:ga525d06c52556b824cbf29d85a8925532" id="r_ga525d06c52556b824cbf29d85a8925532"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga525d06c52556b824cbf29d85a8925532">EXTI_EMR_MR21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga75a62823a85e5c8543646c7c6b273e2f">EXTI_EMR_MR21_Pos</a>)</td></tr>
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<tr class="memitem:ga935956e41524c1f96d208f63a699377a" id="r_ga935956e41524c1f96d208f63a699377a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga935956e41524c1f96d208f63a699377a">EXTI_EMR_MR21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga525d06c52556b824cbf29d85a8925532">EXTI_EMR_MR21_Msk</a></td></tr>
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<tr class="memitem:gae52ca7f79c4b6092d6e2b781f0355bd8" id="r_gae52ca7f79c4b6092d6e2b781f0355bd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae52ca7f79c4b6092d6e2b781f0355bd8">EXTI_EMR_MR22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gae52ca7f79c4b6092d6e2b781f0355bd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79c121c40bb976f66094ced0a851419a" id="r_ga79c121c40bb976f66094ced0a851419a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79c121c40bb976f66094ced0a851419a">EXTI_EMR_MR22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae52ca7f79c4b6092d6e2b781f0355bd8">EXTI_EMR_MR22_Pos</a>)</td></tr>
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<tr class="memitem:ga8fbc202d80be3899d867a0b74abad813" id="r_ga8fbc202d80be3899d867a0b74abad813"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fbc202d80be3899d867a0b74abad813">EXTI_EMR_MR22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga79c121c40bb976f66094ced0a851419a">EXTI_EMR_MR22_Msk</a></td></tr>
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<tr class="memitem:gaf972d7547ed83843150667c301a9d348" id="r_gaf972d7547ed83843150667c301a9d348"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf972d7547ed83843150667c301a9d348">EXTI_EMR_EM0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga515c0dc6d2472e06a89e4bb19725e8f3">EXTI_EMR_MR0</a></td></tr>
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<tr class="memitem:ga07843e6ff5b4ddd02bcf6c66a08cac93" id="r_ga07843e6ff5b4ddd02bcf6c66a08cac93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07843e6ff5b4ddd02bcf6c66a08cac93">EXTI_EMR_EM1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d88e7c10e5985fa425ea7ab4fe4c3e5">EXTI_EMR_MR1</a></td></tr>
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<tr class="separator:ga07843e6ff5b4ddd02bcf6c66a08cac93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga703c31569533b3b6d76f99da69b4d168" id="r_ga703c31569533b3b6d76f99da69b4d168"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga703c31569533b3b6d76f99da69b4d168">EXTI_EMR_EM2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga460d5d4c0b53bcc04d5804e1204ded21">EXTI_EMR_MR2</a></td></tr>
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<tr class="memitem:ga6f2bd51b6a0981492a29436ef2b53344" id="r_ga6f2bd51b6a0981492a29436ef2b53344"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f2bd51b6a0981492a29436ef2b53344">EXTI_EMR_EM3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga73944983ce5a6bde9dc172b4f483898c">EXTI_EMR_MR3</a></td></tr>
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<tr class="memitem:ga7a3f176db76b4eb2cc1400f76afc967a" id="r_ga7a3f176db76b4eb2cc1400f76afc967a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a3f176db76b4eb2cc1400f76afc967a">EXTI_EMR_EM4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab80f809ead83e747677a31c80c6aae03">EXTI_EMR_MR4</a></td></tr>
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<tr class="separator:ga7a3f176db76b4eb2cc1400f76afc967a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc0210d29dceb5682d01786b6fcf47fe" id="r_gacc0210d29dceb5682d01786b6fcf47fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc0210d29dceb5682d01786b6fcf47fe">EXTI_EMR_EM5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65976f75b703f740dea3562ba3b8db59">EXTI_EMR_MR5</a></td></tr>
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<tr class="separator:gacc0210d29dceb5682d01786b6fcf47fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c05702eec349cbbcce9b7bc825e2fd8" id="r_ga1c05702eec349cbbcce9b7bc825e2fd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c05702eec349cbbcce9b7bc825e2fd8">EXTI_EMR_EM6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaea480bd932cd1fa0904f5eb1caee9a12">EXTI_EMR_MR6</a></td></tr>
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<tr class="separator:ga1c05702eec349cbbcce9b7bc825e2fd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf04b9ef7548fb0564beae69739bdea72" id="r_gaf04b9ef7548fb0564beae69739bdea72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf04b9ef7548fb0564beae69739bdea72">EXTI_EMR_EM7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadbb27ff8664928994ef96f87052d14be">EXTI_EMR_MR7</a></td></tr>
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<tr class="separator:gaf04b9ef7548fb0564beae69739bdea72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7af57b60f4623e5a65011519dd707991" id="r_ga7af57b60f4623e5a65011519dd707991"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7af57b60f4623e5a65011519dd707991">EXTI_EMR_EM8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ed4b371da871ffd0cc12ee00147282f">EXTI_EMR_MR8</a></td></tr>
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<tr class="separator:ga7af57b60f4623e5a65011519dd707991"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3757f0da147b7bb49719cb69096b5bc7" id="r_ga3757f0da147b7bb49719cb69096b5bc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3757f0da147b7bb49719cb69096b5bc7">EXTI_EMR_EM9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga109af342179fff1fccfdde582834867a">EXTI_EMR_MR9</a></td></tr>
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<tr class="separator:ga3757f0da147b7bb49719cb69096b5bc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad548185c3c99b69f3eaec50067999112" id="r_gad548185c3c99b69f3eaec50067999112"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad548185c3c99b69f3eaec50067999112">EXTI_EMR_EM10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf342d34ed1b8e4aa916bf49e30c2a234">EXTI_EMR_MR10</a></td></tr>
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<tr class="memitem:gad5d0782c45b8b0951c8bbb5e7037a52b" id="r_gad5d0782c45b8b0951c8bbb5e7037a52b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5d0782c45b8b0951c8bbb5e7037a52b">EXTI_EMR_EM11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ec516af1de770c82c3c9c458cbc0172">EXTI_EMR_MR11</a></td></tr>
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<tr class="separator:gad5d0782c45b8b0951c8bbb5e7037a52b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef9eaec30663289e66b9d9b40682910f" id="r_gaef9eaec30663289e66b9d9b40682910f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef9eaec30663289e66b9d9b40682910f">EXTI_EMR_EM12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga15732553e5b0de9f58180a0b024d4cad">EXTI_EMR_MR12</a></td></tr>
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<tr class="separator:gaef9eaec30663289e66b9d9b40682910f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2fc88afc4ba8231f4368527cc983d50" id="r_gad2fc88afc4ba8231f4368527cc983d50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2fc88afc4ba8231f4368527cc983d50">EXTI_EMR_EM13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9fd2ec6472e46869956acb28f5e1b55f">EXTI_EMR_MR13</a></td></tr>
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<tr class="separator:gad2fc88afc4ba8231f4368527cc983d50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf3c10c55ef88bb255f899d0d0939c98" id="r_gaaf3c10c55ef88bb255f899d0d0939c98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf3c10c55ef88bb255f899d0d0939c98">EXTI_EMR_EM14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaecf5890ea71eea034ec1cd9e96284f89">EXTI_EMR_MR14</a></td></tr>
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<tr class="separator:gaaf3c10c55ef88bb255f899d0d0939c98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3690bd10db8f6505368f84d1d360d83" id="r_gaa3690bd10db8f6505368f84d1d360d83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3690bd10db8f6505368f84d1d360d83">EXTI_EMR_EM15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a7bacc32351a36aefcd5614abc76ae3">EXTI_EMR_MR15</a></td></tr>
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<tr class="separator:gaa3690bd10db8f6505368f84d1d360d83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadea424b2e5e1e8733e5f8ba76b16c6c" id="r_gaadea424b2e5e1e8733e5f8ba76b16c6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadea424b2e5e1e8733e5f8ba76b16c6c">EXTI_EMR_EM16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34b1a6934265da759bc061f73d5d1374">EXTI_EMR_MR16</a></td></tr>
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<tr class="separator:gaadea424b2e5e1e8733e5f8ba76b16c6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f640eaa67ff0f9e3e849fdc65f7f34e" id="r_ga0f640eaa67ff0f9e3e849fdc65f7f34e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f640eaa67ff0f9e3e849fdc65f7f34e">EXTI_EMR_EM17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a30aa20cf475eecf7e15171e83035e4">EXTI_EMR_MR17</a></td></tr>
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<tr class="separator:ga0f640eaa67ff0f9e3e849fdc65f7f34e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7162c4422ad98bec692f15dda4e011eb" id="r_ga7162c4422ad98bec692f15dda4e011eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7162c4422ad98bec692f15dda4e011eb">EXTI_EMR_EM18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga25eee729b57b4c78a0613c184fc539e5">EXTI_EMR_MR18</a></td></tr>
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<tr class="separator:ga7162c4422ad98bec692f15dda4e011eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96076632bf23a1dfb53cfada4008d7b3" id="r_ga96076632bf23a1dfb53cfada4008d7b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96076632bf23a1dfb53cfada4008d7b3">EXTI_EMR_EM19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaeababa85e5ebe6aa93d011d83fd7994">EXTI_EMR_MR19</a></td></tr>
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<tr class="separator:ga96076632bf23a1dfb53cfada4008d7b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a88ab99418d93b7277f19736c14c6c2" id="r_ga2a88ab99418d93b7277f19736c14c6c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a88ab99418d93b7277f19736c14c6c2">EXTI_EMR_EM20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga047743f042d00f058dd8cf199c92fbfa">EXTI_EMR_MR20</a></td></tr>
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<tr class="separator:ga2a88ab99418d93b7277f19736c14c6c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf17512ecb4d8572e8b73ab1a427fd500" id="r_gaf17512ecb4d8572e8b73ab1a427fd500"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf17512ecb4d8572e8b73ab1a427fd500">EXTI_EMR_EM21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga935956e41524c1f96d208f63a699377a">EXTI_EMR_MR21</a></td></tr>
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<tr class="separator:gaf17512ecb4d8572e8b73ab1a427fd500"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31b9e9ec368a547f58ab7f6359c58bdf" id="r_ga31b9e9ec368a547f58ab7f6359c58bdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31b9e9ec368a547f58ab7f6359c58bdf">EXTI_EMR_EM22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fbc202d80be3899d867a0b74abad813">EXTI_EMR_MR22</a></td></tr>
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<tr class="memitem:gaa359160d5aba50c4aff40330fd99d426" id="r_gaa359160d5aba50c4aff40330fd99d426"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa359160d5aba50c4aff40330fd99d426">EXTI_RTSR_TR0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga2b3f74a67ed2871290e5cee5ec27e487" id="r_ga2b3f74a67ed2871290e5cee5ec27e487"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b3f74a67ed2871290e5cee5ec27e487">EXTI_RTSR_TR0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa359160d5aba50c4aff40330fd99d426">EXTI_RTSR_TR0_Pos</a>)</td></tr>
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<tr class="separator:ga2b3f74a67ed2871290e5cee5ec27e487"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb1823a87cd797a6066681a3256cecc6" id="r_gadb1823a87cd797a6066681a3256cecc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb1823a87cd797a6066681a3256cecc6">EXTI_RTSR_TR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b3f74a67ed2871290e5cee5ec27e487">EXTI_RTSR_TR0_Msk</a></td></tr>
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<tr class="separator:gadb1823a87cd797a6066681a3256cecc6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga099233be3061fa5c0e44cbf3e20b6394" id="r_ga099233be3061fa5c0e44cbf3e20b6394"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga099233be3061fa5c0e44cbf3e20b6394">EXTI_RTSR_TR1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga099233be3061fa5c0e44cbf3e20b6394"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57ba4871b93492e5e8c846f2833f9da1" id="r_ga57ba4871b93492e5e8c846f2833f9da1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57ba4871b93492e5e8c846f2833f9da1">EXTI_RTSR_TR1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga099233be3061fa5c0e44cbf3e20b6394">EXTI_RTSR_TR1_Pos</a>)</td></tr>
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<tr class="separator:ga57ba4871b93492e5e8c846f2833f9da1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c42cc3763c52d1061b32219fc441566" id="r_ga1c42cc3763c52d1061b32219fc441566"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c42cc3763c52d1061b32219fc441566">EXTI_RTSR_TR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57ba4871b93492e5e8c846f2833f9da1">EXTI_RTSR_TR1_Msk</a></td></tr>
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<tr class="separator:ga1c42cc3763c52d1061b32219fc441566"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22b2187bec09d19b2b79382c25ff3b4b" id="r_ga22b2187bec09d19b2b79382c25ff3b4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22b2187bec09d19b2b79382c25ff3b4b">EXTI_RTSR_TR2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga22b2187bec09d19b2b79382c25ff3b4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbecd9a805326155030f357bc2d70046" id="r_gadbecd9a805326155030f357bc2d70046"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbecd9a805326155030f357bc2d70046">EXTI_RTSR_TR2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga22b2187bec09d19b2b79382c25ff3b4b">EXTI_RTSR_TR2_Pos</a>)</td></tr>
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<tr class="separator:gadbecd9a805326155030f357bc2d70046"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c073b519f09b130e4ab4039823e290c" id="r_ga1c073b519f09b130e4ab4039823e290c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c073b519f09b130e4ab4039823e290c">EXTI_RTSR_TR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadbecd9a805326155030f357bc2d70046">EXTI_RTSR_TR2_Msk</a></td></tr>
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<tr class="separator:ga1c073b519f09b130e4ab4039823e290c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeae95954e4c5e25f225d3cad0e2b2362" id="r_gaeae95954e4c5e25f225d3cad0e2b2362"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeae95954e4c5e25f225d3cad0e2b2362">EXTI_RTSR_TR3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaeae95954e4c5e25f225d3cad0e2b2362"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga560d856b177ddb7b90e101caf3ce66be" id="r_ga560d856b177ddb7b90e101caf3ce66be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga560d856b177ddb7b90e101caf3ce66be">EXTI_RTSR_TR3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeae95954e4c5e25f225d3cad0e2b2362">EXTI_RTSR_TR3_Pos</a>)</td></tr>
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<tr class="separator:ga560d856b177ddb7b90e101caf3ce66be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga090f295579a774c215585a55e5066b11" id="r_ga090f295579a774c215585a55e5066b11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga090f295579a774c215585a55e5066b11">EXTI_RTSR_TR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga560d856b177ddb7b90e101caf3ce66be">EXTI_RTSR_TR3_Msk</a></td></tr>
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<tr class="separator:ga090f295579a774c215585a55e5066b11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa95865d62fde25381efad4f0c38cd8bd" id="r_gaa95865d62fde25381efad4f0c38cd8bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa95865d62fde25381efad4f0c38cd8bd">EXTI_RTSR_TR4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaa95865d62fde25381efad4f0c38cd8bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga795eff3140a1d0c0e1fcfc03b2fa5860" id="r_ga795eff3140a1d0c0e1fcfc03b2fa5860"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga795eff3140a1d0c0e1fcfc03b2fa5860">EXTI_RTSR_TR4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa95865d62fde25381efad4f0c38cd8bd">EXTI_RTSR_TR4_Pos</a>)</td></tr>
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<tr class="separator:ga795eff3140a1d0c0e1fcfc03b2fa5860"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabce4722e99e3f44d40bfb6afb63444cc" id="r_gabce4722e99e3f44d40bfb6afb63444cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabce4722e99e3f44d40bfb6afb63444cc">EXTI_RTSR_TR4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga795eff3140a1d0c0e1fcfc03b2fa5860">EXTI_RTSR_TR4_Msk</a></td></tr>
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<tr class="separator:gabce4722e99e3f44d40bfb6afb63444cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29eade4e6218042bad165fd8cb162662" id="r_ga29eade4e6218042bad165fd8cb162662"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29eade4e6218042bad165fd8cb162662">EXTI_RTSR_TR5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga29eade4e6218042bad165fd8cb162662"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65a7c4c35c85b3e922e1df8447dd8e6d" id="r_ga65a7c4c35c85b3e922e1df8447dd8e6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65a7c4c35c85b3e922e1df8447dd8e6d">EXTI_RTSR_TR5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga29eade4e6218042bad165fd8cb162662">EXTI_RTSR_TR5_Pos</a>)</td></tr>
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<tr class="separator:ga65a7c4c35c85b3e922e1df8447dd8e6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac57b970ebc88f7bb015119ece9dd32de" id="r_gac57b970ebc88f7bb015119ece9dd32de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac57b970ebc88f7bb015119ece9dd32de">EXTI_RTSR_TR5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65a7c4c35c85b3e922e1df8447dd8e6d">EXTI_RTSR_TR5_Msk</a></td></tr>
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<tr class="separator:gac57b970ebc88f7bb015119ece9dd32de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a5fd949f067c605127932367ba4dad5" id="r_ga7a5fd949f067c605127932367ba4dad5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a5fd949f067c605127932367ba4dad5">EXTI_RTSR_TR6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga7a5fd949f067c605127932367ba4dad5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85d1a629b7cde96375b82803c46cfcb4" id="r_ga85d1a629b7cde96375b82803c46cfcb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85d1a629b7cde96375b82803c46cfcb4">EXTI_RTSR_TR6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a5fd949f067c605127932367ba4dad5">EXTI_RTSR_TR6_Pos</a>)</td></tr>
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<tr class="separator:ga85d1a629b7cde96375b82803c46cfcb4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccc2212ce653d34cf48446ae0a68bed6" id="r_gaccc2212ce653d34cf48446ae0a68bed6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccc2212ce653d34cf48446ae0a68bed6">EXTI_RTSR_TR6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga85d1a629b7cde96375b82803c46cfcb4">EXTI_RTSR_TR6_Msk</a></td></tr>
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<tr class="separator:gaccc2212ce653d34cf48446ae0a68bed6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79f320ed539b225c1e4f50e3cfb43100" id="r_ga79f320ed539b225c1e4f50e3cfb43100"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79f320ed539b225c1e4f50e3cfb43100">EXTI_RTSR_TR7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga79f320ed539b225c1e4f50e3cfb43100"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbc9d6a9f75fdff045e4806edad97b47" id="r_gadbc9d6a9f75fdff045e4806edad97b47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbc9d6a9f75fdff045e4806edad97b47">EXTI_RTSR_TR7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga79f320ed539b225c1e4f50e3cfb43100">EXTI_RTSR_TR7_Pos</a>)</td></tr>
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<tr class="separator:gadbc9d6a9f75fdff045e4806edad97b47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad380a0bc59524f4a0846a0b91d3c65c1" id="r_gad380a0bc59524f4a0846a0b91d3c65c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad380a0bc59524f4a0846a0b91d3c65c1">EXTI_RTSR_TR7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadbc9d6a9f75fdff045e4806edad97b47">EXTI_RTSR_TR7_Msk</a></td></tr>
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<tr class="separator:gad380a0bc59524f4a0846a0b91d3c65c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f9bcf9229eced0f5101842fd9585e40" id="r_ga1f9bcf9229eced0f5101842fd9585e40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f9bcf9229eced0f5101842fd9585e40">EXTI_RTSR_TR8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga1f9bcf9229eced0f5101842fd9585e40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16c3b77b33079caf74151ade9fbc3b82" id="r_ga16c3b77b33079caf74151ade9fbc3b82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16c3b77b33079caf74151ade9fbc3b82">EXTI_RTSR_TR8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f9bcf9229eced0f5101842fd9585e40">EXTI_RTSR_TR8_Pos</a>)</td></tr>
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<tr class="separator:ga16c3b77b33079caf74151ade9fbc3b82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26cd6a5115b0bbe113f39545bff1ee39" id="r_ga26cd6a5115b0bbe113f39545bff1ee39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26cd6a5115b0bbe113f39545bff1ee39">EXTI_RTSR_TR8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga16c3b77b33079caf74151ade9fbc3b82">EXTI_RTSR_TR8_Msk</a></td></tr>
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<tr class="separator:ga26cd6a5115b0bbe113f39545bff1ee39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f3c856ba7076de4742cea9494d2d97b" id="r_ga3f3c856ba7076de4742cea9494d2d97b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f3c856ba7076de4742cea9494d2d97b">EXTI_RTSR_TR9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga3f3c856ba7076de4742cea9494d2d97b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga394b28a010f7937178112dd11c7edf7b" id="r_ga394b28a010f7937178112dd11c7edf7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga394b28a010f7937178112dd11c7edf7b">EXTI_RTSR_TR9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f3c856ba7076de4742cea9494d2d97b">EXTI_RTSR_TR9_Pos</a>)</td></tr>
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<tr class="separator:ga394b28a010f7937178112dd11c7edf7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3127246b2db3571b00c6af2453941d17" id="r_ga3127246b2db3571b00c6af2453941d17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3127246b2db3571b00c6af2453941d17">EXTI_RTSR_TR9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga394b28a010f7937178112dd11c7edf7b">EXTI_RTSR_TR9_Msk</a></td></tr>
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<tr class="separator:ga3127246b2db3571b00c6af2453941d17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf19c55236009d4d88273be1fe6d17b69" id="r_gaf19c55236009d4d88273be1fe6d17b69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf19c55236009d4d88273be1fe6d17b69">EXTI_RTSR_TR10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaf19c55236009d4d88273be1fe6d17b69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12717df4fef207dd689f240bbb23cedf" id="r_ga12717df4fef207dd689f240bbb23cedf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12717df4fef207dd689f240bbb23cedf">EXTI_RTSR_TR10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf19c55236009d4d88273be1fe6d17b69">EXTI_RTSR_TR10_Pos</a>)</td></tr>
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<tr class="separator:ga12717df4fef207dd689f240bbb23cedf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa29df7ddbd067889992eb60ecddce0e4" id="r_gaa29df7ddbd067889992eb60ecddce0e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa29df7ddbd067889992eb60ecddce0e4">EXTI_RTSR_TR10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga12717df4fef207dd689f240bbb23cedf">EXTI_RTSR_TR10_Msk</a></td></tr>
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<tr class="memitem:ga7f11477d08556852c4cf210f75d11920" id="r_ga7f11477d08556852c4cf210f75d11920"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f11477d08556852c4cf210f75d11920">EXTI_RTSR_TR11_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga36a3f679be0d89926b127c4b293111e2" id="r_ga36a3f679be0d89926b127c4b293111e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36a3f679be0d89926b127c4b293111e2">EXTI_RTSR_TR11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f11477d08556852c4cf210f75d11920">EXTI_RTSR_TR11_Pos</a>)</td></tr>
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<tr class="separator:ga36a3f679be0d89926b127c4b293111e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cf7a92cdb61b3f8cf6eec9513317ab7" id="r_ga8cf7a92cdb61b3f8cf6eec9513317ab7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cf7a92cdb61b3f8cf6eec9513317ab7">EXTI_RTSR_TR11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36a3f679be0d89926b127c4b293111e2">EXTI_RTSR_TR11_Msk</a></td></tr>
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<tr class="separator:ga8cf7a92cdb61b3f8cf6eec9513317ab7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8b0314682ff50f85bd8d5570fb6935a" id="r_gaf8b0314682ff50f85bd8d5570fb6935a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8b0314682ff50f85bd8d5570fb6935a">EXTI_RTSR_TR12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaf8b0314682ff50f85bd8d5570fb6935a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4507125ae8a435b97fe643f73e6492e" id="r_gab4507125ae8a435b97fe643f73e6492e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4507125ae8a435b97fe643f73e6492e">EXTI_RTSR_TR12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8b0314682ff50f85bd8d5570fb6935a">EXTI_RTSR_TR12_Pos</a>)</td></tr>
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<tr class="separator:gab4507125ae8a435b97fe643f73e6492e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0423be12bfb13f34eec9656d6d274e04" id="r_ga0423be12bfb13f34eec9656d6d274e04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0423be12bfb13f34eec9656d6d274e04">EXTI_RTSR_TR12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab4507125ae8a435b97fe643f73e6492e">EXTI_RTSR_TR12_Msk</a></td></tr>
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<tr class="separator:ga0423be12bfb13f34eec9656d6d274e04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20176d8fa4181b22a833e1598e96b153" id="r_ga20176d8fa4181b22a833e1598e96b153"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20176d8fa4181b22a833e1598e96b153">EXTI_RTSR_TR13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga20176d8fa4181b22a833e1598e96b153"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga799f99b4edc9604b38ab1f12e0cf9cae" id="r_ga799f99b4edc9604b38ab1f12e0cf9cae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga799f99b4edc9604b38ab1f12e0cf9cae">EXTI_RTSR_TR13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20176d8fa4181b22a833e1598e96b153">EXTI_RTSR_TR13_Pos</a>)</td></tr>
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<tr class="memitem:ga5d5ef451fd76dc0fa9c76d7c520d8f12" id="r_ga5d5ef451fd76dc0fa9c76d7c520d8f12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d5ef451fd76dc0fa9c76d7c520d8f12">EXTI_RTSR_TR13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga799f99b4edc9604b38ab1f12e0cf9cae">EXTI_RTSR_TR13_Msk</a></td></tr>
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<tr class="separator:ga5d5ef451fd76dc0fa9c76d7c520d8f12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e76cfdc7657907d423ba90dcac7bc90" id="r_ga2e76cfdc7657907d423ba90dcac7bc90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e76cfdc7657907d423ba90dcac7bc90">EXTI_RTSR_TR14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga2e76cfdc7657907d423ba90dcac7bc90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42533490cce0d8d3ff55a2d6ad8c24ee" id="r_ga42533490cce0d8d3ff55a2d6ad8c24ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42533490cce0d8d3ff55a2d6ad8c24ee">EXTI_RTSR_TR14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e76cfdc7657907d423ba90dcac7bc90">EXTI_RTSR_TR14_Pos</a>)</td></tr>
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<tr class="separator:ga42533490cce0d8d3ff55a2d6ad8c24ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95b0d883fa0fbc49105bda5596463cda" id="r_ga95b0d883fa0fbc49105bda5596463cda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95b0d883fa0fbc49105bda5596463cda">EXTI_RTSR_TR14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga42533490cce0d8d3ff55a2d6ad8c24ee">EXTI_RTSR_TR14_Msk</a></td></tr>
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<tr class="separator:ga95b0d883fa0fbc49105bda5596463cda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa62a698b0b47384cd72f49ebb9f17f4c" id="r_gaa62a698b0b47384cd72f49ebb9f17f4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa62a698b0b47384cd72f49ebb9f17f4c">EXTI_RTSR_TR15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaa62a698b0b47384cd72f49ebb9f17f4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ffbcdf64f7de2427560316706ddc8c1" id="r_ga3ffbcdf64f7de2427560316706ddc8c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ffbcdf64f7de2427560316706ddc8c1">EXTI_RTSR_TR15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa62a698b0b47384cd72f49ebb9f17f4c">EXTI_RTSR_TR15_Pos</a>)</td></tr>
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<tr class="separator:ga3ffbcdf64f7de2427560316706ddc8c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fe54b09102a18676829c0bafb0aead2" id="r_ga4fe54b09102a18676829c0bafb0aead2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fe54b09102a18676829c0bafb0aead2">EXTI_RTSR_TR15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ffbcdf64f7de2427560316706ddc8c1">EXTI_RTSR_TR15_Msk</a></td></tr>
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<tr class="separator:ga4fe54b09102a18676829c0bafb0aead2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c280314b145321c6a62ce2764d1fd59" id="r_ga5c280314b145321c6a62ce2764d1fd59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c280314b145321c6a62ce2764d1fd59">EXTI_RTSR_TR16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga5c280314b145321c6a62ce2764d1fd59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad883a3a53902664492c684a6dd435d33" id="r_gad883a3a53902664492c684a6dd435d33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad883a3a53902664492c684a6dd435d33">EXTI_RTSR_TR16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c280314b145321c6a62ce2764d1fd59">EXTI_RTSR_TR16_Pos</a>)</td></tr>
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<tr class="separator:gad883a3a53902664492c684a6dd435d33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8e4fb52990f0fa3fb9bed5b74f1a589" id="r_gae8e4fb52990f0fa3fb9bed5b74f1a589"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8e4fb52990f0fa3fb9bed5b74f1a589">EXTI_RTSR_TR16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad883a3a53902664492c684a6dd435d33">EXTI_RTSR_TR16_Msk</a></td></tr>
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<tr class="separator:gae8e4fb52990f0fa3fb9bed5b74f1a589"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47fa1d5d96ea124413c3b81b9c10f75f" id="r_ga47fa1d5d96ea124413c3b81b9c10f75f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47fa1d5d96ea124413c3b81b9c10f75f">EXTI_RTSR_TR17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga47fa1d5d96ea124413c3b81b9c10f75f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42283a804716a4de1910afd032b87681" id="r_ga42283a804716a4de1910afd032b87681"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42283a804716a4de1910afd032b87681">EXTI_RTSR_TR17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga47fa1d5d96ea124413c3b81b9c10f75f">EXTI_RTSR_TR17_Pos</a>)</td></tr>
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<tr class="separator:ga42283a804716a4de1910afd032b87681"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0a8fcb63516a4ed0d91b556f696f806" id="r_gad0a8fcb63516a4ed0d91b556f696f806"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0a8fcb63516a4ed0d91b556f696f806">EXTI_RTSR_TR17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga42283a804716a4de1910afd032b87681">EXTI_RTSR_TR17_Msk</a></td></tr>
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<tr class="separator:gad0a8fcb63516a4ed0d91b556f696f806"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49afa76eab5b3a7d5e5640fced73047c" id="r_ga49afa76eab5b3a7d5e5640fced73047c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49afa76eab5b3a7d5e5640fced73047c">EXTI_RTSR_TR18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga49afa76eab5b3a7d5e5640fced73047c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga708076360f04650ae4bfdd6695caa617" id="r_ga708076360f04650ae4bfdd6695caa617"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga708076360f04650ae4bfdd6695caa617">EXTI_RTSR_TR18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga49afa76eab5b3a7d5e5640fced73047c">EXTI_RTSR_TR18_Pos</a>)</td></tr>
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<tr class="separator:ga708076360f04650ae4bfdd6695caa617"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca4223b8c4bc8726ac96ec64837f7b62" id="r_gaca4223b8c4bc8726ac96ec64837f7b62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca4223b8c4bc8726ac96ec64837f7b62">EXTI_RTSR_TR18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga708076360f04650ae4bfdd6695caa617">EXTI_RTSR_TR18_Msk</a></td></tr>
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<tr class="separator:gaca4223b8c4bc8726ac96ec64837f7b62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef9bfa9cb8df10ec1e3c2dd50235231c" id="r_gaef9bfa9cb8df10ec1e3c2dd50235231c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef9bfa9cb8df10ec1e3c2dd50235231c">EXTI_RTSR_TR19_Pos</a>   (19U)</td></tr>
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<tr class="separator:gaef9bfa9cb8df10ec1e3c2dd50235231c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab40d59af38c6adbe9621b8ab68dbdbe" id="r_gaab40d59af38c6adbe9621b8ab68dbdbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab40d59af38c6adbe9621b8ab68dbdbe">EXTI_RTSR_TR19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef9bfa9cb8df10ec1e3c2dd50235231c">EXTI_RTSR_TR19_Pos</a>)</td></tr>
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<tr class="separator:gaab40d59af38c6adbe9621b8ab68dbdbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40a722b0c36e832f619b2136f1510b3e" id="r_ga40a722b0c36e832f619b2136f1510b3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40a722b0c36e832f619b2136f1510b3e">EXTI_RTSR_TR19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaab40d59af38c6adbe9621b8ab68dbdbe">EXTI_RTSR_TR19_Msk</a></td></tr>
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<tr class="separator:ga40a722b0c36e832f619b2136f1510b3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga825c9ea20abb9a733bc90b94440fbc63" id="r_ga825c9ea20abb9a733bc90b94440fbc63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga825c9ea20abb9a733bc90b94440fbc63">EXTI_RTSR_TR20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga825c9ea20abb9a733bc90b94440fbc63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3497416ddbe940f3f87bdbe94dcb423" id="r_gaf3497416ddbe940f3f87bdbe94dcb423"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3497416ddbe940f3f87bdbe94dcb423">EXTI_RTSR_TR20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga825c9ea20abb9a733bc90b94440fbc63">EXTI_RTSR_TR20_Pos</a>)</td></tr>
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<tr class="separator:gaf3497416ddbe940f3f87bdbe94dcb423"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga076319b89121213ea97b4767182b17bd" id="r_ga076319b89121213ea97b4767182b17bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga076319b89121213ea97b4767182b17bd">EXTI_RTSR_TR20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3497416ddbe940f3f87bdbe94dcb423">EXTI_RTSR_TR20_Msk</a></td></tr>
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<tr class="separator:ga076319b89121213ea97b4767182b17bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a92f33d68f20f61d92563404305ba35" id="r_ga6a92f33d68f20f61d92563404305ba35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a92f33d68f20f61d92563404305ba35">EXTI_RTSR_TR21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga6a92f33d68f20f61d92563404305ba35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0acfd045c5ef66801c4f70a7a529a210" id="r_ga0acfd045c5ef66801c4f70a7a529a210"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0acfd045c5ef66801c4f70a7a529a210">EXTI_RTSR_TR21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a92f33d68f20f61d92563404305ba35">EXTI_RTSR_TR21_Pos</a>)</td></tr>
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<tr class="separator:ga0acfd045c5ef66801c4f70a7a529a210"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b1fd6472c3739cb5d21ba25bb6f745d" id="r_ga5b1fd6472c3739cb5d21ba25bb6f745d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b1fd6472c3739cb5d21ba25bb6f745d">EXTI_RTSR_TR21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0acfd045c5ef66801c4f70a7a529a210">EXTI_RTSR_TR21_Msk</a></td></tr>
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<tr class="memitem:gad9b6c8e3b151388284c11fad135c06f3" id="r_gad9b6c8e3b151388284c11fad135c06f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9b6c8e3b151388284c11fad135c06f3">EXTI_RTSR_TR22_Pos</a>   (22U)</td></tr>
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<tr class="memitem:gadcf74a99ed3d1bc23d06f4e6d634b46f" id="r_gadcf74a99ed3d1bc23d06f4e6d634b46f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcf74a99ed3d1bc23d06f4e6d634b46f">EXTI_RTSR_TR22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9b6c8e3b151388284c11fad135c06f3">EXTI_RTSR_TR22_Pos</a>)</td></tr>
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<tr class="memitem:gaca577c5c1742e043ed5e0a2ffcc88f82" id="r_gaca577c5c1742e043ed5e0a2ffcc88f82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca577c5c1742e043ed5e0a2ffcc88f82">EXTI_RTSR_TR22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadcf74a99ed3d1bc23d06f4e6d634b46f">EXTI_RTSR_TR22_Msk</a></td></tr>
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<tr class="separator:gaca577c5c1742e043ed5e0a2ffcc88f82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a92993932aa377be10ff0376f600b9f" id="r_ga0a92993932aa377be10ff0376f600b9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a92993932aa377be10ff0376f600b9f">EXTI_FTSR_TR0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga6fd5afa140faff4e562142dc289387cc" id="r_ga6fd5afa140faff4e562142dc289387cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fd5afa140faff4e562142dc289387cc">EXTI_FTSR_TR0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a92993932aa377be10ff0376f600b9f">EXTI_FTSR_TR0_Pos</a>)</td></tr>
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<tr class="memitem:gacfb6fa5ae3fcaf08aec6d86c3bfefa4c" id="r_gacfb6fa5ae3fcaf08aec6d86c3bfefa4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfb6fa5ae3fcaf08aec6d86c3bfefa4c">EXTI_FTSR_TR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6fd5afa140faff4e562142dc289387cc">EXTI_FTSR_TR0_Msk</a></td></tr>
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<tr class="memitem:gadf26d85ea048d7c483094a9eebaa7aba" id="r_gadf26d85ea048d7c483094a9eebaa7aba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf26d85ea048d7c483094a9eebaa7aba">EXTI_FTSR_TR1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gadf26d85ea048d7c483094a9eebaa7aba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01090491a062f3b8b4a80b0b66690ce8" id="r_ga01090491a062f3b8b4a80b0b66690ce8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01090491a062f3b8b4a80b0b66690ce8">EXTI_FTSR_TR1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf26d85ea048d7c483094a9eebaa7aba">EXTI_FTSR_TR1_Pos</a>)</td></tr>
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<tr class="separator:ga01090491a062f3b8b4a80b0b66690ce8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac287be3bd3bad84aed48603dbe8bd4ed" id="r_gac287be3bd3bad84aed48603dbe8bd4ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac287be3bd3bad84aed48603dbe8bd4ed">EXTI_FTSR_TR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga01090491a062f3b8b4a80b0b66690ce8">EXTI_FTSR_TR1_Msk</a></td></tr>
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<tr class="memitem:ga425e560479e3bcf114aca570bd170079" id="r_ga425e560479e3bcf114aca570bd170079"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga425e560479e3bcf114aca570bd170079">EXTI_FTSR_TR2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga425e560479e3bcf114aca570bd170079"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71bfd75475e3d65a3bee0a4ccd41e0e3" id="r_ga71bfd75475e3d65a3bee0a4ccd41e0e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71bfd75475e3d65a3bee0a4ccd41e0e3">EXTI_FTSR_TR2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga425e560479e3bcf114aca570bd170079">EXTI_FTSR_TR2_Pos</a>)</td></tr>
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<tr class="memitem:ga9c4503803cbe1933cd35519cfc809041" id="r_ga9c4503803cbe1933cd35519cfc809041"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c4503803cbe1933cd35519cfc809041">EXTI_FTSR_TR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71bfd75475e3d65a3bee0a4ccd41e0e3">EXTI_FTSR_TR2_Msk</a></td></tr>
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<tr class="memitem:gaaf7f91925c2ac9c267480ed6b9fc1a04" id="r_gaaf7f91925c2ac9c267480ed6b9fc1a04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf7f91925c2ac9c267480ed6b9fc1a04">EXTI_FTSR_TR3_Pos</a>   (3U)</td></tr>
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<tr class="memitem:ga71b35fe3af253035fe6c7a8702ef8e5e" id="r_ga71b35fe3af253035fe6c7a8702ef8e5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71b35fe3af253035fe6c7a8702ef8e5e">EXTI_FTSR_TR3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf7f91925c2ac9c267480ed6b9fc1a04">EXTI_FTSR_TR3_Pos</a>)</td></tr>
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<tr class="separator:ga71b35fe3af253035fe6c7a8702ef8e5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23593d2b8a9ec0147bab28765af30e1f" id="r_ga23593d2b8a9ec0147bab28765af30e1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23593d2b8a9ec0147bab28765af30e1f">EXTI_FTSR_TR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71b35fe3af253035fe6c7a8702ef8e5e">EXTI_FTSR_TR3_Msk</a></td></tr>
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<tr class="separator:ga23593d2b8a9ec0147bab28765af30e1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa295a76e5ee487856be1dde365373f5d" id="r_gaa295a76e5ee487856be1dde365373f5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa295a76e5ee487856be1dde365373f5d">EXTI_FTSR_TR4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaa295a76e5ee487856be1dde365373f5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabecb16c1706cb6cad8ec0a8e06ac2475" id="r_gabecb16c1706cb6cad8ec0a8e06ac2475"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabecb16c1706cb6cad8ec0a8e06ac2475">EXTI_FTSR_TR4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa295a76e5ee487856be1dde365373f5d">EXTI_FTSR_TR4_Pos</a>)</td></tr>
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<tr class="separator:gabecb16c1706cb6cad8ec0a8e06ac2475"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa77211bfa8f4d77cf373296954dad6b2" id="r_gaa77211bfa8f4d77cf373296954dad6b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa77211bfa8f4d77cf373296954dad6b2">EXTI_FTSR_TR4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabecb16c1706cb6cad8ec0a8e06ac2475">EXTI_FTSR_TR4_Msk</a></td></tr>
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<tr class="separator:gaa77211bfa8f4d77cf373296954dad6b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f3affd9eee854acf6d5e1d820421532" id="r_ga8f3affd9eee854acf6d5e1d820421532"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f3affd9eee854acf6d5e1d820421532">EXTI_FTSR_TR5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga8f3affd9eee854acf6d5e1d820421532"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafeffba32b6b0854a232493dc2e2634d4" id="r_gafeffba32b6b0854a232493dc2e2634d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafeffba32b6b0854a232493dc2e2634d4">EXTI_FTSR_TR5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f3affd9eee854acf6d5e1d820421532">EXTI_FTSR_TR5_Pos</a>)</td></tr>
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<tr class="memitem:ga903f9b080c5971dd5d7935e5b87886e2" id="r_ga903f9b080c5971dd5d7935e5b87886e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga903f9b080c5971dd5d7935e5b87886e2">EXTI_FTSR_TR5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafeffba32b6b0854a232493dc2e2634d4">EXTI_FTSR_TR5_Msk</a></td></tr>
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<tr class="separator:ga903f9b080c5971dd5d7935e5b87886e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5995bc6ec7301b6623c8014fd9db711" id="r_gac5995bc6ec7301b6623c8014fd9db711"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5995bc6ec7301b6623c8014fd9db711">EXTI_FTSR_TR6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gac5995bc6ec7301b6623c8014fd9db711"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6590e0e011792337a19831a0ea2df2c" id="r_gaa6590e0e011792337a19831a0ea2df2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6590e0e011792337a19831a0ea2df2c">EXTI_FTSR_TR6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac5995bc6ec7301b6623c8014fd9db711">EXTI_FTSR_TR6_Pos</a>)</td></tr>
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<tr class="separator:gaa6590e0e011792337a19831a0ea2df2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8527cce22f69e02a08ed67a67f8e5ca" id="r_gae8527cce22f69e02a08ed67a67f8e5ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8527cce22f69e02a08ed67a67f8e5ca">EXTI_FTSR_TR6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6590e0e011792337a19831a0ea2df2c">EXTI_FTSR_TR6_Msk</a></td></tr>
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<tr class="separator:gae8527cce22f69e02a08ed67a67f8e5ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf100b4a2a76bcfdc3f7d0da8d39cc8b1" id="r_gaf100b4a2a76bcfdc3f7d0da8d39cc8b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf100b4a2a76bcfdc3f7d0da8d39cc8b1">EXTI_FTSR_TR7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaf100b4a2a76bcfdc3f7d0da8d39cc8b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d1347ed594a5d5bb5e0a69f31cbfb20" id="r_ga0d1347ed594a5d5bb5e0a69f31cbfb20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d1347ed594a5d5bb5e0a69f31cbfb20">EXTI_FTSR_TR7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf100b4a2a76bcfdc3f7d0da8d39cc8b1">EXTI_FTSR_TR7_Pos</a>)</td></tr>
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<tr class="memitem:gaf408315e497b902922a9bf40a4c6f567" id="r_gaf408315e497b902922a9bf40a4c6f567"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf408315e497b902922a9bf40a4c6f567">EXTI_FTSR_TR7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d1347ed594a5d5bb5e0a69f31cbfb20">EXTI_FTSR_TR7_Msk</a></td></tr>
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<tr class="separator:gaf408315e497b902922a9bf40a4c6f567"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb1e5c22b9a7b2b53fbcc3d50a7ac80a" id="r_gadb1e5c22b9a7b2b53fbcc3d50a7ac80a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb1e5c22b9a7b2b53fbcc3d50a7ac80a">EXTI_FTSR_TR8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gadb1e5c22b9a7b2b53fbcc3d50a7ac80a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0b6b9ab34a5724cebedd0ccbf1ad65e" id="r_gaf0b6b9ab34a5724cebedd0ccbf1ad65e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0b6b9ab34a5724cebedd0ccbf1ad65e">EXTI_FTSR_TR8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb1e5c22b9a7b2b53fbcc3d50a7ac80a">EXTI_FTSR_TR8_Pos</a>)</td></tr>
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<tr class="separator:gaf0b6b9ab34a5724cebedd0ccbf1ad65e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00f1bded4d121e21116627b8e80784fc" id="r_ga00f1bded4d121e21116627b8e80784fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00f1bded4d121e21116627b8e80784fc">EXTI_FTSR_TR8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0b6b9ab34a5724cebedd0ccbf1ad65e">EXTI_FTSR_TR8_Msk</a></td></tr>
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<tr class="memitem:ga165ac2e2e46e32debc7efd99e258e608" id="r_ga165ac2e2e46e32debc7efd99e258e608"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga165ac2e2e46e32debc7efd99e258e608">EXTI_FTSR_TR9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga165ac2e2e46e32debc7efd99e258e608"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga898047db88343aeac8c05f39c4bc63e0" id="r_ga898047db88343aeac8c05f39c4bc63e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga898047db88343aeac8c05f39c4bc63e0">EXTI_FTSR_TR9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga165ac2e2e46e32debc7efd99e258e608">EXTI_FTSR_TR9_Pos</a>)</td></tr>
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<tr class="memitem:ga89f0c4de2b6acb75302d206b697f83ef" id="r_ga89f0c4de2b6acb75302d206b697f83ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89f0c4de2b6acb75302d206b697f83ef">EXTI_FTSR_TR9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga898047db88343aeac8c05f39c4bc63e0">EXTI_FTSR_TR9_Msk</a></td></tr>
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<tr class="separator:ga89f0c4de2b6acb75302d206b697f83ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0592581c7bd1ea908087aa319528fdae" id="r_ga0592581c7bd1ea908087aa319528fdae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0592581c7bd1ea908087aa319528fdae">EXTI_FTSR_TR10_Pos</a>   (10U)</td></tr>
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<tr class="memitem:ga8e6991a6c2f7e8fd99992d7623a31093" id="r_ga8e6991a6c2f7e8fd99992d7623a31093"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e6991a6c2f7e8fd99992d7623a31093">EXTI_FTSR_TR10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0592581c7bd1ea908087aa319528fdae">EXTI_FTSR_TR10_Pos</a>)</td></tr>
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<tr class="separator:ga8e6991a6c2f7e8fd99992d7623a31093"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9a2b80699a213f0d2b03658f21ad643" id="r_gac9a2b80699a213f0d2b03658f21ad643"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9a2b80699a213f0d2b03658f21ad643">EXTI_FTSR_TR10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e6991a6c2f7e8fd99992d7623a31093">EXTI_FTSR_TR10_Msk</a></td></tr>
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<tr class="separator:gac9a2b80699a213f0d2b03658f21ad643"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32ce99e8292f13831e1c8eaa79dc3554" id="r_ga32ce99e8292f13831e1c8eaa79dc3554"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32ce99e8292f13831e1c8eaa79dc3554">EXTI_FTSR_TR11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga32ce99e8292f13831e1c8eaa79dc3554"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac985e7db4d6a853c4411544878fd0551" id="r_gac985e7db4d6a853c4411544878fd0551"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac985e7db4d6a853c4411544878fd0551">EXTI_FTSR_TR11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga32ce99e8292f13831e1c8eaa79dc3554">EXTI_FTSR_TR11_Pos</a>)</td></tr>
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<tr class="separator:gac985e7db4d6a853c4411544878fd0551"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c74d4d520406a14c517784cdd5fc6ef" id="r_ga6c74d4d520406a14c517784cdd5fc6ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c74d4d520406a14c517784cdd5fc6ef">EXTI_FTSR_TR11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac985e7db4d6a853c4411544878fd0551">EXTI_FTSR_TR11_Msk</a></td></tr>
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<tr class="separator:ga6c74d4d520406a14c517784cdd5fc6ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49f1f39d43c981697a040fc94abbbfc1" id="r_ga49f1f39d43c981697a040fc94abbbfc1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49f1f39d43c981697a040fc94abbbfc1">EXTI_FTSR_TR12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga49f1f39d43c981697a040fc94abbbfc1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f1c99fa4436d7a5fad4632366db4462" id="r_ga3f1c99fa4436d7a5fad4632366db4462"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1c99fa4436d7a5fad4632366db4462">EXTI_FTSR_TR12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga49f1f39d43c981697a040fc94abbbfc1">EXTI_FTSR_TR12_Pos</a>)</td></tr>
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<tr class="separator:ga3f1c99fa4436d7a5fad4632366db4462"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3992511ec1785bdf107873b139d74245" id="r_ga3992511ec1785bdf107873b139d74245"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3992511ec1785bdf107873b139d74245">EXTI_FTSR_TR12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1c99fa4436d7a5fad4632366db4462">EXTI_FTSR_TR12_Msk</a></td></tr>
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<tr class="separator:ga3992511ec1785bdf107873b139d74245"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd86158859c108fbe911aff6498eb15b" id="r_gabd86158859c108fbe911aff6498eb15b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd86158859c108fbe911aff6498eb15b">EXTI_FTSR_TR13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gabd86158859c108fbe911aff6498eb15b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89275d329ff466aee9a8b226376eb9b7" id="r_ga89275d329ff466aee9a8b226376eb9b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89275d329ff466aee9a8b226376eb9b7">EXTI_FTSR_TR13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabd86158859c108fbe911aff6498eb15b">EXTI_FTSR_TR13_Pos</a>)</td></tr>
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<tr class="separator:ga89275d329ff466aee9a8b226376eb9b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0714519a1edcba4695f92f1bba70e825" id="r_ga0714519a1edcba4695f92f1bba70e825"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0714519a1edcba4695f92f1bba70e825">EXTI_FTSR_TR13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga89275d329ff466aee9a8b226376eb9b7">EXTI_FTSR_TR13_Msk</a></td></tr>
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<tr class="separator:ga0714519a1edcba4695f92f1bba70e825"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffd9b96b99f65602a7d5285d62b8c0ac" id="r_gaffd9b96b99f65602a7d5285d62b8c0ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffd9b96b99f65602a7d5285d62b8c0ac">EXTI_FTSR_TR14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gaffd9b96b99f65602a7d5285d62b8c0ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e2e56c2bfea3a94e5bc8905b5008dd0" id="r_ga4e2e56c2bfea3a94e5bc8905b5008dd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e2e56c2bfea3a94e5bc8905b5008dd0">EXTI_FTSR_TR14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaffd9b96b99f65602a7d5285d62b8c0ac">EXTI_FTSR_TR14_Pos</a>)</td></tr>
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<tr class="separator:ga4e2e56c2bfea3a94e5bc8905b5008dd0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b92577e64a95ef2069f1a56176d35ff" id="r_ga5b92577e64a95ef2069f1a56176d35ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b92577e64a95ef2069f1a56176d35ff">EXTI_FTSR_TR14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e2e56c2bfea3a94e5bc8905b5008dd0">EXTI_FTSR_TR14_Msk</a></td></tr>
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<tr class="separator:ga5b92577e64a95ef2069f1a56176d35ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5a3ca20b1ac9fdf5794fe609a3fe333" id="r_gaa5a3ca20b1ac9fdf5794fe609a3fe333"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5a3ca20b1ac9fdf5794fe609a3fe333">EXTI_FTSR_TR15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaa5a3ca20b1ac9fdf5794fe609a3fe333"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b78c01259464833376dbc4755fefc21" id="r_ga7b78c01259464833376dbc4755fefc21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b78c01259464833376dbc4755fefc21">EXTI_FTSR_TR15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5a3ca20b1ac9fdf5794fe609a3fe333">EXTI_FTSR_TR15_Pos</a>)</td></tr>
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<tr class="separator:ga7b78c01259464833376dbc4755fefc21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a6cc515f13ffe1a3620d06fa08addc7" id="r_ga2a6cc515f13ffe1a3620d06fa08addc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a6cc515f13ffe1a3620d06fa08addc7">EXTI_FTSR_TR15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b78c01259464833376dbc4755fefc21">EXTI_FTSR_TR15_Msk</a></td></tr>
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<tr class="separator:ga2a6cc515f13ffe1a3620d06fa08addc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b123b9f8f09d0d1fcb29f846279ce21" id="r_ga5b123b9f8f09d0d1fcb29f846279ce21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b123b9f8f09d0d1fcb29f846279ce21">EXTI_FTSR_TR16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga5b123b9f8f09d0d1fcb29f846279ce21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad43c9167b3d4af750254db5efaf97aa4" id="r_gad43c9167b3d4af750254db5efaf97aa4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad43c9167b3d4af750254db5efaf97aa4">EXTI_FTSR_TR16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b123b9f8f09d0d1fcb29f846279ce21">EXTI_FTSR_TR16_Pos</a>)</td></tr>
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<tr class="separator:gad43c9167b3d4af750254db5efaf97aa4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1b4b850094ccc48790a1e4616ceebd2" id="r_gaa1b4b850094ccc48790a1e4616ceebd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1b4b850094ccc48790a1e4616ceebd2">EXTI_FTSR_TR16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad43c9167b3d4af750254db5efaf97aa4">EXTI_FTSR_TR16_Msk</a></td></tr>
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<tr class="separator:gaa1b4b850094ccc48790a1e4616ceebd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf5a7f78ce681c3f1b7afbaf3471d1f4" id="r_gacf5a7f78ce681c3f1b7afbaf3471d1f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf5a7f78ce681c3f1b7afbaf3471d1f4">EXTI_FTSR_TR17_Pos</a>   (17U)</td></tr>
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<tr class="separator:gacf5a7f78ce681c3f1b7afbaf3471d1f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3170e25ad439045d2372d1e052cea88c" id="r_ga3170e25ad439045d2372d1e052cea88c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3170e25ad439045d2372d1e052cea88c">EXTI_FTSR_TR17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf5a7f78ce681c3f1b7afbaf3471d1f4">EXTI_FTSR_TR17_Pos</a>)</td></tr>
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<tr class="separator:ga3170e25ad439045d2372d1e052cea88c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga009e618c9563b3a8dcaec493006115c7" id="r_ga009e618c9563b3a8dcaec493006115c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga009e618c9563b3a8dcaec493006115c7">EXTI_FTSR_TR17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3170e25ad439045d2372d1e052cea88c">EXTI_FTSR_TR17_Msk</a></td></tr>
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<tr class="separator:ga009e618c9563b3a8dcaec493006115c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52a49bf16fd86f2e5f0c0cd439be375f" id="r_ga52a49bf16fd86f2e5f0c0cd439be375f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52a49bf16fd86f2e5f0c0cd439be375f">EXTI_FTSR_TR18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga52a49bf16fd86f2e5f0c0cd439be375f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac793e138d33f0b8106662bb5783b0eaf" id="r_gac793e138d33f0b8106662bb5783b0eaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac793e138d33f0b8106662bb5783b0eaf">EXTI_FTSR_TR18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52a49bf16fd86f2e5f0c0cd439be375f">EXTI_FTSR_TR18_Pos</a>)</td></tr>
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<tr class="separator:gac793e138d33f0b8106662bb5783b0eaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga405285cdc474ee20085b17ef1f61517e" id="r_ga405285cdc474ee20085b17ef1f61517e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga405285cdc474ee20085b17ef1f61517e">EXTI_FTSR_TR18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac793e138d33f0b8106662bb5783b0eaf">EXTI_FTSR_TR18_Msk</a></td></tr>
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<tr class="separator:ga405285cdc474ee20085b17ef1f61517e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf317413191ad372394192996edebfcb3" id="r_gaf317413191ad372394192996edebfcb3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf317413191ad372394192996edebfcb3">EXTI_FTSR_TR19_Pos</a>   (19U)</td></tr>
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<tr class="separator:gaf317413191ad372394192996edebfcb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1a59ec9892e009f734e6c7703af85c4" id="r_gaa1a59ec9892e009f734e6c7703af85c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1a59ec9892e009f734e6c7703af85c4">EXTI_FTSR_TR19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf317413191ad372394192996edebfcb3">EXTI_FTSR_TR19_Pos</a>)</td></tr>
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<tr class="separator:gaa1a59ec9892e009f734e6c7703af85c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1277527e2fa727fdec2dcc7a300ea1af" id="r_ga1277527e2fa727fdec2dcc7a300ea1af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1277527e2fa727fdec2dcc7a300ea1af">EXTI_FTSR_TR19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1a59ec9892e009f734e6c7703af85c4">EXTI_FTSR_TR19_Msk</a></td></tr>
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<tr class="separator:ga1277527e2fa727fdec2dcc7a300ea1af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga159e0d936264a23e36e44430355412c3" id="r_ga159e0d936264a23e36e44430355412c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga159e0d936264a23e36e44430355412c3">EXTI_FTSR_TR20_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga159e0d936264a23e36e44430355412c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f627753cee5eab2cc5111bc5698fd36" id="r_ga0f627753cee5eab2cc5111bc5698fd36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f627753cee5eab2cc5111bc5698fd36">EXTI_FTSR_TR20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga159e0d936264a23e36e44430355412c3">EXTI_FTSR_TR20_Pos</a>)</td></tr>
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<tr class="memitem:gae185289c161b407cdcd5ca185aca5477" id="r_gae185289c161b407cdcd5ca185aca5477"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae185289c161b407cdcd5ca185aca5477">EXTI_FTSR_TR20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f627753cee5eab2cc5111bc5698fd36">EXTI_FTSR_TR20_Msk</a></td></tr>
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<tr class="separator:gae185289c161b407cdcd5ca185aca5477"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53324986eef8e0f233b9d7c7650f88f8" id="r_ga53324986eef8e0f233b9d7c7650f88f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53324986eef8e0f233b9d7c7650f88f8">EXTI_FTSR_TR21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga53324986eef8e0f233b9d7c7650f88f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bb39db3d5a47c3e7baf4240b5738064" id="r_ga3bb39db3d5a47c3e7baf4240b5738064"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bb39db3d5a47c3e7baf4240b5738064">EXTI_FTSR_TR21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga53324986eef8e0f233b9d7c7650f88f8">EXTI_FTSR_TR21_Pos</a>)</td></tr>
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<tr class="separator:ga3bb39db3d5a47c3e7baf4240b5738064"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04957f9a7aa38bc50d6ac9340697a826" id="r_ga04957f9a7aa38bc50d6ac9340697a826"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04957f9a7aa38bc50d6ac9340697a826">EXTI_FTSR_TR21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bb39db3d5a47c3e7baf4240b5738064">EXTI_FTSR_TR21_Msk</a></td></tr>
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<tr class="separator:ga04957f9a7aa38bc50d6ac9340697a826"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf272ea16ee6c30f486255e71179f34d" id="r_gabf272ea16ee6c30f486255e71179f34d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf272ea16ee6c30f486255e71179f34d">EXTI_FTSR_TR22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gabf272ea16ee6c30f486255e71179f34d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf39fdb81f4c5e0e4a566369b17b1a88a" id="r_gaf39fdb81f4c5e0e4a566369b17b1a88a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf39fdb81f4c5e0e4a566369b17b1a88a">EXTI_FTSR_TR22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf272ea16ee6c30f486255e71179f34d">EXTI_FTSR_TR22_Pos</a>)</td></tr>
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<tr class="separator:gaf39fdb81f4c5e0e4a566369b17b1a88a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7931f3a5864584bc80de7ab3455517e" id="r_gaa7931f3a5864584bc80de7ab3455517e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7931f3a5864584bc80de7ab3455517e">EXTI_FTSR_TR22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf39fdb81f4c5e0e4a566369b17b1a88a">EXTI_FTSR_TR22_Msk</a></td></tr>
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<tr class="separator:gaa7931f3a5864584bc80de7ab3455517e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47cfabfaaaf3453afad037f2b4ee959d" id="r_ga47cfabfaaaf3453afad037f2b4ee959d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47cfabfaaaf3453afad037f2b4ee959d">EXTI_SWIER_SWIER0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga47cfabfaaaf3453afad037f2b4ee959d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaded47468bc0aade2a8c36333d64a3fc7" id="r_gaded47468bc0aade2a8c36333d64a3fc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaded47468bc0aade2a8c36333d64a3fc7">EXTI_SWIER_SWIER0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga47cfabfaaaf3453afad037f2b4ee959d">EXTI_SWIER_SWIER0_Pos</a>)</td></tr>
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<tr class="separator:gaded47468bc0aade2a8c36333d64a3fc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6df16d2e8010a2897888a4acf19cee3" id="r_gaa6df16d2e8010a2897888a4acf19cee3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6df16d2e8010a2897888a4acf19cee3">EXTI_SWIER_SWIER0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaded47468bc0aade2a8c36333d64a3fc7">EXTI_SWIER_SWIER0_Msk</a></td></tr>
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<tr class="separator:gaa6df16d2e8010a2897888a4acf19cee3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf7afd1d1f63c7a76bae06e5c5d86e96" id="r_gadf7afd1d1f63c7a76bae06e5c5d86e96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf7afd1d1f63c7a76bae06e5c5d86e96">EXTI_SWIER_SWIER1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gadf7afd1d1f63c7a76bae06e5c5d86e96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43b28416d9efdd9464c175f594ff0490" id="r_ga43b28416d9efdd9464c175f594ff0490"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43b28416d9efdd9464c175f594ff0490">EXTI_SWIER_SWIER1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf7afd1d1f63c7a76bae06e5c5d86e96">EXTI_SWIER_SWIER1_Pos</a>)</td></tr>
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<tr class="separator:ga43b28416d9efdd9464c175f594ff0490"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb0c3fa5a03204d743ae92ff925421ae" id="r_gaeb0c3fa5a03204d743ae92ff925421ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb0c3fa5a03204d743ae92ff925421ae">EXTI_SWIER_SWIER1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga43b28416d9efdd9464c175f594ff0490">EXTI_SWIER_SWIER1_Msk</a></td></tr>
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<tr class="separator:gaeb0c3fa5a03204d743ae92ff925421ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bc778d2738c9f6b76c560c98c0995c6" id="r_ga6bc778d2738c9f6b76c560c98c0995c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bc778d2738c9f6b76c560c98c0995c6">EXTI_SWIER_SWIER2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga6bc778d2738c9f6b76c560c98c0995c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga701fc135a83a7a43ca6a977fa51087e1" id="r_ga701fc135a83a7a43ca6a977fa51087e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga701fc135a83a7a43ca6a977fa51087e1">EXTI_SWIER_SWIER2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6bc778d2738c9f6b76c560c98c0995c6">EXTI_SWIER_SWIER2_Pos</a>)</td></tr>
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<tr class="separator:ga701fc135a83a7a43ca6a977fa51087e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bea1dbaf71e830dd357135524166f4c" id="r_ga6bea1dbaf71e830dd357135524166f4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bea1dbaf71e830dd357135524166f4c">EXTI_SWIER_SWIER2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga701fc135a83a7a43ca6a977fa51087e1">EXTI_SWIER_SWIER2_Msk</a></td></tr>
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<tr class="separator:ga6bea1dbaf71e830dd357135524166f4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaadaa259d663aebd65a50639e1907e5c" id="r_gaaadaa259d663aebd65a50639e1907e5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaadaa259d663aebd65a50639e1907e5c">EXTI_SWIER_SWIER3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaaadaa259d663aebd65a50639e1907e5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1adab50a513d2ffc1c7ec8c245bb4ce" id="r_gaf1adab50a513d2ffc1c7ec8c245bb4ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1adab50a513d2ffc1c7ec8c245bb4ce">EXTI_SWIER_SWIER3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaadaa259d663aebd65a50639e1907e5c">EXTI_SWIER_SWIER3_Pos</a>)</td></tr>
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<tr class="separator:gaf1adab50a513d2ffc1c7ec8c245bb4ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37395ac6729647ab5ee1fa4ca086c08a" id="r_ga37395ac6729647ab5ee1fa4ca086c08a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37395ac6729647ab5ee1fa4ca086c08a">EXTI_SWIER_SWIER3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1adab50a513d2ffc1c7ec8c245bb4ce">EXTI_SWIER_SWIER3_Msk</a></td></tr>
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<tr class="separator:ga37395ac6729647ab5ee1fa4ca086c08a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93c17eacb283557123595fb08107d9f5" id="r_ga93c17eacb283557123595fb08107d9f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93c17eacb283557123595fb08107d9f5">EXTI_SWIER_SWIER4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga93c17eacb283557123595fb08107d9f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cb85edd29e2bbdbb0ec3021c8f80e72" id="r_ga0cb85edd29e2bbdbb0ec3021c8f80e72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cb85edd29e2bbdbb0ec3021c8f80e72">EXTI_SWIER_SWIER4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga93c17eacb283557123595fb08107d9f5">EXTI_SWIER_SWIER4_Pos</a>)</td></tr>
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<tr class="separator:ga0cb85edd29e2bbdbb0ec3021c8f80e72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab051808f7a1ed9aaf43a3df90fc6a575" id="r_gab051808f7a1ed9aaf43a3df90fc6a575"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab051808f7a1ed9aaf43a3df90fc6a575">EXTI_SWIER_SWIER4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cb85edd29e2bbdbb0ec3021c8f80e72">EXTI_SWIER_SWIER4_Msk</a></td></tr>
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<tr class="separator:gab051808f7a1ed9aaf43a3df90fc6a575"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga626a1b735d1a60ffd3490c307dce91e5" id="r_ga626a1b735d1a60ffd3490c307dce91e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga626a1b735d1a60ffd3490c307dce91e5">EXTI_SWIER_SWIER5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga626a1b735d1a60ffd3490c307dce91e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9bb6ac1da4531f229770893e8803226" id="r_gab9bb6ac1da4531f229770893e8803226"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9bb6ac1da4531f229770893e8803226">EXTI_SWIER_SWIER5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga626a1b735d1a60ffd3490c307dce91e5">EXTI_SWIER_SWIER5_Pos</a>)</td></tr>
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<tr class="separator:gab9bb6ac1da4531f229770893e8803226"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5b4ace22acacac13ce106b2063a3977" id="r_gaa5b4ace22acacac13ce106b2063a3977"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5b4ace22acacac13ce106b2063a3977">EXTI_SWIER_SWIER5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9bb6ac1da4531f229770893e8803226">EXTI_SWIER_SWIER5_Msk</a></td></tr>
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<tr class="separator:gaa5b4ace22acacac13ce106b2063a3977"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac5de035fe3b407ebd937d15b85bb8a6" id="r_gaac5de035fe3b407ebd937d15b85bb8a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac5de035fe3b407ebd937d15b85bb8a6">EXTI_SWIER_SWIER6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaac5de035fe3b407ebd937d15b85bb8a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga820d4fc8485a8c681dd9deddccf85c64" id="r_ga820d4fc8485a8c681dd9deddccf85c64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga820d4fc8485a8c681dd9deddccf85c64">EXTI_SWIER_SWIER6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaac5de035fe3b407ebd937d15b85bb8a6">EXTI_SWIER_SWIER6_Pos</a>)</td></tr>
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<tr class="separator:ga820d4fc8485a8c681dd9deddccf85c64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8ad0142288597993852e4cf350f61ed" id="r_gad8ad0142288597993852e4cf350f61ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8ad0142288597993852e4cf350f61ed">EXTI_SWIER_SWIER6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga820d4fc8485a8c681dd9deddccf85c64">EXTI_SWIER_SWIER6_Msk</a></td></tr>
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<tr class="separator:gad8ad0142288597993852e4cf350f61ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d9dd65850bb89ff5205240324494035" id="r_ga0d9dd65850bb89ff5205240324494035"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d9dd65850bb89ff5205240324494035">EXTI_SWIER_SWIER7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga0d9dd65850bb89ff5205240324494035"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac444748417965f0a263e4a3f99c81c22" id="r_gac444748417965f0a263e4a3f99c81c22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac444748417965f0a263e4a3f99c81c22">EXTI_SWIER_SWIER7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d9dd65850bb89ff5205240324494035">EXTI_SWIER_SWIER7_Pos</a>)</td></tr>
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<tr class="separator:gac444748417965f0a263e4a3f99c81c22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdf8eab3e32cc03ca71f519a9111e28f" id="r_gabdf8eab3e32cc03ca71f519a9111e28f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdf8eab3e32cc03ca71f519a9111e28f">EXTI_SWIER_SWIER7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac444748417965f0a263e4a3f99c81c22">EXTI_SWIER_SWIER7_Msk</a></td></tr>
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<tr class="separator:gabdf8eab3e32cc03ca71f519a9111e28f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga606f473204836b050515446b252877c5" id="r_ga606f473204836b050515446b252877c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga606f473204836b050515446b252877c5">EXTI_SWIER_SWIER8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga606f473204836b050515446b252877c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga584d2b8877c26e45231b2194baba055a" id="r_ga584d2b8877c26e45231b2194baba055a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga584d2b8877c26e45231b2194baba055a">EXTI_SWIER_SWIER8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga606f473204836b050515446b252877c5">EXTI_SWIER_SWIER8_Pos</a>)</td></tr>
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<tr class="memitem:ga5e83a373926804449d500b115e9090ce" id="r_ga5e83a373926804449d500b115e9090ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e83a373926804449d500b115e9090ce">EXTI_SWIER_SWIER8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga584d2b8877c26e45231b2194baba055a">EXTI_SWIER_SWIER8_Msk</a></td></tr>
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<tr class="memitem:ga1d7f6e0def3861e207f4affc4f9755d4" id="r_ga1d7f6e0def3861e207f4affc4f9755d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d7f6e0def3861e207f4affc4f9755d4">EXTI_SWIER_SWIER9_Pos</a>   (9U)</td></tr>
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<tr class="memitem:ga2b275083074cfd7a32fc9af85b56509b" id="r_ga2b275083074cfd7a32fc9af85b56509b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b275083074cfd7a32fc9af85b56509b">EXTI_SWIER_SWIER9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d7f6e0def3861e207f4affc4f9755d4">EXTI_SWIER_SWIER9_Pos</a>)</td></tr>
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<tr class="separator:ga2b275083074cfd7a32fc9af85b56509b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab102aa929ffe463ffe9f2db651704a61" id="r_gab102aa929ffe463ffe9f2db651704a61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab102aa929ffe463ffe9f2db651704a61">EXTI_SWIER_SWIER9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b275083074cfd7a32fc9af85b56509b">EXTI_SWIER_SWIER9_Msk</a></td></tr>
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<tr class="separator:gab102aa929ffe463ffe9f2db651704a61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea5b7316b4b5dde162c9acd4e1d1a441" id="r_gaea5b7316b4b5dde162c9acd4e1d1a441"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea5b7316b4b5dde162c9acd4e1d1a441">EXTI_SWIER_SWIER10_Pos</a>   (10U)</td></tr>
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<tr class="memitem:ga64deb2466771c956d1e912ea09166925" id="r_ga64deb2466771c956d1e912ea09166925"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64deb2466771c956d1e912ea09166925">EXTI_SWIER_SWIER10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea5b7316b4b5dde162c9acd4e1d1a441">EXTI_SWIER_SWIER10_Pos</a>)</td></tr>
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<tr class="separator:ga64deb2466771c956d1e912ea09166925"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9d8691936b6cd80ff8e18c0bfe271d7" id="r_gae9d8691936b6cd80ff8e18c0bfe271d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9d8691936b6cd80ff8e18c0bfe271d7">EXTI_SWIER_SWIER10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64deb2466771c956d1e912ea09166925">EXTI_SWIER_SWIER10_Msk</a></td></tr>
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<tr class="separator:gae9d8691936b6cd80ff8e18c0bfe271d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37276792859bdf50b5bc358b78d4fbbd" id="r_ga37276792859bdf50b5bc358b78d4fbbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37276792859bdf50b5bc358b78d4fbbd">EXTI_SWIER_SWIER11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga37276792859bdf50b5bc358b78d4fbbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaace4933cca50b04988d34d48c7b659c3" id="r_gaace4933cca50b04988d34d48c7b659c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaace4933cca50b04988d34d48c7b659c3">EXTI_SWIER_SWIER11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga37276792859bdf50b5bc358b78d4fbbd">EXTI_SWIER_SWIER11_Pos</a>)</td></tr>
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<tr class="separator:gaace4933cca50b04988d34d48c7b659c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ab9fea9935608ec8ee7fb1e1ae049e7" id="r_ga7ab9fea9935608ec8ee7fb1e1ae049e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ab9fea9935608ec8ee7fb1e1ae049e7">EXTI_SWIER_SWIER11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaace4933cca50b04988d34d48c7b659c3">EXTI_SWIER_SWIER11_Msk</a></td></tr>
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<tr class="separator:ga7ab9fea9935608ec8ee7fb1e1ae049e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab28ccd43920facdbbb974c9e37c40961" id="r_gab28ccd43920facdbbb974c9e37c40961"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab28ccd43920facdbbb974c9e37c40961">EXTI_SWIER_SWIER12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gab28ccd43920facdbbb974c9e37c40961"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d4daf940040b81b93f70afed1ec62e1" id="r_ga7d4daf940040b81b93f70afed1ec62e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d4daf940040b81b93f70afed1ec62e1">EXTI_SWIER_SWIER12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab28ccd43920facdbbb974c9e37c40961">EXTI_SWIER_SWIER12_Pos</a>)</td></tr>
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<tr class="separator:ga7d4daf940040b81b93f70afed1ec62e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d67869db50c848f57633ebf00566539" id="r_ga5d67869db50c848f57633ebf00566539"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d67869db50c848f57633ebf00566539">EXTI_SWIER_SWIER12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d4daf940040b81b93f70afed1ec62e1">EXTI_SWIER_SWIER12_Msk</a></td></tr>
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<tr class="separator:ga5d67869db50c848f57633ebf00566539"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73603dbe0418523c2c83957265e7e65d" id="r_ga73603dbe0418523c2c83957265e7e65d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73603dbe0418523c2c83957265e7e65d">EXTI_SWIER_SWIER13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga73603dbe0418523c2c83957265e7e65d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa747f781753f3db0d1731ce24ad4ddd" id="r_gafa747f781753f3db0d1731ce24ad4ddd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa747f781753f3db0d1731ce24ad4ddd">EXTI_SWIER_SWIER13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga73603dbe0418523c2c83957265e7e65d">EXTI_SWIER_SWIER13_Pos</a>)</td></tr>
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<tr class="separator:gafa747f781753f3db0d1731ce24ad4ddd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga930a1d03fe3c32bd65a336ccee418826" id="r_ga930a1d03fe3c32bd65a336ccee418826"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga930a1d03fe3c32bd65a336ccee418826">EXTI_SWIER_SWIER13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafa747f781753f3db0d1731ce24ad4ddd">EXTI_SWIER_SWIER13_Msk</a></td></tr>
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<tr class="separator:ga930a1d03fe3c32bd65a336ccee418826"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4295bced15121047e453c21f0b32c4de" id="r_ga4295bced15121047e453c21f0b32c4de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4295bced15121047e453c21f0b32c4de">EXTI_SWIER_SWIER14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga4295bced15121047e453c21f0b32c4de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga405d264956ba9e06788545e2ad87413e" id="r_ga405d264956ba9e06788545e2ad87413e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga405d264956ba9e06788545e2ad87413e">EXTI_SWIER_SWIER14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4295bced15121047e453c21f0b32c4de">EXTI_SWIER_SWIER14_Pos</a>)</td></tr>
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<tr class="separator:ga405d264956ba9e06788545e2ad87413e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5d645db667cd63d1a9b91963c543a4b" id="r_gad5d645db667cd63d1a9b91963c543a4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5d645db667cd63d1a9b91963c543a4b">EXTI_SWIER_SWIER14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga405d264956ba9e06788545e2ad87413e">EXTI_SWIER_SWIER14_Msk</a></td></tr>
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<tr class="separator:gad5d645db667cd63d1a9b91963c543a4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe3550ed355b125e7e32503596d47d3b" id="r_gafe3550ed355b125e7e32503596d47d3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe3550ed355b125e7e32503596d47d3b">EXTI_SWIER_SWIER15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gafe3550ed355b125e7e32503596d47d3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga677582734fb712a69ae2d6fb3a3329b6" id="r_ga677582734fb712a69ae2d6fb3a3329b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga677582734fb712a69ae2d6fb3a3329b6">EXTI_SWIER_SWIER15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafe3550ed355b125e7e32503596d47d3b">EXTI_SWIER_SWIER15_Pos</a>)</td></tr>
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<tr class="separator:ga677582734fb712a69ae2d6fb3a3329b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b9e64d5a1779371fa4678713ab18e08" id="r_ga0b9e64d5a1779371fa4678713ab18e08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b9e64d5a1779371fa4678713ab18e08">EXTI_SWIER_SWIER15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga677582734fb712a69ae2d6fb3a3329b6">EXTI_SWIER_SWIER15_Msk</a></td></tr>
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<tr class="separator:ga0b9e64d5a1779371fa4678713ab18e08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb2a375858bd09f73db412291d9672c5" id="r_gabb2a375858bd09f73db412291d9672c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb2a375858bd09f73db412291d9672c5">EXTI_SWIER_SWIER16_Pos</a>   (16U)</td></tr>
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<tr class="separator:gabb2a375858bd09f73db412291d9672c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c201ce487fab3e1b835a718ee9f11bf" id="r_ga0c201ce487fab3e1b835a718ee9f11bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c201ce487fab3e1b835a718ee9f11bf">EXTI_SWIER_SWIER16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb2a375858bd09f73db412291d9672c5">EXTI_SWIER_SWIER16_Pos</a>)</td></tr>
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<tr class="separator:ga0c201ce487fab3e1b835a718ee9f11bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55b528743b11f4ab93ae97ee2e639b5b" id="r_ga55b528743b11f4ab93ae97ee2e639b5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55b528743b11f4ab93ae97ee2e639b5b">EXTI_SWIER_SWIER16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c201ce487fab3e1b835a718ee9f11bf">EXTI_SWIER_SWIER16_Msk</a></td></tr>
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<tr class="separator:ga55b528743b11f4ab93ae97ee2e639b5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a0e994273bfe6b3bdf630b68c673ce7" id="r_ga9a0e994273bfe6b3bdf630b68c673ce7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a0e994273bfe6b3bdf630b68c673ce7">EXTI_SWIER_SWIER17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga9a0e994273bfe6b3bdf630b68c673ce7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46bf902143efb4e89c7e20de1ed4f108" id="r_ga46bf902143efb4e89c7e20de1ed4f108"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46bf902143efb4e89c7e20de1ed4f108">EXTI_SWIER_SWIER17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a0e994273bfe6b3bdf630b68c673ce7">EXTI_SWIER_SWIER17_Pos</a>)</td></tr>
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<tr class="separator:ga46bf902143efb4e89c7e20de1ed4f108"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0da944251419887af3a87c86080fb455" id="r_ga0da944251419887af3a87c86080fb455"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0da944251419887af3a87c86080fb455">EXTI_SWIER_SWIER17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga46bf902143efb4e89c7e20de1ed4f108">EXTI_SWIER_SWIER17_Msk</a></td></tr>
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<tr class="separator:ga0da944251419887af3a87c86080fb455"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf33aa36748aefb6e66d4c2094a94518" id="r_gabf33aa36748aefb6e66d4c2094a94518"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf33aa36748aefb6e66d4c2094a94518">EXTI_SWIER_SWIER18_Pos</a>   (18U)</td></tr>
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<tr class="separator:gabf33aa36748aefb6e66d4c2094a94518"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9db116e94a090f461d8551591f829002" id="r_ga9db116e94a090f461d8551591f829002"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9db116e94a090f461d8551591f829002">EXTI_SWIER_SWIER18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf33aa36748aefb6e66d4c2094a94518">EXTI_SWIER_SWIER18_Pos</a>)</td></tr>
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<tr class="separator:ga9db116e94a090f461d8551591f829002"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab07aefbb7a8a18c9338b49d3b10ff068" id="r_gab07aefbb7a8a18c9338b49d3b10ff068"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab07aefbb7a8a18c9338b49d3b10ff068">EXTI_SWIER_SWIER18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9db116e94a090f461d8551591f829002">EXTI_SWIER_SWIER18_Msk</a></td></tr>
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<tr class="separator:gab07aefbb7a8a18c9338b49d3b10ff068"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab87df3a3d69a14c70b19e1d69c00a7c6" id="r_gab87df3a3d69a14c70b19e1d69c00a7c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab87df3a3d69a14c70b19e1d69c00a7c6">EXTI_SWIER_SWIER19_Pos</a>   (19U)</td></tr>
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<tr class="separator:gab87df3a3d69a14c70b19e1d69c00a7c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fddcdc43381e5daa122589d1a769c41" id="r_ga5fddcdc43381e5daa122589d1a769c41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fddcdc43381e5daa122589d1a769c41">EXTI_SWIER_SWIER19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab87df3a3d69a14c70b19e1d69c00a7c6">EXTI_SWIER_SWIER19_Pos</a>)</td></tr>
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<tr class="separator:ga5fddcdc43381e5daa122589d1a769c41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab7c48ac5522385cdb1d7882985f909b" id="r_gaab7c48ac5522385cdb1d7882985f909b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab7c48ac5522385cdb1d7882985f909b">EXTI_SWIER_SWIER19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fddcdc43381e5daa122589d1a769c41">EXTI_SWIER_SWIER19_Msk</a></td></tr>
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<tr class="separator:gaab7c48ac5522385cdb1d7882985f909b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2a016281fe0bb15bc0ca4ba9b11f97f" id="r_gac2a016281fe0bb15bc0ca4ba9b11f97f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2a016281fe0bb15bc0ca4ba9b11f97f">EXTI_SWIER_SWIER20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gac2a016281fe0bb15bc0ca4ba9b11f97f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed39df1c85fd5856af03e80a5f42e445" id="r_gaed39df1c85fd5856af03e80a5f42e445"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed39df1c85fd5856af03e80a5f42e445">EXTI_SWIER_SWIER20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2a016281fe0bb15bc0ca4ba9b11f97f">EXTI_SWIER_SWIER20_Pos</a>)</td></tr>
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<tr class="separator:gaed39df1c85fd5856af03e80a5f42e445"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac71bf967ecd31eaa57ba4064877a75b" id="r_gaac71bf967ecd31eaa57ba4064877a75b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac71bf967ecd31eaa57ba4064877a75b">EXTI_SWIER_SWIER20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaed39df1c85fd5856af03e80a5f42e445">EXTI_SWIER_SWIER20_Msk</a></td></tr>
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<tr class="separator:gaac71bf967ecd31eaa57ba4064877a75b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34163f6b2b814470372c81f5591efc8a" id="r_ga34163f6b2b814470372c81f5591efc8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34163f6b2b814470372c81f5591efc8a">EXTI_SWIER_SWIER21_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga34163f6b2b814470372c81f5591efc8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab53e7b09746e33f833ad4143bfeb4977" id="r_gab53e7b09746e33f833ad4143bfeb4977"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab53e7b09746e33f833ad4143bfeb4977">EXTI_SWIER_SWIER21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34163f6b2b814470372c81f5591efc8a">EXTI_SWIER_SWIER21_Pos</a>)</td></tr>
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<tr class="separator:gab53e7b09746e33f833ad4143bfeb4977"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23b409de4bca55f1f16cd309e58e88e6" id="r_ga23b409de4bca55f1f16cd309e58e88e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23b409de4bca55f1f16cd309e58e88e6">EXTI_SWIER_SWIER21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab53e7b09746e33f833ad4143bfeb4977">EXTI_SWIER_SWIER21_Msk</a></td></tr>
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<tr class="separator:ga23b409de4bca55f1f16cd309e58e88e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaedc6a73eb5e640541c1b13a822a315a" id="r_gaaedc6a73eb5e640541c1b13a822a315a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaedc6a73eb5e640541c1b13a822a315a">EXTI_SWIER_SWIER22_Pos</a>   (22U)</td></tr>
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<tr class="separator:gaaedc6a73eb5e640541c1b13a822a315a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf58cca6423fc2497df3e6a9ff5942ff3" id="r_gaf58cca6423fc2497df3e6a9ff5942ff3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf58cca6423fc2497df3e6a9ff5942ff3">EXTI_SWIER_SWIER22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaedc6a73eb5e640541c1b13a822a315a">EXTI_SWIER_SWIER22_Pos</a>)</td></tr>
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<tr class="separator:gaf58cca6423fc2497df3e6a9ff5942ff3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6bd7759b8d48c722f05ea3d2e64fc02" id="r_gad6bd7759b8d48c722f05ea3d2e64fc02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6bd7759b8d48c722f05ea3d2e64fc02">EXTI_SWIER_SWIER22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf58cca6423fc2497df3e6a9ff5942ff3">EXTI_SWIER_SWIER22_Msk</a></td></tr>
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<tr class="separator:gad6bd7759b8d48c722f05ea3d2e64fc02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad67b1832b8c6ebd37c07d774bf7b79c8" id="r_gad67b1832b8c6ebd37c07d774bf7b79c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad67b1832b8c6ebd37c07d774bf7b79c8">EXTI_PR_PR0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad67b1832b8c6ebd37c07d774bf7b79c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e52c51a9d888231a788288e42bb8596" id="r_ga6e52c51a9d888231a788288e42bb8596"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e52c51a9d888231a788288e42bb8596">EXTI_PR_PR0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad67b1832b8c6ebd37c07d774bf7b79c8">EXTI_PR_PR0_Pos</a>)</td></tr>
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<tr class="separator:ga6e52c51a9d888231a788288e42bb8596"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6da1c8a465606de1f90a74d369fbf25a" id="r_ga6da1c8a465606de1f90a74d369fbf25a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6da1c8a465606de1f90a74d369fbf25a">EXTI_PR_PR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e52c51a9d888231a788288e42bb8596">EXTI_PR_PR0_Msk</a></td></tr>
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<tr class="separator:ga6da1c8a465606de1f90a74d369fbf25a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7adebcc32984cb835d47179d34206eb" id="r_gac7adebcc32984cb835d47179d34206eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7adebcc32984cb835d47179d34206eb">EXTI_PR_PR1_Pos</a>   (1U)</td></tr>
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<tr class="separator:gac7adebcc32984cb835d47179d34206eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0ea95730ba8514076cc76945a01d850" id="r_gaa0ea95730ba8514076cc76945a01d850"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0ea95730ba8514076cc76945a01d850">EXTI_PR_PR1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac7adebcc32984cb835d47179d34206eb">EXTI_PR_PR1_Pos</a>)</td></tr>
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<tr class="separator:gaa0ea95730ba8514076cc76945a01d850"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b9b5f97edeccf442998a65b19e77f25" id="r_ga4b9b5f97edeccf442998a65b19e77f25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b9b5f97edeccf442998a65b19e77f25">EXTI_PR_PR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0ea95730ba8514076cc76945a01d850">EXTI_PR_PR1_Msk</a></td></tr>
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<tr class="separator:ga4b9b5f97edeccf442998a65b19e77f25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefa65f5976eeb883b977b391e3fbb690" id="r_gaefa65f5976eeb883b977b391e3fbb690"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefa65f5976eeb883b977b391e3fbb690">EXTI_PR_PR2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaefa65f5976eeb883b977b391e3fbb690"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa105697635cbab9ccf5f96efc9feec0d" id="r_gaa105697635cbab9ccf5f96efc9feec0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa105697635cbab9ccf5f96efc9feec0d">EXTI_PR_PR2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaefa65f5976eeb883b977b391e3fbb690">EXTI_PR_PR2_Pos</a>)</td></tr>
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<tr class="separator:gaa105697635cbab9ccf5f96efc9feec0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga085d2105381752a0aadc9be5a93ea665" id="r_ga085d2105381752a0aadc9be5a93ea665"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga085d2105381752a0aadc9be5a93ea665">EXTI_PR_PR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa105697635cbab9ccf5f96efc9feec0d">EXTI_PR_PR2_Msk</a></td></tr>
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<tr class="separator:ga085d2105381752a0aadc9be5a93ea665"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad56d3f9d10fd4c75bf4ba756e3778ea0" id="r_gad56d3f9d10fd4c75bf4ba756e3778ea0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad56d3f9d10fd4c75bf4ba756e3778ea0">EXTI_PR_PR3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gad56d3f9d10fd4c75bf4ba756e3778ea0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbe8a3ee648b4cf47f51e435b8644cee" id="r_gacbe8a3ee648b4cf47f51e435b8644cee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbe8a3ee648b4cf47f51e435b8644cee">EXTI_PR_PR3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad56d3f9d10fd4c75bf4ba756e3778ea0">EXTI_PR_PR3_Pos</a>)</td></tr>
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<tr class="separator:gacbe8a3ee648b4cf47f51e435b8644cee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga064dab3e0d5689b92125713100555ce0" id="r_ga064dab3e0d5689b92125713100555ce0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga064dab3e0d5689b92125713100555ce0">EXTI_PR_PR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacbe8a3ee648b4cf47f51e435b8644cee">EXTI_PR_PR3_Msk</a></td></tr>
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<tr class="separator:ga064dab3e0d5689b92125713100555ce0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58443521d982443a49db3fb2c273f5e4" id="r_ga58443521d982443a49db3fb2c273f5e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58443521d982443a49db3fb2c273f5e4">EXTI_PR_PR4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga58443521d982443a49db3fb2c273f5e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9465307df267001826deb47a946dab61" id="r_ga9465307df267001826deb47a946dab61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9465307df267001826deb47a946dab61">EXTI_PR_PR4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58443521d982443a49db3fb2c273f5e4">EXTI_PR_PR4_Pos</a>)</td></tr>
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<tr class="separator:ga9465307df267001826deb47a946dab61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14f73b3693b3353a006d360cb8fd2ddc" id="r_ga14f73b3693b3353a006d360cb8fd2ddc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14f73b3693b3353a006d360cb8fd2ddc">EXTI_PR_PR4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9465307df267001826deb47a946dab61">EXTI_PR_PR4_Msk</a></td></tr>
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<tr class="separator:ga14f73b3693b3353a006d360cb8fd2ddc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab011cd54f79dd8093ed093c53f9a69f5" id="r_gab011cd54f79dd8093ed093c53f9a69f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab011cd54f79dd8093ed093c53f9a69f5">EXTI_PR_PR5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gab011cd54f79dd8093ed093c53f9a69f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b096f7d09eed26b05531f8b0dbe239c" id="r_ga7b096f7d09eed26b05531f8b0dbe239c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b096f7d09eed26b05531f8b0dbe239c">EXTI_PR_PR5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab011cd54f79dd8093ed093c53f9a69f5">EXTI_PR_PR5_Pos</a>)</td></tr>
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<tr class="separator:ga7b096f7d09eed26b05531f8b0dbe239c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga319e167fa6e112061997d9a8d79f02f8" id="r_ga319e167fa6e112061997d9a8d79f02f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga319e167fa6e112061997d9a8d79f02f8">EXTI_PR_PR5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b096f7d09eed26b05531f8b0dbe239c">EXTI_PR_PR5_Msk</a></td></tr>
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<tr class="separator:ga319e167fa6e112061997d9a8d79f02f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga348bfafc8c5751e74b93c27f2ddce116" id="r_ga348bfafc8c5751e74b93c27f2ddce116"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga348bfafc8c5751e74b93c27f2ddce116">EXTI_PR_PR6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga348bfafc8c5751e74b93c27f2ddce116"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae216f090307338513e0c48b792ff4380" id="r_gae216f090307338513e0c48b792ff4380"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae216f090307338513e0c48b792ff4380">EXTI_PR_PR6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga348bfafc8c5751e74b93c27f2ddce116">EXTI_PR_PR6_Pos</a>)</td></tr>
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<tr class="separator:gae216f090307338513e0c48b792ff4380"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6f47cd1f602692258985784ed5e8e76" id="r_gaf6f47cd1f602692258985784ed5e8e76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6f47cd1f602692258985784ed5e8e76">EXTI_PR_PR6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae216f090307338513e0c48b792ff4380">EXTI_PR_PR6_Msk</a></td></tr>
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<tr class="separator:gaf6f47cd1f602692258985784ed5e8e76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41fd7463743a65921d47e3e888e22fbf" id="r_ga41fd7463743a65921d47e3e888e22fbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41fd7463743a65921d47e3e888e22fbf">EXTI_PR_PR7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga41fd7463743a65921d47e3e888e22fbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81bf1c350de28d01e9d252a2a7907a1c" id="r_ga81bf1c350de28d01e9d252a2a7907a1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81bf1c350de28d01e9d252a2a7907a1c">EXTI_PR_PR7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga41fd7463743a65921d47e3e888e22fbf">EXTI_PR_PR7_Pos</a>)</td></tr>
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<tr class="separator:ga81bf1c350de28d01e9d252a2a7907a1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa17ea7e3fb89e98fd6a232f453fcff9e" id="r_gaa17ea7e3fb89e98fd6a232f453fcff9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa17ea7e3fb89e98fd6a232f453fcff9e">EXTI_PR_PR7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga81bf1c350de28d01e9d252a2a7907a1c">EXTI_PR_PR7_Msk</a></td></tr>
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<tr class="separator:gaa17ea7e3fb89e98fd6a232f453fcff9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06e264ce486fde316beef4d01b07377d" id="r_ga06e264ce486fde316beef4d01b07377d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06e264ce486fde316beef4d01b07377d">EXTI_PR_PR8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga06e264ce486fde316beef4d01b07377d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf15f6df00912ea82ed99154c1824543" id="r_gabf15f6df00912ea82ed99154c1824543"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf15f6df00912ea82ed99154c1824543">EXTI_PR_PR8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga06e264ce486fde316beef4d01b07377d">EXTI_PR_PR8_Pos</a>)</td></tr>
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<tr class="separator:gabf15f6df00912ea82ed99154c1824543"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa82e0dcb4961a32a9b7ebdf30493156d" id="r_gaa82e0dcb4961a32a9b7ebdf30493156d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa82e0dcb4961a32a9b7ebdf30493156d">EXTI_PR_PR8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabf15f6df00912ea82ed99154c1824543">EXTI_PR_PR8_Msk</a></td></tr>
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<tr class="separator:gaa82e0dcb4961a32a9b7ebdf30493156d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74df770efeeac2a51b21229994b265e8" id="r_ga74df770efeeac2a51b21229994b265e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74df770efeeac2a51b21229994b265e8">EXTI_PR_PR9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga74df770efeeac2a51b21229994b265e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5c48dd0cba2bfc3f1cbae965d145019" id="r_gaf5c48dd0cba2bfc3f1cbae965d145019"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5c48dd0cba2bfc3f1cbae965d145019">EXTI_PR_PR9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga74df770efeeac2a51b21229994b265e8">EXTI_PR_PR9_Pos</a>)</td></tr>
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<tr class="separator:gaf5c48dd0cba2bfc3f1cbae965d145019"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2fcc64f03d79af531febc077f45c48eb" id="r_ga2fcc64f03d79af531febc077f45c48eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fcc64f03d79af531febc077f45c48eb">EXTI_PR_PR9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5c48dd0cba2bfc3f1cbae965d145019">EXTI_PR_PR9_Msk</a></td></tr>
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<tr class="separator:ga2fcc64f03d79af531febc077f45c48eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f38ede7f65d599654716b9c70119997" id="r_ga3f38ede7f65d599654716b9c70119997"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f38ede7f65d599654716b9c70119997">EXTI_PR_PR10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga3f38ede7f65d599654716b9c70119997"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19900075592fba3fc4a6641c5a44a4b4" id="r_ga19900075592fba3fc4a6641c5a44a4b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19900075592fba3fc4a6641c5a44a4b4">EXTI_PR_PR10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f38ede7f65d599654716b9c70119997">EXTI_PR_PR10_Pos</a>)</td></tr>
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<tr class="separator:ga19900075592fba3fc4a6641c5a44a4b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ef8e9c691b95763007ed228e98fa108" id="r_ga1ef8e9c691b95763007ed228e98fa108"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ef8e9c691b95763007ed228e98fa108">EXTI_PR_PR10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga19900075592fba3fc4a6641c5a44a4b4">EXTI_PR_PR10_Msk</a></td></tr>
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<tr class="separator:ga1ef8e9c691b95763007ed228e98fa108"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0b7515b407f5831dc120540379ab0ee" id="r_gaf0b7515b407f5831dc120540379ab0ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0b7515b407f5831dc120540379ab0ee">EXTI_PR_PR11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaf0b7515b407f5831dc120540379ab0ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80e7dba5b45bb3fa090607a33ea4b4b7" id="r_ga80e7dba5b45bb3fa090607a33ea4b4b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80e7dba5b45bb3fa090607a33ea4b4b7">EXTI_PR_PR11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0b7515b407f5831dc120540379ab0ee">EXTI_PR_PR11_Pos</a>)</td></tr>
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<tr class="separator:ga80e7dba5b45bb3fa090607a33ea4b4b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga144f1a41abb7b87a1619c15ba5fb548b" id="r_ga144f1a41abb7b87a1619c15ba5fb548b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga144f1a41abb7b87a1619c15ba5fb548b">EXTI_PR_PR11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga80e7dba5b45bb3fa090607a33ea4b4b7">EXTI_PR_PR11_Msk</a></td></tr>
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<tr class="separator:ga144f1a41abb7b87a1619c15ba5fb548b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe319cbf2bf25f1854993b7e9a88c02e" id="r_gabe319cbf2bf25f1854993b7e9a88c02e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe319cbf2bf25f1854993b7e9a88c02e">EXTI_PR_PR12_Pos</a>   (12U)</td></tr>
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<tr class="separator:gabe319cbf2bf25f1854993b7e9a88c02e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a607029be3ca6159090afbf66b84d88" id="r_ga0a607029be3ca6159090afbf66b84d88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a607029be3ca6159090afbf66b84d88">EXTI_PR_PR12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabe319cbf2bf25f1854993b7e9a88c02e">EXTI_PR_PR12_Pos</a>)</td></tr>
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<tr class="separator:ga0a607029be3ca6159090afbf66b84d88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1a68025056b8c84bb13635af5e2a07c" id="r_gae1a68025056b8c84bb13635af5e2a07c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1a68025056b8c84bb13635af5e2a07c">EXTI_PR_PR12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a607029be3ca6159090afbf66b84d88">EXTI_PR_PR12_Msk</a></td></tr>
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<tr class="separator:gae1a68025056b8c84bb13635af5e2a07c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa74c6b6143b3874744573c9ab8f30f65" id="r_gaa74c6b6143b3874744573c9ab8f30f65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa74c6b6143b3874744573c9ab8f30f65">EXTI_PR_PR13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaa74c6b6143b3874744573c9ab8f30f65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46b3cd3e008be5d766a085378dbde61e" id="r_ga46b3cd3e008be5d766a085378dbde61e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46b3cd3e008be5d766a085378dbde61e">EXTI_PR_PR13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa74c6b6143b3874744573c9ab8f30f65">EXTI_PR_PR13_Pos</a>)</td></tr>
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<tr class="separator:ga46b3cd3e008be5d766a085378dbde61e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3471c79d5b19813785387504a1a5f0c4" id="r_ga3471c79d5b19813785387504a1a5f0c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3471c79d5b19813785387504a1a5f0c4">EXTI_PR_PR13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga46b3cd3e008be5d766a085378dbde61e">EXTI_PR_PR13_Msk</a></td></tr>
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<tr class="separator:ga3471c79d5b19813785387504a1a5f0c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada52a67e5e44c06a2e40c3d4c721b345" id="r_gada52a67e5e44c06a2e40c3d4c721b345"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada52a67e5e44c06a2e40c3d4c721b345">EXTI_PR_PR14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gada52a67e5e44c06a2e40c3d4c721b345"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga845983f32b8eccfafede2ece6a9371a1" id="r_ga845983f32b8eccfafede2ece6a9371a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga845983f32b8eccfafede2ece6a9371a1">EXTI_PR_PR14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada52a67e5e44c06a2e40c3d4c721b345">EXTI_PR_PR14_Pos</a>)</td></tr>
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<tr class="separator:ga845983f32b8eccfafede2ece6a9371a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5396ec2dbbee9d7585224fa12273598" id="r_gae5396ec2dbbee9d7585224fa12273598"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5396ec2dbbee9d7585224fa12273598">EXTI_PR_PR14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga845983f32b8eccfafede2ece6a9371a1">EXTI_PR_PR14_Msk</a></td></tr>
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<tr class="separator:gae5396ec2dbbee9d7585224fa12273598"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d396fd4e0a34ebb0d44d2eb53daa753" id="r_ga9d396fd4e0a34ebb0d44d2eb53daa753"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d396fd4e0a34ebb0d44d2eb53daa753">EXTI_PR_PR15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga9d396fd4e0a34ebb0d44d2eb53daa753"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac665a7df31dbb829ee5e8c92b35d1e94" id="r_gac665a7df31dbb829ee5e8c92b35d1e94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac665a7df31dbb829ee5e8c92b35d1e94">EXTI_PR_PR15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d396fd4e0a34ebb0d44d2eb53daa753">EXTI_PR_PR15_Pos</a>)</td></tr>
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<tr class="separator:gac665a7df31dbb829ee5e8c92b35d1e94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga149f9d9d6c1aab867734b59db1117c41" id="r_ga149f9d9d6c1aab867734b59db1117c41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga149f9d9d6c1aab867734b59db1117c41">EXTI_PR_PR15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac665a7df31dbb829ee5e8c92b35d1e94">EXTI_PR_PR15_Msk</a></td></tr>
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<tr class="separator:ga149f9d9d6c1aab867734b59db1117c41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71810ea68a9e4297e245dacdfe77855a" id="r_ga71810ea68a9e4297e245dacdfe77855a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71810ea68a9e4297e245dacdfe77855a">EXTI_PR_PR16_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga71810ea68a9e4297e245dacdfe77855a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1577079526c7f1959e2e0c6c3dd8a4e4" id="r_ga1577079526c7f1959e2e0c6c3dd8a4e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1577079526c7f1959e2e0c6c3dd8a4e4">EXTI_PR_PR16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71810ea68a9e4297e245dacdfe77855a">EXTI_PR_PR16_Pos</a>)</td></tr>
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<tr class="separator:ga1577079526c7f1959e2e0c6c3dd8a4e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa47e5b07d5a407198e09f05262f18bba" id="r_gaa47e5b07d5a407198e09f05262f18bba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa47e5b07d5a407198e09f05262f18bba">EXTI_PR_PR16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1577079526c7f1959e2e0c6c3dd8a4e4">EXTI_PR_PR16_Msk</a></td></tr>
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<tr class="separator:gaa47e5b07d5a407198e09f05262f18bba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c42d3340997c553862f81db64944af9" id="r_ga6c42d3340997c553862f81db64944af9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c42d3340997c553862f81db64944af9">EXTI_PR_PR17_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga6c42d3340997c553862f81db64944af9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60b0021b076cb2e50a546abdc74ff497" id="r_ga60b0021b076cb2e50a546abdc74ff497"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60b0021b076cb2e50a546abdc74ff497">EXTI_PR_PR17_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c42d3340997c553862f81db64944af9">EXTI_PR_PR17_Pos</a>)</td></tr>
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<tr class="separator:ga60b0021b076cb2e50a546abdc74ff497"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbc7d82eb61e2adf0a955ef0cc97690f" id="r_gadbc7d82eb61e2adf0a955ef0cc97690f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbc7d82eb61e2adf0a955ef0cc97690f">EXTI_PR_PR17</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga60b0021b076cb2e50a546abdc74ff497">EXTI_PR_PR17_Msk</a></td></tr>
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<tr class="separator:gadbc7d82eb61e2adf0a955ef0cc97690f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65cfa57b6c19a9a31eb05adfbb24399a" id="r_ga65cfa57b6c19a9a31eb05adfbb24399a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65cfa57b6c19a9a31eb05adfbb24399a">EXTI_PR_PR18_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga65cfa57b6c19a9a31eb05adfbb24399a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09184330e3d3e7839d58dec6b07c284a" id="r_ga09184330e3d3e7839d58dec6b07c284a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09184330e3d3e7839d58dec6b07c284a">EXTI_PR_PR18_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga65cfa57b6c19a9a31eb05adfbb24399a">EXTI_PR_PR18_Pos</a>)</td></tr>
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<tr class="separator:ga09184330e3d3e7839d58dec6b07c284a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga541810a93fbf4cdd9b39f2717f37240d" id="r_ga541810a93fbf4cdd9b39f2717f37240d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga541810a93fbf4cdd9b39f2717f37240d">EXTI_PR_PR18</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga09184330e3d3e7839d58dec6b07c284a">EXTI_PR_PR18_Msk</a></td></tr>
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<tr class="separator:ga541810a93fbf4cdd9b39f2717f37240d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a38e5f6a0896bb0c6c2f3e32a5d51f8" id="r_ga9a38e5f6a0896bb0c6c2f3e32a5d51f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a38e5f6a0896bb0c6c2f3e32a5d51f8">EXTI_PR_PR19_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga9a38e5f6a0896bb0c6c2f3e32a5d51f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2b3167c29bb083e4c0e025846069a78" id="r_gae2b3167c29bb083e4c0e025846069a78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2b3167c29bb083e4c0e025846069a78">EXTI_PR_PR19_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a38e5f6a0896bb0c6c2f3e32a5d51f8">EXTI_PR_PR19_Pos</a>)</td></tr>
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<tr class="separator:gae2b3167c29bb083e4c0e025846069a78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41e43af631a30492e09e5fd5c50f47f5" id="r_ga41e43af631a30492e09e5fd5c50f47f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41e43af631a30492e09e5fd5c50f47f5">EXTI_PR_PR19</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae2b3167c29bb083e4c0e025846069a78">EXTI_PR_PR19_Msk</a></td></tr>
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<tr class="separator:ga41e43af631a30492e09e5fd5c50f47f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3d5ef04e855f2eb705305eba6cf00b9" id="r_gac3d5ef04e855f2eb705305eba6cf00b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3d5ef04e855f2eb705305eba6cf00b9">EXTI_PR_PR20_Pos</a>   (20U)</td></tr>
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<tr class="separator:gac3d5ef04e855f2eb705305eba6cf00b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac02bf4106a2d978a81fc825c808eace4" id="r_gac02bf4106a2d978a81fc825c808eace4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac02bf4106a2d978a81fc825c808eace4">EXTI_PR_PR20_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3d5ef04e855f2eb705305eba6cf00b9">EXTI_PR_PR20_Pos</a>)</td></tr>
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<tr class="separator:gac02bf4106a2d978a81fc825c808eace4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39358e6261a245eba447dfc1a1842e32" id="r_ga39358e6261a245eba447dfc1a1842e32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39358e6261a245eba447dfc1a1842e32">EXTI_PR_PR20</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac02bf4106a2d978a81fc825c808eace4">EXTI_PR_PR20_Msk</a></td></tr>
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<tr class="separator:ga39358e6261a245eba447dfc1a1842e32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad693094b03aec71eeca641ef0739d950" id="r_gad693094b03aec71eeca641ef0739d950"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad693094b03aec71eeca641ef0739d950">EXTI_PR_PR21_Pos</a>   (21U)</td></tr>
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<tr class="separator:gad693094b03aec71eeca641ef0739d950"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe3b7c51abb06113eb6b53ca2c963fba" id="r_gabe3b7c51abb06113eb6b53ca2c963fba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe3b7c51abb06113eb6b53ca2c963fba">EXTI_PR_PR21_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad693094b03aec71eeca641ef0739d950">EXTI_PR_PR21_Pos</a>)</td></tr>
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<tr class="separator:gabe3b7c51abb06113eb6b53ca2c963fba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac14b609a68b5c4cb4a20fb24e34954df" id="r_gac14b609a68b5c4cb4a20fb24e34954df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac14b609a68b5c4cb4a20fb24e34954df">EXTI_PR_PR21</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe3b7c51abb06113eb6b53ca2c963fba">EXTI_PR_PR21_Msk</a></td></tr>
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<tr class="separator:gac14b609a68b5c4cb4a20fb24e34954df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d26bbce3e69e8c80b67e81db99cc2ff" id="r_ga9d26bbce3e69e8c80b67e81db99cc2ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d26bbce3e69e8c80b67e81db99cc2ff">EXTI_PR_PR22_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga9d26bbce3e69e8c80b67e81db99cc2ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa13b7a89ed2d6deef9017757d311e52a" id="r_gaa13b7a89ed2d6deef9017757d311e52a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa13b7a89ed2d6deef9017757d311e52a">EXTI_PR_PR22_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d26bbce3e69e8c80b67e81db99cc2ff">EXTI_PR_PR22_Pos</a>)</td></tr>
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<tr class="separator:gaa13b7a89ed2d6deef9017757d311e52a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8199f21c468deeb2685865c26770ac07" id="r_ga8199f21c468deeb2685865c26770ac07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8199f21c468deeb2685865c26770ac07">EXTI_PR_PR22</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa13b7a89ed2d6deef9017757d311e52a">EXTI_PR_PR22_Msk</a></td></tr>
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<tr class="separator:ga8199f21c468deeb2685865c26770ac07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd27f57311268ed1ad0ddb1a207ce9a4" id="r_gacd27f57311268ed1ad0ddb1a207ce9a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd27f57311268ed1ad0ddb1a207ce9a4">FLASH_ACR_LATENCY_Pos</a>   (0U)</td></tr>
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<tr class="separator:gacd27f57311268ed1ad0ddb1a207ce9a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdcd07c55bf5197e31d5ad9ab61747a3" id="r_gabdcd07c55bf5197e31d5ad9ab61747a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdcd07c55bf5197e31d5ad9ab61747a3">FLASH_ACR_LATENCY_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacd27f57311268ed1ad0ddb1a207ce9a4">FLASH_ACR_LATENCY_Pos</a>)</td></tr>
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<tr class="separator:gabdcd07c55bf5197e31d5ad9ab61747a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef5e44cbb084160a6004ca9951ec7318" id="r_gaef5e44cbb084160a6004ca9951ec7318"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef5e44cbb084160a6004ca9951ec7318">FLASH_ACR_LATENCY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabdcd07c55bf5197e31d5ad9ab61747a3">FLASH_ACR_LATENCY_Msk</a></td></tr>
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<tr class="separator:gaef5e44cbb084160a6004ca9951ec7318"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga936324709ea40109331b76849da2c8b2" id="r_ga936324709ea40109331b76849da2c8b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga936324709ea40109331b76849da2c8b2">FLASH_ACR_LATENCY_0WS</a>   0x00000000U</td></tr>
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<tr class="separator:ga936324709ea40109331b76849da2c8b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec66af244e6afb5bbf9816d7c76e1621" id="r_gaec66af244e6afb5bbf9816d7c76e1621"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec66af244e6afb5bbf9816d7c76e1621">FLASH_ACR_LATENCY_1WS</a>   0x00000001U</td></tr>
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<tr class="separator:gaec66af244e6afb5bbf9816d7c76e1621"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9b09ca8db6df455d0b8f810f8521257" id="r_gad9b09ca8db6df455d0b8f810f8521257"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9b09ca8db6df455d0b8f810f8521257">FLASH_ACR_LATENCY_2WS</a>   0x00000002U</td></tr>
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<tr class="separator:gad9b09ca8db6df455d0b8f810f8521257"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3437dcee177845a407919d3b2d9bd063" id="r_ga3437dcee177845a407919d3b2d9bd063"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3437dcee177845a407919d3b2d9bd063">FLASH_ACR_LATENCY_3WS</a>   0x00000003U</td></tr>
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<tr class="separator:ga3437dcee177845a407919d3b2d9bd063"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3594f2a9e12213efe75cd7df646e1ad" id="r_gad3594f2a9e12213efe75cd7df646e1ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3594f2a9e12213efe75cd7df646e1ad">FLASH_ACR_LATENCY_4WS</a>   0x00000004U</td></tr>
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<tr class="separator:gad3594f2a9e12213efe75cd7df646e1ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67e55ca49f028a701d0c81420a6e2918" id="r_ga67e55ca49f028a701d0c81420a6e2918"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67e55ca49f028a701d0c81420a6e2918">FLASH_ACR_LATENCY_5WS</a>   0x00000005U</td></tr>
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<tr class="separator:ga67e55ca49f028a701d0c81420a6e2918"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3019ff197b4fd698e9625c9abb67f4be" id="r_ga3019ff197b4fd698e9625c9abb67f4be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3019ff197b4fd698e9625c9abb67f4be">FLASH_ACR_LATENCY_6WS</a>   0x00000006U</td></tr>
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<tr class="separator:ga3019ff197b4fd698e9625c9abb67f4be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa164c6e6fdfcae274a84dc87ca87b95e" id="r_gaa164c6e6fdfcae274a84dc87ca87b95e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa164c6e6fdfcae274a84dc87ca87b95e">FLASH_ACR_LATENCY_7WS</a>   0x00000007U</td></tr>
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<tr class="separator:gaa164c6e6fdfcae274a84dc87ca87b95e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf1b922e6400999bfabcde78d1c6f59b" id="r_gaaf1b922e6400999bfabcde78d1c6f59b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf1b922e6400999bfabcde78d1c6f59b">FLASH_ACR_PRFTEN_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaaf1b922e6400999bfabcde78d1c6f59b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga727504c465ce30a499631159bc419179" id="r_ga727504c465ce30a499631159bc419179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga727504c465ce30a499631159bc419179">FLASH_ACR_PRFTEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf1b922e6400999bfabcde78d1c6f59b">FLASH_ACR_PRFTEN_Pos</a>)</td></tr>
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<tr class="separator:ga727504c465ce30a499631159bc419179"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga082e7e91fffee86db39676396d01a8e0" id="r_ga082e7e91fffee86db39676396d01a8e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga082e7e91fffee86db39676396d01a8e0">FLASH_ACR_PRFTEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga727504c465ce30a499631159bc419179">FLASH_ACR_PRFTEN_Msk</a></td></tr>
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<tr class="separator:ga082e7e91fffee86db39676396d01a8e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2045375967b3774ee2a00f3f3de10ad" id="r_gaf2045375967b3774ee2a00f3f3de10ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2045375967b3774ee2a00f3f3de10ad">FLASH_ACR_ICEN_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaf2045375967b3774ee2a00f3f3de10ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95b43999203bce2ccdea6eba1f9925b9" id="r_ga95b43999203bce2ccdea6eba1f9925b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95b43999203bce2ccdea6eba1f9925b9">FLASH_ACR_ICEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2045375967b3774ee2a00f3f3de10ad">FLASH_ACR_ICEN_Pos</a>)</td></tr>
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<tr class="separator:ga95b43999203bce2ccdea6eba1f9925b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51d8b1dd2c46942d377c579a38dce711" id="r_ga51d8b1dd2c46942d377c579a38dce711"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51d8b1dd2c46942d377c579a38dce711">FLASH_ACR_ICEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga95b43999203bce2ccdea6eba1f9925b9">FLASH_ACR_ICEN_Msk</a></td></tr>
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<tr class="separator:ga51d8b1dd2c46942d377c579a38dce711"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga168563c4043c04251fc1524f6780a18e" id="r_ga168563c4043c04251fc1524f6780a18e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga168563c4043c04251fc1524f6780a18e">FLASH_ACR_DCEN_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga168563c4043c04251fc1524f6780a18e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4d8386ca0c38a2a5546714a068e63d5" id="r_gac4d8386ca0c38a2a5546714a068e63d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4d8386ca0c38a2a5546714a068e63d5">FLASH_ACR_DCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga168563c4043c04251fc1524f6780a18e">FLASH_ACR_DCEN_Pos</a>)</td></tr>
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<tr class="separator:gac4d8386ca0c38a2a5546714a068e63d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a9a5cc3aa05dc62264addab1008c896" id="r_ga5a9a5cc3aa05dc62264addab1008c896"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a9a5cc3aa05dc62264addab1008c896">FLASH_ACR_DCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4d8386ca0c38a2a5546714a068e63d5">FLASH_ACR_DCEN_Msk</a></td></tr>
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<tr class="memitem:ga5a8676f7e028638743d0097921be11e5" id="r_ga5a8676f7e028638743d0097921be11e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a8676f7e028638743d0097921be11e5">FLASH_ACR_ICRST_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga5a8676f7e028638743d0097921be11e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga009d7ec202f2ec4e6322d6051731dcea" id="r_ga009d7ec202f2ec4e6322d6051731dcea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga009d7ec202f2ec4e6322d6051731dcea">FLASH_ACR_ICRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a8676f7e028638743d0097921be11e5">FLASH_ACR_ICRST_Pos</a>)</td></tr>
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<tr class="separator:ga009d7ec202f2ec4e6322d6051731dcea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga923ff88475799eea9285f77f5383ced5" id="r_ga923ff88475799eea9285f77f5383ced5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga923ff88475799eea9285f77f5383ced5">FLASH_ACR_ICRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga009d7ec202f2ec4e6322d6051731dcea">FLASH_ACR_ICRST_Msk</a></td></tr>
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<tr class="separator:ga923ff88475799eea9285f77f5383ced5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab97b6c3668fe60543b9d5a4f14e18f06" id="r_gab97b6c3668fe60543b9d5a4f14e18f06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab97b6c3668fe60543b9d5a4f14e18f06">FLASH_ACR_DCRST_Pos</a>   (12U)</td></tr>
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<tr class="separator:gab97b6c3668fe60543b9d5a4f14e18f06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab292276bf617270acde9e91828cbaede" id="r_gab292276bf617270acde9e91828cbaede"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab292276bf617270acde9e91828cbaede">FLASH_ACR_DCRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab97b6c3668fe60543b9d5a4f14e18f06">FLASH_ACR_DCRST_Pos</a>)</td></tr>
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<tr class="separator:gab292276bf617270acde9e91828cbaede"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac53d7c85551a9829014d6027d67ce6c7" id="r_gac53d7c85551a9829014d6027d67ce6c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac53d7c85551a9829014d6027d67ce6c7">FLASH_ACR_DCRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab292276bf617270acde9e91828cbaede">FLASH_ACR_DCRST_Msk</a></td></tr>
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<tr class="separator:gac53d7c85551a9829014d6027d67ce6c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa35bb342e6db09c1515b40635275212b" id="r_gaa35bb342e6db09c1515b40635275212b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa35bb342e6db09c1515b40635275212b">FLASH_ACR_BYTE0_ADDRESS_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaa35bb342e6db09c1515b40635275212b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e53f8ca7c06552c5383884a01908a58" id="r_ga8e53f8ca7c06552c5383884a01908a58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e53f8ca7c06552c5383884a01908a58">FLASH_ACR_BYTE0_ADDRESS_Msk</a>   (0x10008FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa35bb342e6db09c1515b40635275212b">FLASH_ACR_BYTE0_ADDRESS_Pos</a>)</td></tr>
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<tr class="separator:ga8e53f8ca7c06552c5383884a01908a58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga277876cbec14426a7a70ed6b3ead6d49" id="r_ga277876cbec14426a7a70ed6b3ead6d49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga277876cbec14426a7a70ed6b3ead6d49">FLASH_ACR_BYTE0_ADDRESS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e53f8ca7c06552c5383884a01908a58">FLASH_ACR_BYTE0_ADDRESS_Msk</a></td></tr>
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<tr class="separator:ga277876cbec14426a7a70ed6b3ead6d49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c66a942588ae72bc8f5d54bea5e3bf2" id="r_ga5c66a942588ae72bc8f5d54bea5e3bf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c66a942588ae72bc8f5d54bea5e3bf2">FLASH_ACR_BYTE2_ADDRESS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5c66a942588ae72bc8f5d54bea5e3bf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bb60f05f974d5fa62cea9de4dc907d1" id="r_ga5bb60f05f974d5fa62cea9de4dc907d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bb60f05f974d5fa62cea9de4dc907d1">FLASH_ACR_BYTE2_ADDRESS_Msk</a>   (0x40023C03UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c66a942588ae72bc8f5d54bea5e3bf2">FLASH_ACR_BYTE2_ADDRESS_Pos</a>)</td></tr>
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<tr class="separator:ga5bb60f05f974d5fa62cea9de4dc907d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7c5712edb158a725d8647c6af19544e" id="r_gac7c5712edb158a725d8647c6af19544e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7c5712edb158a725d8647c6af19544e">FLASH_ACR_BYTE2_ADDRESS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bb60f05f974d5fa62cea9de4dc907d1">FLASH_ACR_BYTE2_ADDRESS_Msk</a></td></tr>
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<tr class="separator:gac7c5712edb158a725d8647c6af19544e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2013e875c4c210b820e502feea6c9fb1" id="r_ga2013e875c4c210b820e502feea6c9fb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2013e875c4c210b820e502feea6c9fb1">FLASH_SR_EOP_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2013e875c4c210b820e502feea6c9fb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga386f68b5d2c3622b29811577932360ed" id="r_ga386f68b5d2c3622b29811577932360ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga386f68b5d2c3622b29811577932360ed">FLASH_SR_EOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2013e875c4c210b820e502feea6c9fb1">FLASH_SR_EOP_Pos</a>)</td></tr>
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<tr class="separator:ga386f68b5d2c3622b29811577932360ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1301c6b487cfefa247c54a576a0c12b" id="r_gae1301c6b487cfefa247c54a576a0c12b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1301c6b487cfefa247c54a576a0c12b">FLASH_SR_EOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga386f68b5d2c3622b29811577932360ed">FLASH_SR_EOP_Msk</a></td></tr>
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<tr class="separator:gae1301c6b487cfefa247c54a576a0c12b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4af97243ceb7ddfa34b7c3882c41b306" id="r_ga4af97243ceb7ddfa34b7c3882c41b306"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4af97243ceb7ddfa34b7c3882c41b306">FLASH_SR_SOP_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga4af97243ceb7ddfa34b7c3882c41b306"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd0272b01aaf5f6f7d69cd5906f3d755" id="r_gadd0272b01aaf5f6f7d69cd5906f3d755"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd0272b01aaf5f6f7d69cd5906f3d755">FLASH_SR_SOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4af97243ceb7ddfa34b7c3882c41b306">FLASH_SR_SOP_Pos</a>)</td></tr>
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<tr class="separator:gadd0272b01aaf5f6f7d69cd5906f3d755"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab779aa8b88258e15c183041744a846ff" id="r_gab779aa8b88258e15c183041744a846ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab779aa8b88258e15c183041744a846ff">FLASH_SR_SOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadd0272b01aaf5f6f7d69cd5906f3d755">FLASH_SR_SOP_Msk</a></td></tr>
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<tr class="separator:gab779aa8b88258e15c183041744a846ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace591108151f52fd0f18273c00403b80" id="r_gace591108151f52fd0f18273c00403b80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace591108151f52fd0f18273c00403b80">FLASH_SR_WRPERR_Pos</a>   (4U)</td></tr>
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<tr class="separator:gace591108151f52fd0f18273c00403b80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65a2ec1cfe4fece014bacf2c1332e659" id="r_ga65a2ec1cfe4fece014bacf2c1332e659"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65a2ec1cfe4fece014bacf2c1332e659">FLASH_SR_WRPERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gace591108151f52fd0f18273c00403b80">FLASH_SR_WRPERR_Pos</a>)</td></tr>
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<tr class="separator:ga65a2ec1cfe4fece014bacf2c1332e659"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf6f52f59b01530928d747cf32bd4d01" id="r_gabf6f52f59b01530928d747cf32bd4d01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf6f52f59b01530928d747cf32bd4d01">FLASH_SR_WRPERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65a2ec1cfe4fece014bacf2c1332e659">FLASH_SR_WRPERR_Msk</a></td></tr>
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<tr class="separator:gabf6f52f59b01530928d747cf32bd4d01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e91ef00a66f31c28b41f990b0a5b57f" id="r_ga1e91ef00a66f31c28b41f990b0a5b57f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e91ef00a66f31c28b41f990b0a5b57f">FLASH_SR_PGAERR_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga1e91ef00a66f31c28b41f990b0a5b57f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga433ad5d791f6ffcb202165a0131d00de" id="r_ga433ad5d791f6ffcb202165a0131d00de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga433ad5d791f6ffcb202165a0131d00de">FLASH_SR_PGAERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e91ef00a66f31c28b41f990b0a5b57f">FLASH_SR_PGAERR_Pos</a>)</td></tr>
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<tr class="separator:ga433ad5d791f6ffcb202165a0131d00de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac98c2458e114e7f419f3222673878ce0" id="r_gac98c2458e114e7f419f3222673878ce0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac98c2458e114e7f419f3222673878ce0">FLASH_SR_PGAERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga433ad5d791f6ffcb202165a0131d00de">FLASH_SR_PGAERR_Msk</a></td></tr>
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<tr class="separator:gac98c2458e114e7f419f3222673878ce0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac07140ebffc87a7d5c0e006e9753bc12" id="r_gac07140ebffc87a7d5c0e006e9753bc12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac07140ebffc87a7d5c0e006e9753bc12">FLASH_SR_PGPERR_Pos</a>   (6U)</td></tr>
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<tr class="separator:gac07140ebffc87a7d5c0e006e9753bc12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6caf6ab98ec1dd59205297dcf582c945" id="r_ga6caf6ab98ec1dd59205297dcf582c945"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6caf6ab98ec1dd59205297dcf582c945">FLASH_SR_PGPERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac07140ebffc87a7d5c0e006e9753bc12">FLASH_SR_PGPERR_Pos</a>)</td></tr>
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<tr class="separator:ga6caf6ab98ec1dd59205297dcf582c945"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7fd2704724528be959f82089f67e3869" id="r_ga7fd2704724528be959f82089f67e3869"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fd2704724528be959f82089f67e3869">FLASH_SR_PGPERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6caf6ab98ec1dd59205297dcf582c945">FLASH_SR_PGPERR_Msk</a></td></tr>
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<tr class="separator:ga7fd2704724528be959f82089f67e3869"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa714dc154587b83701170e6795646f36" id="r_gaa714dc154587b83701170e6795646f36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa714dc154587b83701170e6795646f36">FLASH_SR_PGSERR_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaa714dc154587b83701170e6795646f36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf315476e1c4d69765908a72e0d1946be" id="r_gaf315476e1c4d69765908a72e0d1946be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf315476e1c4d69765908a72e0d1946be">FLASH_SR_PGSERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa714dc154587b83701170e6795646f36">FLASH_SR_PGSERR_Pos</a>)</td></tr>
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<tr class="separator:gaf315476e1c4d69765908a72e0d1946be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d76ad3629a288bee0136b8b34f274f4" id="r_ga5d76ad3629a288bee0136b8b34f274f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d76ad3629a288bee0136b8b34f274f4">FLASH_SR_PGSERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf315476e1c4d69765908a72e0d1946be">FLASH_SR_PGSERR_Msk</a></td></tr>
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<tr class="separator:ga5d76ad3629a288bee0136b8b34f274f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1fff488dcd0ba14694a05d8c061441e0" id="r_ga1fff488dcd0ba14694a05d8c061441e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fff488dcd0ba14694a05d8c061441e0">FLASH_SR_BSY_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga1fff488dcd0ba14694a05d8c061441e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3564806c8fbd6e0b6ddde539c3e37045" id="r_ga3564806c8fbd6e0b6ddde539c3e37045"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3564806c8fbd6e0b6ddde539c3e37045">FLASH_SR_BSY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fff488dcd0ba14694a05d8c061441e0">FLASH_SR_BSY_Pos</a>)</td></tr>
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<tr class="separator:ga3564806c8fbd6e0b6ddde539c3e37045"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b86181a96fd2f1cc3828e9d8d83d368" id="r_ga4b86181a96fd2f1cc3828e9d8d83d368"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b86181a96fd2f1cc3828e9d8d83d368">FLASH_SR_BSY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3564806c8fbd6e0b6ddde539c3e37045">FLASH_SR_BSY_Msk</a></td></tr>
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<tr class="memitem:ga0a5addaa1ee5049b0c99023d91dd4a70" id="r_ga0a5addaa1ee5049b0c99023d91dd4a70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a5addaa1ee5049b0c99023d91dd4a70">FLASH_CR_PG_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0a5addaa1ee5049b0c99023d91dd4a70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8bc468bdb6b58e9db0f91752dea96b1a" id="r_ga8bc468bdb6b58e9db0f91752dea96b1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8bc468bdb6b58e9db0f91752dea96b1a">FLASH_CR_PG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a5addaa1ee5049b0c99023d91dd4a70">FLASH_CR_PG_Pos</a>)</td></tr>
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<tr class="memitem:ga47754b39bd7a7c79c251d6376f97f661" id="r_ga47754b39bd7a7c79c251d6376f97f661"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47754b39bd7a7c79c251d6376f97f661">FLASH_CR_PG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8bc468bdb6b58e9db0f91752dea96b1a">FLASH_CR_PG_Msk</a></td></tr>
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<tr class="separator:ga47754b39bd7a7c79c251d6376f97f661"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b8aa46dd6b3ec7eac3981210966235e" id="r_ga9b8aa46dd6b3ec7eac3981210966235e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b8aa46dd6b3ec7eac3981210966235e">FLASH_CR_SER_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga9b8aa46dd6b3ec7eac3981210966235e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6479f79813e55ff738208840dd3abfeb" id="r_ga6479f79813e55ff738208840dd3abfeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6479f79813e55ff738208840dd3abfeb">FLASH_CR_SER_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b8aa46dd6b3ec7eac3981210966235e">FLASH_CR_SER_Pos</a>)</td></tr>
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<tr class="separator:ga6479f79813e55ff738208840dd3abfeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0e561d67b381c4bd8714cd6a9c15f56" id="r_gae0e561d67b381c4bd8714cd6a9c15f56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0e561d67b381c4bd8714cd6a9c15f56">FLASH_CR_SER</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6479f79813e55ff738208840dd3abfeb">FLASH_CR_SER_Msk</a></td></tr>
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<tr class="separator:gae0e561d67b381c4bd8714cd6a9c15f56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0627fa13f9e31a0250d6917e4d2ecbc1" id="r_ga0627fa13f9e31a0250d6917e4d2ecbc1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0627fa13f9e31a0250d6917e4d2ecbc1">FLASH_CR_MER_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga0627fa13f9e31a0250d6917e4d2ecbc1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f1b8b67a6173c11f950347f09e63888" id="r_ga3f1b8b67a6173c11f950347f09e63888"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1b8b67a6173c11f950347f09e63888">FLASH_CR_MER_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0627fa13f9e31a0250d6917e4d2ecbc1">FLASH_CR_MER_Pos</a>)</td></tr>
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<tr class="separator:ga3f1b8b67a6173c11f950347f09e63888"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a287aa5a625125301306a02fb69c53a" id="r_ga4a287aa5a625125301306a02fb69c53a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a287aa5a625125301306a02fb69c53a">FLASH_CR_MER</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1b8b67a6173c11f950347f09e63888">FLASH_CR_MER_Msk</a></td></tr>
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<tr class="separator:ga4a287aa5a625125301306a02fb69c53a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab657376caa866d7aebcb539c12d943bb" id="r_gab657376caa866d7aebcb539c12d943bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab657376caa866d7aebcb539c12d943bb">FLASH_CR_SNB_Pos</a>   (3U)</td></tr>
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<tr class="separator:gab657376caa866d7aebcb539c12d943bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67d162f1700e851ee1f94a541f761c7d" id="r_ga67d162f1700e851ee1f94a541f761c7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67d162f1700e851ee1f94a541f761c7d">FLASH_CR_SNB_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab657376caa866d7aebcb539c12d943bb">FLASH_CR_SNB_Pos</a>)</td></tr>
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<tr class="separator:ga67d162f1700e851ee1f94a541f761c7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4375b021000bd1acdecab7f72240f57d" id="r_ga4375b021000bd1acdecab7f72240f57d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4375b021000bd1acdecab7f72240f57d">FLASH_CR_SNB</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67d162f1700e851ee1f94a541f761c7d">FLASH_CR_SNB_Msk</a></td></tr>
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<tr class="memitem:ga9937f2386c7127f9855f68e2ec121448" id="r_ga9937f2386c7127f9855f68e2ec121448"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9937f2386c7127f9855f68e2ec121448">FLASH_CR_SNB_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab657376caa866d7aebcb539c12d943bb">FLASH_CR_SNB_Pos</a>)</td></tr>
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<tr class="separator:ga9937f2386c7127f9855f68e2ec121448"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa70c4abfe231ffeab3f34a97c171427b" id="r_gaa70c4abfe231ffeab3f34a97c171427b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa70c4abfe231ffeab3f34a97c171427b">FLASH_CR_SNB_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab657376caa866d7aebcb539c12d943bb">FLASH_CR_SNB_Pos</a>)</td></tr>
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<tr class="separator:gaa70c4abfe231ffeab3f34a97c171427b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23c44361d3aaf062fc6b288b1d44b988" id="r_ga23c44361d3aaf062fc6b288b1d44b988"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23c44361d3aaf062fc6b288b1d44b988">FLASH_CR_SNB_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab657376caa866d7aebcb539c12d943bb">FLASH_CR_SNB_Pos</a>)</td></tr>
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<tr class="separator:ga23c44361d3aaf062fc6b288b1d44b988"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga417708b5b7aabfe219fb671f2955af31" id="r_ga417708b5b7aabfe219fb671f2955af31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga417708b5b7aabfe219fb671f2955af31">FLASH_CR_SNB_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab657376caa866d7aebcb539c12d943bb">FLASH_CR_SNB_Pos</a>)</td></tr>
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<tr class="separator:ga417708b5b7aabfe219fb671f2955af31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga734972442e2704a86bfb69c5707b33a1" id="r_ga734972442e2704a86bfb69c5707b33a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga734972442e2704a86bfb69c5707b33a1">FLASH_CR_SNB_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab657376caa866d7aebcb539c12d943bb">FLASH_CR_SNB_Pos</a>)</td></tr>
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<tr class="separator:ga734972442e2704a86bfb69c5707b33a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0242af989594850be999d37750caa5c5" id="r_ga0242af989594850be999d37750caa5c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0242af989594850be999d37750caa5c5">FLASH_CR_PSIZE_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga0242af989594850be999d37750caa5c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f6b8486e155b78a7617fe046bade831" id="r_ga4f6b8486e155b78a7617fe046bade831"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f6b8486e155b78a7617fe046bade831">FLASH_CR_PSIZE_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0242af989594850be999d37750caa5c5">FLASH_CR_PSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga4f6b8486e155b78a7617fe046bade831"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga948ebea4921be9f981292b6e6733b00f" id="r_ga948ebea4921be9f981292b6e6733b00f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga948ebea4921be9f981292b6e6733b00f">FLASH_CR_PSIZE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f6b8486e155b78a7617fe046bade831">FLASH_CR_PSIZE_Msk</a></td></tr>
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<tr class="separator:ga948ebea4921be9f981292b6e6733b00f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadbc673f47f1ed33ca4144e9eee91ad6" id="r_gaadbc673f47f1ed33ca4144e9eee91ad6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadbc673f47f1ed33ca4144e9eee91ad6">FLASH_CR_PSIZE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0242af989594850be999d37750caa5c5">FLASH_CR_PSIZE_Pos</a>)</td></tr>
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<tr class="separator:gaadbc673f47f1ed33ca4144e9eee91ad6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga196dca8b265486bf05782e6bbe81d854" id="r_ga196dca8b265486bf05782e6bbe81d854"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga196dca8b265486bf05782e6bbe81d854">FLASH_CR_PSIZE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0242af989594850be999d37750caa5c5">FLASH_CR_PSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga196dca8b265486bf05782e6bbe81d854"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7925df36a4d15838d8cb457f671e7532" id="r_ga7925df36a4d15838d8cb457f671e7532"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7925df36a4d15838d8cb457f671e7532">FLASH_CR_STRT_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga7925df36a4d15838d8cb457f671e7532"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ce773f84ec7782c408a8d9cef09f496" id="r_ga1ce773f84ec7782c408a8d9cef09f496"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ce773f84ec7782c408a8d9cef09f496">FLASH_CR_STRT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7925df36a4d15838d8cb457f671e7532">FLASH_CR_STRT_Pos</a>)</td></tr>
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<tr class="separator:ga1ce773f84ec7782c408a8d9cef09f496"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe4dd28134f93f52b1d4ec5b36a99864" id="r_gafe4dd28134f93f52b1d4ec5b36a99864"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe4dd28134f93f52b1d4ec5b36a99864">FLASH_CR_STRT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ce773f84ec7782c408a8d9cef09f496">FLASH_CR_STRT_Msk</a></td></tr>
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<tr class="separator:gafe4dd28134f93f52b1d4ec5b36a99864"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e162a7fa45cb85ba0df0942a2519478" id="r_ga4e162a7fa45cb85ba0df0942a2519478"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e162a7fa45cb85ba0df0942a2519478">FLASH_CR_EOPIE_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga4e162a7fa45cb85ba0df0942a2519478"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0866e1ddcbf0e7a895ca9a4794db4bd" id="r_gab0866e1ddcbf0e7a895ca9a4794db4bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0866e1ddcbf0e7a895ca9a4794db4bd">FLASH_CR_EOPIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e162a7fa45cb85ba0df0942a2519478">FLASH_CR_EOPIE_Pos</a>)</td></tr>
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<tr class="separator:gab0866e1ddcbf0e7a895ca9a4794db4bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9e69856f654ec430a42791a34799db0" id="r_gab9e69856f654ec430a42791a34799db0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9e69856f654ec430a42791a34799db0">FLASH_CR_EOPIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab0866e1ddcbf0e7a895ca9a4794db4bd">FLASH_CR_EOPIE_Msk</a></td></tr>
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<tr class="separator:gab9e69856f654ec430a42791a34799db0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab075c4eeff509cfe0f34040c29edfb05" id="r_gab075c4eeff509cfe0f34040c29edfb05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab075c4eeff509cfe0f34040c29edfb05">FLASH_CR_ERRIE_Pos</a>   (25U)</td></tr>
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<tr class="separator:gab075c4eeff509cfe0f34040c29edfb05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9f1e535996ab89de1ca07a32a11e526" id="r_gac9f1e535996ab89de1ca07a32a11e526"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9f1e535996ab89de1ca07a32a11e526">FLASH_CR_ERRIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab075c4eeff509cfe0f34040c29edfb05">FLASH_CR_ERRIE_Pos</a>)</td></tr>
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<tr class="separator:gac9f1e535996ab89de1ca07a32a11e526"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga930897cecdaa9dbef8c640b84acbd8c2" id="r_ga930897cecdaa9dbef8c640b84acbd8c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga930897cecdaa9dbef8c640b84acbd8c2">FLASH_CR_ERRIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9f1e535996ab89de1ca07a32a11e526">FLASH_CR_ERRIE_Msk</a></td></tr>
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<tr class="separator:ga930897cecdaa9dbef8c640b84acbd8c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa74509adc6db3db66803966b25423cae" id="r_gaa74509adc6db3db66803966b25423cae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa74509adc6db3db66803966b25423cae">FLASH_CR_LOCK_Pos</a>   (31U)</td></tr>
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<tr class="separator:gaa74509adc6db3db66803966b25423cae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7954a2bc4dd25495e8c164454817a966" id="r_ga7954a2bc4dd25495e8c164454817a966"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7954a2bc4dd25495e8c164454817a966">FLASH_CR_LOCK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa74509adc6db3db66803966b25423cae">FLASH_CR_LOCK_Pos</a>)</td></tr>
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<tr class="separator:ga7954a2bc4dd25495e8c164454817a966"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab25f1fa4127fa015361b61a6f3180784" id="r_gab25f1fa4127fa015361b61a6f3180784"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab25f1fa4127fa015361b61a6f3180784">FLASH_CR_LOCK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7954a2bc4dd25495e8c164454817a966">FLASH_CR_LOCK_Msk</a></td></tr>
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<tr class="separator:gab25f1fa4127fa015361b61a6f3180784"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf12a3ac81fbc65a12d83ed398b6ef28" id="r_gaaf12a3ac81fbc65a12d83ed398b6ef28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf12a3ac81fbc65a12d83ed398b6ef28">FLASH_OPTCR_OPTLOCK_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaaf12a3ac81fbc65a12d83ed398b6ef28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4fb506626a51c8b29c864573f6c2835" id="r_gac4fb506626a51c8b29c864573f6c2835"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4fb506626a51c8b29c864573f6c2835">FLASH_OPTCR_OPTLOCK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf12a3ac81fbc65a12d83ed398b6ef28">FLASH_OPTCR_OPTLOCK_Pos</a>)</td></tr>
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<tr class="separator:gac4fb506626a51c8b29c864573f6c2835"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c1da080e341fca41ce7f7d661cc4904" id="r_ga4c1da080e341fca41ce7f7d661cc4904"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c1da080e341fca41ce7f7d661cc4904">FLASH_OPTCR_OPTLOCK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fb506626a51c8b29c864573f6c2835">FLASH_OPTCR_OPTLOCK_Msk</a></td></tr>
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<tr class="separator:ga4c1da080e341fca41ce7f7d661cc4904"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83a4a90f9f76098cdca63d9931bc79d7" id="r_ga83a4a90f9f76098cdca63d9931bc79d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83a4a90f9f76098cdca63d9931bc79d7">FLASH_OPTCR_OPTSTRT_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga83a4a90f9f76098cdca63d9931bc79d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf93699ed3b5dc9bb83833f2bf1610b11" id="r_gaf93699ed3b5dc9bb83833f2bf1610b11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf93699ed3b5dc9bb83833f2bf1610b11">FLASH_OPTCR_OPTSTRT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83a4a90f9f76098cdca63d9931bc79d7">FLASH_OPTCR_OPTSTRT_Pos</a>)</td></tr>
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<tr class="separator:gaf93699ed3b5dc9bb83833f2bf1610b11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0858d561d4790c86b64a60204a09a3b5" id="r_ga0858d561d4790c86b64a60204a09a3b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0858d561d4790c86b64a60204a09a3b5">FLASH_OPTCR_OPTSTRT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf93699ed3b5dc9bb83833f2bf1610b11">FLASH_OPTCR_OPTSTRT_Msk</a></td></tr>
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<tr class="separator:ga0858d561d4790c86b64a60204a09a3b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf842eaac29efd86925c9431a8eb99b27" id="r_gaf842eaac29efd86925c9431a8eb99b27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf842eaac29efd86925c9431a8eb99b27">FLASH_OPTCR_BOR_LEV_0</a>   0x00000004U</td></tr>
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<tr class="separator:gaf842eaac29efd86925c9431a8eb99b27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2971824f63351f09ad3db521d6a5b212" id="r_ga2971824f63351f09ad3db521d6a5b212"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2971824f63351f09ad3db521d6a5b212">FLASH_OPTCR_BOR_LEV_1</a>   0x00000008U</td></tr>
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<tr class="separator:ga2971824f63351f09ad3db521d6a5b212"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga664b8edfc20be3140e72411130fd9c2c" id="r_ga664b8edfc20be3140e72411130fd9c2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga664b8edfc20be3140e72411130fd9c2c">FLASH_OPTCR_BOR_LEV_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga664b8edfc20be3140e72411130fd9c2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bbb4145b4e60c9aba5a41b52ca7de42" id="r_ga0bbb4145b4e60c9aba5a41b52ca7de42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bbb4145b4e60c9aba5a41b52ca7de42">FLASH_OPTCR_BOR_LEV_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga664b8edfc20be3140e72411130fd9c2c">FLASH_OPTCR_BOR_LEV_Pos</a>)</td></tr>
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<tr class="separator:ga0bbb4145b4e60c9aba5a41b52ca7de42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62cadc42caa03753ab8733da2b957ead" id="r_ga62cadc42caa03753ab8733da2b957ead"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62cadc42caa03753ab8733da2b957ead">FLASH_OPTCR_BOR_LEV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bbb4145b4e60c9aba5a41b52ca7de42">FLASH_OPTCR_BOR_LEV_Msk</a></td></tr>
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<tr class="separator:ga62cadc42caa03753ab8733da2b957ead"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga135a90817c765ba7f80a463cd48b8dd2" id="r_ga135a90817c765ba7f80a463cd48b8dd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga135a90817c765ba7f80a463cd48b8dd2">FLASH_OPTCR_WDG_SW_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga135a90817c765ba7f80a463cd48b8dd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a820fdb171a46fddcc020aa769a7b87" id="r_ga5a820fdb171a46fddcc020aa769a7b87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a820fdb171a46fddcc020aa769a7b87">FLASH_OPTCR_WDG_SW_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga135a90817c765ba7f80a463cd48b8dd2">FLASH_OPTCR_WDG_SW_Pos</a>)</td></tr>
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<tr class="separator:ga5a820fdb171a46fddcc020aa769a7b87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf38cbe85e3a2c30dbe6ccb3b3e636504" id="r_gaf38cbe85e3a2c30dbe6ccb3b3e636504"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf38cbe85e3a2c30dbe6ccb3b3e636504">FLASH_OPTCR_WDG_SW</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a820fdb171a46fddcc020aa769a7b87">FLASH_OPTCR_WDG_SW_Msk</a></td></tr>
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<tr class="separator:gaf38cbe85e3a2c30dbe6ccb3b3e636504"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0df94d9b6c39215d53adeb12124ffe2a" id="r_ga0df94d9b6c39215d53adeb12124ffe2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0df94d9b6c39215d53adeb12124ffe2a">FLASH_OPTCR_nRST_STOP_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga0df94d9b6c39215d53adeb12124ffe2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga203b0fae4100b7cb942d38ab22459793" id="r_ga203b0fae4100b7cb942d38ab22459793"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga203b0fae4100b7cb942d38ab22459793">FLASH_OPTCR_nRST_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0df94d9b6c39215d53adeb12124ffe2a">FLASH_OPTCR_nRST_STOP_Pos</a>)</td></tr>
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<tr class="separator:ga203b0fae4100b7cb942d38ab22459793"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12b1ec98e521815433b3eec1e4136fd2" id="r_ga12b1ec98e521815433b3eec1e4136fd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12b1ec98e521815433b3eec1e4136fd2">FLASH_OPTCR_nRST_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga203b0fae4100b7cb942d38ab22459793">FLASH_OPTCR_nRST_STOP_Msk</a></td></tr>
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<tr class="separator:ga12b1ec98e521815433b3eec1e4136fd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1240d379a33450a4a5fd676f13cd4db2" id="r_ga1240d379a33450a4a5fd676f13cd4db2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1240d379a33450a4a5fd676f13cd4db2">FLASH_OPTCR_nRST_STDBY_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga1240d379a33450a4a5fd676f13cd4db2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02c3e4e48e88b93407109e671e8aaf0e" id="r_ga02c3e4e48e88b93407109e671e8aaf0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02c3e4e48e88b93407109e671e8aaf0e">FLASH_OPTCR_nRST_STDBY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1240d379a33450a4a5fd676f13cd4db2">FLASH_OPTCR_nRST_STDBY_Pos</a>)</td></tr>
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<tr class="separator:ga02c3e4e48e88b93407109e671e8aaf0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82102d640fe1d3e6e9f9c6a3e0adb56f" id="r_ga82102d640fe1d3e6e9f9c6a3e0adb56f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82102d640fe1d3e6e9f9c6a3e0adb56f">FLASH_OPTCR_nRST_STDBY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c3e4e48e88b93407109e671e8aaf0e">FLASH_OPTCR_nRST_STDBY_Msk</a></td></tr>
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<tr class="separator:ga82102d640fe1d3e6e9f9c6a3e0adb56f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e06896e31b4fbbbffaa2865c16a607e" id="r_ga2e06896e31b4fbbbffaa2865c16a607e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e">FLASH_OPTCR_RDP_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga2e06896e31b4fbbbffaa2865c16a607e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bc4c590daea652ce57f3a44a6a67d84" id="r_ga3bc4c590daea652ce57f3a44a6a67d84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bc4c590daea652ce57f3a44a6a67d84">FLASH_OPTCR_RDP_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e">FLASH_OPTCR_RDP_Pos</a>)</td></tr>
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<tr class="separator:ga3bc4c590daea652ce57f3a44a6a67d84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa180c5732c34b271618aa58695c8ff5a" id="r_gaa180c5732c34b271618aa58695c8ff5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa180c5732c34b271618aa58695c8ff5a">FLASH_OPTCR_RDP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bc4c590daea652ce57f3a44a6a67d84">FLASH_OPTCR_RDP_Msk</a></td></tr>
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<tr class="separator:gaa180c5732c34b271618aa58695c8ff5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd79ca0fb8dd121074f40b83b2313d12" id="r_gafd79ca0fb8dd121074f40b83b2313d12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd79ca0fb8dd121074f40b83b2313d12">FLASH_OPTCR_RDP_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e">FLASH_OPTCR_RDP_Pos</a>)</td></tr>
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<tr class="separator:gafd79ca0fb8dd121074f40b83b2313d12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga935fe4b6ea955b3dc26110f19e894e60" id="r_ga935fe4b6ea955b3dc26110f19e894e60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga935fe4b6ea955b3dc26110f19e894e60">FLASH_OPTCR_RDP_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e">FLASH_OPTCR_RDP_Pos</a>)</td></tr>
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<tr class="separator:ga935fe4b6ea955b3dc26110f19e894e60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02ba844244e374fe8105a7cad59ad523" id="r_ga02ba844244e374fe8105a7cad59ad523"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02ba844244e374fe8105a7cad59ad523">FLASH_OPTCR_RDP_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e">FLASH_OPTCR_RDP_Pos</a>)</td></tr>
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<tr class="separator:ga02ba844244e374fe8105a7cad59ad523"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga844d4d62b7de476c90dd5f971f5e9041" id="r_ga844d4d62b7de476c90dd5f971f5e9041"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga844d4d62b7de476c90dd5f971f5e9041">FLASH_OPTCR_RDP_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e">FLASH_OPTCR_RDP_Pos</a>)</td></tr>
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<tr class="separator:ga844d4d62b7de476c90dd5f971f5e9041"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73bffe5ebb8d12020ebf3f2875f4a709" id="r_ga73bffe5ebb8d12020ebf3f2875f4a709"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73bffe5ebb8d12020ebf3f2875f4a709">FLASH_OPTCR_RDP_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e">FLASH_OPTCR_RDP_Pos</a>)</td></tr>
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<tr class="separator:ga73bffe5ebb8d12020ebf3f2875f4a709"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67fef54b7b6c44afcc50e4f20ba461fd" id="r_ga67fef54b7b6c44afcc50e4f20ba461fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67fef54b7b6c44afcc50e4f20ba461fd">FLASH_OPTCR_RDP_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e">FLASH_OPTCR_RDP_Pos</a>)</td></tr>
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<tr class="separator:ga67fef54b7b6c44afcc50e4f20ba461fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18946cdea0f463f1e5386f42986f7e67" id="r_ga18946cdea0f463f1e5386f42986f7e67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18946cdea0f463f1e5386f42986f7e67">FLASH_OPTCR_RDP_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e">FLASH_OPTCR_RDP_Pos</a>)</td></tr>
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<tr class="separator:ga18946cdea0f463f1e5386f42986f7e67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad00a8584a84d18d76e147e4873740b4d" id="r_gad00a8584a84d18d76e147e4873740b4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad00a8584a84d18d76e147e4873740b4d">FLASH_OPTCR_RDP_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e">FLASH_OPTCR_RDP_Pos</a>)</td></tr>
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<tr class="separator:gad00a8584a84d18d76e147e4873740b4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb898dd74f16687db438fac87e762e40" id="r_gabb898dd74f16687db438fac87e762e40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb898dd74f16687db438fac87e762e40">FLASH_OPTCR_nWRP_Pos</a>   (16U)</td></tr>
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<tr class="separator:gabb898dd74f16687db438fac87e762e40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae33aa677769879cad328db0ee92829df" id="r_gae33aa677769879cad328db0ee92829df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae33aa677769879cad328db0ee92829df">FLASH_OPTCR_nWRP_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb898dd74f16687db438fac87e762e40">FLASH_OPTCR_nWRP_Pos</a>)</td></tr>
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<tr class="separator:gae33aa677769879cad328db0ee92829df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c2bbd885cff2e6c16662a014f3125e1" id="r_ga2c2bbd885cff2e6c16662a014f3125e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c2bbd885cff2e6c16662a014f3125e1">FLASH_OPTCR_nWRP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae33aa677769879cad328db0ee92829df">FLASH_OPTCR_nWRP_Msk</a></td></tr>
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<tr class="separator:ga2c2bbd885cff2e6c16662a014f3125e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga823e5c42b89e152a8394c3fa6c8811ca" id="r_ga823e5c42b89e152a8394c3fa6c8811ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga823e5c42b89e152a8394c3fa6c8811ca">FLASH_OPTCR_nWRP_0</a>   0x00010000U</td></tr>
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<tr class="separator:ga823e5c42b89e152a8394c3fa6c8811ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d0ef7c876b297706a26dda017441f9c" id="r_ga4d0ef7c876b297706a26dda017441f9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d0ef7c876b297706a26dda017441f9c">FLASH_OPTCR_nWRP_1</a>   0x00020000U</td></tr>
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<tr class="separator:ga4d0ef7c876b297706a26dda017441f9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96c5b96918f1871febfb31a026028522" id="r_ga96c5b96918f1871febfb31a026028522"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96c5b96918f1871febfb31a026028522">FLASH_OPTCR_nWRP_2</a>   0x00040000U</td></tr>
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<tr class="separator:ga96c5b96918f1871febfb31a026028522"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb0fa51cc0e95dcc79b74f451898f634" id="r_gabb0fa51cc0e95dcc79b74f451898f634"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb0fa51cc0e95dcc79b74f451898f634">FLASH_OPTCR_nWRP_3</a>   0x00080000U</td></tr>
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<tr class="separator:gabb0fa51cc0e95dcc79b74f451898f634"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad936542dd4c587babd790e92783d90fb" id="r_gad936542dd4c587babd790e92783d90fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad936542dd4c587babd790e92783d90fb">FLASH_OPTCR_nWRP_4</a>   0x00100000U</td></tr>
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<tr class="separator:gad936542dd4c587babd790e92783d90fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae20268ac71dad90ee983642bb328e8ca" id="r_gae20268ac71dad90ee983642bb328e8ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae20268ac71dad90ee983642bb328e8ca">FLASH_OPTCR_nWRP_5</a>   0x00200000U</td></tr>
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<tr class="separator:gae20268ac71dad90ee983642bb328e8ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga947616eac2be3f26ae1a3d748e70cac8" id="r_ga947616eac2be3f26ae1a3d748e70cac8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga947616eac2be3f26ae1a3d748e70cac8">FLASH_OPTCR_nWRP_6</a>   0x00400000U</td></tr>
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<tr class="separator:ga947616eac2be3f26ae1a3d748e70cac8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4d248e42a97e1c852cbea42b25598e1" id="r_gaa4d248e42a97e1c852cbea42b25598e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4d248e42a97e1c852cbea42b25598e1">FLASH_OPTCR_nWRP_7</a>   0x00800000U</td></tr>
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<tr class="separator:gaa4d248e42a97e1c852cbea42b25598e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb38a3c5a67d67160a33d1762ed0f51f" id="r_gadb38a3c5a67d67160a33d1762ed0f51f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb38a3c5a67d67160a33d1762ed0f51f">FLASH_OPTCR_nWRP_8</a>   0x01000000U</td></tr>
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<tr class="separator:gadb38a3c5a67d67160a33d1762ed0f51f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e186dbacd1587760b167b9ae4166c5c" id="r_ga5e186dbacd1587760b167b9ae4166c5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e186dbacd1587760b167b9ae4166c5c">FLASH_OPTCR_nWRP_9</a>   0x02000000U</td></tr>
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<tr class="separator:ga5e186dbacd1587760b167b9ae4166c5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38f22bae03f31d60f0c6aded7cd29ead" id="r_ga38f22bae03f31d60f0c6aded7cd29ead"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38f22bae03f31d60f0c6aded7cd29ead">FLASH_OPTCR_nWRP_10</a>   0x04000000U</td></tr>
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<tr class="separator:ga38f22bae03f31d60f0c6aded7cd29ead"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac11ce7f6df6922142fc54fb8d376e239" id="r_gac11ce7f6df6922142fc54fb8d376e239"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac11ce7f6df6922142fc54fb8d376e239">FLASH_OPTCR_nWRP_11</a>   0x08000000U</td></tr>
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<tr class="separator:gac11ce7f6df6922142fc54fb8d376e239"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5258f37e33f2705635abfcfa1e7caf8b" id="r_ga5258f37e33f2705635abfcfa1e7caf8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga5258f37e33f2705635abfcfa1e7caf8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga584b3c849783bc64b9fde5f4f15090b6" id="r_ga584b3c849783bc64b9fde5f4f15090b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga584b3c849783bc64b9fde5f4f15090b6">FLASH_OPTCR1_nWRP_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:ga584b3c849783bc64b9fde5f4f15090b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga166b108d44b55fef7da25bb1a9696d4a" id="r_ga166b108d44b55fef7da25bb1a9696d4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga166b108d44b55fef7da25bb1a9696d4a">FLASH_OPTCR1_nWRP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga584b3c849783bc64b9fde5f4f15090b6">FLASH_OPTCR1_nWRP_Msk</a></td></tr>
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<tr class="separator:ga166b108d44b55fef7da25bb1a9696d4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8704f7d9b4f2ed666a36fd524200393" id="r_gab8704f7d9b4f2ed666a36fd524200393"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8704f7d9b4f2ed666a36fd524200393">FLASH_OPTCR1_nWRP_0</a>   (0x001UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:gab8704f7d9b4f2ed666a36fd524200393"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5dbe2ea161a6b8f8f9410097b56e7f37" id="r_ga5dbe2ea161a6b8f8f9410097b56e7f37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5dbe2ea161a6b8f8f9410097b56e7f37">FLASH_OPTCR1_nWRP_1</a>   (0x002UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:ga5dbe2ea161a6b8f8f9410097b56e7f37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95055e7aee08960157182164896ab53e" id="r_ga95055e7aee08960157182164896ab53e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95055e7aee08960157182164896ab53e">FLASH_OPTCR1_nWRP_2</a>   (0x004UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:ga95055e7aee08960157182164896ab53e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga215ec5e70d6f8e9bcfc23e808720b7b5" id="r_ga215ec5e70d6f8e9bcfc23e808720b7b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga215ec5e70d6f8e9bcfc23e808720b7b5">FLASH_OPTCR1_nWRP_3</a>   (0x008UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:ga215ec5e70d6f8e9bcfc23e808720b7b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga552186f19bc88ebbceb4b20fd17fa15c" id="r_ga552186f19bc88ebbceb4b20fd17fa15c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga552186f19bc88ebbceb4b20fd17fa15c">FLASH_OPTCR1_nWRP_4</a>   (0x010UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:ga552186f19bc88ebbceb4b20fd17fa15c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4370733a7b56759492f1af72272d086" id="r_gaa4370733a7b56759492f1af72272d086"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4370733a7b56759492f1af72272d086">FLASH_OPTCR1_nWRP_5</a>   (0x020UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:gaa4370733a7b56759492f1af72272d086"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeecb61b8efdc36c40fce01e4cd1d5907" id="r_gaeecb61b8efdc36c40fce01e4cd1d5907"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeecb61b8efdc36c40fce01e4cd1d5907">FLASH_OPTCR1_nWRP_6</a>   (0x040UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:gaeecb61b8efdc36c40fce01e4cd1d5907"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e3446bcd7be06c230bc6cbceadae5cf" id="r_ga7e3446bcd7be06c230bc6cbceadae5cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e3446bcd7be06c230bc6cbceadae5cf">FLASH_OPTCR1_nWRP_7</a>   (0x080UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:ga7e3446bcd7be06c230bc6cbceadae5cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97aac6b31d856505401e3bef486df10f" id="r_ga97aac6b31d856505401e3bef486df10f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97aac6b31d856505401e3bef486df10f">FLASH_OPTCR1_nWRP_8</a>   (0x100UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:ga97aac6b31d856505401e3bef486df10f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ab067bd8ab9645c93e6acf3b839dd8d" id="r_ga0ab067bd8ab9645c93e6acf3b839dd8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ab067bd8ab9645c93e6acf3b839dd8d">FLASH_OPTCR1_nWRP_9</a>   (0x200UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:ga0ab067bd8ab9645c93e6acf3b839dd8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf08f9db2b0ca30861faac54b6df672e" id="r_gaaf08f9db2b0ca30861faac54b6df672e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf08f9db2b0ca30861faac54b6df672e">FLASH_OPTCR1_nWRP_10</a>   (0x400UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:gaaf08f9db2b0ca30861faac54b6df672e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga244656eb3ca465d38aba14e92f8c5870" id="r_ga244656eb3ca465d38aba14e92f8c5870"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga244656eb3ca465d38aba14e92f8c5870">FLASH_OPTCR1_nWRP_11</a>   (0x800UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b">FLASH_OPTCR1_nWRP_Pos</a>)</td></tr>
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<tr class="separator:ga244656eb3ca465d38aba14e92f8c5870"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdb4fdc15ea8091df00881c342b88eda" id="r_gabdb4fdc15ea8091df00881c342b88eda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdb4fdc15ea8091df00881c342b88eda">FSMC_BCR1_MBKEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:gabdb4fdc15ea8091df00881c342b88eda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1fb54a74314811fa88d317a79004527c" id="r_ga1fb54a74314811fa88d317a79004527c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fb54a74314811fa88d317a79004527c">FSMC_BCR1_MBKEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabdb4fdc15ea8091df00881c342b88eda">FSMC_BCR1_MBKEN_Pos</a>)</td></tr>
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<tr class="separator:ga1fb54a74314811fa88d317a79004527c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad154cab86ce34cebfe1f76e5c2f78e61" id="r_gad154cab86ce34cebfe1f76e5c2f78e61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad154cab86ce34cebfe1f76e5c2f78e61">FSMC_BCR1_MBKEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fb54a74314811fa88d317a79004527c">FSMC_BCR1_MBKEN_Msk</a></td></tr>
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<tr class="separator:gad154cab86ce34cebfe1f76e5c2f78e61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13b709c2443de9ab40dadc6830f31158" id="r_ga13b709c2443de9ab40dadc6830f31158"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13b709c2443de9ab40dadc6830f31158">FSMC_BCR1_MUXEN_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga1346d0cf99bad4d9863fd777d1930d6c" id="r_ga1346d0cf99bad4d9863fd777d1930d6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1346d0cf99bad4d9863fd777d1930d6c">FSMC_BCR1_MUXEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga13b709c2443de9ab40dadc6830f31158">FSMC_BCR1_MUXEN_Pos</a>)</td></tr>
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<tr class="memitem:ga28dd9f93d8687cdc08745df9fcc38e89" id="r_ga28dd9f93d8687cdc08745df9fcc38e89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28dd9f93d8687cdc08745df9fcc38e89">FSMC_BCR1_MUXEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1346d0cf99bad4d9863fd777d1930d6c">FSMC_BCR1_MUXEN_Msk</a></td></tr>
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<tr class="separator:ga28dd9f93d8687cdc08745df9fcc38e89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf7fa08d310f1b3d957f0600375b3c87" id="r_gacf7fa08d310f1b3d957f0600375b3c87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf7fa08d310f1b3d957f0600375b3c87">FSMC_BCR1_MTYP_Pos</a>   (2U)</td></tr>
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<tr class="separator:gacf7fa08d310f1b3d957f0600375b3c87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76cf34bfdd2f5d9a7959fee17050319f" id="r_ga76cf34bfdd2f5d9a7959fee17050319f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76cf34bfdd2f5d9a7959fee17050319f">FSMC_BCR1_MTYP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf7fa08d310f1b3d957f0600375b3c87">FSMC_BCR1_MTYP_Pos</a>)</td></tr>
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<tr class="separator:ga76cf34bfdd2f5d9a7959fee17050319f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bab7a47703902d187502ac765ebb05d" id="r_ga9bab7a47703902d187502ac765ebb05d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bab7a47703902d187502ac765ebb05d">FSMC_BCR1_MTYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga76cf34bfdd2f5d9a7959fee17050319f">FSMC_BCR1_MTYP_Msk</a></td></tr>
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<tr class="separator:ga9bab7a47703902d187502ac765ebb05d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29b921567bd5a422c51f9a0f426ac3f6" id="r_ga29b921567bd5a422c51f9a0f426ac3f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29b921567bd5a422c51f9a0f426ac3f6">FSMC_BCR1_MTYP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf7fa08d310f1b3d957f0600375b3c87">FSMC_BCR1_MTYP_Pos</a>)</td></tr>
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<tr class="separator:ga29b921567bd5a422c51f9a0f426ac3f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3fe2fd14b3c0d88aecfb9cf5b44995a0" id="r_ga3fe2fd14b3c0d88aecfb9cf5b44995a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3fe2fd14b3c0d88aecfb9cf5b44995a0">FSMC_BCR1_MTYP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf7fa08d310f1b3d957f0600375b3c87">FSMC_BCR1_MTYP_Pos</a>)</td></tr>
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<tr class="separator:ga3fe2fd14b3c0d88aecfb9cf5b44995a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ec03e929628fb56d95403641ec23ac0" id="r_ga5ec03e929628fb56d95403641ec23ac0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec03e929628fb56d95403641ec23ac0">FSMC_BCR1_MWID_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga5ec03e929628fb56d95403641ec23ac0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e42eb74853897be5a39fe4e8549d166" id="r_ga5e42eb74853897be5a39fe4e8549d166"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e42eb74853897be5a39fe4e8549d166">FSMC_BCR1_MWID_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec03e929628fb56d95403641ec23ac0">FSMC_BCR1_MWID_Pos</a>)</td></tr>
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<tr class="separator:ga5e42eb74853897be5a39fe4e8549d166"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa12297787a0580fedbd5244f0caa0a76" id="r_gaa12297787a0580fedbd5244f0caa0a76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa12297787a0580fedbd5244f0caa0a76">FSMC_BCR1_MWID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e42eb74853897be5a39fe4e8549d166">FSMC_BCR1_MWID_Msk</a></td></tr>
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<tr class="separator:gaa12297787a0580fedbd5244f0caa0a76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a6fe3b4b28a31c4bbf26a838695fd0c" id="r_ga1a6fe3b4b28a31c4bbf26a838695fd0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a6fe3b4b28a31c4bbf26a838695fd0c">FSMC_BCR1_MWID_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec03e929628fb56d95403641ec23ac0">FSMC_BCR1_MWID_Pos</a>)</td></tr>
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<tr class="separator:ga1a6fe3b4b28a31c4bbf26a838695fd0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65592a6a20efa6aed5b59fe1eba508d8" id="r_ga65592a6a20efa6aed5b59fe1eba508d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65592a6a20efa6aed5b59fe1eba508d8">FSMC_BCR1_MWID_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec03e929628fb56d95403641ec23ac0">FSMC_BCR1_MWID_Pos</a>)</td></tr>
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<tr class="separator:ga65592a6a20efa6aed5b59fe1eba508d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga955890b4486255e510806f000bb44f43" id="r_ga955890b4486255e510806f000bb44f43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga955890b4486255e510806f000bb44f43">FSMC_BCR1_FACCEN_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga955890b4486255e510806f000bb44f43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5822754c7aa0947d0b6623d884438f0e" id="r_ga5822754c7aa0947d0b6623d884438f0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5822754c7aa0947d0b6623d884438f0e">FSMC_BCR1_FACCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga955890b4486255e510806f000bb44f43">FSMC_BCR1_FACCEN_Pos</a>)</td></tr>
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<tr class="separator:ga5822754c7aa0947d0b6623d884438f0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14aaca2a8bccab73c7726cf73ee9be16" id="r_ga14aaca2a8bccab73c7726cf73ee9be16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14aaca2a8bccab73c7726cf73ee9be16">FSMC_BCR1_FACCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5822754c7aa0947d0b6623d884438f0e">FSMC_BCR1_FACCEN_Msk</a></td></tr>
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<tr class="separator:ga14aaca2a8bccab73c7726cf73ee9be16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd79d1d9b9be97259d21184a38b79e78" id="r_gabd79d1d9b9be97259d21184a38b79e78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd79d1d9b9be97259d21184a38b79e78">FSMC_BCR1_BURSTEN_Pos</a>   (8U)</td></tr>
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<tr class="separator:gabd79d1d9b9be97259d21184a38b79e78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga093941fc5df6f3d174d23a4863be87c3" id="r_ga093941fc5df6f3d174d23a4863be87c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga093941fc5df6f3d174d23a4863be87c3">FSMC_BCR1_BURSTEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabd79d1d9b9be97259d21184a38b79e78">FSMC_BCR1_BURSTEN_Pos</a>)</td></tr>
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<tr class="separator:ga093941fc5df6f3d174d23a4863be87c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94857a0177ae12f1172da65d8708ae97" id="r_ga94857a0177ae12f1172da65d8708ae97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94857a0177ae12f1172da65d8708ae97">FSMC_BCR1_BURSTEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga093941fc5df6f3d174d23a4863be87c3">FSMC_BCR1_BURSTEN_Msk</a></td></tr>
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<tr class="separator:ga94857a0177ae12f1172da65d8708ae97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa688dcd0dc2b3c072f353941a5cb8c63" id="r_gaa688dcd0dc2b3c072f353941a5cb8c63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa688dcd0dc2b3c072f353941a5cb8c63">FSMC_BCR1_WAITPOL_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaa688dcd0dc2b3c072f353941a5cb8c63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66ec261e040de2455880252747ec2954" id="r_ga66ec261e040de2455880252747ec2954"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66ec261e040de2455880252747ec2954">FSMC_BCR1_WAITPOL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa688dcd0dc2b3c072f353941a5cb8c63">FSMC_BCR1_WAITPOL_Pos</a>)</td></tr>
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<tr class="separator:ga66ec261e040de2455880252747ec2954"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57dbc565fbc7d8ec20fda7ef0da30df4" id="r_ga57dbc565fbc7d8ec20fda7ef0da30df4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57dbc565fbc7d8ec20fda7ef0da30df4">FSMC_BCR1_WAITPOL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga66ec261e040de2455880252747ec2954">FSMC_BCR1_WAITPOL_Msk</a></td></tr>
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<tr class="separator:ga57dbc565fbc7d8ec20fda7ef0da30df4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81d2d47d639ff73b641182d78e5388cc" id="r_ga81d2d47d639ff73b641182d78e5388cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81d2d47d639ff73b641182d78e5388cc">FSMC_BCR1_WRAPMOD_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga81d2d47d639ff73b641182d78e5388cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae07f435df040041ae6b196ebc57e5038" id="r_gae07f435df040041ae6b196ebc57e5038"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae07f435df040041ae6b196ebc57e5038">FSMC_BCR1_WRAPMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga81d2d47d639ff73b641182d78e5388cc">FSMC_BCR1_WRAPMOD_Pos</a>)</td></tr>
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<tr class="separator:gae07f435df040041ae6b196ebc57e5038"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad215e95feee8339393bd93a2bcea11f1" id="r_gad215e95feee8339393bd93a2bcea11f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad215e95feee8339393bd93a2bcea11f1">FSMC_BCR1_WRAPMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae07f435df040041ae6b196ebc57e5038">FSMC_BCR1_WRAPMOD_Msk</a></td></tr>
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<tr class="separator:gad215e95feee8339393bd93a2bcea11f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa37e744f19838aaaaa33e3184d68904e" id="r_gaa37e744f19838aaaaa33e3184d68904e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa37e744f19838aaaaa33e3184d68904e">FSMC_BCR1_WAITCFG_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaa37e744f19838aaaaa33e3184d68904e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacccfccbca149c2df3ec50918bcb5822e" id="r_gacccfccbca149c2df3ec50918bcb5822e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacccfccbca149c2df3ec50918bcb5822e">FSMC_BCR1_WAITCFG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa37e744f19838aaaaa33e3184d68904e">FSMC_BCR1_WAITCFG_Pos</a>)</td></tr>
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<tr class="separator:gacccfccbca149c2df3ec50918bcb5822e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga141a337e3f1479e79d62b567ba685bcf" id="r_ga141a337e3f1479e79d62b567ba685bcf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga141a337e3f1479e79d62b567ba685bcf">FSMC_BCR1_WAITCFG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacccfccbca149c2df3ec50918bcb5822e">FSMC_BCR1_WAITCFG_Msk</a></td></tr>
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<tr class="separator:ga141a337e3f1479e79d62b567ba685bcf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa816e36a3fdd330c2f0ce4e4cceabf43" id="r_gaa816e36a3fdd330c2f0ce4e4cceabf43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa816e36a3fdd330c2f0ce4e4cceabf43">FSMC_BCR1_WREN_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaa816e36a3fdd330c2f0ce4e4cceabf43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d6049a6f86dcc5df8daaaa481e6927d" id="r_ga1d6049a6f86dcc5df8daaaa481e6927d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d6049a6f86dcc5df8daaaa481e6927d">FSMC_BCR1_WREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa816e36a3fdd330c2f0ce4e4cceabf43">FSMC_BCR1_WREN_Pos</a>)</td></tr>
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<tr class="separator:ga1d6049a6f86dcc5df8daaaa481e6927d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7349a91da7ba38277a068f4e8eea314" id="r_gaa7349a91da7ba38277a068f4e8eea314"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7349a91da7ba38277a068f4e8eea314">FSMC_BCR1_WREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d6049a6f86dcc5df8daaaa481e6927d">FSMC_BCR1_WREN_Msk</a></td></tr>
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<tr class="memitem:ga0a3407dc3470cd1ced7fd05ffb11159b" id="r_ga0a3407dc3470cd1ced7fd05ffb11159b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a3407dc3470cd1ced7fd05ffb11159b">FSMC_BCR1_WAITEN_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga423ede6efc2a21e6a832faf9154df8a0" id="r_ga423ede6efc2a21e6a832faf9154df8a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga423ede6efc2a21e6a832faf9154df8a0">FSMC_BCR1_WAITEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a3407dc3470cd1ced7fd05ffb11159b">FSMC_BCR1_WAITEN_Pos</a>)</td></tr>
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<tr class="separator:ga423ede6efc2a21e6a832faf9154df8a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe4611a02a4fa635b66d5b5e52328fc5" id="r_gabe4611a02a4fa635b66d5b5e52328fc5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe4611a02a4fa635b66d5b5e52328fc5">FSMC_BCR1_WAITEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga423ede6efc2a21e6a832faf9154df8a0">FSMC_BCR1_WAITEN_Msk</a></td></tr>
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<tr class="separator:gabe4611a02a4fa635b66d5b5e52328fc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b6b842527b6be91baf209d302c0dcb2" id="r_ga8b6b842527b6be91baf209d302c0dcb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b6b842527b6be91baf209d302c0dcb2">FSMC_BCR1_EXTMOD_Pos</a>   (14U)</td></tr>
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<tr class="memitem:ga59c8fad26fdda8528641ccde63012333" id="r_ga59c8fad26fdda8528641ccde63012333"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59c8fad26fdda8528641ccde63012333">FSMC_BCR1_EXTMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b6b842527b6be91baf209d302c0dcb2">FSMC_BCR1_EXTMOD_Pos</a>)</td></tr>
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<tr class="separator:ga59c8fad26fdda8528641ccde63012333"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7936ff74a1cfba880a9b5bc943dc8661" id="r_ga7936ff74a1cfba880a9b5bc943dc8661"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7936ff74a1cfba880a9b5bc943dc8661">FSMC_BCR1_EXTMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga59c8fad26fdda8528641ccde63012333">FSMC_BCR1_EXTMOD_Msk</a></td></tr>
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<tr class="separator:ga7936ff74a1cfba880a9b5bc943dc8661"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49520648ee432b57ad212494763df6f0" id="r_ga49520648ee432b57ad212494763df6f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49520648ee432b57ad212494763df6f0">FSMC_BCR1_ASYNCWAIT_Pos</a>   (15U)</td></tr>
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<tr class="memitem:gaf2587d2fc09a87653afa500cc77ce010" id="r_gaf2587d2fc09a87653afa500cc77ce010"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2587d2fc09a87653afa500cc77ce010">FSMC_BCR1_ASYNCWAIT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga49520648ee432b57ad212494763df6f0">FSMC_BCR1_ASYNCWAIT_Pos</a>)</td></tr>
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<tr class="separator:gaf2587d2fc09a87653afa500cc77ce010"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5673d96c0fb27c7faed335e05ad41c1" id="r_gaf5673d96c0fb27c7faed335e05ad41c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5673d96c0fb27c7faed335e05ad41c1">FSMC_BCR1_ASYNCWAIT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2587d2fc09a87653afa500cc77ce010">FSMC_BCR1_ASYNCWAIT_Msk</a></td></tr>
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<tr class="separator:gaf5673d96c0fb27c7faed335e05ad41c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga150c6b16ddf3ab16470062b3aa651c42" id="r_ga150c6b16ddf3ab16470062b3aa651c42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga150c6b16ddf3ab16470062b3aa651c42">FSMC_BCR1_CPSIZE_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga150c6b16ddf3ab16470062b3aa651c42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10293af49314e88488ceb0d3e0faa53a" id="r_ga10293af49314e88488ceb0d3e0faa53a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10293af49314e88488ceb0d3e0faa53a">FSMC_BCR1_CPSIZE_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga150c6b16ddf3ab16470062b3aa651c42">FSMC_BCR1_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga10293af49314e88488ceb0d3e0faa53a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga192791b6dc4c25e4992b07f098006a4e" id="r_ga192791b6dc4c25e4992b07f098006a4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga192791b6dc4c25e4992b07f098006a4e">FSMC_BCR1_CPSIZE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga10293af49314e88488ceb0d3e0faa53a">FSMC_BCR1_CPSIZE_Msk</a></td></tr>
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<tr class="separator:ga192791b6dc4c25e4992b07f098006a4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90f6d13b70b5cadaf0325336ffa204c2" id="r_ga90f6d13b70b5cadaf0325336ffa204c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90f6d13b70b5cadaf0325336ffa204c2">FSMC_BCR1_CPSIZE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga150c6b16ddf3ab16470062b3aa651c42">FSMC_BCR1_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga90f6d13b70b5cadaf0325336ffa204c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23f9cde76aa0df2b76bec396614542d2" id="r_ga23f9cde76aa0df2b76bec396614542d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23f9cde76aa0df2b76bec396614542d2">FSMC_BCR1_CPSIZE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga150c6b16ddf3ab16470062b3aa651c42">FSMC_BCR1_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga23f9cde76aa0df2b76bec396614542d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b7e96850fe4f75e4ad878696ef94356" id="r_ga6b7e96850fe4f75e4ad878696ef94356"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b7e96850fe4f75e4ad878696ef94356">FSMC_BCR1_CPSIZE_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga150c6b16ddf3ab16470062b3aa651c42">FSMC_BCR1_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga6b7e96850fe4f75e4ad878696ef94356"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92b8ede1953ab41ab13d6a6d62953ffa" id="r_ga92b8ede1953ab41ab13d6a6d62953ffa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92b8ede1953ab41ab13d6a6d62953ffa">FSMC_BCR1_CBURSTRW_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga92b8ede1953ab41ab13d6a6d62953ffa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56ae50002811cf51dce4cb26da2a18bb" id="r_ga56ae50002811cf51dce4cb26da2a18bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56ae50002811cf51dce4cb26da2a18bb">FSMC_BCR1_CBURSTRW_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92b8ede1953ab41ab13d6a6d62953ffa">FSMC_BCR1_CBURSTRW_Pos</a>)</td></tr>
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<tr class="separator:ga56ae50002811cf51dce4cb26da2a18bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga015672f5aa2132a55e316f5b7a577174" id="r_ga015672f5aa2132a55e316f5b7a577174"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga015672f5aa2132a55e316f5b7a577174">FSMC_BCR1_CBURSTRW</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga56ae50002811cf51dce4cb26da2a18bb">FSMC_BCR1_CBURSTRW_Msk</a></td></tr>
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<tr class="separator:ga015672f5aa2132a55e316f5b7a577174"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ad7fd4c0644328d6b50f1af802ec2f8" id="r_ga8ad7fd4c0644328d6b50f1af802ec2f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ad7fd4c0644328d6b50f1af802ec2f8">FSMC_BCR2_MBKEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8ad7fd4c0644328d6b50f1af802ec2f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6ef33bf632e3d9fbe345050be4f322a" id="r_gaa6ef33bf632e3d9fbe345050be4f322a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6ef33bf632e3d9fbe345050be4f322a">FSMC_BCR2_MBKEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ad7fd4c0644328d6b50f1af802ec2f8">FSMC_BCR2_MBKEN_Pos</a>)</td></tr>
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<tr class="separator:gaa6ef33bf632e3d9fbe345050be4f322a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9c99df3c6cebc68f6695ad7bc13f717" id="r_gad9c99df3c6cebc68f6695ad7bc13f717"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9c99df3c6cebc68f6695ad7bc13f717">FSMC_BCR2_MBKEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6ef33bf632e3d9fbe345050be4f322a">FSMC_BCR2_MBKEN_Msk</a></td></tr>
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<tr class="separator:gad9c99df3c6cebc68f6695ad7bc13f717"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ac9fba61cf9cc72921d4f428738826c" id="r_ga6ac9fba61cf9cc72921d4f428738826c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ac9fba61cf9cc72921d4f428738826c">FSMC_BCR2_MUXEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga6ac9fba61cf9cc72921d4f428738826c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bf9eb6b6bdd6af3179dddcaabca890a" id="r_ga4bf9eb6b6bdd6af3179dddcaabca890a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bf9eb6b6bdd6af3179dddcaabca890a">FSMC_BCR2_MUXEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ac9fba61cf9cc72921d4f428738826c">FSMC_BCR2_MUXEN_Pos</a>)</td></tr>
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<tr class="separator:ga4bf9eb6b6bdd6af3179dddcaabca890a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f65c4348ab55c12695730bde8be8986" id="r_ga9f65c4348ab55c12695730bde8be8986"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f65c4348ab55c12695730bde8be8986">FSMC_BCR2_MUXEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bf9eb6b6bdd6af3179dddcaabca890a">FSMC_BCR2_MUXEN_Msk</a></td></tr>
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<tr class="separator:ga9f65c4348ab55c12695730bde8be8986"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7789cdcc69a54e451f419b3d5266edac" id="r_ga7789cdcc69a54e451f419b3d5266edac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7789cdcc69a54e451f419b3d5266edac">FSMC_BCR2_MTYP_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga7789cdcc69a54e451f419b3d5266edac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga166ddafe3e417b6bb11f233e4e2dedf3" id="r_ga166ddafe3e417b6bb11f233e4e2dedf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga166ddafe3e417b6bb11f233e4e2dedf3">FSMC_BCR2_MTYP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7789cdcc69a54e451f419b3d5266edac">FSMC_BCR2_MTYP_Pos</a>)</td></tr>
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<tr class="separator:ga166ddafe3e417b6bb11f233e4e2dedf3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdf82247710aaeff72fb37113bff3daf" id="r_gabdf82247710aaeff72fb37113bff3daf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdf82247710aaeff72fb37113bff3daf">FSMC_BCR2_MTYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga166ddafe3e417b6bb11f233e4e2dedf3">FSMC_BCR2_MTYP_Msk</a></td></tr>
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<tr class="separator:gabdf82247710aaeff72fb37113bff3daf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac595e1e3045aad0b379367f47bf10a84" id="r_gac595e1e3045aad0b379367f47bf10a84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac595e1e3045aad0b379367f47bf10a84">FSMC_BCR2_MTYP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7789cdcc69a54e451f419b3d5266edac">FSMC_BCR2_MTYP_Pos</a>)</td></tr>
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<tr class="separator:gac595e1e3045aad0b379367f47bf10a84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b9e5b00171ea739ba67a627a2484f47" id="r_ga8b9e5b00171ea739ba67a627a2484f47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b9e5b00171ea739ba67a627a2484f47">FSMC_BCR2_MTYP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7789cdcc69a54e451f419b3d5266edac">FSMC_BCR2_MTYP_Pos</a>)</td></tr>
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<tr class="separator:ga8b9e5b00171ea739ba67a627a2484f47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5a899fbf4b3ed1a7fa6ee26cea383b4" id="r_gae5a899fbf4b3ed1a7fa6ee26cea383b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5a899fbf4b3ed1a7fa6ee26cea383b4">FSMC_BCR2_MWID_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae5a899fbf4b3ed1a7fa6ee26cea383b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a1f1c8878a8d8a6680537bf0c5ae926" id="r_ga8a1f1c8878a8d8a6680537bf0c5ae926"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a1f1c8878a8d8a6680537bf0c5ae926">FSMC_BCR2_MWID_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5a899fbf4b3ed1a7fa6ee26cea383b4">FSMC_BCR2_MWID_Pos</a>)</td></tr>
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<tr class="separator:ga8a1f1c8878a8d8a6680537bf0c5ae926"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4099746e30f71a98ea71d1048a5d028a" id="r_ga4099746e30f71a98ea71d1048a5d028a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4099746e30f71a98ea71d1048a5d028a">FSMC_BCR2_MWID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a1f1c8878a8d8a6680537bf0c5ae926">FSMC_BCR2_MWID_Msk</a></td></tr>
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<tr class="memitem:ga8501d3ce728f6a074061294a9e5a54cf" id="r_ga8501d3ce728f6a074061294a9e5a54cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8501d3ce728f6a074061294a9e5a54cf">FSMC_BCR2_MWID_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5a899fbf4b3ed1a7fa6ee26cea383b4">FSMC_BCR2_MWID_Pos</a>)</td></tr>
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<tr class="memitem:ga74276c5828d545cf4b2db2d568c60627" id="r_ga74276c5828d545cf4b2db2d568c60627"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74276c5828d545cf4b2db2d568c60627">FSMC_BCR2_MWID_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5a899fbf4b3ed1a7fa6ee26cea383b4">FSMC_BCR2_MWID_Pos</a>)</td></tr>
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<tr class="memitem:ga5111c287808eaefab515193e2bfe738e" id="r_ga5111c287808eaefab515193e2bfe738e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5111c287808eaefab515193e2bfe738e">FSMC_BCR2_FACCEN_Pos</a>   (6U)</td></tr>
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<tr class="memitem:ga182a7aed98f38419b4d55f4e746ddb78" id="r_ga182a7aed98f38419b4d55f4e746ddb78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga182a7aed98f38419b4d55f4e746ddb78">FSMC_BCR2_FACCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5111c287808eaefab515193e2bfe738e">FSMC_BCR2_FACCEN_Pos</a>)</td></tr>
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<tr class="memitem:ga7a4e1ad30533ab54b45987cab30d51a0" id="r_ga7a4e1ad30533ab54b45987cab30d51a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a4e1ad30533ab54b45987cab30d51a0">FSMC_BCR2_FACCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga182a7aed98f38419b4d55f4e746ddb78">FSMC_BCR2_FACCEN_Msk</a></td></tr>
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<tr class="memitem:ga061b10b005a1fddca182f8df1a520fbd" id="r_ga061b10b005a1fddca182f8df1a520fbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga061b10b005a1fddca182f8df1a520fbd">FSMC_BCR2_BURSTEN_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga061b10b005a1fddca182f8df1a520fbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04ef7898a3300a0e437e98e0f3e266e3" id="r_ga04ef7898a3300a0e437e98e0f3e266e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04ef7898a3300a0e437e98e0f3e266e3">FSMC_BCR2_BURSTEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga061b10b005a1fddca182f8df1a520fbd">FSMC_BCR2_BURSTEN_Pos</a>)</td></tr>
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<tr class="memitem:ga0d8202b9b40d3912a6294fe2a0e28ebf" id="r_ga0d8202b9b40d3912a6294fe2a0e28ebf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d8202b9b40d3912a6294fe2a0e28ebf">FSMC_BCR2_BURSTEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga04ef7898a3300a0e437e98e0f3e266e3">FSMC_BCR2_BURSTEN_Msk</a></td></tr>
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<tr class="memitem:gaf39e91bdf996e863420c7e8fc1e5590e" id="r_gaf39e91bdf996e863420c7e8fc1e5590e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf39e91bdf996e863420c7e8fc1e5590e">FSMC_BCR2_WAITPOL_Pos</a>   (9U)</td></tr>
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<tr class="memitem:ga363eda93ed7acbb8f0d18a3a291730c7" id="r_ga363eda93ed7acbb8f0d18a3a291730c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga363eda93ed7acbb8f0d18a3a291730c7">FSMC_BCR2_WAITPOL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf39e91bdf996e863420c7e8fc1e5590e">FSMC_BCR2_WAITPOL_Pos</a>)</td></tr>
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<tr class="separator:ga363eda93ed7acbb8f0d18a3a291730c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0f59e7aa2664f9c767ce22bec369698" id="r_gaa0f59e7aa2664f9c767ce22bec369698"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0f59e7aa2664f9c767ce22bec369698">FSMC_BCR2_WAITPOL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga363eda93ed7acbb8f0d18a3a291730c7">FSMC_BCR2_WAITPOL_Msk</a></td></tr>
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<tr class="memitem:ga789e78a6f20dfc6d81c80f6f1c6c52a6" id="r_ga789e78a6f20dfc6d81c80f6f1c6c52a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga789e78a6f20dfc6d81c80f6f1c6c52a6">FSMC_BCR2_WRAPMOD_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga789e78a6f20dfc6d81c80f6f1c6c52a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3424ec4e7bd6b62133ca3427cc80293c" id="r_ga3424ec4e7bd6b62133ca3427cc80293c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3424ec4e7bd6b62133ca3427cc80293c">FSMC_BCR2_WRAPMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga789e78a6f20dfc6d81c80f6f1c6c52a6">FSMC_BCR2_WRAPMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga9e93e4e902a636d4d75a1fd7e884afea" id="r_ga9e93e4e902a636d4d75a1fd7e884afea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e93e4e902a636d4d75a1fd7e884afea">FSMC_BCR2_WRAPMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3424ec4e7bd6b62133ca3427cc80293c">FSMC_BCR2_WRAPMOD_Msk</a></td></tr>
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<tr class="separator:ga9e93e4e902a636d4d75a1fd7e884afea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e9aee1a917ef0b27eb9b5734f853670" id="r_ga7e9aee1a917ef0b27eb9b5734f853670"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e9aee1a917ef0b27eb9b5734f853670">FSMC_BCR2_WAITCFG_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga0200789ac85e6c5e1e481c3df1446e18" id="r_ga0200789ac85e6c5e1e481c3df1446e18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0200789ac85e6c5e1e481c3df1446e18">FSMC_BCR2_WAITCFG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e9aee1a917ef0b27eb9b5734f853670">FSMC_BCR2_WAITCFG_Pos</a>)</td></tr>
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<tr class="separator:ga0200789ac85e6c5e1e481c3df1446e18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5141640b4dcb78a524740b681819f9f1" id="r_ga5141640b4dcb78a524740b681819f9f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5141640b4dcb78a524740b681819f9f1">FSMC_BCR2_WAITCFG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0200789ac85e6c5e1e481c3df1446e18">FSMC_BCR2_WAITCFG_Msk</a></td></tr>
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<tr class="separator:ga5141640b4dcb78a524740b681819f9f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c00df8248fceccd441d5d4b73b86622" id="r_ga1c00df8248fceccd441d5d4b73b86622"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c00df8248fceccd441d5d4b73b86622">FSMC_BCR2_WREN_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga1c00df8248fceccd441d5d4b73b86622"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33a8ad888dead565af3852d70b3ad6b9" id="r_ga33a8ad888dead565af3852d70b3ad6b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33a8ad888dead565af3852d70b3ad6b9">FSMC_BCR2_WREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c00df8248fceccd441d5d4b73b86622">FSMC_BCR2_WREN_Pos</a>)</td></tr>
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<tr class="separator:ga33a8ad888dead565af3852d70b3ad6b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad446f2fcb7909b80a8c1731141be5186" id="r_gad446f2fcb7909b80a8c1731141be5186"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad446f2fcb7909b80a8c1731141be5186">FSMC_BCR2_WREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga33a8ad888dead565af3852d70b3ad6b9">FSMC_BCR2_WREN_Msk</a></td></tr>
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<tr class="memitem:ga8f4660e60da72244831d66378c76b627" id="r_ga8f4660e60da72244831d66378c76b627"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f4660e60da72244831d66378c76b627">FSMC_BCR2_WAITEN_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga8f4660e60da72244831d66378c76b627"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8c82d9bdf8bfef070bc96dcfe7e3d8d" id="r_gac8c82d9bdf8bfef070bc96dcfe7e3d8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8c82d9bdf8bfef070bc96dcfe7e3d8d">FSMC_BCR2_WAITEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f4660e60da72244831d66378c76b627">FSMC_BCR2_WAITEN_Pos</a>)</td></tr>
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<tr class="memitem:gad015d2aa1c58b48681f35a4f92eaf7f7" id="r_gad015d2aa1c58b48681f35a4f92eaf7f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad015d2aa1c58b48681f35a4f92eaf7f7">FSMC_BCR2_WAITEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac8c82d9bdf8bfef070bc96dcfe7e3d8d">FSMC_BCR2_WAITEN_Msk</a></td></tr>
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<tr class="separator:gad015d2aa1c58b48681f35a4f92eaf7f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7799a975be4610d90af7d63aff4eb8f6" id="r_ga7799a975be4610d90af7d63aff4eb8f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7799a975be4610d90af7d63aff4eb8f6">FSMC_BCR2_EXTMOD_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga7799a975be4610d90af7d63aff4eb8f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0d624c95c3930043d2561545ecfd5a5" id="r_gab0d624c95c3930043d2561545ecfd5a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0d624c95c3930043d2561545ecfd5a5">FSMC_BCR2_EXTMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7799a975be4610d90af7d63aff4eb8f6">FSMC_BCR2_EXTMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga76d3e5d899ba2399d3318da577d58ac6" id="r_ga76d3e5d899ba2399d3318da577d58ac6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76d3e5d899ba2399d3318da577d58ac6">FSMC_BCR2_EXTMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab0d624c95c3930043d2561545ecfd5a5">FSMC_BCR2_EXTMOD_Msk</a></td></tr>
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<tr class="separator:ga76d3e5d899ba2399d3318da577d58ac6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca3661a377838f2fcd8d13def99b2bfe" id="r_gaca3661a377838f2fcd8d13def99b2bfe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca3661a377838f2fcd8d13def99b2bfe">FSMC_BCR2_ASYNCWAIT_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaca3661a377838f2fcd8d13def99b2bfe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5afee4a8591dcaaa4161fbb6ca509c68" id="r_ga5afee4a8591dcaaa4161fbb6ca509c68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5afee4a8591dcaaa4161fbb6ca509c68">FSMC_BCR2_ASYNCWAIT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaca3661a377838f2fcd8d13def99b2bfe">FSMC_BCR2_ASYNCWAIT_Pos</a>)</td></tr>
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<tr class="separator:ga5afee4a8591dcaaa4161fbb6ca509c68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad45d1b552ba61ccbb1dc4ebfc556285a" id="r_gad45d1b552ba61ccbb1dc4ebfc556285a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad45d1b552ba61ccbb1dc4ebfc556285a">FSMC_BCR2_ASYNCWAIT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5afee4a8591dcaaa4161fbb6ca509c68">FSMC_BCR2_ASYNCWAIT_Msk</a></td></tr>
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<tr class="memitem:ga29b50188ab8dd06a8dcea1db253c43d3" id="r_ga29b50188ab8dd06a8dcea1db253c43d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29b50188ab8dd06a8dcea1db253c43d3">FSMC_BCR2_CPSIZE_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga29b50188ab8dd06a8dcea1db253c43d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga379d9cd3ddb5ad5c73a6aaecd6a39842" id="r_ga379d9cd3ddb5ad5c73a6aaecd6a39842"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga379d9cd3ddb5ad5c73a6aaecd6a39842">FSMC_BCR2_CPSIZE_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga29b50188ab8dd06a8dcea1db253c43d3">FSMC_BCR2_CPSIZE_Pos</a>)</td></tr>
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<tr class="memitem:ga4546f80f34121d6700fbb8389f69854a" id="r_ga4546f80f34121d6700fbb8389f69854a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4546f80f34121d6700fbb8389f69854a">FSMC_BCR2_CPSIZE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga379d9cd3ddb5ad5c73a6aaecd6a39842">FSMC_BCR2_CPSIZE_Msk</a></td></tr>
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<tr class="memitem:ga4bd12d2e7ea6f99a6fb5c2519d3f7a48" id="r_ga4bd12d2e7ea6f99a6fb5c2519d3f7a48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bd12d2e7ea6f99a6fb5c2519d3f7a48">FSMC_BCR2_CPSIZE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga29b50188ab8dd06a8dcea1db253c43d3">FSMC_BCR2_CPSIZE_Pos</a>)</td></tr>
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<tr class="memitem:ga2db6a0901e5f500c9c907a8fa2304c4d" id="r_ga2db6a0901e5f500c9c907a8fa2304c4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6a0901e5f500c9c907a8fa2304c4d">FSMC_BCR2_CPSIZE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga29b50188ab8dd06a8dcea1db253c43d3">FSMC_BCR2_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga2db6a0901e5f500c9c907a8fa2304c4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga983f7ba781deff462208b000d0749d42" id="r_ga983f7ba781deff462208b000d0749d42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga983f7ba781deff462208b000d0749d42">FSMC_BCR2_CPSIZE_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga29b50188ab8dd06a8dcea1db253c43d3">FSMC_BCR2_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga983f7ba781deff462208b000d0749d42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4234ff44107642d57fc60bb1b4986d5" id="r_gaf4234ff44107642d57fc60bb1b4986d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4234ff44107642d57fc60bb1b4986d5">FSMC_BCR2_CBURSTRW_Pos</a>   (19U)</td></tr>
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<tr class="memitem:ga354accac428f799c4156a56f43d81c5e" id="r_ga354accac428f799c4156a56f43d81c5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga354accac428f799c4156a56f43d81c5e">FSMC_BCR2_CBURSTRW_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4234ff44107642d57fc60bb1b4986d5">FSMC_BCR2_CBURSTRW_Pos</a>)</td></tr>
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<tr class="separator:ga354accac428f799c4156a56f43d81c5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae64b1874f1ab83a1d0224cb66e504dff" id="r_gae64b1874f1ab83a1d0224cb66e504dff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae64b1874f1ab83a1d0224cb66e504dff">FSMC_BCR2_CBURSTRW</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga354accac428f799c4156a56f43d81c5e">FSMC_BCR2_CBURSTRW_Msk</a></td></tr>
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<tr class="separator:gae64b1874f1ab83a1d0224cb66e504dff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5eb6d03fe467aad546d992b73194cb27" id="r_ga5eb6d03fe467aad546d992b73194cb27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5eb6d03fe467aad546d992b73194cb27">FSMC_BCR3_MBKEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5eb6d03fe467aad546d992b73194cb27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga969d8a0800e499c8cfaae30766673baf" id="r_ga969d8a0800e499c8cfaae30766673baf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga969d8a0800e499c8cfaae30766673baf">FSMC_BCR3_MBKEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5eb6d03fe467aad546d992b73194cb27">FSMC_BCR3_MBKEN_Pos</a>)</td></tr>
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<tr class="separator:ga969d8a0800e499c8cfaae30766673baf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d7810ad338086a1ec9b15f339ed6f4d" id="r_ga0d7810ad338086a1ec9b15f339ed6f4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d7810ad338086a1ec9b15f339ed6f4d">FSMC_BCR3_MBKEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga969d8a0800e499c8cfaae30766673baf">FSMC_BCR3_MBKEN_Msk</a></td></tr>
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<tr class="separator:ga0d7810ad338086a1ec9b15f339ed6f4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga257d8fa0925c2a6e4ca3c71724a1c727" id="r_ga257d8fa0925c2a6e4ca3c71724a1c727"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga257d8fa0925c2a6e4ca3c71724a1c727">FSMC_BCR3_MUXEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga257d8fa0925c2a6e4ca3c71724a1c727"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade598d66e7b6ff96d1cc42e78566291b" id="r_gade598d66e7b6ff96d1cc42e78566291b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade598d66e7b6ff96d1cc42e78566291b">FSMC_BCR3_MUXEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga257d8fa0925c2a6e4ca3c71724a1c727">FSMC_BCR3_MUXEN_Pos</a>)</td></tr>
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<tr class="separator:gade598d66e7b6ff96d1cc42e78566291b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadaae648c8591e7650cba828910638d3d" id="r_gadaae648c8591e7650cba828910638d3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadaae648c8591e7650cba828910638d3d">FSMC_BCR3_MUXEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gade598d66e7b6ff96d1cc42e78566291b">FSMC_BCR3_MUXEN_Msk</a></td></tr>
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<tr class="separator:gadaae648c8591e7650cba828910638d3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab67e61d2783a793ef984e897897212fa" id="r_gab67e61d2783a793ef984e897897212fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab67e61d2783a793ef984e897897212fa">FSMC_BCR3_MTYP_Pos</a>   (2U)</td></tr>
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<tr class="separator:gab67e61d2783a793ef984e897897212fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga988d00e68c4a63b1fc0b575bd9297db2" id="r_ga988d00e68c4a63b1fc0b575bd9297db2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga988d00e68c4a63b1fc0b575bd9297db2">FSMC_BCR3_MTYP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab67e61d2783a793ef984e897897212fa">FSMC_BCR3_MTYP_Pos</a>)</td></tr>
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<tr class="separator:ga988d00e68c4a63b1fc0b575bd9297db2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga319fb6069b651eb947b4d0ba3c9f6196" id="r_ga319fb6069b651eb947b4d0ba3c9f6196"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga319fb6069b651eb947b4d0ba3c9f6196">FSMC_BCR3_MTYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga988d00e68c4a63b1fc0b575bd9297db2">FSMC_BCR3_MTYP_Msk</a></td></tr>
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<tr class="separator:ga319fb6069b651eb947b4d0ba3c9f6196"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf33b80510e653dd32de2ae1ec1a1dfb5" id="r_gaf33b80510e653dd32de2ae1ec1a1dfb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf33b80510e653dd32de2ae1ec1a1dfb5">FSMC_BCR3_MTYP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab67e61d2783a793ef984e897897212fa">FSMC_BCR3_MTYP_Pos</a>)</td></tr>
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<tr class="separator:gaf33b80510e653dd32de2ae1ec1a1dfb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a038553e3a30df4b6e331cad504069b" id="r_ga2a038553e3a30df4b6e331cad504069b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a038553e3a30df4b6e331cad504069b">FSMC_BCR3_MTYP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab67e61d2783a793ef984e897897212fa">FSMC_BCR3_MTYP_Pos</a>)</td></tr>
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<tr class="separator:ga2a038553e3a30df4b6e331cad504069b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17b5f1b6b3101230c49e90176f430673" id="r_ga17b5f1b6b3101230c49e90176f430673"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17b5f1b6b3101230c49e90176f430673">FSMC_BCR3_MWID_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga17b5f1b6b3101230c49e90176f430673"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cd430671ae5969640d73b758ffdf612" id="r_ga6cd430671ae5969640d73b758ffdf612"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cd430671ae5969640d73b758ffdf612">FSMC_BCR3_MWID_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17b5f1b6b3101230c49e90176f430673">FSMC_BCR3_MWID_Pos</a>)</td></tr>
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<tr class="separator:ga6cd430671ae5969640d73b758ffdf612"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51097cfe8d4263a30d292e7e9dc73cd2" id="r_ga51097cfe8d4263a30d292e7e9dc73cd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51097cfe8d4263a30d292e7e9dc73cd2">FSMC_BCR3_MWID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cd430671ae5969640d73b758ffdf612">FSMC_BCR3_MWID_Msk</a></td></tr>
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<tr class="separator:ga51097cfe8d4263a30d292e7e9dc73cd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga373b764c1a4104300eb587aa4510c1f1" id="r_ga373b764c1a4104300eb587aa4510c1f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga373b764c1a4104300eb587aa4510c1f1">FSMC_BCR3_MWID_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17b5f1b6b3101230c49e90176f430673">FSMC_BCR3_MWID_Pos</a>)</td></tr>
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<tr class="separator:ga373b764c1a4104300eb587aa4510c1f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43c7292c185269cc11d986f3ae0ceb24" id="r_ga43c7292c185269cc11d986f3ae0ceb24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43c7292c185269cc11d986f3ae0ceb24">FSMC_BCR3_MWID_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17b5f1b6b3101230c49e90176f430673">FSMC_BCR3_MWID_Pos</a>)</td></tr>
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<tr class="separator:ga43c7292c185269cc11d986f3ae0ceb24"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70b916af09f1553cb63363b748b1f027" id="r_ga70b916af09f1553cb63363b748b1f027"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70b916af09f1553cb63363b748b1f027">FSMC_BCR3_FACCEN_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga70b916af09f1553cb63363b748b1f027"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38db506ff5f00d90249a3a8521df490b" id="r_ga38db506ff5f00d90249a3a8521df490b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38db506ff5f00d90249a3a8521df490b">FSMC_BCR3_FACCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga70b916af09f1553cb63363b748b1f027">FSMC_BCR3_FACCEN_Pos</a>)</td></tr>
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<tr class="separator:ga38db506ff5f00d90249a3a8521df490b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga380c39b95426ac9a18c70e3f56016c81" id="r_ga380c39b95426ac9a18c70e3f56016c81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga380c39b95426ac9a18c70e3f56016c81">FSMC_BCR3_FACCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38db506ff5f00d90249a3a8521df490b">FSMC_BCR3_FACCEN_Msk</a></td></tr>
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<tr class="separator:ga380c39b95426ac9a18c70e3f56016c81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga334b4a9ae7115924ece63694dcb6ee37" id="r_ga334b4a9ae7115924ece63694dcb6ee37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga334b4a9ae7115924ece63694dcb6ee37">FSMC_BCR3_BURSTEN_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga334b4a9ae7115924ece63694dcb6ee37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga633d9f36439fa9f12c12c2a46152624b" id="r_ga633d9f36439fa9f12c12c2a46152624b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga633d9f36439fa9f12c12c2a46152624b">FSMC_BCR3_BURSTEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga334b4a9ae7115924ece63694dcb6ee37">FSMC_BCR3_BURSTEN_Pos</a>)</td></tr>
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<tr class="separator:ga633d9f36439fa9f12c12c2a46152624b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9badf60f5caa010e041d66d40af596a" id="r_gad9badf60f5caa010e041d66d40af596a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9badf60f5caa010e041d66d40af596a">FSMC_BCR3_BURSTEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga633d9f36439fa9f12c12c2a46152624b">FSMC_BCR3_BURSTEN_Msk</a></td></tr>
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<tr class="separator:gad9badf60f5caa010e041d66d40af596a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8ca3bf2ec7e7869de4f702e2781df26" id="r_gaa8ca3bf2ec7e7869de4f702e2781df26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8ca3bf2ec7e7869de4f702e2781df26">FSMC_BCR3_WAITPOL_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaa8ca3bf2ec7e7869de4f702e2781df26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76308f3761147bead10be8690363ba75" id="r_ga76308f3761147bead10be8690363ba75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76308f3761147bead10be8690363ba75">FSMC_BCR3_WAITPOL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8ca3bf2ec7e7869de4f702e2781df26">FSMC_BCR3_WAITPOL_Pos</a>)</td></tr>
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<tr class="separator:ga76308f3761147bead10be8690363ba75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabbca3d0aa315f3e9bc6bacf244bdb747" id="r_gabbca3d0aa315f3e9bc6bacf244bdb747"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbca3d0aa315f3e9bc6bacf244bdb747">FSMC_BCR3_WAITPOL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga76308f3761147bead10be8690363ba75">FSMC_BCR3_WAITPOL_Msk</a></td></tr>
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<tr class="memitem:gad89219171643f908db3cfa28eee4d5e9" id="r_gad89219171643f908db3cfa28eee4d5e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad89219171643f908db3cfa28eee4d5e9">FSMC_BCR3_WRAPMOD_Pos</a>   (10U)</td></tr>
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<tr class="memitem:gae03d16e63e73b02834d26f33cc91dc64" id="r_gae03d16e63e73b02834d26f33cc91dc64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae03d16e63e73b02834d26f33cc91dc64">FSMC_BCR3_WRAPMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad89219171643f908db3cfa28eee4d5e9">FSMC_BCR3_WRAPMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga44fc6e205695d39b63c0f5b18c3cd214" id="r_ga44fc6e205695d39b63c0f5b18c3cd214"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44fc6e205695d39b63c0f5b18c3cd214">FSMC_BCR3_WRAPMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae03d16e63e73b02834d26f33cc91dc64">FSMC_BCR3_WRAPMOD_Msk</a></td></tr>
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<tr class="separator:ga44fc6e205695d39b63c0f5b18c3cd214"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6429581833534bce92d223e08c93eb32" id="r_ga6429581833534bce92d223e08c93eb32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6429581833534bce92d223e08c93eb32">FSMC_BCR3_WAITCFG_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga6429581833534bce92d223e08c93eb32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86ce7ee19c1952a2cd3a7dd07988d404" id="r_ga86ce7ee19c1952a2cd3a7dd07988d404"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86ce7ee19c1952a2cd3a7dd07988d404">FSMC_BCR3_WAITCFG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6429581833534bce92d223e08c93eb32">FSMC_BCR3_WAITCFG_Pos</a>)</td></tr>
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<tr class="separator:ga86ce7ee19c1952a2cd3a7dd07988d404"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab845515c37adae28d0e1452596cca7ea" id="r_gab845515c37adae28d0e1452596cca7ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab845515c37adae28d0e1452596cca7ea">FSMC_BCR3_WAITCFG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86ce7ee19c1952a2cd3a7dd07988d404">FSMC_BCR3_WAITCFG_Msk</a></td></tr>
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<tr class="separator:gab845515c37adae28d0e1452596cca7ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga704d37df498bac515b6ec4c5e4f94462" id="r_ga704d37df498bac515b6ec4c5e4f94462"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga704d37df498bac515b6ec4c5e4f94462">FSMC_BCR3_WREN_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga704d37df498bac515b6ec4c5e4f94462"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe425cfa93902161f696ee0d9b26e9c5" id="r_gafe425cfa93902161f696ee0d9b26e9c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe425cfa93902161f696ee0d9b26e9c5">FSMC_BCR3_WREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga704d37df498bac515b6ec4c5e4f94462">FSMC_BCR3_WREN_Pos</a>)</td></tr>
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<tr class="separator:gafe425cfa93902161f696ee0d9b26e9c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22c9b0145aa62cafd915a4c7da1931b5" id="r_ga22c9b0145aa62cafd915a4c7da1931b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22c9b0145aa62cafd915a4c7da1931b5">FSMC_BCR3_WREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafe425cfa93902161f696ee0d9b26e9c5">FSMC_BCR3_WREN_Msk</a></td></tr>
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<tr class="separator:ga22c9b0145aa62cafd915a4c7da1931b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabb86a849ca798041db570103d48155c" id="r_gaabb86a849ca798041db570103d48155c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabb86a849ca798041db570103d48155c">FSMC_BCR3_WAITEN_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga955ff9500147df62bd5e71fd46ab399c" id="r_ga955ff9500147df62bd5e71fd46ab399c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga955ff9500147df62bd5e71fd46ab399c">FSMC_BCR3_WAITEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaabb86a849ca798041db570103d48155c">FSMC_BCR3_WAITEN_Pos</a>)</td></tr>
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<tr class="memitem:ga9665b36b791862c464f07ad49dea315c" id="r_ga9665b36b791862c464f07ad49dea315c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9665b36b791862c464f07ad49dea315c">FSMC_BCR3_WAITEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga955ff9500147df62bd5e71fd46ab399c">FSMC_BCR3_WAITEN_Msk</a></td></tr>
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<tr class="memitem:gac15a809e2405d3853528319668a81ef7" id="r_gac15a809e2405d3853528319668a81ef7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac15a809e2405d3853528319668a81ef7">FSMC_BCR3_EXTMOD_Pos</a>   (14U)</td></tr>
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<tr class="memitem:ga5f660417a9ec23815a2d362dea91b1e3" id="r_ga5f660417a9ec23815a2d362dea91b1e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f660417a9ec23815a2d362dea91b1e3">FSMC_BCR3_EXTMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac15a809e2405d3853528319668a81ef7">FSMC_BCR3_EXTMOD_Pos</a>)</td></tr>
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<tr class="separator:ga5f660417a9ec23815a2d362dea91b1e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ab23550b17dca7ede57f8b5ef05f2e7" id="r_ga6ab23550b17dca7ede57f8b5ef05f2e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ab23550b17dca7ede57f8b5ef05f2e7">FSMC_BCR3_EXTMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f660417a9ec23815a2d362dea91b1e3">FSMC_BCR3_EXTMOD_Msk</a></td></tr>
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<tr class="separator:ga6ab23550b17dca7ede57f8b5ef05f2e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7bf971e9566cc6a9e6638e0bca989f6c" id="r_ga7bf971e9566cc6a9e6638e0bca989f6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7bf971e9566cc6a9e6638e0bca989f6c">FSMC_BCR3_ASYNCWAIT_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga7bf971e9566cc6a9e6638e0bca989f6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84c1483478667f1f1121b1b53aaf5bbc" id="r_ga84c1483478667f1f1121b1b53aaf5bbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84c1483478667f1f1121b1b53aaf5bbc">FSMC_BCR3_ASYNCWAIT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7bf971e9566cc6a9e6638e0bca989f6c">FSMC_BCR3_ASYNCWAIT_Pos</a>)</td></tr>
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<tr class="separator:ga84c1483478667f1f1121b1b53aaf5bbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e16fb6b68a8adb7722871ccdd2d9a44" id="r_ga9e16fb6b68a8adb7722871ccdd2d9a44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e16fb6b68a8adb7722871ccdd2d9a44">FSMC_BCR3_ASYNCWAIT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga84c1483478667f1f1121b1b53aaf5bbc">FSMC_BCR3_ASYNCWAIT_Msk</a></td></tr>
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<tr class="separator:ga9e16fb6b68a8adb7722871ccdd2d9a44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaecac8e30310435e28ad6456946b63ceb" id="r_gaecac8e30310435e28ad6456946b63ceb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecac8e30310435e28ad6456946b63ceb">FSMC_BCR3_CPSIZE_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga31e584400d48bf2a9f09b16d93e9aab4" id="r_ga31e584400d48bf2a9f09b16d93e9aab4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31e584400d48bf2a9f09b16d93e9aab4">FSMC_BCR3_CPSIZE_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaecac8e30310435e28ad6456946b63ceb">FSMC_BCR3_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga31e584400d48bf2a9f09b16d93e9aab4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49e7953ee4991f90a96c3b6a72315731" id="r_ga49e7953ee4991f90a96c3b6a72315731"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49e7953ee4991f90a96c3b6a72315731">FSMC_BCR3_CPSIZE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31e584400d48bf2a9f09b16d93e9aab4">FSMC_BCR3_CPSIZE_Msk</a></td></tr>
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<tr class="separator:ga49e7953ee4991f90a96c3b6a72315731"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbe607c14de8dfcce9919fecba70f4b4" id="r_gadbe607c14de8dfcce9919fecba70f4b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbe607c14de8dfcce9919fecba70f4b4">FSMC_BCR3_CPSIZE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaecac8e30310435e28ad6456946b63ceb">FSMC_BCR3_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:gadbe607c14de8dfcce9919fecba70f4b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6790c025341fd005cee64fb8a4a231d8" id="r_ga6790c025341fd005cee64fb8a4a231d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6790c025341fd005cee64fb8a4a231d8">FSMC_BCR3_CPSIZE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaecac8e30310435e28ad6456946b63ceb">FSMC_BCR3_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga6790c025341fd005cee64fb8a4a231d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad77d43cb841e9374c76e93ea443630ad" id="r_gad77d43cb841e9374c76e93ea443630ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad77d43cb841e9374c76e93ea443630ad">FSMC_BCR3_CPSIZE_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaecac8e30310435e28ad6456946b63ceb">FSMC_BCR3_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:gad77d43cb841e9374c76e93ea443630ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07716de72f0cdc426b9c6989d680e05e" id="r_ga07716de72f0cdc426b9c6989d680e05e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07716de72f0cdc426b9c6989d680e05e">FSMC_BCR3_CBURSTRW_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga07716de72f0cdc426b9c6989d680e05e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad14301188370a35a883fbd2c29fbfab7" id="r_gad14301188370a35a883fbd2c29fbfab7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad14301188370a35a883fbd2c29fbfab7">FSMC_BCR3_CBURSTRW_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07716de72f0cdc426b9c6989d680e05e">FSMC_BCR3_CBURSTRW_Pos</a>)</td></tr>
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<tr class="separator:gad14301188370a35a883fbd2c29fbfab7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70c6da37696af84767f82efd0df3a7da" id="r_ga70c6da37696af84767f82efd0df3a7da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70c6da37696af84767f82efd0df3a7da">FSMC_BCR3_CBURSTRW</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad14301188370a35a883fbd2c29fbfab7">FSMC_BCR3_CBURSTRW_Msk</a></td></tr>
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<tr class="separator:ga70c6da37696af84767f82efd0df3a7da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae79298022ec557019f4b238bc0a1c93e" id="r_gae79298022ec557019f4b238bc0a1c93e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae79298022ec557019f4b238bc0a1c93e">FSMC_BCR4_MBKEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae79298022ec557019f4b238bc0a1c93e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b3f9e5b69de79c42b203113832b8767" id="r_ga8b3f9e5b69de79c42b203113832b8767"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b3f9e5b69de79c42b203113832b8767">FSMC_BCR4_MBKEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae79298022ec557019f4b238bc0a1c93e">FSMC_BCR4_MBKEN_Pos</a>)</td></tr>
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<tr class="separator:ga8b3f9e5b69de79c42b203113832b8767"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a1ea2c2967cda7ef1597c4fb1a9dd9a" id="r_ga9a1ea2c2967cda7ef1597c4fb1a9dd9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a1ea2c2967cda7ef1597c4fb1a9dd9a">FSMC_BCR4_MBKEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b3f9e5b69de79c42b203113832b8767">FSMC_BCR4_MBKEN_Msk</a></td></tr>
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<tr class="separator:ga9a1ea2c2967cda7ef1597c4fb1a9dd9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga241a30edf0f4403c5154c249277443a8" id="r_ga241a30edf0f4403c5154c249277443a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga241a30edf0f4403c5154c249277443a8">FSMC_BCR4_MUXEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga241a30edf0f4403c5154c249277443a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1556380a7357a40ef14a0e064adb39ef" id="r_ga1556380a7357a40ef14a0e064adb39ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1556380a7357a40ef14a0e064adb39ef">FSMC_BCR4_MUXEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga241a30edf0f4403c5154c249277443a8">FSMC_BCR4_MUXEN_Pos</a>)</td></tr>
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<tr class="memitem:ga92d644d34b59762d0b48f7784d3aed4b" id="r_ga92d644d34b59762d0b48f7784d3aed4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92d644d34b59762d0b48f7784d3aed4b">FSMC_BCR4_MUXEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1556380a7357a40ef14a0e064adb39ef">FSMC_BCR4_MUXEN_Msk</a></td></tr>
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<tr class="memitem:ga96c0fdb70786e0c784a5a4c002ca41db" id="r_ga96c0fdb70786e0c784a5a4c002ca41db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96c0fdb70786e0c784a5a4c002ca41db">FSMC_BCR4_MTYP_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga96c0fdb70786e0c784a5a4c002ca41db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f4900e19f018d5deee5bbbd8605ccc9" id="r_ga4f4900e19f018d5deee5bbbd8605ccc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f4900e19f018d5deee5bbbd8605ccc9">FSMC_BCR4_MTYP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96c0fdb70786e0c784a5a4c002ca41db">FSMC_BCR4_MTYP_Pos</a>)</td></tr>
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<tr class="separator:ga4f4900e19f018d5deee5bbbd8605ccc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f9bf2c236b772e76174aff4388a1b6f" id="r_ga1f9bf2c236b772e76174aff4388a1b6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f9bf2c236b772e76174aff4388a1b6f">FSMC_BCR4_MTYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f4900e19f018d5deee5bbbd8605ccc9">FSMC_BCR4_MTYP_Msk</a></td></tr>
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<tr class="separator:ga1f9bf2c236b772e76174aff4388a1b6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66d358ec27a34fe13131d852b950643e" id="r_ga66d358ec27a34fe13131d852b950643e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66d358ec27a34fe13131d852b950643e">FSMC_BCR4_MTYP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96c0fdb70786e0c784a5a4c002ca41db">FSMC_BCR4_MTYP_Pos</a>)</td></tr>
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<tr class="memitem:gaac5abffefdc124215182346aba701183" id="r_gaac5abffefdc124215182346aba701183"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac5abffefdc124215182346aba701183">FSMC_BCR4_MTYP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96c0fdb70786e0c784a5a4c002ca41db">FSMC_BCR4_MTYP_Pos</a>)</td></tr>
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<tr class="separator:gaac5abffefdc124215182346aba701183"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab06a48e2793af3cce3d0a32ee5622339" id="r_gab06a48e2793af3cce3d0a32ee5622339"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab06a48e2793af3cce3d0a32ee5622339">FSMC_BCR4_MWID_Pos</a>   (4U)</td></tr>
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<tr class="separator:gab06a48e2793af3cce3d0a32ee5622339"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad01b905b7a139494a1577694bb6401f" id="r_gaad01b905b7a139494a1577694bb6401f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad01b905b7a139494a1577694bb6401f">FSMC_BCR4_MWID_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab06a48e2793af3cce3d0a32ee5622339">FSMC_BCR4_MWID_Pos</a>)</td></tr>
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<tr class="separator:gaad01b905b7a139494a1577694bb6401f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c4ce32ca454c42344cfe73f71abd274" id="r_ga5c4ce32ca454c42344cfe73f71abd274"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c4ce32ca454c42344cfe73f71abd274">FSMC_BCR4_MWID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaad01b905b7a139494a1577694bb6401f">FSMC_BCR4_MWID_Msk</a></td></tr>
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<tr class="separator:ga5c4ce32ca454c42344cfe73f71abd274"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c8f397cfb1f07421abeaf3060f7a329" id="r_ga1c8f397cfb1f07421abeaf3060f7a329"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c8f397cfb1f07421abeaf3060f7a329">FSMC_BCR4_MWID_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab06a48e2793af3cce3d0a32ee5622339">FSMC_BCR4_MWID_Pos</a>)</td></tr>
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<tr class="separator:ga1c8f397cfb1f07421abeaf3060f7a329"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5cd3a31190eb0cea8a72b55d8369970" id="r_gaf5cd3a31190eb0cea8a72b55d8369970"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5cd3a31190eb0cea8a72b55d8369970">FSMC_BCR4_MWID_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab06a48e2793af3cce3d0a32ee5622339">FSMC_BCR4_MWID_Pos</a>)</td></tr>
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<tr class="separator:gaf5cd3a31190eb0cea8a72b55d8369970"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga576f29ec9b1d7afa35bcecd8b974d8af" id="r_ga576f29ec9b1d7afa35bcecd8b974d8af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga576f29ec9b1d7afa35bcecd8b974d8af">FSMC_BCR4_FACCEN_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga576f29ec9b1d7afa35bcecd8b974d8af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga887e51078b00ac24b3ac8a5ff1d2290c" id="r_ga887e51078b00ac24b3ac8a5ff1d2290c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga887e51078b00ac24b3ac8a5ff1d2290c">FSMC_BCR4_FACCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga576f29ec9b1d7afa35bcecd8b974d8af">FSMC_BCR4_FACCEN_Pos</a>)</td></tr>
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<tr class="separator:ga887e51078b00ac24b3ac8a5ff1d2290c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf769d7958a8c610ccca912600e61f30" id="r_gabf769d7958a8c610ccca912600e61f30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf769d7958a8c610ccca912600e61f30">FSMC_BCR4_FACCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga887e51078b00ac24b3ac8a5ff1d2290c">FSMC_BCR4_FACCEN_Msk</a></td></tr>
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<tr class="separator:gabf769d7958a8c610ccca912600e61f30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61065b18069c91ca4a92acba5d8e2815" id="r_ga61065b18069c91ca4a92acba5d8e2815"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61065b18069c91ca4a92acba5d8e2815">FSMC_BCR4_BURSTEN_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga61065b18069c91ca4a92acba5d8e2815"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0adae69dfd0ea81a4e50501b4e71dcf1" id="r_ga0adae69dfd0ea81a4e50501b4e71dcf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0adae69dfd0ea81a4e50501b4e71dcf1">FSMC_BCR4_BURSTEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61065b18069c91ca4a92acba5d8e2815">FSMC_BCR4_BURSTEN_Pos</a>)</td></tr>
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<tr class="separator:ga0adae69dfd0ea81a4e50501b4e71dcf1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c6ffdcee5dc3de1402bd8b644d6ecf4" id="r_ga2c6ffdcee5dc3de1402bd8b644d6ecf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c6ffdcee5dc3de1402bd8b644d6ecf4">FSMC_BCR4_BURSTEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0adae69dfd0ea81a4e50501b4e71dcf1">FSMC_BCR4_BURSTEN_Msk</a></td></tr>
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<tr class="separator:ga2c6ffdcee5dc3de1402bd8b644d6ecf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0716fa00c0b7d9e694f1e4faa3b463af" id="r_ga0716fa00c0b7d9e694f1e4faa3b463af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0716fa00c0b7d9e694f1e4faa3b463af">FSMC_BCR4_WAITPOL_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga0716fa00c0b7d9e694f1e4faa3b463af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf12e7172887f85904c50033b9d8b78fd" id="r_gaf12e7172887f85904c50033b9d8b78fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf12e7172887f85904c50033b9d8b78fd">FSMC_BCR4_WAITPOL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0716fa00c0b7d9e694f1e4faa3b463af">FSMC_BCR4_WAITPOL_Pos</a>)</td></tr>
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<tr class="separator:gaf12e7172887f85904c50033b9d8b78fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga485976f8857949064d060374031cad3d" id="r_ga485976f8857949064d060374031cad3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga485976f8857949064d060374031cad3d">FSMC_BCR4_WAITPOL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf12e7172887f85904c50033b9d8b78fd">FSMC_BCR4_WAITPOL_Msk</a></td></tr>
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<tr class="separator:ga485976f8857949064d060374031cad3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a74bbc78956ddc94627b5b987b05169" id="r_ga6a74bbc78956ddc94627b5b987b05169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a74bbc78956ddc94627b5b987b05169">FSMC_BCR4_WRAPMOD_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga6a74bbc78956ddc94627b5b987b05169"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6f39d62a63c9708594f0d9819d3ad2a" id="r_gad6f39d62a63c9708594f0d9819d3ad2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6f39d62a63c9708594f0d9819d3ad2a">FSMC_BCR4_WRAPMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a74bbc78956ddc94627b5b987b05169">FSMC_BCR4_WRAPMOD_Pos</a>)</td></tr>
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<tr class="separator:gad6f39d62a63c9708594f0d9819d3ad2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa35333cfffc35c7948ee0aa0e5672c3c" id="r_gaa35333cfffc35c7948ee0aa0e5672c3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa35333cfffc35c7948ee0aa0e5672c3c">FSMC_BCR4_WRAPMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad6f39d62a63c9708594f0d9819d3ad2a">FSMC_BCR4_WRAPMOD_Msk</a></td></tr>
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<tr class="separator:gaa35333cfffc35c7948ee0aa0e5672c3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23b0e2f296dd78ec57b8f166cc59bf6b" id="r_ga23b0e2f296dd78ec57b8f166cc59bf6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23b0e2f296dd78ec57b8f166cc59bf6b">FSMC_BCR4_WAITCFG_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga23b0e2f296dd78ec57b8f166cc59bf6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6fe8c8ee1b76354cdd74bb024e2b036d" id="r_ga6fe8c8ee1b76354cdd74bb024e2b036d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fe8c8ee1b76354cdd74bb024e2b036d">FSMC_BCR4_WAITCFG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga23b0e2f296dd78ec57b8f166cc59bf6b">FSMC_BCR4_WAITCFG_Pos</a>)</td></tr>
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<tr class="separator:ga6fe8c8ee1b76354cdd74bb024e2b036d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11c35ab0ee9ee23a5352218b4b84a258" id="r_ga11c35ab0ee9ee23a5352218b4b84a258"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11c35ab0ee9ee23a5352218b4b84a258">FSMC_BCR4_WAITCFG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6fe8c8ee1b76354cdd74bb024e2b036d">FSMC_BCR4_WAITCFG_Msk</a></td></tr>
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<tr class="separator:ga11c35ab0ee9ee23a5352218b4b84a258"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee04969322aa460220249296cbecbc07" id="r_gaee04969322aa460220249296cbecbc07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee04969322aa460220249296cbecbc07">FSMC_BCR4_WREN_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaee04969322aa460220249296cbecbc07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3879a08367749ad58d7f17708998f28" id="r_gad3879a08367749ad58d7f17708998f28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3879a08367749ad58d7f17708998f28">FSMC_BCR4_WREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee04969322aa460220249296cbecbc07">FSMC_BCR4_WREN_Pos</a>)</td></tr>
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<tr class="memitem:gadf2eef4eb8e6bb99cace5145b6ad09ee" id="r_gadf2eef4eb8e6bb99cace5145b6ad09ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf2eef4eb8e6bb99cace5145b6ad09ee">FSMC_BCR4_WREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad3879a08367749ad58d7f17708998f28">FSMC_BCR4_WREN_Msk</a></td></tr>
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<tr class="separator:gadf2eef4eb8e6bb99cace5145b6ad09ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab597ed53b04db4a4f13b57a727b5624c" id="r_gab597ed53b04db4a4f13b57a727b5624c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab597ed53b04db4a4f13b57a727b5624c">FSMC_BCR4_WAITEN_Pos</a>   (13U)</td></tr>
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<tr class="separator:gab597ed53b04db4a4f13b57a727b5624c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55ba3588b86b81122eb8da69f0593741" id="r_ga55ba3588b86b81122eb8da69f0593741"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55ba3588b86b81122eb8da69f0593741">FSMC_BCR4_WAITEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab597ed53b04db4a4f13b57a727b5624c">FSMC_BCR4_WAITEN_Pos</a>)</td></tr>
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<tr class="separator:ga55ba3588b86b81122eb8da69f0593741"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga458727d27c2bc7cede05f6537bfc1bd8" id="r_ga458727d27c2bc7cede05f6537bfc1bd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga458727d27c2bc7cede05f6537bfc1bd8">FSMC_BCR4_WAITEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga55ba3588b86b81122eb8da69f0593741">FSMC_BCR4_WAITEN_Msk</a></td></tr>
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<tr class="memitem:ga63db0c5c207a432ae87a5881b163f000" id="r_ga63db0c5c207a432ae87a5881b163f000"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63db0c5c207a432ae87a5881b163f000">FSMC_BCR4_EXTMOD_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gaf8d523e6b38ea3647b831b65a596faca" id="r_gaf8d523e6b38ea3647b831b65a596faca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8d523e6b38ea3647b831b65a596faca">FSMC_BCR4_EXTMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga63db0c5c207a432ae87a5881b163f000">FSMC_BCR4_EXTMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga6794966a05855913923294f5c2ab69ed" id="r_ga6794966a05855913923294f5c2ab69ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6794966a05855913923294f5c2ab69ed">FSMC_BCR4_EXTMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8d523e6b38ea3647b831b65a596faca">FSMC_BCR4_EXTMOD_Msk</a></td></tr>
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<tr class="memitem:gafdb1dd068a4d2b956aef4fb973342e53" id="r_gafdb1dd068a4d2b956aef4fb973342e53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdb1dd068a4d2b956aef4fb973342e53">FSMC_BCR4_ASYNCWAIT_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga486c5a22b57dba36a2010257c92514ca" id="r_ga486c5a22b57dba36a2010257c92514ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga486c5a22b57dba36a2010257c92514ca">FSMC_BCR4_ASYNCWAIT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafdb1dd068a4d2b956aef4fb973342e53">FSMC_BCR4_ASYNCWAIT_Pos</a>)</td></tr>
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<tr class="memitem:ga158eeaca2258bc25beae918d01e01dd8" id="r_ga158eeaca2258bc25beae918d01e01dd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga158eeaca2258bc25beae918d01e01dd8">FSMC_BCR4_ASYNCWAIT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga486c5a22b57dba36a2010257c92514ca">FSMC_BCR4_ASYNCWAIT_Msk</a></td></tr>
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<tr class="memitem:ga6efaac5bbbd151e85dbb22176550eb75" id="r_ga6efaac5bbbd151e85dbb22176550eb75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6efaac5bbbd151e85dbb22176550eb75">FSMC_BCR4_CPSIZE_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga6efaac5bbbd151e85dbb22176550eb75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a79495e98a82e6895d4b51c66b9af59" id="r_ga3a79495e98a82e6895d4b51c66b9af59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a79495e98a82e6895d4b51c66b9af59">FSMC_BCR4_CPSIZE_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6efaac5bbbd151e85dbb22176550eb75">FSMC_BCR4_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga3a79495e98a82e6895d4b51c66b9af59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad40c68c7a7806c531d78af3ba712f0cd" id="r_gad40c68c7a7806c531d78af3ba712f0cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad40c68c7a7806c531d78af3ba712f0cd">FSMC_BCR4_CPSIZE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a79495e98a82e6895d4b51c66b9af59">FSMC_BCR4_CPSIZE_Msk</a></td></tr>
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<tr class="separator:gad40c68c7a7806c531d78af3ba712f0cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga801fee8ca2fcd5c881f95fa7eb319160" id="r_ga801fee8ca2fcd5c881f95fa7eb319160"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga801fee8ca2fcd5c881f95fa7eb319160">FSMC_BCR4_CPSIZE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6efaac5bbbd151e85dbb22176550eb75">FSMC_BCR4_CPSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga801fee8ca2fcd5c881f95fa7eb319160"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7615f0150d36affdecdb05bdff084020" id="r_ga7615f0150d36affdecdb05bdff084020"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7615f0150d36affdecdb05bdff084020">FSMC_BCR4_CPSIZE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6efaac5bbbd151e85dbb22176550eb75">FSMC_BCR4_CPSIZE_Pos</a>)</td></tr>
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<tr class="memitem:ga59bdb0695f948fa7369451fc38380c12" id="r_ga59bdb0695f948fa7369451fc38380c12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59bdb0695f948fa7369451fc38380c12">FSMC_BCR4_CPSIZE_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6efaac5bbbd151e85dbb22176550eb75">FSMC_BCR4_CPSIZE_Pos</a>)</td></tr>
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<tr class="memitem:gad81ccd2059e86d3108e3c71e5075f936" id="r_gad81ccd2059e86d3108e3c71e5075f936"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad81ccd2059e86d3108e3c71e5075f936">FSMC_BCR4_CBURSTRW_Pos</a>   (19U)</td></tr>
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<tr class="separator:gad81ccd2059e86d3108e3c71e5075f936"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e8b3d5023ae64207d965b9d26816b72" id="r_ga0e8b3d5023ae64207d965b9d26816b72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e8b3d5023ae64207d965b9d26816b72">FSMC_BCR4_CBURSTRW_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad81ccd2059e86d3108e3c71e5075f936">FSMC_BCR4_CBURSTRW_Pos</a>)</td></tr>
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<tr class="separator:ga0e8b3d5023ae64207d965b9d26816b72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19293300b8230e38afa1c16c526b3f29" id="r_ga19293300b8230e38afa1c16c526b3f29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19293300b8230e38afa1c16c526b3f29">FSMC_BCR4_CBURSTRW</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e8b3d5023ae64207d965b9d26816b72">FSMC_BCR4_CBURSTRW_Msk</a></td></tr>
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<tr class="separator:ga19293300b8230e38afa1c16c526b3f29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2b6109a964212ec400829faa37e113a" id="r_gad2b6109a964212ec400829faa37e113a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2b6109a964212ec400829faa37e113a">FSMC_BTR1_ADDSET_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad2b6109a964212ec400829faa37e113a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b91cf869f5ab06c40ad7620ae59ffa8" id="r_ga2b91cf869f5ab06c40ad7620ae59ffa8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b91cf869f5ab06c40ad7620ae59ffa8">FSMC_BTR1_ADDSET_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2b6109a964212ec400829faa37e113a">FSMC_BTR1_ADDSET_Pos</a>)</td></tr>
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<tr class="separator:ga2b91cf869f5ab06c40ad7620ae59ffa8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab457e5d3a33d80db3ad070b1cf57669a" id="r_gab457e5d3a33d80db3ad070b1cf57669a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab457e5d3a33d80db3ad070b1cf57669a">FSMC_BTR1_ADDSET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b91cf869f5ab06c40ad7620ae59ffa8">FSMC_BTR1_ADDSET_Msk</a></td></tr>
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<tr class="separator:gab457e5d3a33d80db3ad070b1cf57669a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae29ca17c63df62cc12c06e6cfa3429e3" id="r_gae29ca17c63df62cc12c06e6cfa3429e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae29ca17c63df62cc12c06e6cfa3429e3">FSMC_BTR1_ADDSET_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2b6109a964212ec400829faa37e113a">FSMC_BTR1_ADDSET_Pos</a>)</td></tr>
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<tr class="separator:gae29ca17c63df62cc12c06e6cfa3429e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefb98ce348ba665f122e44ddc0390b45" id="r_gaefb98ce348ba665f122e44ddc0390b45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefb98ce348ba665f122e44ddc0390b45">FSMC_BTR1_ADDSET_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2b6109a964212ec400829faa37e113a">FSMC_BTR1_ADDSET_Pos</a>)</td></tr>
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<tr class="separator:gaefb98ce348ba665f122e44ddc0390b45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5e5c5b00c91aca1cc266622d3f30bf0" id="r_gaa5e5c5b00c91aca1cc266622d3f30bf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5e5c5b00c91aca1cc266622d3f30bf0">FSMC_BTR1_ADDSET_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2b6109a964212ec400829faa37e113a">FSMC_BTR1_ADDSET_Pos</a>)</td></tr>
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<tr class="separator:gaa5e5c5b00c91aca1cc266622d3f30bf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f0105afe671cd62730cf879072c80f3" id="r_ga2f0105afe671cd62730cf879072c80f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f0105afe671cd62730cf879072c80f3">FSMC_BTR1_ADDSET_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2b6109a964212ec400829faa37e113a">FSMC_BTR1_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gab8d311b7f571c7f1b55638b62da5a5a1" id="r_gab8d311b7f571c7f1b55638b62da5a5a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8d311b7f571c7f1b55638b62da5a5a1">FSMC_BTR1_ADDHLD_Pos</a>   (4U)</td></tr>
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<tr class="separator:gab8d311b7f571c7f1b55638b62da5a5a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d1abafea7ca6c3eecc720b4e9e15b3e" id="r_ga1d1abafea7ca6c3eecc720b4e9e15b3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d1abafea7ca6c3eecc720b4e9e15b3e">FSMC_BTR1_ADDHLD_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8d311b7f571c7f1b55638b62da5a5a1">FSMC_BTR1_ADDHLD_Pos</a>)</td></tr>
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<tr class="separator:ga1d1abafea7ca6c3eecc720b4e9e15b3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc4a3860c48a62ff0290622e1937072d" id="r_gadc4a3860c48a62ff0290622e1937072d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc4a3860c48a62ff0290622e1937072d">FSMC_BTR1_ADDHLD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d1abafea7ca6c3eecc720b4e9e15b3e">FSMC_BTR1_ADDHLD_Msk</a></td></tr>
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<tr class="separator:gadc4a3860c48a62ff0290622e1937072d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga222a16d5a1a8deebaf39a96d94d3c3f0" id="r_ga222a16d5a1a8deebaf39a96d94d3c3f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga222a16d5a1a8deebaf39a96d94d3c3f0">FSMC_BTR1_ADDHLD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8d311b7f571c7f1b55638b62da5a5a1">FSMC_BTR1_ADDHLD_Pos</a>)</td></tr>
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<tr class="separator:ga222a16d5a1a8deebaf39a96d94d3c3f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ad1f9164644c4ff4c6ae5a655478abc" id="r_ga5ad1f9164644c4ff4c6ae5a655478abc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ad1f9164644c4ff4c6ae5a655478abc">FSMC_BTR1_ADDHLD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8d311b7f571c7f1b55638b62da5a5a1">FSMC_BTR1_ADDHLD_Pos</a>)</td></tr>
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<tr class="separator:ga5ad1f9164644c4ff4c6ae5a655478abc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f9d68df0fd84b77342a565e9faad929" id="r_ga3f9d68df0fd84b77342a565e9faad929"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f9d68df0fd84b77342a565e9faad929">FSMC_BTR1_ADDHLD_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8d311b7f571c7f1b55638b62da5a5a1">FSMC_BTR1_ADDHLD_Pos</a>)</td></tr>
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<tr class="separator:ga3f9d68df0fd84b77342a565e9faad929"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e88e45163e76f529b5a94937526f45c" id="r_ga6e88e45163e76f529b5a94937526f45c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e88e45163e76f529b5a94937526f45c">FSMC_BTR1_ADDHLD_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8d311b7f571c7f1b55638b62da5a5a1">FSMC_BTR1_ADDHLD_Pos</a>)</td></tr>
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<tr class="separator:ga6e88e45163e76f529b5a94937526f45c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c6cf527aad7fcdb2e57ef4483cd4e91" id="r_ga5c6cf527aad7fcdb2e57ef4483cd4e91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91">FSMC_BTR1_DATAST_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga5c6cf527aad7fcdb2e57ef4483cd4e91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0a503b09190898423d53534300bf397" id="r_gae0a503b09190898423d53534300bf397"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0a503b09190898423d53534300bf397">FSMC_BTR1_DATAST_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91">FSMC_BTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gae39175370a991b500962fd084230e389" id="r_gae39175370a991b500962fd084230e389"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae39175370a991b500962fd084230e389">FSMC_BTR1_DATAST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae0a503b09190898423d53534300bf397">FSMC_BTR1_DATAST_Msk</a></td></tr>
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<tr class="memitem:ga4488a428f33d96263a00a30af42b849b" id="r_ga4488a428f33d96263a00a30af42b849b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4488a428f33d96263a00a30af42b849b">FSMC_BTR1_DATAST_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91">FSMC_BTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gad53bd6a1decfafdb420a37453b3b5545" id="r_gad53bd6a1decfafdb420a37453b3b5545"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad53bd6a1decfafdb420a37453b3b5545">FSMC_BTR1_DATAST_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91">FSMC_BTR1_DATAST_Pos</a>)</td></tr>
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<tr class="separator:gad53bd6a1decfafdb420a37453b3b5545"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacce8f6cf5a9ba24943b3e762bde00aee" id="r_gacce8f6cf5a9ba24943b3e762bde00aee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacce8f6cf5a9ba24943b3e762bde00aee">FSMC_BTR1_DATAST_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91">FSMC_BTR1_DATAST_Pos</a>)</td></tr>
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<tr class="separator:gacce8f6cf5a9ba24943b3e762bde00aee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99638cc2cbe0dead029c201e5f30c3a8" id="r_ga99638cc2cbe0dead029c201e5f30c3a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99638cc2cbe0dead029c201e5f30c3a8">FSMC_BTR1_DATAST_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91">FSMC_BTR1_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga99638cc2cbe0dead029c201e5f30c3a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46c64dd27460218f4398f84f8a1eb050" id="r_ga46c64dd27460218f4398f84f8a1eb050"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46c64dd27460218f4398f84f8a1eb050">FSMC_BTR1_DATAST_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91">FSMC_BTR1_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga46c64dd27460218f4398f84f8a1eb050"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d19491b3e729c6aac0fea41cc62b695" id="r_ga1d19491b3e729c6aac0fea41cc62b695"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d19491b3e729c6aac0fea41cc62b695">FSMC_BTR1_DATAST_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91">FSMC_BTR1_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga1d19491b3e729c6aac0fea41cc62b695"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50c28cb325d28369d1a9ef764c63887b" id="r_ga50c28cb325d28369d1a9ef764c63887b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50c28cb325d28369d1a9ef764c63887b">FSMC_BTR1_DATAST_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91">FSMC_BTR1_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga50c28cb325d28369d1a9ef764c63887b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f54453aa732f52cbb5a1562d2eddd23" id="r_ga7f54453aa732f52cbb5a1562d2eddd23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f54453aa732f52cbb5a1562d2eddd23">FSMC_BTR1_DATAST_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91">FSMC_BTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga164a173346248449423d03e8d1d40a31" id="r_ga164a173346248449423d03e8d1d40a31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga164a173346248449423d03e8d1d40a31">FSMC_BTR1_BUSTURN_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gaedd0e3c6b2b476a6e6c0578a2bdf3d5d" id="r_gaedd0e3c6b2b476a6e6c0578a2bdf3d5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedd0e3c6b2b476a6e6c0578a2bdf3d5d">FSMC_BTR1_BUSTURN_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga164a173346248449423d03e8d1d40a31">FSMC_BTR1_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga7ec9346bbaf845f1dffe33c4a625c0ac" id="r_ga7ec9346bbaf845f1dffe33c4a625c0ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ec9346bbaf845f1dffe33c4a625c0ac">FSMC_BTR1_BUSTURN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaedd0e3c6b2b476a6e6c0578a2bdf3d5d">FSMC_BTR1_BUSTURN_Msk</a></td></tr>
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<tr class="separator:ga7ec9346bbaf845f1dffe33c4a625c0ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c1578a85c4f2cef9e034c7b5da6d454" id="r_ga6c1578a85c4f2cef9e034c7b5da6d454"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c1578a85c4f2cef9e034c7b5da6d454">FSMC_BTR1_BUSTURN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga164a173346248449423d03e8d1d40a31">FSMC_BTR1_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gaf873cbfe4827496215eb08bb33ae4784" id="r_gaf873cbfe4827496215eb08bb33ae4784"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf873cbfe4827496215eb08bb33ae4784">FSMC_BTR1_BUSTURN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga164a173346248449423d03e8d1d40a31">FSMC_BTR1_BUSTURN_Pos</a>)</td></tr>
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<tr class="separator:gaf873cbfe4827496215eb08bb33ae4784"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad768d3ff0a5159e552663c9489b977f6" id="r_gad768d3ff0a5159e552663c9489b977f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad768d3ff0a5159e552663c9489b977f6">FSMC_BTR1_BUSTURN_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga164a173346248449423d03e8d1d40a31">FSMC_BTR1_BUSTURN_Pos</a>)</td></tr>
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<tr class="separator:gad768d3ff0a5159e552663c9489b977f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3ecfd25fb64efb3745ee96b2877a017" id="r_gaf3ecfd25fb64efb3745ee96b2877a017"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3ecfd25fb64efb3745ee96b2877a017">FSMC_BTR1_BUSTURN_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga164a173346248449423d03e8d1d40a31">FSMC_BTR1_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga514bdebcbaf4a3e4d0ede4fef6bb0dd7" id="r_ga514bdebcbaf4a3e4d0ede4fef6bb0dd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga514bdebcbaf4a3e4d0ede4fef6bb0dd7">FSMC_BTR1_CLKDIV_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga514bdebcbaf4a3e4d0ede4fef6bb0dd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c720b329720574b2c8d30c072f78716" id="r_ga7c720b329720574b2c8d30c072f78716"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c720b329720574b2c8d30c072f78716">FSMC_BTR1_CLKDIV_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga514bdebcbaf4a3e4d0ede4fef6bb0dd7">FSMC_BTR1_CLKDIV_Pos</a>)</td></tr>
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<tr class="separator:ga7c720b329720574b2c8d30c072f78716"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7c4dbd43df84559e30a9c332b265ad5" id="r_gac7c4dbd43df84559e30a9c332b265ad5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7c4dbd43df84559e30a9c332b265ad5">FSMC_BTR1_CLKDIV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c720b329720574b2c8d30c072f78716">FSMC_BTR1_CLKDIV_Msk</a></td></tr>
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<tr class="memitem:gabe9c9e09de00afad666ace28c608032f" id="r_gabe9c9e09de00afad666ace28c608032f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe9c9e09de00afad666ace28c608032f">FSMC_BTR1_CLKDIV_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga514bdebcbaf4a3e4d0ede4fef6bb0dd7">FSMC_BTR1_CLKDIV_Pos</a>)</td></tr>
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<tr class="separator:gabe9c9e09de00afad666ace28c608032f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafffebd7a0cf6e6d80b65804c2c50ce62" id="r_gafffebd7a0cf6e6d80b65804c2c50ce62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafffebd7a0cf6e6d80b65804c2c50ce62">FSMC_BTR1_CLKDIV_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga514bdebcbaf4a3e4d0ede4fef6bb0dd7">FSMC_BTR1_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga43afa754305cc1a7ff3075cdd4309990" id="r_ga43afa754305cc1a7ff3075cdd4309990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43afa754305cc1a7ff3075cdd4309990">FSMC_BTR1_CLKDIV_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga514bdebcbaf4a3e4d0ede4fef6bb0dd7">FSMC_BTR1_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga68a146aec5d723a84945ae6da6c0692f" id="r_ga68a146aec5d723a84945ae6da6c0692f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68a146aec5d723a84945ae6da6c0692f">FSMC_BTR1_CLKDIV_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga514bdebcbaf4a3e4d0ede4fef6bb0dd7">FSMC_BTR1_CLKDIV_Pos</a>)</td></tr>
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<tr class="separator:ga68a146aec5d723a84945ae6da6c0692f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bc0aee3036c6ddba4a1e66b92b0913c" id="r_ga1bc0aee3036c6ddba4a1e66b92b0913c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc0aee3036c6ddba4a1e66b92b0913c">FSMC_BTR1_DATLAT_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga19c7f2d933e94d7f60c22027558f2a23" id="r_ga19c7f2d933e94d7f60c22027558f2a23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19c7f2d933e94d7f60c22027558f2a23">FSMC_BTR1_DATLAT_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc0aee3036c6ddba4a1e66b92b0913c">FSMC_BTR1_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:ga4ef6dcccdb11a1b094966be0c019124b" id="r_ga4ef6dcccdb11a1b094966be0c019124b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ef6dcccdb11a1b094966be0c019124b">FSMC_BTR1_DATLAT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga19c7f2d933e94d7f60c22027558f2a23">FSMC_BTR1_DATLAT_Msk</a></td></tr>
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<tr class="separator:ga4ef6dcccdb11a1b094966be0c019124b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2d832593697ba108d99a97e4fdfd159" id="r_gae2d832593697ba108d99a97e4fdfd159"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2d832593697ba108d99a97e4fdfd159">FSMC_BTR1_DATLAT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc0aee3036c6ddba4a1e66b92b0913c">FSMC_BTR1_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:ga2a7e4efc546c1c9d16c750a4542e1c55" id="r_ga2a7e4efc546c1c9d16c750a4542e1c55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a7e4efc546c1c9d16c750a4542e1c55">FSMC_BTR1_DATLAT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc0aee3036c6ddba4a1e66b92b0913c">FSMC_BTR1_DATLAT_Pos</a>)</td></tr>
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<tr class="separator:ga2a7e4efc546c1c9d16c750a4542e1c55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22e7d41e0f94ab896c6eea199eb0aef1" id="r_ga22e7d41e0f94ab896c6eea199eb0aef1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22e7d41e0f94ab896c6eea199eb0aef1">FSMC_BTR1_DATLAT_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc0aee3036c6ddba4a1e66b92b0913c">FSMC_BTR1_DATLAT_Pos</a>)</td></tr>
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<tr class="separator:ga22e7d41e0f94ab896c6eea199eb0aef1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b42f22fc488e0ed0d06832118773123" id="r_ga8b42f22fc488e0ed0d06832118773123"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b42f22fc488e0ed0d06832118773123">FSMC_BTR1_DATLAT_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc0aee3036c6ddba4a1e66b92b0913c">FSMC_BTR1_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:gabfe73fd49dee3d6123e7be78f49e8dce" id="r_gabfe73fd49dee3d6123e7be78f49e8dce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfe73fd49dee3d6123e7be78f49e8dce">FSMC_BTR1_ACCMOD_Pos</a>   (28U)</td></tr>
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<tr class="memitem:ga97f35ab9565eeb82324ab5015237cdbd" id="r_ga97f35ab9565eeb82324ab5015237cdbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97f35ab9565eeb82324ab5015237cdbd">FSMC_BTR1_ACCMOD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabfe73fd49dee3d6123e7be78f49e8dce">FSMC_BTR1_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga027548b6b5971a2c56558932c956fa4c" id="r_ga027548b6b5971a2c56558932c956fa4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga027548b6b5971a2c56558932c956fa4c">FSMC_BTR1_ACCMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97f35ab9565eeb82324ab5015237cdbd">FSMC_BTR1_ACCMOD_Msk</a></td></tr>
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<tr class="memitem:gaf77aa4936dc4f35d1b426d147c643c80" id="r_gaf77aa4936dc4f35d1b426d147c643c80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf77aa4936dc4f35d1b426d147c643c80">FSMC_BTR1_ACCMOD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabfe73fd49dee3d6123e7be78f49e8dce">FSMC_BTR1_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga7b336cf3ae23cfda19895927b63af558" id="r_ga7b336cf3ae23cfda19895927b63af558"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b336cf3ae23cfda19895927b63af558">FSMC_BTR1_ACCMOD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabfe73fd49dee3d6123e7be78f49e8dce">FSMC_BTR1_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga58b9a54aabd6cc507c6ab1b5fb134727" id="r_ga58b9a54aabd6cc507c6ab1b5fb134727"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58b9a54aabd6cc507c6ab1b5fb134727">FSMC_BTR2_ADDSET_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga58b9a54aabd6cc507c6ab1b5fb134727"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga903bf76eee82e88b1cefc9d1ed1aa4c7" id="r_ga903bf76eee82e88b1cefc9d1ed1aa4c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga903bf76eee82e88b1cefc9d1ed1aa4c7">FSMC_BTR2_ADDSET_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58b9a54aabd6cc507c6ab1b5fb134727">FSMC_BTR2_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga23697810b99730ddf52834a5066c1ba5" id="r_ga23697810b99730ddf52834a5066c1ba5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23697810b99730ddf52834a5066c1ba5">FSMC_BTR2_ADDSET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga903bf76eee82e88b1cefc9d1ed1aa4c7">FSMC_BTR2_ADDSET_Msk</a></td></tr>
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<tr class="memitem:ga827398dc098f2d08bb77a04b2e7d6ba3" id="r_ga827398dc098f2d08bb77a04b2e7d6ba3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga827398dc098f2d08bb77a04b2e7d6ba3">FSMC_BTR2_ADDSET_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58b9a54aabd6cc507c6ab1b5fb134727">FSMC_BTR2_ADDSET_Pos</a>)</td></tr>
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<tr class="separator:ga827398dc098f2d08bb77a04b2e7d6ba3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b40f47f2db0db78de6fe2df58b5d591" id="r_ga1b40f47f2db0db78de6fe2df58b5d591"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b40f47f2db0db78de6fe2df58b5d591">FSMC_BTR2_ADDSET_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58b9a54aabd6cc507c6ab1b5fb134727">FSMC_BTR2_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga558185a28aeedbb098890348a041a74d" id="r_ga558185a28aeedbb098890348a041a74d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga558185a28aeedbb098890348a041a74d">FSMC_BTR2_ADDSET_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58b9a54aabd6cc507c6ab1b5fb134727">FSMC_BTR2_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gadbd4d42459a990825b61962d9118cd7b" id="r_gadbd4d42459a990825b61962d9118cd7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbd4d42459a990825b61962d9118cd7b">FSMC_BTR2_ADDSET_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58b9a54aabd6cc507c6ab1b5fb134727">FSMC_BTR2_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga2be5c64e803c9fe4378275e2acd1b095" id="r_ga2be5c64e803c9fe4378275e2acd1b095"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2be5c64e803c9fe4378275e2acd1b095">FSMC_BTR2_ADDHLD_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga2be5c64e803c9fe4378275e2acd1b095"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe23e10bb28cb59dced9d9db5a4106db" id="r_gabe23e10bb28cb59dced9d9db5a4106db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe23e10bb28cb59dced9d9db5a4106db">FSMC_BTR2_ADDHLD_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2be5c64e803c9fe4378275e2acd1b095">FSMC_BTR2_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gac37c974d0260ba1dbd1acaf6fceb425c" id="r_gac37c974d0260ba1dbd1acaf6fceb425c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac37c974d0260ba1dbd1acaf6fceb425c">FSMC_BTR2_ADDHLD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe23e10bb28cb59dced9d9db5a4106db">FSMC_BTR2_ADDHLD_Msk</a></td></tr>
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<tr class="separator:gac37c974d0260ba1dbd1acaf6fceb425c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabbf56fc3a549d1e68d56e1587123bd27" id="r_gabbf56fc3a549d1e68d56e1587123bd27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbf56fc3a549d1e68d56e1587123bd27">FSMC_BTR2_ADDHLD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2be5c64e803c9fe4378275e2acd1b095">FSMC_BTR2_ADDHLD_Pos</a>)</td></tr>
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<tr class="separator:gabbf56fc3a549d1e68d56e1587123bd27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b7d19f02444ce8b3286d44258c6caef" id="r_ga0b7d19f02444ce8b3286d44258c6caef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b7d19f02444ce8b3286d44258c6caef">FSMC_BTR2_ADDHLD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2be5c64e803c9fe4378275e2acd1b095">FSMC_BTR2_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga7e9433e15e301d5d3f0dd6b73c9db2f7" id="r_ga7e9433e15e301d5d3f0dd6b73c9db2f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e9433e15e301d5d3f0dd6b73c9db2f7">FSMC_BTR2_ADDHLD_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2be5c64e803c9fe4378275e2acd1b095">FSMC_BTR2_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gacc538e46145ed4947194f3ad63e211b7" id="r_gacc538e46145ed4947194f3ad63e211b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc538e46145ed4947194f3ad63e211b7">FSMC_BTR2_ADDHLD_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2be5c64e803c9fe4378275e2acd1b095">FSMC_BTR2_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga2b6e90fc9b165365c147924675deb339" id="r_ga2b6e90fc9b165365c147924675deb339"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339">FSMC_BTR2_DATAST_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga35f2c0de6b8e42c44f1006a29507ce07" id="r_ga35f2c0de6b8e42c44f1006a29507ce07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35f2c0de6b8e42c44f1006a29507ce07">FSMC_BTR2_DATAST_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339">FSMC_BTR2_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga35f2c0de6b8e42c44f1006a29507ce07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe1d3fe096ea53ea073b78bd6ddbff58" id="r_gabe1d3fe096ea53ea073b78bd6ddbff58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe1d3fe096ea53ea073b78bd6ddbff58">FSMC_BTR2_DATAST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga35f2c0de6b8e42c44f1006a29507ce07">FSMC_BTR2_DATAST_Msk</a></td></tr>
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<tr class="memitem:gaa066dab45a22ebd3a7102b92dcd251bd" id="r_gaa066dab45a22ebd3a7102b92dcd251bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa066dab45a22ebd3a7102b92dcd251bd">FSMC_BTR2_DATAST_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339">FSMC_BTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga68c15ca5fdd13efb5499f0e86bd5bc88" id="r_ga68c15ca5fdd13efb5499f0e86bd5bc88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68c15ca5fdd13efb5499f0e86bd5bc88">FSMC_BTR2_DATAST_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339">FSMC_BTR2_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga68c15ca5fdd13efb5499f0e86bd5bc88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36cfe553d431ca6976f0d36c73045836" id="r_ga36cfe553d431ca6976f0d36c73045836"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36cfe553d431ca6976f0d36c73045836">FSMC_BTR2_DATAST_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339">FSMC_BTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga874499b29d2b72a75265f16a2d8ed834" id="r_ga874499b29d2b72a75265f16a2d8ed834"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga874499b29d2b72a75265f16a2d8ed834">FSMC_BTR2_DATAST_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339">FSMC_BTR2_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga874499b29d2b72a75265f16a2d8ed834"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4856fb97d7d04d612f24d7267e6c9b76" id="r_ga4856fb97d7d04d612f24d7267e6c9b76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4856fb97d7d04d612f24d7267e6c9b76">FSMC_BTR2_DATAST_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339">FSMC_BTR2_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga4856fb97d7d04d612f24d7267e6c9b76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb50ada649984a8bde5535cc3163344c" id="r_gacb50ada649984a8bde5535cc3163344c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb50ada649984a8bde5535cc3163344c">FSMC_BTR2_DATAST_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339">FSMC_BTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gaac4784549001168b5ab21a93852100d0" id="r_gaac4784549001168b5ab21a93852100d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac4784549001168b5ab21a93852100d0">FSMC_BTR2_DATAST_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339">FSMC_BTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga4bdd6994cb33a10447cbce5c563746da" id="r_ga4bdd6994cb33a10447cbce5c563746da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bdd6994cb33a10447cbce5c563746da">FSMC_BTR2_DATAST_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339">FSMC_BTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gae4f38b835e2730a7d9e817474b4a304c" id="r_gae4f38b835e2730a7d9e817474b4a304c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4f38b835e2730a7d9e817474b4a304c">FSMC_BTR2_BUSTURN_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga92af3fcfa317680d6fc598faa951d8e9" id="r_ga92af3fcfa317680d6fc598faa951d8e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92af3fcfa317680d6fc598faa951d8e9">FSMC_BTR2_BUSTURN_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4f38b835e2730a7d9e817474b4a304c">FSMC_BTR2_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga5ae7c94522af51d2f96a0fa715dfa9b0" id="r_ga5ae7c94522af51d2f96a0fa715dfa9b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ae7c94522af51d2f96a0fa715dfa9b0">FSMC_BTR2_BUSTURN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga92af3fcfa317680d6fc598faa951d8e9">FSMC_BTR2_BUSTURN_Msk</a></td></tr>
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<tr class="memitem:ga2617a99e5eab8b31ff168557f93852a3" id="r_ga2617a99e5eab8b31ff168557f93852a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2617a99e5eab8b31ff168557f93852a3">FSMC_BTR2_BUSTURN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4f38b835e2730a7d9e817474b4a304c">FSMC_BTR2_BUSTURN_Pos</a>)</td></tr>
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<tr class="separator:ga2617a99e5eab8b31ff168557f93852a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83871fa5cde9d72ec840d29d43aa2e57" id="r_ga83871fa5cde9d72ec840d29d43aa2e57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83871fa5cde9d72ec840d29d43aa2e57">FSMC_BTR2_BUSTURN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4f38b835e2730a7d9e817474b4a304c">FSMC_BTR2_BUSTURN_Pos</a>)</td></tr>
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<tr class="separator:ga83871fa5cde9d72ec840d29d43aa2e57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacada2902f8612df1e5ac6e224bcf8d3c" id="r_gacada2902f8612df1e5ac6e224bcf8d3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacada2902f8612df1e5ac6e224bcf8d3c">FSMC_BTR2_BUSTURN_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4f38b835e2730a7d9e817474b4a304c">FSMC_BTR2_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga66ad543195f36fdb3efdf7550381f982" id="r_ga66ad543195f36fdb3efdf7550381f982"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66ad543195f36fdb3efdf7550381f982">FSMC_BTR2_BUSTURN_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4f38b835e2730a7d9e817474b4a304c">FSMC_BTR2_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga3f1719a782602f2ad5737abd57bc866a" id="r_ga3f1719a782602f2ad5737abd57bc866a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1719a782602f2ad5737abd57bc866a">FSMC_BTR2_CLKDIV_Pos</a>   (20U)</td></tr>
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<tr class="memitem:gafe9c74d5bceaaa34ce11040cff130c7c" id="r_gafe9c74d5bceaaa34ce11040cff130c7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe9c74d5bceaaa34ce11040cff130c7c">FSMC_BTR2_CLKDIV_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1719a782602f2ad5737abd57bc866a">FSMC_BTR2_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga37fdb25c494cf314cb680f84c5e0a503" id="r_ga37fdb25c494cf314cb680f84c5e0a503"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37fdb25c494cf314cb680f84c5e0a503">FSMC_BTR2_CLKDIV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafe9c74d5bceaaa34ce11040cff130c7c">FSMC_BTR2_CLKDIV_Msk</a></td></tr>
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<tr class="memitem:ga1ac8729c8ac330f6ade93a6a15a4ba70" id="r_ga1ac8729c8ac330f6ade93a6a15a4ba70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ac8729c8ac330f6ade93a6a15a4ba70">FSMC_BTR2_CLKDIV_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1719a782602f2ad5737abd57bc866a">FSMC_BTR2_CLKDIV_Pos</a>)</td></tr>
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<tr class="separator:ga1ac8729c8ac330f6ade93a6a15a4ba70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31920e8bf2d83ad3c2849f8e942bb6e4" id="r_ga31920e8bf2d83ad3c2849f8e942bb6e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31920e8bf2d83ad3c2849f8e942bb6e4">FSMC_BTR2_CLKDIV_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1719a782602f2ad5737abd57bc866a">FSMC_BTR2_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:gaf5ba3172687049c687e3a38ec08d6c5a" id="r_gaf5ba3172687049c687e3a38ec08d6c5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5ba3172687049c687e3a38ec08d6c5a">FSMC_BTR2_CLKDIV_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1719a782602f2ad5737abd57bc866a">FSMC_BTR2_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga453c2a90dc3340596c9d34672cede6a0" id="r_ga453c2a90dc3340596c9d34672cede6a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga453c2a90dc3340596c9d34672cede6a0">FSMC_BTR2_CLKDIV_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1719a782602f2ad5737abd57bc866a">FSMC_BTR2_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga3766782905697c6b350ed00bc873baa9" id="r_ga3766782905697c6b350ed00bc873baa9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3766782905697c6b350ed00bc873baa9">FSMC_BTR2_DATLAT_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga3518166716c8654e8c0ad881bf0d2c66" id="r_ga3518166716c8654e8c0ad881bf0d2c66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3518166716c8654e8c0ad881bf0d2c66">FSMC_BTR2_DATLAT_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3766782905697c6b350ed00bc873baa9">FSMC_BTR2_DATLAT_Pos</a>)</td></tr>
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<tr class="separator:ga3518166716c8654e8c0ad881bf0d2c66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3247db1653b31df0c34ab7898400bb5" id="r_gae3247db1653b31df0c34ab7898400bb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3247db1653b31df0c34ab7898400bb5">FSMC_BTR2_DATLAT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3518166716c8654e8c0ad881bf0d2c66">FSMC_BTR2_DATLAT_Msk</a></td></tr>
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<tr class="memitem:ga0510047c932d2833f6cbe0a4a5d7b9b5" id="r_ga0510047c932d2833f6cbe0a4a5d7b9b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0510047c932d2833f6cbe0a4a5d7b9b5">FSMC_BTR2_DATLAT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3766782905697c6b350ed00bc873baa9">FSMC_BTR2_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:ga4e1852b706b3c719c0eab8ef863b39e0" id="r_ga4e1852b706b3c719c0eab8ef863b39e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e1852b706b3c719c0eab8ef863b39e0">FSMC_BTR2_DATLAT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3766782905697c6b350ed00bc873baa9">FSMC_BTR2_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:ga7ace24f50d1c51c978af55d47c13c0e9" id="r_ga7ace24f50d1c51c978af55d47c13c0e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ace24f50d1c51c978af55d47c13c0e9">FSMC_BTR2_DATLAT_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3766782905697c6b350ed00bc873baa9">FSMC_BTR2_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:ga99389b63c4dee3c54aa1de36a4119add" id="r_ga99389b63c4dee3c54aa1de36a4119add"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99389b63c4dee3c54aa1de36a4119add">FSMC_BTR2_DATLAT_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3766782905697c6b350ed00bc873baa9">FSMC_BTR2_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:gad9cba11e01cd8e90b1e56a3d52c44025" id="r_gad9cba11e01cd8e90b1e56a3d52c44025"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9cba11e01cd8e90b1e56a3d52c44025">FSMC_BTR2_ACCMOD_Pos</a>   (28U)</td></tr>
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<tr class="separator:gad9cba11e01cd8e90b1e56a3d52c44025"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad11258e9138b98bf6387167f0a2645f9" id="r_gad11258e9138b98bf6387167f0a2645f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad11258e9138b98bf6387167f0a2645f9">FSMC_BTR2_ACCMOD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9cba11e01cd8e90b1e56a3d52c44025">FSMC_BTR2_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga07b93600977cde6e31a9464f87606043" id="r_ga07b93600977cde6e31a9464f87606043"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07b93600977cde6e31a9464f87606043">FSMC_BTR2_ACCMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad11258e9138b98bf6387167f0a2645f9">FSMC_BTR2_ACCMOD_Msk</a></td></tr>
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<tr class="memitem:ga9383d89d5e557a166f6b8290892b89b3" id="r_ga9383d89d5e557a166f6b8290892b89b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9383d89d5e557a166f6b8290892b89b3">FSMC_BTR2_ACCMOD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9cba11e01cd8e90b1e56a3d52c44025">FSMC_BTR2_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:gad200e1dc2d1835e3dc0fa8f0483eb2c0" id="r_gad200e1dc2d1835e3dc0fa8f0483eb2c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad200e1dc2d1835e3dc0fa8f0483eb2c0">FSMC_BTR2_ACCMOD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9cba11e01cd8e90b1e56a3d52c44025">FSMC_BTR2_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga3f6c91220bbb34e5cb90903df17cfd63" id="r_ga3f6c91220bbb34e5cb90903df17cfd63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f6c91220bbb34e5cb90903df17cfd63">FSMC_BTR3_ADDSET_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga6a2fd577c6b176ec1d1ed35f4230ea74" id="r_ga6a2fd577c6b176ec1d1ed35f4230ea74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a2fd577c6b176ec1d1ed35f4230ea74">FSMC_BTR3_ADDSET_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f6c91220bbb34e5cb90903df17cfd63">FSMC_BTR3_ADDSET_Pos</a>)</td></tr>
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<tr class="separator:ga6a2fd577c6b176ec1d1ed35f4230ea74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3e55daf436a25fadae7384611aa0f89" id="r_gaf3e55daf436a25fadae7384611aa0f89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3e55daf436a25fadae7384611aa0f89">FSMC_BTR3_ADDSET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a2fd577c6b176ec1d1ed35f4230ea74">FSMC_BTR3_ADDSET_Msk</a></td></tr>
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<tr class="memitem:gab6a21211dd7a3445e944af0fe1a4b600" id="r_gab6a21211dd7a3445e944af0fe1a4b600"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6a21211dd7a3445e944af0fe1a4b600">FSMC_BTR3_ADDSET_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f6c91220bbb34e5cb90903df17cfd63">FSMC_BTR3_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga51c23d36fa8e7e38048d94830bf0f74f" id="r_ga51c23d36fa8e7e38048d94830bf0f74f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51c23d36fa8e7e38048d94830bf0f74f">FSMC_BTR3_ADDSET_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f6c91220bbb34e5cb90903df17cfd63">FSMC_BTR3_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga93be4171cb7d0b66d8d4d12e61b07b88" id="r_ga93be4171cb7d0b66d8d4d12e61b07b88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93be4171cb7d0b66d8d4d12e61b07b88">FSMC_BTR3_ADDSET_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f6c91220bbb34e5cb90903df17cfd63">FSMC_BTR3_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gab01cf0b1c88857669d10fee8d7ba4d85" id="r_gab01cf0b1c88857669d10fee8d7ba4d85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab01cf0b1c88857669d10fee8d7ba4d85">FSMC_BTR3_ADDSET_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f6c91220bbb34e5cb90903df17cfd63">FSMC_BTR3_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gac4fb45db8d202b537ad7ca41ed70f459" id="r_gac4fb45db8d202b537ad7ca41ed70f459"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4fb45db8d202b537ad7ca41ed70f459">FSMC_BTR3_ADDHLD_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga2bf5884c4cc7c453908e3ac5272244b7" id="r_ga2bf5884c4cc7c453908e3ac5272244b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf5884c4cc7c453908e3ac5272244b7">FSMC_BTR3_ADDHLD_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fb45db8d202b537ad7ca41ed70f459">FSMC_BTR3_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga7833ee760b2400e6fb483b1d83cbdff3" id="r_ga7833ee760b2400e6fb483b1d83cbdff3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7833ee760b2400e6fb483b1d83cbdff3">FSMC_BTR3_ADDHLD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf5884c4cc7c453908e3ac5272244b7">FSMC_BTR3_ADDHLD_Msk</a></td></tr>
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<tr class="memitem:gad417ccae1c4018d0ff5c76c942aeb2ca" id="r_gad417ccae1c4018d0ff5c76c942aeb2ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad417ccae1c4018d0ff5c76c942aeb2ca">FSMC_BTR3_ADDHLD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fb45db8d202b537ad7ca41ed70f459">FSMC_BTR3_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga60d0ae6af13ef088367cef06c7f207d3" id="r_ga60d0ae6af13ef088367cef06c7f207d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60d0ae6af13ef088367cef06c7f207d3">FSMC_BTR3_ADDHLD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fb45db8d202b537ad7ca41ed70f459">FSMC_BTR3_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gac029aaed48e2a3e2eedf767fe0ce0b92" id="r_gac029aaed48e2a3e2eedf767fe0ce0b92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac029aaed48e2a3e2eedf767fe0ce0b92">FSMC_BTR3_ADDHLD_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fb45db8d202b537ad7ca41ed70f459">FSMC_BTR3_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga5b6aab5907bc42e140ca5a4d60fcd64c" id="r_ga5b6aab5907bc42e140ca5a4d60fcd64c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b6aab5907bc42e140ca5a4d60fcd64c">FSMC_BTR3_ADDHLD_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fb45db8d202b537ad7ca41ed70f459">FSMC_BTR3_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga524942cc9d0eaf2095a6598db32db389" id="r_ga524942cc9d0eaf2095a6598db32db389"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389">FSMC_BTR3_DATAST_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gaf38dfdbab53cbef7b90eb2503114f121" id="r_gaf38dfdbab53cbef7b90eb2503114f121"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf38dfdbab53cbef7b90eb2503114f121">FSMC_BTR3_DATAST_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389">FSMC_BTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga1e9ac671a510ee06e86c41d7876ffe10" id="r_ga1e9ac671a510ee06e86c41d7876ffe10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e9ac671a510ee06e86c41d7876ffe10">FSMC_BTR3_DATAST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf38dfdbab53cbef7b90eb2503114f121">FSMC_BTR3_DATAST_Msk</a></td></tr>
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<tr class="memitem:ga65fe87d29c1a4ee0b08014ed8e0423e1" id="r_ga65fe87d29c1a4ee0b08014ed8e0423e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65fe87d29c1a4ee0b08014ed8e0423e1">FSMC_BTR3_DATAST_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389">FSMC_BTR3_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga65fe87d29c1a4ee0b08014ed8e0423e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad33e3df5c80255cb5e11ba427e9c224f" id="r_gad33e3df5c80255cb5e11ba427e9c224f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad33e3df5c80255cb5e11ba427e9c224f">FSMC_BTR3_DATAST_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389">FSMC_BTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga4a31f070e41c6785ebc606d4f25d103a" id="r_ga4a31f070e41c6785ebc606d4f25d103a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a31f070e41c6785ebc606d4f25d103a">FSMC_BTR3_DATAST_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389">FSMC_BTR3_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga4a31f070e41c6785ebc606d4f25d103a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad220fbd264261a37eac09d4f6c0b79a2" id="r_gad220fbd264261a37eac09d4f6c0b79a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad220fbd264261a37eac09d4f6c0b79a2">FSMC_BTR3_DATAST_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389">FSMC_BTR3_DATAST_Pos</a>)</td></tr>
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<tr class="separator:gad220fbd264261a37eac09d4f6c0b79a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab78ca925e07c24a308b1e603ed42aae1" id="r_gab78ca925e07c24a308b1e603ed42aae1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab78ca925e07c24a308b1e603ed42aae1">FSMC_BTR3_DATAST_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389">FSMC_BTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga3b61775591ffb8faef03a13435fd98b8" id="r_ga3b61775591ffb8faef03a13435fd98b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b61775591ffb8faef03a13435fd98b8">FSMC_BTR3_DATAST_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389">FSMC_BTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga2d58607a3de993f0f7227a14b81ab56c" id="r_ga2d58607a3de993f0f7227a14b81ab56c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d58607a3de993f0f7227a14b81ab56c">FSMC_BTR3_DATAST_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389">FSMC_BTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga10dc7226824fa6ad00380417b3ba095d" id="r_ga10dc7226824fa6ad00380417b3ba095d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10dc7226824fa6ad00380417b3ba095d">FSMC_BTR3_DATAST_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389">FSMC_BTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga2b7b831c25c61676309f80788ec1a9e9" id="r_ga2b7b831c25c61676309f80788ec1a9e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b7b831c25c61676309f80788ec1a9e9">FSMC_BTR3_BUSTURN_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga3a87c9110d709faefbf2d08ee49ca874" id="r_ga3a87c9110d709faefbf2d08ee49ca874"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a87c9110d709faefbf2d08ee49ca874">FSMC_BTR3_BUSTURN_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b7b831c25c61676309f80788ec1a9e9">FSMC_BTR3_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gae8a3ad9f940c6942682d8d97b1eb0ca4" id="r_gae8a3ad9f940c6942682d8d97b1eb0ca4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8a3ad9f940c6942682d8d97b1eb0ca4">FSMC_BTR3_BUSTURN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a87c9110d709faefbf2d08ee49ca874">FSMC_BTR3_BUSTURN_Msk</a></td></tr>
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<tr class="memitem:ga739f2db66e52626aa9a5ee02c11d7a34" id="r_ga739f2db66e52626aa9a5ee02c11d7a34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga739f2db66e52626aa9a5ee02c11d7a34">FSMC_BTR3_BUSTURN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b7b831c25c61676309f80788ec1a9e9">FSMC_BTR3_BUSTURN_Pos</a>)</td></tr>
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<tr class="separator:ga739f2db66e52626aa9a5ee02c11d7a34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e4c4102ea6e6cf2082e78168edfc18e" id="r_ga7e4c4102ea6e6cf2082e78168edfc18e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e4c4102ea6e6cf2082e78168edfc18e">FSMC_BTR3_BUSTURN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b7b831c25c61676309f80788ec1a9e9">FSMC_BTR3_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gad5eab2601ae3cd040bf44feb3e70c459" id="r_gad5eab2601ae3cd040bf44feb3e70c459"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5eab2601ae3cd040bf44feb3e70c459">FSMC_BTR3_BUSTURN_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b7b831c25c61676309f80788ec1a9e9">FSMC_BTR3_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gacf61e23804e0fa3ca45f851ca98de371" id="r_gacf61e23804e0fa3ca45f851ca98de371"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf61e23804e0fa3ca45f851ca98de371">FSMC_BTR3_BUSTURN_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b7b831c25c61676309f80788ec1a9e9">FSMC_BTR3_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gada052eafe7f4ee032f364b82040350a9" id="r_gada052eafe7f4ee032f364b82040350a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada052eafe7f4ee032f364b82040350a9">FSMC_BTR3_CLKDIV_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga050d3fd57381342b9c5d1153623e5d64" id="r_ga050d3fd57381342b9c5d1153623e5d64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga050d3fd57381342b9c5d1153623e5d64">FSMC_BTR3_CLKDIV_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada052eafe7f4ee032f364b82040350a9">FSMC_BTR3_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga47a8d8e279c50995143ecf4124580703" id="r_ga47a8d8e279c50995143ecf4124580703"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47a8d8e279c50995143ecf4124580703">FSMC_BTR3_CLKDIV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga050d3fd57381342b9c5d1153623e5d64">FSMC_BTR3_CLKDIV_Msk</a></td></tr>
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<tr class="memitem:gadd9c93b0ee64856981394a63d6a3a964" id="r_gadd9c93b0ee64856981394a63d6a3a964"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd9c93b0ee64856981394a63d6a3a964">FSMC_BTR3_CLKDIV_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada052eafe7f4ee032f364b82040350a9">FSMC_BTR3_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga98fa7611b4ae197ab25cdf1cae9f8ee1" id="r_ga98fa7611b4ae197ab25cdf1cae9f8ee1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98fa7611b4ae197ab25cdf1cae9f8ee1">FSMC_BTR3_CLKDIV_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada052eafe7f4ee032f364b82040350a9">FSMC_BTR3_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:gaf806c044b2a3d1417acc79907dcaef4b" id="r_gaf806c044b2a3d1417acc79907dcaef4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf806c044b2a3d1417acc79907dcaef4b">FSMC_BTR3_CLKDIV_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada052eafe7f4ee032f364b82040350a9">FSMC_BTR3_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:gaa9bf0683d046f9bcfb0d55a065ae69ab" id="r_gaa9bf0683d046f9bcfb0d55a065ae69ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9bf0683d046f9bcfb0d55a065ae69ab">FSMC_BTR3_CLKDIV_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada052eafe7f4ee032f364b82040350a9">FSMC_BTR3_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga949454e87f17316a0253839e17ebacc6" id="r_ga949454e87f17316a0253839e17ebacc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga949454e87f17316a0253839e17ebacc6">FSMC_BTR3_DATLAT_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga8e8b7682eb997746f807814f4d41ca6b" id="r_ga8e8b7682eb997746f807814f4d41ca6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e8b7682eb997746f807814f4d41ca6b">FSMC_BTR3_DATLAT_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga949454e87f17316a0253839e17ebacc6">FSMC_BTR3_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:gaa88a80458ddd56b0dfa7cf3599b986dd" id="r_gaa88a80458ddd56b0dfa7cf3599b986dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa88a80458ddd56b0dfa7cf3599b986dd">FSMC_BTR3_DATLAT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e8b7682eb997746f807814f4d41ca6b">FSMC_BTR3_DATLAT_Msk</a></td></tr>
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<tr class="memitem:ga655083fdb0e563b9a4d6ea589194ba02" id="r_ga655083fdb0e563b9a4d6ea589194ba02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga655083fdb0e563b9a4d6ea589194ba02">FSMC_BTR3_DATLAT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga949454e87f17316a0253839e17ebacc6">FSMC_BTR3_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:ga486280713c8f07d7033bce4e74825130" id="r_ga486280713c8f07d7033bce4e74825130"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga486280713c8f07d7033bce4e74825130">FSMC_BTR3_DATLAT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga949454e87f17316a0253839e17ebacc6">FSMC_BTR3_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:ga8314e30c84dccd983de04fdeeb57c360" id="r_ga8314e30c84dccd983de04fdeeb57c360"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8314e30c84dccd983de04fdeeb57c360">FSMC_BTR3_DATLAT_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga949454e87f17316a0253839e17ebacc6">FSMC_BTR3_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:gac7e7da5269a2dac164c9d1d01da2bc28" id="r_gac7e7da5269a2dac164c9d1d01da2bc28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7e7da5269a2dac164c9d1d01da2bc28">FSMC_BTR3_DATLAT_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga949454e87f17316a0253839e17ebacc6">FSMC_BTR3_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:ga61e6d33a30b831902487e19a9d79bed0" id="r_ga61e6d33a30b831902487e19a9d79bed0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61e6d33a30b831902487e19a9d79bed0">FSMC_BTR3_ACCMOD_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga61e6d33a30b831902487e19a9d79bed0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02766e5c7ca9549655ea80d68267062e" id="r_ga02766e5c7ca9549655ea80d68267062e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02766e5c7ca9549655ea80d68267062e">FSMC_BTR3_ACCMOD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61e6d33a30b831902487e19a9d79bed0">FSMC_BTR3_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga56c8f213e437ceed2140f2c16a0416cd" id="r_ga56c8f213e437ceed2140f2c16a0416cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56c8f213e437ceed2140f2c16a0416cd">FSMC_BTR3_ACCMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga02766e5c7ca9549655ea80d68267062e">FSMC_BTR3_ACCMOD_Msk</a></td></tr>
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<tr class="memitem:ga4d50e71940995d42c5f9fadcb7cd61f2" id="r_ga4d50e71940995d42c5f9fadcb7cd61f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d50e71940995d42c5f9fadcb7cd61f2">FSMC_BTR3_ACCMOD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61e6d33a30b831902487e19a9d79bed0">FSMC_BTR3_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:gac8bbfd5e08b73d1c5de53ee0ff0ddb9a" id="r_gac8bbfd5e08b73d1c5de53ee0ff0ddb9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8bbfd5e08b73d1c5de53ee0ff0ddb9a">FSMC_BTR3_ACCMOD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61e6d33a30b831902487e19a9d79bed0">FSMC_BTR3_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:gabeff2f8b714d12899beab5530219676b" id="r_gabeff2f8b714d12899beab5530219676b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabeff2f8b714d12899beab5530219676b">FSMC_BTR4_ADDSET_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga6ffb05b35bc25ca9f5f8629e241482c2" id="r_ga6ffb05b35bc25ca9f5f8629e241482c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ffb05b35bc25ca9f5f8629e241482c2">FSMC_BTR4_ADDSET_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabeff2f8b714d12899beab5530219676b">FSMC_BTR4_ADDSET_Pos</a>)</td></tr>
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<tr class="separator:ga6ffb05b35bc25ca9f5f8629e241482c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab44cc2146b4cf6bc8f43292512fd8cf8" id="r_gab44cc2146b4cf6bc8f43292512fd8cf8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab44cc2146b4cf6bc8f43292512fd8cf8">FSMC_BTR4_ADDSET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ffb05b35bc25ca9f5f8629e241482c2">FSMC_BTR4_ADDSET_Msk</a></td></tr>
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<tr class="memitem:gaa0ee1ab3716b0ab1a4e7b51234af7c63" id="r_gaa0ee1ab3716b0ab1a4e7b51234af7c63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0ee1ab3716b0ab1a4e7b51234af7c63">FSMC_BTR4_ADDSET_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabeff2f8b714d12899beab5530219676b">FSMC_BTR4_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gacd427c001c5b17a3e083c81f6b228a50" id="r_gacd427c001c5b17a3e083c81f6b228a50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd427c001c5b17a3e083c81f6b228a50">FSMC_BTR4_ADDSET_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabeff2f8b714d12899beab5530219676b">FSMC_BTR4_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gae722fdaa69bfb7622aa80c82e3772949" id="r_gae722fdaa69bfb7622aa80c82e3772949"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae722fdaa69bfb7622aa80c82e3772949">FSMC_BTR4_ADDSET_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabeff2f8b714d12899beab5530219676b">FSMC_BTR4_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga0f8ab4a1c7fe6e7dc2b093add88c274e" id="r_ga0f8ab4a1c7fe6e7dc2b093add88c274e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f8ab4a1c7fe6e7dc2b093add88c274e">FSMC_BTR4_ADDSET_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabeff2f8b714d12899beab5530219676b">FSMC_BTR4_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gab3d440dee3fe200e9aaeaa5ca74c7cda" id="r_gab3d440dee3fe200e9aaeaa5ca74c7cda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3d440dee3fe200e9aaeaa5ca74c7cda">FSMC_BTR4_ADDHLD_Pos</a>   (4U)</td></tr>
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<tr class="memitem:gaaabb5da557aa89d3f786f2bae2fb3bf0" id="r_gaaabb5da557aa89d3f786f2bae2fb3bf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaabb5da557aa89d3f786f2bae2fb3bf0">FSMC_BTR4_ADDHLD_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3d440dee3fe200e9aaeaa5ca74c7cda">FSMC_BTR4_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga1e52ae9a5d59507bdf9f4f9da19444ed" id="r_ga1e52ae9a5d59507bdf9f4f9da19444ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e52ae9a5d59507bdf9f4f9da19444ed">FSMC_BTR4_ADDHLD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaabb5da557aa89d3f786f2bae2fb3bf0">FSMC_BTR4_ADDHLD_Msk</a></td></tr>
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<tr class="memitem:gadf6200f13c3eed1e9646750897a987a2" id="r_gadf6200f13c3eed1e9646750897a987a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf6200f13c3eed1e9646750897a987a2">FSMC_BTR4_ADDHLD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3d440dee3fe200e9aaeaa5ca74c7cda">FSMC_BTR4_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga0803bc2ad60138e0eef53a53ca5bf537" id="r_ga0803bc2ad60138e0eef53a53ca5bf537"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0803bc2ad60138e0eef53a53ca5bf537">FSMC_BTR4_ADDHLD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3d440dee3fe200e9aaeaa5ca74c7cda">FSMC_BTR4_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga893711250b9d3ea2e5e48ca53d1e0147" id="r_ga893711250b9d3ea2e5e48ca53d1e0147"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga893711250b9d3ea2e5e48ca53d1e0147">FSMC_BTR4_ADDHLD_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3d440dee3fe200e9aaeaa5ca74c7cda">FSMC_BTR4_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga75c73d4bb0ddcac383ca610a604d95b3" id="r_ga75c73d4bb0ddcac383ca610a604d95b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75c73d4bb0ddcac383ca610a604d95b3">FSMC_BTR4_ADDHLD_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3d440dee3fe200e9aaeaa5ca74c7cda">FSMC_BTR4_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga66d0e68db7568649671e7b0338acb688" id="r_ga66d0e68db7568649671e7b0338acb688"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688">FSMC_BTR4_DATAST_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gab99647a6ac8c924ad739bc5cc7244c01" id="r_gab99647a6ac8c924ad739bc5cc7244c01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab99647a6ac8c924ad739bc5cc7244c01">FSMC_BTR4_DATAST_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688">FSMC_BTR4_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga2c28625ee031527a29f7cb7db1bb97cf" id="r_ga2c28625ee031527a29f7cb7db1bb97cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c28625ee031527a29f7cb7db1bb97cf">FSMC_BTR4_DATAST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab99647a6ac8c924ad739bc5cc7244c01">FSMC_BTR4_DATAST_Msk</a></td></tr>
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<tr class="memitem:gabdb0212604c6c58c9524adc7931e2897" id="r_gabdb0212604c6c58c9524adc7931e2897"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdb0212604c6c58c9524adc7931e2897">FSMC_BTR4_DATAST_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688">FSMC_BTR4_DATAST_Pos</a>)</td></tr>
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<tr class="separator:gabdb0212604c6c58c9524adc7931e2897"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2353d753ca5532703b4f822b7d2a7382" id="r_ga2353d753ca5532703b4f822b7d2a7382"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2353d753ca5532703b4f822b7d2a7382">FSMC_BTR4_DATAST_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688">FSMC_BTR4_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga2353d753ca5532703b4f822b7d2a7382"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d82a6f3fcf69d6b96968118db7b8216" id="r_ga8d82a6f3fcf69d6b96968118db7b8216"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d82a6f3fcf69d6b96968118db7b8216">FSMC_BTR4_DATAST_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688">FSMC_BTR4_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga8d82a6f3fcf69d6b96968118db7b8216"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e0860f92bb204c4b5902d3e34b8b30a" id="r_ga3e0860f92bb204c4b5902d3e34b8b30a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e0860f92bb204c4b5902d3e34b8b30a">FSMC_BTR4_DATAST_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688">FSMC_BTR4_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga3e0860f92bb204c4b5902d3e34b8b30a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d6f871ca941d2beed194d2fc5190183" id="r_ga7d6f871ca941d2beed194d2fc5190183"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d6f871ca941d2beed194d2fc5190183">FSMC_BTR4_DATAST_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688">FSMC_BTR4_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gaa798a7170769793b25d5cc37e9eff679" id="r_gaa798a7170769793b25d5cc37e9eff679"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa798a7170769793b25d5cc37e9eff679">FSMC_BTR4_DATAST_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688">FSMC_BTR4_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gac4c89f39ac5a74bdd3fc406da173fe79" id="r_gac4c89f39ac5a74bdd3fc406da173fe79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4c89f39ac5a74bdd3fc406da173fe79">FSMC_BTR4_DATAST_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688">FSMC_BTR4_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga633b76f7fce6507cf044dcb3d82a0d8d" id="r_ga633b76f7fce6507cf044dcb3d82a0d8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga633b76f7fce6507cf044dcb3d82a0d8d">FSMC_BTR4_DATAST_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688">FSMC_BTR4_DATAST_Pos</a>)</td></tr>
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<tr class="separator:ga633b76f7fce6507cf044dcb3d82a0d8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98966c488a394376e2b3bff182317cf6" id="r_ga98966c488a394376e2b3bff182317cf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98966c488a394376e2b3bff182317cf6">FSMC_BTR4_BUSTURN_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gaa72c6ff1ec6f4fb7dee9a109ddc9835f" id="r_gaa72c6ff1ec6f4fb7dee9a109ddc9835f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa72c6ff1ec6f4fb7dee9a109ddc9835f">FSMC_BTR4_BUSTURN_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98966c488a394376e2b3bff182317cf6">FSMC_BTR4_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga207a9eedfc1b244c393be3c34ea60a15" id="r_ga207a9eedfc1b244c393be3c34ea60a15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga207a9eedfc1b244c393be3c34ea60a15">FSMC_BTR4_BUSTURN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa72c6ff1ec6f4fb7dee9a109ddc9835f">FSMC_BTR4_BUSTURN_Msk</a></td></tr>
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<tr class="memitem:ga4dec1fa50fca6639be7179d445aacfe4" id="r_ga4dec1fa50fca6639be7179d445aacfe4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dec1fa50fca6639be7179d445aacfe4">FSMC_BTR4_BUSTURN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98966c488a394376e2b3bff182317cf6">FSMC_BTR4_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gab1db211382068251dc5cfe44a175e639" id="r_gab1db211382068251dc5cfe44a175e639"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1db211382068251dc5cfe44a175e639">FSMC_BTR4_BUSTURN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98966c488a394376e2b3bff182317cf6">FSMC_BTR4_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gaa5391a8c2a1e8cd6abb81fa5b2836464" id="r_gaa5391a8c2a1e8cd6abb81fa5b2836464"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5391a8c2a1e8cd6abb81fa5b2836464">FSMC_BTR4_BUSTURN_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98966c488a394376e2b3bff182317cf6">FSMC_BTR4_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gadbfd74790a1e25339151de440e3a93e5" id="r_gadbfd74790a1e25339151de440e3a93e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbfd74790a1e25339151de440e3a93e5">FSMC_BTR4_BUSTURN_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98966c488a394376e2b3bff182317cf6">FSMC_BTR4_BUSTURN_Pos</a>)</td></tr>
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<tr class="separator:gadbfd74790a1e25339151de440e3a93e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97a0c80d8b160a03fb4276150054be56" id="r_ga97a0c80d8b160a03fb4276150054be56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97a0c80d8b160a03fb4276150054be56">FSMC_BTR4_CLKDIV_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga20d19a8021d7c397928886a751546a0f" id="r_ga20d19a8021d7c397928886a751546a0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20d19a8021d7c397928886a751546a0f">FSMC_BTR4_CLKDIV_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97a0c80d8b160a03fb4276150054be56">FSMC_BTR4_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga7ac39964e3792653e454538407b11504" id="r_ga7ac39964e3792653e454538407b11504"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac39964e3792653e454538407b11504">FSMC_BTR4_CLKDIV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga20d19a8021d7c397928886a751546a0f">FSMC_BTR4_CLKDIV_Msk</a></td></tr>
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<tr class="memitem:gaacee394c98ac568fe1d6df61c887ed53" id="r_gaacee394c98ac568fe1d6df61c887ed53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacee394c98ac568fe1d6df61c887ed53">FSMC_BTR4_CLKDIV_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97a0c80d8b160a03fb4276150054be56">FSMC_BTR4_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga9c7cd1d1a4954d494bd107400925f86f" id="r_ga9c7cd1d1a4954d494bd107400925f86f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c7cd1d1a4954d494bd107400925f86f">FSMC_BTR4_CLKDIV_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97a0c80d8b160a03fb4276150054be56">FSMC_BTR4_CLKDIV_Pos</a>)</td></tr>
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<tr class="separator:ga9c7cd1d1a4954d494bd107400925f86f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93b0ab3235ffacca24e6b285460c5dd3" id="r_ga93b0ab3235ffacca24e6b285460c5dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93b0ab3235ffacca24e6b285460c5dd3">FSMC_BTR4_CLKDIV_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97a0c80d8b160a03fb4276150054be56">FSMC_BTR4_CLKDIV_Pos</a>)</td></tr>
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<tr class="separator:ga93b0ab3235ffacca24e6b285460c5dd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga931463443390c5a706303e87a538d1ce" id="r_ga931463443390c5a706303e87a538d1ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga931463443390c5a706303e87a538d1ce">FSMC_BTR4_CLKDIV_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97a0c80d8b160a03fb4276150054be56">FSMC_BTR4_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:gaa90d3bce2e4d950c80022117b564cb2c" id="r_gaa90d3bce2e4d950c80022117b564cb2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa90d3bce2e4d950c80022117b564cb2c">FSMC_BTR4_DATLAT_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaa90d3bce2e4d950c80022117b564cb2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga737ae8e9d7fbf9906256a03e24d498aa" id="r_ga737ae8e9d7fbf9906256a03e24d498aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga737ae8e9d7fbf9906256a03e24d498aa">FSMC_BTR4_DATLAT_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa90d3bce2e4d950c80022117b564cb2c">FSMC_BTR4_DATLAT_Pos</a>)</td></tr>
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<tr class="separator:ga737ae8e9d7fbf9906256a03e24d498aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa53cb7c299e794915d3aba803374adca" id="r_gaa53cb7c299e794915d3aba803374adca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa53cb7c299e794915d3aba803374adca">FSMC_BTR4_DATLAT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga737ae8e9d7fbf9906256a03e24d498aa">FSMC_BTR4_DATLAT_Msk</a></td></tr>
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<tr class="memitem:gad2315f17d1cd7dd9da1b0ee2f7e4ea29" id="r_gad2315f17d1cd7dd9da1b0ee2f7e4ea29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2315f17d1cd7dd9da1b0ee2f7e4ea29">FSMC_BTR4_DATLAT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa90d3bce2e4d950c80022117b564cb2c">FSMC_BTR4_DATLAT_Pos</a>)</td></tr>
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<tr class="separator:gad2315f17d1cd7dd9da1b0ee2f7e4ea29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga808a7d758e6ca75c573d08ee92228745" id="r_ga808a7d758e6ca75c573d08ee92228745"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga808a7d758e6ca75c573d08ee92228745">FSMC_BTR4_DATLAT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa90d3bce2e4d950c80022117b564cb2c">FSMC_BTR4_DATLAT_Pos</a>)</td></tr>
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<tr class="separator:ga808a7d758e6ca75c573d08ee92228745"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac376a62779292d64bfac24d572b743e9" id="r_gac376a62779292d64bfac24d572b743e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac376a62779292d64bfac24d572b743e9">FSMC_BTR4_DATLAT_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa90d3bce2e4d950c80022117b564cb2c">FSMC_BTR4_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:gadfc558894dcb263451dbac13f48fffe1" id="r_gadfc558894dcb263451dbac13f48fffe1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfc558894dcb263451dbac13f48fffe1">FSMC_BTR4_DATLAT_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa90d3bce2e4d950c80022117b564cb2c">FSMC_BTR4_DATLAT_Pos</a>)</td></tr>
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<tr class="memitem:ga88757eb5c47614f56b9fb13646b437e8" id="r_ga88757eb5c47614f56b9fb13646b437e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88757eb5c47614f56b9fb13646b437e8">FSMC_BTR4_ACCMOD_Pos</a>   (28U)</td></tr>
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<tr class="memitem:ga37535c8d3cc7d4388312e6640d513f6a" id="r_ga37535c8d3cc7d4388312e6640d513f6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37535c8d3cc7d4388312e6640d513f6a">FSMC_BTR4_ACCMOD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga88757eb5c47614f56b9fb13646b437e8">FSMC_BTR4_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:gabbf731d99007936586f9e15f17c3c771" id="r_gabbf731d99007936586f9e15f17c3c771"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbf731d99007936586f9e15f17c3c771">FSMC_BTR4_ACCMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga37535c8d3cc7d4388312e6640d513f6a">FSMC_BTR4_ACCMOD_Msk</a></td></tr>
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<tr class="memitem:ga8e69759ab89b16573bafd2f6ded95bfb" id="r_ga8e69759ab89b16573bafd2f6ded95bfb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e69759ab89b16573bafd2f6ded95bfb">FSMC_BTR4_ACCMOD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga88757eb5c47614f56b9fb13646b437e8">FSMC_BTR4_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga3e486b11f6af0f566f8843a5c95c6a6c" id="r_ga3e486b11f6af0f566f8843a5c95c6a6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e486b11f6af0f566f8843a5c95c6a6c">FSMC_BTR4_ACCMOD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga88757eb5c47614f56b9fb13646b437e8">FSMC_BTR4_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga52ddd50ef2636a8e0bb45957d72b6a49" id="r_ga52ddd50ef2636a8e0bb45957d72b6a49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52ddd50ef2636a8e0bb45957d72b6a49">FSMC_BWTR1_ADDSET_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga513a9612a5c7c61086b2f85d83e2653f" id="r_ga513a9612a5c7c61086b2f85d83e2653f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga513a9612a5c7c61086b2f85d83e2653f">FSMC_BWTR1_ADDSET_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52ddd50ef2636a8e0bb45957d72b6a49">FSMC_BWTR1_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga4aa5ee153cb4bf79f0d4ae2c47f365c4" id="r_ga4aa5ee153cb4bf79f0d4ae2c47f365c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4aa5ee153cb4bf79f0d4ae2c47f365c4">FSMC_BWTR1_ADDSET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga513a9612a5c7c61086b2f85d83e2653f">FSMC_BWTR1_ADDSET_Msk</a></td></tr>
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<tr class="memitem:gaacb80aeedb6d0d9cb09e7b4d3ff8b541" id="r_gaacb80aeedb6d0d9cb09e7b4d3ff8b541"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacb80aeedb6d0d9cb09e7b4d3ff8b541">FSMC_BWTR1_ADDSET_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52ddd50ef2636a8e0bb45957d72b6a49">FSMC_BWTR1_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga20dbbdff1e2f1d57727dabbc4b03c840" id="r_ga20dbbdff1e2f1d57727dabbc4b03c840"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20dbbdff1e2f1d57727dabbc4b03c840">FSMC_BWTR1_ADDSET_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52ddd50ef2636a8e0bb45957d72b6a49">FSMC_BWTR1_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga411f0d164c26dda8132ff22856757470" id="r_ga411f0d164c26dda8132ff22856757470"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga411f0d164c26dda8132ff22856757470">FSMC_BWTR1_ADDSET_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52ddd50ef2636a8e0bb45957d72b6a49">FSMC_BWTR1_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga3e2bc67999e8d2b63771fa223ffa8e4d" id="r_ga3e2bc67999e8d2b63771fa223ffa8e4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e2bc67999e8d2b63771fa223ffa8e4d">FSMC_BWTR1_ADDSET_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52ddd50ef2636a8e0bb45957d72b6a49">FSMC_BWTR1_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gaa6e3be36c874835e8d5b50c546a6e5ce" id="r_gaa6e3be36c874835e8d5b50c546a6e5ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e3be36c874835e8d5b50c546a6e5ce">FSMC_BWTR1_ADDHLD_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga4772c530938b9f655bb0a807b9cd0f9d" id="r_ga4772c530938b9f655bb0a807b9cd0f9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4772c530938b9f655bb0a807b9cd0f9d">FSMC_BWTR1_ADDHLD_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e3be36c874835e8d5b50c546a6e5ce">FSMC_BWTR1_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gafa3d8ff62f87ab6aeb5170dd67de15cf" id="r_gafa3d8ff62f87ab6aeb5170dd67de15cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa3d8ff62f87ab6aeb5170dd67de15cf">FSMC_BWTR1_ADDHLD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4772c530938b9f655bb0a807b9cd0f9d">FSMC_BWTR1_ADDHLD_Msk</a></td></tr>
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<tr class="memitem:ga1e24880c23375636d7504d42077a400a" id="r_ga1e24880c23375636d7504d42077a400a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e24880c23375636d7504d42077a400a">FSMC_BWTR1_ADDHLD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e3be36c874835e8d5b50c546a6e5ce">FSMC_BWTR1_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gafb90dec93198b1d3077feb5fe508f004" id="r_gafb90dec93198b1d3077feb5fe508f004"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb90dec93198b1d3077feb5fe508f004">FSMC_BWTR1_ADDHLD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e3be36c874835e8d5b50c546a6e5ce">FSMC_BWTR1_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga26ef7d6cd5ec547a349462e4f31963b6" id="r_ga26ef7d6cd5ec547a349462e4f31963b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26ef7d6cd5ec547a349462e4f31963b6">FSMC_BWTR1_ADDHLD_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e3be36c874835e8d5b50c546a6e5ce">FSMC_BWTR1_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gac4a961ecd844e14a90d1b2f6c5d59196" id="r_gac4a961ecd844e14a90d1b2f6c5d59196"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4a961ecd844e14a90d1b2f6c5d59196">FSMC_BWTR1_ADDHLD_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e3be36c874835e8d5b50c546a6e5ce">FSMC_BWTR1_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga816436841706a81e91cc1627906c7e64" id="r_ga816436841706a81e91cc1627906c7e64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64">FSMC_BWTR1_DATAST_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga3de71f2a794f4e7a5e3135c715f644cc" id="r_ga3de71f2a794f4e7a5e3135c715f644cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3de71f2a794f4e7a5e3135c715f644cc">FSMC_BWTR1_DATAST_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64">FSMC_BWTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gaee2641a6f415d03df324667662bd3dcf" id="r_gaee2641a6f415d03df324667662bd3dcf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee2641a6f415d03df324667662bd3dcf">FSMC_BWTR1_DATAST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3de71f2a794f4e7a5e3135c715f644cc">FSMC_BWTR1_DATAST_Msk</a></td></tr>
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<tr class="memitem:ga162800452847dd98d27a4078370518b2" id="r_ga162800452847dd98d27a4078370518b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga162800452847dd98d27a4078370518b2">FSMC_BWTR1_DATAST_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64">FSMC_BWTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga16476bfbbcb9726c1fbc593d3568a514" id="r_ga16476bfbbcb9726c1fbc593d3568a514"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16476bfbbcb9726c1fbc593d3568a514">FSMC_BWTR1_DATAST_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64">FSMC_BWTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga623de376d9f5189d73068d0865a5049e" id="r_ga623de376d9f5189d73068d0865a5049e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga623de376d9f5189d73068d0865a5049e">FSMC_BWTR1_DATAST_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64">FSMC_BWTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gade0627f53e3df25fdaa973db6159bd70" id="r_gade0627f53e3df25fdaa973db6159bd70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade0627f53e3df25fdaa973db6159bd70">FSMC_BWTR1_DATAST_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64">FSMC_BWTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga39b5d7ddf6673ff23684c147c192f61b" id="r_ga39b5d7ddf6673ff23684c147c192f61b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39b5d7ddf6673ff23684c147c192f61b">FSMC_BWTR1_DATAST_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64">FSMC_BWTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga211042c480c7d87941b584a591f7d0ab" id="r_ga211042c480c7d87941b584a591f7d0ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga211042c480c7d87941b584a591f7d0ab">FSMC_BWTR1_DATAST_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64">FSMC_BWTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga62232d4ec2bbbf375cfa555f947345fa" id="r_ga62232d4ec2bbbf375cfa555f947345fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62232d4ec2bbbf375cfa555f947345fa">FSMC_BWTR1_DATAST_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64">FSMC_BWTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga7768908f2843432c6e4a4eb8e5153539" id="r_ga7768908f2843432c6e4a4eb8e5153539"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7768908f2843432c6e4a4eb8e5153539">FSMC_BWTR1_DATAST_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64">FSMC_BWTR1_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gade809e856484f40f6e54001fd88c7c80" id="r_gade809e856484f40f6e54001fd88c7c80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade809e856484f40f6e54001fd88c7c80">FSMC_BWTR1_BUSTURN_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga60c9f9abbf9f8110e9d7d5b729932af0" id="r_ga60c9f9abbf9f8110e9d7d5b729932af0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60c9f9abbf9f8110e9d7d5b729932af0">FSMC_BWTR1_BUSTURN_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade809e856484f40f6e54001fd88c7c80">FSMC_BWTR1_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga01289633ae20e7face5cb85cc031b532" id="r_ga01289633ae20e7face5cb85cc031b532"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01289633ae20e7face5cb85cc031b532">FSMC_BWTR1_BUSTURN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga60c9f9abbf9f8110e9d7d5b729932af0">FSMC_BWTR1_BUSTURN_Msk</a></td></tr>
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<tr class="memitem:ga98fad3a30bdcb37dadcf7a443798e202" id="r_ga98fad3a30bdcb37dadcf7a443798e202"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98fad3a30bdcb37dadcf7a443798e202">FSMC_BWTR1_BUSTURN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade809e856484f40f6e54001fd88c7c80">FSMC_BWTR1_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga8c0dc053a9639673abb045e1d50756fa" id="r_ga8c0dc053a9639673abb045e1d50756fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c0dc053a9639673abb045e1d50756fa">FSMC_BWTR1_BUSTURN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade809e856484f40f6e54001fd88c7c80">FSMC_BWTR1_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gafafcc625222c5be36a617572881d6704" id="r_gafafcc625222c5be36a617572881d6704"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafafcc625222c5be36a617572881d6704">FSMC_BWTR1_BUSTURN_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade809e856484f40f6e54001fd88c7c80">FSMC_BWTR1_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gafd830ff4d12444139479977ee13c730b" id="r_gafd830ff4d12444139479977ee13c730b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd830ff4d12444139479977ee13c730b">FSMC_BWTR1_BUSTURN_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade809e856484f40f6e54001fd88c7c80">FSMC_BWTR1_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga1339ee30e40045b01377267cdcdf2e42" id="r_ga1339ee30e40045b01377267cdcdf2e42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1339ee30e40045b01377267cdcdf2e42">FSMC_BWTR1_ACCMOD_Pos</a>   (28U)</td></tr>
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<tr class="memitem:gaeb84768b1b7f99be132fd7fabf109710" id="r_gaeb84768b1b7f99be132fd7fabf109710"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb84768b1b7f99be132fd7fabf109710">FSMC_BWTR1_ACCMOD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1339ee30e40045b01377267cdcdf2e42">FSMC_BWTR1_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:gaa676b8e4f48602c27ea8edab61ce5db0" id="r_gaa676b8e4f48602c27ea8edab61ce5db0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa676b8e4f48602c27ea8edab61ce5db0">FSMC_BWTR1_ACCMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb84768b1b7f99be132fd7fabf109710">FSMC_BWTR1_ACCMOD_Msk</a></td></tr>
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<tr class="separator:gaa676b8e4f48602c27ea8edab61ce5db0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae87cae14e6bb4403b420fc9e4084d6e2" id="r_gae87cae14e6bb4403b420fc9e4084d6e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae87cae14e6bb4403b420fc9e4084d6e2">FSMC_BWTR1_ACCMOD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1339ee30e40045b01377267cdcdf2e42">FSMC_BWTR1_ACCMOD_Pos</a>)</td></tr>
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<tr class="separator:gae87cae14e6bb4403b420fc9e4084d6e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac0cddde5db2e0bb09f1c8938afd6ac98" id="r_gac0cddde5db2e0bb09f1c8938afd6ac98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0cddde5db2e0bb09f1c8938afd6ac98">FSMC_BWTR1_ACCMOD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1339ee30e40045b01377267cdcdf2e42">FSMC_BWTR1_ACCMOD_Pos</a>)</td></tr>
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<tr class="separator:gac0cddde5db2e0bb09f1c8938afd6ac98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf19233630fc32a605d2a4898cb93a7b" id="r_gadf19233630fc32a605d2a4898cb93a7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf19233630fc32a605d2a4898cb93a7b">FSMC_BWTR2_ADDSET_Pos</a>   (0U)</td></tr>
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<tr class="separator:gadf19233630fc32a605d2a4898cb93a7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga124ca65a19ddd2bf11faba48c98f3e84" id="r_ga124ca65a19ddd2bf11faba48c98f3e84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga124ca65a19ddd2bf11faba48c98f3e84">FSMC_BWTR2_ADDSET_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf19233630fc32a605d2a4898cb93a7b">FSMC_BWTR2_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga7b6553bd9ad305aa42341e08b1736260" id="r_ga7b6553bd9ad305aa42341e08b1736260"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b6553bd9ad305aa42341e08b1736260">FSMC_BWTR2_ADDSET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga124ca65a19ddd2bf11faba48c98f3e84">FSMC_BWTR2_ADDSET_Msk</a></td></tr>
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<tr class="separator:ga7b6553bd9ad305aa42341e08b1736260"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga593fe1987e8c6052cdb992e629f1d059" id="r_ga593fe1987e8c6052cdb992e629f1d059"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga593fe1987e8c6052cdb992e629f1d059">FSMC_BWTR2_ADDSET_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf19233630fc32a605d2a4898cb93a7b">FSMC_BWTR2_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga6dc23a2314a44b6ad9f293716f0c8a11" id="r_ga6dc23a2314a44b6ad9f293716f0c8a11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6dc23a2314a44b6ad9f293716f0c8a11">FSMC_BWTR2_ADDSET_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf19233630fc32a605d2a4898cb93a7b">FSMC_BWTR2_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga1e9c799b36f45cad86a3f98d262baa6d" id="r_ga1e9c799b36f45cad86a3f98d262baa6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e9c799b36f45cad86a3f98d262baa6d">FSMC_BWTR2_ADDSET_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf19233630fc32a605d2a4898cb93a7b">FSMC_BWTR2_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga95abc246eb528275d894346c0665e930" id="r_ga95abc246eb528275d894346c0665e930"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95abc246eb528275d894346c0665e930">FSMC_BWTR2_ADDSET_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf19233630fc32a605d2a4898cb93a7b">FSMC_BWTR2_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga71f8b02d43d99e0de2b34cc269d85d60" id="r_ga71f8b02d43d99e0de2b34cc269d85d60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71f8b02d43d99e0de2b34cc269d85d60">FSMC_BWTR2_ADDHLD_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga5a432338fb1c54a6d09a5646556dc1a0" id="r_ga5a432338fb1c54a6d09a5646556dc1a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a432338fb1c54a6d09a5646556dc1a0">FSMC_BWTR2_ADDHLD_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71f8b02d43d99e0de2b34cc269d85d60">FSMC_BWTR2_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gae879db1879650f99b1c75635884bda17" id="r_gae879db1879650f99b1c75635884bda17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae879db1879650f99b1c75635884bda17">FSMC_BWTR2_ADDHLD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a432338fb1c54a6d09a5646556dc1a0">FSMC_BWTR2_ADDHLD_Msk</a></td></tr>
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<tr class="memitem:gaf5826c5d5c544cd59210c071358fb8e9" id="r_gaf5826c5d5c544cd59210c071358fb8e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5826c5d5c544cd59210c071358fb8e9">FSMC_BWTR2_ADDHLD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71f8b02d43d99e0de2b34cc269d85d60">FSMC_BWTR2_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga258acf47f7706a1cd0b0a914e63cbe17" id="r_ga258acf47f7706a1cd0b0a914e63cbe17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga258acf47f7706a1cd0b0a914e63cbe17">FSMC_BWTR2_ADDHLD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71f8b02d43d99e0de2b34cc269d85d60">FSMC_BWTR2_ADDHLD_Pos</a>)</td></tr>
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<tr class="separator:ga258acf47f7706a1cd0b0a914e63cbe17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39f1a9ccc80d1218935936539a000b84" id="r_ga39f1a9ccc80d1218935936539a000b84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39f1a9ccc80d1218935936539a000b84">FSMC_BWTR2_ADDHLD_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71f8b02d43d99e0de2b34cc269d85d60">FSMC_BWTR2_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga81de376a21fc25a7e1c31db341dfcd3f" id="r_ga81de376a21fc25a7e1c31db341dfcd3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81de376a21fc25a7e1c31db341dfcd3f">FSMC_BWTR2_ADDHLD_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71f8b02d43d99e0de2b34cc269d85d60">FSMC_BWTR2_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:ga4f1969ba212c34f57a767b158e6f80ed" id="r_ga4f1969ba212c34f57a767b158e6f80ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed">FSMC_BWTR2_DATAST_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga1a8e67d5ff1e02c745ce4db92a251e7f" id="r_ga1a8e67d5ff1e02c745ce4db92a251e7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a8e67d5ff1e02c745ce4db92a251e7f">FSMC_BWTR2_DATAST_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed">FSMC_BWTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gab280652524006fbb3820597112136f14" id="r_gab280652524006fbb3820597112136f14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab280652524006fbb3820597112136f14">FSMC_BWTR2_DATAST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a8e67d5ff1e02c745ce4db92a251e7f">FSMC_BWTR2_DATAST_Msk</a></td></tr>
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<tr class="memitem:ga78a0f0466162848135313296ebf44890" id="r_ga78a0f0466162848135313296ebf44890"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78a0f0466162848135313296ebf44890">FSMC_BWTR2_DATAST_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed">FSMC_BWTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga51e43e17e99141c9009c779cc359323a" id="r_ga51e43e17e99141c9009c779cc359323a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51e43e17e99141c9009c779cc359323a">FSMC_BWTR2_DATAST_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed">FSMC_BWTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga1f8791c2a33f740f905d45e3754e3353" id="r_ga1f8791c2a33f740f905d45e3754e3353"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f8791c2a33f740f905d45e3754e3353">FSMC_BWTR2_DATAST_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed">FSMC_BWTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga8a2a5797dd14b5b89581c5fb08872fae" id="r_ga8a2a5797dd14b5b89581c5fb08872fae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a2a5797dd14b5b89581c5fb08872fae">FSMC_BWTR2_DATAST_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed">FSMC_BWTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga59727cc45244014c0837b63b79787ef8" id="r_ga59727cc45244014c0837b63b79787ef8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59727cc45244014c0837b63b79787ef8">FSMC_BWTR2_DATAST_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed">FSMC_BWTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gad7bb34356cc805ef2354194307e4119c" id="r_gad7bb34356cc805ef2354194307e4119c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7bb34356cc805ef2354194307e4119c">FSMC_BWTR2_DATAST_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed">FSMC_BWTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga348a18f1a4b0c5463a8692a9f12464a9" id="r_ga348a18f1a4b0c5463a8692a9f12464a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga348a18f1a4b0c5463a8692a9f12464a9">FSMC_BWTR2_DATAST_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed">FSMC_BWTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga6497892b70d765d6f54b43351140d9c8" id="r_ga6497892b70d765d6f54b43351140d9c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6497892b70d765d6f54b43351140d9c8">FSMC_BWTR2_DATAST_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed">FSMC_BWTR2_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gaf50bc4030068335c54e73016b0e72d37" id="r_gaf50bc4030068335c54e73016b0e72d37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf50bc4030068335c54e73016b0e72d37">FSMC_BWTR2_BUSTURN_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga02edb530ab2bf59ff2d2c1339177dc5b" id="r_ga02edb530ab2bf59ff2d2c1339177dc5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02edb530ab2bf59ff2d2c1339177dc5b">FSMC_BWTR2_BUSTURN_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf50bc4030068335c54e73016b0e72d37">FSMC_BWTR2_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga46c9ba35109d12ff41e5d40f16911546" id="r_ga46c9ba35109d12ff41e5d40f16911546"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46c9ba35109d12ff41e5d40f16911546">FSMC_BWTR2_BUSTURN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga02edb530ab2bf59ff2d2c1339177dc5b">FSMC_BWTR2_BUSTURN_Msk</a></td></tr>
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<tr class="memitem:gad2e0a32552e1d57efa9ecacb5121a685" id="r_gad2e0a32552e1d57efa9ecacb5121a685"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2e0a32552e1d57efa9ecacb5121a685">FSMC_BWTR2_BUSTURN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf50bc4030068335c54e73016b0e72d37">FSMC_BWTR2_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gaec6ea37fe04083cee9202e3b814095cd" id="r_gaec6ea37fe04083cee9202e3b814095cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec6ea37fe04083cee9202e3b814095cd">FSMC_BWTR2_BUSTURN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf50bc4030068335c54e73016b0e72d37">FSMC_BWTR2_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gaff765b875a7e16a849d6019e1af147f0" id="r_gaff765b875a7e16a849d6019e1af147f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff765b875a7e16a849d6019e1af147f0">FSMC_BWTR2_BUSTURN_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf50bc4030068335c54e73016b0e72d37">FSMC_BWTR2_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga6a0684d050236cdf6c0a1b6e99c523fd" id="r_ga6a0684d050236cdf6c0a1b6e99c523fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a0684d050236cdf6c0a1b6e99c523fd">FSMC_BWTR2_BUSTURN_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf50bc4030068335c54e73016b0e72d37">FSMC_BWTR2_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gab50bf8884bd5bfd9845932225b058333" id="r_gab50bf8884bd5bfd9845932225b058333"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab50bf8884bd5bfd9845932225b058333">FSMC_BWTR2_ACCMOD_Pos</a>   (28U)</td></tr>
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<tr class="memitem:ga2cebbf681a61a82429105f62eff22230" id="r_ga2cebbf681a61a82429105f62eff22230"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cebbf681a61a82429105f62eff22230">FSMC_BWTR2_ACCMOD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab50bf8884bd5bfd9845932225b058333">FSMC_BWTR2_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga320be3e2e266dc25bd02e10787b2ba0d" id="r_ga320be3e2e266dc25bd02e10787b2ba0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga320be3e2e266dc25bd02e10787b2ba0d">FSMC_BWTR2_ACCMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cebbf681a61a82429105f62eff22230">FSMC_BWTR2_ACCMOD_Msk</a></td></tr>
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<tr class="memitem:gaabe5419d99a7ad4d4eb761c82077d958" id="r_gaabe5419d99a7ad4d4eb761c82077d958"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabe5419d99a7ad4d4eb761c82077d958">FSMC_BWTR2_ACCMOD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab50bf8884bd5bfd9845932225b058333">FSMC_BWTR2_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:gab6cdd284ad94abfef0f24fcb813b4558" id="r_gab6cdd284ad94abfef0f24fcb813b4558"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6cdd284ad94abfef0f24fcb813b4558">FSMC_BWTR2_ACCMOD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab50bf8884bd5bfd9845932225b058333">FSMC_BWTR2_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga7e8110634778086f551394937f738ff9" id="r_ga7e8110634778086f551394937f738ff9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8110634778086f551394937f738ff9">FSMC_BWTR3_ADDSET_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gafcc45a7e8a398c8932cd545fb3ed10a6" id="r_gafcc45a7e8a398c8932cd545fb3ed10a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcc45a7e8a398c8932cd545fb3ed10a6">FSMC_BWTR3_ADDSET_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8110634778086f551394937f738ff9">FSMC_BWTR3_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga455ba53d0f18173b0694d71757a084ff" id="r_ga455ba53d0f18173b0694d71757a084ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga455ba53d0f18173b0694d71757a084ff">FSMC_BWTR3_ADDSET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafcc45a7e8a398c8932cd545fb3ed10a6">FSMC_BWTR3_ADDSET_Msk</a></td></tr>
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<tr class="memitem:ga9dddd5ba924b56867c9cb39484ef498d" id="r_ga9dddd5ba924b56867c9cb39484ef498d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9dddd5ba924b56867c9cb39484ef498d">FSMC_BWTR3_ADDSET_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8110634778086f551394937f738ff9">FSMC_BWTR3_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gacd242d768da1f9ab4304e91e5dabb5a9" id="r_gacd242d768da1f9ab4304e91e5dabb5a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd242d768da1f9ab4304e91e5dabb5a9">FSMC_BWTR3_ADDSET_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8110634778086f551394937f738ff9">FSMC_BWTR3_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gaef99967dc66814cf5d732365c40daebb" id="r_gaef99967dc66814cf5d732365c40daebb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef99967dc66814cf5d732365c40daebb">FSMC_BWTR3_ADDSET_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8110634778086f551394937f738ff9">FSMC_BWTR3_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:ga471ebb2d47fb951340df6ba22b40a788" id="r_ga471ebb2d47fb951340df6ba22b40a788"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga471ebb2d47fb951340df6ba22b40a788">FSMC_BWTR3_ADDSET_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8110634778086f551394937f738ff9">FSMC_BWTR3_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gae752c10ea876415cf0b54aca8c7d77e7" id="r_gae752c10ea876415cf0b54aca8c7d77e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae752c10ea876415cf0b54aca8c7d77e7">FSMC_BWTR3_ADDHLD_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga1025758662868a34da456a8f3c9600dd" id="r_ga1025758662868a34da456a8f3c9600dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1025758662868a34da456a8f3c9600dd">FSMC_BWTR3_ADDHLD_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae752c10ea876415cf0b54aca8c7d77e7">FSMC_BWTR3_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gae3d031a0d71677932a68639ba88bd13e" id="r_gae3d031a0d71677932a68639ba88bd13e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3d031a0d71677932a68639ba88bd13e">FSMC_BWTR3_ADDHLD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1025758662868a34da456a8f3c9600dd">FSMC_BWTR3_ADDHLD_Msk</a></td></tr>
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<tr class="memitem:ga5b3948c407a5a4be6a21cccad0a8d12d" id="r_ga5b3948c407a5a4be6a21cccad0a8d12d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b3948c407a5a4be6a21cccad0a8d12d">FSMC_BWTR3_ADDHLD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae752c10ea876415cf0b54aca8c7d77e7">FSMC_BWTR3_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gaea21d05228f7771c6306726af5da5a4a" id="r_gaea21d05228f7771c6306726af5da5a4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea21d05228f7771c6306726af5da5a4a">FSMC_BWTR3_ADDHLD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae752c10ea876415cf0b54aca8c7d77e7">FSMC_BWTR3_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gaa574b3a1efe581d195789dcc8bba01f8" id="r_gaa574b3a1efe581d195789dcc8bba01f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa574b3a1efe581d195789dcc8bba01f8">FSMC_BWTR3_ADDHLD_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae752c10ea876415cf0b54aca8c7d77e7">FSMC_BWTR3_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gaae8216cf865785468af58dbce0002a7c" id="r_gaae8216cf865785468af58dbce0002a7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae8216cf865785468af58dbce0002a7c">FSMC_BWTR3_ADDHLD_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae752c10ea876415cf0b54aca8c7d77e7">FSMC_BWTR3_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gadfc2a85d6970397944903ed17252a68d" id="r_gadfc2a85d6970397944903ed17252a68d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d">FSMC_BWTR3_DATAST_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga51d5ed2f485b7b92825e4677e11e095a" id="r_ga51d5ed2f485b7b92825e4677e11e095a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51d5ed2f485b7b92825e4677e11e095a">FSMC_BWTR3_DATAST_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d">FSMC_BWTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gae93d9fee8a67491918526019b439a00f" id="r_gae93d9fee8a67491918526019b439a00f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae93d9fee8a67491918526019b439a00f">FSMC_BWTR3_DATAST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga51d5ed2f485b7b92825e4677e11e095a">FSMC_BWTR3_DATAST_Msk</a></td></tr>
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<tr class="memitem:gaf1ec40c6360faeb133cb224a6789bb51" id="r_gaf1ec40c6360faeb133cb224a6789bb51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1ec40c6360faeb133cb224a6789bb51">FSMC_BWTR3_DATAST_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d">FSMC_BWTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gacaf23316e44d731620f0cbde29ae9a93" id="r_gacaf23316e44d731620f0cbde29ae9a93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacaf23316e44d731620f0cbde29ae9a93">FSMC_BWTR3_DATAST_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d">FSMC_BWTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga31686e755ef0f98078d96c08891cf8f4" id="r_ga31686e755ef0f98078d96c08891cf8f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31686e755ef0f98078d96c08891cf8f4">FSMC_BWTR3_DATAST_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d">FSMC_BWTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga5a291f74abf021a7fe66ce8afd714c39" id="r_ga5a291f74abf021a7fe66ce8afd714c39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a291f74abf021a7fe66ce8afd714c39">FSMC_BWTR3_DATAST_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d">FSMC_BWTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:gacd5b6e11c52314eb07772d72353002fa" id="r_gacd5b6e11c52314eb07772d72353002fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd5b6e11c52314eb07772d72353002fa">FSMC_BWTR3_DATAST_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d">FSMC_BWTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga590322c15eb3fb579edec41fd4a86ea5" id="r_ga590322c15eb3fb579edec41fd4a86ea5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga590322c15eb3fb579edec41fd4a86ea5">FSMC_BWTR3_DATAST_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d">FSMC_BWTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga3aec6604821cd38fafbceeaf81556d63" id="r_ga3aec6604821cd38fafbceeaf81556d63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3aec6604821cd38fafbceeaf81556d63">FSMC_BWTR3_DATAST_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d">FSMC_BWTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga79e7035f0bb60e6082f699ee98d2ffc2" id="r_ga79e7035f0bb60e6082f699ee98d2ffc2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79e7035f0bb60e6082f699ee98d2ffc2">FSMC_BWTR3_DATAST_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d">FSMC_BWTR3_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga5b60d7fbc787a9d6df78fbc5fea4c206" id="r_ga5b60d7fbc787a9d6df78fbc5fea4c206"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b60d7fbc787a9d6df78fbc5fea4c206">FSMC_BWTR3_BUSTURN_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga4922c75c6b3c2baf134ad5119a97a098" id="r_ga4922c75c6b3c2baf134ad5119a97a098"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4922c75c6b3c2baf134ad5119a97a098">FSMC_BWTR3_BUSTURN_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b60d7fbc787a9d6df78fbc5fea4c206">FSMC_BWTR3_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga333004366913e1c938f2efb57c259c39" id="r_ga333004366913e1c938f2efb57c259c39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga333004366913e1c938f2efb57c259c39">FSMC_BWTR3_BUSTURN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4922c75c6b3c2baf134ad5119a97a098">FSMC_BWTR3_BUSTURN_Msk</a></td></tr>
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<tr class="memitem:ga966a4bb7d0878efc320d50457c26749d" id="r_ga966a4bb7d0878efc320d50457c26749d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga966a4bb7d0878efc320d50457c26749d">FSMC_BWTR3_BUSTURN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b60d7fbc787a9d6df78fbc5fea4c206">FSMC_BWTR3_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga44b560ff9aaa44e2f4a18ac548c8d65e" id="r_ga44b560ff9aaa44e2f4a18ac548c8d65e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44b560ff9aaa44e2f4a18ac548c8d65e">FSMC_BWTR3_BUSTURN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b60d7fbc787a9d6df78fbc5fea4c206">FSMC_BWTR3_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga89448c3668da87fe261d575166325f3d" id="r_ga89448c3668da87fe261d575166325f3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89448c3668da87fe261d575166325f3d">FSMC_BWTR3_BUSTURN_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b60d7fbc787a9d6df78fbc5fea4c206">FSMC_BWTR3_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga86e615ef161c836eb338cc410f474cf6" id="r_ga86e615ef161c836eb338cc410f474cf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86e615ef161c836eb338cc410f474cf6">FSMC_BWTR3_BUSTURN_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b60d7fbc787a9d6df78fbc5fea4c206">FSMC_BWTR3_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gacad6fb10201c4c9c3e022b8551143f1f" id="r_gacad6fb10201c4c9c3e022b8551143f1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacad6fb10201c4c9c3e022b8551143f1f">FSMC_BWTR3_ACCMOD_Pos</a>   (28U)</td></tr>
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<tr class="memitem:gafcc2c37152b55b3c8c5e178778567261" id="r_gafcc2c37152b55b3c8c5e178778567261"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcc2c37152b55b3c8c5e178778567261">FSMC_BWTR3_ACCMOD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacad6fb10201c4c9c3e022b8551143f1f">FSMC_BWTR3_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:gaa32a792c0c93d854a90bfbc36fa1329b" id="r_gaa32a792c0c93d854a90bfbc36fa1329b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa32a792c0c93d854a90bfbc36fa1329b">FSMC_BWTR3_ACCMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafcc2c37152b55b3c8c5e178778567261">FSMC_BWTR3_ACCMOD_Msk</a></td></tr>
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<tr class="memitem:ga64d4e414ea73b47e07364e1a121af6a4" id="r_ga64d4e414ea73b47e07364e1a121af6a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64d4e414ea73b47e07364e1a121af6a4">FSMC_BWTR3_ACCMOD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacad6fb10201c4c9c3e022b8551143f1f">FSMC_BWTR3_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:gada733b2bda718299345fd0191b25b49f" id="r_gada733b2bda718299345fd0191b25b49f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada733b2bda718299345fd0191b25b49f">FSMC_BWTR3_ACCMOD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacad6fb10201c4c9c3e022b8551143f1f">FSMC_BWTR3_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga46344b3ec4032b5a520833b6ba553b8f" id="r_ga46344b3ec4032b5a520833b6ba553b8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46344b3ec4032b5a520833b6ba553b8f">FSMC_BWTR4_ADDSET_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga46344b3ec4032b5a520833b6ba553b8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac9acf4808b842bc735479c137aceb01" id="r_gaac9acf4808b842bc735479c137aceb01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac9acf4808b842bc735479c137aceb01">FSMC_BWTR4_ADDSET_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46344b3ec4032b5a520833b6ba553b8f">FSMC_BWTR4_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gaa8c3c14faf87768beced4e297edc7bfd" id="r_gaa8c3c14faf87768beced4e297edc7bfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8c3c14faf87768beced4e297edc7bfd">FSMC_BWTR4_ADDSET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac9acf4808b842bc735479c137aceb01">FSMC_BWTR4_ADDSET_Msk</a></td></tr>
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<tr class="memitem:ga65ba73495f6192e409cc00f3e26e27e0" id="r_ga65ba73495f6192e409cc00f3e26e27e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65ba73495f6192e409cc00f3e26e27e0">FSMC_BWTR4_ADDSET_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46344b3ec4032b5a520833b6ba553b8f">FSMC_BWTR4_ADDSET_Pos</a>)</td></tr>
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<tr class="separator:ga65ba73495f6192e409cc00f3e26e27e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cc9fa3c1ceae0724f5005bb1e101775" id="r_ga3cc9fa3c1ceae0724f5005bb1e101775"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cc9fa3c1ceae0724f5005bb1e101775">FSMC_BWTR4_ADDSET_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46344b3ec4032b5a520833b6ba553b8f">FSMC_BWTR4_ADDSET_Pos</a>)</td></tr>
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<tr class="separator:ga3cc9fa3c1ceae0724f5005bb1e101775"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2007941f4869504bfef23edbcc18bfa" id="r_gad2007941f4869504bfef23edbcc18bfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2007941f4869504bfef23edbcc18bfa">FSMC_BWTR4_ADDSET_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46344b3ec4032b5a520833b6ba553b8f">FSMC_BWTR4_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gabcde23639f64241d95b02f5b950ef3cc" id="r_gabcde23639f64241d95b02f5b950ef3cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabcde23639f64241d95b02f5b950ef3cc">FSMC_BWTR4_ADDSET_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46344b3ec4032b5a520833b6ba553b8f">FSMC_BWTR4_ADDSET_Pos</a>)</td></tr>
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<tr class="memitem:gac40aa70101334a56d6ce4cb52d9a64bc" id="r_gac40aa70101334a56d6ce4cb52d9a64bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac40aa70101334a56d6ce4cb52d9a64bc">FSMC_BWTR4_ADDHLD_Pos</a>   (4U)</td></tr>
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<tr class="separator:gac40aa70101334a56d6ce4cb52d9a64bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7cf1485c80e4326e49ab8dc889e5537" id="r_gab7cf1485c80e4326e49ab8dc889e5537"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7cf1485c80e4326e49ab8dc889e5537">FSMC_BWTR4_ADDHLD_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac40aa70101334a56d6ce4cb52d9a64bc">FSMC_BWTR4_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gaafe1198e70d843c883260d354b7ce7b5" id="r_gaafe1198e70d843c883260d354b7ce7b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafe1198e70d843c883260d354b7ce7b5">FSMC_BWTR4_ADDHLD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab7cf1485c80e4326e49ab8dc889e5537">FSMC_BWTR4_ADDHLD_Msk</a></td></tr>
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<tr class="memitem:gac62786f538820baa3f0f8edb17ef1b74" id="r_gac62786f538820baa3f0f8edb17ef1b74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac62786f538820baa3f0f8edb17ef1b74">FSMC_BWTR4_ADDHLD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac40aa70101334a56d6ce4cb52d9a64bc">FSMC_BWTR4_ADDHLD_Pos</a>)</td></tr>
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<tr class="separator:gac62786f538820baa3f0f8edb17ef1b74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa69aa2d9cafe8f952721c88083c8a94e" id="r_gaa69aa2d9cafe8f952721c88083c8a94e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa69aa2d9cafe8f952721c88083c8a94e">FSMC_BWTR4_ADDHLD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac40aa70101334a56d6ce4cb52d9a64bc">FSMC_BWTR4_ADDHLD_Pos</a>)</td></tr>
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<tr class="separator:gaa69aa2d9cafe8f952721c88083c8a94e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c6d991498c385991b461832fb093399" id="r_ga4c6d991498c385991b461832fb093399"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c6d991498c385991b461832fb093399">FSMC_BWTR4_ADDHLD_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac40aa70101334a56d6ce4cb52d9a64bc">FSMC_BWTR4_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gac744bdeb5b9ae048b1fa1a07ce9ce9d1" id="r_gac744bdeb5b9ae048b1fa1a07ce9ce9d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac744bdeb5b9ae048b1fa1a07ce9ce9d1">FSMC_BWTR4_ADDHLD_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac40aa70101334a56d6ce4cb52d9a64bc">FSMC_BWTR4_ADDHLD_Pos</a>)</td></tr>
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<tr class="memitem:gab82ad4f36968e5609b1adc15bc1d0dd5" id="r_gab82ad4f36968e5609b1adc15bc1d0dd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab82ad4f36968e5609b1adc15bc1d0dd5">FSMC_BWTR4_DATAST_Pos</a>   (8U)</td></tr>
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<tr class="separator:gab82ad4f36968e5609b1adc15bc1d0dd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae370408fcf34c2db09d389102c249b1e" id="r_gae370408fcf34c2db09d389102c249b1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae370408fcf34c2db09d389102c249b1e">FSMC_BWTR4_DATAST_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab82ad4f36968e5609b1adc15bc1d0dd5">FSMC_BWTR4_DATAST_Pos</a>)</td></tr>
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<tr class="memitem:ga6656c89aac87fc226c0e80f8f753abeb" id="r_ga6656c89aac87fc226c0e80f8f753abeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6656c89aac87fc226c0e80f8f753abeb">FSMC_BWTR4_DATAST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae370408fcf34c2db09d389102c249b1e">FSMC_BWTR4_DATAST_Msk</a></td></tr>
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<tr class="separator:ga6656c89aac87fc226c0e80f8f753abeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5636aaec144530e1c46e819b62c95f09" id="r_ga5636aaec144530e1c46e819b62c95f09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5636aaec144530e1c46e819b62c95f09">FSMC_BWTR4_DATAST_0</a>   0x00000100U</td></tr>
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<tr class="separator:ga5636aaec144530e1c46e819b62c95f09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19eb9fccff444a00caf75b9d20a143ed" id="r_ga19eb9fccff444a00caf75b9d20a143ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19eb9fccff444a00caf75b9d20a143ed">FSMC_BWTR4_DATAST_1</a>   0x00000200U</td></tr>
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<tr class="separator:ga19eb9fccff444a00caf75b9d20a143ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa40f9fa60ddb69fdcdcdface743f2c26" id="r_gaa40f9fa60ddb69fdcdcdface743f2c26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa40f9fa60ddb69fdcdcdface743f2c26">FSMC_BWTR4_DATAST_2</a>   0x00000400U</td></tr>
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<tr class="separator:gaa40f9fa60ddb69fdcdcdface743f2c26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa173c5ff9a7d316cd67897f8e36dbf5" id="r_gafa173c5ff9a7d316cd67897f8e36dbf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa173c5ff9a7d316cd67897f8e36dbf5">FSMC_BWTR4_DATAST_3</a>   0x00000800U</td></tr>
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<tr class="separator:gafa173c5ff9a7d316cd67897f8e36dbf5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c8dde48be5fa0ea0e920d72e7b43ad0" id="r_ga7c8dde48be5fa0ea0e920d72e7b43ad0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c8dde48be5fa0ea0e920d72e7b43ad0">FSMC_BWTR4_DATAST_4</a>   0x00001000U</td></tr>
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<tr class="separator:ga7c8dde48be5fa0ea0e920d72e7b43ad0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ff7e92fad8d55c205ee1225868c54a4" id="r_ga2ff7e92fad8d55c205ee1225868c54a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ff7e92fad8d55c205ee1225868c54a4">FSMC_BWTR4_DATAST_5</a>   0x00002000U</td></tr>
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<tr class="separator:ga2ff7e92fad8d55c205ee1225868c54a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2dbfd952e906c67ec6bb813d220638f9" id="r_ga2dbfd952e906c67ec6bb813d220638f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dbfd952e906c67ec6bb813d220638f9">FSMC_BWTR4_DATAST_6</a>   0x00004000U</td></tr>
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<tr class="separator:ga2dbfd952e906c67ec6bb813d220638f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67a7e379e49efcdb4a42ed45eb20c620" id="r_ga67a7e379e49efcdb4a42ed45eb20c620"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67a7e379e49efcdb4a42ed45eb20c620">FSMC_BWTR4_DATAST_7</a>   0x00008000U</td></tr>
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<tr class="separator:ga67a7e379e49efcdb4a42ed45eb20c620"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5ff326880c026bb2a70e39e7ce48074" id="r_gae5ff326880c026bb2a70e39e7ce48074"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5ff326880c026bb2a70e39e7ce48074">FSMC_BWTR4_BUSTURN_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga152a5383e408f7ec2e000fcf40f335df" id="r_ga152a5383e408f7ec2e000fcf40f335df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga152a5383e408f7ec2e000fcf40f335df">FSMC_BWTR4_BUSTURN_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5ff326880c026bb2a70e39e7ce48074">FSMC_BWTR4_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga2251ad4a30e8fd743b5ee0cf1f64b479" id="r_ga2251ad4a30e8fd743b5ee0cf1f64b479"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2251ad4a30e8fd743b5ee0cf1f64b479">FSMC_BWTR4_BUSTURN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga152a5383e408f7ec2e000fcf40f335df">FSMC_BWTR4_BUSTURN_Msk</a></td></tr>
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<tr class="separator:ga2251ad4a30e8fd743b5ee0cf1f64b479"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc959ee76e0bf42eca48b4cc8ddb5bf6" id="r_gacc959ee76e0bf42eca48b4cc8ddb5bf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc959ee76e0bf42eca48b4cc8ddb5bf6">FSMC_BWTR4_BUSTURN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5ff326880c026bb2a70e39e7ce48074">FSMC_BWTR4_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga1e77325faba8acb512b97a5bfac186df" id="r_ga1e77325faba8acb512b97a5bfac186df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e77325faba8acb512b97a5bfac186df">FSMC_BWTR4_BUSTURN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5ff326880c026bb2a70e39e7ce48074">FSMC_BWTR4_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:gabc92938093fc0c4da4b3e82b0ac0f440" id="r_gabc92938093fc0c4da4b3e82b0ac0f440"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc92938093fc0c4da4b3e82b0ac0f440">FSMC_BWTR4_BUSTURN_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5ff326880c026bb2a70e39e7ce48074">FSMC_BWTR4_BUSTURN_Pos</a>)</td></tr>
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<tr class="memitem:ga1c239a600bcaa8addc11ef97c5c6248c" id="r_ga1c239a600bcaa8addc11ef97c5c6248c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c239a600bcaa8addc11ef97c5c6248c">FSMC_BWTR4_BUSTURN_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5ff326880c026bb2a70e39e7ce48074">FSMC_BWTR4_BUSTURN_Pos</a>)</td></tr>
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<tr class="separator:ga1c239a600bcaa8addc11ef97c5c6248c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fc1deea073ae82799fcda8073bdeccb" id="r_ga8fc1deea073ae82799fcda8073bdeccb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fc1deea073ae82799fcda8073bdeccb">FSMC_BWTR4_ACCMOD_Pos</a>   (28U)</td></tr>
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<tr class="memitem:gab9daae3a3b8aaafa7afc2069debd8d14" id="r_gab9daae3a3b8aaafa7afc2069debd8d14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9daae3a3b8aaafa7afc2069debd8d14">FSMC_BWTR4_ACCMOD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fc1deea073ae82799fcda8073bdeccb">FSMC_BWTR4_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:ga1d13f46a945d5daf6ec339781d3926a9" id="r_ga1d13f46a945d5daf6ec339781d3926a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d13f46a945d5daf6ec339781d3926a9">FSMC_BWTR4_ACCMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9daae3a3b8aaafa7afc2069debd8d14">FSMC_BWTR4_ACCMOD_Msk</a></td></tr>
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<tr class="memitem:ga5e30f51c68b4ac4f9efee2cd5a45943c" id="r_ga5e30f51c68b4ac4f9efee2cd5a45943c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e30f51c68b4ac4f9efee2cd5a45943c">FSMC_BWTR4_ACCMOD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fc1deea073ae82799fcda8073bdeccb">FSMC_BWTR4_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:gaf7ba26fb09f035addbe1e4c3b0d093c9" id="r_gaf7ba26fb09f035addbe1e4c3b0d093c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7ba26fb09f035addbe1e4c3b0d093c9">FSMC_BWTR4_ACCMOD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fc1deea073ae82799fcda8073bdeccb">FSMC_BWTR4_ACCMOD_Pos</a>)</td></tr>
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<tr class="memitem:gaaa09c72741deafe6d443fd0f25299480" id="r_gaaa09c72741deafe6d443fd0f25299480"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa09c72741deafe6d443fd0f25299480">FSMC_PCR2_PWAITEN_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga427ff4cc50d76345ee3d8885f7f09863" id="r_ga427ff4cc50d76345ee3d8885f7f09863"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga427ff4cc50d76345ee3d8885f7f09863">FSMC_PCR2_PWAITEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa09c72741deafe6d443fd0f25299480">FSMC_PCR2_PWAITEN_Pos</a>)</td></tr>
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<tr class="memitem:ga26f3ae80c9bbede6929c20004804476d" id="r_ga26f3ae80c9bbede6929c20004804476d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26f3ae80c9bbede6929c20004804476d">FSMC_PCR2_PWAITEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga427ff4cc50d76345ee3d8885f7f09863">FSMC_PCR2_PWAITEN_Msk</a></td></tr>
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<tr class="memitem:gaa44a48baf82f718ea68a8f49f41a7197" id="r_gaa44a48baf82f718ea68a8f49f41a7197"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa44a48baf82f718ea68a8f49f41a7197">FSMC_PCR2_PBKEN_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaa44a48baf82f718ea68a8f49f41a7197"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23ca7d9404f38c74f54c617779417247" id="r_ga23ca7d9404f38c74f54c617779417247"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23ca7d9404f38c74f54c617779417247">FSMC_PCR2_PBKEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa44a48baf82f718ea68a8f49f41a7197">FSMC_PCR2_PBKEN_Pos</a>)</td></tr>
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<tr class="memitem:ga2a2bfd8de14f8c726439ba8f494b38a1" id="r_ga2a2bfd8de14f8c726439ba8f494b38a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a2bfd8de14f8c726439ba8f494b38a1">FSMC_PCR2_PBKEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga23ca7d9404f38c74f54c617779417247">FSMC_PCR2_PBKEN_Msk</a></td></tr>
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<tr class="memitem:ga56ca1be84472397c7e7c0e72e45f69c9" id="r_ga56ca1be84472397c7e7c0e72e45f69c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56ca1be84472397c7e7c0e72e45f69c9">FSMC_PCR2_PTYP_Pos</a>   (3U)</td></tr>
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<tr class="memitem:gafcf702c34178ab9c91c1e5e31c5b6b8f" id="r_gafcf702c34178ab9c91c1e5e31c5b6b8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcf702c34178ab9c91c1e5e31c5b6b8f">FSMC_PCR2_PTYP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga56ca1be84472397c7e7c0e72e45f69c9">FSMC_PCR2_PTYP_Pos</a>)</td></tr>
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<tr class="memitem:ga175ab8f61bbc0bb5692fb62691db1ce3" id="r_ga175ab8f61bbc0bb5692fb62691db1ce3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga175ab8f61bbc0bb5692fb62691db1ce3">FSMC_PCR2_PTYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafcf702c34178ab9c91c1e5e31c5b6b8f">FSMC_PCR2_PTYP_Msk</a></td></tr>
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<tr class="memitem:ga786bd3b30640e57e85ccd8faeb812c73" id="r_ga786bd3b30640e57e85ccd8faeb812c73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga786bd3b30640e57e85ccd8faeb812c73">FSMC_PCR2_PWID_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga786bd3b30640e57e85ccd8faeb812c73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeaeb0bbbb281a4cc378e1ac5c0af401b" id="r_gaeaeb0bbbb281a4cc378e1ac5c0af401b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeaeb0bbbb281a4cc378e1ac5c0af401b">FSMC_PCR2_PWID_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga786bd3b30640e57e85ccd8faeb812c73">FSMC_PCR2_PWID_Pos</a>)</td></tr>
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<tr class="memitem:ga656155275dc1c2f690687d07717e017a" id="r_ga656155275dc1c2f690687d07717e017a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga656155275dc1c2f690687d07717e017a">FSMC_PCR2_PWID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaeb0bbbb281a4cc378e1ac5c0af401b">FSMC_PCR2_PWID_Msk</a></td></tr>
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<tr class="memitem:gae36f67be67a473c318fa937246c6de17" id="r_gae36f67be67a473c318fa937246c6de17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae36f67be67a473c318fa937246c6de17">FSMC_PCR2_PWID_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga786bd3b30640e57e85ccd8faeb812c73">FSMC_PCR2_PWID_Pos</a>)</td></tr>
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<tr class="memitem:ga6180d3899a37f7e518b1e4b8bf935baa" id="r_ga6180d3899a37f7e518b1e4b8bf935baa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6180d3899a37f7e518b1e4b8bf935baa">FSMC_PCR2_PWID_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga786bd3b30640e57e85ccd8faeb812c73">FSMC_PCR2_PWID_Pos</a>)</td></tr>
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<tr class="memitem:ga7ca16b5cf800c2fb594a8a06fa0ea883" id="r_ga7ca16b5cf800c2fb594a8a06fa0ea883"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ca16b5cf800c2fb594a8a06fa0ea883">FSMC_PCR2_ECCEN_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga7ca16b5cf800c2fb594a8a06fa0ea883"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga050ab1ee23d46eb34ed79f22bde35200" id="r_ga050ab1ee23d46eb34ed79f22bde35200"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga050ab1ee23d46eb34ed79f22bde35200">FSMC_PCR2_ECCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ca16b5cf800c2fb594a8a06fa0ea883">FSMC_PCR2_ECCEN_Pos</a>)</td></tr>
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<tr class="separator:ga050ab1ee23d46eb34ed79f22bde35200"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa528d578aec8bc0f77a2550d4e48438" id="r_gafa528d578aec8bc0f77a2550d4e48438"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa528d578aec8bc0f77a2550d4e48438">FSMC_PCR2_ECCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga050ab1ee23d46eb34ed79f22bde35200">FSMC_PCR2_ECCEN_Msk</a></td></tr>
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<tr class="memitem:ga6c24b437e7873367aa3db5fe3f9526e5" id="r_ga6c24b437e7873367aa3db5fe3f9526e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c24b437e7873367aa3db5fe3f9526e5">FSMC_PCR2_TCLR_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga6c24b437e7873367aa3db5fe3f9526e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f526b241c14b7292561799c4e824e76" id="r_ga0f526b241c14b7292561799c4e824e76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f526b241c14b7292561799c4e824e76">FSMC_PCR2_TCLR_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c24b437e7873367aa3db5fe3f9526e5">FSMC_PCR2_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:gaa4f2c6c5ed8cd459a0822c35ea9e6800" id="r_gaa4f2c6c5ed8cd459a0822c35ea9e6800"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4f2c6c5ed8cd459a0822c35ea9e6800">FSMC_PCR2_TCLR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f526b241c14b7292561799c4e824e76">FSMC_PCR2_TCLR_Msk</a></td></tr>
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<tr class="memitem:ga1edc7eec1b5a76a851175e5a7caa6c5c" id="r_ga1edc7eec1b5a76a851175e5a7caa6c5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1edc7eec1b5a76a851175e5a7caa6c5c">FSMC_PCR2_TCLR_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c24b437e7873367aa3db5fe3f9526e5">FSMC_PCR2_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:gaf8baae9949bd0f294a698721da24808f" id="r_gaf8baae9949bd0f294a698721da24808f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8baae9949bd0f294a698721da24808f">FSMC_PCR2_TCLR_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c24b437e7873367aa3db5fe3f9526e5">FSMC_PCR2_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:ga01ba36d067efffcfe5ecea3af1411675" id="r_ga01ba36d067efffcfe5ecea3af1411675"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01ba36d067efffcfe5ecea3af1411675">FSMC_PCR2_TCLR_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c24b437e7873367aa3db5fe3f9526e5">FSMC_PCR2_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:ga4999b81ed8783cca5f3b25500183ff9a" id="r_ga4999b81ed8783cca5f3b25500183ff9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4999b81ed8783cca5f3b25500183ff9a">FSMC_PCR2_TCLR_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c24b437e7873367aa3db5fe3f9526e5">FSMC_PCR2_TCLR_Pos</a>)</td></tr>
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<tr class="separator:ga4999b81ed8783cca5f3b25500183ff9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c4fe782dd038165f42f57ebac4721bf" id="r_ga0c4fe782dd038165f42f57ebac4721bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c4fe782dd038165f42f57ebac4721bf">FSMC_PCR2_TAR_Pos</a>   (13U)</td></tr>
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<tr class="memitem:gabb912af6630ca178d706e72bfeafe4e5" id="r_gabb912af6630ca178d706e72bfeafe4e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb912af6630ca178d706e72bfeafe4e5">FSMC_PCR2_TAR_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c4fe782dd038165f42f57ebac4721bf">FSMC_PCR2_TAR_Pos</a>)</td></tr>
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<tr class="memitem:gaa6513b62e23afdbadc4b25697378a0f2" id="r_gaa6513b62e23afdbadc4b25697378a0f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6513b62e23afdbadc4b25697378a0f2">FSMC_PCR2_TAR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabb912af6630ca178d706e72bfeafe4e5">FSMC_PCR2_TAR_Msk</a></td></tr>
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<tr class="memitem:gacd7e456c24f5978e8cb1078c633f0d23" id="r_gacd7e456c24f5978e8cb1078c633f0d23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd7e456c24f5978e8cb1078c633f0d23">FSMC_PCR2_TAR_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c4fe782dd038165f42f57ebac4721bf">FSMC_PCR2_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga8f0b2191750ab21af10f009e1a97ca13" id="r_ga8f0b2191750ab21af10f009e1a97ca13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f0b2191750ab21af10f009e1a97ca13">FSMC_PCR2_TAR_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c4fe782dd038165f42f57ebac4721bf">FSMC_PCR2_TAR_Pos</a>)</td></tr>
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<tr class="separator:ga8f0b2191750ab21af10f009e1a97ca13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3de27b9eb559156b7ed87407206b7a17" id="r_ga3de27b9eb559156b7ed87407206b7a17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3de27b9eb559156b7ed87407206b7a17">FSMC_PCR2_TAR_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c4fe782dd038165f42f57ebac4721bf">FSMC_PCR2_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga1c70f852bb8809e8ea4800a7dd616266" id="r_ga1c70f852bb8809e8ea4800a7dd616266"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c70f852bb8809e8ea4800a7dd616266">FSMC_PCR2_TAR_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c4fe782dd038165f42f57ebac4721bf">FSMC_PCR2_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga252ebef1000455631c4839f64fe943c2" id="r_ga252ebef1000455631c4839f64fe943c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga252ebef1000455631c4839f64fe943c2">FSMC_PCR2_ECCPS_Pos</a>   (17U)</td></tr>
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<tr class="memitem:ga481ae62d08b68ae47e76399a3db6f343" id="r_ga481ae62d08b68ae47e76399a3db6f343"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga481ae62d08b68ae47e76399a3db6f343">FSMC_PCR2_ECCPS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga252ebef1000455631c4839f64fe943c2">FSMC_PCR2_ECCPS_Pos</a>)</td></tr>
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<tr class="memitem:gaf2adbc7b4149193452b69bc55a968cd1" id="r_gaf2adbc7b4149193452b69bc55a968cd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2adbc7b4149193452b69bc55a968cd1">FSMC_PCR2_ECCPS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga481ae62d08b68ae47e76399a3db6f343">FSMC_PCR2_ECCPS_Msk</a></td></tr>
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<tr class="memitem:gae0e06e76b0dd7cc1f6b765b4c3ecfacb" id="r_gae0e06e76b0dd7cc1f6b765b4c3ecfacb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0e06e76b0dd7cc1f6b765b4c3ecfacb">FSMC_PCR2_ECCPS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga252ebef1000455631c4839f64fe943c2">FSMC_PCR2_ECCPS_Pos</a>)</td></tr>
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<tr class="memitem:ga8b947299d05921085b531f12db860f41" id="r_ga8b947299d05921085b531f12db860f41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b947299d05921085b531f12db860f41">FSMC_PCR2_ECCPS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga252ebef1000455631c4839f64fe943c2">FSMC_PCR2_ECCPS_Pos</a>)</td></tr>
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<tr class="separator:ga8b947299d05921085b531f12db860f41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga199db72eae8707aba0b22ff18bd8bcd0" id="r_ga199db72eae8707aba0b22ff18bd8bcd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga199db72eae8707aba0b22ff18bd8bcd0">FSMC_PCR2_ECCPS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga252ebef1000455631c4839f64fe943c2">FSMC_PCR2_ECCPS_Pos</a>)</td></tr>
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<tr class="memitem:ga349eaf51ed38a2cde231d53a0701c961" id="r_ga349eaf51ed38a2cde231d53a0701c961"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga349eaf51ed38a2cde231d53a0701c961">FSMC_PCR3_PWAITEN_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga2a95cabc9c10687663e8d26706a5a012" id="r_ga2a95cabc9c10687663e8d26706a5a012"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a95cabc9c10687663e8d26706a5a012">FSMC_PCR3_PWAITEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga349eaf51ed38a2cde231d53a0701c961">FSMC_PCR3_PWAITEN_Pos</a>)</td></tr>
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<tr class="memitem:gaae3f15324eb8692ddf3f294f358b1d8c" id="r_gaae3f15324eb8692ddf3f294f358b1d8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae3f15324eb8692ddf3f294f358b1d8c">FSMC_PCR3_PWAITEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a95cabc9c10687663e8d26706a5a012">FSMC_PCR3_PWAITEN_Msk</a></td></tr>
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<tr class="separator:gaae3f15324eb8692ddf3f294f358b1d8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ca0936c38ad7fe990f148f58bb1adff" id="r_ga9ca0936c38ad7fe990f148f58bb1adff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ca0936c38ad7fe990f148f58bb1adff">FSMC_PCR3_PBKEN_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga9ca0936c38ad7fe990f148f58bb1adff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad82453ed7e868ba250086608f62fc27c" id="r_gad82453ed7e868ba250086608f62fc27c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad82453ed7e868ba250086608f62fc27c">FSMC_PCR3_PBKEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ca0936c38ad7fe990f148f58bb1adff">FSMC_PCR3_PBKEN_Pos</a>)</td></tr>
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<tr class="memitem:gaac1334587ebb2f313078aab2c2f76cf7" id="r_gaac1334587ebb2f313078aab2c2f76cf7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac1334587ebb2f313078aab2c2f76cf7">FSMC_PCR3_PBKEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad82453ed7e868ba250086608f62fc27c">FSMC_PCR3_PBKEN_Msk</a></td></tr>
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<tr class="memitem:ga63ea560efa8bf6aabab0f0e552844ca6" id="r_ga63ea560efa8bf6aabab0f0e552844ca6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63ea560efa8bf6aabab0f0e552844ca6">FSMC_PCR3_PTYP_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga63ea560efa8bf6aabab0f0e552844ca6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga698eaa08d2ec1dedfceb558efe404a83" id="r_ga698eaa08d2ec1dedfceb558efe404a83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga698eaa08d2ec1dedfceb558efe404a83">FSMC_PCR3_PTYP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga63ea560efa8bf6aabab0f0e552844ca6">FSMC_PCR3_PTYP_Pos</a>)</td></tr>
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<tr class="memitem:gade562589d0572ba223d2f6df265fe5b8" id="r_gade562589d0572ba223d2f6df265fe5b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade562589d0572ba223d2f6df265fe5b8">FSMC_PCR3_PTYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga698eaa08d2ec1dedfceb558efe404a83">FSMC_PCR3_PTYP_Msk</a></td></tr>
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<tr class="memitem:ga1002927e92f1e32f4430eee6387493c5" id="r_ga1002927e92f1e32f4430eee6387493c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1002927e92f1e32f4430eee6387493c5">FSMC_PCR3_PWID_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga1002927e92f1e32f4430eee6387493c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga292dbafb10a606fcee46e2ed5a6465fc" id="r_ga292dbafb10a606fcee46e2ed5a6465fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga292dbafb10a606fcee46e2ed5a6465fc">FSMC_PCR3_PWID_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1002927e92f1e32f4430eee6387493c5">FSMC_PCR3_PWID_Pos</a>)</td></tr>
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<tr class="memitem:gac6f9b4e4449f105aa9bd3630f0466b9f" id="r_gac6f9b4e4449f105aa9bd3630f0466b9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6f9b4e4449f105aa9bd3630f0466b9f">FSMC_PCR3_PWID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga292dbafb10a606fcee46e2ed5a6465fc">FSMC_PCR3_PWID_Msk</a></td></tr>
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<tr class="memitem:gae07191f4d5e3c3ec38b271b30cd1ee07" id="r_gae07191f4d5e3c3ec38b271b30cd1ee07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae07191f4d5e3c3ec38b271b30cd1ee07">FSMC_PCR3_PWID_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1002927e92f1e32f4430eee6387493c5">FSMC_PCR3_PWID_Pos</a>)</td></tr>
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<tr class="memitem:gaa8819a742324c0523f3dc6b8959bcdd5" id="r_gaa8819a742324c0523f3dc6b8959bcdd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8819a742324c0523f3dc6b8959bcdd5">FSMC_PCR3_PWID_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1002927e92f1e32f4430eee6387493c5">FSMC_PCR3_PWID_Pos</a>)</td></tr>
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<tr class="memitem:gaf427fbfd20e6142aa46d625037c67fbe" id="r_gaf427fbfd20e6142aa46d625037c67fbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf427fbfd20e6142aa46d625037c67fbe">FSMC_PCR3_ECCEN_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaf427fbfd20e6142aa46d625037c67fbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62b7f1f808fa00fda792439b9c0f10df" id="r_ga62b7f1f808fa00fda792439b9c0f10df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62b7f1f808fa00fda792439b9c0f10df">FSMC_PCR3_ECCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf427fbfd20e6142aa46d625037c67fbe">FSMC_PCR3_ECCEN_Pos</a>)</td></tr>
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<tr class="memitem:ga723c4c8c3b97cd1ce18c3b5c888e5b4e" id="r_ga723c4c8c3b97cd1ce18c3b5c888e5b4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga723c4c8c3b97cd1ce18c3b5c888e5b4e">FSMC_PCR3_ECCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga62b7f1f808fa00fda792439b9c0f10df">FSMC_PCR3_ECCEN_Msk</a></td></tr>
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<tr class="memitem:ga7d8b78bf2fb85e57fcd42e1dbbd7d0cb" id="r_ga7d8b78bf2fb85e57fcd42e1dbbd7d0cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d8b78bf2fb85e57fcd42e1dbbd7d0cb">FSMC_PCR3_TCLR_Pos</a>   (9U)</td></tr>
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<tr class="memitem:gabf9f398e720fdb04a1c5cdecc91cd857" id="r_gabf9f398e720fdb04a1c5cdecc91cd857"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf9f398e720fdb04a1c5cdecc91cd857">FSMC_PCR3_TCLR_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d8b78bf2fb85e57fcd42e1dbbd7d0cb">FSMC_PCR3_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:ga478e4371d8baf2a0b2675b3113edb071" id="r_ga478e4371d8baf2a0b2675b3113edb071"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga478e4371d8baf2a0b2675b3113edb071">FSMC_PCR3_TCLR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabf9f398e720fdb04a1c5cdecc91cd857">FSMC_PCR3_TCLR_Msk</a></td></tr>
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<tr class="separator:ga478e4371d8baf2a0b2675b3113edb071"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadedb0d10b5b53656dc152b9264faffbd" id="r_gadedb0d10b5b53656dc152b9264faffbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadedb0d10b5b53656dc152b9264faffbd">FSMC_PCR3_TCLR_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d8b78bf2fb85e57fcd42e1dbbd7d0cb">FSMC_PCR3_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:gab5536285f03b1732aed999d20c0e25aa" id="r_gab5536285f03b1732aed999d20c0e25aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5536285f03b1732aed999d20c0e25aa">FSMC_PCR3_TCLR_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d8b78bf2fb85e57fcd42e1dbbd7d0cb">FSMC_PCR3_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:gae7d40ba9c0f0da58948ee2cc546b634c" id="r_gae7d40ba9c0f0da58948ee2cc546b634c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7d40ba9c0f0da58948ee2cc546b634c">FSMC_PCR3_TCLR_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d8b78bf2fb85e57fcd42e1dbbd7d0cb">FSMC_PCR3_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:ga63f96a640afa85d7521b05458f590a19" id="r_ga63f96a640afa85d7521b05458f590a19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63f96a640afa85d7521b05458f590a19">FSMC_PCR3_TCLR_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d8b78bf2fb85e57fcd42e1dbbd7d0cb">FSMC_PCR3_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:gaa2a4166c7fb1ca933148a90ded54588c" id="r_gaa2a4166c7fb1ca933148a90ded54588c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a4166c7fb1ca933148a90ded54588c">FSMC_PCR3_TAR_Pos</a>   (13U)</td></tr>
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<tr class="memitem:gaba49396ea8498e090556ab597f1a4964" id="r_gaba49396ea8498e090556ab597f1a4964"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba49396ea8498e090556ab597f1a4964">FSMC_PCR3_TAR_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a4166c7fb1ca933148a90ded54588c">FSMC_PCR3_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga199c4b0e690f0da0de46e372183da642" id="r_ga199c4b0e690f0da0de46e372183da642"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga199c4b0e690f0da0de46e372183da642">FSMC_PCR3_TAR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba49396ea8498e090556ab597f1a4964">FSMC_PCR3_TAR_Msk</a></td></tr>
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<tr class="memitem:gada0f17bcc683a5a6249348a63004e225" id="r_gada0f17bcc683a5a6249348a63004e225"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada0f17bcc683a5a6249348a63004e225">FSMC_PCR3_TAR_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a4166c7fb1ca933148a90ded54588c">FSMC_PCR3_TAR_Pos</a>)</td></tr>
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<tr class="memitem:gad4afb373f6f1cb1bedd653d8ea1dca78" id="r_gad4afb373f6f1cb1bedd653d8ea1dca78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4afb373f6f1cb1bedd653d8ea1dca78">FSMC_PCR3_TAR_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a4166c7fb1ca933148a90ded54588c">FSMC_PCR3_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga597698c6059f70f61310456e83353738" id="r_ga597698c6059f70f61310456e83353738"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga597698c6059f70f61310456e83353738">FSMC_PCR3_TAR_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a4166c7fb1ca933148a90ded54588c">FSMC_PCR3_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga4bd7aaf7ffcad9f4477ac4f2927a0912" id="r_ga4bd7aaf7ffcad9f4477ac4f2927a0912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bd7aaf7ffcad9f4477ac4f2927a0912">FSMC_PCR3_TAR_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a4166c7fb1ca933148a90ded54588c">FSMC_PCR3_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga102ae2695e494e32ba3a88386da61aaf" id="r_ga102ae2695e494e32ba3a88386da61aaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga102ae2695e494e32ba3a88386da61aaf">FSMC_PCR3_ECCPS_Pos</a>   (17U)</td></tr>
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<tr class="memitem:gae5c4fa241bbfe5cce0debcb6ad2052ce" id="r_gae5c4fa241bbfe5cce0debcb6ad2052ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5c4fa241bbfe5cce0debcb6ad2052ce">FSMC_PCR3_ECCPS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga102ae2695e494e32ba3a88386da61aaf">FSMC_PCR3_ECCPS_Pos</a>)</td></tr>
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<tr class="memitem:gaf8d92853ca6f97f72682c2f53f686998" id="r_gaf8d92853ca6f97f72682c2f53f686998"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8d92853ca6f97f72682c2f53f686998">FSMC_PCR3_ECCPS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae5c4fa241bbfe5cce0debcb6ad2052ce">FSMC_PCR3_ECCPS_Msk</a></td></tr>
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<tr class="separator:gaf8d92853ca6f97f72682c2f53f686998"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga506daa911151e1b9de3ed2b5030d1a5a" id="r_ga506daa911151e1b9de3ed2b5030d1a5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga506daa911151e1b9de3ed2b5030d1a5a">FSMC_PCR3_ECCPS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga102ae2695e494e32ba3a88386da61aaf">FSMC_PCR3_ECCPS_Pos</a>)</td></tr>
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<tr class="separator:ga506daa911151e1b9de3ed2b5030d1a5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6403c557bd93b5297fa7fbbf8dc49cc9" id="r_ga6403c557bd93b5297fa7fbbf8dc49cc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6403c557bd93b5297fa7fbbf8dc49cc9">FSMC_PCR3_ECCPS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga102ae2695e494e32ba3a88386da61aaf">FSMC_PCR3_ECCPS_Pos</a>)</td></tr>
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<tr class="memitem:gaf041e921fb9af07e9c709d79bbfaec89" id="r_gaf041e921fb9af07e9c709d79bbfaec89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf041e921fb9af07e9c709d79bbfaec89">FSMC_PCR3_ECCPS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga102ae2695e494e32ba3a88386da61aaf">FSMC_PCR3_ECCPS_Pos</a>)</td></tr>
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<tr class="memitem:gaaf0bbe752661c9c0cad5f84f067d4714" id="r_gaaf0bbe752661c9c0cad5f84f067d4714"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf0bbe752661c9c0cad5f84f067d4714">FSMC_PCR4_PWAITEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaaf0bbe752661c9c0cad5f84f067d4714"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8766498d3b50a9c490695d777713d492" id="r_ga8766498d3b50a9c490695d777713d492"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8766498d3b50a9c490695d777713d492">FSMC_PCR4_PWAITEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf0bbe752661c9c0cad5f84f067d4714">FSMC_PCR4_PWAITEN_Pos</a>)</td></tr>
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<tr class="separator:ga8766498d3b50a9c490695d777713d492"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab07ce7c785eb296a615b2c50415de21b" id="r_gab07ce7c785eb296a615b2c50415de21b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab07ce7c785eb296a615b2c50415de21b">FSMC_PCR4_PWAITEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8766498d3b50a9c490695d777713d492">FSMC_PCR4_PWAITEN_Msk</a></td></tr>
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<tr class="memitem:ga33cf4873210ab762fd32b654eb055e4a" id="r_ga33cf4873210ab762fd32b654eb055e4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33cf4873210ab762fd32b654eb055e4a">FSMC_PCR4_PBKEN_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga36baaaa99b92a8eb95f34e111e7b1129" id="r_ga36baaaa99b92a8eb95f34e111e7b1129"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36baaaa99b92a8eb95f34e111e7b1129">FSMC_PCR4_PBKEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga33cf4873210ab762fd32b654eb055e4a">FSMC_PCR4_PBKEN_Pos</a>)</td></tr>
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<tr class="memitem:ga2f4a72bae5da27f8da23c13a54fe9622" id="r_ga2f4a72bae5da27f8da23c13a54fe9622"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f4a72bae5da27f8da23c13a54fe9622">FSMC_PCR4_PBKEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36baaaa99b92a8eb95f34e111e7b1129">FSMC_PCR4_PBKEN_Msk</a></td></tr>
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<tr class="memitem:ga02a9e81721d3a6940da19547e32f5542" id="r_ga02a9e81721d3a6940da19547e32f5542"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02a9e81721d3a6940da19547e32f5542">FSMC_PCR4_PTYP_Pos</a>   (3U)</td></tr>
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<tr class="memitem:gad3a1ef73cc660cb04c99fc409bfc75b7" id="r_gad3a1ef73cc660cb04c99fc409bfc75b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3a1ef73cc660cb04c99fc409bfc75b7">FSMC_PCR4_PTYP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02a9e81721d3a6940da19547e32f5542">FSMC_PCR4_PTYP_Pos</a>)</td></tr>
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<tr class="memitem:gabe2d6f4e9bdef35436d521ebbdca5e40" id="r_gabe2d6f4e9bdef35436d521ebbdca5e40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe2d6f4e9bdef35436d521ebbdca5e40">FSMC_PCR4_PTYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad3a1ef73cc660cb04c99fc409bfc75b7">FSMC_PCR4_PTYP_Msk</a></td></tr>
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<tr class="memitem:gabea06d1f6a4648fefdc3939c115d6459" id="r_gabea06d1f6a4648fefdc3939c115d6459"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabea06d1f6a4648fefdc3939c115d6459">FSMC_PCR4_PWID_Pos</a>   (4U)</td></tr>
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<tr class="separator:gabea06d1f6a4648fefdc3939c115d6459"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga487f41300b79f8833d468b64195315f9" id="r_ga487f41300b79f8833d468b64195315f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga487f41300b79f8833d468b64195315f9">FSMC_PCR4_PWID_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabea06d1f6a4648fefdc3939c115d6459">FSMC_PCR4_PWID_Pos</a>)</td></tr>
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<tr class="memitem:ga9486b2b7346570ecc5715f1d551c168a" id="r_ga9486b2b7346570ecc5715f1d551c168a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9486b2b7346570ecc5715f1d551c168a">FSMC_PCR4_PWID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga487f41300b79f8833d468b64195315f9">FSMC_PCR4_PWID_Msk</a></td></tr>
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<tr class="memitem:ga0995cb320e6293ea435df275ce67359f" id="r_ga0995cb320e6293ea435df275ce67359f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0995cb320e6293ea435df275ce67359f">FSMC_PCR4_PWID_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabea06d1f6a4648fefdc3939c115d6459">FSMC_PCR4_PWID_Pos</a>)</td></tr>
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<tr class="memitem:ga8b6be32b3844a299a2c92089e81e27e9" id="r_ga8b6be32b3844a299a2c92089e81e27e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b6be32b3844a299a2c92089e81e27e9">FSMC_PCR4_PWID_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabea06d1f6a4648fefdc3939c115d6459">FSMC_PCR4_PWID_Pos</a>)</td></tr>
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<tr class="memitem:ga424cf5e2f1981675d26adf2196f885fb" id="r_ga424cf5e2f1981675d26adf2196f885fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga424cf5e2f1981675d26adf2196f885fb">FSMC_PCR4_ECCEN_Pos</a>   (6U)</td></tr>
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<tr class="memitem:ga6bee93c8682a87840c8b437c174eb13b" id="r_ga6bee93c8682a87840c8b437c174eb13b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bee93c8682a87840c8b437c174eb13b">FSMC_PCR4_ECCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga424cf5e2f1981675d26adf2196f885fb">FSMC_PCR4_ECCEN_Pos</a>)</td></tr>
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<tr class="memitem:ga646509f8bebb0d662c730ed4cabe741f" id="r_ga646509f8bebb0d662c730ed4cabe741f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga646509f8bebb0d662c730ed4cabe741f">FSMC_PCR4_ECCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6bee93c8682a87840c8b437c174eb13b">FSMC_PCR4_ECCEN_Msk</a></td></tr>
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<tr class="memitem:ga2db09770ae63805a9a06c0382b66c640" id="r_ga2db09770ae63805a9a06c0382b66c640"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2db09770ae63805a9a06c0382b66c640">FSMC_PCR4_TCLR_Pos</a>   (9U)</td></tr>
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<tr class="memitem:gae9971f1f3806a65aee5a5993f687c582" id="r_gae9971f1f3806a65aee5a5993f687c582"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9971f1f3806a65aee5a5993f687c582">FSMC_PCR4_TCLR_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db09770ae63805a9a06c0382b66c640">FSMC_PCR4_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:ga7c7164974019263cacbc7dda2fc14126" id="r_ga7c7164974019263cacbc7dda2fc14126"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c7164974019263cacbc7dda2fc14126">FSMC_PCR4_TCLR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae9971f1f3806a65aee5a5993f687c582">FSMC_PCR4_TCLR_Msk</a></td></tr>
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<tr class="memitem:ga0dd78ad0c755190a69b37ebac75a11dd" id="r_ga0dd78ad0c755190a69b37ebac75a11dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dd78ad0c755190a69b37ebac75a11dd">FSMC_PCR4_TCLR_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db09770ae63805a9a06c0382b66c640">FSMC_PCR4_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:gaf0ea2e2287999d3c7d6583aab492514d" id="r_gaf0ea2e2287999d3c7d6583aab492514d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0ea2e2287999d3c7d6583aab492514d">FSMC_PCR4_TCLR_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db09770ae63805a9a06c0382b66c640">FSMC_PCR4_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:ga34dd56ee892fc187e105e4d820ce3b9a" id="r_ga34dd56ee892fc187e105e4d820ce3b9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34dd56ee892fc187e105e4d820ce3b9a">FSMC_PCR4_TCLR_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db09770ae63805a9a06c0382b66c640">FSMC_PCR4_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:ga0eb8dc60a469cfa96b3b3b7fad25ac92" id="r_ga0eb8dc60a469cfa96b3b3b7fad25ac92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0eb8dc60a469cfa96b3b3b7fad25ac92">FSMC_PCR4_TCLR_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db09770ae63805a9a06c0382b66c640">FSMC_PCR4_TCLR_Pos</a>)</td></tr>
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<tr class="memitem:gaf67899acb4972b2feffc057c69460dc2" id="r_gaf67899acb4972b2feffc057c69460dc2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf67899acb4972b2feffc057c69460dc2">FSMC_PCR4_TAR_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga77f6431c476681f6a4e72f807eba2e41" id="r_ga77f6431c476681f6a4e72f807eba2e41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77f6431c476681f6a4e72f807eba2e41">FSMC_PCR4_TAR_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf67899acb4972b2feffc057c69460dc2">FSMC_PCR4_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga0c583f305906f19b15ce3dc177fa21bd" id="r_ga0c583f305906f19b15ce3dc177fa21bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c583f305906f19b15ce3dc177fa21bd">FSMC_PCR4_TAR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga77f6431c476681f6a4e72f807eba2e41">FSMC_PCR4_TAR_Msk</a></td></tr>
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<tr class="memitem:ga62fe4ede4c658b788596e8ea6f325c9f" id="r_ga62fe4ede4c658b788596e8ea6f325c9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62fe4ede4c658b788596e8ea6f325c9f">FSMC_PCR4_TAR_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf67899acb4972b2feffc057c69460dc2">FSMC_PCR4_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga2a9958cbf815ac97c3500a46aaf573f5" id="r_ga2a9958cbf815ac97c3500a46aaf573f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a9958cbf815ac97c3500a46aaf573f5">FSMC_PCR4_TAR_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf67899acb4972b2feffc057c69460dc2">FSMC_PCR4_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga669e16ecd48c92f65bd66f2da63fe53f" id="r_ga669e16ecd48c92f65bd66f2da63fe53f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga669e16ecd48c92f65bd66f2da63fe53f">FSMC_PCR4_TAR_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf67899acb4972b2feffc057c69460dc2">FSMC_PCR4_TAR_Pos</a>)</td></tr>
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<tr class="memitem:gad298ef64d36721696517ed0d4ac12d32" id="r_gad298ef64d36721696517ed0d4ac12d32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad298ef64d36721696517ed0d4ac12d32">FSMC_PCR4_TAR_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf67899acb4972b2feffc057c69460dc2">FSMC_PCR4_TAR_Pos</a>)</td></tr>
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<tr class="memitem:ga2d07f92979ed4e7985b86118ccf71d9d" id="r_ga2d07f92979ed4e7985b86118ccf71d9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d07f92979ed4e7985b86118ccf71d9d">FSMC_PCR4_ECCPS_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga2d07f92979ed4e7985b86118ccf71d9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07b5adc339bceccfa581082c73978949" id="r_ga07b5adc339bceccfa581082c73978949"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07b5adc339bceccfa581082c73978949">FSMC_PCR4_ECCPS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d07f92979ed4e7985b86118ccf71d9d">FSMC_PCR4_ECCPS_Pos</a>)</td></tr>
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<tr class="separator:ga07b5adc339bceccfa581082c73978949"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2308baba97f307b8beb6239702471038" id="r_ga2308baba97f307b8beb6239702471038"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2308baba97f307b8beb6239702471038">FSMC_PCR4_ECCPS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga07b5adc339bceccfa581082c73978949">FSMC_PCR4_ECCPS_Msk</a></td></tr>
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<tr class="separator:ga2308baba97f307b8beb6239702471038"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76514698225c0734c1e9be46b6dbd298" id="r_ga76514698225c0734c1e9be46b6dbd298"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76514698225c0734c1e9be46b6dbd298">FSMC_PCR4_ECCPS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d07f92979ed4e7985b86118ccf71d9d">FSMC_PCR4_ECCPS_Pos</a>)</td></tr>
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<tr class="separator:ga76514698225c0734c1e9be46b6dbd298"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c43076003bbf01f95765125e19ab94d" id="r_ga1c43076003bbf01f95765125e19ab94d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c43076003bbf01f95765125e19ab94d">FSMC_PCR4_ECCPS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d07f92979ed4e7985b86118ccf71d9d">FSMC_PCR4_ECCPS_Pos</a>)</td></tr>
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<tr class="separator:ga1c43076003bbf01f95765125e19ab94d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4ba96304e6618d4eb7672cdc3bd8f01" id="r_gac4ba96304e6618d4eb7672cdc3bd8f01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4ba96304e6618d4eb7672cdc3bd8f01">FSMC_PCR4_ECCPS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d07f92979ed4e7985b86118ccf71d9d">FSMC_PCR4_ECCPS_Pos</a>)</td></tr>
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<tr class="separator:gac4ba96304e6618d4eb7672cdc3bd8f01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06ebb4b8d85407f96dcbdf67f4a99cb9" id="r_ga06ebb4b8d85407f96dcbdf67f4a99cb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06ebb4b8d85407f96dcbdf67f4a99cb9">FSMC_SR2_IRS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga06ebb4b8d85407f96dcbdf67f4a99cb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad134a6cdb6d9df958be6f45ea4f952a7" id="r_gad134a6cdb6d9df958be6f45ea4f952a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad134a6cdb6d9df958be6f45ea4f952a7">FSMC_SR2_IRS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga06ebb4b8d85407f96dcbdf67f4a99cb9">FSMC_SR2_IRS_Pos</a>)</td></tr>
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<tr class="separator:gad134a6cdb6d9df958be6f45ea4f952a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19f1b90b2da89b68aa754d0a89d60de9" id="r_ga19f1b90b2da89b68aa754d0a89d60de9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19f1b90b2da89b68aa754d0a89d60de9">FSMC_SR2_IRS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad134a6cdb6d9df958be6f45ea4f952a7">FSMC_SR2_IRS_Msk</a></td></tr>
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<tr class="memitem:ga640c5b0f263676b6d0e5934916f6613d" id="r_ga640c5b0f263676b6d0e5934916f6613d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga640c5b0f263676b6d0e5934916f6613d">FSMC_SR2_ILS_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga640c5b0f263676b6d0e5934916f6613d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88ea643e2a899e222e2c9166f0b47af9" id="r_ga88ea643e2a899e222e2c9166f0b47af9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88ea643e2a899e222e2c9166f0b47af9">FSMC_SR2_ILS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga640c5b0f263676b6d0e5934916f6613d">FSMC_SR2_ILS_Pos</a>)</td></tr>
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<tr class="separator:ga88ea643e2a899e222e2c9166f0b47af9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga664d6e1440c12e76dfa34f716af85ed1" id="r_ga664d6e1440c12e76dfa34f716af85ed1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga664d6e1440c12e76dfa34f716af85ed1">FSMC_SR2_ILS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga88ea643e2a899e222e2c9166f0b47af9">FSMC_SR2_ILS_Msk</a></td></tr>
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<tr class="separator:ga664d6e1440c12e76dfa34f716af85ed1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45cd1c374a43ee088640e33e95dc5688" id="r_ga45cd1c374a43ee088640e33e95dc5688"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45cd1c374a43ee088640e33e95dc5688">FSMC_SR2_IFS_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga892a452cb80f67fc2c5f4a0ff775ff5b" id="r_ga892a452cb80f67fc2c5f4a0ff775ff5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga892a452cb80f67fc2c5f4a0ff775ff5b">FSMC_SR2_IFS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga45cd1c374a43ee088640e33e95dc5688">FSMC_SR2_IFS_Pos</a>)</td></tr>
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<tr class="separator:ga892a452cb80f67fc2c5f4a0ff775ff5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6492ad6afe175283d07de38978936dc" id="r_gad6492ad6afe175283d07de38978936dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6492ad6afe175283d07de38978936dc">FSMC_SR2_IFS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga892a452cb80f67fc2c5f4a0ff775ff5b">FSMC_SR2_IFS_Msk</a></td></tr>
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<tr class="separator:gad6492ad6afe175283d07de38978936dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64ac90a6d11f1b83eaaba0bbe76225a6" id="r_ga64ac90a6d11f1b83eaaba0bbe76225a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64ac90a6d11f1b83eaaba0bbe76225a6">FSMC_SR2_IREN_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga64ac90a6d11f1b83eaaba0bbe76225a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99bc457a07a274821c92d025bee142b2" id="r_ga99bc457a07a274821c92d025bee142b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99bc457a07a274821c92d025bee142b2">FSMC_SR2_IREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga64ac90a6d11f1b83eaaba0bbe76225a6">FSMC_SR2_IREN_Pos</a>)</td></tr>
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<tr class="memitem:ga3216bd665a118239e6ef0b58ec5e8a8e" id="r_ga3216bd665a118239e6ef0b58ec5e8a8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3216bd665a118239e6ef0b58ec5e8a8e">FSMC_SR2_IREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga99bc457a07a274821c92d025bee142b2">FSMC_SR2_IREN_Msk</a></td></tr>
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<tr class="separator:ga3216bd665a118239e6ef0b58ec5e8a8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada9faf7f03a84292d12b91b59ecc6e8e" id="r_gada9faf7f03a84292d12b91b59ecc6e8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada9faf7f03a84292d12b91b59ecc6e8e">FSMC_SR2_ILEN_Pos</a>   (4U)</td></tr>
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<tr class="separator:gada9faf7f03a84292d12b91b59ecc6e8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae59b87df9b2b879f3c6228b44f8e67ec" id="r_gae59b87df9b2b879f3c6228b44f8e67ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae59b87df9b2b879f3c6228b44f8e67ec">FSMC_SR2_ILEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada9faf7f03a84292d12b91b59ecc6e8e">FSMC_SR2_ILEN_Pos</a>)</td></tr>
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<tr class="separator:gae59b87df9b2b879f3c6228b44f8e67ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e9df0edd35d0ad6a35ff3a3b045b47c" id="r_ga1e9df0edd35d0ad6a35ff3a3b045b47c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e9df0edd35d0ad6a35ff3a3b045b47c">FSMC_SR2_ILEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae59b87df9b2b879f3c6228b44f8e67ec">FSMC_SR2_ILEN_Msk</a></td></tr>
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<tr class="separator:ga1e9df0edd35d0ad6a35ff3a3b045b47c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19ce3774c409a6824a03414035807696" id="r_ga19ce3774c409a6824a03414035807696"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19ce3774c409a6824a03414035807696">FSMC_SR2_IFEN_Pos</a>   (5U)</td></tr>
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<tr class="memitem:ga5b3607ef98ac617609731f96d63a6d8c" id="r_ga5b3607ef98ac617609731f96d63a6d8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b3607ef98ac617609731f96d63a6d8c">FSMC_SR2_IFEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga19ce3774c409a6824a03414035807696">FSMC_SR2_IFEN_Pos</a>)</td></tr>
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<tr class="memitem:ga755c088c58b27f79108675f56ea9d196" id="r_ga755c088c58b27f79108675f56ea9d196"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga755c088c58b27f79108675f56ea9d196">FSMC_SR2_IFEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b3607ef98ac617609731f96d63a6d8c">FSMC_SR2_IFEN_Msk</a></td></tr>
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<tr class="memitem:ga39d0ccd9fb1c6c802201f0d5b2497892" id="r_ga39d0ccd9fb1c6c802201f0d5b2497892"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39d0ccd9fb1c6c802201f0d5b2497892">FSMC_SR2_FEMPT_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga39d0ccd9fb1c6c802201f0d5b2497892"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa95bc00b8c686ad2b0078d28b0f4830" id="r_gaaa95bc00b8c686ad2b0078d28b0f4830"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa95bc00b8c686ad2b0078d28b0f4830">FSMC_SR2_FEMPT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga39d0ccd9fb1c6c802201f0d5b2497892">FSMC_SR2_FEMPT_Pos</a>)</td></tr>
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<tr class="separator:gaaa95bc00b8c686ad2b0078d28b0f4830"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ae2e544a4a515303f49815cdbd5ebbb" id="r_ga6ae2e544a4a515303f49815cdbd5ebbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ae2e544a4a515303f49815cdbd5ebbb">FSMC_SR2_FEMPT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa95bc00b8c686ad2b0078d28b0f4830">FSMC_SR2_FEMPT_Msk</a></td></tr>
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<tr class="separator:ga6ae2e544a4a515303f49815cdbd5ebbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88805716c1271a441d94a540f00d941b" id="r_ga88805716c1271a441d94a540f00d941b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88805716c1271a441d94a540f00d941b">FSMC_SR3_IRS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga88805716c1271a441d94a540f00d941b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38a4f74813da2200db8d8f7254742593" id="r_ga38a4f74813da2200db8d8f7254742593"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38a4f74813da2200db8d8f7254742593">FSMC_SR3_IRS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga88805716c1271a441d94a540f00d941b">FSMC_SR3_IRS_Pos</a>)</td></tr>
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<tr class="separator:ga38a4f74813da2200db8d8f7254742593"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad929e4a8c1fdb49ee6f690121336afea" id="r_gad929e4a8c1fdb49ee6f690121336afea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad929e4a8c1fdb49ee6f690121336afea">FSMC_SR3_IRS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38a4f74813da2200db8d8f7254742593">FSMC_SR3_IRS_Msk</a></td></tr>
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<tr class="separator:gad929e4a8c1fdb49ee6f690121336afea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9d20d9eb15db67e6195c83c6bfeba1a" id="r_gad9d20d9eb15db67e6195c83c6bfeba1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9d20d9eb15db67e6195c83c6bfeba1a">FSMC_SR3_ILS_Pos</a>   (1U)</td></tr>
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<tr class="separator:gad9d20d9eb15db67e6195c83c6bfeba1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90c83ca70c1030e39babd809c181301b" id="r_ga90c83ca70c1030e39babd809c181301b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90c83ca70c1030e39babd809c181301b">FSMC_SR3_ILS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9d20d9eb15db67e6195c83c6bfeba1a">FSMC_SR3_ILS_Pos</a>)</td></tr>
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<tr class="separator:ga90c83ca70c1030e39babd809c181301b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9803b4ab5b8cce213a80abc11c751d21" id="r_ga9803b4ab5b8cce213a80abc11c751d21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9803b4ab5b8cce213a80abc11c751d21">FSMC_SR3_ILS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga90c83ca70c1030e39babd809c181301b">FSMC_SR3_ILS_Msk</a></td></tr>
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<tr class="memitem:ga6149a6b31cbb1e18378e183cdbfa7cb6" id="r_ga6149a6b31cbb1e18378e183cdbfa7cb6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6149a6b31cbb1e18378e183cdbfa7cb6">FSMC_SR3_IFS_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga6149a6b31cbb1e18378e183cdbfa7cb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a6b22553c9ad5a974bb1e8288932a54" id="r_ga6a6b22553c9ad5a974bb1e8288932a54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a6b22553c9ad5a974bb1e8288932a54">FSMC_SR3_IFS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6149a6b31cbb1e18378e183cdbfa7cb6">FSMC_SR3_IFS_Pos</a>)</td></tr>
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<tr class="separator:ga6a6b22553c9ad5a974bb1e8288932a54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafadff6b6f9e6430ada2f56bc9921dd7d" id="r_gafadff6b6f9e6430ada2f56bc9921dd7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafadff6b6f9e6430ada2f56bc9921dd7d">FSMC_SR3_IFS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a6b22553c9ad5a974bb1e8288932a54">FSMC_SR3_IFS_Msk</a></td></tr>
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<tr class="separator:gafadff6b6f9e6430ada2f56bc9921dd7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02bbc52ce42d56880369709c4f256dd3" id="r_ga02bbc52ce42d56880369709c4f256dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02bbc52ce42d56880369709c4f256dd3">FSMC_SR3_IREN_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga02bbc52ce42d56880369709c4f256dd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b1cab2aa1407a79d66c5c85029ea815" id="r_ga1b1cab2aa1407a79d66c5c85029ea815"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b1cab2aa1407a79d66c5c85029ea815">FSMC_SR3_IREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02bbc52ce42d56880369709c4f256dd3">FSMC_SR3_IREN_Pos</a>)</td></tr>
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<tr class="separator:ga1b1cab2aa1407a79d66c5c85029ea815"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12baad15533ecbc57db95ea4939bc782" id="r_ga12baad15533ecbc57db95ea4939bc782"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12baad15533ecbc57db95ea4939bc782">FSMC_SR3_IREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b1cab2aa1407a79d66c5c85029ea815">FSMC_SR3_IREN_Msk</a></td></tr>
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<tr class="separator:ga12baad15533ecbc57db95ea4939bc782"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2b3bd94d6eddc0cdd3911ad580fa541" id="r_gac2b3bd94d6eddc0cdd3911ad580fa541"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2b3bd94d6eddc0cdd3911ad580fa541">FSMC_SR3_ILEN_Pos</a>   (4U)</td></tr>
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<tr class="separator:gac2b3bd94d6eddc0cdd3911ad580fa541"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafec67196217e783676f157212cfc7976" id="r_gafec67196217e783676f157212cfc7976"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafec67196217e783676f157212cfc7976">FSMC_SR3_ILEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2b3bd94d6eddc0cdd3911ad580fa541">FSMC_SR3_ILEN_Pos</a>)</td></tr>
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<tr class="memitem:ga86ac8f1f9f99c81a26fb54b597b57f12" id="r_ga86ac8f1f9f99c81a26fb54b597b57f12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86ac8f1f9f99c81a26fb54b597b57f12">FSMC_SR3_ILEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafec67196217e783676f157212cfc7976">FSMC_SR3_ILEN_Msk</a></td></tr>
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<tr class="separator:ga86ac8f1f9f99c81a26fb54b597b57f12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c78f3e87e892640e79917b97a58ae0d" id="r_ga2c78f3e87e892640e79917b97a58ae0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c78f3e87e892640e79917b97a58ae0d">FSMC_SR3_IFEN_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga2c78f3e87e892640e79917b97a58ae0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65588f7ae2e908af340e5ff1bfb18671" id="r_ga65588f7ae2e908af340e5ff1bfb18671"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65588f7ae2e908af340e5ff1bfb18671">FSMC_SR3_IFEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c78f3e87e892640e79917b97a58ae0d">FSMC_SR3_IFEN_Pos</a>)</td></tr>
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<tr class="separator:ga65588f7ae2e908af340e5ff1bfb18671"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7355e5368013759dbfabfec8b609ca8" id="r_gaa7355e5368013759dbfabfec8b609ca8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7355e5368013759dbfabfec8b609ca8">FSMC_SR3_IFEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65588f7ae2e908af340e5ff1bfb18671">FSMC_SR3_IFEN_Msk</a></td></tr>
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<tr class="separator:gaa7355e5368013759dbfabfec8b609ca8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76a834622c16170caf9cb2e1fb14c452" id="r_ga76a834622c16170caf9cb2e1fb14c452"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76a834622c16170caf9cb2e1fb14c452">FSMC_SR3_FEMPT_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga76a834622c16170caf9cb2e1fb14c452"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6436500aea203033a62f7ddcbad814a3" id="r_ga6436500aea203033a62f7ddcbad814a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6436500aea203033a62f7ddcbad814a3">FSMC_SR3_FEMPT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga76a834622c16170caf9cb2e1fb14c452">FSMC_SR3_FEMPT_Pos</a>)</td></tr>
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<tr class="memitem:ga230562cf231dc79cd9354933b39ae7de" id="r_ga230562cf231dc79cd9354933b39ae7de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga230562cf231dc79cd9354933b39ae7de">FSMC_SR3_FEMPT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6436500aea203033a62f7ddcbad814a3">FSMC_SR3_FEMPT_Msk</a></td></tr>
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<tr class="memitem:ga8fd0b4be91d7fa754929c96bb772e40d" id="r_ga8fd0b4be91d7fa754929c96bb772e40d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fd0b4be91d7fa754929c96bb772e40d">FSMC_SR4_IRS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8fd0b4be91d7fa754929c96bb772e40d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga359dc66df56e053e76cf0c8d8b1228f3" id="r_ga359dc66df56e053e76cf0c8d8b1228f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga359dc66df56e053e76cf0c8d8b1228f3">FSMC_SR4_IRS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fd0b4be91d7fa754929c96bb772e40d">FSMC_SR4_IRS_Pos</a>)</td></tr>
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<tr class="separator:ga359dc66df56e053e76cf0c8d8b1228f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga163f7143d51b516af0d46b142222957f" id="r_ga163f7143d51b516af0d46b142222957f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga163f7143d51b516af0d46b142222957f">FSMC_SR4_IRS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga359dc66df56e053e76cf0c8d8b1228f3">FSMC_SR4_IRS_Msk</a></td></tr>
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<tr class="separator:ga163f7143d51b516af0d46b142222957f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35d76d1ef37af831006e517f4c495b39" id="r_ga35d76d1ef37af831006e517f4c495b39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35d76d1ef37af831006e517f4c495b39">FSMC_SR4_ILS_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga35d76d1ef37af831006e517f4c495b39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9f640a57868933823d67ed24baae3cd" id="r_gac9f640a57868933823d67ed24baae3cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9f640a57868933823d67ed24baae3cd">FSMC_SR4_ILS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga35d76d1ef37af831006e517f4c495b39">FSMC_SR4_ILS_Pos</a>)</td></tr>
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<tr class="separator:gac9f640a57868933823d67ed24baae3cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e19feccd1553911d08be673c4af72ad" id="r_ga0e19feccd1553911d08be673c4af72ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e19feccd1553911d08be673c4af72ad">FSMC_SR4_ILS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9f640a57868933823d67ed24baae3cd">FSMC_SR4_ILS_Msk</a></td></tr>
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<tr class="memitem:gaaba60426f9ebd437c2fe600929f17b9b" id="r_gaaba60426f9ebd437c2fe600929f17b9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaba60426f9ebd437c2fe600929f17b9b">FSMC_SR4_IFS_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaaba60426f9ebd437c2fe600929f17b9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38930113868c959a3661b7296be4f3b4" id="r_ga38930113868c959a3661b7296be4f3b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38930113868c959a3661b7296be4f3b4">FSMC_SR4_IFS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaba60426f9ebd437c2fe600929f17b9b">FSMC_SR4_IFS_Pos</a>)</td></tr>
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<tr class="separator:ga38930113868c959a3661b7296be4f3b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1e7d71b32a0b70d772fbdc85f7053fc" id="r_gaf1e7d71b32a0b70d772fbdc85f7053fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1e7d71b32a0b70d772fbdc85f7053fc">FSMC_SR4_IFS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38930113868c959a3661b7296be4f3b4">FSMC_SR4_IFS_Msk</a></td></tr>
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<tr class="separator:gaf1e7d71b32a0b70d772fbdc85f7053fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7345c2e21921244fde94badae4cb6084" id="r_ga7345c2e21921244fde94badae4cb6084"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7345c2e21921244fde94badae4cb6084">FSMC_SR4_IREN_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga7345c2e21921244fde94badae4cb6084"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7026294e98de80663d4530e07ae1777c" id="r_ga7026294e98de80663d4530e07ae1777c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7026294e98de80663d4530e07ae1777c">FSMC_SR4_IREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7345c2e21921244fde94badae4cb6084">FSMC_SR4_IREN_Pos</a>)</td></tr>
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<tr class="separator:ga7026294e98de80663d4530e07ae1777c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f5f17d22e07bb6674cbd68740b9708a" id="r_ga6f5f17d22e07bb6674cbd68740b9708a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f5f17d22e07bb6674cbd68740b9708a">FSMC_SR4_IREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7026294e98de80663d4530e07ae1777c">FSMC_SR4_IREN_Msk</a></td></tr>
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<tr class="separator:ga6f5f17d22e07bb6674cbd68740b9708a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb2544b2d75f937bc0ff66eaa824c8fa" id="r_gadb2544b2d75f937bc0ff66eaa824c8fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb2544b2d75f937bc0ff66eaa824c8fa">FSMC_SR4_ILEN_Pos</a>   (4U)</td></tr>
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<tr class="separator:gadb2544b2d75f937bc0ff66eaa824c8fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d2d4242df3e464630c5723bf8ce62f9" id="r_ga7d2d4242df3e464630c5723bf8ce62f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d2d4242df3e464630c5723bf8ce62f9">FSMC_SR4_ILEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb2544b2d75f937bc0ff66eaa824c8fa">FSMC_SR4_ILEN_Pos</a>)</td></tr>
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<tr class="separator:ga7d2d4242df3e464630c5723bf8ce62f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9b8d7c7b68723a4ef01843d547d95bc" id="r_gac9b8d7c7b68723a4ef01843d547d95bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9b8d7c7b68723a4ef01843d547d95bc">FSMC_SR4_ILEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d2d4242df3e464630c5723bf8ce62f9">FSMC_SR4_ILEN_Msk</a></td></tr>
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<tr class="separator:gac9b8d7c7b68723a4ef01843d547d95bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72c86dadfbc92cb71ada1b69afaf0422" id="r_ga72c86dadfbc92cb71ada1b69afaf0422"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72c86dadfbc92cb71ada1b69afaf0422">FSMC_SR4_IFEN_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga72c86dadfbc92cb71ada1b69afaf0422"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf050b0a4e3500f081929ef8893f3a01c" id="r_gaf050b0a4e3500f081929ef8893f3a01c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf050b0a4e3500f081929ef8893f3a01c">FSMC_SR4_IFEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga72c86dadfbc92cb71ada1b69afaf0422">FSMC_SR4_IFEN_Pos</a>)</td></tr>
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<tr class="separator:gaf050b0a4e3500f081929ef8893f3a01c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf97394e42be634cb441204f6bfffb504" id="r_gaf97394e42be634cb441204f6bfffb504"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf97394e42be634cb441204f6bfffb504">FSMC_SR4_IFEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf050b0a4e3500f081929ef8893f3a01c">FSMC_SR4_IFEN_Msk</a></td></tr>
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<tr class="separator:gaf97394e42be634cb441204f6bfffb504"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2927e164634b8377d7f5de607ffa8aae" id="r_ga2927e164634b8377d7f5de607ffa8aae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2927e164634b8377d7f5de607ffa8aae">FSMC_SR4_FEMPT_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga2927e164634b8377d7f5de607ffa8aae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad85d7dabbc8635c7fbcf55e18c1b38c7" id="r_gad85d7dabbc8635c7fbcf55e18c1b38c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad85d7dabbc8635c7fbcf55e18c1b38c7">FSMC_SR4_FEMPT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2927e164634b8377d7f5de607ffa8aae">FSMC_SR4_FEMPT_Pos</a>)</td></tr>
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<tr class="memitem:gaae7081cdf26e75bccfac1b6a29c04124" id="r_gaae7081cdf26e75bccfac1b6a29c04124"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae7081cdf26e75bccfac1b6a29c04124">FSMC_SR4_FEMPT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad85d7dabbc8635c7fbcf55e18c1b38c7">FSMC_SR4_FEMPT_Msk</a></td></tr>
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<tr class="separator:gaae7081cdf26e75bccfac1b6a29c04124"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57fea4182c63e845dfaaeffe67d7dcf8" id="r_ga57fea4182c63e845dfaaeffe67d7dcf8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8">FSMC_PMEM2_MEMSET2_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga57fea4182c63e845dfaaeffe67d7dcf8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b57a52f74837d3aa9b7731a1a33159b" id="r_ga1b57a52f74837d3aa9b7731a1a33159b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b57a52f74837d3aa9b7731a1a33159b">FSMC_PMEM2_MEMSET2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8">FSMC_PMEM2_MEMSET2_Pos</a>)</td></tr>
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<tr class="separator:ga1b57a52f74837d3aa9b7731a1a33159b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50a34195ddb7ab7aebc2acac39b27536" id="r_ga50a34195ddb7ab7aebc2acac39b27536"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50a34195ddb7ab7aebc2acac39b27536">FSMC_PMEM2_MEMSET2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b57a52f74837d3aa9b7731a1a33159b">FSMC_PMEM2_MEMSET2_Msk</a></td></tr>
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<tr class="separator:ga50a34195ddb7ab7aebc2acac39b27536"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga529858550113070878ce680da0a6bf7d" id="r_ga529858550113070878ce680da0a6bf7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga529858550113070878ce680da0a6bf7d">FSMC_PMEM2_MEMSET2_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8">FSMC_PMEM2_MEMSET2_Pos</a>)</td></tr>
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<tr class="separator:ga529858550113070878ce680da0a6bf7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28517c1f5aeded21b3f0326247b0bbe1" id="r_ga28517c1f5aeded21b3f0326247b0bbe1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28517c1f5aeded21b3f0326247b0bbe1">FSMC_PMEM2_MEMSET2_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8">FSMC_PMEM2_MEMSET2_Pos</a>)</td></tr>
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<tr class="separator:ga28517c1f5aeded21b3f0326247b0bbe1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f59339df091ad8a00d75c32b335b711" id="r_ga1f59339df091ad8a00d75c32b335b711"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f59339df091ad8a00d75c32b335b711">FSMC_PMEM2_MEMSET2_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8">FSMC_PMEM2_MEMSET2_Pos</a>)</td></tr>
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<tr class="separator:ga1f59339df091ad8a00d75c32b335b711"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7715c089272c9709e8f94590b46be609" id="r_ga7715c089272c9709e8f94590b46be609"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7715c089272c9709e8f94590b46be609">FSMC_PMEM2_MEMSET2_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8">FSMC_PMEM2_MEMSET2_Pos</a>)</td></tr>
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<tr class="separator:ga7715c089272c9709e8f94590b46be609"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31a0e44106c1ec87375054be15b1cb84" id="r_ga31a0e44106c1ec87375054be15b1cb84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31a0e44106c1ec87375054be15b1cb84">FSMC_PMEM2_MEMSET2_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8">FSMC_PMEM2_MEMSET2_Pos</a>)</td></tr>
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<tr class="separator:ga31a0e44106c1ec87375054be15b1cb84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga221edf50060c5dad91de3c0b877fdbfc" id="r_ga221edf50060c5dad91de3c0b877fdbfc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga221edf50060c5dad91de3c0b877fdbfc">FSMC_PMEM2_MEMSET2_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8">FSMC_PMEM2_MEMSET2_Pos</a>)</td></tr>
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<tr class="separator:ga221edf50060c5dad91de3c0b877fdbfc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5dc6beefe3ea22a84dbc44fd30843778" id="r_ga5dc6beefe3ea22a84dbc44fd30843778"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5dc6beefe3ea22a84dbc44fd30843778">FSMC_PMEM2_MEMSET2_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8">FSMC_PMEM2_MEMSET2_Pos</a>)</td></tr>
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<tr class="separator:ga5dc6beefe3ea22a84dbc44fd30843778"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae14181cbd85100c2b3b104525c42ee6c" id="r_gae14181cbd85100c2b3b104525c42ee6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae14181cbd85100c2b3b104525c42ee6c">FSMC_PMEM2_MEMSET2_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8">FSMC_PMEM2_MEMSET2_Pos</a>)</td></tr>
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<tr class="separator:gae14181cbd85100c2b3b104525c42ee6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0072f7fa82f3fb4ca184511738fc4d30" id="r_ga0072f7fa82f3fb4ca184511738fc4d30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30">FSMC_PMEM2_MEMWAIT2_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga0072f7fa82f3fb4ca184511738fc4d30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90343ef2f0e0433265e721aeba552f3f" id="r_ga90343ef2f0e0433265e721aeba552f3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90343ef2f0e0433265e721aeba552f3f">FSMC_PMEM2_MEMWAIT2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30">FSMC_PMEM2_MEMWAIT2_Pos</a>)</td></tr>
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<tr class="separator:ga90343ef2f0e0433265e721aeba552f3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7affee760cfe5d04a58bda9cd7fc5f72" id="r_ga7affee760cfe5d04a58bda9cd7fc5f72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7affee760cfe5d04a58bda9cd7fc5f72">FSMC_PMEM2_MEMWAIT2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga90343ef2f0e0433265e721aeba552f3f">FSMC_PMEM2_MEMWAIT2_Msk</a></td></tr>
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<tr class="separator:ga7affee760cfe5d04a58bda9cd7fc5f72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ee1c7f3347678dff204e6ac8c6eaf4f" id="r_ga7ee1c7f3347678dff204e6ac8c6eaf4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ee1c7f3347678dff204e6ac8c6eaf4f">FSMC_PMEM2_MEMWAIT2_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30">FSMC_PMEM2_MEMWAIT2_Pos</a>)</td></tr>
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<tr class="separator:ga7ee1c7f3347678dff204e6ac8c6eaf4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56de464fa3f895e75f0ec2ff3f9e1e1e" id="r_ga56de464fa3f895e75f0ec2ff3f9e1e1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56de464fa3f895e75f0ec2ff3f9e1e1e">FSMC_PMEM2_MEMWAIT2_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30">FSMC_PMEM2_MEMWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga922a823292054746923fb13b8f4c1b5c" id="r_ga922a823292054746923fb13b8f4c1b5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga922a823292054746923fb13b8f4c1b5c">FSMC_PMEM2_MEMWAIT2_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30">FSMC_PMEM2_MEMWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga44f9c0141f457b0ef0ff42c1645d7337" id="r_ga44f9c0141f457b0ef0ff42c1645d7337"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44f9c0141f457b0ef0ff42c1645d7337">FSMC_PMEM2_MEMWAIT2_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30">FSMC_PMEM2_MEMWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga8d15645ffe422f3e35cc03efd93361cb" id="r_ga8d15645ffe422f3e35cc03efd93361cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d15645ffe422f3e35cc03efd93361cb">FSMC_PMEM2_MEMWAIT2_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30">FSMC_PMEM2_MEMWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga640d5866b22b11924b7e4c9bfc608624" id="r_ga640d5866b22b11924b7e4c9bfc608624"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga640d5866b22b11924b7e4c9bfc608624">FSMC_PMEM2_MEMWAIT2_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30">FSMC_PMEM2_MEMWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga51d69f501306eae03db719cb52065b3c" id="r_ga51d69f501306eae03db719cb52065b3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51d69f501306eae03db719cb52065b3c">FSMC_PMEM2_MEMWAIT2_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30">FSMC_PMEM2_MEMWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga127b0e01d15f1007cfa67247a99da26f" id="r_ga127b0e01d15f1007cfa67247a99da26f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga127b0e01d15f1007cfa67247a99da26f">FSMC_PMEM2_MEMWAIT2_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30">FSMC_PMEM2_MEMWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga7e62ae5b193c0df1b570af7489ad9e78" id="r_ga7e62ae5b193c0df1b570af7489ad9e78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78">FSMC_PMEM2_MEMHOLD2_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga5f1e5661bbb15ad918a6e2f7d09fcfe6" id="r_ga5f1e5661bbb15ad918a6e2f7d09fcfe6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f1e5661bbb15ad918a6e2f7d09fcfe6">FSMC_PMEM2_MEMHOLD2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78">FSMC_PMEM2_MEMHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:gaad2c79ef9df8b619e93c15b506f4fd7d" id="r_gaad2c79ef9df8b619e93c15b506f4fd7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad2c79ef9df8b619e93c15b506f4fd7d">FSMC_PMEM2_MEMHOLD2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f1e5661bbb15ad918a6e2f7d09fcfe6">FSMC_PMEM2_MEMHOLD2_Msk</a></td></tr>
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<tr class="memitem:gadd16a720c69fcac1f6b798cf6f9bbb7e" id="r_gadd16a720c69fcac1f6b798cf6f9bbb7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd16a720c69fcac1f6b798cf6f9bbb7e">FSMC_PMEM2_MEMHOLD2_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78">FSMC_PMEM2_MEMHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:ga4630e2bdb842914d0f7b53d4ed610122" id="r_ga4630e2bdb842914d0f7b53d4ed610122"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4630e2bdb842914d0f7b53d4ed610122">FSMC_PMEM2_MEMHOLD2_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78">FSMC_PMEM2_MEMHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:gacf699fd414971d0c52159c21652f5e58" id="r_gacf699fd414971d0c52159c21652f5e58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf699fd414971d0c52159c21652f5e58">FSMC_PMEM2_MEMHOLD2_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78">FSMC_PMEM2_MEMHOLD2_Pos</a>)</td></tr>
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<tr class="separator:gacf699fd414971d0c52159c21652f5e58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3e1f50389b82f8737a12ef6d1683c4f" id="r_gad3e1f50389b82f8737a12ef6d1683c4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3e1f50389b82f8737a12ef6d1683c4f">FSMC_PMEM2_MEMHOLD2_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78">FSMC_PMEM2_MEMHOLD2_Pos</a>)</td></tr>
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<tr class="separator:gad3e1f50389b82f8737a12ef6d1683c4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00c7b1a8cbcbcbcc0495ebd7c877ca9e" id="r_ga00c7b1a8cbcbcbcc0495ebd7c877ca9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00c7b1a8cbcbcbcc0495ebd7c877ca9e">FSMC_PMEM2_MEMHOLD2_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78">FSMC_PMEM2_MEMHOLD2_Pos</a>)</td></tr>
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<tr class="separator:ga00c7b1a8cbcbcbcc0495ebd7c877ca9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9cd7c5637824522c2bd0f2cd165ca218" id="r_ga9cd7c5637824522c2bd0f2cd165ca218"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cd7c5637824522c2bd0f2cd165ca218">FSMC_PMEM2_MEMHOLD2_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78">FSMC_PMEM2_MEMHOLD2_Pos</a>)</td></tr>
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<tr class="separator:ga9cd7c5637824522c2bd0f2cd165ca218"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52ee3806d174025ab98d6c9148f17ae2" id="r_ga52ee3806d174025ab98d6c9148f17ae2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52ee3806d174025ab98d6c9148f17ae2">FSMC_PMEM2_MEMHOLD2_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78">FSMC_PMEM2_MEMHOLD2_Pos</a>)</td></tr>
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<tr class="separator:ga52ee3806d174025ab98d6c9148f17ae2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1afae5788b827aebc3df92c74754b38" id="r_gad1afae5788b827aebc3df92c74754b38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1afae5788b827aebc3df92c74754b38">FSMC_PMEM2_MEMHOLD2_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78">FSMC_PMEM2_MEMHOLD2_Pos</a>)</td></tr>
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<tr class="separator:gad1afae5788b827aebc3df92c74754b38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1964483dae67a5aff01ddd046583acb7" id="r_ga1964483dae67a5aff01ddd046583acb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7">FSMC_PMEM2_MEMHIZ2_Pos</a>   (24U)</td></tr>
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<tr class="memitem:gab6155f1c3280ce295a8c90bb5e3dfba9" id="r_gab6155f1c3280ce295a8c90bb5e3dfba9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6155f1c3280ce295a8c90bb5e3dfba9">FSMC_PMEM2_MEMHIZ2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7">FSMC_PMEM2_MEMHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:ga8a7783e155a688bf79e68ebf570421c4" id="r_ga8a7783e155a688bf79e68ebf570421c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a7783e155a688bf79e68ebf570421c4">FSMC_PMEM2_MEMHIZ2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab6155f1c3280ce295a8c90bb5e3dfba9">FSMC_PMEM2_MEMHIZ2_Msk</a></td></tr>
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<tr class="memitem:ga8bb51ecefa94c1ab3b91c7a14705b8c8" id="r_ga8bb51ecefa94c1ab3b91c7a14705b8c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8bb51ecefa94c1ab3b91c7a14705b8c8">FSMC_PMEM2_MEMHIZ2_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7">FSMC_PMEM2_MEMHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:ga4c0d8bf861d9918763b7391d4ad287b0" id="r_ga4c0d8bf861d9918763b7391d4ad287b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c0d8bf861d9918763b7391d4ad287b0">FSMC_PMEM2_MEMHIZ2_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7">FSMC_PMEM2_MEMHIZ2_Pos</a>)</td></tr>
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<tr class="separator:ga4c0d8bf861d9918763b7391d4ad287b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebd6a4457fa0ac4f1b98fdc58bef9999" id="r_gaebd6a4457fa0ac4f1b98fdc58bef9999"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebd6a4457fa0ac4f1b98fdc58bef9999">FSMC_PMEM2_MEMHIZ2_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7">FSMC_PMEM2_MEMHIZ2_Pos</a>)</td></tr>
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<tr class="separator:gaebd6a4457fa0ac4f1b98fdc58bef9999"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaded9a6b1b516fa2595988c84c5465f9b" id="r_gaded9a6b1b516fa2595988c84c5465f9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaded9a6b1b516fa2595988c84c5465f9b">FSMC_PMEM2_MEMHIZ2_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7">FSMC_PMEM2_MEMHIZ2_Pos</a>)</td></tr>
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<tr class="separator:gaded9a6b1b516fa2595988c84c5465f9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9b1831fb25422c7a126a7d029223394" id="r_gad9b1831fb25422c7a126a7d029223394"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9b1831fb25422c7a126a7d029223394">FSMC_PMEM2_MEMHIZ2_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7">FSMC_PMEM2_MEMHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:gae828a4dde56e15f78ab156feeb329af9" id="r_gae828a4dde56e15f78ab156feeb329af9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae828a4dde56e15f78ab156feeb329af9">FSMC_PMEM2_MEMHIZ2_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7">FSMC_PMEM2_MEMHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:gacf5464a2e8aeec6eb06c58283168ef97" id="r_gacf5464a2e8aeec6eb06c58283168ef97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf5464a2e8aeec6eb06c58283168ef97">FSMC_PMEM2_MEMHIZ2_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7">FSMC_PMEM2_MEMHIZ2_Pos</a>)</td></tr>
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<tr class="separator:gacf5464a2e8aeec6eb06c58283168ef97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c5ca1880a516478e1b8f1142066c004" id="r_ga3c5ca1880a516478e1b8f1142066c004"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c5ca1880a516478e1b8f1142066c004">FSMC_PMEM2_MEMHIZ2_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7">FSMC_PMEM2_MEMHIZ2_Pos</a>)</td></tr>
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<tr class="separator:ga3c5ca1880a516478e1b8f1142066c004"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2db6b5656145efa4ae5c03d5932a5abf" id="r_ga2db6b5656145efa4ae5c03d5932a5abf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf">FSMC_PMEM3_MEMSET3_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2db6b5656145efa4ae5c03d5932a5abf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa58775ce9ebda0e97d4bf481c7bd53e" id="r_gaaa58775ce9ebda0e97d4bf481c7bd53e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa58775ce9ebda0e97d4bf481c7bd53e">FSMC_PMEM3_MEMSET3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf">FSMC_PMEM3_MEMSET3_Pos</a>)</td></tr>
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<tr class="memitem:gaf69ac574f9be3c11ada1e2dc4c3abe4f" id="r_gaf69ac574f9be3c11ada1e2dc4c3abe4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf69ac574f9be3c11ada1e2dc4c3abe4f">FSMC_PMEM3_MEMSET3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa58775ce9ebda0e97d4bf481c7bd53e">FSMC_PMEM3_MEMSET3_Msk</a></td></tr>
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<tr class="memitem:gaee68bc7ff3e4cf11c2ca826541858c6a" id="r_gaee68bc7ff3e4cf11c2ca826541858c6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee68bc7ff3e4cf11c2ca826541858c6a">FSMC_PMEM3_MEMSET3_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf">FSMC_PMEM3_MEMSET3_Pos</a>)</td></tr>
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<tr class="memitem:gafa10132605ec4a4be1ab48ee6b36080e" id="r_gafa10132605ec4a4be1ab48ee6b36080e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa10132605ec4a4be1ab48ee6b36080e">FSMC_PMEM3_MEMSET3_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf">FSMC_PMEM3_MEMSET3_Pos</a>)</td></tr>
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<tr class="memitem:gacd867b06de7c7a49244b6a35570d2cd2" id="r_gacd867b06de7c7a49244b6a35570d2cd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd867b06de7c7a49244b6a35570d2cd2">FSMC_PMEM3_MEMSET3_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf">FSMC_PMEM3_MEMSET3_Pos</a>)</td></tr>
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<tr class="memitem:ga292a8826723614aa2504a376f4a2e5d5" id="r_ga292a8826723614aa2504a376f4a2e5d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga292a8826723614aa2504a376f4a2e5d5">FSMC_PMEM3_MEMSET3_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf">FSMC_PMEM3_MEMSET3_Pos</a>)</td></tr>
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<tr class="memitem:ga98703fee6465ba580b052ef76f2c63f2" id="r_ga98703fee6465ba580b052ef76f2c63f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98703fee6465ba580b052ef76f2c63f2">FSMC_PMEM3_MEMSET3_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf">FSMC_PMEM3_MEMSET3_Pos</a>)</td></tr>
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<tr class="memitem:gaaea28a64fc9a7e0df35826b4ec372361" id="r_gaaea28a64fc9a7e0df35826b4ec372361"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaea28a64fc9a7e0df35826b4ec372361">FSMC_PMEM3_MEMSET3_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf">FSMC_PMEM3_MEMSET3_Pos</a>)</td></tr>
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<tr class="memitem:gaea51bbe866574be10bdc1d2d16bb9810" id="r_gaea51bbe866574be10bdc1d2d16bb9810"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea51bbe866574be10bdc1d2d16bb9810">FSMC_PMEM3_MEMSET3_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf">FSMC_PMEM3_MEMSET3_Pos</a>)</td></tr>
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<tr class="memitem:ga702eeb8c3930ea564af728cc3bb9044b" id="r_ga702eeb8c3930ea564af728cc3bb9044b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga702eeb8c3930ea564af728cc3bb9044b">FSMC_PMEM3_MEMSET3_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf">FSMC_PMEM3_MEMSET3_Pos</a>)</td></tr>
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<tr class="memitem:ga1fae8d256e50724a047b115add6b6f8c" id="r_ga1fae8d256e50724a047b115add6b6f8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c">FSMC_PMEM3_MEMWAIT3_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga57e03075040da97e636158721615ca93" id="r_ga57e03075040da97e636158721615ca93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57e03075040da97e636158721615ca93">FSMC_PMEM3_MEMWAIT3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c">FSMC_PMEM3_MEMWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:ga4243cb8b53a10143621872c0d0ed318b" id="r_ga4243cb8b53a10143621872c0d0ed318b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4243cb8b53a10143621872c0d0ed318b">FSMC_PMEM3_MEMWAIT3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57e03075040da97e636158721615ca93">FSMC_PMEM3_MEMWAIT3_Msk</a></td></tr>
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<tr class="memitem:ga30d8aad77f584d1c380b6d04d4984ac5" id="r_ga30d8aad77f584d1c380b6d04d4984ac5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30d8aad77f584d1c380b6d04d4984ac5">FSMC_PMEM3_MEMWAIT3_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c">FSMC_PMEM3_MEMWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:gaacf4638838e3cf2dfa076ef795596967" id="r_gaacf4638838e3cf2dfa076ef795596967"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacf4638838e3cf2dfa076ef795596967">FSMC_PMEM3_MEMWAIT3_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c">FSMC_PMEM3_MEMWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:gaa1c65a1027062f3fff04dfdd24c33e64" id="r_gaa1c65a1027062f3fff04dfdd24c33e64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1c65a1027062f3fff04dfdd24c33e64">FSMC_PMEM3_MEMWAIT3_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c">FSMC_PMEM3_MEMWAIT3_Pos</a>)</td></tr>
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<tr class="separator:gaa1c65a1027062f3fff04dfdd24c33e64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae23146168ddc8e06defd6e75390dde1d" id="r_gae23146168ddc8e06defd6e75390dde1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae23146168ddc8e06defd6e75390dde1d">FSMC_PMEM3_MEMWAIT3_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c">FSMC_PMEM3_MEMWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:ga79640d63c03f94bd4f38859c46bad820" id="r_ga79640d63c03f94bd4f38859c46bad820"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79640d63c03f94bd4f38859c46bad820">FSMC_PMEM3_MEMWAIT3_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c">FSMC_PMEM3_MEMWAIT3_Pos</a>)</td></tr>
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<tr class="separator:ga79640d63c03f94bd4f38859c46bad820"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d36841fa1730bbbc825278cffd623f3" id="r_ga8d36841fa1730bbbc825278cffd623f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d36841fa1730bbbc825278cffd623f3">FSMC_PMEM3_MEMWAIT3_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c">FSMC_PMEM3_MEMWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:ga2bd34f98ee23b7a58ac63cd195c00d70" id="r_ga2bd34f98ee23b7a58ac63cd195c00d70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bd34f98ee23b7a58ac63cd195c00d70">FSMC_PMEM3_MEMWAIT3_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c">FSMC_PMEM3_MEMWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:ga0f485579592b7fdf2e480523ee220418" id="r_ga0f485579592b7fdf2e480523ee220418"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f485579592b7fdf2e480523ee220418">FSMC_PMEM3_MEMWAIT3_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c">FSMC_PMEM3_MEMWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:ga6130db15261d3342f1f6882fabccb590" id="r_ga6130db15261d3342f1f6882fabccb590"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590">FSMC_PMEM3_MEMHOLD3_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga6130db15261d3342f1f6882fabccb590"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1dba6050327dc9b2282e64e8236e6725" id="r_ga1dba6050327dc9b2282e64e8236e6725"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1dba6050327dc9b2282e64e8236e6725">FSMC_PMEM3_MEMHOLD3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590">FSMC_PMEM3_MEMHOLD3_Pos</a>)</td></tr>
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<tr class="separator:ga1dba6050327dc9b2282e64e8236e6725"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8ef1e0f4db1e2792b0939f9058a149b" id="r_gac8ef1e0f4db1e2792b0939f9058a149b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8ef1e0f4db1e2792b0939f9058a149b">FSMC_PMEM3_MEMHOLD3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1dba6050327dc9b2282e64e8236e6725">FSMC_PMEM3_MEMHOLD3_Msk</a></td></tr>
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<tr class="separator:gac8ef1e0f4db1e2792b0939f9058a149b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1abd4698bb45c784b23b8d431eb90f1" id="r_gaa1abd4698bb45c784b23b8d431eb90f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1abd4698bb45c784b23b8d431eb90f1">FSMC_PMEM3_MEMHOLD3_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590">FSMC_PMEM3_MEMHOLD3_Pos</a>)</td></tr>
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<tr class="separator:gaa1abd4698bb45c784b23b8d431eb90f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a93e71d784bdb1cd115805feac42d6b" id="r_ga0a93e71d784bdb1cd115805feac42d6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a93e71d784bdb1cd115805feac42d6b">FSMC_PMEM3_MEMHOLD3_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590">FSMC_PMEM3_MEMHOLD3_Pos</a>)</td></tr>
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<tr class="separator:ga0a93e71d784bdb1cd115805feac42d6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20a5443b5236e71b8dfe0620abffbd68" id="r_ga20a5443b5236e71b8dfe0620abffbd68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20a5443b5236e71b8dfe0620abffbd68">FSMC_PMEM3_MEMHOLD3_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590">FSMC_PMEM3_MEMHOLD3_Pos</a>)</td></tr>
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<tr class="separator:ga20a5443b5236e71b8dfe0620abffbd68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b330eabb266b26cf6aa93b12bfe7b38" id="r_ga3b330eabb266b26cf6aa93b12bfe7b38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b330eabb266b26cf6aa93b12bfe7b38">FSMC_PMEM3_MEMHOLD3_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590">FSMC_PMEM3_MEMHOLD3_Pos</a>)</td></tr>
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<tr class="separator:ga3b330eabb266b26cf6aa93b12bfe7b38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6d1864268bb87124d127d92e8db54dc" id="r_gac6d1864268bb87124d127d92e8db54dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6d1864268bb87124d127d92e8db54dc">FSMC_PMEM3_MEMHOLD3_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590">FSMC_PMEM3_MEMHOLD3_Pos</a>)</td></tr>
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<tr class="memitem:ga8968569a91c0b5d6c456074ddfc98aa3" id="r_ga8968569a91c0b5d6c456074ddfc98aa3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8968569a91c0b5d6c456074ddfc98aa3">FSMC_PMEM3_MEMHOLD3_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590">FSMC_PMEM3_MEMHOLD3_Pos</a>)</td></tr>
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<tr class="separator:ga8968569a91c0b5d6c456074ddfc98aa3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf40967f9e19b41e2692b7fe1177b8629" id="r_gaf40967f9e19b41e2692b7fe1177b8629"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf40967f9e19b41e2692b7fe1177b8629">FSMC_PMEM3_MEMHOLD3_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590">FSMC_PMEM3_MEMHOLD3_Pos</a>)</td></tr>
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<tr class="memitem:gaf0da29e1e300e47aebb0bd47bf5f0563" id="r_gaf0da29e1e300e47aebb0bd47bf5f0563"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0da29e1e300e47aebb0bd47bf5f0563">FSMC_PMEM3_MEMHOLD3_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590">FSMC_PMEM3_MEMHOLD3_Pos</a>)</td></tr>
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<tr class="memitem:ga14b9bedec189a62c563088a91e1a4a0e" id="r_ga14b9bedec189a62c563088a91e1a4a0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e">FSMC_PMEM3_MEMHIZ3_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga0dfe7b65ecc252eca58b04156dbd4c32" id="r_ga0dfe7b65ecc252eca58b04156dbd4c32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dfe7b65ecc252eca58b04156dbd4c32">FSMC_PMEM3_MEMHIZ3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e">FSMC_PMEM3_MEMHIZ3_Pos</a>)</td></tr>
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<tr class="memitem:ga3a77d54c66589f233792d30fc83e7f12" id="r_ga3a77d54c66589f233792d30fc83e7f12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a77d54c66589f233792d30fc83e7f12">FSMC_PMEM3_MEMHIZ3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dfe7b65ecc252eca58b04156dbd4c32">FSMC_PMEM3_MEMHIZ3_Msk</a></td></tr>
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<tr class="memitem:ga2d8453ab8a7488ff13c681154bfd293c" id="r_ga2d8453ab8a7488ff13c681154bfd293c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d8453ab8a7488ff13c681154bfd293c">FSMC_PMEM3_MEMHIZ3_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e">FSMC_PMEM3_MEMHIZ3_Pos</a>)</td></tr>
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<tr class="memitem:gaf023951ad4fd31a691cc26fc3c27ec46" id="r_gaf023951ad4fd31a691cc26fc3c27ec46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf023951ad4fd31a691cc26fc3c27ec46">FSMC_PMEM3_MEMHIZ3_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e">FSMC_PMEM3_MEMHIZ3_Pos</a>)</td></tr>
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<tr class="memitem:gaaf8d790834161e0224c878cd8eab190e" id="r_gaaf8d790834161e0224c878cd8eab190e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf8d790834161e0224c878cd8eab190e">FSMC_PMEM3_MEMHIZ3_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e">FSMC_PMEM3_MEMHIZ3_Pos</a>)</td></tr>
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<tr class="memitem:ga26daeb039123824e2de5fdd64cb3a1ff" id="r_ga26daeb039123824e2de5fdd64cb3a1ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26daeb039123824e2de5fdd64cb3a1ff">FSMC_PMEM3_MEMHIZ3_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e">FSMC_PMEM3_MEMHIZ3_Pos</a>)</td></tr>
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<tr class="memitem:gafd06d96e44933ce665b2af8c2a4098e4" id="r_gafd06d96e44933ce665b2af8c2a4098e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd06d96e44933ce665b2af8c2a4098e4">FSMC_PMEM3_MEMHIZ3_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e">FSMC_PMEM3_MEMHIZ3_Pos</a>)</td></tr>
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<tr class="memitem:gaef1254b2e2251da2b30aa297d1d0a1f8" id="r_gaef1254b2e2251da2b30aa297d1d0a1f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef1254b2e2251da2b30aa297d1d0a1f8">FSMC_PMEM3_MEMHIZ3_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e">FSMC_PMEM3_MEMHIZ3_Pos</a>)</td></tr>
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<tr class="separator:gaef1254b2e2251da2b30aa297d1d0a1f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf33c72c5ab0747d587a801835cf1a897" id="r_gaf33c72c5ab0747d587a801835cf1a897"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf33c72c5ab0747d587a801835cf1a897">FSMC_PMEM3_MEMHIZ3_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e">FSMC_PMEM3_MEMHIZ3_Pos</a>)</td></tr>
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<tr class="memitem:gaa7304d0d28edd32a70be474e656fbf8e" id="r_gaa7304d0d28edd32a70be474e656fbf8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7304d0d28edd32a70be474e656fbf8e">FSMC_PMEM3_MEMHIZ3_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e">FSMC_PMEM3_MEMHIZ3_Pos</a>)</td></tr>
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<tr class="separator:gaa7304d0d28edd32a70be474e656fbf8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeec8eeb3ff3a51842b4bc3a0f01315c0" id="r_gaeec8eeb3ff3a51842b4bc3a0f01315c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0">FSMC_PMEM4_MEMSET4_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaeec8eeb3ff3a51842b4bc3a0f01315c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6506768173e0734a59f62d527f3f0a4" id="r_gaa6506768173e0734a59f62d527f3f0a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6506768173e0734a59f62d527f3f0a4">FSMC_PMEM4_MEMSET4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0">FSMC_PMEM4_MEMSET4_Pos</a>)</td></tr>
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<tr class="separator:gaa6506768173e0734a59f62d527f3f0a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b5cb5385ce2cef772ee4493c25617aa" id="r_ga3b5cb5385ce2cef772ee4493c25617aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b5cb5385ce2cef772ee4493c25617aa">FSMC_PMEM4_MEMSET4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6506768173e0734a59f62d527f3f0a4">FSMC_PMEM4_MEMSET4_Msk</a></td></tr>
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<tr class="memitem:ga6df1a1190522593b71da113c7ea8cfab" id="r_ga6df1a1190522593b71da113c7ea8cfab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6df1a1190522593b71da113c7ea8cfab">FSMC_PMEM4_MEMSET4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0">FSMC_PMEM4_MEMSET4_Pos</a>)</td></tr>
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<tr class="memitem:ga6fa76a9c077f40e973df8fe6903c69c4" id="r_ga6fa76a9c077f40e973df8fe6903c69c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fa76a9c077f40e973df8fe6903c69c4">FSMC_PMEM4_MEMSET4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0">FSMC_PMEM4_MEMSET4_Pos</a>)</td></tr>
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<tr class="separator:ga6fa76a9c077f40e973df8fe6903c69c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03ddc1ecb61313593976bf70aec06e9f" id="r_ga03ddc1ecb61313593976bf70aec06e9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03ddc1ecb61313593976bf70aec06e9f">FSMC_PMEM4_MEMSET4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0">FSMC_PMEM4_MEMSET4_Pos</a>)</td></tr>
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<tr class="separator:ga03ddc1ecb61313593976bf70aec06e9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4280253a6049c7739c6b70a6d7940998" id="r_ga4280253a6049c7739c6b70a6d7940998"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4280253a6049c7739c6b70a6d7940998">FSMC_PMEM4_MEMSET4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0">FSMC_PMEM4_MEMSET4_Pos</a>)</td></tr>
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<tr class="memitem:ga153d7b557dc40b797f93bf5593808279" id="r_ga153d7b557dc40b797f93bf5593808279"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga153d7b557dc40b797f93bf5593808279">FSMC_PMEM4_MEMSET4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0">FSMC_PMEM4_MEMSET4_Pos</a>)</td></tr>
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<tr class="separator:ga153d7b557dc40b797f93bf5593808279"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc8fc6eadc2e952227c121b6d6114834" id="r_gabc8fc6eadc2e952227c121b6d6114834"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc8fc6eadc2e952227c121b6d6114834">FSMC_PMEM4_MEMSET4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0">FSMC_PMEM4_MEMSET4_Pos</a>)</td></tr>
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<tr class="memitem:gaecce633b6da6db82000f1d39dc23bb3b" id="r_gaecce633b6da6db82000f1d39dc23bb3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecce633b6da6db82000f1d39dc23bb3b">FSMC_PMEM4_MEMSET4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0">FSMC_PMEM4_MEMSET4_Pos</a>)</td></tr>
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<tr class="memitem:ga04c68698ff6f47551244ae5a26893059" id="r_ga04c68698ff6f47551244ae5a26893059"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04c68698ff6f47551244ae5a26893059">FSMC_PMEM4_MEMSET4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0">FSMC_PMEM4_MEMSET4_Pos</a>)</td></tr>
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<tr class="separator:ga04c68698ff6f47551244ae5a26893059"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga265881544d02839df4b2a9b03be04358" id="r_ga265881544d02839df4b2a9b03be04358"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358">FSMC_PMEM4_MEMWAIT4_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gaeb6d7917d078c6ccdc62cd80e9578513" id="r_gaeb6d7917d078c6ccdc62cd80e9578513"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb6d7917d078c6ccdc62cd80e9578513">FSMC_PMEM4_MEMWAIT4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358">FSMC_PMEM4_MEMWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga9673f81abf15ad70d09520db9ddfc58d" id="r_ga9673f81abf15ad70d09520db9ddfc58d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9673f81abf15ad70d09520db9ddfc58d">FSMC_PMEM4_MEMWAIT4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb6d7917d078c6ccdc62cd80e9578513">FSMC_PMEM4_MEMWAIT4_Msk</a></td></tr>
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<tr class="memitem:ga9c88b294c963e5be76da4bf3048af411" id="r_ga9c88b294c963e5be76da4bf3048af411"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c88b294c963e5be76da4bf3048af411">FSMC_PMEM4_MEMWAIT4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358">FSMC_PMEM4_MEMWAIT4_Pos</a>)</td></tr>
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<tr class="separator:ga9c88b294c963e5be76da4bf3048af411"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24d45891fa0a503d81f68f62f5fd18e5" id="r_ga24d45891fa0a503d81f68f62f5fd18e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24d45891fa0a503d81f68f62f5fd18e5">FSMC_PMEM4_MEMWAIT4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358">FSMC_PMEM4_MEMWAIT4_Pos</a>)</td></tr>
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<tr class="separator:ga24d45891fa0a503d81f68f62f5fd18e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1fa35a7722b6339a7cef85b5be2280d" id="r_gaf1fa35a7722b6339a7cef85b5be2280d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1fa35a7722b6339a7cef85b5be2280d">FSMC_PMEM4_MEMWAIT4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358">FSMC_PMEM4_MEMWAIT4_Pos</a>)</td></tr>
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<tr class="separator:gaf1fa35a7722b6339a7cef85b5be2280d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga929f7f1066e3f2d69c72126615d06cb0" id="r_ga929f7f1066e3f2d69c72126615d06cb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga929f7f1066e3f2d69c72126615d06cb0">FSMC_PMEM4_MEMWAIT4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358">FSMC_PMEM4_MEMWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga5282e3d9205f778b67ef00c27beb2918" id="r_ga5282e3d9205f778b67ef00c27beb2918"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5282e3d9205f778b67ef00c27beb2918">FSMC_PMEM4_MEMWAIT4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358">FSMC_PMEM4_MEMWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga1eed44a0b89a9f14b08c4ab2578ca5cc" id="r_ga1eed44a0b89a9f14b08c4ab2578ca5cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1eed44a0b89a9f14b08c4ab2578ca5cc">FSMC_PMEM4_MEMWAIT4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358">FSMC_PMEM4_MEMWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:gab2429913d3b7993dfda75413f0a72bf4" id="r_gab2429913d3b7993dfda75413f0a72bf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2429913d3b7993dfda75413f0a72bf4">FSMC_PMEM4_MEMWAIT4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358">FSMC_PMEM4_MEMWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga247eb296ad16d1c7f2ebea0ca85619f9" id="r_ga247eb296ad16d1c7f2ebea0ca85619f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga247eb296ad16d1c7f2ebea0ca85619f9">FSMC_PMEM4_MEMWAIT4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358">FSMC_PMEM4_MEMWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:gaa288ec797541c772dfd1ce78ef63335e" id="r_gaa288ec797541c772dfd1ce78ef63335e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e">FSMC_PMEM4_MEMHOLD4_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gaf0cf6a3b9e83d5785668a232f179922b" id="r_gaf0cf6a3b9e83d5785668a232f179922b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0cf6a3b9e83d5785668a232f179922b">FSMC_PMEM4_MEMHOLD4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e">FSMC_PMEM4_MEMHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:ga5028f0c2a642b7faedf602f0b2c0d64c" id="r_ga5028f0c2a642b7faedf602f0b2c0d64c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5028f0c2a642b7faedf602f0b2c0d64c">FSMC_PMEM4_MEMHOLD4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0cf6a3b9e83d5785668a232f179922b">FSMC_PMEM4_MEMHOLD4_Msk</a></td></tr>
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<tr class="memitem:gaf07eef15a372886fda3182f49e2e912e" id="r_gaf07eef15a372886fda3182f49e2e912e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf07eef15a372886fda3182f49e2e912e">FSMC_PMEM4_MEMHOLD4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e">FSMC_PMEM4_MEMHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:gaa05a691ca81b6fe6df07adb1c5142597" id="r_gaa05a691ca81b6fe6df07adb1c5142597"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa05a691ca81b6fe6df07adb1c5142597">FSMC_PMEM4_MEMHOLD4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e">FSMC_PMEM4_MEMHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:gaafd4f50c33f4ec69e878983fb6065c73" id="r_gaafd4f50c33f4ec69e878983fb6065c73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafd4f50c33f4ec69e878983fb6065c73">FSMC_PMEM4_MEMHOLD4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e">FSMC_PMEM4_MEMHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:gac3cf67d6699d41fc042aed2be6d6aef0" id="r_gac3cf67d6699d41fc042aed2be6d6aef0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3cf67d6699d41fc042aed2be6d6aef0">FSMC_PMEM4_MEMHOLD4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e">FSMC_PMEM4_MEMHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:ga963acb8aef1a1e3f7f369421a3f9bfd9" id="r_ga963acb8aef1a1e3f7f369421a3f9bfd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga963acb8aef1a1e3f7f369421a3f9bfd9">FSMC_PMEM4_MEMHOLD4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e">FSMC_PMEM4_MEMHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:gac3ca8c6eb5fde2be7d38bde8aedb5522" id="r_gac3ca8c6eb5fde2be7d38bde8aedb5522"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3ca8c6eb5fde2be7d38bde8aedb5522">FSMC_PMEM4_MEMHOLD4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e">FSMC_PMEM4_MEMHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:gae0352f9aa02c4037d690b516d7385d27" id="r_gae0352f9aa02c4037d690b516d7385d27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0352f9aa02c4037d690b516d7385d27">FSMC_PMEM4_MEMHOLD4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e">FSMC_PMEM4_MEMHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:ga880aa86c933687f7565b7ab79776923e" id="r_ga880aa86c933687f7565b7ab79776923e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga880aa86c933687f7565b7ab79776923e">FSMC_PMEM4_MEMHOLD4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e">FSMC_PMEM4_MEMHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:gab27dd74b58a232a823408c58277b19ef" id="r_gab27dd74b58a232a823408c58277b19ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef">FSMC_PMEM4_MEMHIZ4_Pos</a>   (24U)</td></tr>
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<tr class="memitem:gaa99cb02c3b57623c92d17f68b44f84a4" id="r_gaa99cb02c3b57623c92d17f68b44f84a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa99cb02c3b57623c92d17f68b44f84a4">FSMC_PMEM4_MEMHIZ4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef">FSMC_PMEM4_MEMHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga6b194500112e61e5dd41ded843bb08c6" id="r_ga6b194500112e61e5dd41ded843bb08c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b194500112e61e5dd41ded843bb08c6">FSMC_PMEM4_MEMHIZ4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa99cb02c3b57623c92d17f68b44f84a4">FSMC_PMEM4_MEMHIZ4_Msk</a></td></tr>
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<tr class="memitem:ga9298e847d13d24cbe87a3c477af9f02c" id="r_ga9298e847d13d24cbe87a3c477af9f02c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9298e847d13d24cbe87a3c477af9f02c">FSMC_PMEM4_MEMHIZ4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef">FSMC_PMEM4_MEMHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga591eb0822bbb91c4ba12f80d35424c4c" id="r_ga591eb0822bbb91c4ba12f80d35424c4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga591eb0822bbb91c4ba12f80d35424c4c">FSMC_PMEM4_MEMHIZ4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef">FSMC_PMEM4_MEMHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga6db858408154b3694bb1fdc995f7e069" id="r_ga6db858408154b3694bb1fdc995f7e069"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6db858408154b3694bb1fdc995f7e069">FSMC_PMEM4_MEMHIZ4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef">FSMC_PMEM4_MEMHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga0e38ef7ec628928bea867de00af9b206" id="r_ga0e38ef7ec628928bea867de00af9b206"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e38ef7ec628928bea867de00af9b206">FSMC_PMEM4_MEMHIZ4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef">FSMC_PMEM4_MEMHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga81a86c24f41bd5363793953df972d941" id="r_ga81a86c24f41bd5363793953df972d941"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81a86c24f41bd5363793953df972d941">FSMC_PMEM4_MEMHIZ4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef">FSMC_PMEM4_MEMHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga08a6ec2df1aa20cfcfacaed7e60417a0" id="r_ga08a6ec2df1aa20cfcfacaed7e60417a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08a6ec2df1aa20cfcfacaed7e60417a0">FSMC_PMEM4_MEMHIZ4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef">FSMC_PMEM4_MEMHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga443fff9e0a661cce0d3fe96886eceb0b" id="r_ga443fff9e0a661cce0d3fe96886eceb0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga443fff9e0a661cce0d3fe96886eceb0b">FSMC_PMEM4_MEMHIZ4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef">FSMC_PMEM4_MEMHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga90cf92af2475f9f7cadbb9553225260d" id="r_ga90cf92af2475f9f7cadbb9553225260d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90cf92af2475f9f7cadbb9553225260d">FSMC_PMEM4_MEMHIZ4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef">FSMC_PMEM4_MEMHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:gabc7a654ded670713a8926626faad19db" id="r_gabc7a654ded670713a8926626faad19db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db">FSMC_PATT2_ATTSET2_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gabc4ae266a174a451c7eff4c6e82a08d6" id="r_gabc4ae266a174a451c7eff4c6e82a08d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc4ae266a174a451c7eff4c6e82a08d6">FSMC_PATT2_ATTSET2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db">FSMC_PATT2_ATTSET2_Pos</a>)</td></tr>
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<tr class="memitem:gaab6cd1418de73ee3b214be589912e45f" id="r_gaab6cd1418de73ee3b214be589912e45f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab6cd1418de73ee3b214be589912e45f">FSMC_PATT2_ATTSET2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabc4ae266a174a451c7eff4c6e82a08d6">FSMC_PATT2_ATTSET2_Msk</a></td></tr>
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<tr class="memitem:gaab4718770edfb1b9b96df7410a58f79b" id="r_gaab4718770edfb1b9b96df7410a58f79b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab4718770edfb1b9b96df7410a58f79b">FSMC_PATT2_ATTSET2_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db">FSMC_PATT2_ATTSET2_Pos</a>)</td></tr>
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<tr class="memitem:ga4cde8c8360b22a3fb63615b4274653c9" id="r_ga4cde8c8360b22a3fb63615b4274653c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4cde8c8360b22a3fb63615b4274653c9">FSMC_PATT2_ATTSET2_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db">FSMC_PATT2_ATTSET2_Pos</a>)</td></tr>
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<tr class="memitem:gae80034b8760da9dd1faaf7e326b6002a" id="r_gae80034b8760da9dd1faaf7e326b6002a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae80034b8760da9dd1faaf7e326b6002a">FSMC_PATT2_ATTSET2_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db">FSMC_PATT2_ATTSET2_Pos</a>)</td></tr>
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<tr class="memitem:ga11924ff951b3e939d2d20807901a82bf" id="r_ga11924ff951b3e939d2d20807901a82bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11924ff951b3e939d2d20807901a82bf">FSMC_PATT2_ATTSET2_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db">FSMC_PATT2_ATTSET2_Pos</a>)</td></tr>
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<tr class="memitem:gad1b81efbb998d5e86685075396fd83b0" id="r_gad1b81efbb998d5e86685075396fd83b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1b81efbb998d5e86685075396fd83b0">FSMC_PATT2_ATTSET2_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db">FSMC_PATT2_ATTSET2_Pos</a>)</td></tr>
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<tr class="memitem:ga3e89896b03049ad636484b44c7ecd670" id="r_ga3e89896b03049ad636484b44c7ecd670"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e89896b03049ad636484b44c7ecd670">FSMC_PATT2_ATTSET2_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db">FSMC_PATT2_ATTSET2_Pos</a>)</td></tr>
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<tr class="memitem:gac751391f5acb1f3229ca65a3424d316d" id="r_gac751391f5acb1f3229ca65a3424d316d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac751391f5acb1f3229ca65a3424d316d">FSMC_PATT2_ATTSET2_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db">FSMC_PATT2_ATTSET2_Pos</a>)</td></tr>
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<tr class="memitem:gabb0f3115642332e5aef5cfa1b6b719d8" id="r_gabb0f3115642332e5aef5cfa1b6b719d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb0f3115642332e5aef5cfa1b6b719d8">FSMC_PATT2_ATTSET2_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db">FSMC_PATT2_ATTSET2_Pos</a>)</td></tr>
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<tr class="memitem:gae092c85efe222aa5d2788335544ab0f1" id="r_gae092c85efe222aa5d2788335544ab0f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1">FSMC_PATT2_ATTWAIT2_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga91b82eb626e2249b2365749e2ddd5b82" id="r_ga91b82eb626e2249b2365749e2ddd5b82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91b82eb626e2249b2365749e2ddd5b82">FSMC_PATT2_ATTWAIT2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1">FSMC_PATT2_ATTWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga6fda97184969b04e909ac97d31da48e6" id="r_ga6fda97184969b04e909ac97d31da48e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fda97184969b04e909ac97d31da48e6">FSMC_PATT2_ATTWAIT2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga91b82eb626e2249b2365749e2ddd5b82">FSMC_PATT2_ATTWAIT2_Msk</a></td></tr>
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<tr class="memitem:gaf43a2874230fbe9b87f9495a736b9363" id="r_gaf43a2874230fbe9b87f9495a736b9363"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf43a2874230fbe9b87f9495a736b9363">FSMC_PATT2_ATTWAIT2_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1">FSMC_PATT2_ATTWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:gaad30fbb45343ced8deb9bbc062dba46b" id="r_gaad30fbb45343ced8deb9bbc062dba46b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad30fbb45343ced8deb9bbc062dba46b">FSMC_PATT2_ATTWAIT2_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1">FSMC_PATT2_ATTWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:gae78c7794f66cd2063464ab2e6ef2bd07" id="r_gae78c7794f66cd2063464ab2e6ef2bd07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae78c7794f66cd2063464ab2e6ef2bd07">FSMC_PATT2_ATTWAIT2_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1">FSMC_PATT2_ATTWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga82c2de9009c75560a342122937b25853" id="r_ga82c2de9009c75560a342122937b25853"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82c2de9009c75560a342122937b25853">FSMC_PATT2_ATTWAIT2_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1">FSMC_PATT2_ATTWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:gae80b6a2fc197435f6b50b4ba035fb5fe" id="r_gae80b6a2fc197435f6b50b4ba035fb5fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae80b6a2fc197435f6b50b4ba035fb5fe">FSMC_PATT2_ATTWAIT2_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1">FSMC_PATT2_ATTWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:gac924773c5fcbee73186600247618d10b" id="r_gac924773c5fcbee73186600247618d10b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac924773c5fcbee73186600247618d10b">FSMC_PATT2_ATTWAIT2_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1">FSMC_PATT2_ATTWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga70b22c0b9a32e473f0eb56952ba58d95" id="r_ga70b22c0b9a32e473f0eb56952ba58d95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70b22c0b9a32e473f0eb56952ba58d95">FSMC_PATT2_ATTWAIT2_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1">FSMC_PATT2_ATTWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga2ade8feb15ddcef159ccf3ff55fb0c24" id="r_ga2ade8feb15ddcef159ccf3ff55fb0c24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ade8feb15ddcef159ccf3ff55fb0c24">FSMC_PATT2_ATTWAIT2_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1">FSMC_PATT2_ATTWAIT2_Pos</a>)</td></tr>
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<tr class="memitem:ga82a9f758e7aac1ee2529a904e5ae7e62" id="r_ga82a9f758e7aac1ee2529a904e5ae7e62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62">FSMC_PATT2_ATTHOLD2_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga836b8150e0ee69c3acc4e1330ad8c9f2" id="r_ga836b8150e0ee69c3acc4e1330ad8c9f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga836b8150e0ee69c3acc4e1330ad8c9f2">FSMC_PATT2_ATTHOLD2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62">FSMC_PATT2_ATTHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:gad007c3c6fbef432a5e6bb08bd6e0b1ce" id="r_gad007c3c6fbef432a5e6bb08bd6e0b1ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad007c3c6fbef432a5e6bb08bd6e0b1ce">FSMC_PATT2_ATTHOLD2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga836b8150e0ee69c3acc4e1330ad8c9f2">FSMC_PATT2_ATTHOLD2_Msk</a></td></tr>
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<tr class="memitem:ga5b5e19eb38592e84b9c0f3f57df51892" id="r_ga5b5e19eb38592e84b9c0f3f57df51892"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b5e19eb38592e84b9c0f3f57df51892">FSMC_PATT2_ATTHOLD2_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62">FSMC_PATT2_ATTHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:ga13dface112bf1300689a4f00ba31abac" id="r_ga13dface112bf1300689a4f00ba31abac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13dface112bf1300689a4f00ba31abac">FSMC_PATT2_ATTHOLD2_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62">FSMC_PATT2_ATTHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:gaea0e1b34ac27f20c85db0f96eaeff994" id="r_gaea0e1b34ac27f20c85db0f96eaeff994"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea0e1b34ac27f20c85db0f96eaeff994">FSMC_PATT2_ATTHOLD2_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62">FSMC_PATT2_ATTHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:ga1582860673c5e72f9441095d5af7b8ad" id="r_ga1582860673c5e72f9441095d5af7b8ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1582860673c5e72f9441095d5af7b8ad">FSMC_PATT2_ATTHOLD2_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62">FSMC_PATT2_ATTHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:gacdd679f3b80617291639cafcdd8f77d1" id="r_gacdd679f3b80617291639cafcdd8f77d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdd679f3b80617291639cafcdd8f77d1">FSMC_PATT2_ATTHOLD2_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62">FSMC_PATT2_ATTHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:ga34e89cd935ec26279bc9876d9dd07b07" id="r_ga34e89cd935ec26279bc9876d9dd07b07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34e89cd935ec26279bc9876d9dd07b07">FSMC_PATT2_ATTHOLD2_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62">FSMC_PATT2_ATTHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:ga12c42d6d5746ef8d763d36b04f6e4644" id="r_ga12c42d6d5746ef8d763d36b04f6e4644"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12c42d6d5746ef8d763d36b04f6e4644">FSMC_PATT2_ATTHOLD2_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62">FSMC_PATT2_ATTHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:ga93558ba1372a3709316b4734160b3874" id="r_ga93558ba1372a3709316b4734160b3874"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93558ba1372a3709316b4734160b3874">FSMC_PATT2_ATTHOLD2_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62">FSMC_PATT2_ATTHOLD2_Pos</a>)</td></tr>
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<tr class="memitem:ga5a79c090eb6e9372f579f1912d266a51" id="r_ga5a79c090eb6e9372f579f1912d266a51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51">FSMC_PATT2_ATTHIZ2_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga68a00587d76421282a4c27b05ab794e4" id="r_ga68a00587d76421282a4c27b05ab794e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68a00587d76421282a4c27b05ab794e4">FSMC_PATT2_ATTHIZ2_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51">FSMC_PATT2_ATTHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:gae2726cd505612675158551fd9eed763f" id="r_gae2726cd505612675158551fd9eed763f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2726cd505612675158551fd9eed763f">FSMC_PATT2_ATTHIZ2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga68a00587d76421282a4c27b05ab794e4">FSMC_PATT2_ATTHIZ2_Msk</a></td></tr>
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<tr class="memitem:gae1ff9b8faa8372116ca931826d18a9c7" id="r_gae1ff9b8faa8372116ca931826d18a9c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1ff9b8faa8372116ca931826d18a9c7">FSMC_PATT2_ATTHIZ2_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51">FSMC_PATT2_ATTHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:gaac4081b55783073164985488c9d4d6b8" id="r_gaac4081b55783073164985488c9d4d6b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac4081b55783073164985488c9d4d6b8">FSMC_PATT2_ATTHIZ2_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51">FSMC_PATT2_ATTHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:gaa3cc10b4217452bae11c69ed9f6f1844" id="r_gaa3cc10b4217452bae11c69ed9f6f1844"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3cc10b4217452bae11c69ed9f6f1844">FSMC_PATT2_ATTHIZ2_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51">FSMC_PATT2_ATTHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:ga93e2929a1bcde578f374bbebaa9482d1" id="r_ga93e2929a1bcde578f374bbebaa9482d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93e2929a1bcde578f374bbebaa9482d1">FSMC_PATT2_ATTHIZ2_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51">FSMC_PATT2_ATTHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:gac536419b5ef258fa3f9140387e2f134f" id="r_gac536419b5ef258fa3f9140387e2f134f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac536419b5ef258fa3f9140387e2f134f">FSMC_PATT2_ATTHIZ2_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51">FSMC_PATT2_ATTHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:ga5deab3153671ff06832dd651372f9ca7" id="r_ga5deab3153671ff06832dd651372f9ca7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5deab3153671ff06832dd651372f9ca7">FSMC_PATT2_ATTHIZ2_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51">FSMC_PATT2_ATTHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:ga047723a357976aca5bdf6575327986d2" id="r_ga047723a357976aca5bdf6575327986d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga047723a357976aca5bdf6575327986d2">FSMC_PATT2_ATTHIZ2_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51">FSMC_PATT2_ATTHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:ga859a5af02e12a11e7548085e9e186547" id="r_ga859a5af02e12a11e7548085e9e186547"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga859a5af02e12a11e7548085e9e186547">FSMC_PATT2_ATTHIZ2_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51">FSMC_PATT2_ATTHIZ2_Pos</a>)</td></tr>
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<tr class="memitem:ga5ec2d77c99acc018d13e3f95ef8072b4" id="r_ga5ec2d77c99acc018d13e3f95ef8072b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4">FSMC_PATT3_ATTSET3_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga7ea2296ea7aafbc8aadd589669dfb638" id="r_ga7ea2296ea7aafbc8aadd589669dfb638"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ea2296ea7aafbc8aadd589669dfb638">FSMC_PATT3_ATTSET3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4">FSMC_PATT3_ATTSET3_Pos</a>)</td></tr>
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<tr class="memitem:gae0487c57e948411f16c3a35927e60dd5" id="r_gae0487c57e948411f16c3a35927e60dd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0487c57e948411f16c3a35927e60dd5">FSMC_PATT3_ATTSET3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ea2296ea7aafbc8aadd589669dfb638">FSMC_PATT3_ATTSET3_Msk</a></td></tr>
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<tr class="memitem:ga0e68a5b1bb5996422eac084d586359d4" id="r_ga0e68a5b1bb5996422eac084d586359d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e68a5b1bb5996422eac084d586359d4">FSMC_PATT3_ATTSET3_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4">FSMC_PATT3_ATTSET3_Pos</a>)</td></tr>
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<tr class="separator:ga0e68a5b1bb5996422eac084d586359d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d8bd09ad36ab8cae67f87cb930ea428" id="r_ga2d8bd09ad36ab8cae67f87cb930ea428"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d8bd09ad36ab8cae67f87cb930ea428">FSMC_PATT3_ATTSET3_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4">FSMC_PATT3_ATTSET3_Pos</a>)</td></tr>
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<tr class="memitem:ga29b9389601899ce2731c612ad05d9a96" id="r_ga29b9389601899ce2731c612ad05d9a96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29b9389601899ce2731c612ad05d9a96">FSMC_PATT3_ATTSET3_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4">FSMC_PATT3_ATTSET3_Pos</a>)</td></tr>
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<tr class="memitem:ga97893656a7b65ec5420382de0b264a11" id="r_ga97893656a7b65ec5420382de0b264a11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97893656a7b65ec5420382de0b264a11">FSMC_PATT3_ATTSET3_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4">FSMC_PATT3_ATTSET3_Pos</a>)</td></tr>
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<tr class="memitem:ga9a6993a1cc304b9300bdc365c2827d43" id="r_ga9a6993a1cc304b9300bdc365c2827d43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a6993a1cc304b9300bdc365c2827d43">FSMC_PATT3_ATTSET3_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4">FSMC_PATT3_ATTSET3_Pos</a>)</td></tr>
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<tr class="memitem:ga8cf65f61ce823183c3866607cab6bd09" id="r_ga8cf65f61ce823183c3866607cab6bd09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cf65f61ce823183c3866607cab6bd09">FSMC_PATT3_ATTSET3_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4">FSMC_PATT3_ATTSET3_Pos</a>)</td></tr>
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<tr class="memitem:gab2d5a3dd16094a6279766692694aa16b" id="r_gab2d5a3dd16094a6279766692694aa16b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2d5a3dd16094a6279766692694aa16b">FSMC_PATT3_ATTSET3_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4">FSMC_PATT3_ATTSET3_Pos</a>)</td></tr>
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<tr class="memitem:ga7668853b7956cdb13fd73ed10faf4526" id="r_ga7668853b7956cdb13fd73ed10faf4526"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7668853b7956cdb13fd73ed10faf4526">FSMC_PATT3_ATTSET3_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4">FSMC_PATT3_ATTSET3_Pos</a>)</td></tr>
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<tr class="memitem:gac9a5135aee8bd8f89325962d2598aaae" id="r_gac9a5135aee8bd8f89325962d2598aaae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae">FSMC_PATT3_ATTWAIT3_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga93f4da8f79e8595a22f0089aa1a3085b" id="r_ga93f4da8f79e8595a22f0089aa1a3085b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93f4da8f79e8595a22f0089aa1a3085b">FSMC_PATT3_ATTWAIT3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae">FSMC_PATT3_ATTWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:gad8aaf4c77a663cab07ac6c365a271599" id="r_gad8aaf4c77a663cab07ac6c365a271599"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8aaf4c77a663cab07ac6c365a271599">FSMC_PATT3_ATTWAIT3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga93f4da8f79e8595a22f0089aa1a3085b">FSMC_PATT3_ATTWAIT3_Msk</a></td></tr>
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<tr class="memitem:gac5c5500a07e7885de5c372c55f147836" id="r_gac5c5500a07e7885de5c372c55f147836"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5c5500a07e7885de5c372c55f147836">FSMC_PATT3_ATTWAIT3_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae">FSMC_PATT3_ATTWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:gaddddbd0a403b2aeefcfdb28a7da56bf0" id="r_gaddddbd0a403b2aeefcfdb28a7da56bf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddddbd0a403b2aeefcfdb28a7da56bf0">FSMC_PATT3_ATTWAIT3_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae">FSMC_PATT3_ATTWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:gac34cbe7e282e1074e6c4b9645e48db2f" id="r_gac34cbe7e282e1074e6c4b9645e48db2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac34cbe7e282e1074e6c4b9645e48db2f">FSMC_PATT3_ATTWAIT3_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae">FSMC_PATT3_ATTWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:ga771f2a5acde98a9760eb8a1338f416a3" id="r_ga771f2a5acde98a9760eb8a1338f416a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga771f2a5acde98a9760eb8a1338f416a3">FSMC_PATT3_ATTWAIT3_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae">FSMC_PATT3_ATTWAIT3_Pos</a>)</td></tr>
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<tr class="separator:ga771f2a5acde98a9760eb8a1338f416a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bcc944836a379b2b878d5129ff94ddb" id="r_ga1bcc944836a379b2b878d5129ff94ddb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bcc944836a379b2b878d5129ff94ddb">FSMC_PATT3_ATTWAIT3_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae">FSMC_PATT3_ATTWAIT3_Pos</a>)</td></tr>
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<tr class="separator:ga1bcc944836a379b2b878d5129ff94ddb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf722482193ca6a1bf90f17af567e019" id="r_gacf722482193ca6a1bf90f17af567e019"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf722482193ca6a1bf90f17af567e019">FSMC_PATT3_ATTWAIT3_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae">FSMC_PATT3_ATTWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:gac2cc3ce135f309f7574f0c3d1a0ffe88" id="r_gac2cc3ce135f309f7574f0c3d1a0ffe88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2cc3ce135f309f7574f0c3d1a0ffe88">FSMC_PATT3_ATTWAIT3_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae">FSMC_PATT3_ATTWAIT3_Pos</a>)</td></tr>
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<tr class="memitem:gaa66342cc1db5dcad99153b5a2f22140e" id="r_gaa66342cc1db5dcad99153b5a2f22140e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa66342cc1db5dcad99153b5a2f22140e">FSMC_PATT3_ATTWAIT3_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae">FSMC_PATT3_ATTWAIT3_Pos</a>)</td></tr>
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<tr class="separator:gaa66342cc1db5dcad99153b5a2f22140e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05923158d59d724b0beec495f7ea9fcf" id="r_ga05923158d59d724b0beec495f7ea9fcf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf">FSMC_PATT3_ATTHOLD3_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga9cd55c17fa5ff544f7d19482034dd6de" id="r_ga9cd55c17fa5ff544f7d19482034dd6de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cd55c17fa5ff544f7d19482034dd6de">FSMC_PATT3_ATTHOLD3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf">FSMC_PATT3_ATTHOLD3_Pos</a>)</td></tr>
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<tr class="memitem:gab3a2e634d0f5e3c9716c0910e1efda60" id="r_gab3a2e634d0f5e3c9716c0910e1efda60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3a2e634d0f5e3c9716c0910e1efda60">FSMC_PATT3_ATTHOLD3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9cd55c17fa5ff544f7d19482034dd6de">FSMC_PATT3_ATTHOLD3_Msk</a></td></tr>
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<tr class="memitem:gad34a9f1b84d670c4132c56fa30ca26f0" id="r_gad34a9f1b84d670c4132c56fa30ca26f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad34a9f1b84d670c4132c56fa30ca26f0">FSMC_PATT3_ATTHOLD3_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf">FSMC_PATT3_ATTHOLD3_Pos</a>)</td></tr>
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<tr class="memitem:ga5b2ed392d654694fc330c6721bed5728" id="r_ga5b2ed392d654694fc330c6721bed5728"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b2ed392d654694fc330c6721bed5728">FSMC_PATT3_ATTHOLD3_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf">FSMC_PATT3_ATTHOLD3_Pos</a>)</td></tr>
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<tr class="memitem:ga679d3ea50788981dac810ec62bc372f0" id="r_ga679d3ea50788981dac810ec62bc372f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga679d3ea50788981dac810ec62bc372f0">FSMC_PATT3_ATTHOLD3_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf">FSMC_PATT3_ATTHOLD3_Pos</a>)</td></tr>
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<tr class="separator:ga679d3ea50788981dac810ec62bc372f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75d74cf52f238826e87d3a3c27b52acc" id="r_ga75d74cf52f238826e87d3a3c27b52acc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75d74cf52f238826e87d3a3c27b52acc">FSMC_PATT3_ATTHOLD3_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf">FSMC_PATT3_ATTHOLD3_Pos</a>)</td></tr>
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<tr class="separator:ga75d74cf52f238826e87d3a3c27b52acc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8d656d40279e1655a6682dcc2762e92" id="r_gaa8d656d40279e1655a6682dcc2762e92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8d656d40279e1655a6682dcc2762e92">FSMC_PATT3_ATTHOLD3_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf">FSMC_PATT3_ATTHOLD3_Pos</a>)</td></tr>
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<tr class="separator:gaa8d656d40279e1655a6682dcc2762e92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafee75f2fcf37e20e983732f258f85371" id="r_gafee75f2fcf37e20e983732f258f85371"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafee75f2fcf37e20e983732f258f85371">FSMC_PATT3_ATTHOLD3_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf">FSMC_PATT3_ATTHOLD3_Pos</a>)</td></tr>
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<tr class="separator:gafee75f2fcf37e20e983732f258f85371"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga777b93e1e3c802ede605644d3ff3bba7" id="r_ga777b93e1e3c802ede605644d3ff3bba7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga777b93e1e3c802ede605644d3ff3bba7">FSMC_PATT3_ATTHOLD3_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf">FSMC_PATT3_ATTHOLD3_Pos</a>)</td></tr>
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<tr class="separator:ga777b93e1e3c802ede605644d3ff3bba7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39acada8d54a7a14d3838d042397bd74" id="r_ga39acada8d54a7a14d3838d042397bd74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39acada8d54a7a14d3838d042397bd74">FSMC_PATT3_ATTHOLD3_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf">FSMC_PATT3_ATTHOLD3_Pos</a>)</td></tr>
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<tr class="separator:ga39acada8d54a7a14d3838d042397bd74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaae5fdcc70300b0e9c7b69d31c9173b5" id="r_gaaae5fdcc70300b0e9c7b69d31c9173b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5">FSMC_PATT3_ATTHIZ3_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaaae5fdcc70300b0e9c7b69d31c9173b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbbd7b49755e0e7052d77f774d72ca18" id="r_gafbbd7b49755e0e7052d77f774d72ca18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbbd7b49755e0e7052d77f774d72ca18">FSMC_PATT3_ATTHIZ3_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5">FSMC_PATT3_ATTHIZ3_Pos</a>)</td></tr>
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<tr class="separator:gafbbd7b49755e0e7052d77f774d72ca18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea9d34b131aa7db353eef060ca37788c" id="r_gaea9d34b131aa7db353eef060ca37788c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea9d34b131aa7db353eef060ca37788c">FSMC_PATT3_ATTHIZ3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafbbd7b49755e0e7052d77f774d72ca18">FSMC_PATT3_ATTHIZ3_Msk</a></td></tr>
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<tr class="memitem:ga5bc6736af23f6f033568e0085cd19964" id="r_ga5bc6736af23f6f033568e0085cd19964"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bc6736af23f6f033568e0085cd19964">FSMC_PATT3_ATTHIZ3_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5">FSMC_PATT3_ATTHIZ3_Pos</a>)</td></tr>
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<tr class="separator:ga5bc6736af23f6f033568e0085cd19964"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41270d0ae8670f39b886b49e47e8195b" id="r_ga41270d0ae8670f39b886b49e47e8195b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41270d0ae8670f39b886b49e47e8195b">FSMC_PATT3_ATTHIZ3_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5">FSMC_PATT3_ATTHIZ3_Pos</a>)</td></tr>
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<tr class="separator:ga41270d0ae8670f39b886b49e47e8195b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga988ec453492aafacf205895c5398caf2" id="r_ga988ec453492aafacf205895c5398caf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga988ec453492aafacf205895c5398caf2">FSMC_PATT3_ATTHIZ3_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5">FSMC_PATT3_ATTHIZ3_Pos</a>)</td></tr>
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<tr class="memitem:ga48885375147c060687bbccc6a234ce39" id="r_ga48885375147c060687bbccc6a234ce39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48885375147c060687bbccc6a234ce39">FSMC_PATT3_ATTHIZ3_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5">FSMC_PATT3_ATTHIZ3_Pos</a>)</td></tr>
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<tr class="separator:ga48885375147c060687bbccc6a234ce39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ea193881223470d7b6a6ca3e3474a84" id="r_ga5ea193881223470d7b6a6ca3e3474a84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ea193881223470d7b6a6ca3e3474a84">FSMC_PATT3_ATTHIZ3_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5">FSMC_PATT3_ATTHIZ3_Pos</a>)</td></tr>
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<tr class="separator:ga5ea193881223470d7b6a6ca3e3474a84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ab1f4cb68cfb8717d2b29e3a84987b1" id="r_ga7ab1f4cb68cfb8717d2b29e3a84987b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ab1f4cb68cfb8717d2b29e3a84987b1">FSMC_PATT3_ATTHIZ3_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5">FSMC_PATT3_ATTHIZ3_Pos</a>)</td></tr>
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<tr class="memitem:ga44fd348b342ec248b821123f3310f475" id="r_ga44fd348b342ec248b821123f3310f475"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44fd348b342ec248b821123f3310f475">FSMC_PATT3_ATTHIZ3_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5">FSMC_PATT3_ATTHIZ3_Pos</a>)</td></tr>
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<tr class="separator:ga44fd348b342ec248b821123f3310f475"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ff1a3acc9bbab229000d48845ea1863" id="r_ga0ff1a3acc9bbab229000d48845ea1863"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff1a3acc9bbab229000d48845ea1863">FSMC_PATT3_ATTHIZ3_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5">FSMC_PATT3_ATTHIZ3_Pos</a>)</td></tr>
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<tr class="separator:ga0ff1a3acc9bbab229000d48845ea1863"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02c498b211356b2ff396a8f793ae1f88" id="r_ga02c498b211356b2ff396a8f793ae1f88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88">FSMC_PATT4_ATTSET4_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga02c498b211356b2ff396a8f793ae1f88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8ee09881a3a83d040c49e7ec91e16f8" id="r_gac8ee09881a3a83d040c49e7ec91e16f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8ee09881a3a83d040c49e7ec91e16f8">FSMC_PATT4_ATTSET4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88">FSMC_PATT4_ATTSET4_Pos</a>)</td></tr>
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<tr class="separator:gac8ee09881a3a83d040c49e7ec91e16f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f4d8fb0d47b4a3fddf55c2532dd3159" id="r_ga7f4d8fb0d47b4a3fddf55c2532dd3159"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f4d8fb0d47b4a3fddf55c2532dd3159">FSMC_PATT4_ATTSET4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac8ee09881a3a83d040c49e7ec91e16f8">FSMC_PATT4_ATTSET4_Msk</a></td></tr>
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<tr class="separator:ga7f4d8fb0d47b4a3fddf55c2532dd3159"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1dac8bcf03610eb2d43b557f4d81532a" id="r_ga1dac8bcf03610eb2d43b557f4d81532a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1dac8bcf03610eb2d43b557f4d81532a">FSMC_PATT4_ATTSET4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88">FSMC_PATT4_ATTSET4_Pos</a>)</td></tr>
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<tr class="separator:ga1dac8bcf03610eb2d43b557f4d81532a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac2576c2a95871cbf9babd0778372571" id="r_gaac2576c2a95871cbf9babd0778372571"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac2576c2a95871cbf9babd0778372571">FSMC_PATT4_ATTSET4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88">FSMC_PATT4_ATTSET4_Pos</a>)</td></tr>
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<tr class="memitem:ga88e760bbe9714ac07f381de3af0abc36" id="r_ga88e760bbe9714ac07f381de3af0abc36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88e760bbe9714ac07f381de3af0abc36">FSMC_PATT4_ATTSET4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88">FSMC_PATT4_ATTSET4_Pos</a>)</td></tr>
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<tr class="memitem:ga4b472fd4848733a921998f0305b5bc02" id="r_ga4b472fd4848733a921998f0305b5bc02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b472fd4848733a921998f0305b5bc02">FSMC_PATT4_ATTSET4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88">FSMC_PATT4_ATTSET4_Pos</a>)</td></tr>
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<tr class="memitem:gae7d0c69190a0d78fedc875c3dc6b9037" id="r_gae7d0c69190a0d78fedc875c3dc6b9037"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7d0c69190a0d78fedc875c3dc6b9037">FSMC_PATT4_ATTSET4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88">FSMC_PATT4_ATTSET4_Pos</a>)</td></tr>
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<tr class="separator:gae7d0c69190a0d78fedc875c3dc6b9037"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga168c6f16be9721a5ea0e31230bd1939b" id="r_ga168c6f16be9721a5ea0e31230bd1939b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga168c6f16be9721a5ea0e31230bd1939b">FSMC_PATT4_ATTSET4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88">FSMC_PATT4_ATTSET4_Pos</a>)</td></tr>
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<tr class="memitem:ga72fe744c036b2acc4fff8733ac48b0ae" id="r_ga72fe744c036b2acc4fff8733ac48b0ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72fe744c036b2acc4fff8733ac48b0ae">FSMC_PATT4_ATTSET4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88">FSMC_PATT4_ATTSET4_Pos</a>)</td></tr>
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<tr class="separator:ga72fe744c036b2acc4fff8733ac48b0ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4529b17de7cb4eeeff25496620978adc" id="r_ga4529b17de7cb4eeeff25496620978adc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4529b17de7cb4eeeff25496620978adc">FSMC_PATT4_ATTSET4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88">FSMC_PATT4_ATTSET4_Pos</a>)</td></tr>
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<tr class="separator:ga4529b17de7cb4eeeff25496620978adc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11a97fde0b98868526b7ea722e3185d3" id="r_ga11a97fde0b98868526b7ea722e3185d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3">FSMC_PATT4_ATTWAIT4_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga11a97fde0b98868526b7ea722e3185d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9b0b756ec9357585c52037f88e87c00" id="r_gab9b0b756ec9357585c52037f88e87c00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9b0b756ec9357585c52037f88e87c00">FSMC_PATT4_ATTWAIT4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3">FSMC_PATT4_ATTWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga01edeaedc31867997a188fa89cab2ec0" id="r_ga01edeaedc31867997a188fa89cab2ec0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01edeaedc31867997a188fa89cab2ec0">FSMC_PATT4_ATTWAIT4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9b0b756ec9357585c52037f88e87c00">FSMC_PATT4_ATTWAIT4_Msk</a></td></tr>
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<tr class="memitem:ga5da7db34cd23f3126f224a0b845a66a8" id="r_ga5da7db34cd23f3126f224a0b845a66a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5da7db34cd23f3126f224a0b845a66a8">FSMC_PATT4_ATTWAIT4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3">FSMC_PATT4_ATTWAIT4_Pos</a>)</td></tr>
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<tr class="separator:ga5da7db34cd23f3126f224a0b845a66a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14644aa2ed55afe2094015d74843a994" id="r_ga14644aa2ed55afe2094015d74843a994"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14644aa2ed55afe2094015d74843a994">FSMC_PATT4_ATTWAIT4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3">FSMC_PATT4_ATTWAIT4_Pos</a>)</td></tr>
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<tr class="separator:ga14644aa2ed55afe2094015d74843a994"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1023d5ae8fab70e7fdfbaff4ed46657" id="r_gaf1023d5ae8fab70e7fdfbaff4ed46657"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1023d5ae8fab70e7fdfbaff4ed46657">FSMC_PATT4_ATTWAIT4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3">FSMC_PATT4_ATTWAIT4_Pos</a>)</td></tr>
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<tr class="separator:gaf1023d5ae8fab70e7fdfbaff4ed46657"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga906c9684ffcd8f0f9222cbfd0e21885a" id="r_ga906c9684ffcd8f0f9222cbfd0e21885a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga906c9684ffcd8f0f9222cbfd0e21885a">FSMC_PATT4_ATTWAIT4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3">FSMC_PATT4_ATTWAIT4_Pos</a>)</td></tr>
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<tr class="separator:ga906c9684ffcd8f0f9222cbfd0e21885a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8d341a7448f645a2f849e591515f020" id="r_gae8d341a7448f645a2f849e591515f020"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8d341a7448f645a2f849e591515f020">FSMC_PATT4_ATTWAIT4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3">FSMC_PATT4_ATTWAIT4_Pos</a>)</td></tr>
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<tr class="separator:gae8d341a7448f645a2f849e591515f020"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf278272c5fdaa8fa7c84e1c095690632" id="r_gaf278272c5fdaa8fa7c84e1c095690632"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf278272c5fdaa8fa7c84e1c095690632">FSMC_PATT4_ATTWAIT4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3">FSMC_PATT4_ATTWAIT4_Pos</a>)</td></tr>
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<tr class="separator:gaf278272c5fdaa8fa7c84e1c095690632"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3126347e126717a761af0b6e44b9d72d" id="r_ga3126347e126717a761af0b6e44b9d72d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3126347e126717a761af0b6e44b9d72d">FSMC_PATT4_ATTWAIT4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3">FSMC_PATT4_ATTWAIT4_Pos</a>)</td></tr>
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<tr class="separator:ga3126347e126717a761af0b6e44b9d72d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34afb78710ca450ac7065f0bc263075c" id="r_ga34afb78710ca450ac7065f0bc263075c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34afb78710ca450ac7065f0bc263075c">FSMC_PATT4_ATTWAIT4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3">FSMC_PATT4_ATTWAIT4_Pos</a>)</td></tr>
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<tr class="separator:ga34afb78710ca450ac7065f0bc263075c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga443220812626d4a02edc701390f33a3d" id="r_ga443220812626d4a02edc701390f33a3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d">FSMC_PATT4_ATTHOLD4_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga443220812626d4a02edc701390f33a3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0108d421a275b527d8cb978b6d9685ce" id="r_ga0108d421a275b527d8cb978b6d9685ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0108d421a275b527d8cb978b6d9685ce">FSMC_PATT4_ATTHOLD4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d">FSMC_PATT4_ATTHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga0108d421a275b527d8cb978b6d9685ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bf06c395d55c775b4fbe202bac517a6" id="r_ga0bf06c395d55c775b4fbe202bac517a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bf06c395d55c775b4fbe202bac517a6">FSMC_PATT4_ATTHOLD4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0108d421a275b527d8cb978b6d9685ce">FSMC_PATT4_ATTHOLD4_Msk</a></td></tr>
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<tr class="separator:ga0bf06c395d55c775b4fbe202bac517a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5c97b102bd1f2b61dcfb793c0d61d66" id="r_gad5c97b102bd1f2b61dcfb793c0d61d66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5c97b102bd1f2b61dcfb793c0d61d66">FSMC_PATT4_ATTHOLD4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d">FSMC_PATT4_ATTHOLD4_Pos</a>)</td></tr>
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<tr class="separator:gad5c97b102bd1f2b61dcfb793c0d61d66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga738c8d87ebcdff68725a54ff7f39675d" id="r_ga738c8d87ebcdff68725a54ff7f39675d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga738c8d87ebcdff68725a54ff7f39675d">FSMC_PATT4_ATTHOLD4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d">FSMC_PATT4_ATTHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga738c8d87ebcdff68725a54ff7f39675d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d9610198e4710ca394e3aeb32aa229f" id="r_ga6d9610198e4710ca394e3aeb32aa229f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d9610198e4710ca394e3aeb32aa229f">FSMC_PATT4_ATTHOLD4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d">FSMC_PATT4_ATTHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga6d9610198e4710ca394e3aeb32aa229f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd14059e9f658f37b3a1f18786395717" id="r_gadd14059e9f658f37b3a1f18786395717"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd14059e9f658f37b3a1f18786395717">FSMC_PATT4_ATTHOLD4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d">FSMC_PATT4_ATTHOLD4_Pos</a>)</td></tr>
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<tr class="separator:gadd14059e9f658f37b3a1f18786395717"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a39fa40e2d4990097e31b47ad85283a" id="r_ga7a39fa40e2d4990097e31b47ad85283a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a39fa40e2d4990097e31b47ad85283a">FSMC_PATT4_ATTHOLD4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d">FSMC_PATT4_ATTHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga7a39fa40e2d4990097e31b47ad85283a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga239e412f20305d58416f10a79e253a87" id="r_ga239e412f20305d58416f10a79e253a87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga239e412f20305d58416f10a79e253a87">FSMC_PATT4_ATTHOLD4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d">FSMC_PATT4_ATTHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga239e412f20305d58416f10a79e253a87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff1aac62acdf71077ee4a9e8e9e6d2d6" id="r_gaff1aac62acdf71077ee4a9e8e9e6d2d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff1aac62acdf71077ee4a9e8e9e6d2d6">FSMC_PATT4_ATTHOLD4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d">FSMC_PATT4_ATTHOLD4_Pos</a>)</td></tr>
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<tr class="separator:gaff1aac62acdf71077ee4a9e8e9e6d2d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga836fd2ad42b0c9f6d0eb651589d04123" id="r_ga836fd2ad42b0c9f6d0eb651589d04123"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga836fd2ad42b0c9f6d0eb651589d04123">FSMC_PATT4_ATTHOLD4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d">FSMC_PATT4_ATTHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga836fd2ad42b0c9f6d0eb651589d04123"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7e76eb10b9d92b8d3d88d4d026679fb" id="r_gaa7e76eb10b9d92b8d3d88d4d026679fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb">FSMC_PATT4_ATTHIZ4_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaa7e76eb10b9d92b8d3d88d4d026679fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac10548dc39d989f970e3397287096126" id="r_gac10548dc39d989f970e3397287096126"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac10548dc39d989f970e3397287096126">FSMC_PATT4_ATTHIZ4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb">FSMC_PATT4_ATTHIZ4_Pos</a>)</td></tr>
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<tr class="separator:gac10548dc39d989f970e3397287096126"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35948e4e9e5ce9d674e9e70ca2aeafe3" id="r_ga35948e4e9e5ce9d674e9e70ca2aeafe3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35948e4e9e5ce9d674e9e70ca2aeafe3">FSMC_PATT4_ATTHIZ4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac10548dc39d989f970e3397287096126">FSMC_PATT4_ATTHIZ4_Msk</a></td></tr>
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<tr class="memitem:ga5b746d7b655f6379af4dd4d5ba842492" id="r_ga5b746d7b655f6379af4dd4d5ba842492"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b746d7b655f6379af4dd4d5ba842492">FSMC_PATT4_ATTHIZ4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb">FSMC_PATT4_ATTHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:gac2dd87929111fc0c888dd7c311f8eba3" id="r_gac2dd87929111fc0c888dd7c311f8eba3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2dd87929111fc0c888dd7c311f8eba3">FSMC_PATT4_ATTHIZ4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb">FSMC_PATT4_ATTHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga353c0709e22a06998f05b908a597f525" id="r_ga353c0709e22a06998f05b908a597f525"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga353c0709e22a06998f05b908a597f525">FSMC_PATT4_ATTHIZ4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb">FSMC_PATT4_ATTHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:gaa777a5d42ac1e36044d7b18ffdd61a21" id="r_gaa777a5d42ac1e36044d7b18ffdd61a21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa777a5d42ac1e36044d7b18ffdd61a21">FSMC_PATT4_ATTHIZ4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb">FSMC_PATT4_ATTHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga65c1778d08bfe2a40961f6acf023b9d4" id="r_ga65c1778d08bfe2a40961f6acf023b9d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65c1778d08bfe2a40961f6acf023b9d4">FSMC_PATT4_ATTHIZ4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb">FSMC_PATT4_ATTHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:gaadb7001986c9a4c28052b46657ad7a7e" id="r_gaadb7001986c9a4c28052b46657ad7a7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadb7001986c9a4c28052b46657ad7a7e">FSMC_PATT4_ATTHIZ4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb">FSMC_PATT4_ATTHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:gaa11a8d896354bd1c6645ac096db8e065" id="r_gaa11a8d896354bd1c6645ac096db8e065"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa11a8d896354bd1c6645ac096db8e065">FSMC_PATT4_ATTHIZ4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb">FSMC_PATT4_ATTHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga1a054f48705ec3fef0686c576f414f29" id="r_ga1a054f48705ec3fef0686c576f414f29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a054f48705ec3fef0686c576f414f29">FSMC_PATT4_ATTHIZ4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb">FSMC_PATT4_ATTHIZ4_Pos</a>)</td></tr>
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<tr class="memitem:ga9972446feb353b113f1c31cf6be894e5" id="r_ga9972446feb353b113f1c31cf6be894e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5">FSMC_PIO4_IOSET4_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga3358c18b8b82cd13305ec60101187b5c" id="r_ga3358c18b8b82cd13305ec60101187b5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3358c18b8b82cd13305ec60101187b5c">FSMC_PIO4_IOSET4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5">FSMC_PIO4_IOSET4_Pos</a>)</td></tr>
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<tr class="memitem:gaf14b77f09f496a1325b5384eef54dd4a" id="r_gaf14b77f09f496a1325b5384eef54dd4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf14b77f09f496a1325b5384eef54dd4a">FSMC_PIO4_IOSET4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3358c18b8b82cd13305ec60101187b5c">FSMC_PIO4_IOSET4_Msk</a></td></tr>
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<tr class="memitem:ga29c07a816f3065ae0c9287b6e3e0e967" id="r_ga29c07a816f3065ae0c9287b6e3e0e967"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29c07a816f3065ae0c9287b6e3e0e967">FSMC_PIO4_IOSET4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5">FSMC_PIO4_IOSET4_Pos</a>)</td></tr>
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<tr class="memitem:gac31898a52e172935f354819c50d3ef8d" id="r_gac31898a52e172935f354819c50d3ef8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac31898a52e172935f354819c50d3ef8d">FSMC_PIO4_IOSET4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5">FSMC_PIO4_IOSET4_Pos</a>)</td></tr>
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<tr class="memitem:gaf35797347825725faef495c676269927" id="r_gaf35797347825725faef495c676269927"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf35797347825725faef495c676269927">FSMC_PIO4_IOSET4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5">FSMC_PIO4_IOSET4_Pos</a>)</td></tr>
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<tr class="memitem:gae45109e3dcc3c3a15efd13eddffdd8c9" id="r_gae45109e3dcc3c3a15efd13eddffdd8c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae45109e3dcc3c3a15efd13eddffdd8c9">FSMC_PIO4_IOSET4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5">FSMC_PIO4_IOSET4_Pos</a>)</td></tr>
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<tr class="memitem:ga349e3a58f832fbc9de16955521355c29" id="r_ga349e3a58f832fbc9de16955521355c29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga349e3a58f832fbc9de16955521355c29">FSMC_PIO4_IOSET4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5">FSMC_PIO4_IOSET4_Pos</a>)</td></tr>
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<tr class="memitem:gaf3304545838a6e20742b0203e0cb023a" id="r_gaf3304545838a6e20742b0203e0cb023a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3304545838a6e20742b0203e0cb023a">FSMC_PIO4_IOSET4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5">FSMC_PIO4_IOSET4_Pos</a>)</td></tr>
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<tr class="memitem:ga800ab779078734ca86eedb6c9e77bc57" id="r_ga800ab779078734ca86eedb6c9e77bc57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga800ab779078734ca86eedb6c9e77bc57">FSMC_PIO4_IOSET4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5">FSMC_PIO4_IOSET4_Pos</a>)</td></tr>
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<tr class="memitem:ga7e29b066726c486c6503d417d18904b1" id="r_ga7e29b066726c486c6503d417d18904b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e29b066726c486c6503d417d18904b1">FSMC_PIO4_IOSET4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5">FSMC_PIO4_IOSET4_Pos</a>)</td></tr>
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<tr class="memitem:ga7003102b5d51a06d74a8176ca1299099" id="r_ga7003102b5d51a06d74a8176ca1299099"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099">FSMC_PIO4_IOWAIT4_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gaa4594c1e3df3d2345bf1207cab2de430" id="r_gaa4594c1e3df3d2345bf1207cab2de430"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4594c1e3df3d2345bf1207cab2de430">FSMC_PIO4_IOWAIT4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099">FSMC_PIO4_IOWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga035a0645caab3851714123302dd0af1c" id="r_ga035a0645caab3851714123302dd0af1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga035a0645caab3851714123302dd0af1c">FSMC_PIO4_IOWAIT4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4594c1e3df3d2345bf1207cab2de430">FSMC_PIO4_IOWAIT4_Msk</a></td></tr>
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<tr class="separator:ga035a0645caab3851714123302dd0af1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb868a5bf3d33997c782f296440cabf7" id="r_gafb868a5bf3d33997c782f296440cabf7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb868a5bf3d33997c782f296440cabf7">FSMC_PIO4_IOWAIT4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099">FSMC_PIO4_IOWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:gaaa48c96fedf31c6ab444828d60e471da" id="r_gaaa48c96fedf31c6ab444828d60e471da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa48c96fedf31c6ab444828d60e471da">FSMC_PIO4_IOWAIT4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099">FSMC_PIO4_IOWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga342e42235a123ea11544b1a230b07a75" id="r_ga342e42235a123ea11544b1a230b07a75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga342e42235a123ea11544b1a230b07a75">FSMC_PIO4_IOWAIT4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099">FSMC_PIO4_IOWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga9c012d7c41f51516580766d6ac36d82f" id="r_ga9c012d7c41f51516580766d6ac36d82f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c012d7c41f51516580766d6ac36d82f">FSMC_PIO4_IOWAIT4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099">FSMC_PIO4_IOWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga5331b528505a31a2b39deca7a5ddba02" id="r_ga5331b528505a31a2b39deca7a5ddba02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5331b528505a31a2b39deca7a5ddba02">FSMC_PIO4_IOWAIT4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099">FSMC_PIO4_IOWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:gaabbfbc377efde5170ac484795a0a4215" id="r_gaabbfbc377efde5170ac484795a0a4215"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabbfbc377efde5170ac484795a0a4215">FSMC_PIO4_IOWAIT4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099">FSMC_PIO4_IOWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga0be64ff24a6ccb7eef471ad2ad0e283b" id="r_ga0be64ff24a6ccb7eef471ad2ad0e283b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0be64ff24a6ccb7eef471ad2ad0e283b">FSMC_PIO4_IOWAIT4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099">FSMC_PIO4_IOWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga3e3fc1b8cfa57116c0521cafd7e733cc" id="r_ga3e3fc1b8cfa57116c0521cafd7e733cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e3fc1b8cfa57116c0521cafd7e733cc">FSMC_PIO4_IOWAIT4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099">FSMC_PIO4_IOWAIT4_Pos</a>)</td></tr>
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<tr class="memitem:ga162d7f97cc7753670f748753357fafd2" id="r_ga162d7f97cc7753670f748753357fafd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2">FSMC_PIO4_IOHOLD4_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga162d7f97cc7753670f748753357fafd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cfbf79cf550a6d25af660a9b78ae382" id="r_ga6cfbf79cf550a6d25af660a9b78ae382"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cfbf79cf550a6d25af660a9b78ae382">FSMC_PIO4_IOHOLD4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2">FSMC_PIO4_IOHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:gab55064df0d9fab8a072da6baa7b85878" id="r_gab55064df0d9fab8a072da6baa7b85878"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab55064df0d9fab8a072da6baa7b85878">FSMC_PIO4_IOHOLD4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cfbf79cf550a6d25af660a9b78ae382">FSMC_PIO4_IOHOLD4_Msk</a></td></tr>
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<tr class="separator:gab55064df0d9fab8a072da6baa7b85878"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc1a288b385fcf83bfa95da479d387a4" id="r_gadc1a288b385fcf83bfa95da479d387a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc1a288b385fcf83bfa95da479d387a4">FSMC_PIO4_IOHOLD4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2">FSMC_PIO4_IOHOLD4_Pos</a>)</td></tr>
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<tr class="separator:gadc1a288b385fcf83bfa95da479d387a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga402d7221ee27ce71d1b8bb18539d8307" id="r_ga402d7221ee27ce71d1b8bb18539d8307"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga402d7221ee27ce71d1b8bb18539d8307">FSMC_PIO4_IOHOLD4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2">FSMC_PIO4_IOHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga402d7221ee27ce71d1b8bb18539d8307"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga274c5b835ec95c97c4f1c6ebbf72a096" id="r_ga274c5b835ec95c97c4f1c6ebbf72a096"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga274c5b835ec95c97c4f1c6ebbf72a096">FSMC_PIO4_IOHOLD4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2">FSMC_PIO4_IOHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga274c5b835ec95c97c4f1c6ebbf72a096"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga519b9b4ae5b136769278eb98eb10c3a6" id="r_ga519b9b4ae5b136769278eb98eb10c3a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga519b9b4ae5b136769278eb98eb10c3a6">FSMC_PIO4_IOHOLD4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2">FSMC_PIO4_IOHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga519b9b4ae5b136769278eb98eb10c3a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2d013be2823d9ea9b81f8f76331c11d" id="r_gab2d013be2823d9ea9b81f8f76331c11d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2d013be2823d9ea9b81f8f76331c11d">FSMC_PIO4_IOHOLD4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2">FSMC_PIO4_IOHOLD4_Pos</a>)</td></tr>
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<tr class="separator:gab2d013be2823d9ea9b81f8f76331c11d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a14c965f1ff993e0976aaefe638e2f6" id="r_ga5a14c965f1ff993e0976aaefe638e2f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a14c965f1ff993e0976aaefe638e2f6">FSMC_PIO4_IOHOLD4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2">FSMC_PIO4_IOHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga5a14c965f1ff993e0976aaefe638e2f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49411f21445032ad8eaca19e89d204bc" id="r_ga49411f21445032ad8eaca19e89d204bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49411f21445032ad8eaca19e89d204bc">FSMC_PIO4_IOHOLD4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2">FSMC_PIO4_IOHOLD4_Pos</a>)</td></tr>
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<tr class="memitem:ga323dcc3be986d57d14b794cca0038953" id="r_ga323dcc3be986d57d14b794cca0038953"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga323dcc3be986d57d14b794cca0038953">FSMC_PIO4_IOHOLD4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2">FSMC_PIO4_IOHOLD4_Pos</a>)</td></tr>
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<tr class="separator:ga323dcc3be986d57d14b794cca0038953"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeaac653ebed9641460a4275d30047630" id="r_gaeaac653ebed9641460a4275d30047630"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630">FSMC_PIO4_IOHIZ4_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaeaac653ebed9641460a4275d30047630"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b36d517941428d62268b10e8058abf4" id="r_ga0b36d517941428d62268b10e8058abf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b36d517941428d62268b10e8058abf4">FSMC_PIO4_IOHIZ4_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630">FSMC_PIO4_IOHIZ4_Pos</a>)</td></tr>
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<tr class="separator:ga0b36d517941428d62268b10e8058abf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4cce93379430df64fd697ad772bc477d" id="r_ga4cce93379430df64fd697ad772bc477d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4cce93379430df64fd697ad772bc477d">FSMC_PIO4_IOHIZ4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b36d517941428d62268b10e8058abf4">FSMC_PIO4_IOHIZ4_Msk</a></td></tr>
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<tr class="separator:ga4cce93379430df64fd697ad772bc477d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf3b5c59e3eb4e259ddb722b1e536e5c" id="r_gaaf3b5c59e3eb4e259ddb722b1e536e5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf3b5c59e3eb4e259ddb722b1e536e5c">FSMC_PIO4_IOHIZ4_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630">FSMC_PIO4_IOHIZ4_Pos</a>)</td></tr>
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<tr class="separator:gaaf3b5c59e3eb4e259ddb722b1e536e5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e8c66264d4ec7b69de613cb528cfee2" id="r_ga3e8c66264d4ec7b69de613cb528cfee2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e8c66264d4ec7b69de613cb528cfee2">FSMC_PIO4_IOHIZ4_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630">FSMC_PIO4_IOHIZ4_Pos</a>)</td></tr>
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<tr class="separator:ga3e8c66264d4ec7b69de613cb528cfee2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab943b8acd274a8892e691ffab36a6a21" id="r_gab943b8acd274a8892e691ffab36a6a21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab943b8acd274a8892e691ffab36a6a21">FSMC_PIO4_IOHIZ4_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630">FSMC_PIO4_IOHIZ4_Pos</a>)</td></tr>
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<tr class="separator:gab943b8acd274a8892e691ffab36a6a21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4184c40fd57a850605ac12c73553b6ba" id="r_ga4184c40fd57a850605ac12c73553b6ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4184c40fd57a850605ac12c73553b6ba">FSMC_PIO4_IOHIZ4_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630">FSMC_PIO4_IOHIZ4_Pos</a>)</td></tr>
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<tr class="separator:ga4184c40fd57a850605ac12c73553b6ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f966bdf26f7fa0f52076438219df7ee" id="r_ga9f966bdf26f7fa0f52076438219df7ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f966bdf26f7fa0f52076438219df7ee">FSMC_PIO4_IOHIZ4_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630">FSMC_PIO4_IOHIZ4_Pos</a>)</td></tr>
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<tr class="separator:ga9f966bdf26f7fa0f52076438219df7ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ba68883e73a331543a2990a76d1e91a" id="r_ga9ba68883e73a331543a2990a76d1e91a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ba68883e73a331543a2990a76d1e91a">FSMC_PIO4_IOHIZ4_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630">FSMC_PIO4_IOHIZ4_Pos</a>)</td></tr>
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<tr class="separator:ga9ba68883e73a331543a2990a76d1e91a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b2c084a1dfbf7fb7bd922faa48bad8a" id="r_ga8b2c084a1dfbf7fb7bd922faa48bad8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b2c084a1dfbf7fb7bd922faa48bad8a">FSMC_PIO4_IOHIZ4_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630">FSMC_PIO4_IOHIZ4_Pos</a>)</td></tr>
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<tr class="separator:ga8b2c084a1dfbf7fb7bd922faa48bad8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc8aef29e6eaecd3ff2c13bae143b8b4" id="r_gabc8aef29e6eaecd3ff2c13bae143b8b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc8aef29e6eaecd3ff2c13bae143b8b4">FSMC_PIO4_IOHIZ4_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630">FSMC_PIO4_IOHIZ4_Pos</a>)</td></tr>
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<tr class="separator:gabc8aef29e6eaecd3ff2c13bae143b8b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29ff399335d0f733c9c1476a5231bd92" id="r_ga29ff399335d0f733c9c1476a5231bd92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29ff399335d0f733c9c1476a5231bd92">FSMC_ECCR2_ECC2_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga29ff399335d0f733c9c1476a5231bd92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga263cd31cea7c03124b24b94bec2ba751" id="r_ga263cd31cea7c03124b24b94bec2ba751"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga263cd31cea7c03124b24b94bec2ba751">FSMC_ECCR2_ECC2_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga29ff399335d0f733c9c1476a5231bd92">FSMC_ECCR2_ECC2_Pos</a>)</td></tr>
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<tr class="separator:ga263cd31cea7c03124b24b94bec2ba751"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43da355ad2eb7d974488a02921b1b2ba" id="r_ga43da355ad2eb7d974488a02921b1b2ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43da355ad2eb7d974488a02921b1b2ba">FSMC_ECCR2_ECC2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga263cd31cea7c03124b24b94bec2ba751">FSMC_ECCR2_ECC2_Msk</a></td></tr>
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<tr class="separator:ga43da355ad2eb7d974488a02921b1b2ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad671bdabc43e3a5cdebc69d006e7227f" id="r_gad671bdabc43e3a5cdebc69d006e7227f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad671bdabc43e3a5cdebc69d006e7227f">FSMC_ECCR3_ECC3_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad671bdabc43e3a5cdebc69d006e7227f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8f7ec32f0cb28be8c241bf487fdc8c3" id="r_gaf8f7ec32f0cb28be8c241bf487fdc8c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8f7ec32f0cb28be8c241bf487fdc8c3">FSMC_ECCR3_ECC3_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad671bdabc43e3a5cdebc69d006e7227f">FSMC_ECCR3_ECC3_Pos</a>)</td></tr>
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<tr class="separator:gaf8f7ec32f0cb28be8c241bf487fdc8c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga798b288a17d84edc99ff1f5f81cf70be" id="r_ga798b288a17d84edc99ff1f5f81cf70be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga798b288a17d84edc99ff1f5f81cf70be">FSMC_ECCR3_ECC3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8f7ec32f0cb28be8c241bf487fdc8c3">FSMC_ECCR3_ECC3_Msk</a></td></tr>
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<tr class="separator:ga798b288a17d84edc99ff1f5f81cf70be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2244aa753f0340359098d15944602258" id="r_ga2244aa753f0340359098d15944602258"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2244aa753f0340359098d15944602258">GPIO_MODER_MODER0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2244aa753f0340359098d15944602258"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44c7a73f891cc60cb11c8dc122fde9bd" id="r_ga44c7a73f891cc60cb11c8dc122fde9bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44c7a73f891cc60cb11c8dc122fde9bd">GPIO_MODER_MODER0_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2244aa753f0340359098d15944602258">GPIO_MODER_MODER0_Pos</a>)</td></tr>
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<tr class="separator:ga44c7a73f891cc60cb11c8dc122fde9bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b64d47643f8d3c08c2be0722ff23b93" id="r_ga7b64d47643f8d3c08c2be0722ff23b93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b64d47643f8d3c08c2be0722ff23b93">GPIO_MODER_MODER0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44c7a73f891cc60cb11c8dc122fde9bd">GPIO_MODER_MODER0_Msk</a></td></tr>
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<tr class="separator:ga7b64d47643f8d3c08c2be0722ff23b93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9547fc54057db093f9ee4b846fcc4723" id="r_ga9547fc54057db093f9ee4b846fcc4723"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9547fc54057db093f9ee4b846fcc4723">GPIO_MODER_MODER0_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2244aa753f0340359098d15944602258">GPIO_MODER_MODER0_Pos</a>)</td></tr>
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<tr class="memitem:ga9e77a3bc750fe2ea8e06da301c65d6ef" id="r_ga9e77a3bc750fe2ea8e06da301c65d6ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e77a3bc750fe2ea8e06da301c65d6ef">GPIO_MODER_MODER0_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2244aa753f0340359098d15944602258">GPIO_MODER_MODER0_Pos</a>)</td></tr>
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<tr class="separator:ga9e77a3bc750fe2ea8e06da301c65d6ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1030dee3583ca3e42adbdfe515ff542" id="r_gae1030dee3583ca3e42adbdfe515ff542"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1030dee3583ca3e42adbdfe515ff542">GPIO_MODER_MODER1_Pos</a>   (2U)</td></tr>
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<tr class="separator:gae1030dee3583ca3e42adbdfe515ff542"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b96dc64bbedb58b5a6fdcc3c97eab1d" id="r_ga3b96dc64bbedb58b5a6fdcc3c97eab1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b96dc64bbedb58b5a6fdcc3c97eab1d">GPIO_MODER_MODER1_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae1030dee3583ca3e42adbdfe515ff542">GPIO_MODER_MODER1_Pos</a>)</td></tr>
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<tr class="separator:ga3b96dc64bbedb58b5a6fdcc3c97eab1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e0597b084c911728ee92b5fc4a2ae5a" id="r_ga2e0597b084c911728ee92b5fc4a2ae5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e0597b084c911728ee92b5fc4a2ae5a">GPIO_MODER_MODER1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b96dc64bbedb58b5a6fdcc3c97eab1d">GPIO_MODER_MODER1_Msk</a></td></tr>
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<tr class="separator:ga2e0597b084c911728ee92b5fc4a2ae5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d85123ad7c77e052b542f2df47a1371" id="r_ga5d85123ad7c77e052b542f2df47a1371"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d85123ad7c77e052b542f2df47a1371">GPIO_MODER_MODER1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae1030dee3583ca3e42adbdfe515ff542">GPIO_MODER_MODER1_Pos</a>)</td></tr>
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<tr class="separator:ga5d85123ad7c77e052b542f2df47a1371"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9f16759689b9ac61d9c68842ac49746" id="r_gad9f16759689b9ac61d9c68842ac49746"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9f16759689b9ac61d9c68842ac49746">GPIO_MODER_MODER1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae1030dee3583ca3e42adbdfe515ff542">GPIO_MODER_MODER1_Pos</a>)</td></tr>
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<tr class="separator:gad9f16759689b9ac61d9c68842ac49746"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga945f52c8af561a1c9a3358b0e8605ffc" id="r_ga945f52c8af561a1c9a3358b0e8605ffc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga945f52c8af561a1c9a3358b0e8605ffc">GPIO_MODER_MODER2_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga945f52c8af561a1c9a3358b0e8605ffc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6c01a65d00f6b648984e34f71ce0b83" id="r_gaf6c01a65d00f6b648984e34f71ce0b83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6c01a65d00f6b648984e34f71ce0b83">GPIO_MODER_MODER2_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga945f52c8af561a1c9a3358b0e8605ffc">GPIO_MODER_MODER2_Pos</a>)</td></tr>
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<tr class="separator:gaf6c01a65d00f6b648984e34f71ce0b83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06865341707bb4dd9671ce464d99ab2c" id="r_ga06865341707bb4dd9671ce464d99ab2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06865341707bb4dd9671ce464d99ab2c">GPIO_MODER_MODER2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6c01a65d00f6b648984e34f71ce0b83">GPIO_MODER_MODER2_Msk</a></td></tr>
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<tr class="separator:ga06865341707bb4dd9671ce464d99ab2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06e9f9713b7a822784cd2c0fa79dcff0" id="r_ga06e9f9713b7a822784cd2c0fa79dcff0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06e9f9713b7a822784cd2c0fa79dcff0">GPIO_MODER_MODER2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga945f52c8af561a1c9a3358b0e8605ffc">GPIO_MODER_MODER2_Pos</a>)</td></tr>
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<tr class="separator:ga06e9f9713b7a822784cd2c0fa79dcff0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97f7959265384b2621288c8340990665" id="r_ga97f7959265384b2621288c8340990665"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97f7959265384b2621288c8340990665">GPIO_MODER_MODER2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga945f52c8af561a1c9a3358b0e8605ffc">GPIO_MODER_MODER2_Pos</a>)</td></tr>
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<tr class="separator:ga97f7959265384b2621288c8340990665"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0df2c02569d6b84757d70cd5ab99d262" id="r_ga0df2c02569d6b84757d70cd5ab99d262"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0df2c02569d6b84757d70cd5ab99d262">GPIO_MODER_MODER3_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga0df2c02569d6b84757d70cd5ab99d262"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga053851b8f1df3d358a7b07fe8f720a25" id="r_ga053851b8f1df3d358a7b07fe8f720a25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga053851b8f1df3d358a7b07fe8f720a25">GPIO_MODER_MODER3_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0df2c02569d6b84757d70cd5ab99d262">GPIO_MODER_MODER3_Pos</a>)</td></tr>
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<tr class="separator:ga053851b8f1df3d358a7b07fe8f720a25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae06c9d07a091fb64ab53d0c899a9dda5" id="r_gae06c9d07a091fb64ab53d0c899a9dda5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae06c9d07a091fb64ab53d0c899a9dda5">GPIO_MODER_MODER3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga053851b8f1df3d358a7b07fe8f720a25">GPIO_MODER_MODER3_Msk</a></td></tr>
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<tr class="separator:gae06c9d07a091fb64ab53d0c899a9dda5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4aeeac804c07e25aeff31bebf3a639f6" id="r_ga4aeeac804c07e25aeff31bebf3a639f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4aeeac804c07e25aeff31bebf3a639f6">GPIO_MODER_MODER3_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0df2c02569d6b84757d70cd5ab99d262">GPIO_MODER_MODER3_Pos</a>)</td></tr>
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<tr class="separator:ga4aeeac804c07e25aeff31bebf3a639f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc09e4958f306ddcb6107942504b45e0" id="r_gafc09e4958f306ddcb6107942504b45e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc09e4958f306ddcb6107942504b45e0">GPIO_MODER_MODER3_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0df2c02569d6b84757d70cd5ab99d262">GPIO_MODER_MODER3_Pos</a>)</td></tr>
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<tr class="separator:gafc09e4958f306ddcb6107942504b45e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7866ff150289c04d52c808607dabbf9e" id="r_ga7866ff150289c04d52c808607dabbf9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7866ff150289c04d52c808607dabbf9e">GPIO_MODER_MODER4_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga7866ff150289c04d52c808607dabbf9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0678135cc7fb1e00fe0de880d822fde5" id="r_ga0678135cc7fb1e00fe0de880d822fde5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0678135cc7fb1e00fe0de880d822fde5">GPIO_MODER_MODER4_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7866ff150289c04d52c808607dabbf9e">GPIO_MODER_MODER4_Pos</a>)</td></tr>
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<tr class="separator:ga0678135cc7fb1e00fe0de880d822fde5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52cf9361d90c863c107cdeb859bd8b41" id="r_ga52cf9361d90c863c107cdeb859bd8b41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52cf9361d90c863c107cdeb859bd8b41">GPIO_MODER_MODER4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0678135cc7fb1e00fe0de880d822fde5">GPIO_MODER_MODER4_Msk</a></td></tr>
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<tr class="separator:ga52cf9361d90c863c107cdeb859bd8b41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67276f1aa615d1af388fef7232483795" id="r_ga67276f1aa615d1af388fef7232483795"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67276f1aa615d1af388fef7232483795">GPIO_MODER_MODER4_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7866ff150289c04d52c808607dabbf9e">GPIO_MODER_MODER4_Pos</a>)</td></tr>
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<tr class="separator:ga67276f1aa615d1af388fef7232483795"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5203150980865199911d58af22f49567" id="r_ga5203150980865199911d58af22f49567"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5203150980865199911d58af22f49567">GPIO_MODER_MODER4_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7866ff150289c04d52c808607dabbf9e">GPIO_MODER_MODER4_Pos</a>)</td></tr>
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<tr class="separator:ga5203150980865199911d58af22f49567"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84f88cbf25e1defb5f9b99c95797f7ab" id="r_ga84f88cbf25e1defb5f9b99c95797f7ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84f88cbf25e1defb5f9b99c95797f7ab">GPIO_MODER_MODER5_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga84f88cbf25e1defb5f9b99c95797f7ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f1827fce38f560f895e4486f1aacaac" id="r_ga9f1827fce38f560f895e4486f1aacaac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f1827fce38f560f895e4486f1aacaac">GPIO_MODER_MODER5_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84f88cbf25e1defb5f9b99c95797f7ab">GPIO_MODER_MODER5_Pos</a>)</td></tr>
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<tr class="separator:ga9f1827fce38f560f895e4486f1aacaac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae94ab55c126ff24572bbff0da5a3f360" id="r_gae94ab55c126ff24572bbff0da5a3f360"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae94ab55c126ff24572bbff0da5a3f360">GPIO_MODER_MODER5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f1827fce38f560f895e4486f1aacaac">GPIO_MODER_MODER5_Msk</a></td></tr>
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<tr class="separator:gae94ab55c126ff24572bbff0da5a3f360"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62665be9bddb711eedf99c85e37bb5ad" id="r_ga62665be9bddb711eedf99c85e37bb5ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62665be9bddb711eedf99c85e37bb5ad">GPIO_MODER_MODER5_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84f88cbf25e1defb5f9b99c95797f7ab">GPIO_MODER_MODER5_Pos</a>)</td></tr>
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<tr class="separator:ga62665be9bddb711eedf99c85e37bb5ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5096355e22b25bd4e6324399d5764630" id="r_ga5096355e22b25bd4e6324399d5764630"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5096355e22b25bd4e6324399d5764630">GPIO_MODER_MODER5_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84f88cbf25e1defb5f9b99c95797f7ab">GPIO_MODER_MODER5_Pos</a>)</td></tr>
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<tr class="separator:ga5096355e22b25bd4e6324399d5764630"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81c3fdecd37cce14983b42d28fc46d27" id="r_ga81c3fdecd37cce14983b42d28fc46d27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81c3fdecd37cce14983b42d28fc46d27">GPIO_MODER_MODER6_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga81c3fdecd37cce14983b42d28fc46d27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83a6d2a5dbd3f6f8447e0082c0e8d6ab" id="r_ga83a6d2a5dbd3f6f8447e0082c0e8d6ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83a6d2a5dbd3f6f8447e0082c0e8d6ab">GPIO_MODER_MODER6_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga81c3fdecd37cce14983b42d28fc46d27">GPIO_MODER_MODER6_Pos</a>)</td></tr>
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<tr class="separator:ga83a6d2a5dbd3f6f8447e0082c0e8d6ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97a85a1bb88cf8f730e0de38cb664282" id="r_ga97a85a1bb88cf8f730e0de38cb664282"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97a85a1bb88cf8f730e0de38cb664282">GPIO_MODER_MODER6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga83a6d2a5dbd3f6f8447e0082c0e8d6ab">GPIO_MODER_MODER6_Msk</a></td></tr>
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<tr class="separator:ga97a85a1bb88cf8f730e0de38cb664282"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf45f41af21a000ab66da5b99b998deb3" id="r_gaf45f41af21a000ab66da5b99b998deb3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf45f41af21a000ab66da5b99b998deb3">GPIO_MODER_MODER6_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga81c3fdecd37cce14983b42d28fc46d27">GPIO_MODER_MODER6_Pos</a>)</td></tr>
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<tr class="separator:gaf45f41af21a000ab66da5b99b998deb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41dfd1f39fe849fe3707ebf2ac0d8371" id="r_ga41dfd1f39fe849fe3707ebf2ac0d8371"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41dfd1f39fe849fe3707ebf2ac0d8371">GPIO_MODER_MODER6_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga81c3fdecd37cce14983b42d28fc46d27">GPIO_MODER_MODER6_Pos</a>)</td></tr>
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<tr class="memitem:gaf586709481b1450208dae7d9e53b9057" id="r_gaf586709481b1450208dae7d9e53b9057"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf586709481b1450208dae7d9e53b9057">GPIO_MODER_MODER7_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gae685da5b1c5c085e69be64ecf0b65ec5" id="r_gae685da5b1c5c085e69be64ecf0b65ec5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae685da5b1c5c085e69be64ecf0b65ec5">GPIO_MODER_MODER7_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf586709481b1450208dae7d9e53b9057">GPIO_MODER_MODER7_Pos</a>)</td></tr>
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<tr class="memitem:ga22dc08ecc39bceba020d8e5949b658e0" id="r_ga22dc08ecc39bceba020d8e5949b658e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22dc08ecc39bceba020d8e5949b658e0">GPIO_MODER_MODER7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae685da5b1c5c085e69be64ecf0b65ec5">GPIO_MODER_MODER7_Msk</a></td></tr>
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<tr class="separator:ga22dc08ecc39bceba020d8e5949b658e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga585ab6cb29e3763ab8c1e997c55f2b43" id="r_ga585ab6cb29e3763ab8c1e997c55f2b43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga585ab6cb29e3763ab8c1e997c55f2b43">GPIO_MODER_MODER7_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf586709481b1450208dae7d9e53b9057">GPIO_MODER_MODER7_Pos</a>)</td></tr>
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<tr class="separator:ga585ab6cb29e3763ab8c1e997c55f2b43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b5cca014fc55f64cdbbb42ea0515e05" id="r_ga2b5cca014fc55f64cdbbb42ea0515e05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b5cca014fc55f64cdbbb42ea0515e05">GPIO_MODER_MODER7_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf586709481b1450208dae7d9e53b9057">GPIO_MODER_MODER7_Pos</a>)</td></tr>
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<tr class="separator:ga2b5cca014fc55f64cdbbb42ea0515e05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80e5f1f7c986ee7f31178901cab442ab" id="r_ga80e5f1f7c986ee7f31178901cab442ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80e5f1f7c986ee7f31178901cab442ab">GPIO_MODER_MODER8_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga80e5f1f7c986ee7f31178901cab442ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaddfeb2d4f139bd00fdcd2ce538f2087" id="r_gaaddfeb2d4f139bd00fdcd2ce538f2087"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaddfeb2d4f139bd00fdcd2ce538f2087">GPIO_MODER_MODER8_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80e5f1f7c986ee7f31178901cab442ab">GPIO_MODER_MODER8_Pos</a>)</td></tr>
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<tr class="separator:gaaddfeb2d4f139bd00fdcd2ce538f2087"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac41f2174ef4444c685ea92da1258c678" id="r_gac41f2174ef4444c685ea92da1258c678"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac41f2174ef4444c685ea92da1258c678">GPIO_MODER_MODER8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaddfeb2d4f139bd00fdcd2ce538f2087">GPIO_MODER_MODER8_Msk</a></td></tr>
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<tr class="separator:gac41f2174ef4444c685ea92da1258c678"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cdb8e55aa223af568ae12d316a22f8d" id="r_ga2cdb8e55aa223af568ae12d316a22f8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdb8e55aa223af568ae12d316a22f8d">GPIO_MODER_MODER8_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80e5f1f7c986ee7f31178901cab442ab">GPIO_MODER_MODER8_Pos</a>)</td></tr>
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<tr class="separator:ga2cdb8e55aa223af568ae12d316a22f8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0729411ccd74a91cdd0f23adada25782" id="r_ga0729411ccd74a91cdd0f23adada25782"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0729411ccd74a91cdd0f23adada25782">GPIO_MODER_MODER8_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80e5f1f7c986ee7f31178901cab442ab">GPIO_MODER_MODER8_Pos</a>)</td></tr>
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<tr class="separator:ga0729411ccd74a91cdd0f23adada25782"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf310164aef074cbdda2af5b0af223139" id="r_gaf310164aef074cbdda2af5b0af223139"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf310164aef074cbdda2af5b0af223139">GPIO_MODER_MODER9_Pos</a>   (18U)</td></tr>
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<tr class="memitem:gafdcb7c58d623c51ababeb5917430132b" id="r_gafdcb7c58d623c51ababeb5917430132b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdcb7c58d623c51ababeb5917430132b">GPIO_MODER_MODER9_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf310164aef074cbdda2af5b0af223139">GPIO_MODER_MODER9_Pos</a>)</td></tr>
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<tr class="separator:gafdcb7c58d623c51ababeb5917430132b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d4ed9018bf72565bab1d08c476fed20" id="r_ga5d4ed9018bf72565bab1d08c476fed20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d4ed9018bf72565bab1d08c476fed20">GPIO_MODER_MODER9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafdcb7c58d623c51ababeb5917430132b">GPIO_MODER_MODER9_Msk</a></td></tr>
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<tr class="separator:ga5d4ed9018bf72565bab1d08c476fed20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea7c7ec787b1ee1ae7e0b4da216eb418" id="r_gaea7c7ec787b1ee1ae7e0b4da216eb418"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea7c7ec787b1ee1ae7e0b4da216eb418">GPIO_MODER_MODER9_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf310164aef074cbdda2af5b0af223139">GPIO_MODER_MODER9_Pos</a>)</td></tr>
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<tr class="separator:gaea7c7ec787b1ee1ae7e0b4da216eb418"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5cd33689071b7af70ece64a371645df" id="r_gaa5cd33689071b7af70ece64a371645df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5cd33689071b7af70ece64a371645df">GPIO_MODER_MODER9_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf310164aef074cbdda2af5b0af223139">GPIO_MODER_MODER9_Pos</a>)</td></tr>
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<tr class="separator:gaa5cd33689071b7af70ece64a371645df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf36ddfa8971a143e722ca9897d6a554" id="r_gacf36ddfa8971a143e722ca9897d6a554"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf36ddfa8971a143e722ca9897d6a554">GPIO_MODER_MODER10_Pos</a>   (20U)</td></tr>
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<tr class="separator:gacf36ddfa8971a143e722ca9897d6a554"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9af602f158627d6d61a2fcf7149a6178" id="r_ga9af602f158627d6d61a2fcf7149a6178"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9af602f158627d6d61a2fcf7149a6178">GPIO_MODER_MODER10_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf36ddfa8971a143e722ca9897d6a554">GPIO_MODER_MODER10_Pos</a>)</td></tr>
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<tr class="separator:ga9af602f158627d6d61a2fcf7149a6178"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacbdb241d7bebde85d7d0b42c2f35563" id="r_gaacbdb241d7bebde85d7d0b42c2f35563"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacbdb241d7bebde85d7d0b42c2f35563">GPIO_MODER_MODER10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9af602f158627d6d61a2fcf7149a6178">GPIO_MODER_MODER10_Msk</a></td></tr>
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<tr class="separator:gaacbdb241d7bebde85d7d0b42c2f35563"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f4d2b18e57e7b2f600e4f5d9b17bd95" id="r_ga6f4d2b18e57e7b2f600e4f5d9b17bd95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f4d2b18e57e7b2f600e4f5d9b17bd95">GPIO_MODER_MODER10_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf36ddfa8971a143e722ca9897d6a554">GPIO_MODER_MODER10_Pos</a>)</td></tr>
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<tr class="separator:ga6f4d2b18e57e7b2f600e4f5d9b17bd95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9dcae08e0f7afc002658a4ef4a764dc4" id="r_ga9dcae08e0f7afc002658a4ef4a764dc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9dcae08e0f7afc002658a4ef4a764dc4">GPIO_MODER_MODER10_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf36ddfa8971a143e722ca9897d6a554">GPIO_MODER_MODER10_Pos</a>)</td></tr>
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<tr class="separator:ga9dcae08e0f7afc002658a4ef4a764dc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac60a554e688d63d15bce7240549d2ccb" id="r_gac60a554e688d63d15bce7240549d2ccb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac60a554e688d63d15bce7240549d2ccb">GPIO_MODER_MODER11_Pos</a>   (22U)</td></tr>
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<tr class="separator:gac60a554e688d63d15bce7240549d2ccb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82a8fa719e9f98d2a7b4fd00ad41927d" id="r_ga82a8fa719e9f98d2a7b4fd00ad41927d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82a8fa719e9f98d2a7b4fd00ad41927d">GPIO_MODER_MODER11_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac60a554e688d63d15bce7240549d2ccb">GPIO_MODER_MODER11_Pos</a>)</td></tr>
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<tr class="separator:ga82a8fa719e9f98d2a7b4fd00ad41927d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf18bc295f7195fc050221287c4564474" id="r_gaf18bc295f7195fc050221287c4564474"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf18bc295f7195fc050221287c4564474">GPIO_MODER_MODER11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a8fa719e9f98d2a7b4fd00ad41927d">GPIO_MODER_MODER11_Msk</a></td></tr>
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<tr class="separator:gaf18bc295f7195fc050221287c4564474"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4082cd576f50cd2687e45557b70d458" id="r_gaf4082cd576f50cd2687e45557b70d458"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4082cd576f50cd2687e45557b70d458">GPIO_MODER_MODER11_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac60a554e688d63d15bce7240549d2ccb">GPIO_MODER_MODER11_Pos</a>)</td></tr>
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<tr class="separator:gaf4082cd576f50cd2687e45557b70d458"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b2f611ae75f3441bad03866550f6263" id="r_ga1b2f611ae75f3441bad03866550f6263"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b2f611ae75f3441bad03866550f6263">GPIO_MODER_MODER11_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac60a554e688d63d15bce7240549d2ccb">GPIO_MODER_MODER11_Pos</a>)</td></tr>
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<tr class="separator:ga1b2f611ae75f3441bad03866550f6263"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec7b868a25af299e046b49b017c1114f" id="r_gaec7b868a25af299e046b49b017c1114f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec7b868a25af299e046b49b017c1114f">GPIO_MODER_MODER12_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaec7b868a25af299e046b49b017c1114f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd6d6390219a23c8420cc152901ca9bd" id="r_gabd6d6390219a23c8420cc152901ca9bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd6d6390219a23c8420cc152901ca9bd">GPIO_MODER_MODER12_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaec7b868a25af299e046b49b017c1114f">GPIO_MODER_MODER12_Pos</a>)</td></tr>
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<tr class="separator:gabd6d6390219a23c8420cc152901ca9bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63101c5c410b55b668ec190422dc3597" id="r_ga63101c5c410b55b668ec190422dc3597"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63101c5c410b55b668ec190422dc3597">GPIO_MODER_MODER12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd6d6390219a23c8420cc152901ca9bd">GPIO_MODER_MODER12_Msk</a></td></tr>
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<tr class="separator:ga63101c5c410b55b668ec190422dc3597"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa89cd8ed328ed0116cbf51810fcd8788" id="r_gaa89cd8ed328ed0116cbf51810fcd8788"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa89cd8ed328ed0116cbf51810fcd8788">GPIO_MODER_MODER12_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaec7b868a25af299e046b49b017c1114f">GPIO_MODER_MODER12_Pos</a>)</td></tr>
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<tr class="separator:gaa89cd8ed328ed0116cbf51810fcd8788"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74f91bdd676e477e4c19d30d3ea5c4c8" id="r_ga74f91bdd676e477e4c19d30d3ea5c4c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74f91bdd676e477e4c19d30d3ea5c4c8">GPIO_MODER_MODER12_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaec7b868a25af299e046b49b017c1114f">GPIO_MODER_MODER12_Pos</a>)</td></tr>
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<tr class="separator:ga74f91bdd676e477e4c19d30d3ea5c4c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e91d26a428aa90b419bf51324491246" id="r_ga1e91d26a428aa90b419bf51324491246"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e91d26a428aa90b419bf51324491246">GPIO_MODER_MODER13_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga1e91d26a428aa90b419bf51324491246"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ae7344fb7e360c013ae484a7b3ce06e" id="r_ga3ae7344fb7e360c013ae484a7b3ce06e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ae7344fb7e360c013ae484a7b3ce06e">GPIO_MODER_MODER13_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e91d26a428aa90b419bf51324491246">GPIO_MODER_MODER13_Pos</a>)</td></tr>
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<tr class="memitem:ga353af246bef5dca5aadfe6fe3fd695c3" id="r_ga353af246bef5dca5aadfe6fe3fd695c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga353af246bef5dca5aadfe6fe3fd695c3">GPIO_MODER_MODER13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ae7344fb7e360c013ae484a7b3ce06e">GPIO_MODER_MODER13_Msk</a></td></tr>
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<tr class="separator:ga353af246bef5dca5aadfe6fe3fd695c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc01e2e6cf45e8ec27d3a66ff36c2cfa" id="r_gabc01e2e6cf45e8ec27d3a66ff36c2cfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc01e2e6cf45e8ec27d3a66ff36c2cfa">GPIO_MODER_MODER13_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e91d26a428aa90b419bf51324491246">GPIO_MODER_MODER13_Pos</a>)</td></tr>
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<tr class="memitem:ga71a30088f5475ae8774404ae7d41872e" id="r_ga71a30088f5475ae8774404ae7d41872e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71a30088f5475ae8774404ae7d41872e">GPIO_MODER_MODER13_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e91d26a428aa90b419bf51324491246">GPIO_MODER_MODER13_Pos</a>)</td></tr>
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<tr class="separator:ga71a30088f5475ae8774404ae7d41872e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac67c9470dc741033d3254a4041e3d320" id="r_gac67c9470dc741033d3254a4041e3d320"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac67c9470dc741033d3254a4041e3d320">GPIO_MODER_MODER14_Pos</a>   (28U)</td></tr>
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<tr class="separator:gac67c9470dc741033d3254a4041e3d320"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1fd4d1526a36e0838bc8c9bab621aba0" id="r_ga1fd4d1526a36e0838bc8c9bab621aba0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fd4d1526a36e0838bc8c9bab621aba0">GPIO_MODER_MODER14_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac67c9470dc741033d3254a4041e3d320">GPIO_MODER_MODER14_Pos</a>)</td></tr>
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<tr class="separator:ga1fd4d1526a36e0838bc8c9bab621aba0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18a722f9682045c1d2460fedf32b02b1" id="r_ga18a722f9682045c1d2460fedf32b02b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18a722f9682045c1d2460fedf32b02b1">GPIO_MODER_MODER14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fd4d1526a36e0838bc8c9bab621aba0">GPIO_MODER_MODER14_Msk</a></td></tr>
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<tr class="separator:ga18a722f9682045c1d2460fedf32b02b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad295063c22bd981239bc1b26f2e7f9c0" id="r_gad295063c22bd981239bc1b26f2e7f9c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad295063c22bd981239bc1b26f2e7f9c0">GPIO_MODER_MODER14_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac67c9470dc741033d3254a4041e3d320">GPIO_MODER_MODER14_Pos</a>)</td></tr>
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<tr class="separator:gad295063c22bd981239bc1b26f2e7f9c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ff3a914796db9625d86996b6f6f5288" id="r_ga0ff3a914796db9625d86996b6f6f5288"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3a914796db9625d86996b6f6f5288">GPIO_MODER_MODER14_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac67c9470dc741033d3254a4041e3d320">GPIO_MODER_MODER14_Pos</a>)</td></tr>
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<tr class="separator:ga0ff3a914796db9625d86996b6f6f5288"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8c4f0c2ee0dbf7761c9acf9f4d9fa8b" id="r_gac8c4f0c2ee0dbf7761c9acf9f4d9fa8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8c4f0c2ee0dbf7761c9acf9f4d9fa8b">GPIO_MODER_MODER15_Pos</a>   (30U)</td></tr>
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<tr class="separator:gac8c4f0c2ee0dbf7761c9acf9f4d9fa8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97ba0885b9dda0bec8202305bf9cf0ad" id="r_ga97ba0885b9dda0bec8202305bf9cf0ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97ba0885b9dda0bec8202305bf9cf0ad">GPIO_MODER_MODER15_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8c4f0c2ee0dbf7761c9acf9f4d9fa8b">GPIO_MODER_MODER15_Pos</a>)</td></tr>
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<tr class="separator:ga97ba0885b9dda0bec8202305bf9cf0ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefc40e6fae78c1c5c857346793f9d4c8" id="r_gaefc40e6fae78c1c5c857346793f9d4c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefc40e6fae78c1c5c857346793f9d4c8">GPIO_MODER_MODER15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97ba0885b9dda0bec8202305bf9cf0ad">GPIO_MODER_MODER15_Msk</a></td></tr>
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<tr class="separator:gaefc40e6fae78c1c5c857346793f9d4c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c4b7f270eb99d851b84b9917fe49564" id="r_ga6c4b7f270eb99d851b84b9917fe49564"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c4b7f270eb99d851b84b9917fe49564">GPIO_MODER_MODER15_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8c4f0c2ee0dbf7761c9acf9f4d9fa8b">GPIO_MODER_MODER15_Pos</a>)</td></tr>
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<tr class="separator:ga6c4b7f270eb99d851b84b9917fe49564"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9297c041f5f74aec73e6f4dd89ad819c" id="r_ga9297c041f5f74aec73e6f4dd89ad819c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9297c041f5f74aec73e6f4dd89ad819c">GPIO_MODER_MODER15_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8c4f0c2ee0dbf7761c9acf9f4d9fa8b">GPIO_MODER_MODER15_Pos</a>)</td></tr>
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<tr class="separator:ga9297c041f5f74aec73e6f4dd89ad819c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f3903d8ae31585af4d8e0a4a980a53f" id="r_ga6f3903d8ae31585af4d8e0a4a980a53f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f3903d8ae31585af4d8e0a4a980a53f">GPIO_MODER_MODE0_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2244aa753f0340359098d15944602258">GPIO_MODER_MODER0_Pos</a></td></tr>
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<tr class="separator:ga6f3903d8ae31585af4d8e0a4a980a53f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9cff105dfdd73e5a1705a3a52bfe4953" id="r_ga9cff105dfdd73e5a1705a3a52bfe4953"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cff105dfdd73e5a1705a3a52bfe4953">GPIO_MODER_MODE0_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44c7a73f891cc60cb11c8dc122fde9bd">GPIO_MODER_MODER0_Msk</a></td></tr>
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<tr class="separator:ga9cff105dfdd73e5a1705a3a52bfe4953"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabad45500839e6f801c64ee9474e4da33" id="r_gabad45500839e6f801c64ee9474e4da33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabad45500839e6f801c64ee9474e4da33">GPIO_MODER_MODE0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b64d47643f8d3c08c2be0722ff23b93">GPIO_MODER_MODER0</a></td></tr>
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<tr class="separator:gabad45500839e6f801c64ee9474e4da33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac21859652224406f970f4c99d5198d16" id="r_gac21859652224406f970f4c99d5198d16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac21859652224406f970f4c99d5198d16">GPIO_MODER_MODE0_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9547fc54057db093f9ee4b846fcc4723">GPIO_MODER_MODER0_0</a></td></tr>
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<tr class="separator:gac21859652224406f970f4c99d5198d16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7a47a04b8e25a1de3250bd4921eeddc" id="r_gae7a47a04b8e25a1de3250bd4921eeddc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7a47a04b8e25a1de3250bd4921eeddc">GPIO_MODER_MODE0_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e77a3bc750fe2ea8e06da301c65d6ef">GPIO_MODER_MODER0_1</a></td></tr>
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<tr class="separator:gae7a47a04b8e25a1de3250bd4921eeddc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcd114563c35dd9bc117884af80acda8" id="r_gadcd114563c35dd9bc117884af80acda8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcd114563c35dd9bc117884af80acda8">GPIO_MODER_MODE1_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae1030dee3583ca3e42adbdfe515ff542">GPIO_MODER_MODER1_Pos</a></td></tr>
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<tr class="separator:gadcd114563c35dd9bc117884af80acda8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30d7601c96266dc29ab8d67804154b3f" id="r_ga30d7601c96266dc29ab8d67804154b3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30d7601c96266dc29ab8d67804154b3f">GPIO_MODER_MODE1_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b96dc64bbedb58b5a6fdcc3c97eab1d">GPIO_MODER_MODER1_Msk</a></td></tr>
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<tr class="separator:ga30d7601c96266dc29ab8d67804154b3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76d7c80c5afbf9bf5aada55d91d59ecb" id="r_ga76d7c80c5afbf9bf5aada55d91d59ecb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76d7c80c5afbf9bf5aada55d91d59ecb">GPIO_MODER_MODE1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e0597b084c911728ee92b5fc4a2ae5a">GPIO_MODER_MODER1</a></td></tr>
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<tr class="separator:ga76d7c80c5afbf9bf5aada55d91d59ecb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdd2690fbea56b2d7dd8af222370cc95" id="r_gabdd2690fbea56b2d7dd8af222370cc95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdd2690fbea56b2d7dd8af222370cc95">GPIO_MODER_MODE1_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5d85123ad7c77e052b542f2df47a1371">GPIO_MODER_MODER1_0</a></td></tr>
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<tr class="separator:gabdd2690fbea56b2d7dd8af222370cc95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a240f6f0b335fe9595019531b4607b9" id="r_ga1a240f6f0b335fe9595019531b4607b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a240f6f0b335fe9595019531b4607b9">GPIO_MODER_MODE1_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad9f16759689b9ac61d9c68842ac49746">GPIO_MODER_MODER1_1</a></td></tr>
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<tr class="separator:ga1a240f6f0b335fe9595019531b4607b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6405d97990f322ac711f5d50d69c41f" id="r_gaf6405d97990f322ac711f5d50d69c41f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6405d97990f322ac711f5d50d69c41f">GPIO_MODER_MODE2_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga945f52c8af561a1c9a3358b0e8605ffc">GPIO_MODER_MODER2_Pos</a></td></tr>
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<tr class="separator:gaf6405d97990f322ac711f5d50d69c41f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a188e7809bffb5a963302debcc602bf" id="r_ga7a188e7809bffb5a963302debcc602bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a188e7809bffb5a963302debcc602bf">GPIO_MODER_MODE2_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6c01a65d00f6b648984e34f71ce0b83">GPIO_MODER_MODER2_Msk</a></td></tr>
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<tr class="separator:ga7a188e7809bffb5a963302debcc602bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90970df916fe323664322ecbe516993d" id="r_ga90970df916fe323664322ecbe516993d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90970df916fe323664322ecbe516993d">GPIO_MODER_MODE2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06865341707bb4dd9671ce464d99ab2c">GPIO_MODER_MODER2</a></td></tr>
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<tr class="separator:ga90970df916fe323664322ecbe516993d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66a90c798fa54047f30b83f3eec1821b" id="r_ga66a90c798fa54047f30b83f3eec1821b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66a90c798fa54047f30b83f3eec1821b">GPIO_MODER_MODE2_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06e9f9713b7a822784cd2c0fa79dcff0">GPIO_MODER_MODER2_0</a></td></tr>
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<tr class="separator:ga66a90c798fa54047f30b83f3eec1821b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae88847b33d3c78142f99e5d1753451e" id="r_gaae88847b33d3c78142f99e5d1753451e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae88847b33d3c78142f99e5d1753451e">GPIO_MODER_MODE2_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97f7959265384b2621288c8340990665">GPIO_MODER_MODER2_1</a></td></tr>
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<tr class="separator:gaae88847b33d3c78142f99e5d1753451e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3d6572d265c72f92e2005c141202422" id="r_gaf3d6572d265c72f92e2005c141202422"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3d6572d265c72f92e2005c141202422">GPIO_MODER_MODE3_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0df2c02569d6b84757d70cd5ab99d262">GPIO_MODER_MODER3_Pos</a></td></tr>
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<tr class="separator:gaf3d6572d265c72f92e2005c141202422"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4eaea23a16c4fb39e27d295ce0e5b94" id="r_gad4eaea23a16c4fb39e27d295ce0e5b94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4eaea23a16c4fb39e27d295ce0e5b94">GPIO_MODER_MODE3_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga053851b8f1df3d358a7b07fe8f720a25">GPIO_MODER_MODER3_Msk</a></td></tr>
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<tr class="separator:gad4eaea23a16c4fb39e27d295ce0e5b94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9062e2f2d10271c05e5f963be522db96" id="r_ga9062e2f2d10271c05e5f963be522db96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9062e2f2d10271c05e5f963be522db96">GPIO_MODER_MODE3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae06c9d07a091fb64ab53d0c899a9dda5">GPIO_MODER_MODER3</a></td></tr>
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<tr class="separator:ga9062e2f2d10271c05e5f963be522db96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga908f28256ab03cf88ed6e2fce3a2a70d" id="r_ga908f28256ab03cf88ed6e2fce3a2a70d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga908f28256ab03cf88ed6e2fce3a2a70d">GPIO_MODER_MODE3_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4aeeac804c07e25aeff31bebf3a639f6">GPIO_MODER_MODER3_0</a></td></tr>
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<tr class="separator:ga908f28256ab03cf88ed6e2fce3a2a70d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99db34fd563915c2fc4eb16ef2505c98" id="r_ga99db34fd563915c2fc4eb16ef2505c98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99db34fd563915c2fc4eb16ef2505c98">GPIO_MODER_MODE3_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafc09e4958f306ddcb6107942504b45e0">GPIO_MODER_MODER3_1</a></td></tr>
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<tr class="memitem:gab14bbd003834724332b11c3a33eba1a6" id="r_gab14bbd003834724332b11c3a33eba1a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab14bbd003834724332b11c3a33eba1a6">GPIO_MODER_MODE4_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7866ff150289c04d52c808607dabbf9e">GPIO_MODER_MODER4_Pos</a></td></tr>
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<tr class="memitem:gac9b416b464e6bcd73aa11bf0ef734b47" id="r_gac9b416b464e6bcd73aa11bf0ef734b47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9b416b464e6bcd73aa11bf0ef734b47">GPIO_MODER_MODE4_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0678135cc7fb1e00fe0de880d822fde5">GPIO_MODER_MODER4_Msk</a></td></tr>
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<tr class="separator:gac9b416b464e6bcd73aa11bf0ef734b47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae11faa17747d422f5d88ced879e09bb6" id="r_gae11faa17747d422f5d88ced879e09bb6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae11faa17747d422f5d88ced879e09bb6">GPIO_MODER_MODE4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga52cf9361d90c863c107cdeb859bd8b41">GPIO_MODER_MODER4</a></td></tr>
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<tr class="separator:gae11faa17747d422f5d88ced879e09bb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2336f60fe03642339cbfd4e994812875" id="r_ga2336f60fe03642339cbfd4e994812875"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2336f60fe03642339cbfd4e994812875">GPIO_MODER_MODE4_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67276f1aa615d1af388fef7232483795">GPIO_MODER_MODER4_0</a></td></tr>
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<tr class="separator:ga2336f60fe03642339cbfd4e994812875"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae946375c36dfb3b3669864ee62002e62" id="r_gae946375c36dfb3b3669864ee62002e62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae946375c36dfb3b3669864ee62002e62">GPIO_MODER_MODE4_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5203150980865199911d58af22f49567">GPIO_MODER_MODER4_1</a></td></tr>
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<tr class="separator:gae946375c36dfb3b3669864ee62002e62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3db08d5515fb6203ea8c2cf83d5ccd9" id="r_gaf3db08d5515fb6203ea8c2cf83d5ccd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3db08d5515fb6203ea8c2cf83d5ccd9">GPIO_MODER_MODE5_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga84f88cbf25e1defb5f9b99c95797f7ab">GPIO_MODER_MODER5_Pos</a></td></tr>
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<tr class="separator:gaf3db08d5515fb6203ea8c2cf83d5ccd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ecdacbc580acb1d0045366bab0605a3" id="r_ga5ecdacbc580acb1d0045366bab0605a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ecdacbc580acb1d0045366bab0605a3">GPIO_MODER_MODE5_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f1827fce38f560f895e4486f1aacaac">GPIO_MODER_MODER5_Msk</a></td></tr>
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<tr class="separator:ga5ecdacbc580acb1d0045366bab0605a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b40ba8ed0964516f512bb55a7783425" id="r_ga1b40ba8ed0964516f512bb55a7783425"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b40ba8ed0964516f512bb55a7783425">GPIO_MODER_MODE5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae94ab55c126ff24572bbff0da5a3f360">GPIO_MODER_MODER5</a></td></tr>
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<tr class="separator:ga1b40ba8ed0964516f512bb55a7783425"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9fbe729f8b1780ef0a6a24ce46a5dc9" id="r_gae9fbe729f8b1780ef0a6a24ce46a5dc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9fbe729f8b1780ef0a6a24ce46a5dc9">GPIO_MODER_MODE5_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga62665be9bddb711eedf99c85e37bb5ad">GPIO_MODER_MODER5_0</a></td></tr>
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<tr class="separator:gae9fbe729f8b1780ef0a6a24ce46a5dc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85fd33570c7059e94708cb99a1d88e55" id="r_ga85fd33570c7059e94708cb99a1d88e55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85fd33570c7059e94708cb99a1d88e55">GPIO_MODER_MODE5_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5096355e22b25bd4e6324399d5764630">GPIO_MODER_MODER5_1</a></td></tr>
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<tr class="separator:ga85fd33570c7059e94708cb99a1d88e55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1605f3cdb581e59663fd9fb0bab17d74" id="r_ga1605f3cdb581e59663fd9fb0bab17d74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1605f3cdb581e59663fd9fb0bab17d74">GPIO_MODER_MODE6_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga81c3fdecd37cce14983b42d28fc46d27">GPIO_MODER_MODER6_Pos</a></td></tr>
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<tr class="separator:ga1605f3cdb581e59663fd9fb0bab17d74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga923f7562b497aa9e864872e6314aec8b" id="r_ga923f7562b497aa9e864872e6314aec8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga923f7562b497aa9e864872e6314aec8b">GPIO_MODER_MODE6_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga83a6d2a5dbd3f6f8447e0082c0e8d6ab">GPIO_MODER_MODER6_Msk</a></td></tr>
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<tr class="separator:ga923f7562b497aa9e864872e6314aec8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad09b263a1b49cc5db86e5e6fe5d0d59c" id="r_gad09b263a1b49cc5db86e5e6fe5d0d59c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad09b263a1b49cc5db86e5e6fe5d0d59c">GPIO_MODER_MODE6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97a85a1bb88cf8f730e0de38cb664282">GPIO_MODER_MODER6</a></td></tr>
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<tr class="separator:gad09b263a1b49cc5db86e5e6fe5d0d59c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9fe86e9e52f1ba692d5ea66c2e43678" id="r_gac9fe86e9e52f1ba692d5ea66c2e43678"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9fe86e9e52f1ba692d5ea66c2e43678">GPIO_MODER_MODE6_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf45f41af21a000ab66da5b99b998deb3">GPIO_MODER_MODER6_0</a></td></tr>
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<tr class="separator:gac9fe86e9e52f1ba692d5ea66c2e43678"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ef7f24d9e982418baef863fbe1ffe5f" id="r_ga7ef7f24d9e982418baef863fbe1ffe5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ef7f24d9e982418baef863fbe1ffe5f">GPIO_MODER_MODE6_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga41dfd1f39fe849fe3707ebf2ac0d8371">GPIO_MODER_MODER6_1</a></td></tr>
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<tr class="separator:ga7ef7f24d9e982418baef863fbe1ffe5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd7bb459725ad9a92adb58341f64c5db" id="r_gabd7bb459725ad9a92adb58341f64c5db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd7bb459725ad9a92adb58341f64c5db">GPIO_MODER_MODE7_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf586709481b1450208dae7d9e53b9057">GPIO_MODER_MODER7_Pos</a></td></tr>
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<tr class="separator:gabd7bb459725ad9a92adb58341f64c5db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga395417bce21078a26c0930132c9853ee" id="r_ga395417bce21078a26c0930132c9853ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga395417bce21078a26c0930132c9853ee">GPIO_MODER_MODE7_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae685da5b1c5c085e69be64ecf0b65ec5">GPIO_MODER_MODER7_Msk</a></td></tr>
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<tr class="separator:ga395417bce21078a26c0930132c9853ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafff70c209574ca7023aa0a853a341e2b" id="r_gafff70c209574ca7023aa0a853a341e2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafff70c209574ca7023aa0a853a341e2b">GPIO_MODER_MODE7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga22dc08ecc39bceba020d8e5949b658e0">GPIO_MODER_MODER7</a></td></tr>
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<tr class="separator:gafff70c209574ca7023aa0a853a341e2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac77ebcfb844a2b8893641ee9de058178" id="r_gac77ebcfb844a2b8893641ee9de058178"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac77ebcfb844a2b8893641ee9de058178">GPIO_MODER_MODE7_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga585ab6cb29e3763ab8c1e997c55f2b43">GPIO_MODER_MODER7_0</a></td></tr>
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<tr class="separator:gac77ebcfb844a2b8893641ee9de058178"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f64e364157865520082d72aa98ab0ee" id="r_ga1f64e364157865520082d72aa98ab0ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f64e364157865520082d72aa98ab0ee">GPIO_MODER_MODE7_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b5cca014fc55f64cdbbb42ea0515e05">GPIO_MODER_MODER7_1</a></td></tr>
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<tr class="separator:ga1f64e364157865520082d72aa98ab0ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga962ec8cd96b449ed7cc142b491db4e0c" id="r_ga962ec8cd96b449ed7cc142b491db4e0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga962ec8cd96b449ed7cc142b491db4e0c">GPIO_MODER_MODE8_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga80e5f1f7c986ee7f31178901cab442ab">GPIO_MODER_MODER8_Pos</a></td></tr>
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<tr class="separator:ga962ec8cd96b449ed7cc142b491db4e0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe7b281c031a88069e827a6ac710e0c5" id="r_gabe7b281c031a88069e827a6ac710e0c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe7b281c031a88069e827a6ac710e0c5">GPIO_MODER_MODE8_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaddfeb2d4f139bd00fdcd2ce538f2087">GPIO_MODER_MODER8_Msk</a></td></tr>
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<tr class="separator:gabe7b281c031a88069e827a6ac710e0c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d7027e90da284883872b827f78fbc26" id="r_ga1d7027e90da284883872b827f78fbc26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d7027e90da284883872b827f78fbc26">GPIO_MODER_MODE8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac41f2174ef4444c685ea92da1258c678">GPIO_MODER_MODER8</a></td></tr>
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<tr class="separator:ga1d7027e90da284883872b827f78fbc26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac1715680209944bc7593cedf31f491b" id="r_gaac1715680209944bc7593cedf31f491b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac1715680209944bc7593cedf31f491b">GPIO_MODER_MODE8_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdb8e55aa223af568ae12d316a22f8d">GPIO_MODER_MODER8_0</a></td></tr>
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<tr class="separator:gaac1715680209944bc7593cedf31f491b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3197ca6a90d936e5a564d377bd4126fd" id="r_ga3197ca6a90d936e5a564d377bd4126fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3197ca6a90d936e5a564d377bd4126fd">GPIO_MODER_MODE8_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0729411ccd74a91cdd0f23adada25782">GPIO_MODER_MODER8_1</a></td></tr>
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<tr class="separator:ga3197ca6a90d936e5a564d377bd4126fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1093b1b58d8a8b51f204fc78239cbbb0" id="r_ga1093b1b58d8a8b51f204fc78239cbbb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1093b1b58d8a8b51f204fc78239cbbb0">GPIO_MODER_MODE9_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf310164aef074cbdda2af5b0af223139">GPIO_MODER_MODER9_Pos</a></td></tr>
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<tr class="separator:ga1093b1b58d8a8b51f204fc78239cbbb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0acba3f02fb730df350c2d938792fd74" id="r_ga0acba3f02fb730df350c2d938792fd74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0acba3f02fb730df350c2d938792fd74">GPIO_MODER_MODE9_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafdcb7c58d623c51ababeb5917430132b">GPIO_MODER_MODER9_Msk</a></td></tr>
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<tr class="separator:ga0acba3f02fb730df350c2d938792fd74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf81e4a6121d0fe0ee5bc3fbe0f245572" id="r_gaf81e4a6121d0fe0ee5bc3fbe0f245572"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf81e4a6121d0fe0ee5bc3fbe0f245572">GPIO_MODER_MODE9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5d4ed9018bf72565bab1d08c476fed20">GPIO_MODER_MODER9</a></td></tr>
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<tr class="separator:gaf81e4a6121d0fe0ee5bc3fbe0f245572"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga659899030e816750c2e4ecbf4250cc91" id="r_ga659899030e816750c2e4ecbf4250cc91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga659899030e816750c2e4ecbf4250cc91">GPIO_MODER_MODE9_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaea7c7ec787b1ee1ae7e0b4da216eb418">GPIO_MODER_MODER9_0</a></td></tr>
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<tr class="separator:ga659899030e816750c2e4ecbf4250cc91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15a408c473d172282468a1fccad482bb" id="r_ga15a408c473d172282468a1fccad482bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15a408c473d172282468a1fccad482bb">GPIO_MODER_MODE9_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5cd33689071b7af70ece64a371645df">GPIO_MODER_MODER9_1</a></td></tr>
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<tr class="separator:ga15a408c473d172282468a1fccad482bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga034f78f504f81a1ed9a3d457792f4197" id="r_ga034f78f504f81a1ed9a3d457792f4197"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga034f78f504f81a1ed9a3d457792f4197">GPIO_MODER_MODE10_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacf36ddfa8971a143e722ca9897d6a554">GPIO_MODER_MODER10_Pos</a></td></tr>
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<tr class="separator:ga034f78f504f81a1ed9a3d457792f4197"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc0dafc52e2eb8562733153c8658e8f4" id="r_gadc0dafc52e2eb8562733153c8658e8f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc0dafc52e2eb8562733153c8658e8f4">GPIO_MODER_MODE10_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9af602f158627d6d61a2fcf7149a6178">GPIO_MODER_MODER10_Msk</a></td></tr>
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<tr class="separator:gadc0dafc52e2eb8562733153c8658e8f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10461308203bd8e510c3205e6a499c20" id="r_ga10461308203bd8e510c3205e6a499c20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10461308203bd8e510c3205e6a499c20">GPIO_MODER_MODE10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaacbdb241d7bebde85d7d0b42c2f35563">GPIO_MODER_MODER10</a></td></tr>
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<tr class="separator:ga10461308203bd8e510c3205e6a499c20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7aa2a41e913180598b59b20ffafc4a47" id="r_ga7aa2a41e913180598b59b20ffafc4a47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7aa2a41e913180598b59b20ffafc4a47">GPIO_MODER_MODE10_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f4d2b18e57e7b2f600e4f5d9b17bd95">GPIO_MODER_MODER10_0</a></td></tr>
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<tr class="separator:ga7aa2a41e913180598b59b20ffafc4a47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad59d8ec1da352c55b9cb65b751f193e1" id="r_gad59d8ec1da352c55b9cb65b751f193e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad59d8ec1da352c55b9cb65b751f193e1">GPIO_MODER_MODE10_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9dcae08e0f7afc002658a4ef4a764dc4">GPIO_MODER_MODER10_1</a></td></tr>
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<tr class="separator:gad59d8ec1da352c55b9cb65b751f193e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3c361d8935e5c043775a1dbf77b4530" id="r_gaf3c361d8935e5c043775a1dbf77b4530"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3c361d8935e5c043775a1dbf77b4530">GPIO_MODER_MODE11_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac60a554e688d63d15bce7240549d2ccb">GPIO_MODER_MODER11_Pos</a></td></tr>
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<tr class="separator:gaf3c361d8935e5c043775a1dbf77b4530"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga313382ddc024a2cde3a1a3bb6ff1fc4d" id="r_ga313382ddc024a2cde3a1a3bb6ff1fc4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga313382ddc024a2cde3a1a3bb6ff1fc4d">GPIO_MODER_MODE11_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a8fa719e9f98d2a7b4fd00ad41927d">GPIO_MODER_MODER11_Msk</a></td></tr>
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<tr class="separator:ga313382ddc024a2cde3a1a3bb6ff1fc4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4d968b108aa28b20cd40a7746004d2c" id="r_gad4d968b108aa28b20cd40a7746004d2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4d968b108aa28b20cd40a7746004d2c">GPIO_MODER_MODE11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf18bc295f7195fc050221287c4564474">GPIO_MODER_MODER11</a></td></tr>
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<tr class="separator:gad4d968b108aa28b20cd40a7746004d2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadeb4ecb54a0dc7f304007367e112725d" id="r_gadeb4ecb54a0dc7f304007367e112725d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadeb4ecb54a0dc7f304007367e112725d">GPIO_MODER_MODE11_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4082cd576f50cd2687e45557b70d458">GPIO_MODER_MODER11_0</a></td></tr>
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<tr class="separator:gadeb4ecb54a0dc7f304007367e112725d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a7b954225f0a664d602cba0ed1e03d4" id="r_ga7a7b954225f0a664d602cba0ed1e03d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a7b954225f0a664d602cba0ed1e03d4">GPIO_MODER_MODE11_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b2f611ae75f3441bad03866550f6263">GPIO_MODER_MODER11_1</a></td></tr>
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<tr class="separator:ga7a7b954225f0a664d602cba0ed1e03d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8967fa759f57e187e4b87b9723a12e05" id="r_ga8967fa759f57e187e4b87b9723a12e05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8967fa759f57e187e4b87b9723a12e05">GPIO_MODER_MODE12_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec7b868a25af299e046b49b017c1114f">GPIO_MODER_MODER12_Pos</a></td></tr>
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<tr class="separator:ga8967fa759f57e187e4b87b9723a12e05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bab0d5ff031fcff49dedb0c36073008" id="r_ga2bab0d5ff031fcff49dedb0c36073008"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bab0d5ff031fcff49dedb0c36073008">GPIO_MODER_MODE12_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd6d6390219a23c8420cc152901ca9bd">GPIO_MODER_MODER12_Msk</a></td></tr>
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<tr class="separator:ga2bab0d5ff031fcff49dedb0c36073008"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac09cecc889ead7bc7a079d4889da0578" id="r_gac09cecc889ead7bc7a079d4889da0578"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac09cecc889ead7bc7a079d4889da0578">GPIO_MODER_MODE12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63101c5c410b55b668ec190422dc3597">GPIO_MODER_MODER12</a></td></tr>
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<tr class="separator:gac09cecc889ead7bc7a079d4889da0578"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dc7e3ea6e86a627d7697dafbb7feab6" id="r_ga4dc7e3ea6e86a627d7697dafbb7feab6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dc7e3ea6e86a627d7697dafbb7feab6">GPIO_MODER_MODE12_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa89cd8ed328ed0116cbf51810fcd8788">GPIO_MODER_MODER12_0</a></td></tr>
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<tr class="separator:ga4dc7e3ea6e86a627d7697dafbb7feab6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a2313be3f7d3fb0f2203456beaa4efe" id="r_ga9a2313be3f7d3fb0f2203456beaa4efe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a2313be3f7d3fb0f2203456beaa4efe">GPIO_MODER_MODE12_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga74f91bdd676e477e4c19d30d3ea5c4c8">GPIO_MODER_MODER12_1</a></td></tr>
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<tr class="separator:ga9a2313be3f7d3fb0f2203456beaa4efe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4895814d5aa1829b1abfbd2d4df8b66" id="r_gac4895814d5aa1829b1abfbd2d4df8b66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4895814d5aa1829b1abfbd2d4df8b66">GPIO_MODER_MODE13_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e91d26a428aa90b419bf51324491246">GPIO_MODER_MODER13_Pos</a></td></tr>
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<tr class="separator:gac4895814d5aa1829b1abfbd2d4df8b66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02c48c21d983bab6115b056239d84217" id="r_ga02c48c21d983bab6115b056239d84217"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02c48c21d983bab6115b056239d84217">GPIO_MODER_MODE13_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ae7344fb7e360c013ae484a7b3ce06e">GPIO_MODER_MODER13_Msk</a></td></tr>
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<tr class="separator:ga02c48c21d983bab6115b056239d84217"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf38e8e70d58b97d462d45e6e116115be" id="r_gaf38e8e70d58b97d462d45e6e116115be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf38e8e70d58b97d462d45e6e116115be">GPIO_MODER_MODE13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga353af246bef5dca5aadfe6fe3fd695c3">GPIO_MODER_MODER13</a></td></tr>
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<tr class="separator:gaf38e8e70d58b97d462d45e6e116115be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga575519f151a9dda7c8e24d7c9e625b0f" id="r_ga575519f151a9dda7c8e24d7c9e625b0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga575519f151a9dda7c8e24d7c9e625b0f">GPIO_MODER_MODE13_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabc01e2e6cf45e8ec27d3a66ff36c2cfa">GPIO_MODER_MODER13_0</a></td></tr>
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<tr class="separator:ga575519f151a9dda7c8e24d7c9e625b0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad93a355f773bc67b68b0a665c5a15136" id="r_gad93a355f773bc67b68b0a665c5a15136"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad93a355f773bc67b68b0a665c5a15136">GPIO_MODER_MODE13_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71a30088f5475ae8774404ae7d41872e">GPIO_MODER_MODER13_1</a></td></tr>
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<tr class="separator:gad93a355f773bc67b68b0a665c5a15136"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab23c1a3d555305265fe00c4a2f25d705" id="r_gab23c1a3d555305265fe00c4a2f25d705"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab23c1a3d555305265fe00c4a2f25d705">GPIO_MODER_MODE14_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac67c9470dc741033d3254a4041e3d320">GPIO_MODER_MODER14_Pos</a></td></tr>
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<tr class="separator:gab23c1a3d555305265fe00c4a2f25d705"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ee9ecd8c12612d429efa6b2694b8a25" id="r_ga8ee9ecd8c12612d429efa6b2694b8a25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ee9ecd8c12612d429efa6b2694b8a25">GPIO_MODER_MODE14_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1fd4d1526a36e0838bc8c9bab621aba0">GPIO_MODER_MODER14_Msk</a></td></tr>
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<tr class="separator:ga8ee9ecd8c12612d429efa6b2694b8a25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e67512a90147ccad6991e5b16821811" id="r_ga1e67512a90147ccad6991e5b16821811"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e67512a90147ccad6991e5b16821811">GPIO_MODER_MODE14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga18a722f9682045c1d2460fedf32b02b1">GPIO_MODER_MODER14</a></td></tr>
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<tr class="separator:ga1e67512a90147ccad6991e5b16821811"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa664199b48953065ec3b16e7de90d9b" id="r_gaaa664199b48953065ec3b16e7de90d9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa664199b48953065ec3b16e7de90d9b">GPIO_MODER_MODE14_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad295063c22bd981239bc1b26f2e7f9c0">GPIO_MODER_MODER14_0</a></td></tr>
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<tr class="separator:gaaa664199b48953065ec3b16e7de90d9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e8638837bc4e6d69cd7635296a51730" id="r_ga1e8638837bc4e6d69cd7635296a51730"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e8638837bc4e6d69cd7635296a51730">GPIO_MODER_MODE14_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3a914796db9625d86996b6f6f5288">GPIO_MODER_MODER14_1</a></td></tr>
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<tr class="separator:ga1e8638837bc4e6d69cd7635296a51730"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga040b83bff88d237d447bfe658913f2e7" id="r_ga040b83bff88d237d447bfe658913f2e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga040b83bff88d237d447bfe658913f2e7">GPIO_MODER_MODE15_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac8c4f0c2ee0dbf7761c9acf9f4d9fa8b">GPIO_MODER_MODER15_Pos</a></td></tr>
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<tr class="separator:ga040b83bff88d237d447bfe658913f2e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbdbb728d5db2fb68bbedd6e4374827b" id="r_gacbdbb728d5db2fb68bbedd6e4374827b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbdbb728d5db2fb68bbedd6e4374827b">GPIO_MODER_MODE15_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97ba0885b9dda0bec8202305bf9cf0ad">GPIO_MODER_MODER15_Msk</a></td></tr>
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<tr class="separator:gacbdbb728d5db2fb68bbedd6e4374827b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8027405e42e74b5065861c067e0b9f77" id="r_ga8027405e42e74b5065861c067e0b9f77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8027405e42e74b5065861c067e0b9f77">GPIO_MODER_MODE15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaefc40e6fae78c1c5c857346793f9d4c8">GPIO_MODER_MODER15</a></td></tr>
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<tr class="separator:ga8027405e42e74b5065861c067e0b9f77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace9ec013afbf2e01286ca61726e92332" id="r_gace9ec013afbf2e01286ca61726e92332"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace9ec013afbf2e01286ca61726e92332">GPIO_MODER_MODE15_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c4b7f270eb99d851b84b9917fe49564">GPIO_MODER_MODER15_0</a></td></tr>
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<tr class="separator:gace9ec013afbf2e01286ca61726e92332"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7055ea8ec31fe604f1b5f04e2b194c4" id="r_gaf7055ea8ec31fe604f1b5f04e2b194c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7055ea8ec31fe604f1b5f04e2b194c4">GPIO_MODER_MODE15_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9297c041f5f74aec73e6f4dd89ad819c">GPIO_MODER_MODER15_1</a></td></tr>
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<tr class="separator:gaf7055ea8ec31fe604f1b5f04e2b194c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d59a7c3218b146d61516cabb81588d1" id="r_ga1d59a7c3218b146d61516cabb81588d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d59a7c3218b146d61516cabb81588d1">GPIO_OTYPER_OT0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga1d59a7c3218b146d61516cabb81588d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1dbf22f662367e7f4033c6ef85f69162" id="r_ga1dbf22f662367e7f4033c6ef85f69162"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1dbf22f662367e7f4033c6ef85f69162">GPIO_OTYPER_OT0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d59a7c3218b146d61516cabb81588d1">GPIO_OTYPER_OT0_Pos</a>)</td></tr>
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<tr class="separator:ga1dbf22f662367e7f4033c6ef85f69162"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2aebd85688999595239036bd63eac4a3" id="r_ga2aebd85688999595239036bd63eac4a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2aebd85688999595239036bd63eac4a3">GPIO_OTYPER_OT0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1dbf22f662367e7f4033c6ef85f69162">GPIO_OTYPER_OT0_Msk</a></td></tr>
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<tr class="separator:ga2aebd85688999595239036bd63eac4a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga592defc7541ea5c2463d0a5c9566a337" id="r_ga592defc7541ea5c2463d0a5c9566a337"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga592defc7541ea5c2463d0a5c9566a337">GPIO_OTYPER_OT1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga592defc7541ea5c2463d0a5c9566a337"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d6d2752a99a69a1ed6fde751477f65e" id="r_ga2d6d2752a99a69a1ed6fde751477f65e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d6d2752a99a69a1ed6fde751477f65e">GPIO_OTYPER_OT1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga592defc7541ea5c2463d0a5c9566a337">GPIO_OTYPER_OT1_Pos</a>)</td></tr>
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<tr class="separator:ga2d6d2752a99a69a1ed6fde751477f65e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c2e6db60417e319c9a8de701ab4d93d" id="r_ga3c2e6db60417e319c9a8de701ab4d93d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c2e6db60417e319c9a8de701ab4d93d">GPIO_OTYPER_OT1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d6d2752a99a69a1ed6fde751477f65e">GPIO_OTYPER_OT1_Msk</a></td></tr>
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<tr class="separator:ga3c2e6db60417e319c9a8de701ab4d93d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3a3f4f3a5a9a13e74861ada55fe8373" id="r_gac3a3f4f3a5a9a13e74861ada55fe8373"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3a3f4f3a5a9a13e74861ada55fe8373">GPIO_OTYPER_OT2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gac3a3f4f3a5a9a13e74861ada55fe8373"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90c1021a385b3e3ad84b5c3f55dcd2bd" id="r_ga90c1021a385b3e3ad84b5c3f55dcd2bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90c1021a385b3e3ad84b5c3f55dcd2bd">GPIO_OTYPER_OT2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3a3f4f3a5a9a13e74861ada55fe8373">GPIO_OTYPER_OT2_Pos</a>)</td></tr>
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<tr class="separator:ga90c1021a385b3e3ad84b5c3f55dcd2bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5478c1782217eec4b8d09fcc930a55c1" id="r_ga5478c1782217eec4b8d09fcc930a55c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5478c1782217eec4b8d09fcc930a55c1">GPIO_OTYPER_OT2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga90c1021a385b3e3ad84b5c3f55dcd2bd">GPIO_OTYPER_OT2_Msk</a></td></tr>
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<tr class="separator:ga5478c1782217eec4b8d09fcc930a55c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad678ac2b9b55a718f1e81237ee4a5b30" id="r_gad678ac2b9b55a718f1e81237ee4a5b30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad678ac2b9b55a718f1e81237ee4a5b30">GPIO_OTYPER_OT3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gad678ac2b9b55a718f1e81237ee4a5b30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac467eaf271fc0abc674a0f1657b754b9" id="r_gac467eaf271fc0abc674a0f1657b754b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac467eaf271fc0abc674a0f1657b754b9">GPIO_OTYPER_OT3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad678ac2b9b55a718f1e81237ee4a5b30">GPIO_OTYPER_OT3_Pos</a>)</td></tr>
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<tr class="separator:gac467eaf271fc0abc674a0f1657b754b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52cbd557435c2173e390b534cc6a893b" id="r_ga52cbd557435c2173e390b534cc6a893b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52cbd557435c2173e390b534cc6a893b">GPIO_OTYPER_OT3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac467eaf271fc0abc674a0f1657b754b9">GPIO_OTYPER_OT3_Msk</a></td></tr>
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<tr class="separator:ga52cbd557435c2173e390b534cc6a893b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9104ccbb9f57282217df7a4af2fa149" id="r_gaa9104ccbb9f57282217df7a4af2fa149"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9104ccbb9f57282217df7a4af2fa149">GPIO_OTYPER_OT4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaa9104ccbb9f57282217df7a4af2fa149"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab826bfea8ea3e5500900e31d24603a3f" id="r_gab826bfea8ea3e5500900e31d24603a3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab826bfea8ea3e5500900e31d24603a3f">GPIO_OTYPER_OT4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9104ccbb9f57282217df7a4af2fa149">GPIO_OTYPER_OT4_Pos</a>)</td></tr>
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<tr class="separator:gab826bfea8ea3e5500900e31d24603a3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedd72ae7a6ef61cb01d7b31e7ac3f02f" id="r_gaedd72ae7a6ef61cb01d7b31e7ac3f02f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedd72ae7a6ef61cb01d7b31e7ac3f02f">GPIO_OTYPER_OT4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab826bfea8ea3e5500900e31d24603a3f">GPIO_OTYPER_OT4_Msk</a></td></tr>
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<tr class="separator:gaedd72ae7a6ef61cb01d7b31e7ac3f02f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffcd8be7000a751ac97b432e6f8febcd" id="r_gaffcd8be7000a751ac97b432e6f8febcd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffcd8be7000a751ac97b432e6f8febcd">GPIO_OTYPER_OT5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaffcd8be7000a751ac97b432e6f8febcd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa41f6d81f21b5d4c984d318c3d5ea5fc" id="r_gaa41f6d81f21b5d4c984d318c3d5ea5fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa41f6d81f21b5d4c984d318c3d5ea5fc">GPIO_OTYPER_OT5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaffcd8be7000a751ac97b432e6f8febcd">GPIO_OTYPER_OT5_Pos</a>)</td></tr>
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<tr class="separator:gaa41f6d81f21b5d4c984d318c3d5ea5fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabfa602db904a1c4ac0bfe2f57e044f03" id="r_gabfa602db904a1c4ac0bfe2f57e044f03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfa602db904a1c4ac0bfe2f57e044f03">GPIO_OTYPER_OT5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa41f6d81f21b5d4c984d318c3d5ea5fc">GPIO_OTYPER_OT5_Msk</a></td></tr>
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<tr class="separator:gabfa602db904a1c4ac0bfe2f57e044f03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5673f4acd1ca97723538455ce2ad8fa5" id="r_ga5673f4acd1ca97723538455ce2ad8fa5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5673f4acd1ca97723538455ce2ad8fa5">GPIO_OTYPER_OT6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga5673f4acd1ca97723538455ce2ad8fa5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf04845f8e00f58279129c9d7cbc40340" id="r_gaf04845f8e00f58279129c9d7cbc40340"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf04845f8e00f58279129c9d7cbc40340">GPIO_OTYPER_OT6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5673f4acd1ca97723538455ce2ad8fa5">GPIO_OTYPER_OT6_Pos</a>)</td></tr>
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<tr class="separator:gaf04845f8e00f58279129c9d7cbc40340"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga872f2008be45e90a2663c31f5e3858ee" id="r_ga872f2008be45e90a2663c31f5e3858ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga872f2008be45e90a2663c31f5e3858ee">GPIO_OTYPER_OT6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf04845f8e00f58279129c9d7cbc40340">GPIO_OTYPER_OT6_Msk</a></td></tr>
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<tr class="separator:ga872f2008be45e90a2663c31f5e3858ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5567f31bc7165b0a55e42a392306faf5" id="r_ga5567f31bc7165b0a55e42a392306faf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5567f31bc7165b0a55e42a392306faf5">GPIO_OTYPER_OT7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga5567f31bc7165b0a55e42a392306faf5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c4371991d169bbce9043ef03eebc3e7" id="r_ga1c4371991d169bbce9043ef03eebc3e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c4371991d169bbce9043ef03eebc3e7">GPIO_OTYPER_OT7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5567f31bc7165b0a55e42a392306faf5">GPIO_OTYPER_OT7_Pos</a>)</td></tr>
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<tr class="separator:ga1c4371991d169bbce9043ef03eebc3e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac22a8999bf349459af4bd58fe319d03" id="r_gaac22a8999bf349459af4bd58fe319d03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac22a8999bf349459af4bd58fe319d03">GPIO_OTYPER_OT7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c4371991d169bbce9043ef03eebc3e7">GPIO_OTYPER_OT7_Msk</a></td></tr>
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<tr class="separator:gaac22a8999bf349459af4bd58fe319d03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2df4811f95aae5d25c63d1e6645914e4" id="r_ga2df4811f95aae5d25c63d1e6645914e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2df4811f95aae5d25c63d1e6645914e4">GPIO_OTYPER_OT8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga2df4811f95aae5d25c63d1e6645914e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88986ea0ef6829d98ea063355ed574bd" id="r_ga88986ea0ef6829d98ea063355ed574bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88986ea0ef6829d98ea063355ed574bd">GPIO_OTYPER_OT8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2df4811f95aae5d25c63d1e6645914e4">GPIO_OTYPER_OT8_Pos</a>)</td></tr>
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<tr class="separator:ga88986ea0ef6829d98ea063355ed574bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b89d7c4cc8986895b4e4cbc8455f912" id="r_ga1b89d7c4cc8986895b4e4cbc8455f912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b89d7c4cc8986895b4e4cbc8455f912">GPIO_OTYPER_OT8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga88986ea0ef6829d98ea063355ed574bd">GPIO_OTYPER_OT8_Msk</a></td></tr>
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<tr class="separator:ga1b89d7c4cc8986895b4e4cbc8455f912"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a517c02253d8081d006ba12b939ddb7" id="r_ga9a517c02253d8081d006ba12b939ddb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a517c02253d8081d006ba12b939ddb7">GPIO_OTYPER_OT9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga9a517c02253d8081d006ba12b939ddb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23374263ed146dfa55de5e09a9984520" id="r_ga23374263ed146dfa55de5e09a9984520"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23374263ed146dfa55de5e09a9984520">GPIO_OTYPER_OT9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a517c02253d8081d006ba12b939ddb7">GPIO_OTYPER_OT9_Pos</a>)</td></tr>
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<tr class="separator:ga23374263ed146dfa55de5e09a9984520"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae53d4f666ee3410123ab941ee29fc886" id="r_gae53d4f666ee3410123ab941ee29fc886"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae53d4f666ee3410123ab941ee29fc886">GPIO_OTYPER_OT9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga23374263ed146dfa55de5e09a9984520">GPIO_OTYPER_OT9_Msk</a></td></tr>
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<tr class="separator:gae53d4f666ee3410123ab941ee29fc886"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ae2d866e0737d3b40919d877a321dbe" id="r_ga8ae2d866e0737d3b40919d877a321dbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ae2d866e0737d3b40919d877a321dbe">GPIO_OTYPER_OT10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga8ae2d866e0737d3b40919d877a321dbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga108993b457894e46ee48421cf847d6b6" id="r_ga108993b457894e46ee48421cf847d6b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga108993b457894e46ee48421cf847d6b6">GPIO_OTYPER_OT10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ae2d866e0737d3b40919d877a321dbe">GPIO_OTYPER_OT10_Pos</a>)</td></tr>
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<tr class="separator:ga108993b457894e46ee48421cf847d6b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bc9516ce236e7d3429066b16a7dfa9a" id="r_ga6bc9516ce236e7d3429066b16a7dfa9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bc9516ce236e7d3429066b16a7dfa9a">GPIO_OTYPER_OT10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga108993b457894e46ee48421cf847d6b6">GPIO_OTYPER_OT10_Msk</a></td></tr>
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<tr class="memitem:ga72764b8f1eaca4407ddce7f3313d045d" id="r_ga72764b8f1eaca4407ddce7f3313d045d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72764b8f1eaca4407ddce7f3313d045d">GPIO_OTYPER_OT11_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga0f833cf9e36cd48b282a838ee5d4d269" id="r_ga0f833cf9e36cd48b282a838ee5d4d269"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f833cf9e36cd48b282a838ee5d4d269">GPIO_OTYPER_OT11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga72764b8f1eaca4407ddce7f3313d045d">GPIO_OTYPER_OT11_Pos</a>)</td></tr>
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<tr class="memitem:ga9d842d0b79b54cd990a819197a0ecc6f" id="r_ga9d842d0b79b54cd990a819197a0ecc6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d842d0b79b54cd990a819197a0ecc6f">GPIO_OTYPER_OT11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f833cf9e36cd48b282a838ee5d4d269">GPIO_OTYPER_OT11_Msk</a></td></tr>
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<tr class="separator:ga9d842d0b79b54cd990a819197a0ecc6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9cbdcf0cf8146de12cb5ff36c6cbdc35" id="r_ga9cbdcf0cf8146de12cb5ff36c6cbdc35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cbdcf0cf8146de12cb5ff36c6cbdc35">GPIO_OTYPER_OT12_Pos</a>   (12U)</td></tr>
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<tr class="memitem:gac138e0a10703e6da87ff724a9e8314e6" id="r_gac138e0a10703e6da87ff724a9e8314e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac138e0a10703e6da87ff724a9e8314e6">GPIO_OTYPER_OT12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9cbdcf0cf8146de12cb5ff36c6cbdc35">GPIO_OTYPER_OT12_Pos</a>)</td></tr>
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<tr class="separator:gac138e0a10703e6da87ff724a9e8314e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ab821f1edc7c879a34e51d85be89927" id="r_ga6ab821f1edc7c879a34e51d85be89927"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ab821f1edc7c879a34e51d85be89927">GPIO_OTYPER_OT12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac138e0a10703e6da87ff724a9e8314e6">GPIO_OTYPER_OT12_Msk</a></td></tr>
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<tr class="separator:ga6ab821f1edc7c879a34e51d85be89927"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25fc93b49714517d14b95c51496f4dde" id="r_ga25fc93b49714517d14b95c51496f4dde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25fc93b49714517d14b95c51496f4dde">GPIO_OTYPER_OT13_Pos</a>   (13U)</td></tr>
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<tr class="memitem:gacc65a535136ed14fbaba9d5557d766a9" id="r_gacc65a535136ed14fbaba9d5557d766a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc65a535136ed14fbaba9d5557d766a9">GPIO_OTYPER_OT13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25fc93b49714517d14b95c51496f4dde">GPIO_OTYPER_OT13_Pos</a>)</td></tr>
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<tr class="memitem:ga84f78f6726211e6183ec7fcd3a40d2a8" id="r_ga84f78f6726211e6183ec7fcd3a40d2a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84f78f6726211e6183ec7fcd3a40d2a8">GPIO_OTYPER_OT13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacc65a535136ed14fbaba9d5557d766a9">GPIO_OTYPER_OT13_Msk</a></td></tr>
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<tr class="separator:ga84f78f6726211e6183ec7fcd3a40d2a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed656d73e74d6e4dc451d61cdd4529f9" id="r_gaed656d73e74d6e4dc451d61cdd4529f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed656d73e74d6e4dc451d61cdd4529f9">GPIO_OTYPER_OT14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gaed656d73e74d6e4dc451d61cdd4529f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7a50883c2c1f5f71ffed16b182b4690" id="r_gaf7a50883c2c1f5f71ffed16b182b4690"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7a50883c2c1f5f71ffed16b182b4690">GPIO_OTYPER_OT14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed656d73e74d6e4dc451d61cdd4529f9">GPIO_OTYPER_OT14_Pos</a>)</td></tr>
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<tr class="separator:gaf7a50883c2c1f5f71ffed16b182b4690"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1323319e1db0678046b6f77c45bfee8b" id="r_ga1323319e1db0678046b6f77c45bfee8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1323319e1db0678046b6f77c45bfee8b">GPIO_OTYPER_OT14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7a50883c2c1f5f71ffed16b182b4690">GPIO_OTYPER_OT14_Msk</a></td></tr>
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<tr class="separator:ga1323319e1db0678046b6f77c45bfee8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5efa1dc79a92b77579d2fd7fe2612c1b" id="r_ga5efa1dc79a92b77579d2fd7fe2612c1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5efa1dc79a92b77579d2fd7fe2612c1b">GPIO_OTYPER_OT15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga5efa1dc79a92b77579d2fd7fe2612c1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe5d4eaffe4617f72cc460127fc20cf5" id="r_gafe5d4eaffe4617f72cc460127fc20cf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe5d4eaffe4617f72cc460127fc20cf5">GPIO_OTYPER_OT15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5efa1dc79a92b77579d2fd7fe2612c1b">GPIO_OTYPER_OT15_Pos</a>)</td></tr>
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<tr class="separator:gafe5d4eaffe4617f72cc460127fc20cf5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c309a7ab680e01fcb7d001ea0a98c70" id="r_ga2c309a7ab680e01fcb7d001ea0a98c70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c309a7ab680e01fcb7d001ea0a98c70">GPIO_OTYPER_OT15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafe5d4eaffe4617f72cc460127fc20cf5">GPIO_OTYPER_OT15_Msk</a></td></tr>
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<tr class="separator:ga2c309a7ab680e01fcb7d001ea0a98c70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2f02eab04f88423789f532370680305" id="r_gaf2f02eab04f88423789f532370680305"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2f02eab04f88423789f532370680305">GPIO_OTYPER_OT_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2aebd85688999595239036bd63eac4a3">GPIO_OTYPER_OT0</a></td></tr>
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<tr class="memitem:ga8a842ad8f83c21f019f2e1e08f104a7f" id="r_ga8a842ad8f83c21f019f2e1e08f104a7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a842ad8f83c21f019f2e1e08f104a7f">GPIO_OTYPER_OT_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c2e6db60417e319c9a8de701ab4d93d">GPIO_OTYPER_OT1</a></td></tr>
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<tr class="separator:ga8a842ad8f83c21f019f2e1e08f104a7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d3a246b6320fc51b39123249e1e6817" id="r_ga3d3a246b6320fc51b39123249e1e6817"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d3a246b6320fc51b39123249e1e6817">GPIO_OTYPER_OT_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5478c1782217eec4b8d09fcc930a55c1">GPIO_OTYPER_OT2</a></td></tr>
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<tr class="separator:ga3d3a246b6320fc51b39123249e1e6817"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef881bb4fa6b2dd9cecd4ee1385b6361" id="r_gaef881bb4fa6b2dd9cecd4ee1385b6361"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef881bb4fa6b2dd9cecd4ee1385b6361">GPIO_OTYPER_OT_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga52cbd557435c2173e390b534cc6a893b">GPIO_OTYPER_OT3</a></td></tr>
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<tr class="separator:gaef881bb4fa6b2dd9cecd4ee1385b6361"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c3cc7a0b2c9b99212879cc8d7455258" id="r_ga8c3cc7a0b2c9b99212879cc8d7455258"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c3cc7a0b2c9b99212879cc8d7455258">GPIO_OTYPER_OT_4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaedd72ae7a6ef61cb01d7b31e7ac3f02f">GPIO_OTYPER_OT4</a></td></tr>
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<tr class="separator:ga8c3cc7a0b2c9b99212879cc8d7455258"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa0dd76857b25ae35a785cee97c8403d" id="r_gaaa0dd76857b25ae35a785cee97c8403d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa0dd76857b25ae35a785cee97c8403d">GPIO_OTYPER_OT_5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabfa602db904a1c4ac0bfe2f57e044f03">GPIO_OTYPER_OT5</a></td></tr>
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<tr class="separator:gaaa0dd76857b25ae35a785cee97c8403d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1dbea639fd4ffe59a706a11fb1ee104b" id="r_ga1dbea639fd4ffe59a706a11fb1ee104b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1dbea639fd4ffe59a706a11fb1ee104b">GPIO_OTYPER_OT_6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga872f2008be45e90a2663c31f5e3858ee">GPIO_OTYPER_OT6</a></td></tr>
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<tr class="separator:ga1dbea639fd4ffe59a706a11fb1ee104b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaacead96dc3377342af4aa18adf6453e" id="r_gaaacead96dc3377342af4aa18adf6453e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaacead96dc3377342af4aa18adf6453e">GPIO_OTYPER_OT_7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac22a8999bf349459af4bd58fe319d03">GPIO_OTYPER_OT7</a></td></tr>
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<tr class="separator:gaaacead96dc3377342af4aa18adf6453e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a1f64fdf2ab84c634c0fa8cb060a65f" id="r_ga5a1f64fdf2ab84c634c0fa8cb060a65f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a1f64fdf2ab84c634c0fa8cb060a65f">GPIO_OTYPER_OT_8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b89d7c4cc8986895b4e4cbc8455f912">GPIO_OTYPER_OT8</a></td></tr>
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<tr class="separator:ga5a1f64fdf2ab84c634c0fa8cb060a65f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5c7deea3d764bb3999578030e3158aa" id="r_gaa5c7deea3d764bb3999578030e3158aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5c7deea3d764bb3999578030e3158aa">GPIO_OTYPER_OT_9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae53d4f666ee3410123ab941ee29fc886">GPIO_OTYPER_OT9</a></td></tr>
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<tr class="separator:gaa5c7deea3d764bb3999578030e3158aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc1ef9cbe4226f9616c64bb641b44b3b" id="r_gadc1ef9cbe4226f9616c64bb641b44b3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc1ef9cbe4226f9616c64bb641b44b3b">GPIO_OTYPER_OT_10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6bc9516ce236e7d3429066b16a7dfa9a">GPIO_OTYPER_OT10</a></td></tr>
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<tr class="separator:gadc1ef9cbe4226f9616c64bb641b44b3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd4fc33a12439fdf4ada19c04227dea7" id="r_gafd4fc33a12439fdf4ada19c04227dea7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd4fc33a12439fdf4ada19c04227dea7">GPIO_OTYPER_OT_11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d842d0b79b54cd990a819197a0ecc6f">GPIO_OTYPER_OT11</a></td></tr>
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<tr class="separator:gafd4fc33a12439fdf4ada19c04227dea7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24e978fcc3d4e87bed919511e1226f0c" id="r_ga24e978fcc3d4e87bed919511e1226f0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24e978fcc3d4e87bed919511e1226f0c">GPIO_OTYPER_OT_12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ab821f1edc7c879a34e51d85be89927">GPIO_OTYPER_OT12</a></td></tr>
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<tr class="separator:ga24e978fcc3d4e87bed919511e1226f0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c5d7751cfdfaf58782f01692d8c88e8" id="r_ga7c5d7751cfdfaf58782f01692d8c88e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c5d7751cfdfaf58782f01692d8c88e8">GPIO_OTYPER_OT_13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga84f78f6726211e6183ec7fcd3a40d2a8">GPIO_OTYPER_OT13</a></td></tr>
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<tr class="separator:ga7c5d7751cfdfaf58782f01692d8c88e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c26938a0e8c03d90a966fc33f186e50" id="r_ga6c26938a0e8c03d90a966fc33f186e50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c26938a0e8c03d90a966fc33f186e50">GPIO_OTYPER_OT_14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1323319e1db0678046b6f77c45bfee8b">GPIO_OTYPER_OT14</a></td></tr>
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<tr class="separator:ga6c26938a0e8c03d90a966fc33f186e50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51f153263d58a45fc2ef0734fc3f73eb" id="r_ga51f153263d58a45fc2ef0734fc3f73eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51f153263d58a45fc2ef0734fc3f73eb">GPIO_OTYPER_OT_15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c309a7ab680e01fcb7d001ea0a98c70">GPIO_OTYPER_OT15</a></td></tr>
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<tr class="separator:ga51f153263d58a45fc2ef0734fc3f73eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga129f816361ac723f130c2757ab606de2" id="r_ga129f816361ac723f130c2757ab606de2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga129f816361ac723f130c2757ab606de2">GPIO_OSPEEDR_OSPEED0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gab411afa3d01185fcac7de1834855b03b" id="r_gab411afa3d01185fcac7de1834855b03b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab411afa3d01185fcac7de1834855b03b">GPIO_OSPEEDR_OSPEED0_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga129f816361ac723f130c2757ab606de2">GPIO_OSPEEDR_OSPEED0_Pos</a>)</td></tr>
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<tr class="memitem:ga25d567c6d24df0adb6402498fd5eb582" id="r_ga25d567c6d24df0adb6402498fd5eb582"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25d567c6d24df0adb6402498fd5eb582">GPIO_OSPEEDR_OSPEED0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab411afa3d01185fcac7de1834855b03b">GPIO_OSPEEDR_OSPEED0_Msk</a></td></tr>
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<tr class="memitem:gae999b23bc1e7f750599e3919db67bba7" id="r_gae999b23bc1e7f750599e3919db67bba7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae999b23bc1e7f750599e3919db67bba7">GPIO_OSPEEDR_OSPEED0_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga129f816361ac723f130c2757ab606de2">GPIO_OSPEEDR_OSPEED0_Pos</a>)</td></tr>
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<tr class="memitem:gaa211d91a2e8fa199d4d1c64e20c2283c" id="r_gaa211d91a2e8fa199d4d1c64e20c2283c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa211d91a2e8fa199d4d1c64e20c2283c">GPIO_OSPEEDR_OSPEED0_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga129f816361ac723f130c2757ab606de2">GPIO_OSPEEDR_OSPEED0_Pos</a>)</td></tr>
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<tr class="separator:gaa211d91a2e8fa199d4d1c64e20c2283c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8253e839d2f456baf264cc3639876b25" id="r_ga8253e839d2f456baf264cc3639876b25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8253e839d2f456baf264cc3639876b25">GPIO_OSPEEDR_OSPEED1_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga788188c5bf4669f2b316aa0c6b723e9e" id="r_ga788188c5bf4669f2b316aa0c6b723e9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga788188c5bf4669f2b316aa0c6b723e9e">GPIO_OSPEEDR_OSPEED1_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8253e839d2f456baf264cc3639876b25">GPIO_OSPEEDR_OSPEED1_Pos</a>)</td></tr>
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<tr class="separator:ga788188c5bf4669f2b316aa0c6b723e9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8996628496af3a04fb060e7be6b4af6" id="r_gab8996628496af3a04fb060e7be6b4af6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8996628496af3a04fb060e7be6b4af6">GPIO_OSPEEDR_OSPEED1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga788188c5bf4669f2b316aa0c6b723e9e">GPIO_OSPEEDR_OSPEED1_Msk</a></td></tr>
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<tr class="separator:gab8996628496af3a04fb060e7be6b4af6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08097ab565c4771df00762e15e93642c" id="r_ga08097ab565c4771df00762e15e93642c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08097ab565c4771df00762e15e93642c">GPIO_OSPEEDR_OSPEED1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8253e839d2f456baf264cc3639876b25">GPIO_OSPEEDR_OSPEED1_Pos</a>)</td></tr>
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<tr class="memitem:ga0cb2eaafcac4ea42ea17c030512fd59d" id="r_ga0cb2eaafcac4ea42ea17c030512fd59d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cb2eaafcac4ea42ea17c030512fd59d">GPIO_OSPEEDR_OSPEED1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8253e839d2f456baf264cc3639876b25">GPIO_OSPEEDR_OSPEED1_Pos</a>)</td></tr>
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<tr class="separator:ga0cb2eaafcac4ea42ea17c030512fd59d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcc5a8e431eddf53ff110e3cabcf84a9" id="r_gafcc5a8e431eddf53ff110e3cabcf84a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcc5a8e431eddf53ff110e3cabcf84a9">GPIO_OSPEEDR_OSPEED2_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga5a287b69df598692ea5425ac903ee934" id="r_ga5a287b69df598692ea5425ac903ee934"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a287b69df598692ea5425ac903ee934">GPIO_OSPEEDR_OSPEED2_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcc5a8e431eddf53ff110e3cabcf84a9">GPIO_OSPEEDR_OSPEED2_Pos</a>)</td></tr>
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<tr class="separator:ga5a287b69df598692ea5425ac903ee934"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00c3e1150ff05598e93fdee8dd68936e" id="r_ga00c3e1150ff05598e93fdee8dd68936e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00c3e1150ff05598e93fdee8dd68936e">GPIO_OSPEEDR_OSPEED2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a287b69df598692ea5425ac903ee934">GPIO_OSPEEDR_OSPEED2_Msk</a></td></tr>
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<tr class="separator:ga00c3e1150ff05598e93fdee8dd68936e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e96818c186656af3af439dcfa16528b" id="r_ga8e96818c186656af3af439dcfa16528b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e96818c186656af3af439dcfa16528b">GPIO_OSPEEDR_OSPEED2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcc5a8e431eddf53ff110e3cabcf84a9">GPIO_OSPEEDR_OSPEED2_Pos</a>)</td></tr>
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<tr class="separator:ga8e96818c186656af3af439dcfa16528b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2548db9b2371c3502f92f75566344141" id="r_ga2548db9b2371c3502f92f75566344141"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2548db9b2371c3502f92f75566344141">GPIO_OSPEEDR_OSPEED2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcc5a8e431eddf53ff110e3cabcf84a9">GPIO_OSPEEDR_OSPEED2_Pos</a>)</td></tr>
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<tr class="separator:ga2548db9b2371c3502f92f75566344141"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b5205a128da01cee0bf8911e6deeba3" id="r_ga2b5205a128da01cee0bf8911e6deeba3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b5205a128da01cee0bf8911e6deeba3">GPIO_OSPEEDR_OSPEED3_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga2b5205a128da01cee0bf8911e6deeba3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1932d5de59094f3b77d1c38c3363e022" id="r_ga1932d5de59094f3b77d1c38c3363e022"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1932d5de59094f3b77d1c38c3363e022">GPIO_OSPEEDR_OSPEED3_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b5205a128da01cee0bf8911e6deeba3">GPIO_OSPEEDR_OSPEED3_Pos</a>)</td></tr>
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<tr class="separator:ga1932d5de59094f3b77d1c38c3363e022"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70a77f985b46c258894f35dd089b0d20" id="r_ga70a77f985b46c258894f35dd089b0d20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70a77f985b46c258894f35dd089b0d20">GPIO_OSPEEDR_OSPEED3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1932d5de59094f3b77d1c38c3363e022">GPIO_OSPEEDR_OSPEED3_Msk</a></td></tr>
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<tr class="separator:ga70a77f985b46c258894f35dd089b0d20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2d54448afbd578a80e745bf88141f15" id="r_gaa2d54448afbd578a80e745bf88141f15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2d54448afbd578a80e745bf88141f15">GPIO_OSPEEDR_OSPEED3_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b5205a128da01cee0bf8911e6deeba3">GPIO_OSPEEDR_OSPEED3_Pos</a>)</td></tr>
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<tr class="separator:gaa2d54448afbd578a80e745bf88141f15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7445a434c85d73f0343f07e4b1abd2e" id="r_gaa7445a434c85d73f0343f07e4b1abd2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7445a434c85d73f0343f07e4b1abd2e">GPIO_OSPEEDR_OSPEED3_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b5205a128da01cee0bf8911e6deeba3">GPIO_OSPEEDR_OSPEED3_Pos</a>)</td></tr>
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<tr class="separator:gaa7445a434c85d73f0343f07e4b1abd2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8965c0a99fbe9052bf008a4da714b84b" id="r_ga8965c0a99fbe9052bf008a4da714b84b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8965c0a99fbe9052bf008a4da714b84b">GPIO_OSPEEDR_OSPEED4_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga8965c0a99fbe9052bf008a4da714b84b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91182962d406df7459584b8cb9646e9e" id="r_ga91182962d406df7459584b8cb9646e9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91182962d406df7459584b8cb9646e9e">GPIO_OSPEEDR_OSPEED4_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8965c0a99fbe9052bf008a4da714b84b">GPIO_OSPEEDR_OSPEED4_Pos</a>)</td></tr>
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<tr class="separator:ga91182962d406df7459584b8cb9646e9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44b7462b3a8eac83a6190a9d4ed94733" id="r_ga44b7462b3a8eac83a6190a9d4ed94733"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44b7462b3a8eac83a6190a9d4ed94733">GPIO_OSPEEDR_OSPEED4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga91182962d406df7459584b8cb9646e9e">GPIO_OSPEEDR_OSPEED4_Msk</a></td></tr>
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<tr class="separator:ga44b7462b3a8eac83a6190a9d4ed94733"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7bc92d4bc48eb29f15eeda3b4f2b7729" id="r_ga7bc92d4bc48eb29f15eeda3b4f2b7729"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7bc92d4bc48eb29f15eeda3b4f2b7729">GPIO_OSPEEDR_OSPEED4_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8965c0a99fbe9052bf008a4da714b84b">GPIO_OSPEEDR_OSPEED4_Pos</a>)</td></tr>
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<tr class="separator:ga7bc92d4bc48eb29f15eeda3b4f2b7729"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1074b9afc9555d005eed1283990ee2e" id="r_gaa1074b9afc9555d005eed1283990ee2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1074b9afc9555d005eed1283990ee2e">GPIO_OSPEEDR_OSPEED4_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8965c0a99fbe9052bf008a4da714b84b">GPIO_OSPEEDR_OSPEED4_Pos</a>)</td></tr>
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<tr class="separator:gaa1074b9afc9555d005eed1283990ee2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3dbca74e2ddaa85108e7326cd681c345" id="r_ga3dbca74e2ddaa85108e7326cd681c345"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3dbca74e2ddaa85108e7326cd681c345">GPIO_OSPEEDR_OSPEED5_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga3dbca74e2ddaa85108e7326cd681c345"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fe5071dcf994ca5836756cd44c7df76" id="r_ga9fe5071dcf994ca5836756cd44c7df76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fe5071dcf994ca5836756cd44c7df76">GPIO_OSPEEDR_OSPEED5_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3dbca74e2ddaa85108e7326cd681c345">GPIO_OSPEEDR_OSPEED5_Pos</a>)</td></tr>
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<tr class="separator:ga9fe5071dcf994ca5836756cd44c7df76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39a76e505a04bac8df5b801bc759d9cf" id="r_ga39a76e505a04bac8df5b801bc759d9cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39a76e505a04bac8df5b801bc759d9cf">GPIO_OSPEEDR_OSPEED5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9fe5071dcf994ca5836756cd44c7df76">GPIO_OSPEEDR_OSPEED5_Msk</a></td></tr>
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<tr class="separator:ga39a76e505a04bac8df5b801bc759d9cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51db6938ff53112b1546ea2955c6bec8" id="r_ga51db6938ff53112b1546ea2955c6bec8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51db6938ff53112b1546ea2955c6bec8">GPIO_OSPEEDR_OSPEED5_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3dbca74e2ddaa85108e7326cd681c345">GPIO_OSPEEDR_OSPEED5_Pos</a>)</td></tr>
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<tr class="separator:ga51db6938ff53112b1546ea2955c6bec8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33507bcb6d4a5f11748cd0f81483e900" id="r_ga33507bcb6d4a5f11748cd0f81483e900"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33507bcb6d4a5f11748cd0f81483e900">GPIO_OSPEEDR_OSPEED5_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3dbca74e2ddaa85108e7326cd681c345">GPIO_OSPEEDR_OSPEED5_Pos</a>)</td></tr>
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<tr class="separator:ga33507bcb6d4a5f11748cd0f81483e900"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2559ea5b8212d7799d95c5a67593826" id="r_gaa2559ea5b8212d7799d95c5a67593826"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2559ea5b8212d7799d95c5a67593826">GPIO_OSPEEDR_OSPEED6_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaa2559ea5b8212d7799d95c5a67593826"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f07ebb84c0aa6967ca9057d75f3d5cc" id="r_ga1f07ebb84c0aa6967ca9057d75f3d5cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f07ebb84c0aa6967ca9057d75f3d5cc">GPIO_OSPEEDR_OSPEED6_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2559ea5b8212d7799d95c5a67593826">GPIO_OSPEEDR_OSPEED6_Pos</a>)</td></tr>
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<tr class="separator:ga1f07ebb84c0aa6967ca9057d75f3d5cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga220c76017b851a0861252cdc19e5ad8e" id="r_ga220c76017b851a0861252cdc19e5ad8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga220c76017b851a0861252cdc19e5ad8e">GPIO_OSPEEDR_OSPEED6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f07ebb84c0aa6967ca9057d75f3d5cc">GPIO_OSPEEDR_OSPEED6_Msk</a></td></tr>
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<tr class="memitem:gab28c483d24d4f8aefdf89578af2a66a5" id="r_gab28c483d24d4f8aefdf89578af2a66a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab28c483d24d4f8aefdf89578af2a66a5">GPIO_OSPEEDR_OSPEED6_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2559ea5b8212d7799d95c5a67593826">GPIO_OSPEEDR_OSPEED6_Pos</a>)</td></tr>
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<tr class="memitem:gaa2d7d80ccb16466efc06dc08334539fe" id="r_gaa2d7d80ccb16466efc06dc08334539fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2d7d80ccb16466efc06dc08334539fe">GPIO_OSPEEDR_OSPEED6_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2559ea5b8212d7799d95c5a67593826">GPIO_OSPEEDR_OSPEED6_Pos</a>)</td></tr>
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<tr class="memitem:ga0e1d68c48b823f2ddcbc19f9472b71e0" id="r_ga0e1d68c48b823f2ddcbc19f9472b71e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e1d68c48b823f2ddcbc19f9472b71e0">GPIO_OSPEEDR_OSPEED7_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga0e1d68c48b823f2ddcbc19f9472b71e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab238b715009a8081e4299a04464f8fba" id="r_gab238b715009a8081e4299a04464f8fba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab238b715009a8081e4299a04464f8fba">GPIO_OSPEEDR_OSPEED7_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e1d68c48b823f2ddcbc19f9472b71e0">GPIO_OSPEEDR_OSPEED7_Pos</a>)</td></tr>
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<tr class="memitem:gada868726c50880ee3f5e3cf35bf7be07" id="r_gada868726c50880ee3f5e3cf35bf7be07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada868726c50880ee3f5e3cf35bf7be07">GPIO_OSPEEDR_OSPEED7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab238b715009a8081e4299a04464f8fba">GPIO_OSPEEDR_OSPEED7_Msk</a></td></tr>
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<tr class="separator:gada868726c50880ee3f5e3cf35bf7be07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga241f032a5afcf9fbaf7a03ca6756dae3" id="r_ga241f032a5afcf9fbaf7a03ca6756dae3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga241f032a5afcf9fbaf7a03ca6756dae3">GPIO_OSPEEDR_OSPEED7_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e1d68c48b823f2ddcbc19f9472b71e0">GPIO_OSPEEDR_OSPEED7_Pos</a>)</td></tr>
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<tr class="separator:ga241f032a5afcf9fbaf7a03ca6756dae3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55510fcf6f51a1badbd0507b0174ca82" id="r_ga55510fcf6f51a1badbd0507b0174ca82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55510fcf6f51a1badbd0507b0174ca82">GPIO_OSPEEDR_OSPEED7_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e1d68c48b823f2ddcbc19f9472b71e0">GPIO_OSPEEDR_OSPEED7_Pos</a>)</td></tr>
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<tr class="separator:ga55510fcf6f51a1badbd0507b0174ca82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga752447edb6283f5ab3639ea160311702" id="r_ga752447edb6283f5ab3639ea160311702"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga752447edb6283f5ab3639ea160311702">GPIO_OSPEEDR_OSPEED8_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga752447edb6283f5ab3639ea160311702"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b220cadf1c6f35a7a5ee9141b353361" id="r_ga1b220cadf1c6f35a7a5ee9141b353361"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b220cadf1c6f35a7a5ee9141b353361">GPIO_OSPEEDR_OSPEED8_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga752447edb6283f5ab3639ea160311702">GPIO_OSPEEDR_OSPEED8_Pos</a>)</td></tr>
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<tr class="separator:ga1b220cadf1c6f35a7a5ee9141b353361"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48fc91b25c5e9b44cb2c5281e430b530" id="r_ga48fc91b25c5e9b44cb2c5281e430b530"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48fc91b25c5e9b44cb2c5281e430b530">GPIO_OSPEEDR_OSPEED8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b220cadf1c6f35a7a5ee9141b353361">GPIO_OSPEEDR_OSPEED8_Msk</a></td></tr>
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<tr class="separator:ga48fc91b25c5e9b44cb2c5281e430b530"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9cc347eada649f592544fe46a60d61f" id="r_gaf9cc347eada649f592544fe46a60d61f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9cc347eada649f592544fe46a60d61f">GPIO_OSPEEDR_OSPEED8_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga752447edb6283f5ab3639ea160311702">GPIO_OSPEEDR_OSPEED8_Pos</a>)</td></tr>
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<tr class="separator:gaf9cc347eada649f592544fe46a60d61f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga001e0393d3563dce9de7822581d99f74" id="r_ga001e0393d3563dce9de7822581d99f74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga001e0393d3563dce9de7822581d99f74">GPIO_OSPEEDR_OSPEED8_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga752447edb6283f5ab3639ea160311702">GPIO_OSPEEDR_OSPEED8_Pos</a>)</td></tr>
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<tr class="separator:ga001e0393d3563dce9de7822581d99f74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05c5c757f8ec338edbbf08bf5d8d68c5" id="r_ga05c5c757f8ec338edbbf08bf5d8d68c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05c5c757f8ec338edbbf08bf5d8d68c5">GPIO_OSPEEDR_OSPEED9_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga05c5c757f8ec338edbbf08bf5d8d68c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaaf713561b3fe73574b8566e54dbb7da" id="r_gaaaf713561b3fe73574b8566e54dbb7da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaaf713561b3fe73574b8566e54dbb7da">GPIO_OSPEEDR_OSPEED9_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05c5c757f8ec338edbbf08bf5d8d68c5">GPIO_OSPEEDR_OSPEED9_Pos</a>)</td></tr>
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<tr class="separator:gaaaf713561b3fe73574b8566e54dbb7da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa18d29dd7797e82889241af2394d9bac" id="r_gaa18d29dd7797e82889241af2394d9bac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa18d29dd7797e82889241af2394d9bac">GPIO_OSPEEDR_OSPEED9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaaf713561b3fe73574b8566e54dbb7da">GPIO_OSPEEDR_OSPEED9_Msk</a></td></tr>
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<tr class="separator:gaa18d29dd7797e82889241af2394d9bac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79c3d503027ce61ba59f5362579c8c75" id="r_ga79c3d503027ce61ba59f5362579c8c75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79c3d503027ce61ba59f5362579c8c75">GPIO_OSPEEDR_OSPEED9_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05c5c757f8ec338edbbf08bf5d8d68c5">GPIO_OSPEEDR_OSPEED9_Pos</a>)</td></tr>
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<tr class="separator:ga79c3d503027ce61ba59f5362579c8c75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cf1f4b8620e0003ea2ee281c4d1a86e" id="r_ga8cf1f4b8620e0003ea2ee281c4d1a86e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cf1f4b8620e0003ea2ee281c4d1a86e">GPIO_OSPEEDR_OSPEED9_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05c5c757f8ec338edbbf08bf5d8d68c5">GPIO_OSPEEDR_OSPEED9_Pos</a>)</td></tr>
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<tr class="separator:ga8cf1f4b8620e0003ea2ee281c4d1a86e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fbf963f1c171fe8902f5b81b6e45e6e" id="r_ga4fbf963f1c171fe8902f5b81b6e45e6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fbf963f1c171fe8902f5b81b6e45e6e">GPIO_OSPEEDR_OSPEED10_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga4fbf963f1c171fe8902f5b81b6e45e6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7aa2187e9c9634216889077d878c85ae" id="r_ga7aa2187e9c9634216889077d878c85ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7aa2187e9c9634216889077d878c85ae">GPIO_OSPEEDR_OSPEED10_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4fbf963f1c171fe8902f5b81b6e45e6e">GPIO_OSPEEDR_OSPEED10_Pos</a>)</td></tr>
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<tr class="separator:ga7aa2187e9c9634216889077d878c85ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0d96748028e1d2c05fb5a12d6ec6148" id="r_gaa0d96748028e1d2c05fb5a12d6ec6148"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0d96748028e1d2c05fb5a12d6ec6148">GPIO_OSPEEDR_OSPEED10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7aa2187e9c9634216889077d878c85ae">GPIO_OSPEEDR_OSPEED10_Msk</a></td></tr>
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<tr class="separator:gaa0d96748028e1d2c05fb5a12d6ec6148"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4af74162b730df90c198dd5375c93db" id="r_gae4af74162b730df90c198dd5375c93db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4af74162b730df90c198dd5375c93db">GPIO_OSPEEDR_OSPEED10_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4fbf963f1c171fe8902f5b81b6e45e6e">GPIO_OSPEEDR_OSPEED10_Pos</a>)</td></tr>
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<tr class="separator:gae4af74162b730df90c198dd5375c93db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac42c58e1c4f708bb1702b980d7335481" id="r_gac42c58e1c4f708bb1702b980d7335481"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac42c58e1c4f708bb1702b980d7335481">GPIO_OSPEEDR_OSPEED10_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4fbf963f1c171fe8902f5b81b6e45e6e">GPIO_OSPEEDR_OSPEED10_Pos</a>)</td></tr>
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<tr class="separator:gac42c58e1c4f708bb1702b980d7335481"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab897b530b59c6f2f54305fb9db56fa9d" id="r_gab897b530b59c6f2f54305fb9db56fa9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab897b530b59c6f2f54305fb9db56fa9d">GPIO_OSPEEDR_OSPEED11_Pos</a>   (22U)</td></tr>
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<tr class="separator:gab897b530b59c6f2f54305fb9db56fa9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffc4df43b3ca66616ef75c75d828031f" id="r_gaffc4df43b3ca66616ef75c75d828031f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffc4df43b3ca66616ef75c75d828031f">GPIO_OSPEEDR_OSPEED11_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab897b530b59c6f2f54305fb9db56fa9d">GPIO_OSPEEDR_OSPEED11_Pos</a>)</td></tr>
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<tr class="separator:gaffc4df43b3ca66616ef75c75d828031f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae71fee4a9fee0076207522f7b05d3e7b" id="r_gae71fee4a9fee0076207522f7b05d3e7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae71fee4a9fee0076207522f7b05d3e7b">GPIO_OSPEEDR_OSPEED11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaffc4df43b3ca66616ef75c75d828031f">GPIO_OSPEEDR_OSPEED11_Msk</a></td></tr>
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<tr class="separator:gae71fee4a9fee0076207522f7b05d3e7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac1765e06791c8f44a8ab2771ce6e3e0" id="r_gaac1765e06791c8f44a8ab2771ce6e3e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac1765e06791c8f44a8ab2771ce6e3e0">GPIO_OSPEEDR_OSPEED11_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab897b530b59c6f2f54305fb9db56fa9d">GPIO_OSPEEDR_OSPEED11_Pos</a>)</td></tr>
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<tr class="separator:gaac1765e06791c8f44a8ab2771ce6e3e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad48d309936025096bfc6cb30fa37464c" id="r_gad48d309936025096bfc6cb30fa37464c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad48d309936025096bfc6cb30fa37464c">GPIO_OSPEEDR_OSPEED11_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab897b530b59c6f2f54305fb9db56fa9d">GPIO_OSPEEDR_OSPEED11_Pos</a>)</td></tr>
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<tr class="separator:gad48d309936025096bfc6cb30fa37464c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7326dbd78a260f065b3df743fbea3054" id="r_ga7326dbd78a260f065b3df743fbea3054"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7326dbd78a260f065b3df743fbea3054">GPIO_OSPEEDR_OSPEED12_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga7326dbd78a260f065b3df743fbea3054"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga941e03858f17e677f54ee229faacdeaa" id="r_ga941e03858f17e677f54ee229faacdeaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga941e03858f17e677f54ee229faacdeaa">GPIO_OSPEEDR_OSPEED12_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7326dbd78a260f065b3df743fbea3054">GPIO_OSPEEDR_OSPEED12_Pos</a>)</td></tr>
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<tr class="separator:ga941e03858f17e677f54ee229faacdeaa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91c0b6ceee5147b85871df78f1b7ae38" id="r_ga91c0b6ceee5147b85871df78f1b7ae38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91c0b6ceee5147b85871df78f1b7ae38">GPIO_OSPEEDR_OSPEED12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga941e03858f17e677f54ee229faacdeaa">GPIO_OSPEEDR_OSPEED12_Msk</a></td></tr>
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<tr class="separator:ga91c0b6ceee5147b85871df78f1b7ae38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga227ef84ae7d0d0ed7f2e01c26804ad0b" id="r_ga227ef84ae7d0d0ed7f2e01c26804ad0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga227ef84ae7d0d0ed7f2e01c26804ad0b">GPIO_OSPEEDR_OSPEED12_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7326dbd78a260f065b3df743fbea3054">GPIO_OSPEEDR_OSPEED12_Pos</a>)</td></tr>
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<tr class="separator:ga227ef84ae7d0d0ed7f2e01c26804ad0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42e694529900596202d4cdd7ba188427" id="r_ga42e694529900596202d4cdd7ba188427"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42e694529900596202d4cdd7ba188427">GPIO_OSPEEDR_OSPEED12_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7326dbd78a260f065b3df743fbea3054">GPIO_OSPEEDR_OSPEED12_Pos</a>)</td></tr>
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<tr class="separator:ga42e694529900596202d4cdd7ba188427"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8362c7b2a216297bbf58ea02b3df434d" id="r_ga8362c7b2a216297bbf58ea02b3df434d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8362c7b2a216297bbf58ea02b3df434d">GPIO_OSPEEDR_OSPEED13_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga8362c7b2a216297bbf58ea02b3df434d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga087816fdc310c1d74fa885b608c620c9" id="r_ga087816fdc310c1d74fa885b608c620c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga087816fdc310c1d74fa885b608c620c9">GPIO_OSPEEDR_OSPEED13_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8362c7b2a216297bbf58ea02b3df434d">GPIO_OSPEEDR_OSPEED13_Pos</a>)</td></tr>
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<tr class="separator:ga087816fdc310c1d74fa885b608c620c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabec7c4b2c0464c31b94d819b458294bc" id="r_gabec7c4b2c0464c31b94d819b458294bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabec7c4b2c0464c31b94d819b458294bc">GPIO_OSPEEDR_OSPEED13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga087816fdc310c1d74fa885b608c620c9">GPIO_OSPEEDR_OSPEED13_Msk</a></td></tr>
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<tr class="separator:gabec7c4b2c0464c31b94d819b458294bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27d214e42ae822601fe8469c5310337d" id="r_ga27d214e42ae822601fe8469c5310337d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27d214e42ae822601fe8469c5310337d">GPIO_OSPEEDR_OSPEED13_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8362c7b2a216297bbf58ea02b3df434d">GPIO_OSPEEDR_OSPEED13_Pos</a>)</td></tr>
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<tr class="separator:ga27d214e42ae822601fe8469c5310337d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2ce26af8af11b3592c5e70fddf24a1a" id="r_gad2ce26af8af11b3592c5e70fddf24a1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2ce26af8af11b3592c5e70fddf24a1a">GPIO_OSPEEDR_OSPEED13_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8362c7b2a216297bbf58ea02b3df434d">GPIO_OSPEEDR_OSPEED13_Pos</a>)</td></tr>
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<tr class="separator:gad2ce26af8af11b3592c5e70fddf24a1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga542445998ee4d4e0a1ecc80f96415769" id="r_ga542445998ee4d4e0a1ecc80f96415769"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga542445998ee4d4e0a1ecc80f96415769">GPIO_OSPEEDR_OSPEED14_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga542445998ee4d4e0a1ecc80f96415769"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fb875fe73210c3a4e1c269e030a357b" id="r_ga8fb875fe73210c3a4e1c269e030a357b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fb875fe73210c3a4e1c269e030a357b">GPIO_OSPEEDR_OSPEED14_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga542445998ee4d4e0a1ecc80f96415769">GPIO_OSPEEDR_OSPEED14_Pos</a>)</td></tr>
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<tr class="separator:ga8fb875fe73210c3a4e1c269e030a357b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa27efa359dedf4559a0cae3b4ccbb866" id="r_gaa27efa359dedf4559a0cae3b4ccbb866"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa27efa359dedf4559a0cae3b4ccbb866">GPIO_OSPEEDR_OSPEED14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fb875fe73210c3a4e1c269e030a357b">GPIO_OSPEEDR_OSPEED14_Msk</a></td></tr>
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<tr class="separator:gaa27efa359dedf4559a0cae3b4ccbb866"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf32f167e31bfe8d231d99369cad3a932" id="r_gaf32f167e31bfe8d231d99369cad3a932"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf32f167e31bfe8d231d99369cad3a932">GPIO_OSPEEDR_OSPEED14_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga542445998ee4d4e0a1ecc80f96415769">GPIO_OSPEEDR_OSPEED14_Pos</a>)</td></tr>
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<tr class="separator:gaf32f167e31bfe8d231d99369cad3a932"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e7a469a29270897c6a7f44e94fca1f2" id="r_ga2e7a469a29270897c6a7f44e94fca1f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e7a469a29270897c6a7f44e94fca1f2">GPIO_OSPEEDR_OSPEED14_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga542445998ee4d4e0a1ecc80f96415769">GPIO_OSPEEDR_OSPEED14_Pos</a>)</td></tr>
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<tr class="separator:ga2e7a469a29270897c6a7f44e94fca1f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e98a82b548dbb52cb0d16d6c9b68da9" id="r_ga0e98a82b548dbb52cb0d16d6c9b68da9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e98a82b548dbb52cb0d16d6c9b68da9">GPIO_OSPEEDR_OSPEED15_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga0e98a82b548dbb52cb0d16d6c9b68da9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45c126130830699c993c2d790c31f5e6" id="r_ga45c126130830699c993c2d790c31f5e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45c126130830699c993c2d790c31f5e6">GPIO_OSPEEDR_OSPEED15_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e98a82b548dbb52cb0d16d6c9b68da9">GPIO_OSPEEDR_OSPEED15_Pos</a>)</td></tr>
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<tr class="separator:ga45c126130830699c993c2d790c31f5e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62066038e31f29b2d96a9c9756b47007" id="r_ga62066038e31f29b2d96a9c9756b47007"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62066038e31f29b2d96a9c9756b47007">GPIO_OSPEEDR_OSPEED15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45c126130830699c993c2d790c31f5e6">GPIO_OSPEEDR_OSPEED15_Msk</a></td></tr>
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<tr class="separator:ga62066038e31f29b2d96a9c9756b47007"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4114c96c51d3cee45535ff5265b47b2" id="r_gaf4114c96c51d3cee45535ff5265b47b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4114c96c51d3cee45535ff5265b47b2">GPIO_OSPEEDR_OSPEED15_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e98a82b548dbb52cb0d16d6c9b68da9">GPIO_OSPEEDR_OSPEED15_Pos</a>)</td></tr>
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<tr class="separator:gaf4114c96c51d3cee45535ff5265b47b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01afd6d3720d359e6b8c76d03e6c5eb9" id="r_ga01afd6d3720d359e6b8c76d03e6c5eb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01afd6d3720d359e6b8c76d03e6c5eb9">GPIO_OSPEEDR_OSPEED15_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e98a82b548dbb52cb0d16d6c9b68da9">GPIO_OSPEEDR_OSPEED15_Pos</a>)</td></tr>
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<tr class="separator:ga01afd6d3720d359e6b8c76d03e6c5eb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86a137cc8e566a0da86e2fd4778938a6" id="r_ga86a137cc8e566a0da86e2fd4778938a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86a137cc8e566a0da86e2fd4778938a6">GPIO_OSPEEDER_OSPEEDR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga25d567c6d24df0adb6402498fd5eb582">GPIO_OSPEEDR_OSPEED0</a></td></tr>
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<tr class="separator:ga86a137cc8e566a0da86e2fd4778938a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95ff622f2b5941ce7202fe97a6e8c730" id="r_ga95ff622f2b5941ce7202fe97a6e8c730"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95ff622f2b5941ce7202fe97a6e8c730">GPIO_OSPEEDER_OSPEEDR0_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae999b23bc1e7f750599e3919db67bba7">GPIO_OSPEEDR_OSPEED0_0</a></td></tr>
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<tr class="separator:ga95ff622f2b5941ce7202fe97a6e8c730"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a8e561180cdfcb7440a017d2aa10f59" id="r_ga5a8e561180cdfcb7440a017d2aa10f59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a8e561180cdfcb7440a017d2aa10f59">GPIO_OSPEEDER_OSPEEDR0_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa211d91a2e8fa199d4d1c64e20c2283c">GPIO_OSPEEDR_OSPEED0_1</a></td></tr>
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<tr class="separator:ga5a8e561180cdfcb7440a017d2aa10f59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9aca2c7cf73dd7a08fee8ae9a675c1d5" id="r_ga9aca2c7cf73dd7a08fee8ae9a675c1d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9aca2c7cf73dd7a08fee8ae9a675c1d5">GPIO_OSPEEDER_OSPEEDR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab8996628496af3a04fb060e7be6b4af6">GPIO_OSPEEDR_OSPEED1</a></td></tr>
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<tr class="separator:ga9aca2c7cf73dd7a08fee8ae9a675c1d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5dd10c0d3419e2d2fda1af77fbc28156" id="r_ga5dd10c0d3419e2d2fda1af77fbc28156"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5dd10c0d3419e2d2fda1af77fbc28156">GPIO_OSPEEDER_OSPEEDR1_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga08097ab565c4771df00762e15e93642c">GPIO_OSPEEDR_OSPEED1_0</a></td></tr>
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<tr class="separator:ga5dd10c0d3419e2d2fda1af77fbc28156"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ebe740312db53a7d49ff7f78436bcb6" id="r_ga4ebe740312db53a7d49ff7f78436bcb6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ebe740312db53a7d49ff7f78436bcb6">GPIO_OSPEEDER_OSPEEDR1_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cb2eaafcac4ea42ea17c030512fd59d">GPIO_OSPEEDR_OSPEED1_1</a></td></tr>
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<tr class="separator:ga4ebe740312db53a7d49ff7f78436bcb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f3dd6eabaf2dee10a45718bf9214bff" id="r_ga9f3dd6eabaf2dee10a45718bf9214bff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f3dd6eabaf2dee10a45718bf9214bff">GPIO_OSPEEDER_OSPEEDR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga00c3e1150ff05598e93fdee8dd68936e">GPIO_OSPEEDR_OSPEED2</a></td></tr>
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<tr class="separator:ga9f3dd6eabaf2dee10a45718bf9214bff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga285b9f4328a29f624945f8fc57daab0e" id="r_ga285b9f4328a29f624945f8fc57daab0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga285b9f4328a29f624945f8fc57daab0e">GPIO_OSPEEDER_OSPEEDR2_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e96818c186656af3af439dcfa16528b">GPIO_OSPEEDR_OSPEED2_0</a></td></tr>
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<tr class="separator:ga285b9f4328a29f624945f8fc57daab0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb41ac1ecdc620a7888e9714f36611c2" id="r_gaeb41ac1ecdc620a7888e9714f36611c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb41ac1ecdc620a7888e9714f36611c2">GPIO_OSPEEDER_OSPEEDR2_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2548db9b2371c3502f92f75566344141">GPIO_OSPEEDR_OSPEED2_1</a></td></tr>
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<tr class="separator:gaeb41ac1ecdc620a7888e9714f36611c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bd77104c298e2cc79608954ed8a81e6" id="r_ga3bd77104c298e2cc79608954ed8a81e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bd77104c298e2cc79608954ed8a81e6">GPIO_OSPEEDER_OSPEEDR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga70a77f985b46c258894f35dd089b0d20">GPIO_OSPEEDR_OSPEED3</a></td></tr>
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<tr class="separator:ga3bd77104c298e2cc79608954ed8a81e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86ad8f39a6399526c2a06f5e481b7edd" id="r_ga86ad8f39a6399526c2a06f5e481b7edd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86ad8f39a6399526c2a06f5e481b7edd">GPIO_OSPEEDER_OSPEEDR3_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2d54448afbd578a80e745bf88141f15">GPIO_OSPEEDR_OSPEED3_0</a></td></tr>
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<tr class="separator:ga86ad8f39a6399526c2a06f5e481b7edd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4cbbc6c634d9f64d2959bfce25e475e3" id="r_ga4cbbc6c634d9f64d2959bfce25e475e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4cbbc6c634d9f64d2959bfce25e475e3">GPIO_OSPEEDER_OSPEEDR3_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7445a434c85d73f0343f07e4b1abd2e">GPIO_OSPEEDR_OSPEED3_1</a></td></tr>
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<tr class="separator:ga4cbbc6c634d9f64d2959bfce25e475e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae993f7764c1e10e2f5022cba2a081f97" id="r_gae993f7764c1e10e2f5022cba2a081f97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae993f7764c1e10e2f5022cba2a081f97">GPIO_OSPEEDER_OSPEEDR4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44b7462b3a8eac83a6190a9d4ed94733">GPIO_OSPEEDR_OSPEED4</a></td></tr>
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<tr class="separator:gae993f7764c1e10e2f5022cba2a081f97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e6579b81f162ca8d4b8ee6690b258e9" id="r_ga1e6579b81f162ca8d4b8ee6690b258e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e6579b81f162ca8d4b8ee6690b258e9">GPIO_OSPEEDER_OSPEEDR4_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7bc92d4bc48eb29f15eeda3b4f2b7729">GPIO_OSPEEDR_OSPEED4_0</a></td></tr>
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<tr class="memitem:ga56650b0113cbb5ed50903e684abfdabc" id="r_ga56650b0113cbb5ed50903e684abfdabc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56650b0113cbb5ed50903e684abfdabc">GPIO_OSPEEDER_OSPEEDR4_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1074b9afc9555d005eed1283990ee2e">GPIO_OSPEEDR_OSPEED4_1</a></td></tr>
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<tr class="memitem:gaa6e84a83dd64be450a33a67c9ba44add" id="r_gaa6e84a83dd64be450a33a67c9ba44add"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e84a83dd64be450a33a67c9ba44add">GPIO_OSPEEDER_OSPEEDR5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga39a76e505a04bac8df5b801bc759d9cf">GPIO_OSPEEDR_OSPEED5</a></td></tr>
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<tr class="memitem:ga0ee63c65224da433a0f588bdd579c88d" id="r_ga0ee63c65224da433a0f588bdd579c88d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ee63c65224da433a0f588bdd579c88d">GPIO_OSPEEDER_OSPEEDR5_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga51db6938ff53112b1546ea2955c6bec8">GPIO_OSPEEDR_OSPEED5_0</a></td></tr>
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<tr class="separator:ga0ee63c65224da433a0f588bdd579c88d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9feeadb829cbfbcc7f5ff5aa614e35de" id="r_ga9feeadb829cbfbcc7f5ff5aa614e35de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9feeadb829cbfbcc7f5ff5aa614e35de">GPIO_OSPEEDER_OSPEEDR5_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga33507bcb6d4a5f11748cd0f81483e900">GPIO_OSPEEDR_OSPEED5_1</a></td></tr>
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<tr class="separator:ga9feeadb829cbfbcc7f5ff5aa614e35de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa153220faa507b53170bd49dcffcfc76" id="r_gaa153220faa507b53170bd49dcffcfc76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa153220faa507b53170bd49dcffcfc76">GPIO_OSPEEDER_OSPEEDR6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga220c76017b851a0861252cdc19e5ad8e">GPIO_OSPEEDR_OSPEED6</a></td></tr>
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<tr class="memitem:ga314fae4f204824abf26545482246eb46" id="r_ga314fae4f204824abf26545482246eb46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga314fae4f204824abf26545482246eb46">GPIO_OSPEEDER_OSPEEDR6_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab28c483d24d4f8aefdf89578af2a66a5">GPIO_OSPEEDR_OSPEED6_0</a></td></tr>
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<tr class="memitem:gad5502c629c3894c58a5e3e5e4398f92b" id="r_gad5502c629c3894c58a5e3e5e4398f92b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5502c629c3894c58a5e3e5e4398f92b">GPIO_OSPEEDER_OSPEEDR6_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2d7d80ccb16466efc06dc08334539fe">GPIO_OSPEEDR_OSPEED6_1</a></td></tr>
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<tr class="separator:gad5502c629c3894c58a5e3e5e4398f92b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga187b9c0a07272ef24ff4e579c2c724a9" id="r_ga187b9c0a07272ef24ff4e579c2c724a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga187b9c0a07272ef24ff4e579c2c724a9">GPIO_OSPEEDER_OSPEEDR7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada868726c50880ee3f5e3cf35bf7be07">GPIO_OSPEEDR_OSPEED7</a></td></tr>
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<tr class="separator:ga187b9c0a07272ef24ff4e579c2c724a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa351c9cc66134dd2077fe4936e10068e" id="r_gaa351c9cc66134dd2077fe4936e10068e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa351c9cc66134dd2077fe4936e10068e">GPIO_OSPEEDER_OSPEEDR7_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga241f032a5afcf9fbaf7a03ca6756dae3">GPIO_OSPEEDR_OSPEED7_0</a></td></tr>
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<tr class="separator:gaa351c9cc66134dd2077fe4936e10068e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5824b9a56d3ab570c90c02e959f8e8a3" id="r_ga5824b9a56d3ab570c90c02e959f8e8a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5824b9a56d3ab570c90c02e959f8e8a3">GPIO_OSPEEDER_OSPEEDR7_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga55510fcf6f51a1badbd0507b0174ca82">GPIO_OSPEEDR_OSPEED7_1</a></td></tr>
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<tr class="separator:ga5824b9a56d3ab570c90c02e959f8e8a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57fdec64829712f410b7099168d03335" id="r_ga57fdec64829712f410b7099168d03335"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57fdec64829712f410b7099168d03335">GPIO_OSPEEDER_OSPEEDR8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga48fc91b25c5e9b44cb2c5281e430b530">GPIO_OSPEEDR_OSPEED8</a></td></tr>
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<tr class="separator:ga57fdec64829712f410b7099168d03335"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00e257135823303b40c2dfe2054c72e6" id="r_ga00e257135823303b40c2dfe2054c72e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00e257135823303b40c2dfe2054c72e6">GPIO_OSPEEDER_OSPEEDR8_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9cc347eada649f592544fe46a60d61f">GPIO_OSPEEDR_OSPEED8_0</a></td></tr>
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<tr class="separator:ga00e257135823303b40c2dfe2054c72e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab026b036652fcab5dbec7fcccd8ec117" id="r_gab026b036652fcab5dbec7fcccd8ec117"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab026b036652fcab5dbec7fcccd8ec117">GPIO_OSPEEDER_OSPEEDR8_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga001e0393d3563dce9de7822581d99f74">GPIO_OSPEEDR_OSPEED8_1</a></td></tr>
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<tr class="separator:gab026b036652fcab5dbec7fcccd8ec117"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2974e9de8b939e683976d3244f946c5" id="r_gaf2974e9de8b939e683976d3244f946c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2974e9de8b939e683976d3244f946c5">GPIO_OSPEEDER_OSPEEDR9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa18d29dd7797e82889241af2394d9bac">GPIO_OSPEEDR_OSPEED9</a></td></tr>
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<tr class="separator:gaf2974e9de8b939e683976d3244f946c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga922dc2241064ba91a32163b52dc979a1" id="r_ga922dc2241064ba91a32163b52dc979a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga922dc2241064ba91a32163b52dc979a1">GPIO_OSPEEDER_OSPEEDR9_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga79c3d503027ce61ba59f5362579c8c75">GPIO_OSPEEDR_OSPEED9_0</a></td></tr>
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<tr class="memitem:ga8958bf41efda58bc0c216496c3523a95" id="r_ga8958bf41efda58bc0c216496c3523a95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8958bf41efda58bc0c216496c3523a95">GPIO_OSPEEDER_OSPEEDR9_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8cf1f4b8620e0003ea2ee281c4d1a86e">GPIO_OSPEEDR_OSPEED9_1</a></td></tr>
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<tr class="memitem:ga7f368a4fe9f84a2a1f75127cd92de706" id="r_ga7f368a4fe9f84a2a1f75127cd92de706"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f368a4fe9f84a2a1f75127cd92de706">GPIO_OSPEEDER_OSPEEDR10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0d96748028e1d2c05fb5a12d6ec6148">GPIO_OSPEEDR_OSPEED10</a></td></tr>
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<tr class="separator:ga7f368a4fe9f84a2a1f75127cd92de706"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad24e2db3605c0510221a5d6cc18de45d" id="r_gad24e2db3605c0510221a5d6cc18de45d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad24e2db3605c0510221a5d6cc18de45d">GPIO_OSPEEDER_OSPEEDR10_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae4af74162b730df90c198dd5375c93db">GPIO_OSPEEDR_OSPEED10_0</a></td></tr>
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<tr class="separator:gad24e2db3605c0510221a5d6cc18de45d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac0b5fe166b79464e9419092b50a216e8" id="r_gac0b5fe166b79464e9419092b50a216e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0b5fe166b79464e9419092b50a216e8">GPIO_OSPEEDER_OSPEEDR10_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac42c58e1c4f708bb1702b980d7335481">GPIO_OSPEEDR_OSPEED10_1</a></td></tr>
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<tr class="separator:gac0b5fe166b79464e9419092b50a216e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f6fbff92ca95c7b4b49b773993af08f" id="r_ga6f6fbff92ca95c7b4b49b773993af08f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f6fbff92ca95c7b4b49b773993af08f">GPIO_OSPEEDER_OSPEEDR11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae71fee4a9fee0076207522f7b05d3e7b">GPIO_OSPEEDR_OSPEED11</a></td></tr>
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<tr class="separator:ga6f6fbff92ca95c7b4b49b773993af08f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7413457e1249fedd60208f6d1fe66fec" id="r_ga7413457e1249fedd60208f6d1fe66fec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7413457e1249fedd60208f6d1fe66fec">GPIO_OSPEEDER_OSPEEDR11_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac1765e06791c8f44a8ab2771ce6e3e0">GPIO_OSPEEDR_OSPEED11_0</a></td></tr>
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<tr class="memitem:gad5a0177db55f86818a42240bf188c0bc" id="r_gad5a0177db55f86818a42240bf188c0bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5a0177db55f86818a42240bf188c0bc">GPIO_OSPEEDER_OSPEEDR11_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad48d309936025096bfc6cb30fa37464c">GPIO_OSPEEDR_OSPEED11_1</a></td></tr>
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<tr class="separator:gad5a0177db55f86818a42240bf188c0bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9928dcdc592ee959941c97aed702a99" id="r_gac9928dcdc592ee959941c97aed702a99"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9928dcdc592ee959941c97aed702a99">GPIO_OSPEEDER_OSPEEDR12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga91c0b6ceee5147b85871df78f1b7ae38">GPIO_OSPEEDR_OSPEED12</a></td></tr>
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<tr class="memitem:ga68d9034e325bf95773f70a9cc94598af" id="r_ga68d9034e325bf95773f70a9cc94598af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68d9034e325bf95773f70a9cc94598af">GPIO_OSPEEDER_OSPEEDR12_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga227ef84ae7d0d0ed7f2e01c26804ad0b">GPIO_OSPEEDR_OSPEED12_0</a></td></tr>
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<tr class="memitem:ga225f0a354cd3c2391ed922b08dbc0cae" id="r_ga225f0a354cd3c2391ed922b08dbc0cae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga225f0a354cd3c2391ed922b08dbc0cae">GPIO_OSPEEDER_OSPEEDR12_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga42e694529900596202d4cdd7ba188427">GPIO_OSPEEDR_OSPEED12_1</a></td></tr>
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<tr class="separator:ga225f0a354cd3c2391ed922b08dbc0cae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09d3845b5e708a7636cddf01c5a30468" id="r_ga09d3845b5e708a7636cddf01c5a30468"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09d3845b5e708a7636cddf01c5a30468">GPIO_OSPEEDER_OSPEEDR13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabec7c4b2c0464c31b94d819b458294bc">GPIO_OSPEEDR_OSPEED13</a></td></tr>
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<tr class="separator:ga09d3845b5e708a7636cddf01c5a30468"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93ce0e08aefefa639657d0ca1a169557" id="r_ga93ce0e08aefefa639657d0ca1a169557"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93ce0e08aefefa639657d0ca1a169557">GPIO_OSPEEDER_OSPEEDR13_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga27d214e42ae822601fe8469c5310337d">GPIO_OSPEEDR_OSPEED13_0</a></td></tr>
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<tr class="memitem:ga2fee18398176eeceef1a6a0229d81029" id="r_ga2fee18398176eeceef1a6a0229d81029"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fee18398176eeceef1a6a0229d81029">GPIO_OSPEEDER_OSPEEDR13_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad2ce26af8af11b3592c5e70fddf24a1a">GPIO_OSPEEDR_OSPEED13_1</a></td></tr>
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<tr class="memitem:gae956b8918d07e914a3f9861de501623f" id="r_gae956b8918d07e914a3f9861de501623f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae956b8918d07e914a3f9861de501623f">GPIO_OSPEEDER_OSPEEDR14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa27efa359dedf4559a0cae3b4ccbb866">GPIO_OSPEEDR_OSPEED14</a></td></tr>
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<tr class="memitem:gafcec6386ada8c016b4696b853a6d1ff1" id="r_gafcec6386ada8c016b4696b853a6d1ff1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcec6386ada8c016b4696b853a6d1ff1">GPIO_OSPEEDER_OSPEEDR14_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf32f167e31bfe8d231d99369cad3a932">GPIO_OSPEEDR_OSPEED14_0</a></td></tr>
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<tr class="memitem:gae8fb23e47faf2dd2b69a22e36c4ea56d" id="r_gae8fb23e47faf2dd2b69a22e36c4ea56d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8fb23e47faf2dd2b69a22e36c4ea56d">GPIO_OSPEEDER_OSPEEDR14_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e7a469a29270897c6a7f44e94fca1f2">GPIO_OSPEEDR_OSPEED14_1</a></td></tr>
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<tr class="separator:gae8fb23e47faf2dd2b69a22e36c4ea56d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b405fe1beed00abecfb3d83b9f94b65" id="r_ga9b405fe1beed00abecfb3d83b9f94b65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b405fe1beed00abecfb3d83b9f94b65">GPIO_OSPEEDER_OSPEEDR15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga62066038e31f29b2d96a9c9756b47007">GPIO_OSPEEDR_OSPEED15</a></td></tr>
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<tr class="memitem:ga782862d03460b05a56d3287c971aabc8" id="r_ga782862d03460b05a56d3287c971aabc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga782862d03460b05a56d3287c971aabc8">GPIO_OSPEEDER_OSPEEDR15_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4114c96c51d3cee45535ff5265b47b2">GPIO_OSPEEDR_OSPEED15_0</a></td></tr>
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<tr class="memitem:ga929ae0a4ff8f30c45042715a73ab1ad7" id="r_ga929ae0a4ff8f30c45042715a73ab1ad7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga929ae0a4ff8f30c45042715a73ab1ad7">GPIO_OSPEEDER_OSPEEDR15_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga01afd6d3720d359e6b8c76d03e6c5eb9">GPIO_OSPEEDR_OSPEED15_1</a></td></tr>
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<tr class="separator:ga929ae0a4ff8f30c45042715a73ab1ad7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada27513a02562dc3e44c361eb96d8d60" id="r_gada27513a02562dc3e44c361eb96d8d60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada27513a02562dc3e44c361eb96d8d60">GPIO_PUPDR_PUPD0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gaa0be0e927e30b38360486e4d57854c20" id="r_gaa0be0e927e30b38360486e4d57854c20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0be0e927e30b38360486e4d57854c20">GPIO_PUPDR_PUPD0_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada27513a02562dc3e44c361eb96d8d60">GPIO_PUPDR_PUPD0_Pos</a>)</td></tr>
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<tr class="memitem:ga757af1d9f0ba5f4ed76320b6932e3741" id="r_ga757af1d9f0ba5f4ed76320b6932e3741"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga757af1d9f0ba5f4ed76320b6932e3741">GPIO_PUPDR_PUPD0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0be0e927e30b38360486e4d57854c20">GPIO_PUPDR_PUPD0_Msk</a></td></tr>
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<tr class="separator:ga757af1d9f0ba5f4ed76320b6932e3741"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ecb6eae6b933d78446834bf320cc235" id="r_ga7ecb6eae6b933d78446834bf320cc235"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ecb6eae6b933d78446834bf320cc235">GPIO_PUPDR_PUPD0_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada27513a02562dc3e44c361eb96d8d60">GPIO_PUPDR_PUPD0_Pos</a>)</td></tr>
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<tr class="separator:ga7ecb6eae6b933d78446834bf320cc235"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d8177954b7806374d1cbba3bbbfe034" id="r_ga9d8177954b7806374d1cbba3bbbfe034"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d8177954b7806374d1cbba3bbbfe034">GPIO_PUPDR_PUPD0_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada27513a02562dc3e44c361eb96d8d60">GPIO_PUPDR_PUPD0_Pos</a>)</td></tr>
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<tr class="separator:ga9d8177954b7806374d1cbba3bbbfe034"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2dc73dd62120c9617e25ccbf4b038991" id="r_ga2dc73dd62120c9617e25ccbf4b038991"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dc73dd62120c9617e25ccbf4b038991">GPIO_PUPDR_PUPD1_Pos</a>   (2U)</td></tr>
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<tr class="memitem:gac529eb9b34ed26a9fb436c230cbad882" id="r_gac529eb9b34ed26a9fb436c230cbad882"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac529eb9b34ed26a9fb436c230cbad882">GPIO_PUPDR_PUPD1_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2dc73dd62120c9617e25ccbf4b038991">GPIO_PUPDR_PUPD1_Pos</a>)</td></tr>
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<tr class="separator:gac529eb9b34ed26a9fb436c230cbad882"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8da0bf95f1973c18a4a4b7c0aa3d1404" id="r_ga8da0bf95f1973c18a4a4b7c0aa3d1404"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8da0bf95f1973c18a4a4b7c0aa3d1404">GPIO_PUPDR_PUPD1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac529eb9b34ed26a9fb436c230cbad882">GPIO_PUPDR_PUPD1_Msk</a></td></tr>
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<tr class="separator:ga8da0bf95f1973c18a4a4b7c0aa3d1404"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6512d7fee2b400279ebd0843a5e481c" id="r_gaf6512d7fee2b400279ebd0843a5e481c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6512d7fee2b400279ebd0843a5e481c">GPIO_PUPDR_PUPD1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2dc73dd62120c9617e25ccbf4b038991">GPIO_PUPDR_PUPD1_Pos</a>)</td></tr>
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<tr class="separator:gaf6512d7fee2b400279ebd0843a5e481c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb010cc75a60effd883969c35611f5c8" id="r_gadb010cc75a60effd883969c35611f5c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb010cc75a60effd883969c35611f5c8">GPIO_PUPDR_PUPD1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2dc73dd62120c9617e25ccbf4b038991">GPIO_PUPDR_PUPD1_Pos</a>)</td></tr>
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<tr class="separator:gadb010cc75a60effd883969c35611f5c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga586d58e70155a838a7607fa1d209e367" id="r_ga586d58e70155a838a7607fa1d209e367"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga586d58e70155a838a7607fa1d209e367">GPIO_PUPDR_PUPD2_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga586d58e70155a838a7607fa1d209e367"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa71a5ea0b0b124a1af187ef2160b412a" id="r_gaa71a5ea0b0b124a1af187ef2160b412a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa71a5ea0b0b124a1af187ef2160b412a">GPIO_PUPDR_PUPD2_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga586d58e70155a838a7607fa1d209e367">GPIO_PUPDR_PUPD2_Pos</a>)</td></tr>
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<tr class="separator:gaa71a5ea0b0b124a1af187ef2160b412a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e8cc32256e605234ec8bfba9ebbe2d2" id="r_ga0e8cc32256e605234ec8bfba9ebbe2d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e8cc32256e605234ec8bfba9ebbe2d2">GPIO_PUPDR_PUPD2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa71a5ea0b0b124a1af187ef2160b412a">GPIO_PUPDR_PUPD2_Msk</a></td></tr>
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<tr class="separator:ga0e8cc32256e605234ec8bfba9ebbe2d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga044bf572e114a7746127135a3f38caef" id="r_ga044bf572e114a7746127135a3f38caef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga044bf572e114a7746127135a3f38caef">GPIO_PUPDR_PUPD2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga586d58e70155a838a7607fa1d209e367">GPIO_PUPDR_PUPD2_Pos</a>)</td></tr>
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<tr class="separator:ga044bf572e114a7746127135a3f38caef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06efd822240e0026cb83e661b88a9e3c" id="r_ga06efd822240e0026cb83e661b88a9e3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06efd822240e0026cb83e661b88a9e3c">GPIO_PUPDR_PUPD2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga586d58e70155a838a7607fa1d209e367">GPIO_PUPDR_PUPD2_Pos</a>)</td></tr>
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<tr class="separator:ga06efd822240e0026cb83e661b88a9e3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16874909048265725250c4d8b3d1fe16" id="r_ga16874909048265725250c4d8b3d1fe16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16874909048265725250c4d8b3d1fe16">GPIO_PUPDR_PUPD3_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga16874909048265725250c4d8b3d1fe16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fbaf3b066dac1e0986a5b68ce30b0d3" id="r_ga4fbaf3b066dac1e0986a5b68ce30b0d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fbaf3b066dac1e0986a5b68ce30b0d3">GPIO_PUPDR_PUPD3_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16874909048265725250c4d8b3d1fe16">GPIO_PUPDR_PUPD3_Pos</a>)</td></tr>
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<tr class="separator:ga4fbaf3b066dac1e0986a5b68ce30b0d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c6217b6d33bf54771323d7f55e6fa9c" id="r_ga0c6217b6d33bf54771323d7f55e6fa9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c6217b6d33bf54771323d7f55e6fa9c">GPIO_PUPDR_PUPD3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4fbaf3b066dac1e0986a5b68ce30b0d3">GPIO_PUPDR_PUPD3_Msk</a></td></tr>
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<tr class="separator:ga0c6217b6d33bf54771323d7f55e6fa9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f885f83700f6710d75e8a23135e4449" id="r_ga1f885f83700f6710d75e8a23135e4449"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f885f83700f6710d75e8a23135e4449">GPIO_PUPDR_PUPD3_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16874909048265725250c4d8b3d1fe16">GPIO_PUPDR_PUPD3_Pos</a>)</td></tr>
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<tr class="separator:ga1f885f83700f6710d75e8a23135e4449"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga713dc2ffd7e76239f05399299043538a" id="r_ga713dc2ffd7e76239f05399299043538a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga713dc2ffd7e76239f05399299043538a">GPIO_PUPDR_PUPD3_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16874909048265725250c4d8b3d1fe16">GPIO_PUPDR_PUPD3_Pos</a>)</td></tr>
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<tr class="separator:ga713dc2ffd7e76239f05399299043538a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffa6624f76681ba96183f8ea998da581" id="r_gaffa6624f76681ba96183f8ea998da581"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffa6624f76681ba96183f8ea998da581">GPIO_PUPDR_PUPD4_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaffa6624f76681ba96183f8ea998da581"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f0de7c586465d6dfb0e50d1194271cf" id="r_ga1f0de7c586465d6dfb0e50d1194271cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f0de7c586465d6dfb0e50d1194271cf">GPIO_PUPDR_PUPD4_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaffa6624f76681ba96183f8ea998da581">GPIO_PUPDR_PUPD4_Pos</a>)</td></tr>
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<tr class="separator:ga1f0de7c586465d6dfb0e50d1194271cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf02aa5885737e111d98770d67b858d8e" id="r_gaf02aa5885737e111d98770d67b858d8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf02aa5885737e111d98770d67b858d8e">GPIO_PUPDR_PUPD4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f0de7c586465d6dfb0e50d1194271cf">GPIO_PUPDR_PUPD4_Msk</a></td></tr>
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<tr class="separator:gaf02aa5885737e111d98770d67b858d8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa25af0133be08cc46bd64d19913f090c" id="r_gaa25af0133be08cc46bd64d19913f090c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa25af0133be08cc46bd64d19913f090c">GPIO_PUPDR_PUPD4_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaffa6624f76681ba96183f8ea998da581">GPIO_PUPDR_PUPD4_Pos</a>)</td></tr>
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<tr class="separator:gaa25af0133be08cc46bd64d19913f090c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac699c89b1b15ad635a1a1109cbe2963e" id="r_gac699c89b1b15ad635a1a1109cbe2963e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac699c89b1b15ad635a1a1109cbe2963e">GPIO_PUPDR_PUPD4_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaffa6624f76681ba96183f8ea998da581">GPIO_PUPDR_PUPD4_Pos</a>)</td></tr>
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<tr class="separator:gac699c89b1b15ad635a1a1109cbe2963e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17c1aea5321b3308171bc9b813fccf02" id="r_ga17c1aea5321b3308171bc9b813fccf02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17c1aea5321b3308171bc9b813fccf02">GPIO_PUPDR_PUPD5_Pos</a>   (10U)</td></tr>
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<tr class="memitem:ga2dca8d52990a63a4185d8185d3100222" id="r_ga2dca8d52990a63a4185d8185d3100222"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dca8d52990a63a4185d8185d3100222">GPIO_PUPDR_PUPD5_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17c1aea5321b3308171bc9b813fccf02">GPIO_PUPDR_PUPD5_Pos</a>)</td></tr>
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<tr class="separator:ga2dca8d52990a63a4185d8185d3100222"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe54b8696e32251e874a821819d7c94d" id="r_gabe54b8696e32251e874a821819d7c94d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe54b8696e32251e874a821819d7c94d">GPIO_PUPDR_PUPD5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2dca8d52990a63a4185d8185d3100222">GPIO_PUPDR_PUPD5_Msk</a></td></tr>
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<tr class="separator:gabe54b8696e32251e874a821819d7c94d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31e7a8da20fb184d4bca472726c98058" id="r_ga31e7a8da20fb184d4bca472726c98058"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31e7a8da20fb184d4bca472726c98058">GPIO_PUPDR_PUPD5_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17c1aea5321b3308171bc9b813fccf02">GPIO_PUPDR_PUPD5_Pos</a>)</td></tr>
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<tr class="separator:ga31e7a8da20fb184d4bca472726c98058"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c3f4ba96ad50d3d5230fa8fb89f637d" id="r_ga0c3f4ba96ad50d3d5230fa8fb89f637d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c3f4ba96ad50d3d5230fa8fb89f637d">GPIO_PUPDR_PUPD5_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17c1aea5321b3308171bc9b813fccf02">GPIO_PUPDR_PUPD5_Pos</a>)</td></tr>
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<tr class="separator:ga0c3f4ba96ad50d3d5230fa8fb89f637d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5cfdcc6b1779a517c19516429c6666b" id="r_gac5cfdcc6b1779a517c19516429c6666b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5cfdcc6b1779a517c19516429c6666b">GPIO_PUPDR_PUPD6_Pos</a>   (12U)</td></tr>
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<tr class="separator:gac5cfdcc6b1779a517c19516429c6666b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga841c8e128f84ac7451f431d24a222072" id="r_ga841c8e128f84ac7451f431d24a222072"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga841c8e128f84ac7451f431d24a222072">GPIO_PUPDR_PUPD6_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac5cfdcc6b1779a517c19516429c6666b">GPIO_PUPDR_PUPD6_Pos</a>)</td></tr>
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<tr class="separator:ga841c8e128f84ac7451f431d24a222072"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa52d8b944af9bb59f52c2fd46559abdb" id="r_gaa52d8b944af9bb59f52c2fd46559abdb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa52d8b944af9bb59f52c2fd46559abdb">GPIO_PUPDR_PUPD6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga841c8e128f84ac7451f431d24a222072">GPIO_PUPDR_PUPD6_Msk</a></td></tr>
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<tr class="separator:gaa52d8b944af9bb59f52c2fd46559abdb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6aa2ea03e1632d3dfe812911bfd97f0b" id="r_ga6aa2ea03e1632d3dfe812911bfd97f0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6aa2ea03e1632d3dfe812911bfd97f0b">GPIO_PUPDR_PUPD6_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac5cfdcc6b1779a517c19516429c6666b">GPIO_PUPDR_PUPD6_Pos</a>)</td></tr>
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<tr class="separator:ga6aa2ea03e1632d3dfe812911bfd97f0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b5d490177e16ae30cd5264012feaa87" id="r_ga3b5d490177e16ae30cd5264012feaa87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b5d490177e16ae30cd5264012feaa87">GPIO_PUPDR_PUPD6_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac5cfdcc6b1779a517c19516429c6666b">GPIO_PUPDR_PUPD6_Pos</a>)</td></tr>
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<tr class="separator:ga3b5d490177e16ae30cd5264012feaa87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3de6729553a81ba44a7d1b93378d9536" id="r_ga3de6729553a81ba44a7d1b93378d9536"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3de6729553a81ba44a7d1b93378d9536">GPIO_PUPDR_PUPD7_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga3de6729553a81ba44a7d1b93378d9536"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga268436f429d673b3b39ea443656997ad" id="r_ga268436f429d673b3b39ea443656997ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga268436f429d673b3b39ea443656997ad">GPIO_PUPDR_PUPD7_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3de6729553a81ba44a7d1b93378d9536">GPIO_PUPDR_PUPD7_Pos</a>)</td></tr>
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<tr class="separator:ga268436f429d673b3b39ea443656997ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18557333a95ca1a26bcd1d7f9fe207be" id="r_ga18557333a95ca1a26bcd1d7f9fe207be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18557333a95ca1a26bcd1d7f9fe207be">GPIO_PUPDR_PUPD7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga268436f429d673b3b39ea443656997ad">GPIO_PUPDR_PUPD7_Msk</a></td></tr>
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<tr class="separator:ga18557333a95ca1a26bcd1d7f9fe207be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2954be6ab54a7d922b2d0f9e5d173f4" id="r_gae2954be6ab54a7d922b2d0f9e5d173f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2954be6ab54a7d922b2d0f9e5d173f4">GPIO_PUPDR_PUPD7_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3de6729553a81ba44a7d1b93378d9536">GPIO_PUPDR_PUPD7_Pos</a>)</td></tr>
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<tr class="separator:gae2954be6ab54a7d922b2d0f9e5d173f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb959dd401c4890303c5c7fd962bcc08" id="r_gabb959dd401c4890303c5c7fd962bcc08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb959dd401c4890303c5c7fd962bcc08">GPIO_PUPDR_PUPD7_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3de6729553a81ba44a7d1b93378d9536">GPIO_PUPDR_PUPD7_Pos</a>)</td></tr>
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<tr class="separator:gabb959dd401c4890303c5c7fd962bcc08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55b1f4d9f5e3bedd3c6af387409e5eba" id="r_ga55b1f4d9f5e3bedd3c6af387409e5eba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55b1f4d9f5e3bedd3c6af387409e5eba">GPIO_PUPDR_PUPD8_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga55b1f4d9f5e3bedd3c6af387409e5eba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga750db53344fb2cc3fb432ff0d7faa85c" id="r_ga750db53344fb2cc3fb432ff0d7faa85c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga750db53344fb2cc3fb432ff0d7faa85c">GPIO_PUPDR_PUPD8_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55b1f4d9f5e3bedd3c6af387409e5eba">GPIO_PUPDR_PUPD8_Pos</a>)</td></tr>
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<tr class="separator:ga750db53344fb2cc3fb432ff0d7faa85c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e71b61abf42a76033e458460793f940" id="r_ga0e71b61abf42a76033e458460793f940"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e71b61abf42a76033e458460793f940">GPIO_PUPDR_PUPD8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga750db53344fb2cc3fb432ff0d7faa85c">GPIO_PUPDR_PUPD8_Msk</a></td></tr>
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<tr class="separator:ga0e71b61abf42a76033e458460793f940"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga430de706497b304d9821b50b3a51ac49" id="r_ga430de706497b304d9821b50b3a51ac49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga430de706497b304d9821b50b3a51ac49">GPIO_PUPDR_PUPD8_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55b1f4d9f5e3bedd3c6af387409e5eba">GPIO_PUPDR_PUPD8_Pos</a>)</td></tr>
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<tr class="separator:ga430de706497b304d9821b50b3a51ac49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9a687c70a3cd5ef5ccef3a13e431b89" id="r_gae9a687c70a3cd5ef5ccef3a13e431b89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9a687c70a3cd5ef5ccef3a13e431b89">GPIO_PUPDR_PUPD8_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55b1f4d9f5e3bedd3c6af387409e5eba">GPIO_PUPDR_PUPD8_Pos</a>)</td></tr>
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<tr class="separator:gae9a687c70a3cd5ef5ccef3a13e431b89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0e83ee550967747ec5a38f064031b3e" id="r_gab0e83ee550967747ec5a38f064031b3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0e83ee550967747ec5a38f064031b3e">GPIO_PUPDR_PUPD9_Pos</a>   (18U)</td></tr>
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<tr class="separator:gab0e83ee550967747ec5a38f064031b3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae60c0e898107eed9a832cc445d00e8f8" id="r_gae60c0e898107eed9a832cc445d00e8f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae60c0e898107eed9a832cc445d00e8f8">GPIO_PUPDR_PUPD9_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab0e83ee550967747ec5a38f064031b3e">GPIO_PUPDR_PUPD9_Pos</a>)</td></tr>
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<tr class="separator:gae60c0e898107eed9a832cc445d00e8f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c7ece6fe1df8b61fd7f11f6751693a9" id="r_ga5c7ece6fe1df8b61fd7f11f6751693a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c7ece6fe1df8b61fd7f11f6751693a9">GPIO_PUPDR_PUPD9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae60c0e898107eed9a832cc445d00e8f8">GPIO_PUPDR_PUPD9_Msk</a></td></tr>
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<tr class="separator:ga5c7ece6fe1df8b61fd7f11f6751693a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b6a86ea34af6c236caa23893d34e6d2" id="r_ga5b6a86ea34af6c236caa23893d34e6d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b6a86ea34af6c236caa23893d34e6d2">GPIO_PUPDR_PUPD9_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab0e83ee550967747ec5a38f064031b3e">GPIO_PUPDR_PUPD9_Pos</a>)</td></tr>
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<tr class="separator:ga5b6a86ea34af6c236caa23893d34e6d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07fb1faf433996b633d49c8307ce9bb2" id="r_ga07fb1faf433996b633d49c8307ce9bb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07fb1faf433996b633d49c8307ce9bb2">GPIO_PUPDR_PUPD9_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab0e83ee550967747ec5a38f064031b3e">GPIO_PUPDR_PUPD9_Pos</a>)</td></tr>
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<tr class="separator:ga07fb1faf433996b633d49c8307ce9bb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19ff590a0540fab5751f0f0b36ea3ac8" id="r_ga19ff590a0540fab5751f0f0b36ea3ac8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19ff590a0540fab5751f0f0b36ea3ac8">GPIO_PUPDR_PUPD10_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga19ff590a0540fab5751f0f0b36ea3ac8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94f8b1bfa375b95aa586d4e657d810c1" id="r_ga94f8b1bfa375b95aa586d4e657d810c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94f8b1bfa375b95aa586d4e657d810c1">GPIO_PUPDR_PUPD10_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga19ff590a0540fab5751f0f0b36ea3ac8">GPIO_PUPDR_PUPD10_Pos</a>)</td></tr>
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<tr class="separator:ga94f8b1bfa375b95aa586d4e657d810c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53f1c72b27ac3f18d6e8c7b366416ba6" id="r_ga53f1c72b27ac3f18d6e8c7b366416ba6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53f1c72b27ac3f18d6e8c7b366416ba6">GPIO_PUPDR_PUPD10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga94f8b1bfa375b95aa586d4e657d810c1">GPIO_PUPDR_PUPD10_Msk</a></td></tr>
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<tr class="separator:ga53f1c72b27ac3f18d6e8c7b366416ba6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71dc18b0db03b06216a30e15bb08c81f" id="r_ga71dc18b0db03b06216a30e15bb08c81f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71dc18b0db03b06216a30e15bb08c81f">GPIO_PUPDR_PUPD10_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga19ff590a0540fab5751f0f0b36ea3ac8">GPIO_PUPDR_PUPD10_Pos</a>)</td></tr>
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<tr class="separator:ga71dc18b0db03b06216a30e15bb08c81f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga955fdb4da04d3702e3566d5068d9fd0a" id="r_ga955fdb4da04d3702e3566d5068d9fd0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga955fdb4da04d3702e3566d5068d9fd0a">GPIO_PUPDR_PUPD10_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga19ff590a0540fab5751f0f0b36ea3ac8">GPIO_PUPDR_PUPD10_Pos</a>)</td></tr>
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<tr class="separator:ga955fdb4da04d3702e3566d5068d9fd0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab55094695264b5c3342f623dec206815" id="r_gab55094695264b5c3342f623dec206815"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab55094695264b5c3342f623dec206815">GPIO_PUPDR_PUPD11_Pos</a>   (22U)</td></tr>
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<tr class="separator:gab55094695264b5c3342f623dec206815"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd0f388b7d8039e4b3d8dd573bc8f429" id="r_gabd0f388b7d8039e4b3d8dd573bc8f429"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd0f388b7d8039e4b3d8dd573bc8f429">GPIO_PUPDR_PUPD11_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab55094695264b5c3342f623dec206815">GPIO_PUPDR_PUPD11_Pos</a>)</td></tr>
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<tr class="separator:gabd0f388b7d8039e4b3d8dd573bc8f429"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85596aa60b034d0de6ecb98f94a8d036" id="r_ga85596aa60b034d0de6ecb98f94a8d036"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85596aa60b034d0de6ecb98f94a8d036">GPIO_PUPDR_PUPD11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd0f388b7d8039e4b3d8dd573bc8f429">GPIO_PUPDR_PUPD11_Msk</a></td></tr>
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<tr class="separator:ga85596aa60b034d0de6ecb98f94a8d036"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5acc6eda43958a03426815a0db4a494b" id="r_ga5acc6eda43958a03426815a0db4a494b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5acc6eda43958a03426815a0db4a494b">GPIO_PUPDR_PUPD11_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab55094695264b5c3342f623dec206815">GPIO_PUPDR_PUPD11_Pos</a>)</td></tr>
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<tr class="memitem:ga2666e7ba5f50abf8502ba8e0f0f57430" id="r_ga2666e7ba5f50abf8502ba8e0f0f57430"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2666e7ba5f50abf8502ba8e0f0f57430">GPIO_PUPDR_PUPD11_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab55094695264b5c3342f623dec206815">GPIO_PUPDR_PUPD11_Pos</a>)</td></tr>
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<tr class="separator:ga2666e7ba5f50abf8502ba8e0f0f57430"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2f7ab8ad7a8ac91e877e24f8119a783" id="r_gaa2f7ab8ad7a8ac91e877e24f8119a783"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2f7ab8ad7a8ac91e877e24f8119a783">GPIO_PUPDR_PUPD12_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaa2f7ab8ad7a8ac91e877e24f8119a783"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30a14d0a21b413ff9c5ff1efdec903bc" id="r_ga30a14d0a21b413ff9c5ff1efdec903bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30a14d0a21b413ff9c5ff1efdec903bc">GPIO_PUPDR_PUPD12_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2f7ab8ad7a8ac91e877e24f8119a783">GPIO_PUPDR_PUPD12_Pos</a>)</td></tr>
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<tr class="separator:ga30a14d0a21b413ff9c5ff1efdec903bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga834911368392a16ff6b7e051a7e7ae9c" id="r_ga834911368392a16ff6b7e051a7e7ae9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga834911368392a16ff6b7e051a7e7ae9c">GPIO_PUPDR_PUPD12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga30a14d0a21b413ff9c5ff1efdec903bc">GPIO_PUPDR_PUPD12_Msk</a></td></tr>
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<tr class="separator:ga834911368392a16ff6b7e051a7e7ae9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabac3dea5943de3917f93772936539e74" id="r_gabac3dea5943de3917f93772936539e74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabac3dea5943de3917f93772936539e74">GPIO_PUPDR_PUPD12_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2f7ab8ad7a8ac91e877e24f8119a783">GPIO_PUPDR_PUPD12_Pos</a>)</td></tr>
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<tr class="separator:gabac3dea5943de3917f93772936539e74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90f8b6c555a779ed1bef06e7ab1a0600" id="r_ga90f8b6c555a779ed1bef06e7ab1a0600"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90f8b6c555a779ed1bef06e7ab1a0600">GPIO_PUPDR_PUPD12_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2f7ab8ad7a8ac91e877e24f8119a783">GPIO_PUPDR_PUPD12_Pos</a>)</td></tr>
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<tr class="separator:ga90f8b6c555a779ed1bef06e7ab1a0600"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb87a27f5193bc33e7b553faa006086b" id="r_gadb87a27f5193bc33e7b553faa006086b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb87a27f5193bc33e7b553faa006086b">GPIO_PUPDR_PUPD13_Pos</a>   (26U)</td></tr>
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<tr class="separator:gadb87a27f5193bc33e7b553faa006086b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadebe9101a2f2de81d563e9e982c186cd" id="r_gadebe9101a2f2de81d563e9e982c186cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadebe9101a2f2de81d563e9e982c186cd">GPIO_PUPDR_PUPD13_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb87a27f5193bc33e7b553faa006086b">GPIO_PUPDR_PUPD13_Pos</a>)</td></tr>
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<tr class="separator:gadebe9101a2f2de81d563e9e982c186cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga746478979825dcad6323b002906581b9" id="r_ga746478979825dcad6323b002906581b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga746478979825dcad6323b002906581b9">GPIO_PUPDR_PUPD13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadebe9101a2f2de81d563e9e982c186cd">GPIO_PUPDR_PUPD13_Msk</a></td></tr>
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<tr class="separator:ga746478979825dcad6323b002906581b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4f37903148418084e6059041ac2d3c8" id="r_gab4f37903148418084e6059041ac2d3c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4f37903148418084e6059041ac2d3c8">GPIO_PUPDR_PUPD13_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb87a27f5193bc33e7b553faa006086b">GPIO_PUPDR_PUPD13_Pos</a>)</td></tr>
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<tr class="separator:gab4f37903148418084e6059041ac2d3c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4dd950825a4c5bb9e89e44f4398f050" id="r_gaf4dd950825a4c5bb9e89e44f4398f050"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4dd950825a4c5bb9e89e44f4398f050">GPIO_PUPDR_PUPD13_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb87a27f5193bc33e7b553faa006086b">GPIO_PUPDR_PUPD13_Pos</a>)</td></tr>
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<tr class="separator:gaf4dd950825a4c5bb9e89e44f4398f050"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4405ac26d78b02793fc695d410bd7b88" id="r_ga4405ac26d78b02793fc695d410bd7b88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4405ac26d78b02793fc695d410bd7b88">GPIO_PUPDR_PUPD14_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga4405ac26d78b02793fc695d410bd7b88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7e0dc8ebc4e7c81e65265cae3b23aa4" id="r_gaf7e0dc8ebc4e7c81e65265cae3b23aa4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7e0dc8ebc4e7c81e65265cae3b23aa4">GPIO_PUPDR_PUPD14_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4405ac26d78b02793fc695d410bd7b88">GPIO_PUPDR_PUPD14_Pos</a>)</td></tr>
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<tr class="separator:gaf7e0dc8ebc4e7c81e65265cae3b23aa4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga398c010d45105e8e37b1995430a52a94" id="r_ga398c010d45105e8e37b1995430a52a94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga398c010d45105e8e37b1995430a52a94">GPIO_PUPDR_PUPD14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7e0dc8ebc4e7c81e65265cae3b23aa4">GPIO_PUPDR_PUPD14_Msk</a></td></tr>
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<tr class="separator:ga398c010d45105e8e37b1995430a52a94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2312d606bfcd3b62e9885d7d7b316b39" id="r_ga2312d606bfcd3b62e9885d7d7b316b39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2312d606bfcd3b62e9885d7d7b316b39">GPIO_PUPDR_PUPD14_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4405ac26d78b02793fc695d410bd7b88">GPIO_PUPDR_PUPD14_Pos</a>)</td></tr>
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<tr class="separator:ga2312d606bfcd3b62e9885d7d7b316b39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88f904affe99bf7a5045c1c3704d1146" id="r_ga88f904affe99bf7a5045c1c3704d1146"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88f904affe99bf7a5045c1c3704d1146">GPIO_PUPDR_PUPD14_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4405ac26d78b02793fc695d410bd7b88">GPIO_PUPDR_PUPD14_Pos</a>)</td></tr>
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<tr class="separator:ga88f904affe99bf7a5045c1c3704d1146"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9596e5ba318ea6eb9d0de839e5125f7e" id="r_ga9596e5ba318ea6eb9d0de839e5125f7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9596e5ba318ea6eb9d0de839e5125f7e">GPIO_PUPDR_PUPD15_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga9596e5ba318ea6eb9d0de839e5125f7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae63e9b1d8c9e5f92cbb3f8ad67304f67" id="r_gae63e9b1d8c9e5f92cbb3f8ad67304f67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae63e9b1d8c9e5f92cbb3f8ad67304f67">GPIO_PUPDR_PUPD15_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9596e5ba318ea6eb9d0de839e5125f7e">GPIO_PUPDR_PUPD15_Pos</a>)</td></tr>
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<tr class="separator:gae63e9b1d8c9e5f92cbb3f8ad67304f67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd5cdc50a6f6ee671aa1ac39c9048241" id="r_gacd5cdc50a6f6ee671aa1ac39c9048241"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd5cdc50a6f6ee671aa1ac39c9048241">GPIO_PUPDR_PUPD15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae63e9b1d8c9e5f92cbb3f8ad67304f67">GPIO_PUPDR_PUPD15_Msk</a></td></tr>
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<tr class="separator:gacd5cdc50a6f6ee671aa1ac39c9048241"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39538a30aef08d4bbf9ce88ee22d1b46" id="r_ga39538a30aef08d4bbf9ce88ee22d1b46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39538a30aef08d4bbf9ce88ee22d1b46">GPIO_PUPDR_PUPD15_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9596e5ba318ea6eb9d0de839e5125f7e">GPIO_PUPDR_PUPD15_Pos</a>)</td></tr>
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<tr class="separator:ga39538a30aef08d4bbf9ce88ee22d1b46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24352127803f5fbe718ff22e7a1062b4" id="r_ga24352127803f5fbe718ff22e7a1062b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24352127803f5fbe718ff22e7a1062b4">GPIO_PUPDR_PUPD15_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9596e5ba318ea6eb9d0de839e5125f7e">GPIO_PUPDR_PUPD15_Pos</a>)</td></tr>
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<tr class="separator:ga24352127803f5fbe718ff22e7a1062b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04d9e85c6ccb1c915142139b2fd40277" id="r_ga04d9e85c6ccb1c915142139b2fd40277"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04d9e85c6ccb1c915142139b2fd40277">GPIO_PUPDR_PUPDR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga757af1d9f0ba5f4ed76320b6932e3741">GPIO_PUPDR_PUPD0</a></td></tr>
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<tr class="separator:ga04d9e85c6ccb1c915142139b2fd40277"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90ce7d30e6ae0b2faca4a6861ecc4cc6" id="r_ga90ce7d30e6ae0b2faca4a6861ecc4cc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90ce7d30e6ae0b2faca4a6861ecc4cc6">GPIO_PUPDR_PUPDR0_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ecb6eae6b933d78446834bf320cc235">GPIO_PUPDR_PUPD0_0</a></td></tr>
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<tr class="separator:ga90ce7d30e6ae0b2faca4a6861ecc4cc6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafce37884b3fefd13f415d3d0e86cba54" id="r_gafce37884b3fefd13f415d3d0e86cba54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafce37884b3fefd13f415d3d0e86cba54">GPIO_PUPDR_PUPDR0_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d8177954b7806374d1cbba3bbbfe034">GPIO_PUPDR_PUPD0_1</a></td></tr>
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<tr class="separator:gafce37884b3fefd13f415d3d0e86cba54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2fc992293f3aea2c0bfb5a04524a0f29" id="r_ga2fc992293f3aea2c0bfb5a04524a0f29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fc992293f3aea2c0bfb5a04524a0f29">GPIO_PUPDR_PUPDR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8da0bf95f1973c18a4a4b7c0aa3d1404">GPIO_PUPDR_PUPD1</a></td></tr>
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<tr class="separator:ga2fc992293f3aea2c0bfb5a04524a0f29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf102b1b4f826fdc1febfeaf42a7d8a7f" id="r_gaf102b1b4f826fdc1febfeaf42a7d8a7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf102b1b4f826fdc1febfeaf42a7d8a7f">GPIO_PUPDR_PUPDR1_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6512d7fee2b400279ebd0843a5e481c">GPIO_PUPDR_PUPD1_0</a></td></tr>
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<tr class="separator:gaf102b1b4f826fdc1febfeaf42a7d8a7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33e13010f729b9a9555c1af45ee42bf7" id="r_ga33e13010f729b9a9555c1af45ee42bf7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33e13010f729b9a9555c1af45ee42bf7">GPIO_PUPDR_PUPDR1_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadb010cc75a60effd883969c35611f5c8">GPIO_PUPDR_PUPD1_1</a></td></tr>
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<tr class="separator:ga33e13010f729b9a9555c1af45ee42bf7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga719f6a7905af1965aeb1d22053819ea4" id="r_ga719f6a7905af1965aeb1d22053819ea4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga719f6a7905af1965aeb1d22053819ea4">GPIO_PUPDR_PUPDR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e8cc32256e605234ec8bfba9ebbe2d2">GPIO_PUPDR_PUPD2</a></td></tr>
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<tr class="separator:ga719f6a7905af1965aeb1d22053819ea4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae53f1f88362bc9d12367842b2c41ac5f" id="r_gae53f1f88362bc9d12367842b2c41ac5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae53f1f88362bc9d12367842b2c41ac5f">GPIO_PUPDR_PUPDR2_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga044bf572e114a7746127135a3f38caef">GPIO_PUPDR_PUPD2_0</a></td></tr>
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<tr class="memitem:gad00c76742cc343b8be0aef2b7a552b21" id="r_gad00c76742cc343b8be0aef2b7a552b21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad00c76742cc343b8be0aef2b7a552b21">GPIO_PUPDR_PUPDR2_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06efd822240e0026cb83e661b88a9e3c">GPIO_PUPDR_PUPD2_1</a></td></tr>
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<tr class="memitem:gaaae9d69d2db60b442144cc0f7427455d" id="r_gaaae9d69d2db60b442144cc0f7427455d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaae9d69d2db60b442144cc0f7427455d">GPIO_PUPDR_PUPDR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c6217b6d33bf54771323d7f55e6fa9c">GPIO_PUPDR_PUPD3</a></td></tr>
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<tr class="memitem:ga1fa0a8d6a6bfc0dd9d6cd2cf26a736a9" id="r_ga1fa0a8d6a6bfc0dd9d6cd2cf26a736a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fa0a8d6a6bfc0dd9d6cd2cf26a736a9">GPIO_PUPDR_PUPDR3_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f885f83700f6710d75e8a23135e4449">GPIO_PUPDR_PUPD3_0</a></td></tr>
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<tr class="separator:ga1fa0a8d6a6bfc0dd9d6cd2cf26a736a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bd409075d0271cfcf5f2a382f55af83" id="r_ga9bd409075d0271cfcf5f2a382f55af83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bd409075d0271cfcf5f2a382f55af83">GPIO_PUPDR_PUPDR3_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga713dc2ffd7e76239f05399299043538a">GPIO_PUPDR_PUPD3_1</a></td></tr>
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<tr class="separator:ga9bd409075d0271cfcf5f2a382f55af83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46b83340a77ca8575458294e095a1b3e" id="r_ga46b83340a77ca8575458294e095a1b3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46b83340a77ca8575458294e095a1b3e">GPIO_PUPDR_PUPDR4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf02aa5885737e111d98770d67b858d8e">GPIO_PUPDR_PUPD4</a></td></tr>
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<tr class="memitem:gaaaa42ab206386a753e8d57b76761d787" id="r_gaaaa42ab206386a753e8d57b76761d787"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaaa42ab206386a753e8d57b76761d787">GPIO_PUPDR_PUPDR4_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa25af0133be08cc46bd64d19913f090c">GPIO_PUPDR_PUPD4_0</a></td></tr>
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<tr class="memitem:gaa7c19b72c8d4ebff81d9e7a6bb292d9e" id="r_gaa7c19b72c8d4ebff81d9e7a6bb292d9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7c19b72c8d4ebff81d9e7a6bb292d9e">GPIO_PUPDR_PUPDR4_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac699c89b1b15ad635a1a1109cbe2963e">GPIO_PUPDR_PUPD4_1</a></td></tr>
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<tr class="separator:gaa7c19b72c8d4ebff81d9e7a6bb292d9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga184f05795320c61aac7d5f99875aaaf3" id="r_ga184f05795320c61aac7d5f99875aaaf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga184f05795320c61aac7d5f99875aaaf3">GPIO_PUPDR_PUPDR5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe54b8696e32251e874a821819d7c94d">GPIO_PUPDR_PUPD5</a></td></tr>
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<tr class="separator:ga184f05795320c61aac7d5f99875aaaf3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga407f836cfe9440c0a9346bae50593324" id="r_ga407f836cfe9440c0a9346bae50593324"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga407f836cfe9440c0a9346bae50593324">GPIO_PUPDR_PUPDR5_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31e7a8da20fb184d4bca472726c98058">GPIO_PUPDR_PUPD5_0</a></td></tr>
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<tr class="memitem:ga6e969eee59eb13d03cecb10296f3cba3" id="r_ga6e969eee59eb13d03cecb10296f3cba3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e969eee59eb13d03cecb10296f3cba3">GPIO_PUPDR_PUPDR5_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c3f4ba96ad50d3d5230fa8fb89f637d">GPIO_PUPDR_PUPD5_1</a></td></tr>
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<tr class="separator:ga6e969eee59eb13d03cecb10296f3cba3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga867aff49673e9c790a7c07ffc94c9426" id="r_ga867aff49673e9c790a7c07ffc94c9426"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga867aff49673e9c790a7c07ffc94c9426">GPIO_PUPDR_PUPDR6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa52d8b944af9bb59f52c2fd46559abdb">GPIO_PUPDR_PUPD6</a></td></tr>
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<tr class="separator:ga867aff49673e9c790a7c07ffc94c9426"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa74c5941b0d588bfd8334c97dd16871e" id="r_gaa74c5941b0d588bfd8334c97dd16871e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa74c5941b0d588bfd8334c97dd16871e">GPIO_PUPDR_PUPDR6_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6aa2ea03e1632d3dfe812911bfd97f0b">GPIO_PUPDR_PUPD6_0</a></td></tr>
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<tr class="separator:gaa74c5941b0d588bfd8334c97dd16871e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84fe57689233ae16b9b38b3db0f8b31b" id="r_ga84fe57689233ae16b9b38b3db0f8b31b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84fe57689233ae16b9b38b3db0f8b31b">GPIO_PUPDR_PUPDR6_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b5d490177e16ae30cd5264012feaa87">GPIO_PUPDR_PUPD6_1</a></td></tr>
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<tr class="separator:ga84fe57689233ae16b9b38b3db0f8b31b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa747a73c564fc74b1b7cf597b4df2e2f" id="r_gaa747a73c564fc74b1b7cf597b4df2e2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa747a73c564fc74b1b7cf597b4df2e2f">GPIO_PUPDR_PUPDR7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga18557333a95ca1a26bcd1d7f9fe207be">GPIO_PUPDR_PUPD7</a></td></tr>
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<tr class="separator:gaa747a73c564fc74b1b7cf597b4df2e2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b75312f187bed2ef764a0f244b8cd1b" id="r_ga7b75312f187bed2ef764a0f244b8cd1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b75312f187bed2ef764a0f244b8cd1b">GPIO_PUPDR_PUPDR7_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae2954be6ab54a7d922b2d0f9e5d173f4">GPIO_PUPDR_PUPD7_0</a></td></tr>
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<tr class="separator:ga7b75312f187bed2ef764a0f244b8cd1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga284ea60cb769d74a000af43ddebfdbeb" id="r_ga284ea60cb769d74a000af43ddebfdbeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga284ea60cb769d74a000af43ddebfdbeb">GPIO_PUPDR_PUPDR7_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabb959dd401c4890303c5c7fd962bcc08">GPIO_PUPDR_PUPD7_1</a></td></tr>
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<tr class="separator:ga284ea60cb769d74a000af43ddebfdbeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c9d14950ed3985ab81c13047ac0df81" id="r_ga1c9d14950ed3985ab81c13047ac0df81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c9d14950ed3985ab81c13047ac0df81">GPIO_PUPDR_PUPDR8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e71b61abf42a76033e458460793f940">GPIO_PUPDR_PUPD8</a></td></tr>
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<tr class="separator:ga1c9d14950ed3985ab81c13047ac0df81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76b3b97a4a27a8bb2e942c0f95f7af31" id="r_ga76b3b97a4a27a8bb2e942c0f95f7af31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76b3b97a4a27a8bb2e942c0f95f7af31">GPIO_PUPDR_PUPDR8_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga430de706497b304d9821b50b3a51ac49">GPIO_PUPDR_PUPD8_0</a></td></tr>
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<tr class="separator:ga76b3b97a4a27a8bb2e942c0f95f7af31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9963e91e82f1059ec170793cbf32986" id="r_gab9963e91e82f1059ec170793cbf32986"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9963e91e82f1059ec170793cbf32986">GPIO_PUPDR_PUPDR8_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae9a687c70a3cd5ef5ccef3a13e431b89">GPIO_PUPDR_PUPD8_1</a></td></tr>
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<tr class="memitem:ga35b41b7cab641de2538e1e1d21562bc8" id="r_ga35b41b7cab641de2538e1e1d21562bc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35b41b7cab641de2538e1e1d21562bc8">GPIO_PUPDR_PUPDR9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c7ece6fe1df8b61fd7f11f6751693a9">GPIO_PUPDR_PUPD9</a></td></tr>
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<tr class="separator:ga35b41b7cab641de2538e1e1d21562bc8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45a4501a9b4ff20e5404a97031e02537" id="r_ga45a4501a9b4ff20e5404a97031e02537"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45a4501a9b4ff20e5404a97031e02537">GPIO_PUPDR_PUPDR9_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b6a86ea34af6c236caa23893d34e6d2">GPIO_PUPDR_PUPD9_0</a></td></tr>
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<tr class="separator:ga45a4501a9b4ff20e5404a97031e02537"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef8b9bad1bc1bb219f6b51bb12c48e67" id="r_gaef8b9bad1bc1bb219f6b51bb12c48e67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef8b9bad1bc1bb219f6b51bb12c48e67">GPIO_PUPDR_PUPDR9_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga07fb1faf433996b633d49c8307ce9bb2">GPIO_PUPDR_PUPD9_1</a></td></tr>
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<tr class="separator:gaef8b9bad1bc1bb219f6b51bb12c48e67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3ea3497ce2e90ac0e709e7a99088b09" id="r_gac3ea3497ce2e90ac0e709e7a99088b09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3ea3497ce2e90ac0e709e7a99088b09">GPIO_PUPDR_PUPDR10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga53f1c72b27ac3f18d6e8c7b366416ba6">GPIO_PUPDR_PUPD10</a></td></tr>
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<tr class="separator:gac3ea3497ce2e90ac0e709e7a99088b09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67fd34cdbc389ee49f5a9bf1271d7dd9" id="r_ga67fd34cdbc389ee49f5a9bf1271d7dd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67fd34cdbc389ee49f5a9bf1271d7dd9">GPIO_PUPDR_PUPDR10_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71dc18b0db03b06216a30e15bb08c81f">GPIO_PUPDR_PUPD10_0</a></td></tr>
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<tr class="memitem:ga08ac8e25da27d1b6c97647fd18b3a335" id="r_ga08ac8e25da27d1b6c97647fd18b3a335"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08ac8e25da27d1b6c97647fd18b3a335">GPIO_PUPDR_PUPDR10_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga955fdb4da04d3702e3566d5068d9fd0a">GPIO_PUPDR_PUPD10_1</a></td></tr>
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<tr class="separator:ga08ac8e25da27d1b6c97647fd18b3a335"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa93fd3e658c07a9daf9c8016fb4cf46" id="r_gaaa93fd3e658c07a9daf9c8016fb4cf46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa93fd3e658c07a9daf9c8016fb4cf46">GPIO_PUPDR_PUPDR11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga85596aa60b034d0de6ecb98f94a8d036">GPIO_PUPDR_PUPD11</a></td></tr>
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<tr class="separator:gaaa93fd3e658c07a9daf9c8016fb4cf46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18b3ea6ccb52b072cb19d6677b610831" id="r_ga18b3ea6ccb52b072cb19d6677b610831"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18b3ea6ccb52b072cb19d6677b610831">GPIO_PUPDR_PUPDR11_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5acc6eda43958a03426815a0db4a494b">GPIO_PUPDR_PUPD11_0</a></td></tr>
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<tr class="separator:ga18b3ea6ccb52b072cb19d6677b610831"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78a3508e309b9acfa99c3a4301dfb0d8" id="r_ga78a3508e309b9acfa99c3a4301dfb0d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78a3508e309b9acfa99c3a4301dfb0d8">GPIO_PUPDR_PUPDR11_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2666e7ba5f50abf8502ba8e0f0f57430">GPIO_PUPDR_PUPD11_1</a></td></tr>
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<tr class="separator:ga78a3508e309b9acfa99c3a4301dfb0d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ae4262e6f46de65ce93149a20e0d006" id="r_ga9ae4262e6f46de65ce93149a20e0d006"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ae4262e6f46de65ce93149a20e0d006">GPIO_PUPDR_PUPDR12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga834911368392a16ff6b7e051a7e7ae9c">GPIO_PUPDR_PUPD12</a></td></tr>
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<tr class="separator:ga9ae4262e6f46de65ce93149a20e0d006"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a0cd6d85037a7ae0d19806a7dc428a0" id="r_ga9a0cd6d85037a7ae0d19806a7dc428a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a0cd6d85037a7ae0d19806a7dc428a0">GPIO_PUPDR_PUPDR12_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabac3dea5943de3917f93772936539e74">GPIO_PUPDR_PUPD12_0</a></td></tr>
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<tr class="memitem:ga460b8f9029d8703782110e118fd6ccdb" id="r_ga460b8f9029d8703782110e118fd6ccdb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga460b8f9029d8703782110e118fd6ccdb">GPIO_PUPDR_PUPDR12_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga90f8b6c555a779ed1bef06e7ab1a0600">GPIO_PUPDR_PUPD12_1</a></td></tr>
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<tr class="memitem:gaa63ee70f61bc9df40d9b38af69f93a7e" id="r_gaa63ee70f61bc9df40d9b38af69f93a7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa63ee70f61bc9df40d9b38af69f93a7e">GPIO_PUPDR_PUPDR13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga746478979825dcad6323b002906581b9">GPIO_PUPDR_PUPD13</a></td></tr>
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<tr class="separator:gaa63ee70f61bc9df40d9b38af69f93a7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae29eccc9daf15c787ebfc26af3fb3194" id="r_gae29eccc9daf15c787ebfc26af3fb3194"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae29eccc9daf15c787ebfc26af3fb3194">GPIO_PUPDR_PUPDR13_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab4f37903148418084e6059041ac2d3c8">GPIO_PUPDR_PUPD13_0</a></td></tr>
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<tr class="memitem:ga80eddbf0106ccf71413851269315125d" id="r_ga80eddbf0106ccf71413851269315125d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80eddbf0106ccf71413851269315125d">GPIO_PUPDR_PUPDR13_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4dd950825a4c5bb9e89e44f4398f050">GPIO_PUPDR_PUPD13_1</a></td></tr>
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<tr class="separator:ga80eddbf0106ccf71413851269315125d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62f533a38f324be7e3e68f5c0f2b3570" id="r_ga62f533a38f324be7e3e68f5c0f2b3570"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62f533a38f324be7e3e68f5c0f2b3570">GPIO_PUPDR_PUPDR14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga398c010d45105e8e37b1995430a52a94">GPIO_PUPDR_PUPD14</a></td></tr>
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<tr class="separator:ga62f533a38f324be7e3e68f5c0f2b3570"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8521ddc4fa71b57540b61ec7803e77f" id="r_gad8521ddc4fa71b57540b61ec7803e77f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8521ddc4fa71b57540b61ec7803e77f">GPIO_PUPDR_PUPDR14_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2312d606bfcd3b62e9885d7d7b316b39">GPIO_PUPDR_PUPD14_0</a></td></tr>
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<tr class="separator:gad8521ddc4fa71b57540b61ec7803e77f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5bcc6307af9a6e5f578dfcb4fda49b3" id="r_gac5bcc6307af9a6e5f578dfcb4fda49b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5bcc6307af9a6e5f578dfcb4fda49b3">GPIO_PUPDR_PUPDR14_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga88f904affe99bf7a5045c1c3704d1146">GPIO_PUPDR_PUPD14_1</a></td></tr>
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<tr class="separator:gac5bcc6307af9a6e5f578dfcb4fda49b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac266bda493b96f1200bc0f7ae05a7475" id="r_gac266bda493b96f1200bc0f7ae05a7475"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac266bda493b96f1200bc0f7ae05a7475">GPIO_PUPDR_PUPDR15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacd5cdc50a6f6ee671aa1ac39c9048241">GPIO_PUPDR_PUPD15</a></td></tr>
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<tr class="separator:gac266bda493b96f1200bc0f7ae05a7475"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b6f6a720852e3791433148aab8b722c" id="r_ga0b6f6a720852e3791433148aab8b722c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b6f6a720852e3791433148aab8b722c">GPIO_PUPDR_PUPDR15_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga39538a30aef08d4bbf9ce88ee22d1b46">GPIO_PUPDR_PUPD15_0</a></td></tr>
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<tr class="separator:ga0b6f6a720852e3791433148aab8b722c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d827196cbbdebdf82554c8c04a1db6f" id="r_ga0d827196cbbdebdf82554c8c04a1db6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d827196cbbdebdf82554c8c04a1db6f">GPIO_PUPDR_PUPDR15_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga24352127803f5fbe718ff22e7a1062b4">GPIO_PUPDR_PUPD15_1</a></td></tr>
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<tr class="separator:ga0d827196cbbdebdf82554c8c04a1db6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1069cfa20fb4680057c8f9b91826ebe1" id="r_ga1069cfa20fb4680057c8f9b91826ebe1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1069cfa20fb4680057c8f9b91826ebe1">GPIO_IDR_ID0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga1069cfa20fb4680057c8f9b91826ebe1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fe6424f42570902856737fb45f7d321" id="r_ga8fe6424f42570902856737fb45f7d321"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fe6424f42570902856737fb45f7d321">GPIO_IDR_ID0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1069cfa20fb4680057c8f9b91826ebe1">GPIO_IDR_ID0_Pos</a>)</td></tr>
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<tr class="separator:ga8fe6424f42570902856737fb45f7d321"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64aa379a4bcfe84ae33383d689373096" id="r_ga64aa379a4bcfe84ae33383d689373096"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64aa379a4bcfe84ae33383d689373096">GPIO_IDR_ID0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fe6424f42570902856737fb45f7d321">GPIO_IDR_ID0_Msk</a></td></tr>
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<tr class="separator:ga64aa379a4bcfe84ae33383d689373096"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38320698cffb50138c8438a860030cb9" id="r_ga38320698cffb50138c8438a860030cb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38320698cffb50138c8438a860030cb9">GPIO_IDR_ID1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga38320698cffb50138c8438a860030cb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00dbb77370754ad461600ed3cf418dba" id="r_ga00dbb77370754ad461600ed3cf418dba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00dbb77370754ad461600ed3cf418dba">GPIO_IDR_ID1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga38320698cffb50138c8438a860030cb9">GPIO_IDR_ID1_Pos</a>)</td></tr>
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<tr class="separator:ga00dbb77370754ad461600ed3cf418dba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e44bbc1d39579b027765f259dc897ea" id="r_ga2e44bbc1d39579b027765f259dc897ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e44bbc1d39579b027765f259dc897ea">GPIO_IDR_ID1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga00dbb77370754ad461600ed3cf418dba">GPIO_IDR_ID1_Msk</a></td></tr>
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<tr class="separator:ga2e44bbc1d39579b027765f259dc897ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1720532896734b3e5ffaccd76834fdef" id="r_ga1720532896734b3e5ffaccd76834fdef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1720532896734b3e5ffaccd76834fdef">GPIO_IDR_ID2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga1720532896734b3e5ffaccd76834fdef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b48dad5247c404dda274ab5e5fde340" id="r_ga1b48dad5247c404dda274ab5e5fde340"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b48dad5247c404dda274ab5e5fde340">GPIO_IDR_ID2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1720532896734b3e5ffaccd76834fdef">GPIO_IDR_ID2_Pos</a>)</td></tr>
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<tr class="separator:ga1b48dad5247c404dda274ab5e5fde340"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2b06b287f35a0b048d8f5fbe4a06a9c" id="r_gaf2b06b287f35a0b048d8f5fbe4a06a9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2b06b287f35a0b048d8f5fbe4a06a9c">GPIO_IDR_ID2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b48dad5247c404dda274ab5e5fde340">GPIO_IDR_ID2_Msk</a></td></tr>
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<tr class="separator:gaf2b06b287f35a0b048d8f5fbe4a06a9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9ea4291861a56bb8901653b2c148ccd" id="r_gac9ea4291861a56bb8901653b2c148ccd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9ea4291861a56bb8901653b2c148ccd">GPIO_IDR_ID3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gac9ea4291861a56bb8901653b2c148ccd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ca640e7db8f27244ae9515a58910ae3" id="r_ga2ca640e7db8f27244ae9515a58910ae3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ca640e7db8f27244ae9515a58910ae3">GPIO_IDR_ID3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9ea4291861a56bb8901653b2c148ccd">GPIO_IDR_ID3_Pos</a>)</td></tr>
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<tr class="separator:ga2ca640e7db8f27244ae9515a58910ae3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac0c3adefa4cafaf0455139b4e80b70eb" id="r_gac0c3adefa4cafaf0455139b4e80b70eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0c3adefa4cafaf0455139b4e80b70eb">GPIO_IDR_ID3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ca640e7db8f27244ae9515a58910ae3">GPIO_IDR_ID3_Msk</a></td></tr>
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<tr class="separator:gac0c3adefa4cafaf0455139b4e80b70eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3acb4b4ccaae63ec98c19fbe056c74ae" id="r_ga3acb4b4ccaae63ec98c19fbe056c74ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3acb4b4ccaae63ec98c19fbe056c74ae">GPIO_IDR_ID4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga3acb4b4ccaae63ec98c19fbe056c74ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1d6c2b8346744bc456ea65d4365c207" id="r_gaa1d6c2b8346744bc456ea65d4365c207"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1d6c2b8346744bc456ea65d4365c207">GPIO_IDR_ID4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3acb4b4ccaae63ec98c19fbe056c74ae">GPIO_IDR_ID4_Pos</a>)</td></tr>
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<tr class="separator:gaa1d6c2b8346744bc456ea65d4365c207"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7454dab87916ca6076b287a21c2e4cd7" id="r_ga7454dab87916ca6076b287a21c2e4cd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7454dab87916ca6076b287a21c2e4cd7">GPIO_IDR_ID4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1d6c2b8346744bc456ea65d4365c207">GPIO_IDR_ID4_Msk</a></td></tr>
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<tr class="separator:ga7454dab87916ca6076b287a21c2e4cd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f45f4603706510827aa92d39fd4bb45" id="r_ga4f45f4603706510827aa92d39fd4bb45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f45f4603706510827aa92d39fd4bb45">GPIO_IDR_ID5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga4f45f4603706510827aa92d39fd4bb45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b44907427286bcb72189dbef6fc0148" id="r_ga8b44907427286bcb72189dbef6fc0148"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b44907427286bcb72189dbef6fc0148">GPIO_IDR_ID5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f45f4603706510827aa92d39fd4bb45">GPIO_IDR_ID5_Pos</a>)</td></tr>
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<tr class="separator:ga8b44907427286bcb72189dbef6fc0148"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cbfa2ff564030d912ce8f327850a3bf" id="r_ga2cbfa2ff564030d912ce8f327850a3bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cbfa2ff564030d912ce8f327850a3bf">GPIO_IDR_ID5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b44907427286bcb72189dbef6fc0148">GPIO_IDR_ID5_Msk</a></td></tr>
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<tr class="separator:ga2cbfa2ff564030d912ce8f327850a3bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbd6ccece5d47d40c929af5cf9973203" id="r_gafbd6ccece5d47d40c929af5cf9973203"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbd6ccece5d47d40c929af5cf9973203">GPIO_IDR_ID6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gafbd6ccece5d47d40c929af5cf9973203"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb18ccf8bb22161f83ad929a18d4c4aa" id="r_gafb18ccf8bb22161f83ad929a18d4c4aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb18ccf8bb22161f83ad929a18d4c4aa">GPIO_IDR_ID6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafbd6ccece5d47d40c929af5cf9973203">GPIO_IDR_ID6_Pos</a>)</td></tr>
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<tr class="separator:gafb18ccf8bb22161f83ad929a18d4c4aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac933b9235cae5f9fccbd2fc41f9a2dc4" id="r_gac933b9235cae5f9fccbd2fc41f9a2dc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac933b9235cae5f9fccbd2fc41f9a2dc4">GPIO_IDR_ID6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb18ccf8bb22161f83ad929a18d4c4aa">GPIO_IDR_ID6_Msk</a></td></tr>
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<tr class="separator:gac933b9235cae5f9fccbd2fc41f9a2dc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23669c60b1baa1d95dac788cff2a0eb8" id="r_ga23669c60b1baa1d95dac788cff2a0eb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23669c60b1baa1d95dac788cff2a0eb8">GPIO_IDR_ID7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga23669c60b1baa1d95dac788cff2a0eb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45c9835db5c12b661eae0c5a0a69af5a" id="r_ga45c9835db5c12b661eae0c5a0a69af5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45c9835db5c12b661eae0c5a0a69af5a">GPIO_IDR_ID7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga23669c60b1baa1d95dac788cff2a0eb8">GPIO_IDR_ID7_Pos</a>)</td></tr>
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<tr class="separator:ga45c9835db5c12b661eae0c5a0a69af5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09ce75fcb48ac0db30f99ba312e8538a" id="r_ga09ce75fcb48ac0db30f99ba312e8538a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09ce75fcb48ac0db30f99ba312e8538a">GPIO_IDR_ID7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45c9835db5c12b661eae0c5a0a69af5a">GPIO_IDR_ID7_Msk</a></td></tr>
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<tr class="separator:ga09ce75fcb48ac0db30f99ba312e8538a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaba7afe6abb55e6a80fb0ace5d46c883" id="r_gaaba7afe6abb55e6a80fb0ace5d46c883"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaba7afe6abb55e6a80fb0ace5d46c883">GPIO_IDR_ID8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaaba7afe6abb55e6a80fb0ace5d46c883"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08a268c98dea54059f48bbda7edd8e74" id="r_ga08a268c98dea54059f48bbda7edd8e74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08a268c98dea54059f48bbda7edd8e74">GPIO_IDR_ID8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaba7afe6abb55e6a80fb0ace5d46c883">GPIO_IDR_ID8_Pos</a>)</td></tr>
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<tr class="separator:ga08a268c98dea54059f48bbda7edd8e74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa193633720d142ceca6c6b27c4e87f02" id="r_gaa193633720d142ceca6c6b27c4e87f02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa193633720d142ceca6c6b27c4e87f02">GPIO_IDR_ID8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga08a268c98dea54059f48bbda7edd8e74">GPIO_IDR_ID8_Msk</a></td></tr>
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<tr class="separator:gaa193633720d142ceca6c6b27c4e87f02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad46ff99f2017c2a5eeab2fdeebfb1012" id="r_gad46ff99f2017c2a5eeab2fdeebfb1012"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad46ff99f2017c2a5eeab2fdeebfb1012">GPIO_IDR_ID9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gad46ff99f2017c2a5eeab2fdeebfb1012"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dad9a902a8200c53d60ba02de858315" id="r_ga4dad9a902a8200c53d60ba02de858315"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dad9a902a8200c53d60ba02de858315">GPIO_IDR_ID9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad46ff99f2017c2a5eeab2fdeebfb1012">GPIO_IDR_ID9_Pos</a>)</td></tr>
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<tr class="separator:ga4dad9a902a8200c53d60ba02de858315"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga888325b6581f9ae181f3e4fe904b0c44" id="r_ga888325b6581f9ae181f3e4fe904b0c44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga888325b6581f9ae181f3e4fe904b0c44">GPIO_IDR_ID9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4dad9a902a8200c53d60ba02de858315">GPIO_IDR_ID9_Msk</a></td></tr>
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<tr class="separator:ga888325b6581f9ae181f3e4fe904b0c44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6842601dbe73734e8058a6858fa7078" id="r_gaf6842601dbe73734e8058a6858fa7078"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6842601dbe73734e8058a6858fa7078">GPIO_IDR_ID10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaf6842601dbe73734e8058a6858fa7078"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa33d3d411ebb4a1009e148df02d2ac54" id="r_gaa33d3d411ebb4a1009e148df02d2ac54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa33d3d411ebb4a1009e148df02d2ac54">GPIO_IDR_ID10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6842601dbe73734e8058a6858fa7078">GPIO_IDR_ID10_Pos</a>)</td></tr>
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<tr class="separator:gaa33d3d411ebb4a1009e148df02d2ac54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cd53d2742d0ace30b835bd0f44f5ebf" id="r_ga6cd53d2742d0ace30b835bd0f44f5ebf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cd53d2742d0ace30b835bd0f44f5ebf">GPIO_IDR_ID10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa33d3d411ebb4a1009e148df02d2ac54">GPIO_IDR_ID10_Msk</a></td></tr>
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<tr class="separator:ga6cd53d2742d0ace30b835bd0f44f5ebf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga117cc21fe4de69983c2444c7f8587687" id="r_ga117cc21fe4de69983c2444c7f8587687"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga117cc21fe4de69983c2444c7f8587687">GPIO_IDR_ID11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga117cc21fe4de69983c2444c7f8587687"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad068577edb9af03083fcd0f4de0f8758" id="r_gad068577edb9af03083fcd0f4de0f8758"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad068577edb9af03083fcd0f4de0f8758">GPIO_IDR_ID11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga117cc21fe4de69983c2444c7f8587687">GPIO_IDR_ID11_Pos</a>)</td></tr>
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<tr class="separator:gad068577edb9af03083fcd0f4de0f8758"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade5e087b267f95733cc4328522b7890d" id="r_gade5e087b267f95733cc4328522b7890d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade5e087b267f95733cc4328522b7890d">GPIO_IDR_ID11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad068577edb9af03083fcd0f4de0f8758">GPIO_IDR_ID11_Msk</a></td></tr>
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<tr class="separator:gade5e087b267f95733cc4328522b7890d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bc8d6bc8dd7654ccb18d936a3efe79f" id="r_ga1bc8d6bc8dd7654ccb18d936a3efe79f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc8d6bc8dd7654ccb18d936a3efe79f">GPIO_IDR_ID12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga1bc8d6bc8dd7654ccb18d936a3efe79f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04a2965de2040e7c131ca5ab24a6724c" id="r_ga04a2965de2040e7c131ca5ab24a6724c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04a2965de2040e7c131ca5ab24a6724c">GPIO_IDR_ID12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc8d6bc8dd7654ccb18d936a3efe79f">GPIO_IDR_ID12_Pos</a>)</td></tr>
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<tr class="separator:ga04a2965de2040e7c131ca5ab24a6724c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33564d1679db8201389f806595d000d9" id="r_ga33564d1679db8201389f806595d000d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33564d1679db8201389f806595d000d9">GPIO_IDR_ID12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga04a2965de2040e7c131ca5ab24a6724c">GPIO_IDR_ID12_Msk</a></td></tr>
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<tr class="separator:ga33564d1679db8201389f806595d000d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada649f077b81777a8ba7ae97160e9fe4" id="r_gada649f077b81777a8ba7ae97160e9fe4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada649f077b81777a8ba7ae97160e9fe4">GPIO_IDR_ID13_Pos</a>   (13U)</td></tr>
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<tr class="separator:gada649f077b81777a8ba7ae97160e9fe4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38255de273b95c94e29c1bdaa637579e" id="r_ga38255de273b95c94e29c1bdaa637579e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38255de273b95c94e29c1bdaa637579e">GPIO_IDR_ID13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada649f077b81777a8ba7ae97160e9fe4">GPIO_IDR_ID13_Pos</a>)</td></tr>
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<tr class="separator:ga38255de273b95c94e29c1bdaa637579e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82e0ce0fca46443e3cbaf887a3a35713" id="r_ga82e0ce0fca46443e3cbaf887a3a35713"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82e0ce0fca46443e3cbaf887a3a35713">GPIO_IDR_ID13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38255de273b95c94e29c1bdaa637579e">GPIO_IDR_ID13_Msk</a></td></tr>
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<tr class="separator:ga82e0ce0fca46443e3cbaf887a3a35713"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0921a37817bff3c30f5e4c019b6a4084" id="r_ga0921a37817bff3c30f5e4c019b6a4084"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0921a37817bff3c30f5e4c019b6a4084">GPIO_IDR_ID14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga0921a37817bff3c30f5e4c019b6a4084"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacba67a5c308fb3b335dcd8979625b1b3" id="r_gacba67a5c308fb3b335dcd8979625b1b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacba67a5c308fb3b335dcd8979625b1b3">GPIO_IDR_ID14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0921a37817bff3c30f5e4c019b6a4084">GPIO_IDR_ID14_Pos</a>)</td></tr>
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<tr class="separator:gacba67a5c308fb3b335dcd8979625b1b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac716fc8a3853431b69697ea5ee0aa8d2" id="r_gac716fc8a3853431b69697ea5ee0aa8d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac716fc8a3853431b69697ea5ee0aa8d2">GPIO_IDR_ID14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacba67a5c308fb3b335dcd8979625b1b3">GPIO_IDR_ID14_Msk</a></td></tr>
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<tr class="separator:gac716fc8a3853431b69697ea5ee0aa8d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga631021cf3bab4864fdc505ceee8a6c4f" id="r_ga631021cf3bab4864fdc505ceee8a6c4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga631021cf3bab4864fdc505ceee8a6c4f">GPIO_IDR_ID15_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga631021cf3bab4864fdc505ceee8a6c4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18c156b5eb9356ecd1ba66c96864d5a5" id="r_ga18c156b5eb9356ecd1ba66c96864d5a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18c156b5eb9356ecd1ba66c96864d5a5">GPIO_IDR_ID15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga631021cf3bab4864fdc505ceee8a6c4f">GPIO_IDR_ID15_Pos</a>)</td></tr>
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<tr class="separator:ga18c156b5eb9356ecd1ba66c96864d5a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae72c80e97c41b8143cf299c078459ea4" id="r_gae72c80e97c41b8143cf299c078459ea4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae72c80e97c41b8143cf299c078459ea4">GPIO_IDR_ID15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga18c156b5eb9356ecd1ba66c96864d5a5">GPIO_IDR_ID15_Msk</a></td></tr>
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<tr class="separator:gae72c80e97c41b8143cf299c078459ea4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7691154d734ec08089eb3dc28a369726" id="r_ga7691154d734ec08089eb3dc28a369726"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7691154d734ec08089eb3dc28a369726">GPIO_IDR_IDR_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64aa379a4bcfe84ae33383d689373096">GPIO_IDR_ID0</a></td></tr>
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<tr class="separator:ga7691154d734ec08089eb3dc28a369726"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4b3e9ceaa683b7cbc89f2507ef0f110" id="r_gad4b3e9ceaa683b7cbc89f2507ef0f110"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4b3e9ceaa683b7cbc89f2507ef0f110">GPIO_IDR_IDR_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e44bbc1d39579b027765f259dc897ea">GPIO_IDR_ID1</a></td></tr>
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<tr class="separator:gad4b3e9ceaa683b7cbc89f2507ef0f110"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf32691b8213a6b9c7ddb164bcc66af7f" id="r_gaf32691b8213a6b9c7ddb164bcc66af7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf32691b8213a6b9c7ddb164bcc66af7f">GPIO_IDR_IDR_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2b06b287f35a0b048d8f5fbe4a06a9c">GPIO_IDR_ID2</a></td></tr>
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<tr class="separator:gaf32691b8213a6b9c7ddb164bcc66af7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga172dc9a76f772c8e386ac0162e0a52fa" id="r_ga172dc9a76f772c8e386ac0162e0a52fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga172dc9a76f772c8e386ac0162e0a52fa">GPIO_IDR_IDR_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac0c3adefa4cafaf0455139b4e80b70eb">GPIO_IDR_ID3</a></td></tr>
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<tr class="separator:ga172dc9a76f772c8e386ac0162e0a52fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5aded5247a4fa0834a311679c593fcd7" id="r_ga5aded5247a4fa0834a311679c593fcd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5aded5247a4fa0834a311679c593fcd7">GPIO_IDR_IDR_4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7454dab87916ca6076b287a21c2e4cd7">GPIO_IDR_ID4</a></td></tr>
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<tr class="separator:ga5aded5247a4fa0834a311679c593fcd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e7bf44f34ab51218a24b6b9467e9166" id="r_ga4e7bf44f34ab51218a24b6b9467e9166"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e7bf44f34ab51218a24b6b9467e9166">GPIO_IDR_IDR_5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cbfa2ff564030d912ce8f327850a3bf">GPIO_IDR_ID5</a></td></tr>
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<tr class="separator:ga4e7bf44f34ab51218a24b6b9467e9166"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6aa5a3c8353ab0ce15d6500baf902e8b" id="r_ga6aa5a3c8353ab0ce15d6500baf902e8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6aa5a3c8353ab0ce15d6500baf902e8b">GPIO_IDR_IDR_6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac933b9235cae5f9fccbd2fc41f9a2dc4">GPIO_IDR_ID6</a></td></tr>
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<tr class="memitem:gaeccc9232d1758570c7dd9d8733d9f5b6" id="r_gaeccc9232d1758570c7dd9d8733d9f5b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeccc9232d1758570c7dd9d8733d9f5b6">GPIO_IDR_IDR_7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga09ce75fcb48ac0db30f99ba312e8538a">GPIO_IDR_ID7</a></td></tr>
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<tr class="memitem:ga2b5f3c629daa6d4dd3ace095a127f9e1" id="r_ga2b5f3c629daa6d4dd3ace095a127f9e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b5f3c629daa6d4dd3ace095a127f9e1">GPIO_IDR_IDR_8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa193633720d142ceca6c6b27c4e87f02">GPIO_IDR_ID8</a></td></tr>
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<tr class="memitem:gacd452f85fa151363ffbf1d263185ef0d" id="r_gacd452f85fa151363ffbf1d263185ef0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd452f85fa151363ffbf1d263185ef0d">GPIO_IDR_IDR_9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga888325b6581f9ae181f3e4fe904b0c44">GPIO_IDR_ID9</a></td></tr>
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<tr class="separator:gacd452f85fa151363ffbf1d263185ef0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff38e1078878bdd79375295e7ab829b5" id="r_gaff38e1078878bdd79375295e7ab829b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff38e1078878bdd79375295e7ab829b5">GPIO_IDR_IDR_10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cd53d2742d0ace30b835bd0f44f5ebf">GPIO_IDR_ID10</a></td></tr>
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<tr class="memitem:ga84c3f48e386abf1f6d97e4fb86cbaa7c" id="r_ga84c3f48e386abf1f6d97e4fb86cbaa7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84c3f48e386abf1f6d97e4fb86cbaa7c">GPIO_IDR_IDR_11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gade5e087b267f95733cc4328522b7890d">GPIO_IDR_ID11</a></td></tr>
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<tr class="separator:ga84c3f48e386abf1f6d97e4fb86cbaa7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec151d78711f0274d3ab5b239884e645" id="r_gaec151d78711f0274d3ab5b239884e645"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec151d78711f0274d3ab5b239884e645">GPIO_IDR_IDR_12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga33564d1679db8201389f806595d000d9">GPIO_IDR_ID12</a></td></tr>
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<tr class="memitem:ga6771a14a3c52f397295737e509633b05" id="r_ga6771a14a3c52f397295737e509633b05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6771a14a3c52f397295737e509633b05">GPIO_IDR_IDR_13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga82e0ce0fca46443e3cbaf887a3a35713">GPIO_IDR_ID13</a></td></tr>
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<tr class="memitem:gae0b8882f4473b5d65266792ed631f0bb" id="r_gae0b8882f4473b5d65266792ed631f0bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0b8882f4473b5d65266792ed631f0bb">GPIO_IDR_IDR_14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac716fc8a3853431b69697ea5ee0aa8d2">GPIO_IDR_ID14</a></td></tr>
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<tr class="memitem:ga5fa9b2bca3451f0be4560333692fb5a4" id="r_ga5fa9b2bca3451f0be4560333692fb5a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fa9b2bca3451f0be4560333692fb5a4">GPIO_IDR_IDR_15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae72c80e97c41b8143cf299c078459ea4">GPIO_IDR_ID15</a></td></tr>
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<tr class="separator:ga5fa9b2bca3451f0be4560333692fb5a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade6bff88e55b2428269c90ebde121d31" id="r_gade6bff88e55b2428269c90ebde121d31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade6bff88e55b2428269c90ebde121d31">GPIO_ODR_OD0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga5c08637123e42a30fbf4e9e49feb650f" id="r_ga5c08637123e42a30fbf4e9e49feb650f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c08637123e42a30fbf4e9e49feb650f">GPIO_ODR_OD0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade6bff88e55b2428269c90ebde121d31">GPIO_ODR_OD0_Pos</a>)</td></tr>
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<tr class="separator:ga5c08637123e42a30fbf4e9e49feb650f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e7937b0a505e771361804a211c7656f" id="r_ga7e7937b0a505e771361804a211c7656f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e7937b0a505e771361804a211c7656f">GPIO_ODR_OD0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c08637123e42a30fbf4e9e49feb650f">GPIO_ODR_OD0_Msk</a></td></tr>
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<tr class="separator:ga7e7937b0a505e771361804a211c7656f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60dfdab58aa53c6790eb545f50f92722" id="r_ga60dfdab58aa53c6790eb545f50f92722"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60dfdab58aa53c6790eb545f50f92722">GPIO_ODR_OD1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga60dfdab58aa53c6790eb545f50f92722"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga284902fc92059f740dc599945071d767" id="r_ga284902fc92059f740dc599945071d767"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga284902fc92059f740dc599945071d767">GPIO_ODR_OD1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga60dfdab58aa53c6790eb545f50f92722">GPIO_ODR_OD1_Pos</a>)</td></tr>
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<tr class="separator:ga284902fc92059f740dc599945071d767"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga104dff849ee2c6a0b58777a336912583" id="r_ga104dff849ee2c6a0b58777a336912583"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga104dff849ee2c6a0b58777a336912583">GPIO_ODR_OD1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga284902fc92059f740dc599945071d767">GPIO_ODR_OD1_Msk</a></td></tr>
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<tr class="separator:ga104dff849ee2c6a0b58777a336912583"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ea388b190f9040a9657d9b395471596" id="r_ga9ea388b190f9040a9657d9b395471596"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ea388b190f9040a9657d9b395471596">GPIO_ODR_OD2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga9ea388b190f9040a9657d9b395471596"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b7c3794b7948875eea27a4b09bac063" id="r_ga7b7c3794b7948875eea27a4b09bac063"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b7c3794b7948875eea27a4b09bac063">GPIO_ODR_OD2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ea388b190f9040a9657d9b395471596">GPIO_ODR_OD2_Pos</a>)</td></tr>
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<tr class="separator:ga7b7c3794b7948875eea27a4b09bac063"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff3ff4b6fa52aac52991053b26d8dd80" id="r_gaff3ff4b6fa52aac52991053b26d8dd80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff3ff4b6fa52aac52991053b26d8dd80">GPIO_ODR_OD2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b7c3794b7948875eea27a4b09bac063">GPIO_ODR_OD2_Msk</a></td></tr>
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<tr class="separator:gaff3ff4b6fa52aac52991053b26d8dd80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a4ae35ae856330bc937251fd9ccf01c" id="r_ga3a4ae35ae856330bc937251fd9ccf01c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a4ae35ae856330bc937251fd9ccf01c">GPIO_ODR_OD3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga3a4ae35ae856330bc937251fd9ccf01c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b3312000af1016c233b04590b8c054c" id="r_ga6b3312000af1016c233b04590b8c054c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b3312000af1016c233b04590b8c054c">GPIO_ODR_OD3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a4ae35ae856330bc937251fd9ccf01c">GPIO_ODR_OD3_Pos</a>)</td></tr>
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<tr class="separator:ga6b3312000af1016c233b04590b8c054c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba5790d50582befba7f91037df94b159" id="r_gaba5790d50582befba7f91037df94b159"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba5790d50582befba7f91037df94b159">GPIO_ODR_OD3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b3312000af1016c233b04590b8c054c">GPIO_ODR_OD3_Msk</a></td></tr>
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<tr class="separator:gaba5790d50582befba7f91037df94b159"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91e0a70767add938306339ea3f3c8df5" id="r_ga91e0a70767add938306339ea3f3c8df5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91e0a70767add938306339ea3f3c8df5">GPIO_ODR_OD4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga91e0a70767add938306339ea3f3c8df5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab27b415dc46e3832b021eb0d697f1b13" id="r_gab27b415dc46e3832b021eb0d697f1b13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab27b415dc46e3832b021eb0d697f1b13">GPIO_ODR_OD4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga91e0a70767add938306339ea3f3c8df5">GPIO_ODR_OD4_Pos</a>)</td></tr>
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<tr class="separator:gab27b415dc46e3832b021eb0d697f1b13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd275e221a79cf7a3ac0c98ee15af3c5" id="r_gacd275e221a79cf7a3ac0c98ee15af3c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd275e221a79cf7a3ac0c98ee15af3c5">GPIO_ODR_OD4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab27b415dc46e3832b021eb0d697f1b13">GPIO_ODR_OD4_Msk</a></td></tr>
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<tr class="separator:gacd275e221a79cf7a3ac0c98ee15af3c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada7f2c3690272b52bde0c22223d39dff" id="r_gada7f2c3690272b52bde0c22223d39dff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada7f2c3690272b52bde0c22223d39dff">GPIO_ODR_OD5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gada7f2c3690272b52bde0c22223d39dff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga530c4cdcbeb559b2f990a237b4765631" id="r_ga530c4cdcbeb559b2f990a237b4765631"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga530c4cdcbeb559b2f990a237b4765631">GPIO_ODR_OD5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada7f2c3690272b52bde0c22223d39dff">GPIO_ODR_OD5_Pos</a>)</td></tr>
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<tr class="separator:ga530c4cdcbeb559b2f990a237b4765631"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4046ad484b858f3c49eb0449f45e3af5" id="r_ga4046ad484b858f3c49eb0449f45e3af5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4046ad484b858f3c49eb0449f45e3af5">GPIO_ODR_OD5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga530c4cdcbeb559b2f990a237b4765631">GPIO_ODR_OD5_Msk</a></td></tr>
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<tr class="separator:ga4046ad484b858f3c49eb0449f45e3af5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeaffa5b5eec9c90b552ebef5fc13828a" id="r_gaeaffa5b5eec9c90b552ebef5fc13828a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeaffa5b5eec9c90b552ebef5fc13828a">GPIO_ODR_OD6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaeaffa5b5eec9c90b552ebef5fc13828a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga965661d93777219b16fee1d210831622" id="r_ga965661d93777219b16fee1d210831622"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga965661d93777219b16fee1d210831622">GPIO_ODR_OD6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaffa5b5eec9c90b552ebef5fc13828a">GPIO_ODR_OD6_Pos</a>)</td></tr>
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<tr class="separator:ga965661d93777219b16fee1d210831622"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34550e0c5098cf24a2ab86e2ecc67c14" id="r_ga34550e0c5098cf24a2ab86e2ecc67c14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34550e0c5098cf24a2ab86e2ecc67c14">GPIO_ODR_OD6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga965661d93777219b16fee1d210831622">GPIO_ODR_OD6_Msk</a></td></tr>
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<tr class="separator:ga34550e0c5098cf24a2ab86e2ecc67c14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34bf70d7723a8e809a7ec2baba5583b1" id="r_ga34bf70d7723a8e809a7ec2baba5583b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34bf70d7723a8e809a7ec2baba5583b1">GPIO_ODR_OD7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga34bf70d7723a8e809a7ec2baba5583b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad697f4e743a67aad8ad37560a176ed25" id="r_gad697f4e743a67aad8ad37560a176ed25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad697f4e743a67aad8ad37560a176ed25">GPIO_ODR_OD7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34bf70d7723a8e809a7ec2baba5583b1">GPIO_ODR_OD7_Pos</a>)</td></tr>
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<tr class="memitem:gaba7559603648f95b76d128f0a637675c" id="r_gaba7559603648f95b76d128f0a637675c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba7559603648f95b76d128f0a637675c">GPIO_ODR_OD7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad697f4e743a67aad8ad37560a176ed25">GPIO_ODR_OD7_Msk</a></td></tr>
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<tr class="memitem:gad52cedd015ac8e511f7f2cdda0e6c4ca" id="r_gad52cedd015ac8e511f7f2cdda0e6c4ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad52cedd015ac8e511f7f2cdda0e6c4ca">GPIO_ODR_OD8_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gacad5442c3f20d25fdb0b24d78d1eab5b" id="r_gacad5442c3f20d25fdb0b24d78d1eab5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacad5442c3f20d25fdb0b24d78d1eab5b">GPIO_ODR_OD8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad52cedd015ac8e511f7f2cdda0e6c4ca">GPIO_ODR_OD8_Pos</a>)</td></tr>
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<tr class="memitem:ga60a61ea7de95ccdcb674e8b972969a1f" id="r_ga60a61ea7de95ccdcb674e8b972969a1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60a61ea7de95ccdcb674e8b972969a1f">GPIO_ODR_OD8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacad5442c3f20d25fdb0b24d78d1eab5b">GPIO_ODR_OD8_Msk</a></td></tr>
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<tr class="separator:ga60a61ea7de95ccdcb674e8b972969a1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41b713787d20ffacdc2c2b4f6fe05e4e" id="r_ga41b713787d20ffacdc2c2b4f6fe05e4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41b713787d20ffacdc2c2b4f6fe05e4e">GPIO_ODR_OD9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga41b713787d20ffacdc2c2b4f6fe05e4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga871215a04902f7abbc8e4753aa523d87" id="r_ga871215a04902f7abbc8e4753aa523d87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga871215a04902f7abbc8e4753aa523d87">GPIO_ODR_OD9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga41b713787d20ffacdc2c2b4f6fe05e4e">GPIO_ODR_OD9_Pos</a>)</td></tr>
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<tr class="memitem:gaa3bfdb1e3526890736b0c1238adda99c" id="r_gaa3bfdb1e3526890736b0c1238adda99c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3bfdb1e3526890736b0c1238adda99c">GPIO_ODR_OD9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga871215a04902f7abbc8e4753aa523d87">GPIO_ODR_OD9_Msk</a></td></tr>
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<tr class="separator:gaa3bfdb1e3526890736b0c1238adda99c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa47f67a9087ba57c2144a8a19d597bf5" id="r_gaa47f67a9087ba57c2144a8a19d597bf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa47f67a9087ba57c2144a8a19d597bf5">GPIO_ODR_OD10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaa47f67a9087ba57c2144a8a19d597bf5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5e3aca353a76254fd8d02debede2fae" id="r_gad5e3aca353a76254fd8d02debede2fae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5e3aca353a76254fd8d02debede2fae">GPIO_ODR_OD10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa47f67a9087ba57c2144a8a19d597bf5">GPIO_ODR_OD10_Pos</a>)</td></tr>
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<tr class="separator:gad5e3aca353a76254fd8d02debede2fae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5c6ba137db2753434a1253e111ff6a2" id="r_gac5c6ba137db2753434a1253e111ff6a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5c6ba137db2753434a1253e111ff6a2">GPIO_ODR_OD10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad5e3aca353a76254fd8d02debede2fae">GPIO_ODR_OD10_Msk</a></td></tr>
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<tr class="separator:gac5c6ba137db2753434a1253e111ff6a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4f6824376eb5f7f0185580a780d5ecf" id="r_gaf4f6824376eb5f7f0185580a780d5ecf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4f6824376eb5f7f0185580a780d5ecf">GPIO_ODR_OD11_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaf4f6824376eb5f7f0185580a780d5ecf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5432eff2238e4c6adf1f5c5cda9a797d" id="r_ga5432eff2238e4c6adf1f5c5cda9a797d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5432eff2238e4c6adf1f5c5cda9a797d">GPIO_ODR_OD11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4f6824376eb5f7f0185580a780d5ecf">GPIO_ODR_OD11_Pos</a>)</td></tr>
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<tr class="separator:ga5432eff2238e4c6adf1f5c5cda9a797d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e7e487eb914e276c92534eab7b1efdc" id="r_ga5e7e487eb914e276c92534eab7b1efdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e7e487eb914e276c92534eab7b1efdc">GPIO_ODR_OD11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5432eff2238e4c6adf1f5c5cda9a797d">GPIO_ODR_OD11_Msk</a></td></tr>
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<tr class="separator:ga5e7e487eb914e276c92534eab7b1efdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a3eca32e4b8eca5b984c371fc118c44" id="r_ga0a3eca32e4b8eca5b984c371fc118c44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a3eca32e4b8eca5b984c371fc118c44">GPIO_ODR_OD12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga0a3eca32e4b8eca5b984c371fc118c44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae85ad24a6fcfac506e330e0f896b1e23" id="r_gae85ad24a6fcfac506e330e0f896b1e23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae85ad24a6fcfac506e330e0f896b1e23">GPIO_ODR_OD12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a3eca32e4b8eca5b984c371fc118c44">GPIO_ODR_OD12_Pos</a>)</td></tr>
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<tr class="separator:gae85ad24a6fcfac506e330e0f896b1e23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac42a77f0ced79d51a5952d929a7e0528" id="r_gac42a77f0ced79d51a5952d929a7e0528"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac42a77f0ced79d51a5952d929a7e0528">GPIO_ODR_OD12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae85ad24a6fcfac506e330e0f896b1e23">GPIO_ODR_OD12_Msk</a></td></tr>
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<tr class="separator:gac42a77f0ced79d51a5952d929a7e0528"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29598cda6568737ee82992f76d07c45c" id="r_ga29598cda6568737ee82992f76d07c45c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29598cda6568737ee82992f76d07c45c">GPIO_ODR_OD13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga29598cda6568737ee82992f76d07c45c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93481785eb62b6669b8aceb1907b8e13" id="r_ga93481785eb62b6669b8aceb1907b8e13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93481785eb62b6669b8aceb1907b8e13">GPIO_ODR_OD13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga29598cda6568737ee82992f76d07c45c">GPIO_ODR_OD13_Pos</a>)</td></tr>
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<tr class="separator:ga93481785eb62b6669b8aceb1907b8e13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga582584ba2995b3b9993728b02a98f2c1" id="r_ga582584ba2995b3b9993728b02a98f2c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga582584ba2995b3b9993728b02a98f2c1">GPIO_ODR_OD13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga93481785eb62b6669b8aceb1907b8e13">GPIO_ODR_OD13_Msk</a></td></tr>
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<tr class="separator:ga582584ba2995b3b9993728b02a98f2c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd02d3bb351676e31027d8bad0c8eb70" id="r_gafd02d3bb351676e31027d8bad0c8eb70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd02d3bb351676e31027d8bad0c8eb70">GPIO_ODR_OD14_Pos</a>   (14U)</td></tr>
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<tr class="separator:gafd02d3bb351676e31027d8bad0c8eb70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf028b3836cb425dab56d38dd1df17062" id="r_gaf028b3836cb425dab56d38dd1df17062"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf028b3836cb425dab56d38dd1df17062">GPIO_ODR_OD14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafd02d3bb351676e31027d8bad0c8eb70">GPIO_ODR_OD14_Pos</a>)</td></tr>
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<tr class="memitem:ga6c2ec83ded91512630244d2d1e1c300b" id="r_ga6c2ec83ded91512630244d2d1e1c300b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c2ec83ded91512630244d2d1e1c300b">GPIO_ODR_OD14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf028b3836cb425dab56d38dd1df17062">GPIO_ODR_OD14_Msk</a></td></tr>
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<tr class="memitem:gaa3bac5a39dda0f70c8fb9de38450eb21" id="r_gaa3bac5a39dda0f70c8fb9de38450eb21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3bac5a39dda0f70c8fb9de38450eb21">GPIO_ODR_OD15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaa3bac5a39dda0f70c8fb9de38450eb21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26a07f39cf1e55d17f56df37cd875288" id="r_ga26a07f39cf1e55d17f56df37cd875288"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26a07f39cf1e55d17f56df37cd875288">GPIO_ODR_OD15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3bac5a39dda0f70c8fb9de38450eb21">GPIO_ODR_OD15_Pos</a>)</td></tr>
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<tr class="separator:ga26a07f39cf1e55d17f56df37cd875288"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e411f3d6f91e5218dc9ca1b6739f053" id="r_ga7e411f3d6f91e5218dc9ca1b6739f053"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e411f3d6f91e5218dc9ca1b6739f053">GPIO_ODR_OD15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga26a07f39cf1e55d17f56df37cd875288">GPIO_ODR_OD15_Msk</a></td></tr>
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<tr class="separator:ga7e411f3d6f91e5218dc9ca1b6739f053"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42386f40895bc86ff49eefe80708bbc6" id="r_ga42386f40895bc86ff49eefe80708bbc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42386f40895bc86ff49eefe80708bbc6">GPIO_ODR_ODR_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e7937b0a505e771361804a211c7656f">GPIO_ODR_OD0</a></td></tr>
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<tr class="memitem:ga7680b11616859cd0f462703224511fb2" id="r_ga7680b11616859cd0f462703224511fb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7680b11616859cd0f462703224511fb2">GPIO_ODR_ODR_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga104dff849ee2c6a0b58777a336912583">GPIO_ODR_OD1</a></td></tr>
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<tr class="memitem:gae93b86fd4c1bfcfafc42bf820c17c019" id="r_gae93b86fd4c1bfcfafc42bf820c17c019"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae93b86fd4c1bfcfafc42bf820c17c019">GPIO_ODR_ODR_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaff3ff4b6fa52aac52991053b26d8dd80">GPIO_ODR_OD2</a></td></tr>
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<tr class="memitem:ga3fffcd41fa6347ce4b61e6abbae55c7a" id="r_ga3fffcd41fa6347ce4b61e6abbae55c7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3fffcd41fa6347ce4b61e6abbae55c7a">GPIO_ODR_ODR_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba5790d50582befba7f91037df94b159">GPIO_ODR_OD3</a></td></tr>
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<tr class="memitem:gac9b5f55a1f9dda2285576a276d0fb0e2" id="r_gac9b5f55a1f9dda2285576a276d0fb0e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9b5f55a1f9dda2285576a276d0fb0e2">GPIO_ODR_ODR_4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacd275e221a79cf7a3ac0c98ee15af3c5">GPIO_ODR_OD4</a></td></tr>
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<tr class="memitem:ga6723e4adf0b6b333f74e15e00a60a4db" id="r_ga6723e4adf0b6b333f74e15e00a60a4db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6723e4adf0b6b333f74e15e00a60a4db">GPIO_ODR_ODR_5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4046ad484b858f3c49eb0449f45e3af5">GPIO_ODR_OD5</a></td></tr>
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<tr class="separator:ga6723e4adf0b6b333f74e15e00a60a4db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga202234d8f40086f6343e30597b52c838" id="r_ga202234d8f40086f6343e30597b52c838"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga202234d8f40086f6343e30597b52c838">GPIO_ODR_ODR_6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34550e0c5098cf24a2ab86e2ecc67c14">GPIO_ODR_OD6</a></td></tr>
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<tr class="memitem:ga3c713b846aa56d5a31b2e4525d705679" id="r_ga3c713b846aa56d5a31b2e4525d705679"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c713b846aa56d5a31b2e4525d705679">GPIO_ODR_ODR_7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba7559603648f95b76d128f0a637675c">GPIO_ODR_OD7</a></td></tr>
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<tr class="memitem:gaabe9c0b33000bbfe71f107cce0af0eb2" id="r_gaabe9c0b33000bbfe71f107cce0af0eb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabe9c0b33000bbfe71f107cce0af0eb2">GPIO_ODR_ODR_8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga60a61ea7de95ccdcb674e8b972969a1f">GPIO_ODR_OD8</a></td></tr>
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<tr class="memitem:ga25f53481a7575ebb0eb5477950673188" id="r_ga25f53481a7575ebb0eb5477950673188"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25f53481a7575ebb0eb5477950673188">GPIO_ODR_ODR_9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3bfdb1e3526890736b0c1238adda99c">GPIO_ODR_OD9</a></td></tr>
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<tr class="memitem:ga5e2817e62685ec81d3ca6674d8e75187" id="r_ga5e2817e62685ec81d3ca6674d8e75187"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e2817e62685ec81d3ca6674d8e75187">GPIO_ODR_ODR_10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac5c6ba137db2753434a1253e111ff6a2">GPIO_ODR_OD10</a></td></tr>
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<tr class="memitem:ga6022058342e528d097d2d352ccb3210c" id="r_ga6022058342e528d097d2d352ccb3210c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6022058342e528d097d2d352ccb3210c">GPIO_ODR_ODR_11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e7e487eb914e276c92534eab7b1efdc">GPIO_ODR_OD11</a></td></tr>
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<tr class="memitem:ga6df2c7bfa97e4536c3c112fa6dc00992" id="r_ga6df2c7bfa97e4536c3c112fa6dc00992"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6df2c7bfa97e4536c3c112fa6dc00992">GPIO_ODR_ODR_12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac42a77f0ced79d51a5952d929a7e0528">GPIO_ODR_OD12</a></td></tr>
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<tr class="memitem:gab7a51e706f1931e6ac3ddd117242da23" id="r_gab7a51e706f1931e6ac3ddd117242da23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7a51e706f1931e6ac3ddd117242da23">GPIO_ODR_ODR_13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga582584ba2995b3b9993728b02a98f2c1">GPIO_ODR_OD13</a></td></tr>
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<tr class="memitem:ga090cea405c38fd8c48f77e561deaaa07" id="r_ga090cea405c38fd8c48f77e561deaaa07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga090cea405c38fd8c48f77e561deaaa07">GPIO_ODR_ODR_14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c2ec83ded91512630244d2d1e1c300b">GPIO_ODR_OD14</a></td></tr>
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<tr class="memitem:ga527b7d78707f17edfe826be72aa59fdc" id="r_ga527b7d78707f17edfe826be72aa59fdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga527b7d78707f17edfe826be72aa59fdc">GPIO_ODR_ODR_15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e411f3d6f91e5218dc9ca1b6739f053">GPIO_ODR_OD15</a></td></tr>
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<tr class="memitem:ga409d8650af1aa0e1958cc1ed2f96acda" id="r_ga409d8650af1aa0e1958cc1ed2f96acda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga409d8650af1aa0e1958cc1ed2f96acda">GPIO_BSRR_BS0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga758aadb3c036759a162542216f98fcbc" id="r_ga758aadb3c036759a162542216f98fcbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga758aadb3c036759a162542216f98fcbc">GPIO_BSRR_BS0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga409d8650af1aa0e1958cc1ed2f96acda">GPIO_BSRR_BS0_Pos</a>)</td></tr>
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<tr class="memitem:ga4bdfbe2a618de42c420de923b2f8507d" id="r_ga4bdfbe2a618de42c420de923b2f8507d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bdfbe2a618de42c420de923b2f8507d">GPIO_BSRR_BS0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga758aadb3c036759a162542216f98fcbc">GPIO_BSRR_BS0_Msk</a></td></tr>
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<tr class="separator:ga4bdfbe2a618de42c420de923b2f8507d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7457f610b20ffdd73c97d90724ed4d4e" id="r_ga7457f610b20ffdd73c97d90724ed4d4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7457f610b20ffdd73c97d90724ed4d4e">GPIO_BSRR_BS1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga7457f610b20ffdd73c97d90724ed4d4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga875bc62855425da548fa2f68d3be0f49" id="r_ga875bc62855425da548fa2f68d3be0f49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga875bc62855425da548fa2f68d3be0f49">GPIO_BSRR_BS1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7457f610b20ffdd73c97d90724ed4d4e">GPIO_BSRR_BS1_Pos</a>)</td></tr>
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<tr class="separator:ga875bc62855425da548fa2f68d3be0f49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga316604d9223fee0c0591b58bd42b5f51" id="r_ga316604d9223fee0c0591b58bd42b5f51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga316604d9223fee0c0591b58bd42b5f51">GPIO_BSRR_BS1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga875bc62855425da548fa2f68d3be0f49">GPIO_BSRR_BS1_Msk</a></td></tr>
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<tr class="memitem:ga3af1acce0c96a515284b6f8bd12b8436" id="r_ga3af1acce0c96a515284b6f8bd12b8436"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3af1acce0c96a515284b6f8bd12b8436">GPIO_BSRR_BS2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga3af1acce0c96a515284b6f8bd12b8436"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0d718587115b4b07190c9ade21789ac" id="r_gaf0d718587115b4b07190c9ade21789ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0d718587115b4b07190c9ade21789ac">GPIO_BSRR_BS2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3af1acce0c96a515284b6f8bd12b8436">GPIO_BSRR_BS2_Pos</a>)</td></tr>
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<tr class="separator:gaf0d718587115b4b07190c9ade21789ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc89617a25217236b94eec1fd93891cb" id="r_gacc89617a25217236b94eec1fd93891cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc89617a25217236b94eec1fd93891cb">GPIO_BSRR_BS2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0d718587115b4b07190c9ade21789ac">GPIO_BSRR_BS2_Msk</a></td></tr>
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<tr class="memitem:gac0837604e1baac4b8b86fc3e660b17ad" id="r_gac0837604e1baac4b8b86fc3e660b17ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0837604e1baac4b8b86fc3e660b17ad">GPIO_BSRR_BS3_Pos</a>   (3U)</td></tr>
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<tr class="separator:gac0837604e1baac4b8b86fc3e660b17ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8d8114b4db83d01096d0337750d3099" id="r_gab8d8114b4db83d01096d0337750d3099"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8d8114b4db83d01096d0337750d3099">GPIO_BSRR_BS3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac0837604e1baac4b8b86fc3e660b17ad">GPIO_BSRR_BS3_Pos</a>)</td></tr>
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<tr class="separator:gab8d8114b4db83d01096d0337750d3099"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79e5ac9ace2d797ecfcc3d633c7ca52f" id="r_ga79e5ac9ace2d797ecfcc3d633c7ca52f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79e5ac9ace2d797ecfcc3d633c7ca52f">GPIO_BSRR_BS3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab8d8114b4db83d01096d0337750d3099">GPIO_BSRR_BS3_Msk</a></td></tr>
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<tr class="separator:ga79e5ac9ace2d797ecfcc3d633c7ca52f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae421b6676ce8b2865cbb6e15fc45d495" id="r_gae421b6676ce8b2865cbb6e15fc45d495"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae421b6676ce8b2865cbb6e15fc45d495">GPIO_BSRR_BS4_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae421b6676ce8b2865cbb6e15fc45d495"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0331d270ba3fe6bad1f3353ed09194bf" id="r_ga0331d270ba3fe6bad1f3353ed09194bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0331d270ba3fe6bad1f3353ed09194bf">GPIO_BSRR_BS4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae421b6676ce8b2865cbb6e15fc45d495">GPIO_BSRR_BS4_Pos</a>)</td></tr>
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<tr class="separator:ga0331d270ba3fe6bad1f3353ed09194bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga692f3966c5260fd55f3bb09829f69e75" id="r_ga692f3966c5260fd55f3bb09829f69e75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga692f3966c5260fd55f3bb09829f69e75">GPIO_BSRR_BS4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0331d270ba3fe6bad1f3353ed09194bf">GPIO_BSRR_BS4_Msk</a></td></tr>
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<tr class="separator:ga692f3966c5260fd55f3bb09829f69e75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad686100d76807920229b49d233cbd96d" id="r_gad686100d76807920229b49d233cbd96d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad686100d76807920229b49d233cbd96d">GPIO_BSRR_BS5_Pos</a>   (5U)</td></tr>
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<tr class="separator:gad686100d76807920229b49d233cbd96d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga502f44e296cddc2c4099ab7e7e9b11d8" id="r_ga502f44e296cddc2c4099ab7e7e9b11d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga502f44e296cddc2c4099ab7e7e9b11d8">GPIO_BSRR_BS5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad686100d76807920229b49d233cbd96d">GPIO_BSRR_BS5_Pos</a>)</td></tr>
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<tr class="separator:ga502f44e296cddc2c4099ab7e7e9b11d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ea824455e136eee60ec17f42dabab0b" id="r_ga5ea824455e136eee60ec17f42dabab0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ea824455e136eee60ec17f42dabab0b">GPIO_BSRR_BS5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga502f44e296cddc2c4099ab7e7e9b11d8">GPIO_BSRR_BS5_Msk</a></td></tr>
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<tr class="separator:ga5ea824455e136eee60ec17f42dabab0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91f4268de41bba2e411879d3fa900af7" id="r_ga91f4268de41bba2e411879d3fa900af7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91f4268de41bba2e411879d3fa900af7">GPIO_BSRR_BS6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga91f4268de41bba2e411879d3fa900af7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8d6a22635cfd41987e341af34b87a63" id="r_gab8d6a22635cfd41987e341af34b87a63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8d6a22635cfd41987e341af34b87a63">GPIO_BSRR_BS6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga91f4268de41bba2e411879d3fa900af7">GPIO_BSRR_BS6_Pos</a>)</td></tr>
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<tr class="separator:gab8d6a22635cfd41987e341af34b87a63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69b3333e39824fde00bc36b181de3929" id="r_ga69b3333e39824fde00bc36b181de3929"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69b3333e39824fde00bc36b181de3929">GPIO_BSRR_BS6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab8d6a22635cfd41987e341af34b87a63">GPIO_BSRR_BS6_Msk</a></td></tr>
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<tr class="separator:ga69b3333e39824fde00bc36b181de3929"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d1dd4ddac06be768bb7727bcb657081" id="r_ga6d1dd4ddac06be768bb7727bcb657081"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d1dd4ddac06be768bb7727bcb657081">GPIO_BSRR_BS7_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga6d1dd4ddac06be768bb7727bcb657081"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga635b08b445669748e8fadbcb0d2481e6" id="r_ga635b08b445669748e8fadbcb0d2481e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga635b08b445669748e8fadbcb0d2481e6">GPIO_BSRR_BS7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d1dd4ddac06be768bb7727bcb657081">GPIO_BSRR_BS7_Pos</a>)</td></tr>
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<tr class="separator:ga635b08b445669748e8fadbcb0d2481e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9836771d1c021b9b7350fd3c3d544b0" id="r_gaf9836771d1c021b9b7350fd3c3d544b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9836771d1c021b9b7350fd3c3d544b0">GPIO_BSRR_BS7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga635b08b445669748e8fadbcb0d2481e6">GPIO_BSRR_BS7_Msk</a></td></tr>
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<tr class="separator:gaf9836771d1c021b9b7350fd3c3d544b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga595b5fd07dcafd23fd6ed6e23cb43b5a" id="r_ga595b5fd07dcafd23fd6ed6e23cb43b5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga595b5fd07dcafd23fd6ed6e23cb43b5a">GPIO_BSRR_BS8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga595b5fd07dcafd23fd6ed6e23cb43b5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga765d016146d30e6112499598959a948a" id="r_ga765d016146d30e6112499598959a948a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga765d016146d30e6112499598959a948a">GPIO_BSRR_BS8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga595b5fd07dcafd23fd6ed6e23cb43b5a">GPIO_BSRR_BS8_Pos</a>)</td></tr>
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<tr class="separator:ga765d016146d30e6112499598959a948a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c295b6482aa91ef51198e570166f60f" id="r_ga2c295b6482aa91ef51198e570166f60f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c295b6482aa91ef51198e570166f60f">GPIO_BSRR_BS8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga765d016146d30e6112499598959a948a">GPIO_BSRR_BS8_Msk</a></td></tr>
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<tr class="separator:ga2c295b6482aa91ef51198e570166f60f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab415c303400428fa585419e57aa2513d" id="r_gab415c303400428fa585419e57aa2513d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab415c303400428fa585419e57aa2513d">GPIO_BSRR_BS9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gab415c303400428fa585419e57aa2513d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e1f12d75678bb5d295b8f77d5db15a0" id="r_ga5e1f12d75678bb5d295b8f77d5db15a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e1f12d75678bb5d295b8f77d5db15a0">GPIO_BSRR_BS9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab415c303400428fa585419e57aa2513d">GPIO_BSRR_BS9_Pos</a>)</td></tr>
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<tr class="separator:ga5e1f12d75678bb5d295b8f77d5db15a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49258fbb201ec8e332b248bbd0370b07" id="r_ga49258fbb201ec8e332b248bbd0370b07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49258fbb201ec8e332b248bbd0370b07">GPIO_BSRR_BS9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e1f12d75678bb5d295b8f77d5db15a0">GPIO_BSRR_BS9_Msk</a></td></tr>
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<tr class="separator:ga49258fbb201ec8e332b248bbd0370b07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf85195c9fb5642687151366b0f363441" id="r_gaf85195c9fb5642687151366b0f363441"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf85195c9fb5642687151366b0f363441">GPIO_BSRR_BS10_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaf85195c9fb5642687151366b0f363441"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a8f9979581623c5ee8a3b16be563cd1" id="r_ga2a8f9979581623c5ee8a3b16be563cd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a8f9979581623c5ee8a3b16be563cd1">GPIO_BSRR_BS10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf85195c9fb5642687151366b0f363441">GPIO_BSRR_BS10_Pos</a>)</td></tr>
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<tr class="separator:ga2a8f9979581623c5ee8a3b16be563cd1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbe42933da56edaa62f89d6fb5093b32" id="r_gadbe42933da56edaa62f89d6fb5093b32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbe42933da56edaa62f89d6fb5093b32">GPIO_BSRR_BS10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a8f9979581623c5ee8a3b16be563cd1">GPIO_BSRR_BS10_Msk</a></td></tr>
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<tr class="separator:gadbe42933da56edaa62f89d6fb5093b32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f79cf6b45de75813ed9d2af64f0d91b" id="r_ga7f79cf6b45de75813ed9d2af64f0d91b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f79cf6b45de75813ed9d2af64f0d91b">GPIO_BSRR_BS11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga7f79cf6b45de75813ed9d2af64f0d91b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d224601eb9ec2476451efe136693769" id="r_ga5d224601eb9ec2476451efe136693769"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d224601eb9ec2476451efe136693769">GPIO_BSRR_BS11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f79cf6b45de75813ed9d2af64f0d91b">GPIO_BSRR_BS11_Pos</a>)</td></tr>
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<tr class="separator:ga5d224601eb9ec2476451efe136693769"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71b06aba868da67827335c823cde772c" id="r_ga71b06aba868da67827335c823cde772c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71b06aba868da67827335c823cde772c">GPIO_BSRR_BS11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5d224601eb9ec2476451efe136693769">GPIO_BSRR_BS11_Msk</a></td></tr>
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<tr class="separator:ga71b06aba868da67827335c823cde772c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4302c8e25dd2711d37262b73865f3c19" id="r_ga4302c8e25dd2711d37262b73865f3c19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4302c8e25dd2711d37262b73865f3c19">GPIO_BSRR_BS12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga4302c8e25dd2711d37262b73865f3c19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cc01661d2dec2e9dd4b02528e271393" id="r_ga8cc01661d2dec2e9dd4b02528e271393"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cc01661d2dec2e9dd4b02528e271393">GPIO_BSRR_BS12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4302c8e25dd2711d37262b73865f3c19">GPIO_BSRR_BS12_Pos</a>)</td></tr>
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<tr class="separator:ga8cc01661d2dec2e9dd4b02528e271393"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34dec3bc91096fccb3339f2d6d181846" id="r_ga34dec3bc91096fccb3339f2d6d181846"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34dec3bc91096fccb3339f2d6d181846">GPIO_BSRR_BS12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8cc01661d2dec2e9dd4b02528e271393">GPIO_BSRR_BS12_Msk</a></td></tr>
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<tr class="separator:ga34dec3bc91096fccb3339f2d6d181846"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fe11d923932261f904c089da78e7ebc" id="r_ga5fe11d923932261f904c089da78e7ebc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe11d923932261f904c089da78e7ebc">GPIO_BSRR_BS13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga5fe11d923932261f904c089da78e7ebc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed57c94725261a35387ef04c9675cdbe" id="r_gaed57c94725261a35387ef04c9675cdbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed57c94725261a35387ef04c9675cdbe">GPIO_BSRR_BS13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe11d923932261f904c089da78e7ebc">GPIO_BSRR_BS13_Pos</a>)</td></tr>
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<tr class="separator:gaed57c94725261a35387ef04c9675cdbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ea853befe5a2a238f0e0fe5d6c41b9c" id="r_ga1ea853befe5a2a238f0e0fe5d6c41b9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ea853befe5a2a238f0e0fe5d6c41b9c">GPIO_BSRR_BS13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaed57c94725261a35387ef04c9675cdbe">GPIO_BSRR_BS13_Msk</a></td></tr>
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<tr class="separator:ga1ea853befe5a2a238f0e0fe5d6c41b9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c86de2a9b2e7394040a65bf114131bc" id="r_ga7c86de2a9b2e7394040a65bf114131bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c86de2a9b2e7394040a65bf114131bc">GPIO_BSRR_BS14_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga7c86de2a9b2e7394040a65bf114131bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeaaedec226989e8048f5cbde2de6c1c5" id="r_gaeaaedec226989e8048f5cbde2de6c1c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeaaedec226989e8048f5cbde2de6c1c5">GPIO_BSRR_BS14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c86de2a9b2e7394040a65bf114131bc">GPIO_BSRR_BS14_Pos</a>)</td></tr>
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<tr class="separator:gaeaaedec226989e8048f5cbde2de6c1c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24e32d8f8af43a171ed1a4c7eb202d17" id="r_ga24e32d8f8af43a171ed1a4c7eb202d17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24e32d8f8af43a171ed1a4c7eb202d17">GPIO_BSRR_BS14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaaedec226989e8048f5cbde2de6c1c5">GPIO_BSRR_BS14_Msk</a></td></tr>
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<tr class="separator:ga24e32d8f8af43a171ed1a4c7eb202d17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae93dccdbf7e8ef41da1b847975cf0eac" id="r_gae93dccdbf7e8ef41da1b847975cf0eac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae93dccdbf7e8ef41da1b847975cf0eac">GPIO_BSRR_BS15_Pos</a>   (15U)</td></tr>
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<tr class="separator:gae93dccdbf7e8ef41da1b847975cf0eac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab40b26153e5c50ae45ebc6deb06cc0fb" id="r_gab40b26153e5c50ae45ebc6deb06cc0fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab40b26153e5c50ae45ebc6deb06cc0fb">GPIO_BSRR_BS15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae93dccdbf7e8ef41da1b847975cf0eac">GPIO_BSRR_BS15_Pos</a>)</td></tr>
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<tr class="separator:gab40b26153e5c50ae45ebc6deb06cc0fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8427fb5c9074e51fbf27480a6a65a80" id="r_gad8427fb5c9074e51fbf27480a6a65a80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8427fb5c9074e51fbf27480a6a65a80">GPIO_BSRR_BS15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab40b26153e5c50ae45ebc6deb06cc0fb">GPIO_BSRR_BS15_Msk</a></td></tr>
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<tr class="separator:gad8427fb5c9074e51fbf27480a6a65a80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b9e4440bb44a4ab919e9a0171af788b" id="r_ga9b9e4440bb44a4ab919e9a0171af788b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b9e4440bb44a4ab919e9a0171af788b">GPIO_BSRR_BR0_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga9b9e4440bb44a4ab919e9a0171af788b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6ca69cbc7e23bf313dda10288ce21f5" id="r_gac6ca69cbc7e23bf313dda10288ce21f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6ca69cbc7e23bf313dda10288ce21f5">GPIO_BSRR_BR0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b9e4440bb44a4ab919e9a0171af788b">GPIO_BSRR_BR0_Pos</a>)</td></tr>
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<tr class="separator:gac6ca69cbc7e23bf313dda10288ce21f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44316fb208a551d63550ab435a65faaf" id="r_ga44316fb208a551d63550ab435a65faaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44316fb208a551d63550ab435a65faaf">GPIO_BSRR_BR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac6ca69cbc7e23bf313dda10288ce21f5">GPIO_BSRR_BR0_Msk</a></td></tr>
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<tr class="separator:ga44316fb208a551d63550ab435a65faaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga075d239db694cea8f30c70534ddf7be9" id="r_ga075d239db694cea8f30c70534ddf7be9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga075d239db694cea8f30c70534ddf7be9">GPIO_BSRR_BR1_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga075d239db694cea8f30c70534ddf7be9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9890be2a151b0b31119eba03b36b9df" id="r_gac9890be2a151b0b31119eba03b36b9df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9890be2a151b0b31119eba03b36b9df">GPIO_BSRR_BR1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga075d239db694cea8f30c70534ddf7be9">GPIO_BSRR_BR1_Pos</a>)</td></tr>
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<tr class="separator:gac9890be2a151b0b31119eba03b36b9df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga855ce6a1019d453bd1fbe9f61b5531b8" id="r_ga855ce6a1019d453bd1fbe9f61b5531b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga855ce6a1019d453bd1fbe9f61b5531b8">GPIO_BSRR_BR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9890be2a151b0b31119eba03b36b9df">GPIO_BSRR_BR1_Msk</a></td></tr>
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<tr class="separator:ga855ce6a1019d453bd1fbe9f61b5531b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c5825e38ef02071bf0d888ab636d241" id="r_ga2c5825e38ef02071bf0d888ab636d241"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c5825e38ef02071bf0d888ab636d241">GPIO_BSRR_BR2_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga2c5825e38ef02071bf0d888ab636d241"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca8d1db9b985749bcdcc4f83d80e25b1" id="r_gaca8d1db9b985749bcdcc4f83d80e25b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca8d1db9b985749bcdcc4f83d80e25b1">GPIO_BSRR_BR2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c5825e38ef02071bf0d888ab636d241">GPIO_BSRR_BR2_Pos</a>)</td></tr>
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<tr class="separator:gaca8d1db9b985749bcdcc4f83d80e25b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ac2103861a8ab0c8c8fed5e3bf7db0a" id="r_ga7ac2103861a8ab0c8c8fed5e3bf7db0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac2103861a8ab0c8c8fed5e3bf7db0a">GPIO_BSRR_BR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaca8d1db9b985749bcdcc4f83d80e25b1">GPIO_BSRR_BR2_Msk</a></td></tr>
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<tr class="separator:ga7ac2103861a8ab0c8c8fed5e3bf7db0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ef6b53609ca5d188a6916d8574d6030" id="r_ga1ef6b53609ca5d188a6916d8574d6030"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ef6b53609ca5d188a6916d8574d6030">GPIO_BSRR_BR3_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga1ef6b53609ca5d188a6916d8574d6030"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7045c8361aeed94f72ed591c604d1f1" id="r_gad7045c8361aeed94f72ed591c604d1f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7045c8361aeed94f72ed591c604d1f1">GPIO_BSRR_BR3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ef6b53609ca5d188a6916d8574d6030">GPIO_BSRR_BR3_Pos</a>)</td></tr>
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<tr class="separator:gad7045c8361aeed94f72ed591c604d1f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf256a26094e33026f7f575f04d0e05c9" id="r_gaf256a26094e33026f7f575f04d0e05c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf256a26094e33026f7f575f04d0e05c9">GPIO_BSRR_BR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad7045c8361aeed94f72ed591c604d1f1">GPIO_BSRR_BR3_Msk</a></td></tr>
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<tr class="separator:gaf256a26094e33026f7f575f04d0e05c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71bbd49dad3b3dcd6ecb60b0fb1fa8eb" id="r_ga71bbd49dad3b3dcd6ecb60b0fb1fa8eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71bbd49dad3b3dcd6ecb60b0fb1fa8eb">GPIO_BSRR_BR4_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga71bbd49dad3b3dcd6ecb60b0fb1fa8eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94341de3b04731a0df5c530c572dad7f" id="r_ga94341de3b04731a0df5c530c572dad7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94341de3b04731a0df5c530c572dad7f">GPIO_BSRR_BR4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71bbd49dad3b3dcd6ecb60b0fb1fa8eb">GPIO_BSRR_BR4_Pos</a>)</td></tr>
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<tr class="separator:ga94341de3b04731a0df5c530c572dad7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac84f66118397bb661ad9edfdd50432f0" id="r_gac84f66118397bb661ad9edfdd50432f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac84f66118397bb661ad9edfdd50432f0">GPIO_BSRR_BR4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga94341de3b04731a0df5c530c572dad7f">GPIO_BSRR_BR4_Msk</a></td></tr>
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<tr class="separator:gac84f66118397bb661ad9edfdd50432f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa565b7acd495e70be1b68204ef2910db" id="r_gaa565b7acd495e70be1b68204ef2910db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa565b7acd495e70be1b68204ef2910db">GPIO_BSRR_BR5_Pos</a>   (21U)</td></tr>
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<tr class="separator:gaa565b7acd495e70be1b68204ef2910db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d366ba8f09d9211e25c5e76b56a91af" id="r_ga4d366ba8f09d9211e25c5e76b56a91af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d366ba8f09d9211e25c5e76b56a91af">GPIO_BSRR_BR5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa565b7acd495e70be1b68204ef2910db">GPIO_BSRR_BR5_Pos</a>)</td></tr>
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<tr class="separator:ga4d366ba8f09d9211e25c5e76b56a91af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09a777f006ef68641e80110f20117a8d" id="r_ga09a777f006ef68641e80110f20117a8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09a777f006ef68641e80110f20117a8d">GPIO_BSRR_BR5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d366ba8f09d9211e25c5e76b56a91af">GPIO_BSRR_BR5_Msk</a></td></tr>
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<tr class="separator:ga09a777f006ef68641e80110f20117a8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafce8dd4c2ed3764a234fc40ad192ae03" id="r_gafce8dd4c2ed3764a234fc40ad192ae03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafce8dd4c2ed3764a234fc40ad192ae03">GPIO_BSRR_BR6_Pos</a>   (22U)</td></tr>
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<tr class="separator:gafce8dd4c2ed3764a234fc40ad192ae03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga354a942cded8f779316613b5a73b71ad" id="r_ga354a942cded8f779316613b5a73b71ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga354a942cded8f779316613b5a73b71ad">GPIO_BSRR_BR6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafce8dd4c2ed3764a234fc40ad192ae03">GPIO_BSRR_BR6_Pos</a>)</td></tr>
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<tr class="separator:ga354a942cded8f779316613b5a73b71ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8695c8bfcc32bda2806805339db1e8ce" id="r_ga8695c8bfcc32bda2806805339db1e8ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8695c8bfcc32bda2806805339db1e8ce">GPIO_BSRR_BR6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga354a942cded8f779316613b5a73b71ad">GPIO_BSRR_BR6_Msk</a></td></tr>
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<tr class="separator:ga8695c8bfcc32bda2806805339db1e8ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34e114c3d131dbb2abc05837b9c20fff" id="r_ga34e114c3d131dbb2abc05837b9c20fff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34e114c3d131dbb2abc05837b9c20fff">GPIO_BSRR_BR7_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga34e114c3d131dbb2abc05837b9c20fff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b90d1d54ad1a0def096663cfe9cbd74" id="r_ga6b90d1d54ad1a0def096663cfe9cbd74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b90d1d54ad1a0def096663cfe9cbd74">GPIO_BSRR_BR7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34e114c3d131dbb2abc05837b9c20fff">GPIO_BSRR_BR7_Pos</a>)</td></tr>
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<tr class="separator:ga6b90d1d54ad1a0def096663cfe9cbd74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba577e8f2650976f219ad7ad93244f8a" id="r_gaba577e8f2650976f219ad7ad93244f8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba577e8f2650976f219ad7ad93244f8a">GPIO_BSRR_BR7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b90d1d54ad1a0def096663cfe9cbd74">GPIO_BSRR_BR7_Msk</a></td></tr>
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<tr class="separator:gaba577e8f2650976f219ad7ad93244f8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadebc6e8a656a3adbff46f398b5bcb3d4" id="r_gadebc6e8a656a3adbff46f398b5bcb3d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadebc6e8a656a3adbff46f398b5bcb3d4">GPIO_BSRR_BR8_Pos</a>   (24U)</td></tr>
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<tr class="separator:gadebc6e8a656a3adbff46f398b5bcb3d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5460b708647c1a9f742c0ff0d5bcb17b" id="r_ga5460b708647c1a9f742c0ff0d5bcb17b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5460b708647c1a9f742c0ff0d5bcb17b">GPIO_BSRR_BR8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadebc6e8a656a3adbff46f398b5bcb3d4">GPIO_BSRR_BR8_Pos</a>)</td></tr>
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<tr class="separator:ga5460b708647c1a9f742c0ff0d5bcb17b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaedbc146cc7659d51bc5f472d3a405ee" id="r_gaaedbc146cc7659d51bc5f472d3a405ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaedbc146cc7659d51bc5f472d3a405ee">GPIO_BSRR_BR8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5460b708647c1a9f742c0ff0d5bcb17b">GPIO_BSRR_BR8_Msk</a></td></tr>
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<tr class="separator:gaaedbc146cc7659d51bc5f472d3a405ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13d98b977fc86581e566299bd363176d" id="r_ga13d98b977fc86581e566299bd363176d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13d98b977fc86581e566299bd363176d">GPIO_BSRR_BR9_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga13d98b977fc86581e566299bd363176d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4aa6d3943ec6a8d96dd855f436ab8e19" id="r_ga4aa6d3943ec6a8d96dd855f436ab8e19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4aa6d3943ec6a8d96dd855f436ab8e19">GPIO_BSRR_BR9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga13d98b977fc86581e566299bd363176d">GPIO_BSRR_BR9_Pos</a>)</td></tr>
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<tr class="separator:ga4aa6d3943ec6a8d96dd855f436ab8e19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3e0c779115c59cb98e021ede5605df3" id="r_gaa3e0c779115c59cb98e021ede5605df3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3e0c779115c59cb98e021ede5605df3">GPIO_BSRR_BR9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4aa6d3943ec6a8d96dd855f436ab8e19">GPIO_BSRR_BR9_Msk</a></td></tr>
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<tr class="separator:gaa3e0c779115c59cb98e021ede5605df3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga968f494c3928ba28bfa7c87da5f2cbaa" id="r_ga968f494c3928ba28bfa7c87da5f2cbaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga968f494c3928ba28bfa7c87da5f2cbaa">GPIO_BSRR_BR10_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga968f494c3928ba28bfa7c87da5f2cbaa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3f93f6e94ae0d842e5b0cda9ba6a1cd" id="r_gae3f93f6e94ae0d842e5b0cda9ba6a1cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3f93f6e94ae0d842e5b0cda9ba6a1cd">GPIO_BSRR_BR10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga968f494c3928ba28bfa7c87da5f2cbaa">GPIO_BSRR_BR10_Pos</a>)</td></tr>
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<tr class="separator:gae3f93f6e94ae0d842e5b0cda9ba6a1cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98581ac23be9f4fa003686d2ea523a81" id="r_ga98581ac23be9f4fa003686d2ea523a81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98581ac23be9f4fa003686d2ea523a81">GPIO_BSRR_BR10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3f93f6e94ae0d842e5b0cda9ba6a1cd">GPIO_BSRR_BR10_Msk</a></td></tr>
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<tr class="separator:ga98581ac23be9f4fa003686d2ea523a81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b421b338b145649e8937806472a59c6" id="r_ga8b421b338b145649e8937806472a59c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b421b338b145649e8937806472a59c6">GPIO_BSRR_BR11_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga8b421b338b145649e8937806472a59c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f483f67fbc5614c010aa147e9ce6b3f" id="r_ga9f483f67fbc5614c010aa147e9ce6b3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f483f67fbc5614c010aa147e9ce6b3f">GPIO_BSRR_BR11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b421b338b145649e8937806472a59c6">GPIO_BSRR_BR11_Pos</a>)</td></tr>
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<tr class="separator:ga9f483f67fbc5614c010aa147e9ce6b3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacedacd6c3e840a8172269cac3dbb550b" id="r_gacedacd6c3e840a8172269cac3dbb550b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacedacd6c3e840a8172269cac3dbb550b">GPIO_BSRR_BR11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f483f67fbc5614c010aa147e9ce6b3f">GPIO_BSRR_BR11_Msk</a></td></tr>
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<tr class="separator:gacedacd6c3e840a8172269cac3dbb550b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79f141572b1c065dcabbc7ddfe4092f2" id="r_ga79f141572b1c065dcabbc7ddfe4092f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79f141572b1c065dcabbc7ddfe4092f2">GPIO_BSRR_BR12_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga79f141572b1c065dcabbc7ddfe4092f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa10f5ee9aeb2eefb25fd195e472c0de8" id="r_gaa10f5ee9aeb2eefb25fd195e472c0de8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa10f5ee9aeb2eefb25fd195e472c0de8">GPIO_BSRR_BR12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga79f141572b1c065dcabbc7ddfe4092f2">GPIO_BSRR_BR12_Pos</a>)</td></tr>
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<tr class="separator:gaa10f5ee9aeb2eefb25fd195e472c0de8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4622e78de418b59cd4199928801b6958" id="r_ga4622e78de418b59cd4199928801b6958"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4622e78de418b59cd4199928801b6958">GPIO_BSRR_BR12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa10f5ee9aeb2eefb25fd195e472c0de8">GPIO_BSRR_BR12_Msk</a></td></tr>
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<tr class="separator:ga4622e78de418b59cd4199928801b6958"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53a07a77a4bb0457b13abfee48ed3e39" id="r_ga53a07a77a4bb0457b13abfee48ed3e39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53a07a77a4bb0457b13abfee48ed3e39">GPIO_BSRR_BR13_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga53a07a77a4bb0457b13abfee48ed3e39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d000805bb6f4ad68ec73159df771422" id="r_ga7d000805bb6f4ad68ec73159df771422"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d000805bb6f4ad68ec73159df771422">GPIO_BSRR_BR13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga53a07a77a4bb0457b13abfee48ed3e39">GPIO_BSRR_BR13_Pos</a>)</td></tr>
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<tr class="separator:ga7d000805bb6f4ad68ec73159df771422"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga292c1d0172620e0454ccc36f91f0c6ea" id="r_ga292c1d0172620e0454ccc36f91f0c6ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga292c1d0172620e0454ccc36f91f0c6ea">GPIO_BSRR_BR13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d000805bb6f4ad68ec73159df771422">GPIO_BSRR_BR13_Msk</a></td></tr>
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<tr class="separator:ga292c1d0172620e0454ccc36f91f0c6ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e6b3f0c1a866cd39319f28cacbb768e" id="r_ga1e6b3f0c1a866cd39319f28cacbb768e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e6b3f0c1a866cd39319f28cacbb768e">GPIO_BSRR_BR14_Pos</a>   (30U)</td></tr>
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<tr class="memitem:ga1ad1816ec382b6ef6e952cef1408933f" id="r_ga1ad1816ec382b6ef6e952cef1408933f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ad1816ec382b6ef6e952cef1408933f">GPIO_BSRR_BR14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e6b3f0c1a866cd39319f28cacbb768e">GPIO_BSRR_BR14_Pos</a>)</td></tr>
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<tr class="memitem:ga32477ac5ab4f5c7257ca332bb691b7cf" id="r_ga32477ac5ab4f5c7257ca332bb691b7cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32477ac5ab4f5c7257ca332bb691b7cf">GPIO_BSRR_BR14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ad1816ec382b6ef6e952cef1408933f">GPIO_BSRR_BR14_Msk</a></td></tr>
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<tr class="memitem:ga30d885f9a72889c6f1070b6da4d4d782" id="r_ga30d885f9a72889c6f1070b6da4d4d782"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30d885f9a72889c6f1070b6da4d4d782">GPIO_BSRR_BR15_Pos</a>   (31U)</td></tr>
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<tr class="memitem:gaf8c00dff452eea9a285e36a81c5abd79" id="r_gaf8c00dff452eea9a285e36a81c5abd79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8c00dff452eea9a285e36a81c5abd79">GPIO_BSRR_BR15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30d885f9a72889c6f1070b6da4d4d782">GPIO_BSRR_BR15_Pos</a>)</td></tr>
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<tr class="memitem:ga3c6d612adeaae9b26d0ea4af74ffe1cd" id="r_ga3c6d612adeaae9b26d0ea4af74ffe1cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c6d612adeaae9b26d0ea4af74ffe1cd">GPIO_BSRR_BR15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8c00dff452eea9a285e36a81c5abd79">GPIO_BSRR_BR15_Msk</a></td></tr>
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<tr class="memitem:ga4b69748fd2f5e2890e784bc0970b31d5" id="r_ga4b69748fd2f5e2890e784bc0970b31d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b69748fd2f5e2890e784bc0970b31d5">GPIO_BSRR_BS_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bdfbe2a618de42c420de923b2f8507d">GPIO_BSRR_BS0</a></td></tr>
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<tr class="memitem:gaa887cd170c757a2954ae8384908d030a" id="r_gaa887cd170c757a2954ae8384908d030a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa887cd170c757a2954ae8384908d030a">GPIO_BSRR_BS_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga316604d9223fee0c0591b58bd42b5f51">GPIO_BSRR_BS1</a></td></tr>
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<tr class="memitem:gaa59c6fcfc63587ebe3cbf640cc74776a" id="r_gaa59c6fcfc63587ebe3cbf640cc74776a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa59c6fcfc63587ebe3cbf640cc74776a">GPIO_BSRR_BS_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacc89617a25217236b94eec1fd93891cb">GPIO_BSRR_BS2</a></td></tr>
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<tr class="memitem:gac41aaeaf32b8837f8f6e29e09ed92152" id="r_gac41aaeaf32b8837f8f6e29e09ed92152"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac41aaeaf32b8837f8f6e29e09ed92152">GPIO_BSRR_BS_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga79e5ac9ace2d797ecfcc3d633c7ca52f">GPIO_BSRR_BS3</a></td></tr>
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<tr class="memitem:ga002773af2697ddca1bac26831cfbf231" id="r_ga002773af2697ddca1bac26831cfbf231"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga002773af2697ddca1bac26831cfbf231">GPIO_BSRR_BS_4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga692f3966c5260fd55f3bb09829f69e75">GPIO_BSRR_BS4</a></td></tr>
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<tr class="memitem:gaf9f2671eae81f28d0054b62ca5e2f763" id="r_gaf9f2671eae81f28d0054b62ca5e2f763"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9f2671eae81f28d0054b62ca5e2f763">GPIO_BSRR_BS_5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ea824455e136eee60ec17f42dabab0b">GPIO_BSRR_BS5</a></td></tr>
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<tr class="memitem:ga5dab92d27518649b3807aa4c8ef376b6" id="r_ga5dab92d27518649b3807aa4c8ef376b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5dab92d27518649b3807aa4c8ef376b6">GPIO_BSRR_BS_6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga69b3333e39824fde00bc36b181de3929">GPIO_BSRR_BS6</a></td></tr>
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<tr class="memitem:gaac4945b022950bdb9570e744279a0dd6" id="r_gaac4945b022950bdb9570e744279a0dd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac4945b022950bdb9570e744279a0dd6">GPIO_BSRR_BS_7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9836771d1c021b9b7350fd3c3d544b0">GPIO_BSRR_BS7</a></td></tr>
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<tr class="memitem:ga648026b2f11d992bb0e3383644be4eb9" id="r_ga648026b2f11d992bb0e3383644be4eb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga648026b2f11d992bb0e3383644be4eb9">GPIO_BSRR_BS_8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c295b6482aa91ef51198e570166f60f">GPIO_BSRR_BS8</a></td></tr>
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<tr class="memitem:ga9db2ccea6361f65c6bf156aa57cd4b88" id="r_ga9db2ccea6361f65c6bf156aa57cd4b88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9db2ccea6361f65c6bf156aa57cd4b88">GPIO_BSRR_BS_9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga49258fbb201ec8e332b248bbd0370b07">GPIO_BSRR_BS9</a></td></tr>
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<tr class="separator:ga9db2ccea6361f65c6bf156aa57cd4b88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa58e335b962fc81af70d19dbd09d9137" id="r_gaa58e335b962fc81af70d19dbd09d9137"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa58e335b962fc81af70d19dbd09d9137">GPIO_BSRR_BS_10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadbe42933da56edaa62f89d6fb5093b32">GPIO_BSRR_BS10</a></td></tr>
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<tr class="separator:gaa58e335b962fc81af70d19dbd09d9137"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5744153a68c73330e2ebe9a9a0ef8036" id="r_ga5744153a68c73330e2ebe9a9a0ef8036"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5744153a68c73330e2ebe9a9a0ef8036">GPIO_BSRR_BS_11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71b06aba868da67827335c823cde772c">GPIO_BSRR_BS11</a></td></tr>
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<tr class="separator:ga5744153a68c73330e2ebe9a9a0ef8036"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78652a72a05249db1d343735d1764208" id="r_ga78652a72a05249db1d343735d1764208"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78652a72a05249db1d343735d1764208">GPIO_BSRR_BS_12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34dec3bc91096fccb3339f2d6d181846">GPIO_BSRR_BS12</a></td></tr>
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<tr class="separator:ga78652a72a05249db1d343735d1764208"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6367e64393bc954efa6fdce80e94f1be" id="r_ga6367e64393bc954efa6fdce80e94f1be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6367e64393bc954efa6fdce80e94f1be">GPIO_BSRR_BS_13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ea853befe5a2a238f0e0fe5d6c41b9c">GPIO_BSRR_BS13</a></td></tr>
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<tr class="separator:ga6367e64393bc954efa6fdce80e94f1be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8c5c56ab4bc16dd7341203c73899e41" id="r_gaa8c5c56ab4bc16dd7341203c73899e41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8c5c56ab4bc16dd7341203c73899e41">GPIO_BSRR_BS_14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga24e32d8f8af43a171ed1a4c7eb202d17">GPIO_BSRR_BS14</a></td></tr>
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<tr class="separator:gaa8c5c56ab4bc16dd7341203c73899e41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66c0c77c304415bdccf47a0f08b58e4d" id="r_ga66c0c77c304415bdccf47a0f08b58e4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66c0c77c304415bdccf47a0f08b58e4d">GPIO_BSRR_BS_15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad8427fb5c9074e51fbf27480a6a65a80">GPIO_BSRR_BS15</a></td></tr>
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<tr class="separator:ga66c0c77c304415bdccf47a0f08b58e4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga831554de814ae2941c7f527ed6b0a742" id="r_ga831554de814ae2941c7f527ed6b0a742"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga831554de814ae2941c7f527ed6b0a742">GPIO_BSRR_BR_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44316fb208a551d63550ab435a65faaf">GPIO_BSRR_BR0</a></td></tr>
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<tr class="separator:ga831554de814ae2941c7f527ed6b0a742"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cf488fcb38fc660f7e3d1820a12ae07" id="r_ga6cf488fcb38fc660f7e3d1820a12ae07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cf488fcb38fc660f7e3d1820a12ae07">GPIO_BSRR_BR_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga855ce6a1019d453bd1fbe9f61b5531b8">GPIO_BSRR_BR1</a></td></tr>
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<tr class="separator:ga6cf488fcb38fc660f7e3d1820a12ae07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7fe0f9386b50b899fdf1f9008c54f893" id="r_ga7fe0f9386b50b899fdf1f9008c54f893"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fe0f9386b50b899fdf1f9008c54f893">GPIO_BSRR_BR_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac2103861a8ab0c8c8fed5e3bf7db0a">GPIO_BSRR_BR2</a></td></tr>
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<tr class="separator:ga7fe0f9386b50b899fdf1f9008c54f893"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42b377f0c5f564fb39480afe43ee8796" id="r_ga42b377f0c5f564fb39480afe43ee8796"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42b377f0c5f564fb39480afe43ee8796">GPIO_BSRR_BR_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf256a26094e33026f7f575f04d0e05c9">GPIO_BSRR_BR3</a></td></tr>
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<tr class="separator:ga42b377f0c5f564fb39480afe43ee8796"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab723c0327da5fb41fe366416b7d61d88" id="r_gab723c0327da5fb41fe366416b7d61d88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab723c0327da5fb41fe366416b7d61d88">GPIO_BSRR_BR_4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac84f66118397bb661ad9edfdd50432f0">GPIO_BSRR_BR4</a></td></tr>
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<tr class="separator:gab723c0327da5fb41fe366416b7d61d88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d6d8644953029e183eda4404fe9bd27" id="r_ga0d6d8644953029e183eda4404fe9bd27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d6d8644953029e183eda4404fe9bd27">GPIO_BSRR_BR_5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga09a777f006ef68641e80110f20117a8d">GPIO_BSRR_BR5</a></td></tr>
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<tr class="separator:ga0d6d8644953029e183eda4404fe9bd27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59e4a03667e8a750fd2e775edc44ecbe" id="r_ga59e4a03667e8a750fd2e775edc44ecbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59e4a03667e8a750fd2e775edc44ecbe">GPIO_BSRR_BR_6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8695c8bfcc32bda2806805339db1e8ce">GPIO_BSRR_BR6</a></td></tr>
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<tr class="separator:ga59e4a03667e8a750fd2e775edc44ecbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafca85d377fe820e5099d870342d634a8" id="r_gafca85d377fe820e5099d870342d634a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafca85d377fe820e5099d870342d634a8">GPIO_BSRR_BR_7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba577e8f2650976f219ad7ad93244f8a">GPIO_BSRR_BR7</a></td></tr>
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<tr class="memitem:gab02c6e6e879085fd8912facf86d822cd" id="r_gab02c6e6e879085fd8912facf86d822cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab02c6e6e879085fd8912facf86d822cd">GPIO_BSRR_BR_8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaedbc146cc7659d51bc5f472d3a405ee">GPIO_BSRR_BR8</a></td></tr>
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<tr class="separator:gab02c6e6e879085fd8912facf86d822cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47ff03b3d52a7f40ae15cc167b34cc58" id="r_ga47ff03b3d52a7f40ae15cc167b34cc58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47ff03b3d52a7f40ae15cc167b34cc58">GPIO_BSRR_BR_9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3e0c779115c59cb98e021ede5605df3">GPIO_BSRR_BR9</a></td></tr>
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<tr class="memitem:ga7c14a1c84cc91ff1d21b6802cda7d7ef" id="r_ga7c14a1c84cc91ff1d21b6802cda7d7ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c14a1c84cc91ff1d21b6802cda7d7ef">GPIO_BSRR_BR_10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga98581ac23be9f4fa003686d2ea523a81">GPIO_BSRR_BR10</a></td></tr>
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<tr class="memitem:ga498185a76dcc2305113c5d168c2844d9" id="r_ga498185a76dcc2305113c5d168c2844d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga498185a76dcc2305113c5d168c2844d9">GPIO_BSRR_BR_11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacedacd6c3e840a8172269cac3dbb550b">GPIO_BSRR_BR11</a></td></tr>
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<tr class="memitem:ga222460b26eaba7d333bb4d4ae9426aff" id="r_ga222460b26eaba7d333bb4d4ae9426aff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga222460b26eaba7d333bb4d4ae9426aff">GPIO_BSRR_BR_12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4622e78de418b59cd4199928801b6958">GPIO_BSRR_BR12</a></td></tr>
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<tr class="memitem:gaca2dc3bd09745f8de6c6788fb1d106af" id="r_gaca2dc3bd09745f8de6c6788fb1d106af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca2dc3bd09745f8de6c6788fb1d106af">GPIO_BSRR_BR_13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga292c1d0172620e0454ccc36f91f0c6ea">GPIO_BSRR_BR13</a></td></tr>
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<tr class="memitem:ga67c96f72bdd15516e22097a3a3dad5f1" id="r_ga67c96f72bdd15516e22097a3a3dad5f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67c96f72bdd15516e22097a3a3dad5f1">GPIO_BSRR_BR_14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga32477ac5ab4f5c7257ca332bb691b7cf">GPIO_BSRR_BR14</a></td></tr>
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<tr class="memitem:ga6eaa59f6afa3fcebaf2a27c31ae38544" id="r_ga6eaa59f6afa3fcebaf2a27c31ae38544"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6eaa59f6afa3fcebaf2a27c31ae38544">GPIO_BSRR_BR_15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c6d612adeaae9b26d0ea4af74ffe1cd">GPIO_BSRR_BR15</a></td></tr>
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<tr class="separator:ga6eaa59f6afa3fcebaf2a27c31ae38544"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8acd11feb4223a7ca438effb3d926fc" id="r_gad8acd11feb4223a7ca438effb3d926fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8acd11feb4223a7ca438effb3d926fc">GPIO_BRR_BR0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44316fb208a551d63550ab435a65faaf">GPIO_BSRR_BR0</a></td></tr>
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<tr class="memitem:gaa4adfe8c79c3cf7e0fb7e8714ae15adf" id="r_gaa4adfe8c79c3cf7e0fb7e8714ae15adf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4adfe8c79c3cf7e0fb7e8714ae15adf">GPIO_BRR_BR0_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b9e4440bb44a4ab919e9a0171af788b">GPIO_BSRR_BR0_Pos</a></td></tr>
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<tr class="memitem:gab8094099cbec15df24976405da11376f" id="r_gab8094099cbec15df24976405da11376f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8094099cbec15df24976405da11376f">GPIO_BRR_BR0_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac6ca69cbc7e23bf313dda10288ce21f5">GPIO_BSRR_BR0_Msk</a></td></tr>
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<tr class="memitem:ga68f94e96c502467ad528983494cb6645" id="r_ga68f94e96c502467ad528983494cb6645"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68f94e96c502467ad528983494cb6645">GPIO_BRR_BR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga855ce6a1019d453bd1fbe9f61b5531b8">GPIO_BSRR_BR1</a></td></tr>
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<tr class="memitem:ga483e475a913145601000fc57ef63afcd" id="r_ga483e475a913145601000fc57ef63afcd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga483e475a913145601000fc57ef63afcd">GPIO_BRR_BR1_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga075d239db694cea8f30c70534ddf7be9">GPIO_BSRR_BR1_Pos</a></td></tr>
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<tr class="memitem:gad742debac1d7e18afd61fda41eda1454" id="r_gad742debac1d7e18afd61fda41eda1454"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad742debac1d7e18afd61fda41eda1454">GPIO_BRR_BR1_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9890be2a151b0b31119eba03b36b9df">GPIO_BSRR_BR1_Msk</a></td></tr>
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<tr class="separator:gad742debac1d7e18afd61fda41eda1454"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeebe4dddede0f14e00885b70c09bbd09" id="r_gaeebe4dddede0f14e00885b70c09bbd09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeebe4dddede0f14e00885b70c09bbd09">GPIO_BRR_BR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac2103861a8ab0c8c8fed5e3bf7db0a">GPIO_BSRR_BR2</a></td></tr>
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<tr class="separator:gaeebe4dddede0f14e00885b70c09bbd09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb13164bb973d1a4591ca626903e66b7" id="r_gadb13164bb973d1a4591ca626903e66b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb13164bb973d1a4591ca626903e66b7">GPIO_BRR_BR2_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c5825e38ef02071bf0d888ab636d241">GPIO_BSRR_BR2_Pos</a></td></tr>
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<tr class="memitem:ga91d9b343fe4038316557b5665ad90895" id="r_ga91d9b343fe4038316557b5665ad90895"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91d9b343fe4038316557b5665ad90895">GPIO_BRR_BR2_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaca8d1db9b985749bcdcc4f83d80e25b1">GPIO_BSRR_BR2_Msk</a></td></tr>
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<tr class="memitem:ga95b3047fcdfe9269f5a94b6412ec6a3c" id="r_ga95b3047fcdfe9269f5a94b6412ec6a3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95b3047fcdfe9269f5a94b6412ec6a3c">GPIO_BRR_BR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf256a26094e33026f7f575f04d0e05c9">GPIO_BSRR_BR3</a></td></tr>
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<tr class="memitem:gac814288cc968b01d3e7ee1b6d340a8dd" id="r_gac814288cc968b01d3e7ee1b6d340a8dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac814288cc968b01d3e7ee1b6d340a8dd">GPIO_BRR_BR3_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ef6b53609ca5d188a6916d8574d6030">GPIO_BSRR_BR3_Pos</a></td></tr>
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<tr class="separator:gac814288cc968b01d3e7ee1b6d340a8dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59b86cdd805087a6aa27886a1c8f3f64" id="r_ga59b86cdd805087a6aa27886a1c8f3f64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59b86cdd805087a6aa27886a1c8f3f64">GPIO_BRR_BR3_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad7045c8361aeed94f72ed591c604d1f1">GPIO_BSRR_BR3_Msk</a></td></tr>
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<tr class="separator:ga59b86cdd805087a6aa27886a1c8f3f64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fc7d79f0103f892f8c3a87d8038525a" id="r_ga8fc7d79f0103f892f8c3a87d8038525a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fc7d79f0103f892f8c3a87d8038525a">GPIO_BRR_BR4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac84f66118397bb661ad9edfdd50432f0">GPIO_BSRR_BR4</a></td></tr>
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<tr class="separator:ga8fc7d79f0103f892f8c3a87d8038525a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9f7fabe9e3187ac070c2ed6e4ae7725" id="r_gac9f7fabe9e3187ac070c2ed6e4ae7725"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9f7fabe9e3187ac070c2ed6e4ae7725">GPIO_BRR_BR4_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71bbd49dad3b3dcd6ecb60b0fb1fa8eb">GPIO_BSRR_BR4_Pos</a></td></tr>
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<tr class="separator:gac9f7fabe9e3187ac070c2ed6e4ae7725"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84709afb9f2b311db9916987f5b62803" id="r_ga84709afb9f2b311db9916987f5b62803"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84709afb9f2b311db9916987f5b62803">GPIO_BRR_BR4_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga94341de3b04731a0df5c530c572dad7f">GPIO_BSRR_BR4_Msk</a></td></tr>
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<tr class="separator:ga84709afb9f2b311db9916987f5b62803"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cc7663eaa1496185041af93b4ff808b" id="r_ga6cc7663eaa1496185041af93b4ff808b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cc7663eaa1496185041af93b4ff808b">GPIO_BRR_BR5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga09a777f006ef68641e80110f20117a8d">GPIO_BSRR_BR5</a></td></tr>
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<tr class="separator:ga6cc7663eaa1496185041af93b4ff808b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b24f01f67db366ff6adf86f5f940669" id="r_ga6b24f01f67db366ff6adf86f5f940669"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b24f01f67db366ff6adf86f5f940669">GPIO_BRR_BR5_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa565b7acd495e70be1b68204ef2910db">GPIO_BSRR_BR5_Pos</a></td></tr>
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<tr class="separator:ga6b24f01f67db366ff6adf86f5f940669"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50fd21ca329283e8f79675f8195d6a7e" id="r_ga50fd21ca329283e8f79675f8195d6a7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50fd21ca329283e8f79675f8195d6a7e">GPIO_BRR_BR5_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d366ba8f09d9211e25c5e76b56a91af">GPIO_BSRR_BR5_Msk</a></td></tr>
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<tr class="separator:ga50fd21ca329283e8f79675f8195d6a7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa84d5cb9d0a0a945389ad0fef07eb2a" id="r_gafa84d5cb9d0a0a945389ad0fef07eb2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa84d5cb9d0a0a945389ad0fef07eb2a">GPIO_BRR_BR6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8695c8bfcc32bda2806805339db1e8ce">GPIO_BSRR_BR6</a></td></tr>
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<tr class="memitem:ga22e8aaa7e05c2f824d6fc1ae83f04913" id="r_ga22e8aaa7e05c2f824d6fc1ae83f04913"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22e8aaa7e05c2f824d6fc1ae83f04913">GPIO_BRR_BR6_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafce8dd4c2ed3764a234fc40ad192ae03">GPIO_BSRR_BR6_Pos</a></td></tr>
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<tr class="separator:ga22e8aaa7e05c2f824d6fc1ae83f04913"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae29f8525d511f39db8b6ac9efbae9ecc" id="r_gae29f8525d511f39db8b6ac9efbae9ecc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae29f8525d511f39db8b6ac9efbae9ecc">GPIO_BRR_BR6_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga354a942cded8f779316613b5a73b71ad">GPIO_BSRR_BR6_Msk</a></td></tr>
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<tr class="separator:gae29f8525d511f39db8b6ac9efbae9ecc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5110afe1f5bda4fde7983b447ce162c4" id="r_ga5110afe1f5bda4fde7983b447ce162c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5110afe1f5bda4fde7983b447ce162c4">GPIO_BRR_BR7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba577e8f2650976f219ad7ad93244f8a">GPIO_BSRR_BR7</a></td></tr>
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<tr class="separator:ga5110afe1f5bda4fde7983b447ce162c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga321d9cc2bc9fd4601694780ac4fcc7f6" id="r_ga321d9cc2bc9fd4601694780ac4fcc7f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga321d9cc2bc9fd4601694780ac4fcc7f6">GPIO_BRR_BR7_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34e114c3d131dbb2abc05837b9c20fff">GPIO_BSRR_BR7_Pos</a></td></tr>
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<tr class="separator:ga321d9cc2bc9fd4601694780ac4fcc7f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae40c636136e51fffad265559938cb9f0" id="r_gae40c636136e51fffad265559938cb9f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae40c636136e51fffad265559938cb9f0">GPIO_BRR_BR7_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b90d1d54ad1a0def096663cfe9cbd74">GPIO_BSRR_BR7_Msk</a></td></tr>
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<tr class="memitem:gae1560a3457fcec47c6f1871cf225557e" id="r_gae1560a3457fcec47c6f1871cf225557e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1560a3457fcec47c6f1871cf225557e">GPIO_BRR_BR8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaedbc146cc7659d51bc5f472d3a405ee">GPIO_BSRR_BR8</a></td></tr>
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<tr class="memitem:gaf45a746e5bb2a1c132093a2844d22683" id="r_gaf45a746e5bb2a1c132093a2844d22683"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf45a746e5bb2a1c132093a2844d22683">GPIO_BRR_BR8_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadebc6e8a656a3adbff46f398b5bcb3d4">GPIO_BSRR_BR8_Pos</a></td></tr>
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<tr class="memitem:gab9cd1191844e03a1aa271bd08e608e77" id="r_gab9cd1191844e03a1aa271bd08e608e77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9cd1191844e03a1aa271bd08e608e77">GPIO_BRR_BR8_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5460b708647c1a9f742c0ff0d5bcb17b">GPIO_BSRR_BR8_Msk</a></td></tr>
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<tr class="memitem:ga248ac798aa8fdd42573fa6ff4762ba58" id="r_ga248ac798aa8fdd42573fa6ff4762ba58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga248ac798aa8fdd42573fa6ff4762ba58">GPIO_BRR_BR9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3e0c779115c59cb98e021ede5605df3">GPIO_BSRR_BR9</a></td></tr>
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<tr class="memitem:ga84ae3878f9088d349453430a79e26810" id="r_ga84ae3878f9088d349453430a79e26810"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84ae3878f9088d349453430a79e26810">GPIO_BRR_BR9_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga13d98b977fc86581e566299bd363176d">GPIO_BSRR_BR9_Pos</a></td></tr>
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<tr class="memitem:ga0621db455e4164529a8e632bb413055d" id="r_ga0621db455e4164529a8e632bb413055d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0621db455e4164529a8e632bb413055d">GPIO_BRR_BR9_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4aa6d3943ec6a8d96dd855f436ab8e19">GPIO_BSRR_BR9_Msk</a></td></tr>
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<tr class="memitem:ga8fe20398333e9f7e5c247e0bcfcd1d31" id="r_ga8fe20398333e9f7e5c247e0bcfcd1d31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fe20398333e9f7e5c247e0bcfcd1d31">GPIO_BRR_BR10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga98581ac23be9f4fa003686d2ea523a81">GPIO_BSRR_BR10</a></td></tr>
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<tr class="memitem:ga08c89c18c00e1747d1392245f4fdeb19" id="r_ga08c89c18c00e1747d1392245f4fdeb19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08c89c18c00e1747d1392245f4fdeb19">GPIO_BRR_BR10_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga968f494c3928ba28bfa7c87da5f2cbaa">GPIO_BSRR_BR10_Pos</a></td></tr>
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<tr class="memitem:ga079add3e90617726dd8748c74abaf023" id="r_ga079add3e90617726dd8748c74abaf023"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga079add3e90617726dd8748c74abaf023">GPIO_BRR_BR10_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3f93f6e94ae0d842e5b0cda9ba6a1cd">GPIO_BSRR_BR10_Msk</a></td></tr>
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<tr class="memitem:gac65c4bf495800254168edce220f12294" id="r_gac65c4bf495800254168edce220f12294"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac65c4bf495800254168edce220f12294">GPIO_BRR_BR11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacedacd6c3e840a8172269cac3dbb550b">GPIO_BSRR_BR11</a></td></tr>
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<tr class="memitem:ga3a92027f04f25fd1b7ec7ad660052b42" id="r_ga3a92027f04f25fd1b7ec7ad660052b42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a92027f04f25fd1b7ec7ad660052b42">GPIO_BRR_BR11_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b421b338b145649e8937806472a59c6">GPIO_BSRR_BR11_Pos</a></td></tr>
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<tr class="separator:ga3a92027f04f25fd1b7ec7ad660052b42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad2be9a16fb6670ebb3492795bf6866a" id="r_gaad2be9a16fb6670ebb3492795bf6866a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad2be9a16fb6670ebb3492795bf6866a">GPIO_BRR_BR11_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f483f67fbc5614c010aa147e9ce6b3f">GPIO_BSRR_BR11_Msk</a></td></tr>
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<tr class="memitem:ga443c4943581f7590d706b183fb47250e" id="r_ga443c4943581f7590d706b183fb47250e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga443c4943581f7590d706b183fb47250e">GPIO_BRR_BR12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4622e78de418b59cd4199928801b6958">GPIO_BSRR_BR12</a></td></tr>
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<tr class="memitem:ga372754b6a71cbf3d09b959b2eef5fa7f" id="r_ga372754b6a71cbf3d09b959b2eef5fa7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga372754b6a71cbf3d09b959b2eef5fa7f">GPIO_BRR_BR12_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga79f141572b1c065dcabbc7ddfe4092f2">GPIO_BSRR_BR12_Pos</a></td></tr>
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<tr class="separator:ga372754b6a71cbf3d09b959b2eef5fa7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed3507b082d551500536f8c0c3929dca" id="r_gaed3507b082d551500536f8c0c3929dca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed3507b082d551500536f8c0c3929dca">GPIO_BRR_BR12_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa10f5ee9aeb2eefb25fd195e472c0de8">GPIO_BSRR_BR12_Msk</a></td></tr>
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<tr class="separator:gaed3507b082d551500536f8c0c3929dca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41f1e586a459fe54089921daed6b99cc" id="r_ga41f1e586a459fe54089921daed6b99cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41f1e586a459fe54089921daed6b99cc">GPIO_BRR_BR13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga292c1d0172620e0454ccc36f91f0c6ea">GPIO_BSRR_BR13</a></td></tr>
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<tr class="memitem:ga2dd4f25b9a855fb50ddc394a2384ccf2" id="r_ga2dd4f25b9a855fb50ddc394a2384ccf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dd4f25b9a855fb50ddc394a2384ccf2">GPIO_BRR_BR13_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga53a07a77a4bb0457b13abfee48ed3e39">GPIO_BSRR_BR13_Pos</a></td></tr>
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<tr class="separator:ga2dd4f25b9a855fb50ddc394a2384ccf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53217d2a5609f35d6b029a5e1eaf2e5f" id="r_ga53217d2a5609f35d6b029a5e1eaf2e5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53217d2a5609f35d6b029a5e1eaf2e5f">GPIO_BRR_BR13_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d000805bb6f4ad68ec73159df771422">GPIO_BSRR_BR13_Msk</a></td></tr>
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<tr class="separator:ga53217d2a5609f35d6b029a5e1eaf2e5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a77aa07922b7541f1e1c936a6651713" id="r_ga4a77aa07922b7541f1e1c936a6651713"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a77aa07922b7541f1e1c936a6651713">GPIO_BRR_BR14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga32477ac5ab4f5c7257ca332bb691b7cf">GPIO_BSRR_BR14</a></td></tr>
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<tr class="separator:ga4a77aa07922b7541f1e1c936a6651713"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10e2ac4dac68a55a7c574736a2964312" id="r_ga10e2ac4dac68a55a7c574736a2964312"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10e2ac4dac68a55a7c574736a2964312">GPIO_BRR_BR14_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e6b3f0c1a866cd39319f28cacbb768e">GPIO_BSRR_BR14_Pos</a></td></tr>
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<tr class="separator:ga10e2ac4dac68a55a7c574736a2964312"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga239abb28695da394a23f119ddd5aa724" id="r_ga239abb28695da394a23f119ddd5aa724"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga239abb28695da394a23f119ddd5aa724">GPIO_BRR_BR14_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ad1816ec382b6ef6e952cef1408933f">GPIO_BSRR_BR14_Msk</a></td></tr>
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<tr class="memitem:gab2ab1e0d0902e871836ae13d70c566df" id="r_gab2ab1e0d0902e871836ae13d70c566df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2ab1e0d0902e871836ae13d70c566df">GPIO_BRR_BR15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c6d612adeaae9b26d0ea4af74ffe1cd">GPIO_BSRR_BR15</a></td></tr>
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<tr class="separator:gab2ab1e0d0902e871836ae13d70c566df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d13b2c8e758203e32008267734f961f" id="r_ga7d13b2c8e758203e32008267734f961f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d13b2c8e758203e32008267734f961f">GPIO_BRR_BR15_Pos</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga30d885f9a72889c6f1070b6da4d4d782">GPIO_BSRR_BR15_Pos</a></td></tr>
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<tr class="separator:ga7d13b2c8e758203e32008267734f961f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga032413396d570a1f3041385e84ab009e" id="r_ga032413396d570a1f3041385e84ab009e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga032413396d570a1f3041385e84ab009e">GPIO_BRR_BR15_Msk</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8c00dff452eea9a285e36a81c5abd79">GPIO_BSRR_BR15_Msk</a></td></tr>
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<tr class="separator:ga032413396d570a1f3041385e84ab009e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a97048a23afc262b30fc9d0a4cb65bc" id="r_ga9a97048a23afc262b30fc9d0a4cb65bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a97048a23afc262b30fc9d0a4cb65bc">GPIO_LCKR_LCK0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga9a97048a23afc262b30fc9d0a4cb65bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b01ced29f1324ec2711a784f35504dd" id="r_ga8b01ced29f1324ec2711a784f35504dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b01ced29f1324ec2711a784f35504dd">GPIO_LCKR_LCK0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a97048a23afc262b30fc9d0a4cb65bc">GPIO_LCKR_LCK0_Pos</a>)</td></tr>
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<tr class="separator:ga8b01ced29f1324ec2711a784f35504dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6ae6b6d787a6af758bfde54b6ae934f" id="r_gaf6ae6b6d787a6af758bfde54b6ae934f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6ae6b6d787a6af758bfde54b6ae934f">GPIO_LCKR_LCK0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b01ced29f1324ec2711a784f35504dd">GPIO_LCKR_LCK0_Msk</a></td></tr>
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<tr class="separator:gaf6ae6b6d787a6af758bfde54b6ae934f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94100a3d7d43a5b8718aea76e31279a7" id="r_ga94100a3d7d43a5b8718aea76e31279a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94100a3d7d43a5b8718aea76e31279a7">GPIO_LCKR_LCK1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga94100a3d7d43a5b8718aea76e31279a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4780ec15743062227ad0808efb16d633" id="r_ga4780ec15743062227ad0808efb16d633"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4780ec15743062227ad0808efb16d633">GPIO_LCKR_LCK1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga94100a3d7d43a5b8718aea76e31279a7">GPIO_LCKR_LCK1_Pos</a>)</td></tr>
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<tr class="separator:ga4780ec15743062227ad0808efb16d633"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga627d088ded79e6da761eaa880582372a" id="r_ga627d088ded79e6da761eaa880582372a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga627d088ded79e6da761eaa880582372a">GPIO_LCKR_LCK1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4780ec15743062227ad0808efb16d633">GPIO_LCKR_LCK1_Msk</a></td></tr>
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<tr class="separator:ga627d088ded79e6da761eaa880582372a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96d48b0834c3898e74309980020f88a3" id="r_ga96d48b0834c3898e74309980020f88a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96d48b0834c3898e74309980020f88a3">GPIO_LCKR_LCK2_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga96d48b0834c3898e74309980020f88a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc8315e9687b2a21a55a2abe39d42fdf" id="r_gabc8315e9687b2a21a55a2abe39d42fdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc8315e9687b2a21a55a2abe39d42fdf">GPIO_LCKR_LCK2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96d48b0834c3898e74309980020f88a3">GPIO_LCKR_LCK2_Pos</a>)</td></tr>
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<tr class="separator:gabc8315e9687b2a21a55a2abe39d42fdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5a17a7348d45dbe2b2ea41a0908d7de" id="r_gac5a17a7348d45dbe2b2ea41a0908d7de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5a17a7348d45dbe2b2ea41a0908d7de">GPIO_LCKR_LCK2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabc8315e9687b2a21a55a2abe39d42fdf">GPIO_LCKR_LCK2_Msk</a></td></tr>
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<tr class="memitem:ga348f1d0358ea70f6a7dc2a00a1c519bf" id="r_ga348f1d0358ea70f6a7dc2a00a1c519bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga348f1d0358ea70f6a7dc2a00a1c519bf">GPIO_LCKR_LCK3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga348f1d0358ea70f6a7dc2a00a1c519bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f2a02d88e51b603d4b80078ccf691e0" id="r_ga7f2a02d88e51b603d4b80078ccf691e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f2a02d88e51b603d4b80078ccf691e0">GPIO_LCKR_LCK3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga348f1d0358ea70f6a7dc2a00a1c519bf">GPIO_LCKR_LCK3_Pos</a>)</td></tr>
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<tr class="separator:ga7f2a02d88e51b603d4b80078ccf691e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1597c1b50d32ed0229c38811656ba402" id="r_ga1597c1b50d32ed0229c38811656ba402"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1597c1b50d32ed0229c38811656ba402">GPIO_LCKR_LCK3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f2a02d88e51b603d4b80078ccf691e0">GPIO_LCKR_LCK3_Msk</a></td></tr>
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<tr class="separator:ga1597c1b50d32ed0229c38811656ba402"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fd29e0757ed2bc8e3935d17960b68df" id="r_ga9fd29e0757ed2bc8e3935d17960b68df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fd29e0757ed2bc8e3935d17960b68df">GPIO_LCKR_LCK4_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga9fd29e0757ed2bc8e3935d17960b68df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6c6dff29eb48ca0a5f6da2bc0bf3639" id="r_gac6c6dff29eb48ca0a5f6da2bc0bf3639"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6c6dff29eb48ca0a5f6da2bc0bf3639">GPIO_LCKR_LCK4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9fd29e0757ed2bc8e3935d17960b68df">GPIO_LCKR_LCK4_Pos</a>)</td></tr>
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<tr class="separator:gac6c6dff29eb48ca0a5f6da2bc0bf3639"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga723577475747d2405d86b1ab28767cb5" id="r_ga723577475747d2405d86b1ab28767cb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga723577475747d2405d86b1ab28767cb5">GPIO_LCKR_LCK4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac6c6dff29eb48ca0a5f6da2bc0bf3639">GPIO_LCKR_LCK4_Msk</a></td></tr>
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<tr class="separator:ga723577475747d2405d86b1ab28767cb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07f73a37145ff6709a20081d329900c2" id="r_ga07f73a37145ff6709a20081d329900c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07f73a37145ff6709a20081d329900c2">GPIO_LCKR_LCK5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga07f73a37145ff6709a20081d329900c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc6ac7aca22480f300049102d2b1c4be" id="r_gacc6ac7aca22480f300049102d2b1c4be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc6ac7aca22480f300049102d2b1c4be">GPIO_LCKR_LCK5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07f73a37145ff6709a20081d329900c2">GPIO_LCKR_LCK5_Pos</a>)</td></tr>
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<tr class="separator:gacc6ac7aca22480f300049102d2b1c4be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c2446bfe50cbd04617496c30eda6c18" id="r_ga7c2446bfe50cbd04617496c30eda6c18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c2446bfe50cbd04617496c30eda6c18">GPIO_LCKR_LCK5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacc6ac7aca22480f300049102d2b1c4be">GPIO_LCKR_LCK5_Msk</a></td></tr>
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<tr class="separator:ga7c2446bfe50cbd04617496c30eda6c18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga456193c04a296b05ad87aa0f8e51c144" id="r_ga456193c04a296b05ad87aa0f8e51c144"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga456193c04a296b05ad87aa0f8e51c144">GPIO_LCKR_LCK6_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga456193c04a296b05ad87aa0f8e51c144"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga083a590c26723e38ae5d7fd77e23809c" id="r_ga083a590c26723e38ae5d7fd77e23809c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga083a590c26723e38ae5d7fd77e23809c">GPIO_LCKR_LCK6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga456193c04a296b05ad87aa0f8e51c144">GPIO_LCKR_LCK6_Pos</a>)</td></tr>
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<tr class="separator:ga083a590c26723e38ae5d7fd77e23809c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga606249f4cc3ac14cf8133b76f3c7edd7" id="r_ga606249f4cc3ac14cf8133b76f3c7edd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga606249f4cc3ac14cf8133b76f3c7edd7">GPIO_LCKR_LCK6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga083a590c26723e38ae5d7fd77e23809c">GPIO_LCKR_LCK6_Msk</a></td></tr>
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<tr class="separator:ga606249f4cc3ac14cf8133b76f3c7edd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9c741b163a1b1e23b05432f866544f4" id="r_gaf9c741b163a1b1e23b05432f866544f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9c741b163a1b1e23b05432f866544f4">GPIO_LCKR_LCK7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaf9c741b163a1b1e23b05432f866544f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b322ee1833e0c7d369127406b5ea90e" id="r_ga5b322ee1833e0c7d369127406b5ea90e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b322ee1833e0c7d369127406b5ea90e">GPIO_LCKR_LCK7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9c741b163a1b1e23b05432f866544f4">GPIO_LCKR_LCK7_Pos</a>)</td></tr>
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<tr class="separator:ga5b322ee1833e0c7d369127406b5ea90e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf998da536594af780718084cee0d22a4" id="r_gaf998da536594af780718084cee0d22a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf998da536594af780718084cee0d22a4">GPIO_LCKR_LCK7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b322ee1833e0c7d369127406b5ea90e">GPIO_LCKR_LCK7_Msk</a></td></tr>
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<tr class="separator:gaf998da536594af780718084cee0d22a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9a02f2ef3023a1c82f04391fcb79859" id="r_gae9a02f2ef3023a1c82f04391fcb79859"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9a02f2ef3023a1c82f04391fcb79859">GPIO_LCKR_LCK8_Pos</a>   (8U)</td></tr>
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<tr class="separator:gae9a02f2ef3023a1c82f04391fcb79859"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0e44a9155de4980cdb0f8c4d3afc43e" id="r_gaa0e44a9155de4980cdb0f8c4d3afc43e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0e44a9155de4980cdb0f8c4d3afc43e">GPIO_LCKR_LCK8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9a02f2ef3023a1c82f04391fcb79859">GPIO_LCKR_LCK8_Pos</a>)</td></tr>
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<tr class="separator:gaa0e44a9155de4980cdb0f8c4d3afc43e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab00a81afcf4d92f6f5644724803b7404" id="r_gab00a81afcf4d92f6f5644724803b7404"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab00a81afcf4d92f6f5644724803b7404">GPIO_LCKR_LCK8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0e44a9155de4980cdb0f8c4d3afc43e">GPIO_LCKR_LCK8_Msk</a></td></tr>
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<tr class="separator:gab00a81afcf4d92f6f5644724803b7404"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga821f9dc79420f84e79fe2697addf1d42" id="r_ga821f9dc79420f84e79fe2697addf1d42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga821f9dc79420f84e79fe2697addf1d42">GPIO_LCKR_LCK9_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga821f9dc79420f84e79fe2697addf1d42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga551c1ad8749c8ddb6785c06c1461338f" id="r_ga551c1ad8749c8ddb6785c06c1461338f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga551c1ad8749c8ddb6785c06c1461338f">GPIO_LCKR_LCK9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga821f9dc79420f84e79fe2697addf1d42">GPIO_LCKR_LCK9_Pos</a>)</td></tr>
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<tr class="separator:ga551c1ad8749c8ddb6785c06c1461338f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9aa0442c88bc17eaf07c55dd84910ea" id="r_gab9aa0442c88bc17eaf07c55dd84910ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9aa0442c88bc17eaf07c55dd84910ea">GPIO_LCKR_LCK9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga551c1ad8749c8ddb6785c06c1461338f">GPIO_LCKR_LCK9_Msk</a></td></tr>
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<tr class="separator:gab9aa0442c88bc17eaf07c55dd84910ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8eeb57953118508685e74055da9d6348" id="r_ga8eeb57953118508685e74055da9d6348"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8eeb57953118508685e74055da9d6348">GPIO_LCKR_LCK10_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga8eeb57953118508685e74055da9d6348"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1373c9d71b76f466fd817823e64e7aae" id="r_ga1373c9d71b76f466fd817823e64e7aae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1373c9d71b76f466fd817823e64e7aae">GPIO_LCKR_LCK10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8eeb57953118508685e74055da9d6348">GPIO_LCKR_LCK10_Pos</a>)</td></tr>
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<tr class="separator:ga1373c9d71b76f466fd817823e64e7aae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae055f5848967c7929f47e848b2ed812" id="r_gaae055f5848967c7929f47e848b2ed812"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae055f5848967c7929f47e848b2ed812">GPIO_LCKR_LCK10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1373c9d71b76f466fd817823e64e7aae">GPIO_LCKR_LCK10_Msk</a></td></tr>
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<tr class="separator:gaae055f5848967c7929f47e848b2ed812"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a19305a39f7bd02815a39c998c34216" id="r_ga4a19305a39f7bd02815a39c998c34216"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a19305a39f7bd02815a39c998c34216">GPIO_LCKR_LCK11_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga4a19305a39f7bd02815a39c998c34216"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1aea84ab5cf33a4b62cdb3af4a819bde" id="r_ga1aea84ab5cf33a4b62cdb3af4a819bde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1aea84ab5cf33a4b62cdb3af4a819bde">GPIO_LCKR_LCK11_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a19305a39f7bd02815a39c998c34216">GPIO_LCKR_LCK11_Pos</a>)</td></tr>
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<tr class="separator:ga1aea84ab5cf33a4b62cdb3af4a819bde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4de971426a1248621733a9b78ef552ab" id="r_ga4de971426a1248621733a9b78ef552ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4de971426a1248621733a9b78ef552ab">GPIO_LCKR_LCK11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1aea84ab5cf33a4b62cdb3af4a819bde">GPIO_LCKR_LCK11_Msk</a></td></tr>
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<tr class="separator:ga4de971426a1248621733a9b78ef552ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81e8901ea395cd0a1b56c4118670fa0e" id="r_ga81e8901ea395cd0a1b56c4118670fa0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81e8901ea395cd0a1b56c4118670fa0e">GPIO_LCKR_LCK12_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga81e8901ea395cd0a1b56c4118670fa0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf21271b45020769396b2980a02a4c309" id="r_gaf21271b45020769396b2980a02a4c309"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf21271b45020769396b2980a02a4c309">GPIO_LCKR_LCK12_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga81e8901ea395cd0a1b56c4118670fa0e">GPIO_LCKR_LCK12_Pos</a>)</td></tr>
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<tr class="separator:gaf21271b45020769396b2980a02a4c309"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38e8685790aea3fb09194683d1f58508" id="r_ga38e8685790aea3fb09194683d1f58508"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38e8685790aea3fb09194683d1f58508">GPIO_LCKR_LCK12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf21271b45020769396b2980a02a4c309">GPIO_LCKR_LCK12_Msk</a></td></tr>
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<tr class="separator:ga38e8685790aea3fb09194683d1f58508"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5dd0ccab863e23880863f0d431fdee11" id="r_ga5dd0ccab863e23880863f0d431fdee11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5dd0ccab863e23880863f0d431fdee11">GPIO_LCKR_LCK13_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga5dd0ccab863e23880863f0d431fdee11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64171a6f566fed1f9ea7418d6a00871c" id="r_ga64171a6f566fed1f9ea7418d6a00871c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64171a6f566fed1f9ea7418d6a00871c">GPIO_LCKR_LCK13_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5dd0ccab863e23880863f0d431fdee11">GPIO_LCKR_LCK13_Pos</a>)</td></tr>
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<tr class="separator:ga64171a6f566fed1f9ea7418d6a00871c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0279fa554731160a9115c21d95312a5" id="r_gae0279fa554731160a9115c21d95312a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0279fa554731160a9115c21d95312a5">GPIO_LCKR_LCK13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64171a6f566fed1f9ea7418d6a00871c">GPIO_LCKR_LCK13_Msk</a></td></tr>
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<tr class="memitem:ga5686e00f4e40771a31eb18d88e1ca1e9" id="r_ga5686e00f4e40771a31eb18d88e1ca1e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5686e00f4e40771a31eb18d88e1ca1e9">GPIO_LCKR_LCK14_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gac42b591ea761bd0ee23287ff8d508714" id="r_gac42b591ea761bd0ee23287ff8d508714"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac42b591ea761bd0ee23287ff8d508714">GPIO_LCKR_LCK14_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5686e00f4e40771a31eb18d88e1ca1e9">GPIO_LCKR_LCK14_Pos</a>)</td></tr>
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<tr class="memitem:ga8bf290cecb54b6b68ac42a544b87dcee" id="r_ga8bf290cecb54b6b68ac42a544b87dcee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8bf290cecb54b6b68ac42a544b87dcee">GPIO_LCKR_LCK14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac42b591ea761bd0ee23287ff8d508714">GPIO_LCKR_LCK14_Msk</a></td></tr>
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<tr class="memitem:ga5ba6d99e256f344ea2d8a4ba9278a0e3" id="r_ga5ba6d99e256f344ea2d8a4ba9278a0e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ba6d99e256f344ea2d8a4ba9278a0e3">GPIO_LCKR_LCK15_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga3841ea86b5a8200485ab90c2c6511cec" id="r_ga3841ea86b5a8200485ab90c2c6511cec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3841ea86b5a8200485ab90c2c6511cec">GPIO_LCKR_LCK15_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ba6d99e256f344ea2d8a4ba9278a0e3">GPIO_LCKR_LCK15_Pos</a>)</td></tr>
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<tr class="memitem:ga47c3114c8cd603d8aee022d0b426bf04" id="r_ga47c3114c8cd603d8aee022d0b426bf04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47c3114c8cd603d8aee022d0b426bf04">GPIO_LCKR_LCK15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3841ea86b5a8200485ab90c2c6511cec">GPIO_LCKR_LCK15_Msk</a></td></tr>
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<tr class="memitem:ga40eb2db1c2df544774f41995d029565d" id="r_ga40eb2db1c2df544774f41995d029565d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40eb2db1c2df544774f41995d029565d">GPIO_LCKR_LCKK_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga9312bf35ddbae593f8e94b3ea7dce9b5" id="r_ga9312bf35ddbae593f8e94b3ea7dce9b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9312bf35ddbae593f8e94b3ea7dce9b5">GPIO_LCKR_LCKK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga40eb2db1c2df544774f41995d029565d">GPIO_LCKR_LCKK_Pos</a>)</td></tr>
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<tr class="memitem:gafa2a83bf31ef76ee3857c7cb0a90c4d9" id="r_gafa2a83bf31ef76ee3857c7cb0a90c4d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa2a83bf31ef76ee3857c7cb0a90c4d9">GPIO_LCKR_LCKK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9312bf35ddbae593f8e94b3ea7dce9b5">GPIO_LCKR_LCKK_Msk</a></td></tr>
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<tr class="memitem:gac06dd36e2c8c90fe9502bad271b2ee60" id="r_gac06dd36e2c8c90fe9502bad271b2ee60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac06dd36e2c8c90fe9502bad271b2ee60">GPIO_AFRL_AFSEL0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga214860438ba3256833543e2f5018922f" id="r_ga214860438ba3256833543e2f5018922f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga214860438ba3256833543e2f5018922f">GPIO_AFRL_AFSEL0_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac06dd36e2c8c90fe9502bad271b2ee60">GPIO_AFRL_AFSEL0_Pos</a>)</td></tr>
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<tr class="memitem:ga7ec251e186471ae09aeb3cb0aa788594" id="r_ga7ec251e186471ae09aeb3cb0aa788594"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ec251e186471ae09aeb3cb0aa788594">GPIO_AFRL_AFSEL0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga214860438ba3256833543e2f5018922f">GPIO_AFRL_AFSEL0_Msk</a></td></tr>
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<tr class="memitem:ga3d64770b98ab6db5eee36068d6e0c45a" id="r_ga3d64770b98ab6db5eee36068d6e0c45a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d64770b98ab6db5eee36068d6e0c45a">GPIO_AFRL_AFSEL0_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac06dd36e2c8c90fe9502bad271b2ee60">GPIO_AFRL_AFSEL0_Pos</a>)</td></tr>
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<tr class="separator:ga3d64770b98ab6db5eee36068d6e0c45a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabf16f4a3f9458d9576accc1695bed4a" id="r_gaabf16f4a3f9458d9576accc1695bed4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabf16f4a3f9458d9576accc1695bed4a">GPIO_AFRL_AFSEL0_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac06dd36e2c8c90fe9502bad271b2ee60">GPIO_AFRL_AFSEL0_Pos</a>)</td></tr>
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<tr class="memitem:gab872e44f9df01f18e4f78cee45d5cf43" id="r_gab872e44f9df01f18e4f78cee45d5cf43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab872e44f9df01f18e4f78cee45d5cf43">GPIO_AFRL_AFSEL0_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac06dd36e2c8c90fe9502bad271b2ee60">GPIO_AFRL_AFSEL0_Pos</a>)</td></tr>
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<tr class="memitem:ga5a83a0eb943535ea970419f7bb87fa52" id="r_ga5a83a0eb943535ea970419f7bb87fa52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a83a0eb943535ea970419f7bb87fa52">GPIO_AFRL_AFSEL0_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac06dd36e2c8c90fe9502bad271b2ee60">GPIO_AFRL_AFSEL0_Pos</a>)</td></tr>
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<tr class="separator:ga5a83a0eb943535ea970419f7bb87fa52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga313ba8093d5a511430908d9adc90dc6a" id="r_ga313ba8093d5a511430908d9adc90dc6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga313ba8093d5a511430908d9adc90dc6a">GPIO_AFRL_AFSEL1_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga313ba8093d5a511430908d9adc90dc6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5aac45598b88539da585e098fc93d68b" id="r_ga5aac45598b88539da585e098fc93d68b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5aac45598b88539da585e098fc93d68b">GPIO_AFRL_AFSEL1_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga313ba8093d5a511430908d9adc90dc6a">GPIO_AFRL_AFSEL1_Pos</a>)</td></tr>
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<tr class="separator:ga5aac45598b88539da585e098fc93d68b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fbd174222a013c9a0e222fdd0888de2" id="r_ga9fbd174222a013c9a0e222fdd0888de2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fbd174222a013c9a0e222fdd0888de2">GPIO_AFRL_AFSEL1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5aac45598b88539da585e098fc93d68b">GPIO_AFRL_AFSEL1_Msk</a></td></tr>
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<tr class="memitem:gae6834a1a64ce4c42bd71cdb0bc685f06" id="r_gae6834a1a64ce4c42bd71cdb0bc685f06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6834a1a64ce4c42bd71cdb0bc685f06">GPIO_AFRL_AFSEL1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga313ba8093d5a511430908d9adc90dc6a">GPIO_AFRL_AFSEL1_Pos</a>)</td></tr>
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<tr class="memitem:gac4f1e8fe3cf48f2dcdd6cd96c88b5754" id="r_gac4f1e8fe3cf48f2dcdd6cd96c88b5754"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4f1e8fe3cf48f2dcdd6cd96c88b5754">GPIO_AFRL_AFSEL1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga313ba8093d5a511430908d9adc90dc6a">GPIO_AFRL_AFSEL1_Pos</a>)</td></tr>
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<tr class="separator:gac4f1e8fe3cf48f2dcdd6cd96c88b5754"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac38c620ad920142f38db8ef78674df56" id="r_gac38c620ad920142f38db8ef78674df56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac38c620ad920142f38db8ef78674df56">GPIO_AFRL_AFSEL1_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga313ba8093d5a511430908d9adc90dc6a">GPIO_AFRL_AFSEL1_Pos</a>)</td></tr>
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<tr class="memitem:ga4ee3c6fd5280247ff5cb1e4c139ab85d" id="r_ga4ee3c6fd5280247ff5cb1e4c139ab85d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ee3c6fd5280247ff5cb1e4c139ab85d">GPIO_AFRL_AFSEL1_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga313ba8093d5a511430908d9adc90dc6a">GPIO_AFRL_AFSEL1_Pos</a>)</td></tr>
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<tr class="separator:ga4ee3c6fd5280247ff5cb1e4c139ab85d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae132b28ab4f67a9e90e7d15302aad49b" id="r_gae132b28ab4f67a9e90e7d15302aad49b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae132b28ab4f67a9e90e7d15302aad49b">GPIO_AFRL_AFSEL2_Pos</a>   (8U)</td></tr>
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<tr class="separator:gae132b28ab4f67a9e90e7d15302aad49b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga729f1e6b663a55ce7f5cfbe1c71489a4" id="r_ga729f1e6b663a55ce7f5cfbe1c71489a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga729f1e6b663a55ce7f5cfbe1c71489a4">GPIO_AFRL_AFSEL2_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae132b28ab4f67a9e90e7d15302aad49b">GPIO_AFRL_AFSEL2_Pos</a>)</td></tr>
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<tr class="separator:ga729f1e6b663a55ce7f5cfbe1c71489a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9bc63205b8a09bd2ae7fb066058f3da" id="r_gaa9bc63205b8a09bd2ae7fb066058f3da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9bc63205b8a09bd2ae7fb066058f3da">GPIO_AFRL_AFSEL2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga729f1e6b663a55ce7f5cfbe1c71489a4">GPIO_AFRL_AFSEL2_Msk</a></td></tr>
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<tr class="separator:gaa9bc63205b8a09bd2ae7fb066058f3da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga566eef02569b14ba89745698e4c7f4cb" id="r_ga566eef02569b14ba89745698e4c7f4cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga566eef02569b14ba89745698e4c7f4cb">GPIO_AFRL_AFSEL2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae132b28ab4f67a9e90e7d15302aad49b">GPIO_AFRL_AFSEL2_Pos</a>)</td></tr>
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<tr class="memitem:ga99704f0bd6543a391b934faae9f86c0e" id="r_ga99704f0bd6543a391b934faae9f86c0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99704f0bd6543a391b934faae9f86c0e">GPIO_AFRL_AFSEL2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae132b28ab4f67a9e90e7d15302aad49b">GPIO_AFRL_AFSEL2_Pos</a>)</td></tr>
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<tr class="separator:ga99704f0bd6543a391b934faae9f86c0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e90655a95edd288bda4552137310e7c" id="r_ga8e90655a95edd288bda4552137310e7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e90655a95edd288bda4552137310e7c">GPIO_AFRL_AFSEL2_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae132b28ab4f67a9e90e7d15302aad49b">GPIO_AFRL_AFSEL2_Pos</a>)</td></tr>
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<tr class="memitem:ga2a2b8fe31b1620d99caaa0d5b00214fc" id="r_ga2a2b8fe31b1620d99caaa0d5b00214fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a2b8fe31b1620d99caaa0d5b00214fc">GPIO_AFRL_AFSEL2_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae132b28ab4f67a9e90e7d15302aad49b">GPIO_AFRL_AFSEL2_Pos</a>)</td></tr>
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<tr class="separator:ga2a2b8fe31b1620d99caaa0d5b00214fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d9325a035cc3d6962d660d3f54a8df4" id="r_ga0d9325a035cc3d6962d660d3f54a8df4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d9325a035cc3d6962d660d3f54a8df4">GPIO_AFRL_AFSEL3_Pos</a>   (12U)</td></tr>
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<tr class="memitem:gaf34ee7b30defbcad60d167a279a8c17d" id="r_gaf34ee7b30defbcad60d167a279a8c17d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf34ee7b30defbcad60d167a279a8c17d">GPIO_AFRL_AFSEL3_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d9325a035cc3d6962d660d3f54a8df4">GPIO_AFRL_AFSEL3_Pos</a>)</td></tr>
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<tr class="memitem:gae0fb36c07eac3809b6a5baaee74ee426" id="r_gae0fb36c07eac3809b6a5baaee74ee426"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0fb36c07eac3809b6a5baaee74ee426">GPIO_AFRL_AFSEL3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf34ee7b30defbcad60d167a279a8c17d">GPIO_AFRL_AFSEL3_Msk</a></td></tr>
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<tr class="memitem:gaf0eb39bec095e2b4661141b20c1bd80d" id="r_gaf0eb39bec095e2b4661141b20c1bd80d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0eb39bec095e2b4661141b20c1bd80d">GPIO_AFRL_AFSEL3_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d9325a035cc3d6962d660d3f54a8df4">GPIO_AFRL_AFSEL3_Pos</a>)</td></tr>
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<tr class="memitem:ga97101a6c182091257d9a86f38bbf8015" id="r_ga97101a6c182091257d9a86f38bbf8015"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97101a6c182091257d9a86f38bbf8015">GPIO_AFRL_AFSEL3_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d9325a035cc3d6962d660d3f54a8df4">GPIO_AFRL_AFSEL3_Pos</a>)</td></tr>
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<tr class="memitem:gaf97dd08bfd9439ae9a8be2aae31572ab" id="r_gaf97dd08bfd9439ae9a8be2aae31572ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf97dd08bfd9439ae9a8be2aae31572ab">GPIO_AFRL_AFSEL3_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d9325a035cc3d6962d660d3f54a8df4">GPIO_AFRL_AFSEL3_Pos</a>)</td></tr>
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<tr class="memitem:ga640b17198ae3a4dca834c93941bb459e" id="r_ga640b17198ae3a4dca834c93941bb459e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga640b17198ae3a4dca834c93941bb459e">GPIO_AFRL_AFSEL3_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d9325a035cc3d6962d660d3f54a8df4">GPIO_AFRL_AFSEL3_Pos</a>)</td></tr>
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<tr class="memitem:ga723fbe4b28093f1837001110d8d44d36" id="r_ga723fbe4b28093f1837001110d8d44d36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga723fbe4b28093f1837001110d8d44d36">GPIO_AFRL_AFSEL4_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga47cfab1b5c3a37414bc4a6ac2cbd746a" id="r_ga47cfab1b5c3a37414bc4a6ac2cbd746a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47cfab1b5c3a37414bc4a6ac2cbd746a">GPIO_AFRL_AFSEL4_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga723fbe4b28093f1837001110d8d44d36">GPIO_AFRL_AFSEL4_Pos</a>)</td></tr>
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<tr class="separator:ga47cfab1b5c3a37414bc4a6ac2cbd746a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga728e20cadadaa3c5aa1c42c25356a9f4" id="r_ga728e20cadadaa3c5aa1c42c25356a9f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga728e20cadadaa3c5aa1c42c25356a9f4">GPIO_AFRL_AFSEL4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47cfab1b5c3a37414bc4a6ac2cbd746a">GPIO_AFRL_AFSEL4_Msk</a></td></tr>
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<tr class="memitem:ga958dcb0150574251c77490397469d443" id="r_ga958dcb0150574251c77490397469d443"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga958dcb0150574251c77490397469d443">GPIO_AFRL_AFSEL4_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga723fbe4b28093f1837001110d8d44d36">GPIO_AFRL_AFSEL4_Pos</a>)</td></tr>
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<tr class="memitem:ga89f30587f699e9b28347b41b1752d846" id="r_ga89f30587f699e9b28347b41b1752d846"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89f30587f699e9b28347b41b1752d846">GPIO_AFRL_AFSEL4_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga723fbe4b28093f1837001110d8d44d36">GPIO_AFRL_AFSEL4_Pos</a>)</td></tr>
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<tr class="separator:ga89f30587f699e9b28347b41b1752d846"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafeb379dcb35516d7744e8a7467aa9ddf" id="r_gafeb379dcb35516d7744e8a7467aa9ddf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafeb379dcb35516d7744e8a7467aa9ddf">GPIO_AFRL_AFSEL4_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga723fbe4b28093f1837001110d8d44d36">GPIO_AFRL_AFSEL4_Pos</a>)</td></tr>
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<tr class="memitem:ga3c7a684490eaf01f5e1bd29f89bebfb8" id="r_ga3c7a684490eaf01f5e1bd29f89bebfb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c7a684490eaf01f5e1bd29f89bebfb8">GPIO_AFRL_AFSEL4_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga723fbe4b28093f1837001110d8d44d36">GPIO_AFRL_AFSEL4_Pos</a>)</td></tr>
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<tr class="separator:ga3c7a684490eaf01f5e1bd29f89bebfb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf35270d71f53047d2a14d1047478c0ba" id="r_gaf35270d71f53047d2a14d1047478c0ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf35270d71f53047d2a14d1047478c0ba">GPIO_AFRL_AFSEL5_Pos</a>   (20U)</td></tr>
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<tr class="separator:gaf35270d71f53047d2a14d1047478c0ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf514d5f0c3456e2f7fc6d82f2b392051" id="r_gaf514d5f0c3456e2f7fc6d82f2b392051"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf514d5f0c3456e2f7fc6d82f2b392051">GPIO_AFRL_AFSEL5_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf35270d71f53047d2a14d1047478c0ba">GPIO_AFRL_AFSEL5_Pos</a>)</td></tr>
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<tr class="separator:gaf514d5f0c3456e2f7fc6d82f2b392051"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad158052aa17b4bf12f9ad20b6e0c6d0c" id="r_gad158052aa17b4bf12f9ad20b6e0c6d0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad158052aa17b4bf12f9ad20b6e0c6d0c">GPIO_AFRL_AFSEL5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf514d5f0c3456e2f7fc6d82f2b392051">GPIO_AFRL_AFSEL5_Msk</a></td></tr>
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<tr class="separator:gad158052aa17b4bf12f9ad20b6e0c6d0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fba4a0c264295148200fdbea3645efb" id="r_ga4fba4a0c264295148200fdbea3645efb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fba4a0c264295148200fdbea3645efb">GPIO_AFRL_AFSEL5_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf35270d71f53047d2a14d1047478c0ba">GPIO_AFRL_AFSEL5_Pos</a>)</td></tr>
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<tr class="separator:ga4fba4a0c264295148200fdbea3645efb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf532421a6d6665eb9dd82752aa71bda6" id="r_gaf532421a6d6665eb9dd82752aa71bda6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf532421a6d6665eb9dd82752aa71bda6">GPIO_AFRL_AFSEL5_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf35270d71f53047d2a14d1047478c0ba">GPIO_AFRL_AFSEL5_Pos</a>)</td></tr>
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<tr class="separator:gaf532421a6d6665eb9dd82752aa71bda6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga600caf3a081a223a0c9bbd22c1d65fd7" id="r_ga600caf3a081a223a0c9bbd22c1d65fd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga600caf3a081a223a0c9bbd22c1d65fd7">GPIO_AFRL_AFSEL5_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf35270d71f53047d2a14d1047478c0ba">GPIO_AFRL_AFSEL5_Pos</a>)</td></tr>
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<tr class="separator:ga600caf3a081a223a0c9bbd22c1d65fd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cf281224f66730f522948ce2f16a9dc" id="r_ga3cf281224f66730f522948ce2f16a9dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cf281224f66730f522948ce2f16a9dc">GPIO_AFRL_AFSEL5_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf35270d71f53047d2a14d1047478c0ba">GPIO_AFRL_AFSEL5_Pos</a>)</td></tr>
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<tr class="separator:ga3cf281224f66730f522948ce2f16a9dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9943c5aeeb649ab6bf33fde0d844803" id="r_gad9943c5aeeb649ab6bf33fde0d844803"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9943c5aeeb649ab6bf33fde0d844803">GPIO_AFRL_AFSEL6_Pos</a>   (24U)</td></tr>
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<tr class="separator:gad9943c5aeeb649ab6bf33fde0d844803"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb4e272e9b14944740fbe643542f0ade" id="r_gafb4e272e9b14944740fbe643542f0ade"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb4e272e9b14944740fbe643542f0ade">GPIO_AFRL_AFSEL6_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9943c5aeeb649ab6bf33fde0d844803">GPIO_AFRL_AFSEL6_Pos</a>)</td></tr>
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<tr class="separator:gafb4e272e9b14944740fbe643542f0ade"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga893c83ab521d1bf15e71b20309d71503" id="r_ga893c83ab521d1bf15e71b20309d71503"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga893c83ab521d1bf15e71b20309d71503">GPIO_AFRL_AFSEL6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb4e272e9b14944740fbe643542f0ade">GPIO_AFRL_AFSEL6_Msk</a></td></tr>
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<tr class="separator:ga893c83ab521d1bf15e71b20309d71503"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4eb2b4e77d1338ae80e889bb7f98159" id="r_gae4eb2b4e77d1338ae80e889bb7f98159"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4eb2b4e77d1338ae80e889bb7f98159">GPIO_AFRL_AFSEL6_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9943c5aeeb649ab6bf33fde0d844803">GPIO_AFRL_AFSEL6_Pos</a>)</td></tr>
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<tr class="separator:gae4eb2b4e77d1338ae80e889bb7f98159"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87ae4b89cf40e01fc3d0c1cca38db1de" id="r_ga87ae4b89cf40e01fc3d0c1cca38db1de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87ae4b89cf40e01fc3d0c1cca38db1de">GPIO_AFRL_AFSEL6_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9943c5aeeb649ab6bf33fde0d844803">GPIO_AFRL_AFSEL6_Pos</a>)</td></tr>
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<tr class="separator:ga87ae4b89cf40e01fc3d0c1cca38db1de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace077c57cb72736ef5dca98052403b72" id="r_gace077c57cb72736ef5dca98052403b72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace077c57cb72736ef5dca98052403b72">GPIO_AFRL_AFSEL6_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9943c5aeeb649ab6bf33fde0d844803">GPIO_AFRL_AFSEL6_Pos</a>)</td></tr>
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<tr class="separator:gace077c57cb72736ef5dca98052403b72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b1fee857fd7d1b412ed64b1c6572280" id="r_ga0b1fee857fd7d1b412ed64b1c6572280"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b1fee857fd7d1b412ed64b1c6572280">GPIO_AFRL_AFSEL6_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9943c5aeeb649ab6bf33fde0d844803">GPIO_AFRL_AFSEL6_Pos</a>)</td></tr>
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<tr class="separator:ga0b1fee857fd7d1b412ed64b1c6572280"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2836c1149e06b2497f1f53518f1151f2" id="r_ga2836c1149e06b2497f1f53518f1151f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2836c1149e06b2497f1f53518f1151f2">GPIO_AFRL_AFSEL7_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga2836c1149e06b2497f1f53518f1151f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3248acbb1bea59926db7edb98a245b0" id="r_gab3248acbb1bea59926db7edb98a245b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3248acbb1bea59926db7edb98a245b0">GPIO_AFRL_AFSEL7_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2836c1149e06b2497f1f53518f1151f2">GPIO_AFRL_AFSEL7_Pos</a>)</td></tr>
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<tr class="separator:gab3248acbb1bea59926db7edb98a245b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0128026ab2c8ed18da456aaf82827e11" id="r_ga0128026ab2c8ed18da456aaf82827e11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0128026ab2c8ed18da456aaf82827e11">GPIO_AFRL_AFSEL7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab3248acbb1bea59926db7edb98a245b0">GPIO_AFRL_AFSEL7_Msk</a></td></tr>
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<tr class="memitem:ga35641566dd5e2c3483d8ac494ff9e50d" id="r_ga35641566dd5e2c3483d8ac494ff9e50d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35641566dd5e2c3483d8ac494ff9e50d">GPIO_AFRL_AFSEL7_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2836c1149e06b2497f1f53518f1151f2">GPIO_AFRL_AFSEL7_Pos</a>)</td></tr>
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<tr class="memitem:ga6a155fcc736492a694dac6b25c803f85" id="r_ga6a155fcc736492a694dac6b25c803f85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a155fcc736492a694dac6b25c803f85">GPIO_AFRL_AFSEL7_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2836c1149e06b2497f1f53518f1151f2">GPIO_AFRL_AFSEL7_Pos</a>)</td></tr>
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<tr class="memitem:ga31a4fdc80b155797db598779ae7a242f" id="r_ga31a4fdc80b155797db598779ae7a242f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31a4fdc80b155797db598779ae7a242f">GPIO_AFRL_AFSEL7_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2836c1149e06b2497f1f53518f1151f2">GPIO_AFRL_AFSEL7_Pos</a>)</td></tr>
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<tr class="memitem:gac11328845c720331b1d6a12003b3f4d3" id="r_gac11328845c720331b1d6a12003b3f4d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac11328845c720331b1d6a12003b3f4d3">GPIO_AFRL_AFSEL7_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2836c1149e06b2497f1f53518f1151f2">GPIO_AFRL_AFSEL7_Pos</a>)</td></tr>
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<tr class="memitem:gaf4af89daf61c25562733d281e9acde3d" id="r_gaf4af89daf61c25562733d281e9acde3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4af89daf61c25562733d281e9acde3d">GPIO_AFRL_AFRL0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ec251e186471ae09aeb3cb0aa788594">GPIO_AFRL_AFSEL0</a></td></tr>
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<tr class="separator:gaf4af89daf61c25562733d281e9acde3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3f152d808e8aa43362b108b1160c128" id="r_gac3f152d808e8aa43362b108b1160c128"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3f152d808e8aa43362b108b1160c128">GPIO_AFRL_AFRL0_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d64770b98ab6db5eee36068d6e0c45a">GPIO_AFRL_AFSEL0_0</a></td></tr>
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<tr class="memitem:gabd77c2da1b416d80c239a024c8e4ef61" id="r_gabd77c2da1b416d80c239a024c8e4ef61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd77c2da1b416d80c239a024c8e4ef61">GPIO_AFRL_AFRL0_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaabf16f4a3f9458d9576accc1695bed4a">GPIO_AFRL_AFSEL0_1</a></td></tr>
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<tr class="separator:gabd77c2da1b416d80c239a024c8e4ef61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga693446d17258b95fafb2685a5fe868ab" id="r_ga693446d17258b95fafb2685a5fe868ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga693446d17258b95fafb2685a5fe868ab">GPIO_AFRL_AFRL0_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab872e44f9df01f18e4f78cee45d5cf43">GPIO_AFRL_AFSEL0_2</a></td></tr>
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<tr class="memitem:gac17d2fbadcaab82ce79836839278642c" id="r_gac17d2fbadcaab82ce79836839278642c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac17d2fbadcaab82ce79836839278642c">GPIO_AFRL_AFRL0_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a83a0eb943535ea970419f7bb87fa52">GPIO_AFRL_AFSEL0_3</a></td></tr>
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<tr class="separator:gac17d2fbadcaab82ce79836839278642c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga122cbed720d27776f0cfa6dab1fbc84c" id="r_ga122cbed720d27776f0cfa6dab1fbc84c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga122cbed720d27776f0cfa6dab1fbc84c">GPIO_AFRL_AFRL1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9fbd174222a013c9a0e222fdd0888de2">GPIO_AFRL_AFSEL1</a></td></tr>
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<tr class="memitem:ga9f2f94b9a8f50f296dd0a20b110b2e93" id="r_ga9f2f94b9a8f50f296dd0a20b110b2e93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f2f94b9a8f50f296dd0a20b110b2e93">GPIO_AFRL_AFRL1_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae6834a1a64ce4c42bd71cdb0bc685f06">GPIO_AFRL_AFSEL1_0</a></td></tr>
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<tr class="separator:ga9f2f94b9a8f50f296dd0a20b110b2e93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf34ee437f14787a7bc240b13469f8d02" id="r_gaf34ee437f14787a7bc240b13469f8d02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf34ee437f14787a7bc240b13469f8d02">GPIO_AFRL_AFRL1_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4f1e8fe3cf48f2dcdd6cd96c88b5754">GPIO_AFRL_AFSEL1_1</a></td></tr>
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<tr class="separator:gaf34ee437f14787a7bc240b13469f8d02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b9d92f139b6f523c8ece0582caa9205" id="r_ga3b9d92f139b6f523c8ece0582caa9205"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b9d92f139b6f523c8ece0582caa9205">GPIO_AFRL_AFRL1_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac38c620ad920142f38db8ef78674df56">GPIO_AFRL_AFSEL1_2</a></td></tr>
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<tr class="separator:ga3b9d92f139b6f523c8ece0582caa9205"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga385ae9713490b8a47c63fb3f1d92eecf" id="r_ga385ae9713490b8a47c63fb3f1d92eecf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga385ae9713490b8a47c63fb3f1d92eecf">GPIO_AFRL_AFRL1_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ee3c6fd5280247ff5cb1e4c139ab85d">GPIO_AFRL_AFSEL1_3</a></td></tr>
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<tr class="separator:ga385ae9713490b8a47c63fb3f1d92eecf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafda8ce333741832561e1e3e76abcee7a" id="r_gafda8ce333741832561e1e3e76abcee7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafda8ce333741832561e1e3e76abcee7a">GPIO_AFRL_AFRL2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9bc63205b8a09bd2ae7fb066058f3da">GPIO_AFRL_AFSEL2</a></td></tr>
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<tr class="separator:gafda8ce333741832561e1e3e76abcee7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ae4ecfdc6739da7658d5618f949b4f0" id="r_ga3ae4ecfdc6739da7658d5618f949b4f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ae4ecfdc6739da7658d5618f949b4f0">GPIO_AFRL_AFRL2_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga566eef02569b14ba89745698e4c7f4cb">GPIO_AFRL_AFSEL2_0</a></td></tr>
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<tr class="separator:ga3ae4ecfdc6739da7658d5618f949b4f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6105e47f03d5c714f52753c721848e2" id="r_gae6105e47f03d5c714f52753c721848e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6105e47f03d5c714f52753c721848e2">GPIO_AFRL_AFRL2_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga99704f0bd6543a391b934faae9f86c0e">GPIO_AFRL_AFSEL2_1</a></td></tr>
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<tr class="separator:gae6105e47f03d5c714f52753c721848e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d392ca99cf444404f329d5419febb1d" id="r_ga2d392ca99cf444404f329d5419febb1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d392ca99cf444404f329d5419febb1d">GPIO_AFRL_AFRL2_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e90655a95edd288bda4552137310e7c">GPIO_AFRL_AFSEL2_2</a></td></tr>
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<tr class="separator:ga2d392ca99cf444404f329d5419febb1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08baef06281ebf48156f43cd6727bd7f" id="r_ga08baef06281ebf48156f43cd6727bd7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08baef06281ebf48156f43cd6727bd7f">GPIO_AFRL_AFRL2_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a2b8fe31b1620d99caaa0d5b00214fc">GPIO_AFRL_AFSEL2_3</a></td></tr>
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<tr class="separator:ga08baef06281ebf48156f43cd6727bd7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee969704e28b7b0159838a8aec5f1e65" id="r_gaee969704e28b7b0159838a8aec5f1e65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee969704e28b7b0159838a8aec5f1e65">GPIO_AFRL_AFRL3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae0fb36c07eac3809b6a5baaee74ee426">GPIO_AFRL_AFSEL3</a></td></tr>
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<tr class="separator:gaee969704e28b7b0159838a8aec5f1e65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95865001c230cb9d6794a1a8faa53464" id="r_ga95865001c230cb9d6794a1a8faa53464"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95865001c230cb9d6794a1a8faa53464">GPIO_AFRL_AFRL3_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0eb39bec095e2b4661141b20c1bd80d">GPIO_AFRL_AFSEL3_0</a></td></tr>
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<tr class="separator:ga95865001c230cb9d6794a1a8faa53464"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8669f979e8cde27c80e8b33fb5cc4f96" id="r_ga8669f979e8cde27c80e8b33fb5cc4f96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8669f979e8cde27c80e8b33fb5cc4f96">GPIO_AFRL_AFRL3_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97101a6c182091257d9a86f38bbf8015">GPIO_AFRL_AFSEL3_1</a></td></tr>
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<tr class="separator:ga8669f979e8cde27c80e8b33fb5cc4f96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c4a49fa8bb4a4e2cd8613be0fe8a4e3" id="r_ga6c4a49fa8bb4a4e2cd8613be0fe8a4e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c4a49fa8bb4a4e2cd8613be0fe8a4e3">GPIO_AFRL_AFRL3_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf97dd08bfd9439ae9a8be2aae31572ab">GPIO_AFRL_AFSEL3_2</a></td></tr>
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<tr class="separator:ga6c4a49fa8bb4a4e2cd8613be0fe8a4e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14278231a30cffd346762047a69f4cc2" id="r_ga14278231a30cffd346762047a69f4cc2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14278231a30cffd346762047a69f4cc2">GPIO_AFRL_AFRL3_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga640b17198ae3a4dca834c93941bb459e">GPIO_AFRL_AFSEL3_3</a></td></tr>
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<tr class="separator:ga14278231a30cffd346762047a69f4cc2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac862d4f115fd881871356418943a4446" id="r_gac862d4f115fd881871356418943a4446"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac862d4f115fd881871356418943a4446">GPIO_AFRL_AFRL4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga728e20cadadaa3c5aa1c42c25356a9f4">GPIO_AFRL_AFSEL4</a></td></tr>
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<tr class="separator:gac862d4f115fd881871356418943a4446"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2138d6628f63ceff1b9340fe143e4309" id="r_ga2138d6628f63ceff1b9340fe143e4309"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2138d6628f63ceff1b9340fe143e4309">GPIO_AFRL_AFRL4_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga958dcb0150574251c77490397469d443">GPIO_AFRL_AFSEL4_0</a></td></tr>
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<tr class="separator:ga2138d6628f63ceff1b9340fe143e4309"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa691f7acdc66a2d79e128264a7bd1a63" id="r_gaa691f7acdc66a2d79e128264a7bd1a63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa691f7acdc66a2d79e128264a7bd1a63">GPIO_AFRL_AFRL4_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga89f30587f699e9b28347b41b1752d846">GPIO_AFRL_AFSEL4_1</a></td></tr>
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<tr class="separator:gaa691f7acdc66a2d79e128264a7bd1a63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b2c314441cd3d4841bdb1e3d5de9db5" id="r_ga6b2c314441cd3d4841bdb1e3d5de9db5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b2c314441cd3d4841bdb1e3d5de9db5">GPIO_AFRL_AFRL4_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafeb379dcb35516d7744e8a7467aa9ddf">GPIO_AFRL_AFSEL4_2</a></td></tr>
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<tr class="separator:ga6b2c314441cd3d4841bdb1e3d5de9db5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacab260848c23e7b1ea2777f0e4a40fc1" id="r_gacab260848c23e7b1ea2777f0e4a40fc1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacab260848c23e7b1ea2777f0e4a40fc1">GPIO_AFRL_AFRL4_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c7a684490eaf01f5e1bd29f89bebfb8">GPIO_AFRL_AFSEL4_3</a></td></tr>
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<tr class="separator:gacab260848c23e7b1ea2777f0e4a40fc1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga481f4065077c16365632e6a647cdcb4e" id="r_ga481f4065077c16365632e6a647cdcb4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga481f4065077c16365632e6a647cdcb4e">GPIO_AFRL_AFRL5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad158052aa17b4bf12f9ad20b6e0c6d0c">GPIO_AFRL_AFSEL5</a></td></tr>
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<tr class="separator:ga481f4065077c16365632e6a647cdcb4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe45d3ec4c0a71d968112e7a65b5510d" id="r_gabe45d3ec4c0a71d968112e7a65b5510d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe45d3ec4c0a71d968112e7a65b5510d">GPIO_AFRL_AFRL5_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4fba4a0c264295148200fdbea3645efb">GPIO_AFRL_AFSEL5_0</a></td></tr>
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<tr class="separator:gabe45d3ec4c0a71d968112e7a65b5510d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6372195804d3e61723030fb0d9a2268f" id="r_ga6372195804d3e61723030fb0d9a2268f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6372195804d3e61723030fb0d9a2268f">GPIO_AFRL_AFRL5_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf532421a6d6665eb9dd82752aa71bda6">GPIO_AFRL_AFSEL5_1</a></td></tr>
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<tr class="memitem:gaf383c494976eda7fad4006b937a6f359" id="r_gaf383c494976eda7fad4006b937a6f359"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf383c494976eda7fad4006b937a6f359">GPIO_AFRL_AFRL5_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga600caf3a081a223a0c9bbd22c1d65fd7">GPIO_AFRL_AFSEL5_2</a></td></tr>
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<tr class="memitem:ga01dfdf9aa650eb4d3c06c6f7a4e79e44" id="r_ga01dfdf9aa650eb4d3c06c6f7a4e79e44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01dfdf9aa650eb4d3c06c6f7a4e79e44">GPIO_AFRL_AFRL5_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cf281224f66730f522948ce2f16a9dc">GPIO_AFRL_AFSEL5_3</a></td></tr>
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<tr class="memitem:gac87a55d05f6d16cbfbce6e04a2c6888e" id="r_gac87a55d05f6d16cbfbce6e04a2c6888e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac87a55d05f6d16cbfbce6e04a2c6888e">GPIO_AFRL_AFRL6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga893c83ab521d1bf15e71b20309d71503">GPIO_AFRL_AFSEL6</a></td></tr>
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<tr class="memitem:gaa94adf1532fc4188a926ba7d366cc13e" id="r_gaa94adf1532fc4188a926ba7d366cc13e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa94adf1532fc4188a926ba7d366cc13e">GPIO_AFRL_AFRL6_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae4eb2b4e77d1338ae80e889bb7f98159">GPIO_AFRL_AFSEL6_0</a></td></tr>
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<tr class="memitem:ga1f5289d6b05cf1ed7959b89dfb4e64a0" id="r_ga1f5289d6b05cf1ed7959b89dfb4e64a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f5289d6b05cf1ed7959b89dfb4e64a0">GPIO_AFRL_AFRL6_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga87ae4b89cf40e01fc3d0c1cca38db1de">GPIO_AFRL_AFSEL6_1</a></td></tr>
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<tr class="memitem:gaaf8dff68b61d57bf6cbe6f22d76c5629" id="r_gaaf8dff68b61d57bf6cbe6f22d76c5629"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf8dff68b61d57bf6cbe6f22d76c5629">GPIO_AFRL_AFRL6_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gace077c57cb72736ef5dca98052403b72">GPIO_AFRL_AFSEL6_2</a></td></tr>
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<tr class="memitem:gaf05b72714d2577958fa5c2b5e871d223" id="r_gaf05b72714d2577958fa5c2b5e871d223"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf05b72714d2577958fa5c2b5e871d223">GPIO_AFRL_AFRL6_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b1fee857fd7d1b412ed64b1c6572280">GPIO_AFRL_AFSEL6_3</a></td></tr>
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<tr class="memitem:ga97a41237468859702de7ea91dad62ed8" id="r_ga97a41237468859702de7ea91dad62ed8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97a41237468859702de7ea91dad62ed8">GPIO_AFRL_AFRL7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0128026ab2c8ed18da456aaf82827e11">GPIO_AFRL_AFSEL7</a></td></tr>
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<tr class="memitem:ga292b5b0e56572245d5c5d72fcdada9fa" id="r_ga292b5b0e56572245d5c5d72fcdada9fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga292b5b0e56572245d5c5d72fcdada9fa">GPIO_AFRL_AFRL7_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga35641566dd5e2c3483d8ac494ff9e50d">GPIO_AFRL_AFSEL7_0</a></td></tr>
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<tr class="separator:ga292b5b0e56572245d5c5d72fcdada9fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d5348d823ed82075ed48b74a36c9db2" id="r_ga6d5348d823ed82075ed48b74a36c9db2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d5348d823ed82075ed48b74a36c9db2">GPIO_AFRL_AFRL7_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a155fcc736492a694dac6b25c803f85">GPIO_AFRL_AFSEL7_1</a></td></tr>
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<tr class="separator:ga6d5348d823ed82075ed48b74a36c9db2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf28527531ac7958b1de74f0883a53334" id="r_gaf28527531ac7958b1de74f0883a53334"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf28527531ac7958b1de74f0883a53334">GPIO_AFRL_AFRL7_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31a4fdc80b155797db598779ae7a242f">GPIO_AFRL_AFSEL7_2</a></td></tr>
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<tr class="memitem:ga1adb4a490f9b5c323dba6e591f4131f6" id="r_ga1adb4a490f9b5c323dba6e591f4131f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1adb4a490f9b5c323dba6e591f4131f6">GPIO_AFRL_AFRL7_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac11328845c720331b1d6a12003b3f4d3">GPIO_AFRL_AFSEL7_3</a></td></tr>
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<tr class="memitem:ga2cdfdbcb5332d98e0202f4f86480736f" id="r_ga2cdfdbcb5332d98e0202f4f86480736f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdfdbcb5332d98e0202f4f86480736f">GPIO_AFRH_AFSEL8_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga5be819e7ca1f69e2d5f6d63aaee056c2" id="r_ga5be819e7ca1f69e2d5f6d63aaee056c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5be819e7ca1f69e2d5f6d63aaee056c2">GPIO_AFRH_AFSEL8_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdfdbcb5332d98e0202f4f86480736f">GPIO_AFRH_AFSEL8_Pos</a>)</td></tr>
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<tr class="separator:ga5be819e7ca1f69e2d5f6d63aaee056c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ed3881740613378329271150088f1b2" id="r_ga6ed3881740613378329271150088f1b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ed3881740613378329271150088f1b2">GPIO_AFRH_AFSEL8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5be819e7ca1f69e2d5f6d63aaee056c2">GPIO_AFRH_AFSEL8_Msk</a></td></tr>
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<tr class="separator:ga6ed3881740613378329271150088f1b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72cc5ca956395dbb409019f45601727d" id="r_ga72cc5ca956395dbb409019f45601727d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72cc5ca956395dbb409019f45601727d">GPIO_AFRH_AFSEL8_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdfdbcb5332d98e0202f4f86480736f">GPIO_AFRH_AFSEL8_Pos</a>)</td></tr>
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<tr class="memitem:ga23cb04d03ed3fc80a827dd4fcd092e92" id="r_ga23cb04d03ed3fc80a827dd4fcd092e92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23cb04d03ed3fc80a827dd4fcd092e92">GPIO_AFRH_AFSEL8_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdfdbcb5332d98e0202f4f86480736f">GPIO_AFRH_AFSEL8_Pos</a>)</td></tr>
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<tr class="separator:ga23cb04d03ed3fc80a827dd4fcd092e92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0d2ccbadd52c0de148593218c735ed3" id="r_gaf0d2ccbadd52c0de148593218c735ed3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0d2ccbadd52c0de148593218c735ed3">GPIO_AFRH_AFSEL8_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdfdbcb5332d98e0202f4f86480736f">GPIO_AFRH_AFSEL8_Pos</a>)</td></tr>
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<tr class="separator:gaf0d2ccbadd52c0de148593218c735ed3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd9fc9adc13e5e90df54b8885522f98e" id="r_gabd9fc9adc13e5e90df54b8885522f98e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd9fc9adc13e5e90df54b8885522f98e">GPIO_AFRH_AFSEL8_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cdfdbcb5332d98e0202f4f86480736f">GPIO_AFRH_AFSEL8_Pos</a>)</td></tr>
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<tr class="memitem:gae9aeed0c87696c3a98e7e4fc3dc6dc80" id="r_gae9aeed0c87696c3a98e7e4fc3dc6dc80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9aeed0c87696c3a98e7e4fc3dc6dc80">GPIO_AFRH_AFSEL9_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae9aeed0c87696c3a98e7e4fc3dc6dc80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb779906c49372a9c0d7c8eaf7face71" id="r_gafb779906c49372a9c0d7c8eaf7face71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb779906c49372a9c0d7c8eaf7face71">GPIO_AFRH_AFSEL9_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9aeed0c87696c3a98e7e4fc3dc6dc80">GPIO_AFRH_AFSEL9_Pos</a>)</td></tr>
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<tr class="separator:gafb779906c49372a9c0d7c8eaf7face71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacff5a20b7c9f10be43364ff422bb40ef" id="r_gacff5a20b7c9f10be43364ff422bb40ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacff5a20b7c9f10be43364ff422bb40ef">GPIO_AFRH_AFSEL9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb779906c49372a9c0d7c8eaf7face71">GPIO_AFRH_AFSEL9_Msk</a></td></tr>
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<tr class="separator:gacff5a20b7c9f10be43364ff422bb40ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44f61f3cb607268196179fa0a28b051e" id="r_ga44f61f3cb607268196179fa0a28b051e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44f61f3cb607268196179fa0a28b051e">GPIO_AFRH_AFSEL9_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9aeed0c87696c3a98e7e4fc3dc6dc80">GPIO_AFRH_AFSEL9_Pos</a>)</td></tr>
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<tr class="separator:ga44f61f3cb607268196179fa0a28b051e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6093967302f540000072f05d3e64bf6f" id="r_ga6093967302f540000072f05d3e64bf6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6093967302f540000072f05d3e64bf6f">GPIO_AFRH_AFSEL9_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9aeed0c87696c3a98e7e4fc3dc6dc80">GPIO_AFRH_AFSEL9_Pos</a>)</td></tr>
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<tr class="memitem:gaa7d91556fe4f170bbd818e6d88f5bc56" id="r_gaa7d91556fe4f170bbd818e6d88f5bc56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7d91556fe4f170bbd818e6d88f5bc56">GPIO_AFRH_AFSEL9_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9aeed0c87696c3a98e7e4fc3dc6dc80">GPIO_AFRH_AFSEL9_Pos</a>)</td></tr>
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<tr class="separator:gaa7d91556fe4f170bbd818e6d88f5bc56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab68b3750a95f3627dea9867fb5cf4689" id="r_gab68b3750a95f3627dea9867fb5cf4689"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab68b3750a95f3627dea9867fb5cf4689">GPIO_AFRH_AFSEL9_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9aeed0c87696c3a98e7e4fc3dc6dc80">GPIO_AFRH_AFSEL9_Pos</a>)</td></tr>
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<tr class="separator:gab68b3750a95f3627dea9867fb5cf4689"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga334f2ca0e5684d230cb7788969997f07" id="r_ga334f2ca0e5684d230cb7788969997f07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga334f2ca0e5684d230cb7788969997f07">GPIO_AFRH_AFSEL10_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga334f2ca0e5684d230cb7788969997f07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33b875b9713ed4640e400fcf126cf105" id="r_ga33b875b9713ed4640e400fcf126cf105"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33b875b9713ed4640e400fcf126cf105">GPIO_AFRH_AFSEL10_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga334f2ca0e5684d230cb7788969997f07">GPIO_AFRH_AFSEL10_Pos</a>)</td></tr>
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<tr class="separator:ga33b875b9713ed4640e400fcf126cf105"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c41926ac3fc6ec0fb8def28275bbe30" id="r_ga9c41926ac3fc6ec0fb8def28275bbe30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c41926ac3fc6ec0fb8def28275bbe30">GPIO_AFRH_AFSEL10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga33b875b9713ed4640e400fcf126cf105">GPIO_AFRH_AFSEL10_Msk</a></td></tr>
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<tr class="memitem:ga6d9771de8ec013027f8f26d799e7a3fe" id="r_ga6d9771de8ec013027f8f26d799e7a3fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d9771de8ec013027f8f26d799e7a3fe">GPIO_AFRH_AFSEL10_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga334f2ca0e5684d230cb7788969997f07">GPIO_AFRH_AFSEL10_Pos</a>)</td></tr>
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<tr class="separator:ga6d9771de8ec013027f8f26d799e7a3fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8f7170c263301f7b7c55dcdf1acb832" id="r_gad8f7170c263301f7b7c55dcdf1acb832"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8f7170c263301f7b7c55dcdf1acb832">GPIO_AFRH_AFSEL10_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga334f2ca0e5684d230cb7788969997f07">GPIO_AFRH_AFSEL10_Pos</a>)</td></tr>
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<tr class="memitem:gaf0b280a9f8a751dcb4a27cf2e9a73598" id="r_gaf0b280a9f8a751dcb4a27cf2e9a73598"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0b280a9f8a751dcb4a27cf2e9a73598">GPIO_AFRH_AFSEL10_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga334f2ca0e5684d230cb7788969997f07">GPIO_AFRH_AFSEL10_Pos</a>)</td></tr>
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<tr class="memitem:gacc1431b847bccbc8841d8ab9a6aa36e5" id="r_gacc1431b847bccbc8841d8ab9a6aa36e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc1431b847bccbc8841d8ab9a6aa36e5">GPIO_AFRH_AFSEL10_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga334f2ca0e5684d230cb7788969997f07">GPIO_AFRH_AFSEL10_Pos</a>)</td></tr>
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<tr class="memitem:ga9f655e646b26d49e38053d9ee9cc064b" id="r_ga9f655e646b26d49e38053d9ee9cc064b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f655e646b26d49e38053d9ee9cc064b">GPIO_AFRH_AFSEL11_Pos</a>   (12U)</td></tr>
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<tr class="memitem:ga76888c8d8080e47339e0fd2e69ab42d8" id="r_ga76888c8d8080e47339e0fd2e69ab42d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76888c8d8080e47339e0fd2e69ab42d8">GPIO_AFRH_AFSEL11_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f655e646b26d49e38053d9ee9cc064b">GPIO_AFRH_AFSEL11_Pos</a>)</td></tr>
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<tr class="separator:ga76888c8d8080e47339e0fd2e69ab42d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47a97a35b9f12ef795aa1ebb3d85c3aa" id="r_ga47a97a35b9f12ef795aa1ebb3d85c3aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47a97a35b9f12ef795aa1ebb3d85c3aa">GPIO_AFRH_AFSEL11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga76888c8d8080e47339e0fd2e69ab42d8">GPIO_AFRH_AFSEL11_Msk</a></td></tr>
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<tr class="separator:ga47a97a35b9f12ef795aa1ebb3d85c3aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga711beadb293e4ef285bb813b2e9feb6d" id="r_ga711beadb293e4ef285bb813b2e9feb6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga711beadb293e4ef285bb813b2e9feb6d">GPIO_AFRH_AFSEL11_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f655e646b26d49e38053d9ee9cc064b">GPIO_AFRH_AFSEL11_Pos</a>)</td></tr>
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<tr class="memitem:ga8ad64e530b4cf96c745f69ac97d23195" id="r_ga8ad64e530b4cf96c745f69ac97d23195"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ad64e530b4cf96c745f69ac97d23195">GPIO_AFRH_AFSEL11_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f655e646b26d49e38053d9ee9cc064b">GPIO_AFRH_AFSEL11_Pos</a>)</td></tr>
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<tr class="memitem:ga3ffb839fbc0a35b148f17363553f6647" id="r_ga3ffb839fbc0a35b148f17363553f6647"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ffb839fbc0a35b148f17363553f6647">GPIO_AFRH_AFSEL11_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f655e646b26d49e38053d9ee9cc064b">GPIO_AFRH_AFSEL11_Pos</a>)</td></tr>
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<tr class="memitem:ga570aa5e92e75568945191853f0196321" id="r_ga570aa5e92e75568945191853f0196321"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga570aa5e92e75568945191853f0196321">GPIO_AFRH_AFSEL11_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f655e646b26d49e38053d9ee9cc064b">GPIO_AFRH_AFSEL11_Pos</a>)</td></tr>
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<tr class="memitem:ga0dce1ce501e0b3b5e5e4b4961f7afda3" id="r_ga0dce1ce501e0b3b5e5e4b4961f7afda3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dce1ce501e0b3b5e5e4b4961f7afda3">GPIO_AFRH_AFSEL12_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga0dce1ce501e0b3b5e5e4b4961f7afda3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae162137694aa110fb89b9afeea1c648f" id="r_gae162137694aa110fb89b9afeea1c648f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae162137694aa110fb89b9afeea1c648f">GPIO_AFRH_AFSEL12_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dce1ce501e0b3b5e5e4b4961f7afda3">GPIO_AFRH_AFSEL12_Pos</a>)</td></tr>
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<tr class="separator:gae162137694aa110fb89b9afeea1c648f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c12c0939e7fcc354e37d55b74afb351" id="r_ga0c12c0939e7fcc354e37d55b74afb351"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c12c0939e7fcc354e37d55b74afb351">GPIO_AFRH_AFSEL12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae162137694aa110fb89b9afeea1c648f">GPIO_AFRH_AFSEL12_Msk</a></td></tr>
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<tr class="separator:ga0c12c0939e7fcc354e37d55b74afb351"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffe1b4dcd4e796a2e145df206f35d6ea" id="r_gaffe1b4dcd4e796a2e145df206f35d6ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffe1b4dcd4e796a2e145df206f35d6ea">GPIO_AFRH_AFSEL12_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dce1ce501e0b3b5e5e4b4961f7afda3">GPIO_AFRH_AFSEL12_Pos</a>)</td></tr>
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<tr class="separator:gaffe1b4dcd4e796a2e145df206f35d6ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac5933c2c73fec3d2f3c41d32fb64bfa" id="r_gaac5933c2c73fec3d2f3c41d32fb64bfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac5933c2c73fec3d2f3c41d32fb64bfa">GPIO_AFRH_AFSEL12_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dce1ce501e0b3b5e5e4b4961f7afda3">GPIO_AFRH_AFSEL12_Pos</a>)</td></tr>
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<tr class="separator:gaac5933c2c73fec3d2f3c41d32fb64bfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ed0f0c148e3c52bf041ab53af1d88bf" id="r_ga3ed0f0c148e3c52bf041ab53af1d88bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ed0f0c148e3c52bf041ab53af1d88bf">GPIO_AFRH_AFSEL12_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dce1ce501e0b3b5e5e4b4961f7afda3">GPIO_AFRH_AFSEL12_Pos</a>)</td></tr>
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<tr class="separator:ga3ed0f0c148e3c52bf041ab53af1d88bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbd6cfac7c23742a6e1fe120adfe3183" id="r_gacbd6cfac7c23742a6e1fe120adfe3183"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbd6cfac7c23742a6e1fe120adfe3183">GPIO_AFRH_AFSEL12_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dce1ce501e0b3b5e5e4b4961f7afda3">GPIO_AFRH_AFSEL12_Pos</a>)</td></tr>
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<tr class="separator:gacbd6cfac7c23742a6e1fe120adfe3183"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65b195db19c1ca62ef95eed10c649180" id="r_ga65b195db19c1ca62ef95eed10c649180"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65b195db19c1ca62ef95eed10c649180">GPIO_AFRH_AFSEL13_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga65b195db19c1ca62ef95eed10c649180"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc533ac377beb113777896f0deb0ef91" id="r_gacc533ac377beb113777896f0deb0ef91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc533ac377beb113777896f0deb0ef91">GPIO_AFRH_AFSEL13_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga65b195db19c1ca62ef95eed10c649180">GPIO_AFRH_AFSEL13_Pos</a>)</td></tr>
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<tr class="separator:gacc533ac377beb113777896f0deb0ef91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60e9a3a49cdad6cd65d377fb675185da" id="r_ga60e9a3a49cdad6cd65d377fb675185da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60e9a3a49cdad6cd65d377fb675185da">GPIO_AFRH_AFSEL13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacc533ac377beb113777896f0deb0ef91">GPIO_AFRH_AFSEL13_Msk</a></td></tr>
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<tr class="separator:ga60e9a3a49cdad6cd65d377fb675185da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab74ce92f856d5f687b069166f211ecaf" id="r_gab74ce92f856d5f687b069166f211ecaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab74ce92f856d5f687b069166f211ecaf">GPIO_AFRH_AFSEL13_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga65b195db19c1ca62ef95eed10c649180">GPIO_AFRH_AFSEL13_Pos</a>)</td></tr>
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<tr class="separator:gab74ce92f856d5f687b069166f211ecaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d2985f042e79fb320b402a6e1c425f7" id="r_ga1d2985f042e79fb320b402a6e1c425f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d2985f042e79fb320b402a6e1c425f7">GPIO_AFRH_AFSEL13_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga65b195db19c1ca62ef95eed10c649180">GPIO_AFRH_AFSEL13_Pos</a>)</td></tr>
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<tr class="separator:ga1d2985f042e79fb320b402a6e1c425f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59cb8d2b8ca336c6c169c0e1a07cb2eb" id="r_ga59cb8d2b8ca336c6c169c0e1a07cb2eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59cb8d2b8ca336c6c169c0e1a07cb2eb">GPIO_AFRH_AFSEL13_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga65b195db19c1ca62ef95eed10c649180">GPIO_AFRH_AFSEL13_Pos</a>)</td></tr>
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<tr class="separator:ga59cb8d2b8ca336c6c169c0e1a07cb2eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2ff66c2036fd651e7ae366db237b76c" id="r_gac2ff66c2036fd651e7ae366db237b76c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2ff66c2036fd651e7ae366db237b76c">GPIO_AFRH_AFSEL13_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga65b195db19c1ca62ef95eed10c649180">GPIO_AFRH_AFSEL13_Pos</a>)</td></tr>
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<tr class="separator:gac2ff66c2036fd651e7ae366db237b76c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7fcd5b907f7ca9538dffe1aeb00d7942" id="r_ga7fcd5b907f7ca9538dffe1aeb00d7942"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fcd5b907f7ca9538dffe1aeb00d7942">GPIO_AFRH_AFSEL14_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga7fcd5b907f7ca9538dffe1aeb00d7942"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae997df2b0bb50f310e7fd17df043e8e8" id="r_gae997df2b0bb50f310e7fd17df043e8e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae997df2b0bb50f310e7fd17df043e8e8">GPIO_AFRH_AFSEL14_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7fcd5b907f7ca9538dffe1aeb00d7942">GPIO_AFRH_AFSEL14_Pos</a>)</td></tr>
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<tr class="separator:gae997df2b0bb50f310e7fd17df043e8e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3d930c6c5ffa92e461a0190be4bff78" id="r_gae3d930c6c5ffa92e461a0190be4bff78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3d930c6c5ffa92e461a0190be4bff78">GPIO_AFRH_AFSEL14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae997df2b0bb50f310e7fd17df043e8e8">GPIO_AFRH_AFSEL14_Msk</a></td></tr>
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<tr class="separator:gae3d930c6c5ffa92e461a0190be4bff78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf5b6ebd9c3a8039b46748dcbd3eda99" id="r_gacf5b6ebd9c3a8039b46748dcbd3eda99"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf5b6ebd9c3a8039b46748dcbd3eda99">GPIO_AFRH_AFSEL14_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7fcd5b907f7ca9538dffe1aeb00d7942">GPIO_AFRH_AFSEL14_Pos</a>)</td></tr>
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<tr class="separator:gacf5b6ebd9c3a8039b46748dcbd3eda99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21985995f6f22d63ba1170ee629bcf02" id="r_ga21985995f6f22d63ba1170ee629bcf02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21985995f6f22d63ba1170ee629bcf02">GPIO_AFRH_AFSEL14_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7fcd5b907f7ca9538dffe1aeb00d7942">GPIO_AFRH_AFSEL14_Pos</a>)</td></tr>
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<tr class="separator:ga21985995f6f22d63ba1170ee629bcf02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c98e75f198a3d84038029711c3f299f" id="r_ga0c98e75f198a3d84038029711c3f299f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c98e75f198a3d84038029711c3f299f">GPIO_AFRH_AFSEL14_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7fcd5b907f7ca9538dffe1aeb00d7942">GPIO_AFRH_AFSEL14_Pos</a>)</td></tr>
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<tr class="separator:ga0c98e75f198a3d84038029711c3f299f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41d1c1c7ac6886975bca9cc8ef57c73d" id="r_ga41d1c1c7ac6886975bca9cc8ef57c73d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41d1c1c7ac6886975bca9cc8ef57c73d">GPIO_AFRH_AFSEL14_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7fcd5b907f7ca9538dffe1aeb00d7942">GPIO_AFRH_AFSEL14_Pos</a>)</td></tr>
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<tr class="separator:ga41d1c1c7ac6886975bca9cc8ef57c73d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a0ed32e0f197da7ea8856a58cebdb46" id="r_ga0a0ed32e0f197da7ea8856a58cebdb46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a0ed32e0f197da7ea8856a58cebdb46">GPIO_AFRH_AFSEL15_Pos</a>   (28U)</td></tr>
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<tr class="memitem:gaf94ca202e9ee8d766a5ee7794dba95b6" id="r_gaf94ca202e9ee8d766a5ee7794dba95b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf94ca202e9ee8d766a5ee7794dba95b6">GPIO_AFRH_AFSEL15_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a0ed32e0f197da7ea8856a58cebdb46">GPIO_AFRH_AFSEL15_Pos</a>)</td></tr>
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<tr class="separator:gaf94ca202e9ee8d766a5ee7794dba95b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46417b0da710ef512ac4ceb95b3ab44a" id="r_ga46417b0da710ef512ac4ceb95b3ab44a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46417b0da710ef512ac4ceb95b3ab44a">GPIO_AFRH_AFSEL15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf94ca202e9ee8d766a5ee7794dba95b6">GPIO_AFRH_AFSEL15_Msk</a></td></tr>
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<tr class="separator:ga46417b0da710ef512ac4ceb95b3ab44a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga841bd65d5afd409fd7f2bf5f1e859348" id="r_ga841bd65d5afd409fd7f2bf5f1e859348"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga841bd65d5afd409fd7f2bf5f1e859348">GPIO_AFRH_AFSEL15_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a0ed32e0f197da7ea8856a58cebdb46">GPIO_AFRH_AFSEL15_Pos</a>)</td></tr>
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<tr class="separator:ga841bd65d5afd409fd7f2bf5f1e859348"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga233f1ae0a856a18e7b706093c80a6274" id="r_ga233f1ae0a856a18e7b706093c80a6274"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga233f1ae0a856a18e7b706093c80a6274">GPIO_AFRH_AFSEL15_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a0ed32e0f197da7ea8856a58cebdb46">GPIO_AFRH_AFSEL15_Pos</a>)</td></tr>
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<tr class="separator:ga233f1ae0a856a18e7b706093c80a6274"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadaae51ed82039c62ec075b42a192c861" id="r_gadaae51ed82039c62ec075b42a192c861"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadaae51ed82039c62ec075b42a192c861">GPIO_AFRH_AFSEL15_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a0ed32e0f197da7ea8856a58cebdb46">GPIO_AFRH_AFSEL15_Pos</a>)</td></tr>
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<tr class="memitem:ga8699f7ff5369b8c20eaa32cfecbe7daf" id="r_ga8699f7ff5369b8c20eaa32cfecbe7daf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8699f7ff5369b8c20eaa32cfecbe7daf">GPIO_AFRH_AFSEL15_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a0ed32e0f197da7ea8856a58cebdb46">GPIO_AFRH_AFSEL15_Pos</a>)</td></tr>
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<tr class="separator:ga8699f7ff5369b8c20eaa32cfecbe7daf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc5bb516e3b29af807cf4772787dfd0d" id="r_gadc5bb516e3b29af807cf4772787dfd0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc5bb516e3b29af807cf4772787dfd0d">GPIO_AFRH_AFRH0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ed3881740613378329271150088f1b2">GPIO_AFRH_AFSEL8</a></td></tr>
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<tr class="memitem:ga696d2e7fbb6ae2b172f64f9edd5af9b0" id="r_ga696d2e7fbb6ae2b172f64f9edd5af9b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga696d2e7fbb6ae2b172f64f9edd5af9b0">GPIO_AFRH_AFRH0_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga72cc5ca956395dbb409019f45601727d">GPIO_AFRH_AFSEL8_0</a></td></tr>
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<tr class="separator:ga696d2e7fbb6ae2b172f64f9edd5af9b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21e5f36c2bf8a8977d72621d93876b0b" id="r_ga21e5f36c2bf8a8977d72621d93876b0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21e5f36c2bf8a8977d72621d93876b0b">GPIO_AFRH_AFRH0_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga23cb04d03ed3fc80a827dd4fcd092e92">GPIO_AFRH_AFSEL8_1</a></td></tr>
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<tr class="separator:ga21e5f36c2bf8a8977d72621d93876b0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40d8eb06b294389ac37efc69291182ec" id="r_ga40d8eb06b294389ac37efc69291182ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40d8eb06b294389ac37efc69291182ec">GPIO_AFRH_AFRH0_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0d2ccbadd52c0de148593218c735ed3">GPIO_AFRH_AFSEL8_2</a></td></tr>
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<tr class="separator:ga40d8eb06b294389ac37efc69291182ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa177428d840116200ec8e3645cfffbc7" id="r_gaa177428d840116200ec8e3645cfffbc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa177428d840116200ec8e3645cfffbc7">GPIO_AFRH_AFRH0_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd9fc9adc13e5e90df54b8885522f98e">GPIO_AFRH_AFSEL8_3</a></td></tr>
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<tr class="separator:gaa177428d840116200ec8e3645cfffbc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75ca2458aef597ebfcd1eb6b83035acd" id="r_ga75ca2458aef597ebfcd1eb6b83035acd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75ca2458aef597ebfcd1eb6b83035acd">GPIO_AFRH_AFRH1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacff5a20b7c9f10be43364ff422bb40ef">GPIO_AFRH_AFSEL9</a></td></tr>
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<tr class="separator:ga75ca2458aef597ebfcd1eb6b83035acd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5050213115941df4d89f1803ff3dce18" id="r_ga5050213115941df4d89f1803ff3dce18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5050213115941df4d89f1803ff3dce18">GPIO_AFRH_AFRH1_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44f61f3cb607268196179fa0a28b051e">GPIO_AFRH_AFSEL9_0</a></td></tr>
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<tr class="separator:ga5050213115941df4d89f1803ff3dce18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga413c97129e63fb91bdf0ac8220d9db00" id="r_ga413c97129e63fb91bdf0ac8220d9db00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga413c97129e63fb91bdf0ac8220d9db00">GPIO_AFRH_AFRH1_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6093967302f540000072f05d3e64bf6f">GPIO_AFRH_AFSEL9_1</a></td></tr>
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<tr class="separator:ga413c97129e63fb91bdf0ac8220d9db00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b89ccc6c477c0cd8ff857285df07d84" id="r_ga5b89ccc6c477c0cd8ff857285df07d84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b89ccc6c477c0cd8ff857285df07d84">GPIO_AFRH_AFRH1_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7d91556fe4f170bbd818e6d88f5bc56">GPIO_AFRH_AFSEL9_2</a></td></tr>
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<tr class="separator:ga5b89ccc6c477c0cd8ff857285df07d84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0ead68cbb1f4aadad0789e8d2bd32e4" id="r_gad0ead68cbb1f4aadad0789e8d2bd32e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0ead68cbb1f4aadad0789e8d2bd32e4">GPIO_AFRH_AFRH1_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab68b3750a95f3627dea9867fb5cf4689">GPIO_AFRH_AFSEL9_3</a></td></tr>
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<tr class="separator:gad0ead68cbb1f4aadad0789e8d2bd32e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dc39c907cd02befde4b7681b2fa070b" id="r_ga4dc39c907cd02befde4b7681b2fa070b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dc39c907cd02befde4b7681b2fa070b">GPIO_AFRH_AFRH2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c41926ac3fc6ec0fb8def28275bbe30">GPIO_AFRH_AFSEL10</a></td></tr>
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<tr class="separator:ga4dc39c907cd02befde4b7681b2fa070b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bc474910f7c3867c687e3d642dc7f86" id="r_ga3bc474910f7c3867c687e3d642dc7f86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bc474910f7c3867c687e3d642dc7f86">GPIO_AFRH_AFRH2_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d9771de8ec013027f8f26d799e7a3fe">GPIO_AFRH_AFSEL10_0</a></td></tr>
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<tr class="separator:ga3bc474910f7c3867c687e3d642dc7f86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6284f87ff50100a6c3e2cb496be1388a" id="r_ga6284f87ff50100a6c3e2cb496be1388a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6284f87ff50100a6c3e2cb496be1388a">GPIO_AFRH_AFRH2_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad8f7170c263301f7b7c55dcdf1acb832">GPIO_AFRH_AFSEL10_1</a></td></tr>
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<tr class="separator:ga6284f87ff50100a6c3e2cb496be1388a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa444f8755f374e202cb437a9f202f635" id="r_gaa444f8755f374e202cb437a9f202f635"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa444f8755f374e202cb437a9f202f635">GPIO_AFRH_AFRH2_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0b280a9f8a751dcb4a27cf2e9a73598">GPIO_AFRH_AFSEL10_2</a></td></tr>
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<tr class="separator:gaa444f8755f374e202cb437a9f202f635"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02b23ce670e6b5a0e87f28d1baa673a2" id="r_ga02b23ce670e6b5a0e87f28d1baa673a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02b23ce670e6b5a0e87f28d1baa673a2">GPIO_AFRH_AFRH2_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacc1431b847bccbc8841d8ab9a6aa36e5">GPIO_AFRH_AFSEL10_3</a></td></tr>
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<tr class="separator:ga02b23ce670e6b5a0e87f28d1baa673a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7043cbf3ca044ba36d59a8844c50552b" id="r_ga7043cbf3ca044ba36d59a8844c50552b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7043cbf3ca044ba36d59a8844c50552b">GPIO_AFRH_AFRH3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47a97a35b9f12ef795aa1ebb3d85c3aa">GPIO_AFRH_AFSEL11</a></td></tr>
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<tr class="separator:ga7043cbf3ca044ba36d59a8844c50552b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a0bca51b2c5a8635202590ed61842ab" id="r_ga5a0bca51b2c5a8635202590ed61842ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a0bca51b2c5a8635202590ed61842ab">GPIO_AFRH_AFRH3_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga711beadb293e4ef285bb813b2e9feb6d">GPIO_AFRH_AFSEL11_0</a></td></tr>
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<tr class="separator:ga5a0bca51b2c5a8635202590ed61842ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace0ca814ed3617d6f520ded8bc05cf3e" id="r_gace0ca814ed3617d6f520ded8bc05cf3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace0ca814ed3617d6f520ded8bc05cf3e">GPIO_AFRH_AFRH3_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ad64e530b4cf96c745f69ac97d23195">GPIO_AFRH_AFSEL11_1</a></td></tr>
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<tr class="separator:gace0ca814ed3617d6f520ded8bc05cf3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e22f1d39a67e130c29ba1d30d8b0740" id="r_ga9e22f1d39a67e130c29ba1d30d8b0740"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e22f1d39a67e130c29ba1d30d8b0740">GPIO_AFRH_AFRH3_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ffb839fbc0a35b148f17363553f6647">GPIO_AFRH_AFSEL11_2</a></td></tr>
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<tr class="separator:ga9e22f1d39a67e130c29ba1d30d8b0740"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22d6db61365e1172a8e5d895cbc16f59" id="r_ga22d6db61365e1172a8e5d895cbc16f59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22d6db61365e1172a8e5d895cbc16f59">GPIO_AFRH_AFRH3_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga570aa5e92e75568945191853f0196321">GPIO_AFRH_AFSEL11_3</a></td></tr>
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<tr class="separator:ga22d6db61365e1172a8e5d895cbc16f59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadae24d162b9e5a99064a81ba6a8d01d8" id="r_gadae24d162b9e5a99064a81ba6a8d01d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadae24d162b9e5a99064a81ba6a8d01d8">GPIO_AFRH_AFRH4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c12c0939e7fcc354e37d55b74afb351">GPIO_AFRH_AFSEL12</a></td></tr>
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<tr class="separator:gadae24d162b9e5a99064a81ba6a8d01d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee18ebc3ee54fcf4b049c722aaabd664" id="r_gaee18ebc3ee54fcf4b049c722aaabd664"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee18ebc3ee54fcf4b049c722aaabd664">GPIO_AFRH_AFRH4_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaffe1b4dcd4e796a2e145df206f35d6ea">GPIO_AFRH_AFSEL12_0</a></td></tr>
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<tr class="separator:gaee18ebc3ee54fcf4b049c722aaabd664"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd4ef3f6843069e21c3474025f9ad452" id="r_gabd4ef3f6843069e21c3474025f9ad452"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd4ef3f6843069e21c3474025f9ad452">GPIO_AFRH_AFRH4_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac5933c2c73fec3d2f3c41d32fb64bfa">GPIO_AFRH_AFSEL12_1</a></td></tr>
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<tr class="separator:gabd4ef3f6843069e21c3474025f9ad452"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23d973c410f46a567dd05719fc60e8b9" id="r_ga23d973c410f46a567dd05719fc60e8b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23d973c410f46a567dd05719fc60e8b9">GPIO_AFRH_AFRH4_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ed0f0c148e3c52bf041ab53af1d88bf">GPIO_AFRH_AFSEL12_2</a></td></tr>
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<tr class="memitem:gaef19c9e546b1d7130244a824a129a86d" id="r_gaef19c9e546b1d7130244a824a129a86d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef19c9e546b1d7130244a824a129a86d">GPIO_AFRH_AFRH4_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacbd6cfac7c23742a6e1fe120adfe3183">GPIO_AFRH_AFSEL12_3</a></td></tr>
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<tr class="separator:gaef19c9e546b1d7130244a824a129a86d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33b1d2c7b5ed5804798660a3e86214c4" id="r_ga33b1d2c7b5ed5804798660a3e86214c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33b1d2c7b5ed5804798660a3e86214c4">GPIO_AFRH_AFRH5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga60e9a3a49cdad6cd65d377fb675185da">GPIO_AFRH_AFSEL13</a></td></tr>
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<tr class="separator:ga33b1d2c7b5ed5804798660a3e86214c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaccf0f28c6792dcea352d16295a3370e" id="r_gaaccf0f28c6792dcea352d16295a3370e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaccf0f28c6792dcea352d16295a3370e">GPIO_AFRH_AFRH5_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab74ce92f856d5f687b069166f211ecaf">GPIO_AFRH_AFSEL13_0</a></td></tr>
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<tr class="separator:gaaccf0f28c6792dcea352d16295a3370e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb8de41b0dd5fdb53556acbd27eaffef" id="r_gadb8de41b0dd5fdb53556acbd27eaffef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb8de41b0dd5fdb53556acbd27eaffef">GPIO_AFRH_AFRH5_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d2985f042e79fb320b402a6e1c425f7">GPIO_AFRH_AFSEL13_1</a></td></tr>
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<tr class="separator:gadb8de41b0dd5fdb53556acbd27eaffef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17d3ee9f02ed784d1f9eafd306c7770b" id="r_ga17d3ee9f02ed784d1f9eafd306c7770b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17d3ee9f02ed784d1f9eafd306c7770b">GPIO_AFRH_AFRH5_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga59cb8d2b8ca336c6c169c0e1a07cb2eb">GPIO_AFRH_AFSEL13_2</a></td></tr>
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<tr class="separator:ga17d3ee9f02ed784d1f9eafd306c7770b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaca724f908dbf5ae10fe4721c4bb9a63" id="r_gaaca724f908dbf5ae10fe4721c4bb9a63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaca724f908dbf5ae10fe4721c4bb9a63">GPIO_AFRH_AFRH5_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac2ff66c2036fd651e7ae366db237b76c">GPIO_AFRH_AFSEL13_3</a></td></tr>
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<tr class="separator:gaaca724f908dbf5ae10fe4721c4bb9a63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56c388b4718d2257b4af362bec67a74a" id="r_ga56c388b4718d2257b4af362bec67a74a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56c388b4718d2257b4af362bec67a74a">GPIO_AFRH_AFRH6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3d930c6c5ffa92e461a0190be4bff78">GPIO_AFRH_AFSEL14</a></td></tr>
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<tr class="memitem:ga67bfcdbe201c0d10d6c604a7a77ef2c0" id="r_ga67bfcdbe201c0d10d6c604a7a77ef2c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67bfcdbe201c0d10d6c604a7a77ef2c0">GPIO_AFRH_AFRH6_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacf5b6ebd9c3a8039b46748dcbd3eda99">GPIO_AFRH_AFSEL14_0</a></td></tr>
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<tr class="separator:ga67bfcdbe201c0d10d6c604a7a77ef2c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c262cd0c09affb4b7a8d7fe40cb8737" id="r_ga3c262cd0c09affb4b7a8d7fe40cb8737"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c262cd0c09affb4b7a8d7fe40cb8737">GPIO_AFRH_AFRH6_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga21985995f6f22d63ba1170ee629bcf02">GPIO_AFRH_AFSEL14_1</a></td></tr>
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<tr class="separator:ga3c262cd0c09affb4b7a8d7fe40cb8737"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37c5f9c67bf086d5d2adf5e894476103" id="r_ga37c5f9c67bf086d5d2adf5e894476103"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37c5f9c67bf086d5d2adf5e894476103">GPIO_AFRH_AFRH6_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c98e75f198a3d84038029711c3f299f">GPIO_AFRH_AFSEL14_2</a></td></tr>
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<tr class="separator:ga37c5f9c67bf086d5d2adf5e894476103"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69f0639cf752be23c3d72c7218a1e179" id="r_ga69f0639cf752be23c3d72c7218a1e179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69f0639cf752be23c3d72c7218a1e179">GPIO_AFRH_AFRH6_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga41d1c1c7ac6886975bca9cc8ef57c73d">GPIO_AFRH_AFSEL14_3</a></td></tr>
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<tr class="separator:ga69f0639cf752be23c3d72c7218a1e179"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga770397420d63cb6e8317ae401e6b2977" id="r_ga770397420d63cb6e8317ae401e6b2977"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga770397420d63cb6e8317ae401e6b2977">GPIO_AFRH_AFRH7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga46417b0da710ef512ac4ceb95b3ab44a">GPIO_AFRH_AFSEL15</a></td></tr>
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<tr class="separator:ga770397420d63cb6e8317ae401e6b2977"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5323b47a92dc55d60b67a8d36049b07" id="r_gae5323b47a92dc55d60b67a8d36049b07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5323b47a92dc55d60b67a8d36049b07">GPIO_AFRH_AFRH7_0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga841bd65d5afd409fd7f2bf5f1e859348">GPIO_AFRH_AFSEL15_0</a></td></tr>
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<tr class="separator:gae5323b47a92dc55d60b67a8d36049b07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga133a9bf6920bdf13fbeda9e02c88bab4" id="r_ga133a9bf6920bdf13fbeda9e02c88bab4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga133a9bf6920bdf13fbeda9e02c88bab4">GPIO_AFRH_AFRH7_1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga233f1ae0a856a18e7b706093c80a6274">GPIO_AFRH_AFSEL15_1</a></td></tr>
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<tr class="separator:ga133a9bf6920bdf13fbeda9e02c88bab4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa20fc99964f4f634664e4498869d1ec4" id="r_gaa20fc99964f4f634664e4498869d1ec4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa20fc99964f4f634664e4498869d1ec4">GPIO_AFRH_AFRH7_2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadaae51ed82039c62ec075b42a192c861">GPIO_AFRH_AFSEL15_2</a></td></tr>
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<tr class="separator:gaa20fc99964f4f634664e4498869d1ec4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a6c924c6c54448656df6acfa66b9aae" id="r_ga3a6c924c6c54448656df6acfa66b9aae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a6c924c6c54448656df6acfa66b9aae">GPIO_AFRH_AFRH7_3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8699f7ff5369b8c20eaa32cfecbe7daf">GPIO_AFRH_AFSEL15_3</a></td></tr>
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<tr class="separator:ga3a6c924c6c54448656df6acfa66b9aae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7954738eae12426137b23733f12c7c14" id="r_ga7954738eae12426137b23733f12c7c14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7954738eae12426137b23733f12c7c14">I2C_CR1_PE_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7954738eae12426137b23733f12c7c14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga641d1563a97f92a4c5e20dcdd0756986" id="r_ga641d1563a97f92a4c5e20dcdd0756986"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga641d1563a97f92a4c5e20dcdd0756986">I2C_CR1_PE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7954738eae12426137b23733f12c7c14">I2C_CR1_PE_Pos</a>)</td></tr>
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<tr class="separator:ga641d1563a97f92a4c5e20dcdd0756986"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga953b0d38414808db79da116842ed3262" id="r_ga953b0d38414808db79da116842ed3262"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga953b0d38414808db79da116842ed3262">I2C_CR1_PE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga641d1563a97f92a4c5e20dcdd0756986">I2C_CR1_PE_Msk</a></td></tr>
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<tr class="separator:ga953b0d38414808db79da116842ed3262"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae26dbc9f9c06eb552db052b0603430c0" id="r_gae26dbc9f9c06eb552db052b0603430c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae26dbc9f9c06eb552db052b0603430c0">I2C_CR1_SMBUS_Pos</a>   (1U)</td></tr>
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<tr class="separator:gae26dbc9f9c06eb552db052b0603430c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf62afbb725efae2aa5a18c7841cfc51" id="r_gadf62afbb725efae2aa5a18c7841cfc51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf62afbb725efae2aa5a18c7841cfc51">I2C_CR1_SMBUS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae26dbc9f9c06eb552db052b0603430c0">I2C_CR1_SMBUS_Pos</a>)</td></tr>
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<tr class="separator:gadf62afbb725efae2aa5a18c7841cfc51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4cfee7b020a49bd037fa7cf27c796abc" id="r_ga4cfee7b020a49bd037fa7cf27c796abc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4cfee7b020a49bd037fa7cf27c796abc">I2C_CR1_SMBUS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadf62afbb725efae2aa5a18c7841cfc51">I2C_CR1_SMBUS_Msk</a></td></tr>
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<tr class="separator:ga4cfee7b020a49bd037fa7cf27c796abc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf03323d716d67da6242e4da7431cd1ea" id="r_gaf03323d716d67da6242e4da7431cd1ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf03323d716d67da6242e4da7431cd1ea">I2C_CR1_SMBTYPE_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaf03323d716d67da6242e4da7431cd1ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67a812813bce3b9996dec37eff310945" id="r_ga67a812813bce3b9996dec37eff310945"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67a812813bce3b9996dec37eff310945">I2C_CR1_SMBTYPE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf03323d716d67da6242e4da7431cd1ea">I2C_CR1_SMBTYPE_Pos</a>)</td></tr>
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<tr class="separator:ga67a812813bce3b9996dec37eff310945"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga001198ff898802888edf58f56d5371c9" id="r_ga001198ff898802888edf58f56d5371c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga001198ff898802888edf58f56d5371c9">I2C_CR1_SMBTYPE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67a812813bce3b9996dec37eff310945">I2C_CR1_SMBTYPE_Msk</a></td></tr>
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<tr class="separator:ga001198ff898802888edf58f56d5371c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga183847901bff6ed293ac42cedcd0a00f" id="r_ga183847901bff6ed293ac42cedcd0a00f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga183847901bff6ed293ac42cedcd0a00f">I2C_CR1_ENARP_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga183847901bff6ed293ac42cedcd0a00f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga608ec88f391d4617d8d196acf88ae4c3" id="r_ga608ec88f391d4617d8d196acf88ae4c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga608ec88f391d4617d8d196acf88ae4c3">I2C_CR1_ENARP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga183847901bff6ed293ac42cedcd0a00f">I2C_CR1_ENARP_Pos</a>)</td></tr>
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<tr class="separator:ga608ec88f391d4617d8d196acf88ae4c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4598185d9092edfbf943464bcbb342ac" id="r_ga4598185d9092edfbf943464bcbb342ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4598185d9092edfbf943464bcbb342ac">I2C_CR1_ENARP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga608ec88f391d4617d8d196acf88ae4c3">I2C_CR1_ENARP_Msk</a></td></tr>
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<tr class="separator:ga4598185d9092edfbf943464bcbb342ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6320b277f4eb5ad80869cf46509ab63" id="r_gad6320b277f4eb5ad80869cf46509ab63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6320b277f4eb5ad80869cf46509ab63">I2C_CR1_ENPEC_Pos</a>   (5U)</td></tr>
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<tr class="separator:gad6320b277f4eb5ad80869cf46509ab63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga047dbff196b5cc2e0ca679cf09daad7d" id="r_ga047dbff196b5cc2e0ca679cf09daad7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga047dbff196b5cc2e0ca679cf09daad7d">I2C_CR1_ENPEC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad6320b277f4eb5ad80869cf46509ab63">I2C_CR1_ENPEC_Pos</a>)</td></tr>
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<tr class="separator:ga047dbff196b5cc2e0ca679cf09daad7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40d2eb849f9d55e6298035b61e84ca42" id="r_ga40d2eb849f9d55e6298035b61e84ca42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40d2eb849f9d55e6298035b61e84ca42">I2C_CR1_ENPEC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga047dbff196b5cc2e0ca679cf09daad7d">I2C_CR1_ENPEC_Msk</a></td></tr>
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<tr class="separator:ga40d2eb849f9d55e6298035b61e84ca42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54ffd903ba1ddb087e7166a83b30d145" id="r_ga54ffd903ba1ddb087e7166a83b30d145"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54ffd903ba1ddb087e7166a83b30d145">I2C_CR1_ENGC_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga54ffd903ba1ddb087e7166a83b30d145"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7eff07d7a774d45f0c0b853be70b1a06" id="r_ga7eff07d7a774d45f0c0b853be70b1a06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7eff07d7a774d45f0c0b853be70b1a06">I2C_CR1_ENGC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga54ffd903ba1ddb087e7166a83b30d145">I2C_CR1_ENGC_Pos</a>)</td></tr>
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<tr class="separator:ga7eff07d7a774d45f0c0b853be70b1a06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d8c219193b11f8507d7b85831d14912" id="r_ga1d8c219193b11f8507d7b85831d14912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d8c219193b11f8507d7b85831d14912">I2C_CR1_ENGC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7eff07d7a774d45f0c0b853be70b1a06">I2C_CR1_ENGC_Msk</a></td></tr>
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<tr class="separator:ga1d8c219193b11f8507d7b85831d14912"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57955bf36ff5f4cd6a753e01817bf3b2" id="r_ga57955bf36ff5f4cd6a753e01817bf3b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57955bf36ff5f4cd6a753e01817bf3b2">I2C_CR1_NOSTRETCH_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga57955bf36ff5f4cd6a753e01817bf3b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e4eb2525f0444cc6320f96cc6c01804" id="r_ga1e4eb2525f0444cc6320f96cc6c01804"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e4eb2525f0444cc6320f96cc6c01804">I2C_CR1_NOSTRETCH_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57955bf36ff5f4cd6a753e01817bf3b2">I2C_CR1_NOSTRETCH_Pos</a>)</td></tr>
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<tr class="separator:ga1e4eb2525f0444cc6320f96cc6c01804"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga197aaca79f64e832af3a0a0864c2a08c" id="r_ga197aaca79f64e832af3a0a0864c2a08c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga197aaca79f64e832af3a0a0864c2a08c">I2C_CR1_NOSTRETCH</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e4eb2525f0444cc6320f96cc6c01804">I2C_CR1_NOSTRETCH_Msk</a></td></tr>
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<tr class="separator:ga197aaca79f64e832af3a0a0864c2a08c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26478428c37301f88c8fe5a27ab7cff0" id="r_ga26478428c37301f88c8fe5a27ab7cff0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26478428c37301f88c8fe5a27ab7cff0">I2C_CR1_START_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga26478428c37301f88c8fe5a27ab7cff0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20183fa72a3acfb6eb7cd333569af62b" id="r_ga20183fa72a3acfb6eb7cd333569af62b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20183fa72a3acfb6eb7cd333569af62b">I2C_CR1_START_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga26478428c37301f88c8fe5a27ab7cff0">I2C_CR1_START_Pos</a>)</td></tr>
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<tr class="separator:ga20183fa72a3acfb6eb7cd333569af62b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ca7f18dd5bc1130dbefae4ff8736143" id="r_ga2ca7f18dd5bc1130dbefae4ff8736143"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ca7f18dd5bc1130dbefae4ff8736143">I2C_CR1_START</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga20183fa72a3acfb6eb7cd333569af62b">I2C_CR1_START_Msk</a></td></tr>
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<tr class="separator:ga2ca7f18dd5bc1130dbefae4ff8736143"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1acc4153373e71ad85766145727d751f" id="r_ga1acc4153373e71ad85766145727d751f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1acc4153373e71ad85766145727d751f">I2C_CR1_STOP_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga1acc4153373e71ad85766145727d751f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac560445dddd085e2ec78b6c38d290893" id="r_gac560445dddd085e2ec78b6c38d290893"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac560445dddd085e2ec78b6c38d290893">I2C_CR1_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1acc4153373e71ad85766145727d751f">I2C_CR1_STOP_Pos</a>)</td></tr>
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<tr class="separator:gac560445dddd085e2ec78b6c38d290893"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace70293f3dfa24d448b600fc58e45223" id="r_gace70293f3dfa24d448b600fc58e45223"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace70293f3dfa24d448b600fc58e45223">I2C_CR1_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac560445dddd085e2ec78b6c38d290893">I2C_CR1_STOP_Msk</a></td></tr>
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<tr class="separator:gace70293f3dfa24d448b600fc58e45223"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4d488ef9214c8e156aa5789193b1af2" id="r_gac4d488ef9214c8e156aa5789193b1af2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4d488ef9214c8e156aa5789193b1af2">I2C_CR1_ACK_Pos</a>   (10U)</td></tr>
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<tr class="separator:gac4d488ef9214c8e156aa5789193b1af2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga901752f0d8d57314c1bf5841b4d15927" id="r_ga901752f0d8d57314c1bf5841b4d15927"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga901752f0d8d57314c1bf5841b4d15927">I2C_CR1_ACK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4d488ef9214c8e156aa5789193b1af2">I2C_CR1_ACK_Pos</a>)</td></tr>
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<tr class="separator:ga901752f0d8d57314c1bf5841b4d15927"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf933b105259a4bc46a957576adb8d96d" id="r_gaf933b105259a4bc46a957576adb8d96d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf933b105259a4bc46a957576adb8d96d">I2C_CR1_ACK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga901752f0d8d57314c1bf5841b4d15927">I2C_CR1_ACK_Msk</a></td></tr>
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<tr class="separator:gaf933b105259a4bc46a957576adb8d96d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c8ebf2be75a57d79c3963cbb73299e5" id="r_ga1c8ebf2be75a57d79c3963cbb73299e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c8ebf2be75a57d79c3963cbb73299e5">I2C_CR1_POS_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga1c8ebf2be75a57d79c3963cbb73299e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44cbb4dfe0bace0e0f63516352cdd686" id="r_ga44cbb4dfe0bace0e0f63516352cdd686"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44cbb4dfe0bace0e0f63516352cdd686">I2C_CR1_POS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c8ebf2be75a57d79c3963cbb73299e5">I2C_CR1_POS_Pos</a>)</td></tr>
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<tr class="separator:ga44cbb4dfe0bace0e0f63516352cdd686"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34721958229a5983f2e95dfeaa8e55c3" id="r_ga34721958229a5983f2e95dfeaa8e55c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34721958229a5983f2e95dfeaa8e55c3">I2C_CR1_POS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44cbb4dfe0bace0e0f63516352cdd686">I2C_CR1_POS_Msk</a></td></tr>
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<tr class="separator:ga34721958229a5983f2e95dfeaa8e55c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae27ac08c854b421c8bbef0f91cb02e77" id="r_gae27ac08c854b421c8bbef0f91cb02e77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae27ac08c854b421c8bbef0f91cb02e77">I2C_CR1_PEC_Pos</a>   (12U)</td></tr>
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<tr class="separator:gae27ac08c854b421c8bbef0f91cb02e77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad603ba46a4c90d87755bc21032343a8e" id="r_gad603ba46a4c90d87755bc21032343a8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad603ba46a4c90d87755bc21032343a8e">I2C_CR1_PEC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae27ac08c854b421c8bbef0f91cb02e77">I2C_CR1_PEC_Pos</a>)</td></tr>
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<tr class="separator:gad603ba46a4c90d87755bc21032343a8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4d0119253d93a106b5ca704e5020c12" id="r_gab4d0119253d93a106b5ca704e5020c12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4d0119253d93a106b5ca704e5020c12">I2C_CR1_PEC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad603ba46a4c90d87755bc21032343a8e">I2C_CR1_PEC_Msk</a></td></tr>
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<tr class="separator:gab4d0119253d93a106b5ca704e5020c12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cbad0729b1263ee12efe299c460c7a9" id="r_ga2cbad0729b1263ee12efe299c460c7a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cbad0729b1263ee12efe299c460c7a9">I2C_CR1_ALERT_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga2cbad0729b1263ee12efe299c460c7a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c1f4432707ef457508aa265173d3ce6" id="r_ga2c1f4432707ef457508aa265173d3ce6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c1f4432707ef457508aa265173d3ce6">I2C_CR1_ALERT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cbad0729b1263ee12efe299c460c7a9">I2C_CR1_ALERT_Pos</a>)</td></tr>
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<tr class="separator:ga2c1f4432707ef457508aa265173d3ce6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56729ccf93c5d9f5b5b05002e3a2323c" id="r_ga56729ccf93c5d9f5b5b05002e3a2323c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56729ccf93c5d9f5b5b05002e3a2323c">I2C_CR1_ALERT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c1f4432707ef457508aa265173d3ce6">I2C_CR1_ALERT_Msk</a></td></tr>
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<tr class="separator:ga56729ccf93c5d9f5b5b05002e3a2323c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f26e1407449ae64fade6b92a5e85bc9" id="r_ga5f26e1407449ae64fade6b92a5e85bc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f26e1407449ae64fade6b92a5e85bc9">I2C_CR1_SWRST_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga5f26e1407449ae64fade6b92a5e85bc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87f58f075ab791157d5a7f73d61ea4a0" id="r_ga87f58f075ab791157d5a7f73d61ea4a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87f58f075ab791157d5a7f73d61ea4a0">I2C_CR1_SWRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f26e1407449ae64fade6b92a5e85bc9">I2C_CR1_SWRST_Pos</a>)</td></tr>
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<tr class="separator:ga87f58f075ab791157d5a7f73d61ea4a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8dc661ef13da02e5bcb943f2003d576d" id="r_ga8dc661ef13da02e5bcb943f2003d576d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8dc661ef13da02e5bcb943f2003d576d">I2C_CR1_SWRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga87f58f075ab791157d5a7f73d61ea4a0">I2C_CR1_SWRST_Msk</a></td></tr>
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<tr class="separator:ga8dc661ef13da02e5bcb943f2003d576d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae37aa57192c71b1b734815130eeee8cd" id="r_gae37aa57192c71b1b734815130eeee8cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae37aa57192c71b1b734815130eeee8cd">I2C_CR2_FREQ_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae37aa57192c71b1b734815130eeee8cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga409296c2e8ff17ef7633266fad88d5ea" id="r_ga409296c2e8ff17ef7633266fad88d5ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga409296c2e8ff17ef7633266fad88d5ea">I2C_CR2_FREQ_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae37aa57192c71b1b734815130eeee8cd">I2C_CR2_FREQ_Pos</a>)</td></tr>
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<tr class="separator:ga409296c2e8ff17ef7633266fad88d5ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga293fbe15ed5fd1fc95915bd6437859e7" id="r_ga293fbe15ed5fd1fc95915bd6437859e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga293fbe15ed5fd1fc95915bd6437859e7">I2C_CR2_FREQ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga409296c2e8ff17ef7633266fad88d5ea">I2C_CR2_FREQ_Msk</a></td></tr>
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<tr class="separator:ga293fbe15ed5fd1fc95915bd6437859e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09d944f5260f40a0eb714d41859e0d23" id="r_ga09d944f5260f40a0eb714d41859e0d23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09d944f5260f40a0eb714d41859e0d23">I2C_CR2_FREQ_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae37aa57192c71b1b734815130eeee8cd">I2C_CR2_FREQ_Pos</a>)</td></tr>
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<tr class="separator:ga09d944f5260f40a0eb714d41859e0d23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25ab0ef2a7795e3326900b277479d89c" id="r_ga25ab0ef2a7795e3326900b277479d89c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25ab0ef2a7795e3326900b277479d89c">I2C_CR2_FREQ_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae37aa57192c71b1b734815130eeee8cd">I2C_CR2_FREQ_Pos</a>)</td></tr>
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<tr class="memitem:ga657af5a02534cc900cbddc260319d845" id="r_ga657af5a02534cc900cbddc260319d845"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga657af5a02534cc900cbddc260319d845">I2C_CR2_FREQ_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae37aa57192c71b1b734815130eeee8cd">I2C_CR2_FREQ_Pos</a>)</td></tr>
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<tr class="memitem:ga655214f8327fd1322998c9d8bffe308d" id="r_ga655214f8327fd1322998c9d8bffe308d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga655214f8327fd1322998c9d8bffe308d">I2C_CR2_FREQ_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae37aa57192c71b1b734815130eeee8cd">I2C_CR2_FREQ_Pos</a>)</td></tr>
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<tr class="memitem:ga3382a7262743bc824985af7339449386" id="r_ga3382a7262743bc824985af7339449386"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3382a7262743bc824985af7339449386">I2C_CR2_FREQ_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae37aa57192c71b1b734815130eeee8cd">I2C_CR2_FREQ_Pos</a>)</td></tr>
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<tr class="separator:ga3382a7262743bc824985af7339449386"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3b1a2b777fcf158c9e4264485682a20" id="r_gad3b1a2b777fcf158c9e4264485682a20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3b1a2b777fcf158c9e4264485682a20">I2C_CR2_FREQ_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae37aa57192c71b1b734815130eeee8cd">I2C_CR2_FREQ_Pos</a>)</td></tr>
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<tr class="separator:gad3b1a2b777fcf158c9e4264485682a20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d664ebaabc46a45c4453e17e5132056" id="r_ga1d664ebaabc46a45c4453e17e5132056"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d664ebaabc46a45c4453e17e5132056">I2C_CR2_ITERREN_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga1d664ebaabc46a45c4453e17e5132056"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cbb0dde5e57765d211af8595a728029" id="r_ga3cbb0dde5e57765d211af8595a728029"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cbb0dde5e57765d211af8595a728029">I2C_CR2_ITERREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d664ebaabc46a45c4453e17e5132056">I2C_CR2_ITERREN_Pos</a>)</td></tr>
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<tr class="separator:ga3cbb0dde5e57765d211af8595a728029"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f14ae48e4609c2b3645211234cba974" id="r_ga6f14ae48e4609c2b3645211234cba974"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f14ae48e4609c2b3645211234cba974">I2C_CR2_ITERREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cbb0dde5e57765d211af8595a728029">I2C_CR2_ITERREN_Msk</a></td></tr>
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<tr class="separator:ga6f14ae48e4609c2b3645211234cba974"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6b73580546ba348cd434416f7729d65" id="r_gae6b73580546ba348cd434416f7729d65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6b73580546ba348cd434416f7729d65">I2C_CR2_ITEVTEN_Pos</a>   (9U)</td></tr>
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<tr class="separator:gae6b73580546ba348cd434416f7729d65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4a4a92cd2663c4e4e690fe5f66a1706" id="r_gac4a4a92cd2663c4e4e690fe5f66a1706"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4a4a92cd2663c4e4e690fe5f66a1706">I2C_CR2_ITEVTEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae6b73580546ba348cd434416f7729d65">I2C_CR2_ITEVTEN_Pos</a>)</td></tr>
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<tr class="separator:gac4a4a92cd2663c4e4e690fe5f66a1706"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b1ebaf8173090ec469b055b98e585d2" id="r_ga3b1ebaf8173090ec469b055b98e585d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b1ebaf8173090ec469b055b98e585d2">I2C_CR2_ITEVTEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4a4a92cd2663c4e4e690fe5f66a1706">I2C_CR2_ITEVTEN_Msk</a></td></tr>
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<tr class="separator:ga3b1ebaf8173090ec469b055b98e585d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cf0976d8a817ec970a78137e6bac452" id="r_ga1cf0976d8a817ec970a78137e6bac452"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cf0976d8a817ec970a78137e6bac452">I2C_CR2_ITBUFEN_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga1cf0976d8a817ec970a78137e6bac452"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga765fa0272f4a94eed64fba9b3cdac713" id="r_ga765fa0272f4a94eed64fba9b3cdac713"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga765fa0272f4a94eed64fba9b3cdac713">I2C_CR2_ITBUFEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1cf0976d8a817ec970a78137e6bac452">I2C_CR2_ITBUFEN_Pos</a>)</td></tr>
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<tr class="separator:ga765fa0272f4a94eed64fba9b3cdac713"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2efbe5d96ed0ce447a45a62e8317a68a" id="r_ga2efbe5d96ed0ce447a45a62e8317a68a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2efbe5d96ed0ce447a45a62e8317a68a">I2C_CR2_ITBUFEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga765fa0272f4a94eed64fba9b3cdac713">I2C_CR2_ITBUFEN_Msk</a></td></tr>
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<tr class="separator:ga2efbe5d96ed0ce447a45a62e8317a68a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69b0d5b0217bd628743324b8393bc74a" id="r_ga69b0d5b0217bd628743324b8393bc74a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69b0d5b0217bd628743324b8393bc74a">I2C_CR2_DMAEN_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga69b0d5b0217bd628743324b8393bc74a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2987290a42860b8700c2dcfb8eaef399" id="r_ga2987290a42860b8700c2dcfb8eaef399"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2987290a42860b8700c2dcfb8eaef399">I2C_CR2_DMAEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69b0d5b0217bd628743324b8393bc74a">I2C_CR2_DMAEN_Pos</a>)</td></tr>
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<tr class="separator:ga2987290a42860b8700c2dcfb8eaef399"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb81d5c91486b873bd0bf279a4ffcf69" id="r_gadb81d5c91486b873bd0bf279a4ffcf69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb81d5c91486b873bd0bf279a4ffcf69">I2C_CR2_DMAEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2987290a42860b8700c2dcfb8eaef399">I2C_CR2_DMAEN_Msk</a></td></tr>
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<tr class="separator:gadb81d5c91486b873bd0bf279a4ffcf69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c908f15a0b4c9e603d17b066fc85b7b" id="r_ga0c908f15a0b4c9e603d17b066fc85b7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c908f15a0b4c9e603d17b066fc85b7b">I2C_CR2_LAST_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga0c908f15a0b4c9e603d17b066fc85b7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c9c22f3c0a1abb70e0255c765b30382" id="r_ga2c9c22f3c0a1abb70e0255c765b30382"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c9c22f3c0a1abb70e0255c765b30382">I2C_CR2_LAST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c908f15a0b4c9e603d17b066fc85b7b">I2C_CR2_LAST_Pos</a>)</td></tr>
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<tr class="separator:ga2c9c22f3c0a1abb70e0255c765b30382"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a0955008cbabbb6b726ba0b4f8da609" id="r_ga6a0955008cbabbb6b726ba0b4f8da609"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a0955008cbabbb6b726ba0b4f8da609">I2C_CR2_LAST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c9c22f3c0a1abb70e0255c765b30382">I2C_CR2_LAST_Msk</a></td></tr>
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<tr class="separator:ga6a0955008cbabbb6b726ba0b4f8da609"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8250616a993a5f2bb04cd0f116005864" id="r_ga8250616a993a5f2bb04cd0f116005864"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8250616a993a5f2bb04cd0f116005864">I2C_OAR1_ADD1_7</a>   0x000000FEU</td></tr>
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<tr class="separator:ga8250616a993a5f2bb04cd0f116005864"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8141dcd63a8429a64d488cc78ef3ec1" id="r_gab8141dcd63a8429a64d488cc78ef3ec1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8141dcd63a8429a64d488cc78ef3ec1">I2C_OAR1_ADD8_9</a>   0x00000300U</td></tr>
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<tr class="separator:gab8141dcd63a8429a64d488cc78ef3ec1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5025971b93434d9d6c1b47ba93cc4249" id="r_ga5025971b93434d9d6c1b47ba93cc4249"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5025971b93434d9d6c1b47ba93cc4249">I2C_OAR1_ADD0_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5025971b93434d9d6c1b47ba93cc4249"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga315ebd53e115b321f02d945a5a485356" id="r_ga315ebd53e115b321f02d945a5a485356"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga315ebd53e115b321f02d945a5a485356">I2C_OAR1_ADD0_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5025971b93434d9d6c1b47ba93cc4249">I2C_OAR1_ADD0_Pos</a>)</td></tr>
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<tr class="separator:ga315ebd53e115b321f02d945a5a485356"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b7c20c81f79d17921718412b8fca6d7" id="r_ga8b7c20c81f79d17921718412b8fca6d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b7c20c81f79d17921718412b8fca6d7">I2C_OAR1_ADD0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga315ebd53e115b321f02d945a5a485356">I2C_OAR1_ADD0_Msk</a></td></tr>
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<tr class="separator:ga8b7c20c81f79d17921718412b8fca6d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53aaf5c99387556eb05205972a9fd765" id="r_ga53aaf5c99387556eb05205972a9fd765"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53aaf5c99387556eb05205972a9fd765">I2C_OAR1_ADD1_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga53aaf5c99387556eb05205972a9fd765"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedbc5009a53817d14a5b61b81abe47eb" id="r_gaedbc5009a53817d14a5b61b81abe47eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedbc5009a53817d14a5b61b81abe47eb">I2C_OAR1_ADD1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga53aaf5c99387556eb05205972a9fd765">I2C_OAR1_ADD1_Pos</a>)</td></tr>
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<tr class="separator:gaedbc5009a53817d14a5b61b81abe47eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga499a61f0013c5c6fe38b848901f58769" id="r_ga499a61f0013c5c6fe38b848901f58769"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga499a61f0013c5c6fe38b848901f58769">I2C_OAR1_ADD1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaedbc5009a53817d14a5b61b81abe47eb">I2C_OAR1_ADD1_Msk</a></td></tr>
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<tr class="separator:ga499a61f0013c5c6fe38b848901f58769"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1601f93351d29fd314910972bd4a997" id="r_gac1601f93351d29fd314910972bd4a997"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1601f93351d29fd314910972bd4a997">I2C_OAR1_ADD2_Pos</a>   (2U)</td></tr>
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<tr class="separator:gac1601f93351d29fd314910972bd4a997"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74d6b1ee8556d79db1f804871576381e" id="r_ga74d6b1ee8556d79db1f804871576381e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74d6b1ee8556d79db1f804871576381e">I2C_OAR1_ADD2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac1601f93351d29fd314910972bd4a997">I2C_OAR1_ADD2_Pos</a>)</td></tr>
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<tr class="separator:ga74d6b1ee8556d79db1f804871576381e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab44a263e36a7f34d922ff124aebd99c3" id="r_gab44a263e36a7f34d922ff124aebd99c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab44a263e36a7f34d922ff124aebd99c3">I2C_OAR1_ADD2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga74d6b1ee8556d79db1f804871576381e">I2C_OAR1_ADD2_Msk</a></td></tr>
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<tr class="separator:gab44a263e36a7f34d922ff124aebd99c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04c1306ea26d1fde330540af98f2ebaf" id="r_ga04c1306ea26d1fde330540af98f2ebaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04c1306ea26d1fde330540af98f2ebaf">I2C_OAR1_ADD3_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga04c1306ea26d1fde330540af98f2ebaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bd895166f6d0f2b1fe5bdb245495e7c" id="r_ga3bd895166f6d0f2b1fe5bdb245495e7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bd895166f6d0f2b1fe5bdb245495e7c">I2C_OAR1_ADD3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga04c1306ea26d1fde330540af98f2ebaf">I2C_OAR1_ADD3_Pos</a>)</td></tr>
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<tr class="separator:ga3bd895166f6d0f2b1fe5bdb245495e7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9584dca3b1b414a63cf7ba75e557155b" id="r_ga9584dca3b1b414a63cf7ba75e557155b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9584dca3b1b414a63cf7ba75e557155b">I2C_OAR1_ADD3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bd895166f6d0f2b1fe5bdb245495e7c">I2C_OAR1_ADD3_Msk</a></td></tr>
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<tr class="separator:ga9584dca3b1b414a63cf7ba75e557155b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91ebb7dae5c13a499109a9f0089387b2" id="r_ga91ebb7dae5c13a499109a9f0089387b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91ebb7dae5c13a499109a9f0089387b2">I2C_OAR1_ADD4_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga3261bcc4b1d94f2800cc78d26ef6a638" id="r_ga3261bcc4b1d94f2800cc78d26ef6a638"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3261bcc4b1d94f2800cc78d26ef6a638">I2C_OAR1_ADD4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga91ebb7dae5c13a499109a9f0089387b2">I2C_OAR1_ADD4_Pos</a>)</td></tr>
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<tr class="separator:ga3261bcc4b1d94f2800cc78d26ef6a638"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga110b915b907f4bf29ff03da1f077bd97" id="r_ga110b915b907f4bf29ff03da1f077bd97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga110b915b907f4bf29ff03da1f077bd97">I2C_OAR1_ADD4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3261bcc4b1d94f2800cc78d26ef6a638">I2C_OAR1_ADD4_Msk</a></td></tr>
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<tr class="separator:ga110b915b907f4bf29ff03da1f077bd97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga863a732cfab0b27034149a5d95c1c978" id="r_ga863a732cfab0b27034149a5d95c1c978"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga863a732cfab0b27034149a5d95c1c978">I2C_OAR1_ADD5_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga863a732cfab0b27034149a5d95c1c978"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga078a30f84550430baa5ea4ce4b424afd" id="r_ga078a30f84550430baa5ea4ce4b424afd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga078a30f84550430baa5ea4ce4b424afd">I2C_OAR1_ADD5_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga863a732cfab0b27034149a5d95c1c978">I2C_OAR1_ADD5_Pos</a>)</td></tr>
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<tr class="separator:ga078a30f84550430baa5ea4ce4b424afd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0856dee2657cf0a04d79084da86988ca" id="r_ga0856dee2657cf0a04d79084da86988ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0856dee2657cf0a04d79084da86988ca">I2C_OAR1_ADD5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga078a30f84550430baa5ea4ce4b424afd">I2C_OAR1_ADD5_Msk</a></td></tr>
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<tr class="separator:ga0856dee2657cf0a04d79084da86988ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadeef10580199e2315af15107d03374b6" id="r_gadeef10580199e2315af15107d03374b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadeef10580199e2315af15107d03374b6">I2C_OAR1_ADD6_Pos</a>   (6U)</td></tr>
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<tr class="separator:gadeef10580199e2315af15107d03374b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga708c99b9b7c44311be6a91fa01e2603d" id="r_ga708c99b9b7c44311be6a91fa01e2603d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga708c99b9b7c44311be6a91fa01e2603d">I2C_OAR1_ADD6_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadeef10580199e2315af15107d03374b6">I2C_OAR1_ADD6_Pos</a>)</td></tr>
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<tr class="separator:ga708c99b9b7c44311be6a91fa01e2603d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5507af6154f60125dadc4654f57776ca" id="r_ga5507af6154f60125dadc4654f57776ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5507af6154f60125dadc4654f57776ca">I2C_OAR1_ADD6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga708c99b9b7c44311be6a91fa01e2603d">I2C_OAR1_ADD6_Msk</a></td></tr>
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<tr class="separator:ga5507af6154f60125dadc4654f57776ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff51a9d14ec34d35f911c1c4d474db02" id="r_gaff51a9d14ec34d35f911c1c4d474db02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff51a9d14ec34d35f911c1c4d474db02">I2C_OAR1_ADD7_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaff51a9d14ec34d35f911c1c4d474db02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c9645decd676803bd6a1cb9e5cca0f8" id="r_ga6c9645decd676803bd6a1cb9e5cca0f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c9645decd676803bd6a1cb9e5cca0f8">I2C_OAR1_ADD7_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaff51a9d14ec34d35f911c1c4d474db02">I2C_OAR1_ADD7_Pos</a>)</td></tr>
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<tr class="separator:ga6c9645decd676803bd6a1cb9e5cca0f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca710515f0aac5abdac02a630e09097c" id="r_gaca710515f0aac5abdac02a630e09097c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca710515f0aac5abdac02a630e09097c">I2C_OAR1_ADD7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c9645decd676803bd6a1cb9e5cca0f8">I2C_OAR1_ADD7_Msk</a></td></tr>
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<tr class="separator:gaca710515f0aac5abdac02a630e09097c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15f7918fdb3af6d0c8ade393fb8c8357" id="r_ga15f7918fdb3af6d0c8ade393fb8c8357"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15f7918fdb3af6d0c8ade393fb8c8357">I2C_OAR1_ADD8_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga15f7918fdb3af6d0c8ade393fb8c8357"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga484398bbd79662011f8fb6467c127d65" id="r_ga484398bbd79662011f8fb6467c127d65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga484398bbd79662011f8fb6467c127d65">I2C_OAR1_ADD8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga15f7918fdb3af6d0c8ade393fb8c8357">I2C_OAR1_ADD8_Pos</a>)</td></tr>
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<tr class="separator:ga484398bbd79662011f8fb6467c127d65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab945eba8b842a253cc64cce722537264" id="r_gab945eba8b842a253cc64cce722537264"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab945eba8b842a253cc64cce722537264">I2C_OAR1_ADD8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga484398bbd79662011f8fb6467c127d65">I2C_OAR1_ADD8_Msk</a></td></tr>
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<tr class="separator:gab945eba8b842a253cc64cce722537264"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9208eb446047890ea90e2f87f57a8e0" id="r_gad9208eb446047890ea90e2f87f57a8e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9208eb446047890ea90e2f87f57a8e0">I2C_OAR1_ADD9_Pos</a>   (9U)</td></tr>
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<tr class="separator:gad9208eb446047890ea90e2f87f57a8e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf1cdf0196ac2b11475fbf7078a852a2" id="r_gaaf1cdf0196ac2b11475fbf7078a852a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf1cdf0196ac2b11475fbf7078a852a2">I2C_OAR1_ADD9_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9208eb446047890ea90e2f87f57a8e0">I2C_OAR1_ADD9_Pos</a>)</td></tr>
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<tr class="separator:gaaf1cdf0196ac2b11475fbf7078a852a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10cf2dfc6b1ed55413be06acca413430" id="r_ga10cf2dfc6b1ed55413be06acca413430"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10cf2dfc6b1ed55413be06acca413430">I2C_OAR1_ADD9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf1cdf0196ac2b11475fbf7078a852a2">I2C_OAR1_ADD9_Msk</a></td></tr>
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<tr class="separator:ga10cf2dfc6b1ed55413be06acca413430"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a9d87efeab027259266521e849cd0f6" id="r_ga0a9d87efeab027259266521e849cd0f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a9d87efeab027259266521e849cd0f6">I2C_OAR1_ADDMODE_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga0a9d87efeab027259266521e849cd0f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga465856ef24302471bd5562be5f4d8418" id="r_ga465856ef24302471bd5562be5f4d8418"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga465856ef24302471bd5562be5f4d8418">I2C_OAR1_ADDMODE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a9d87efeab027259266521e849cd0f6">I2C_OAR1_ADDMODE_Pos</a>)</td></tr>
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<tr class="separator:ga465856ef24302471bd5562be5f4d8418"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d8df80cd27313c896e887aae81fa639" id="r_ga7d8df80cd27313c896e887aae81fa639"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d8df80cd27313c896e887aae81fa639">I2C_OAR1_ADDMODE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga465856ef24302471bd5562be5f4d8418">I2C_OAR1_ADDMODE_Msk</a></td></tr>
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<tr class="separator:ga7d8df80cd27313c896e887aae81fa639"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd1b7689ba1197bb496f7b0042e59ac9" id="r_gabd1b7689ba1197bb496f7b0042e59ac9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd1b7689ba1197bb496f7b0042e59ac9">I2C_OAR2_ENDUAL_Pos</a>   (0U)</td></tr>
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<tr class="separator:gabd1b7689ba1197bb496f7b0042e59ac9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28fa608f2cec586e6bdb98ae510022d9" id="r_ga28fa608f2cec586e6bdb98ae510022d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28fa608f2cec586e6bdb98ae510022d9">I2C_OAR2_ENDUAL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabd1b7689ba1197bb496f7b0042e59ac9">I2C_OAR2_ENDUAL_Pos</a>)</td></tr>
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<tr class="separator:ga28fa608f2cec586e6bdb98ae510022d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab83ed1ee64439cb2734a708445f37e94" id="r_gab83ed1ee64439cb2734a708445f37e94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab83ed1ee64439cb2734a708445f37e94">I2C_OAR2_ENDUAL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga28fa608f2cec586e6bdb98ae510022d9">I2C_OAR2_ENDUAL_Msk</a></td></tr>
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<tr class="separator:gab83ed1ee64439cb2734a708445f37e94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga809d88f42d6572f85dd75ab2bb92b243" id="r_ga809d88f42d6572f85dd75ab2bb92b243"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga809d88f42d6572f85dd75ab2bb92b243">I2C_OAR2_ADD2_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga809d88f42d6572f85dd75ab2bb92b243"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18d179042a15bdc94dd4477b990082c5" id="r_ga18d179042a15bdc94dd4477b990082c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18d179042a15bdc94dd4477b990082c5">I2C_OAR2_ADD2_Msk</a>   (0x7FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga809d88f42d6572f85dd75ab2bb92b243">I2C_OAR2_ADD2_Pos</a>)</td></tr>
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<tr class="separator:ga18d179042a15bdc94dd4477b990082c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd3d8fd1de1f16d051efb52dd3d657c4" id="r_gadd3d8fd1de1f16d051efb52dd3d657c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd3d8fd1de1f16d051efb52dd3d657c4">I2C_OAR2_ADD2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga18d179042a15bdc94dd4477b990082c5">I2C_OAR2_ADD2_Msk</a></td></tr>
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<tr class="separator:gadd3d8fd1de1f16d051efb52dd3d657c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8168b87f1d876a0cdbafff9f3dd922f5" id="r_ga8168b87f1d876a0cdbafff9f3dd922f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8168b87f1d876a0cdbafff9f3dd922f5">I2C_DR_DR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8168b87f1d876a0cdbafff9f3dd922f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b487d8e08e84b2ef59c6de0e92316b1" id="r_ga2b487d8e08e84b2ef59c6de0e92316b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b487d8e08e84b2ef59c6de0e92316b1">I2C_DR_DR_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8168b87f1d876a0cdbafff9f3dd922f5">I2C_DR_DR_Pos</a>)</td></tr>
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<tr class="separator:ga2b487d8e08e84b2ef59c6de0e92316b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac43021a4a7f79672d27c36a469b301d5" id="r_gac43021a4a7f79672d27c36a469b301d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac43021a4a7f79672d27c36a469b301d5">I2C_DR_DR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b487d8e08e84b2ef59c6de0e92316b1">I2C_DR_DR_Msk</a></td></tr>
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<tr class="separator:gac43021a4a7f79672d27c36a469b301d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67ed7d8c3e9dc642c2c70c834aeec6ea" id="r_ga67ed7d8c3e9dc642c2c70c834aeec6ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67ed7d8c3e9dc642c2c70c834aeec6ea">I2C_SR1_SB_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga67ed7d8c3e9dc642c2c70c834aeec6ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9d2227f20b51eda4af2fb9e9dd4f6df" id="r_gab9d2227f20b51eda4af2fb9e9dd4f6df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9d2227f20b51eda4af2fb9e9dd4f6df">I2C_SR1_SB_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67ed7d8c3e9dc642c2c70c834aeec6ea">I2C_SR1_SB_Pos</a>)</td></tr>
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<tr class="separator:gab9d2227f20b51eda4af2fb9e9dd4f6df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6935c920da59d755d0cf834548a70ec4" id="r_ga6935c920da59d755d0cf834548a70ec4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6935c920da59d755d0cf834548a70ec4">I2C_SR1_SB</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9d2227f20b51eda4af2fb9e9dd4f6df">I2C_SR1_SB_Msk</a></td></tr>
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<tr class="memitem:ga4662fc1d4534a406d3e4e417dcaa29c1" id="r_ga4662fc1d4534a406d3e4e417dcaa29c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4662fc1d4534a406d3e4e417dcaa29c1">I2C_SR1_ADDR_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga4662fc1d4534a406d3e4e417dcaa29c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga387882c1ac38b5af80a88ac6c5c8961f" id="r_ga387882c1ac38b5af80a88ac6c5c8961f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga387882c1ac38b5af80a88ac6c5c8961f">I2C_SR1_ADDR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4662fc1d4534a406d3e4e417dcaa29c1">I2C_SR1_ADDR_Pos</a>)</td></tr>
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<tr class="separator:ga387882c1ac38b5af80a88ac6c5c8961f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3db361a4d9dd84b187085a11d933b45d" id="r_ga3db361a4d9dd84b187085a11d933b45d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3db361a4d9dd84b187085a11d933b45d">I2C_SR1_ADDR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga387882c1ac38b5af80a88ac6c5c8961f">I2C_SR1_ADDR_Msk</a></td></tr>
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<tr class="separator:ga3db361a4d9dd84b187085a11d933b45d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c662220a2fc8d437b929ac360b7b6d3" id="r_ga3c662220a2fc8d437b929ac360b7b6d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c662220a2fc8d437b929ac360b7b6d3">I2C_SR1_BTF_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga3c662220a2fc8d437b929ac360b7b6d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9da3a67ef386eb3c7fc5be2016a1f0b1" id="r_ga9da3a67ef386eb3c7fc5be2016a1f0b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9da3a67ef386eb3c7fc5be2016a1f0b1">I2C_SR1_BTF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c662220a2fc8d437b929ac360b7b6d3">I2C_SR1_BTF_Pos</a>)</td></tr>
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<tr class="separator:ga9da3a67ef386eb3c7fc5be2016a1f0b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb279f85d78cfe5abd3eeb0b40a65ab1" id="r_gafb279f85d78cfe5abd3eeb0b40a65ab1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb279f85d78cfe5abd3eeb0b40a65ab1">I2C_SR1_BTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9da3a67ef386eb3c7fc5be2016a1f0b1">I2C_SR1_BTF_Msk</a></td></tr>
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<tr class="separator:gafb279f85d78cfe5abd3eeb0b40a65ab1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57e3e98939884a675f561bd0133c73f7" id="r_ga57e3e98939884a675f561bd0133c73f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57e3e98939884a675f561bd0133c73f7">I2C_SR1_ADD10_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga57e3e98939884a675f561bd0133c73f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc01a4be991adeeffbdf18b5767ea30b" id="r_gabc01a4be991adeeffbdf18b5767ea30b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc01a4be991adeeffbdf18b5767ea30b">I2C_SR1_ADD10_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57e3e98939884a675f561bd0133c73f7">I2C_SR1_ADD10_Pos</a>)</td></tr>
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<tr class="memitem:ga6faaa55a1e48aa7c1f2b69669901445d" id="r_ga6faaa55a1e48aa7c1f2b69669901445d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6faaa55a1e48aa7c1f2b69669901445d">I2C_SR1_ADD10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabc01a4be991adeeffbdf18b5767ea30b">I2C_SR1_ADD10_Msk</a></td></tr>
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<tr class="separator:ga6faaa55a1e48aa7c1f2b69669901445d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga508dc538aee33bf854cfbe3b7f4a7ba9" id="r_ga508dc538aee33bf854cfbe3b7f4a7ba9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga508dc538aee33bf854cfbe3b7f4a7ba9">I2C_SR1_STOPF_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga508dc538aee33bf854cfbe3b7f4a7ba9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1679ebac13f8ad5aad54acd446f70e4" id="r_gad1679ebac13f8ad5aad54acd446f70e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1679ebac13f8ad5aad54acd446f70e4">I2C_SR1_STOPF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga508dc538aee33bf854cfbe3b7f4a7ba9">I2C_SR1_STOPF_Pos</a>)</td></tr>
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<tr class="separator:gad1679ebac13f8ad5aad54acd446f70e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaafcea4cdbe2f6da31566c897fa893a7c" id="r_gaafcea4cdbe2f6da31566c897fa893a7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafcea4cdbe2f6da31566c897fa893a7c">I2C_SR1_STOPF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad1679ebac13f8ad5aad54acd446f70e4">I2C_SR1_STOPF_Msk</a></td></tr>
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<tr class="separator:gaafcea4cdbe2f6da31566c897fa893a7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga380b3695a5b03ae70e411ba048a04e49" id="r_ga380b3695a5b03ae70e411ba048a04e49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga380b3695a5b03ae70e411ba048a04e49">I2C_SR1_RXNE_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga380b3695a5b03ae70e411ba048a04e49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf56d0f5cc9b333a2d287baf96e1ca62" id="r_gacf56d0f5cc9b333a2d287baf96e1ca62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf56d0f5cc9b333a2d287baf96e1ca62">I2C_SR1_RXNE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga380b3695a5b03ae70e411ba048a04e49">I2C_SR1_RXNE_Pos</a>)</td></tr>
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<tr class="separator:gacf56d0f5cc9b333a2d287baf96e1ca62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6ebe33c992611bc2e25bbb01c1441a5" id="r_gaf6ebe33c992611bc2e25bbb01c1441a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6ebe33c992611bc2e25bbb01c1441a5">I2C_SR1_RXNE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacf56d0f5cc9b333a2d287baf96e1ca62">I2C_SR1_RXNE_Msk</a></td></tr>
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<tr class="separator:gaf6ebe33c992611bc2e25bbb01c1441a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdceff8db6df40c017f96a5e606ea884" id="r_gabdceff8db6df40c017f96a5e606ea884"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdceff8db6df40c017f96a5e606ea884">I2C_SR1_TXE_Pos</a>   (7U)</td></tr>
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<tr class="separator:gabdceff8db6df40c017f96a5e606ea884"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga835a04e1e2c43a4462b9b5cd04b2b4ea" id="r_ga835a04e1e2c43a4462b9b5cd04b2b4ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga835a04e1e2c43a4462b9b5cd04b2b4ea">I2C_SR1_TXE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabdceff8db6df40c017f96a5e606ea884">I2C_SR1_TXE_Pos</a>)</td></tr>
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<tr class="separator:ga835a04e1e2c43a4462b9b5cd04b2b4ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdc4da49c163910203255e384591b6f7" id="r_gafdc4da49c163910203255e384591b6f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdc4da49c163910203255e384591b6f7">I2C_SR1_TXE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga835a04e1e2c43a4462b9b5cd04b2b4ea">I2C_SR1_TXE_Msk</a></td></tr>
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<tr class="separator:gafdc4da49c163910203255e384591b6f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a1c615024c02d5ea5bcb3717ff6863d" id="r_ga0a1c615024c02d5ea5bcb3717ff6863d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a1c615024c02d5ea5bcb3717ff6863d">I2C_SR1_BERR_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga0a1c615024c02d5ea5bcb3717ff6863d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga591f9c02dd6c1b393f295ddd9be5f28d" id="r_ga591f9c02dd6c1b393f295ddd9be5f28d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga591f9c02dd6c1b393f295ddd9be5f28d">I2C_SR1_BERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a1c615024c02d5ea5bcb3717ff6863d">I2C_SR1_BERR_Pos</a>)</td></tr>
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<tr class="separator:ga591f9c02dd6c1b393f295ddd9be5f28d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d12990c90ab0757dcfea150ea50b227" id="r_ga1d12990c90ab0757dcfea150ea50b227"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d12990c90ab0757dcfea150ea50b227">I2C_SR1_BERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga591f9c02dd6c1b393f295ddd9be5f28d">I2C_SR1_BERR_Msk</a></td></tr>
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<tr class="separator:ga1d12990c90ab0757dcfea150ea50b227"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafab03fd640b6661848addb3cd9d38519" id="r_gafab03fd640b6661848addb3cd9d38519"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafab03fd640b6661848addb3cd9d38519">I2C_SR1_ARLO_Pos</a>   (9U)</td></tr>
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<tr class="memitem:ga7859c854cc27fefc075eb3a6d67410da" id="r_ga7859c854cc27fefc075eb3a6d67410da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7859c854cc27fefc075eb3a6d67410da">I2C_SR1_ARLO_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafab03fd640b6661848addb3cd9d38519">I2C_SR1_ARLO_Pos</a>)</td></tr>
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<tr class="separator:ga7859c854cc27fefc075eb3a6d67410da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbc52f6ec6172c71d8b026a22c2f69d2" id="r_gacbc52f6ec6172c71d8b026a22c2f69d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbc52f6ec6172c71d8b026a22c2f69d2">I2C_SR1_ARLO</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7859c854cc27fefc075eb3a6d67410da">I2C_SR1_ARLO_Msk</a></td></tr>
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<tr class="separator:gacbc52f6ec6172c71d8b026a22c2f69d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb0a33028b96b10708bd881b21c17dae" id="r_gafb0a33028b96b10708bd881b21c17dae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb0a33028b96b10708bd881b21c17dae">I2C_SR1_AF_Pos</a>   (10U)</td></tr>
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<tr class="separator:gafb0a33028b96b10708bd881b21c17dae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae64af2b76c8fc655547f07d0eda3c8d6" id="r_gae64af2b76c8fc655547f07d0eda3c8d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae64af2b76c8fc655547f07d0eda3c8d6">I2C_SR1_AF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafb0a33028b96b10708bd881b21c17dae">I2C_SR1_AF_Pos</a>)</td></tr>
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<tr class="separator:gae64af2b76c8fc655547f07d0eda3c8d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62aa2496d4b3955214a16a7bd998fd88" id="r_ga62aa2496d4b3955214a16a7bd998fd88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62aa2496d4b3955214a16a7bd998fd88">I2C_SR1_AF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae64af2b76c8fc655547f07d0eda3c8d6">I2C_SR1_AF_Msk</a></td></tr>
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<tr class="separator:ga62aa2496d4b3955214a16a7bd998fd88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga628a0e0ea5fa7dd31b68d2bac80b8b20" id="r_ga628a0e0ea5fa7dd31b68d2bac80b8b20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga628a0e0ea5fa7dd31b68d2bac80b8b20">I2C_SR1_OVR_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga628a0e0ea5fa7dd31b68d2bac80b8b20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeca6c423a2a9d7495c35517b3cc9a9b8" id="r_gaeca6c423a2a9d7495c35517b3cc9a9b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeca6c423a2a9d7495c35517b3cc9a9b8">I2C_SR1_OVR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga628a0e0ea5fa7dd31b68d2bac80b8b20">I2C_SR1_OVR_Pos</a>)</td></tr>
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<tr class="separator:gaeca6c423a2a9d7495c35517b3cc9a9b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad42d2435d2e64bf710c701c9b17adfb4" id="r_gad42d2435d2e64bf710c701c9b17adfb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad42d2435d2e64bf710c701c9b17adfb4">I2C_SR1_OVR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeca6c423a2a9d7495c35517b3cc9a9b8">I2C_SR1_OVR_Msk</a></td></tr>
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<tr class="separator:gad42d2435d2e64bf710c701c9b17adfb4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f1e78360bc478a00ca5c8176dcd0b22" id="r_ga1f1e78360bc478a00ca5c8176dcd0b22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f1e78360bc478a00ca5c8176dcd0b22">I2C_SR1_PECERR_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga1f1e78360bc478a00ca5c8176dcd0b22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaafd640f94fa388e27d4747c5eb8fc938" id="r_gaafd640f94fa388e27d4747c5eb8fc938"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafd640f94fa388e27d4747c5eb8fc938">I2C_SR1_PECERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f1e78360bc478a00ca5c8176dcd0b22">I2C_SR1_PECERR_Pos</a>)</td></tr>
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<tr class="memitem:ga4b2976279024e832e53ad12796a7bb71" id="r_ga4b2976279024e832e53ad12796a7bb71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b2976279024e832e53ad12796a7bb71">I2C_SR1_PECERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaafd640f94fa388e27d4747c5eb8fc938">I2C_SR1_PECERR_Msk</a></td></tr>
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<tr class="separator:ga4b2976279024e832e53ad12796a7bb71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80a7d5a7ab0b5eb4bbbcf59d64e9e58e" id="r_ga80a7d5a7ab0b5eb4bbbcf59d64e9e58e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80a7d5a7ab0b5eb4bbbcf59d64e9e58e">I2C_SR1_TIMEOUT_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga80a7d5a7ab0b5eb4bbbcf59d64e9e58e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c0209188a2791eddad0c143ac7f9416" id="r_ga7c0209188a2791eddad0c143ac7f9416"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c0209188a2791eddad0c143ac7f9416">I2C_SR1_TIMEOUT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80a7d5a7ab0b5eb4bbbcf59d64e9e58e">I2C_SR1_TIMEOUT_Pos</a>)</td></tr>
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<tr class="separator:ga7c0209188a2791eddad0c143ac7f9416"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef3a1e4921d7c509d1b639c67882c4c9" id="r_gaef3a1e4921d7c509d1b639c67882c4c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef3a1e4921d7c509d1b639c67882c4c9">I2C_SR1_TIMEOUT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c0209188a2791eddad0c143ac7f9416">I2C_SR1_TIMEOUT_Msk</a></td></tr>
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<tr class="separator:gaef3a1e4921d7c509d1b639c67882c4c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0c047e24fefb89f3928b37b7695aa55" id="r_gad0c047e24fefb89f3928b37b7695aa55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0c047e24fefb89f3928b37b7695aa55">I2C_SR1_SMBALERT_Pos</a>   (15U)</td></tr>
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<tr class="separator:gad0c047e24fefb89f3928b37b7695aa55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga617464b325a3649c9a36ad80386558b6" id="r_ga617464b325a3649c9a36ad80386558b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga617464b325a3649c9a36ad80386558b6">I2C_SR1_SMBALERT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad0c047e24fefb89f3928b37b7695aa55">I2C_SR1_SMBALERT_Pos</a>)</td></tr>
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<tr class="separator:ga617464b325a3649c9a36ad80386558b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8df36c38deb8791d0ac3cb5881298c1c" id="r_ga8df36c38deb8791d0ac3cb5881298c1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8df36c38deb8791d0ac3cb5881298c1c">I2C_SR1_SMBALERT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga617464b325a3649c9a36ad80386558b6">I2C_SR1_SMBALERT_Msk</a></td></tr>
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<tr class="separator:ga8df36c38deb8791d0ac3cb5881298c1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada5253dbcd3c7d67d0fad31d938f4b5b" id="r_gada5253dbcd3c7d67d0fad31d938f4b5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada5253dbcd3c7d67d0fad31d938f4b5b">I2C_SR2_MSL_Pos</a>   (0U)</td></tr>
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<tr class="separator:gada5253dbcd3c7d67d0fad31d938f4b5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad723df35fcda84431aefaace405b62b2" id="r_gad723df35fcda84431aefaace405b62b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad723df35fcda84431aefaace405b62b2">I2C_SR2_MSL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada5253dbcd3c7d67d0fad31d938f4b5b">I2C_SR2_MSL_Pos</a>)</td></tr>
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<tr class="separator:gad723df35fcda84431aefaace405b62b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75cc361adf0e72e33d6771ebfa17b52d" id="r_ga75cc361adf0e72e33d6771ebfa17b52d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75cc361adf0e72e33d6771ebfa17b52d">I2C_SR2_MSL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad723df35fcda84431aefaace405b62b2">I2C_SR2_MSL_Msk</a></td></tr>
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<tr class="separator:ga75cc361adf0e72e33d6771ebfa17b52d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9b4a60a8e919cfe14e222976859b1cd" id="r_gaa9b4a60a8e919cfe14e222976859b1cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9b4a60a8e919cfe14e222976859b1cd">I2C_SR2_BUSY_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaa9b4a60a8e919cfe14e222976859b1cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43693f4a5b2f232a145eee42f26a1110" id="r_ga43693f4a5b2f232a145eee42f26a1110"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43693f4a5b2f232a145eee42f26a1110">I2C_SR2_BUSY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9b4a60a8e919cfe14e222976859b1cd">I2C_SR2_BUSY_Pos</a>)</td></tr>
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<tr class="separator:ga43693f4a5b2f232a145eee42f26a1110"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b1e75a82da73ae2873cff1cd27c3179" id="r_ga3b1e75a82da73ae2873cff1cd27c3179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b1e75a82da73ae2873cff1cd27c3179">I2C_SR2_BUSY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga43693f4a5b2f232a145eee42f26a1110">I2C_SR2_BUSY_Msk</a></td></tr>
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<tr class="separator:ga3b1e75a82da73ae2873cff1cd27c3179"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91e4b3f7e5bff2ea65eefeadbc0a2e2a" id="r_ga91e4b3f7e5bff2ea65eefeadbc0a2e2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91e4b3f7e5bff2ea65eefeadbc0a2e2a">I2C_SR2_TRA_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga91e4b3f7e5bff2ea65eefeadbc0a2e2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga260f5bfa56cd55a6e25ae1585fc1381e" id="r_ga260f5bfa56cd55a6e25ae1585fc1381e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga260f5bfa56cd55a6e25ae1585fc1381e">I2C_SR2_TRA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga91e4b3f7e5bff2ea65eefeadbc0a2e2a">I2C_SR2_TRA_Pos</a>)</td></tr>
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<tr class="separator:ga260f5bfa56cd55a6e25ae1585fc1381e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga288b20416b42a79e591aa80d9a690fca" id="r_ga288b20416b42a79e591aa80d9a690fca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga288b20416b42a79e591aa80d9a690fca">I2C_SR2_TRA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga260f5bfa56cd55a6e25ae1585fc1381e">I2C_SR2_TRA_Msk</a></td></tr>
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<tr class="separator:ga288b20416b42a79e591aa80d9a690fca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26e3032167b56ec310c7b81945dc76a4" id="r_ga26e3032167b56ec310c7b81945dc76a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26e3032167b56ec310c7b81945dc76a4">I2C_SR2_GENCALL_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga26e3032167b56ec310c7b81945dc76a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada42e3c3d8e62bfab1117a382def5383" id="r_gada42e3c3d8e62bfab1117a382def5383"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada42e3c3d8e62bfab1117a382def5383">I2C_SR2_GENCALL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga26e3032167b56ec310c7b81945dc76a4">I2C_SR2_GENCALL_Pos</a>)</td></tr>
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<tr class="separator:gada42e3c3d8e62bfab1117a382def5383"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3aeb79cbe04f7ec1e3c2615921c4fab" id="r_gaf3aeb79cbe04f7ec1e3c2615921c4fab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3aeb79cbe04f7ec1e3c2615921c4fab">I2C_SR2_GENCALL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada42e3c3d8e62bfab1117a382def5383">I2C_SR2_GENCALL_Msk</a></td></tr>
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<tr class="separator:gaf3aeb79cbe04f7ec1e3c2615921c4fab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4be26fe6702a976b50628c3df1b352c" id="r_gaf4be26fe6702a976b50628c3df1b352c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4be26fe6702a976b50628c3df1b352c">I2C_SR2_SMBDEFAULT_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaf4be26fe6702a976b50628c3df1b352c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa390034d42a7873287b68e9ae3935a26" id="r_gaa390034d42a7873287b68e9ae3935a26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa390034d42a7873287b68e9ae3935a26">I2C_SR2_SMBDEFAULT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4be26fe6702a976b50628c3df1b352c">I2C_SR2_SMBDEFAULT_Pos</a>)</td></tr>
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<tr class="separator:gaa390034d42a7873287b68e9ae3935a26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcf50334903013177a8c6f4e36b8d6fe" id="r_gafcf50334903013177a8c6f4e36b8d6fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcf50334903013177a8c6f4e36b8d6fe">I2C_SR2_SMBDEFAULT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa390034d42a7873287b68e9ae3935a26">I2C_SR2_SMBDEFAULT_Msk</a></td></tr>
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<tr class="separator:gafcf50334903013177a8c6f4e36b8d6fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3da82932b239f193ac2f57f87c3b1f0" id="r_gab3da82932b239f193ac2f57f87c3b1f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3da82932b239f193ac2f57f87c3b1f0">I2C_SR2_SMBHOST_Pos</a>   (6U)</td></tr>
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<tr class="separator:gab3da82932b239f193ac2f57f87c3b1f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bd5daae1a83a7a62584be9f601ec52d" id="r_ga6bd5daae1a83a7a62584be9f601ec52d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bd5daae1a83a7a62584be9f601ec52d">I2C_SR2_SMBHOST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3da82932b239f193ac2f57f87c3b1f0">I2C_SR2_SMBHOST_Pos</a>)</td></tr>
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<tr class="separator:ga6bd5daae1a83a7a62584be9f601ec52d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa07cf3e404f9f57e98d1ba3793079c80" id="r_gaa07cf3e404f9f57e98d1ba3793079c80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa07cf3e404f9f57e98d1ba3793079c80">I2C_SR2_SMBHOST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6bd5daae1a83a7a62584be9f601ec52d">I2C_SR2_SMBHOST_Msk</a></td></tr>
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<tr class="separator:gaa07cf3e404f9f57e98d1ba3793079c80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga546ae463133d2c719996689e24e61e1f" id="r_ga546ae463133d2c719996689e24e61e1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga546ae463133d2c719996689e24e61e1f">I2C_SR2_DUALF_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga546ae463133d2c719996689e24e61e1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga338ddbff50ca2b01dacc4b8e93014f30" id="r_ga338ddbff50ca2b01dacc4b8e93014f30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga338ddbff50ca2b01dacc4b8e93014f30">I2C_SR2_DUALF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga546ae463133d2c719996689e24e61e1f">I2C_SR2_DUALF_Pos</a>)</td></tr>
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<tr class="separator:ga338ddbff50ca2b01dacc4b8e93014f30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79a6a21835e06d9bc48009f4269b7798" id="r_ga79a6a21835e06d9bc48009f4269b7798"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79a6a21835e06d9bc48009f4269b7798">I2C_SR2_DUALF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga338ddbff50ca2b01dacc4b8e93014f30">I2C_SR2_DUALF_Msk</a></td></tr>
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<tr class="separator:ga79a6a21835e06d9bc48009f4269b7798"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga332f5e12ed830e7d99b241549220a3c0" id="r_ga332f5e12ed830e7d99b241549220a3c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga332f5e12ed830e7d99b241549220a3c0">I2C_SR2_PEC_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga332f5e12ed830e7d99b241549220a3c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a9dceb742f98aa0f27e5ae8dc427a88" id="r_ga5a9dceb742f98aa0f27e5ae8dc427a88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a9dceb742f98aa0f27e5ae8dc427a88">I2C_SR2_PEC_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga332f5e12ed830e7d99b241549220a3c0">I2C_SR2_PEC_Pos</a>)</td></tr>
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<tr class="separator:ga5a9dceb742f98aa0f27e5ae8dc427a88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a4fd5d9c9e2593be920d19a5f6ae732" id="r_ga4a4fd5d9c9e2593be920d19a5f6ae732"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a4fd5d9c9e2593be920d19a5f6ae732">I2C_SR2_PEC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a9dceb742f98aa0f27e5ae8dc427a88">I2C_SR2_PEC_Msk</a></td></tr>
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<tr class="separator:ga4a4fd5d9c9e2593be920d19a5f6ae732"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga908f5b1edffdedba90f8bbb141eedb8a" id="r_ga908f5b1edffdedba90f8bbb141eedb8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga908f5b1edffdedba90f8bbb141eedb8a">I2C_CCR_CCR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga908f5b1edffdedba90f8bbb141eedb8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3f68b672f4ff2fa9a6ba3e79e9e302b" id="r_gaf3f68b672f4ff2fa9a6ba3e79e9e302b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3f68b672f4ff2fa9a6ba3e79e9e302b">I2C_CCR_CCR_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga908f5b1edffdedba90f8bbb141eedb8a">I2C_CCR_CCR_Pos</a>)</td></tr>
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<tr class="memitem:ga5c8cb2bd83dd7dbdcf6ca4bbf4a841de" id="r_ga5c8cb2bd83dd7dbdcf6ca4bbf4a841de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c8cb2bd83dd7dbdcf6ca4bbf4a841de">I2C_CCR_CCR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3f68b672f4ff2fa9a6ba3e79e9e302b">I2C_CCR_CCR_Msk</a></td></tr>
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<tr class="separator:ga5c8cb2bd83dd7dbdcf6ca4bbf4a841de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga152abc0c5a01abf887e702cbc9fe4f49" id="r_ga152abc0c5a01abf887e702cbc9fe4f49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga152abc0c5a01abf887e702cbc9fe4f49">I2C_CCR_DUTY_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga152abc0c5a01abf887e702cbc9fe4f49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e91ff511dab94ae774aaa9c3052fbc6" id="r_ga7e91ff511dab94ae774aaa9c3052fbc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e91ff511dab94ae774aaa9c3052fbc6">I2C_CCR_DUTY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga152abc0c5a01abf887e702cbc9fe4f49">I2C_CCR_DUTY_Pos</a>)</td></tr>
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<tr class="separator:ga7e91ff511dab94ae774aaa9c3052fbc6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga851c8a6b598d54c1a805b1632a4078e5" id="r_ga851c8a6b598d54c1a805b1632a4078e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga851c8a6b598d54c1a805b1632a4078e5">I2C_CCR_DUTY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e91ff511dab94ae774aaa9c3052fbc6">I2C_CCR_DUTY_Msk</a></td></tr>
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<tr class="separator:ga851c8a6b598d54c1a805b1632a4078e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga017a81aea2e87d24a49e078079d72313" id="r_ga017a81aea2e87d24a49e078079d72313"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga017a81aea2e87d24a49e078079d72313">I2C_CCR_FS_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga017a81aea2e87d24a49e078079d72313"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1823d70e520da08c5b40320ed2f8331e" id="r_ga1823d70e520da08c5b40320ed2f8331e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1823d70e520da08c5b40320ed2f8331e">I2C_CCR_FS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga017a81aea2e87d24a49e078079d72313">I2C_CCR_FS_Pos</a>)</td></tr>
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<tr class="separator:ga1823d70e520da08c5b40320ed2f8331e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea64e5d7eba609ac9a84964bc0bc2def" id="r_gaea64e5d7eba609ac9a84964bc0bc2def"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea64e5d7eba609ac9a84964bc0bc2def">I2C_CCR_FS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1823d70e520da08c5b40320ed2f8331e">I2C_CCR_FS_Msk</a></td></tr>
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<tr class="separator:gaea64e5d7eba609ac9a84964bc0bc2def"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb08ecb9599f81e5112a25142cb0e98f" id="r_gafb08ecb9599f81e5112a25142cb0e98f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb08ecb9599f81e5112a25142cb0e98f">I2C_TRISE_TRISE_Pos</a>   (0U)</td></tr>
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<tr class="separator:gafb08ecb9599f81e5112a25142cb0e98f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a3152b3f16c453126cc1cef41b765fe" id="r_ga8a3152b3f16c453126cc1cef41b765fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a3152b3f16c453126cc1cef41b765fe">I2C_TRISE_TRISE_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafb08ecb9599f81e5112a25142cb0e98f">I2C_TRISE_TRISE_Pos</a>)</td></tr>
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<tr class="separator:ga8a3152b3f16c453126cc1cef41b765fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff77a39aba630647af62dc7f1a5dc218" id="r_gaff77a39aba630647af62dc7f1a5dc218"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff77a39aba630647af62dc7f1a5dc218">I2C_TRISE_TRISE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a3152b3f16c453126cc1cef41b765fe">I2C_TRISE_TRISE_Msk</a></td></tr>
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<tr class="separator:gaff77a39aba630647af62dc7f1a5dc218"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a5d1982414442435695ce911fc91b3c" id="r_ga6a5d1982414442435695ce911fc91b3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a5d1982414442435695ce911fc91b3c">IWDG_KR_KEY_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga6a5d1982414442435695ce911fc91b3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ccb19a688f8e5b1c41626d3718db07e" id="r_ga4ccb19a688f8e5b1c41626d3718db07e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ccb19a688f8e5b1c41626d3718db07e">IWDG_KR_KEY_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a5d1982414442435695ce911fc91b3c">IWDG_KR_KEY_Pos</a>)</td></tr>
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<tr class="separator:ga4ccb19a688f8e5b1c41626d3718db07e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga957f7d5f8a0ec1a6956a7f05cfbd97c2" id="r_ga957f7d5f8a0ec1a6956a7f05cfbd97c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga957f7d5f8a0ec1a6956a7f05cfbd97c2">IWDG_KR_KEY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ccb19a688f8e5b1c41626d3718db07e">IWDG_KR_KEY_Msk</a></td></tr>
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<tr class="separator:ga957f7d5f8a0ec1a6956a7f05cfbd97c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25d9c482d27bbc46b08d321c79d058e7" id="r_ga25d9c482d27bbc46b08d321c79d058e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25d9c482d27bbc46b08d321c79d058e7">IWDG_PR_PR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga25d9c482d27bbc46b08d321c79d058e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75390b0bbc7eb3073a88536fe7f1c5ff" id="r_ga75390b0bbc7eb3073a88536fe7f1c5ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75390b0bbc7eb3073a88536fe7f1c5ff">IWDG_PR_PR_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25d9c482d27bbc46b08d321c79d058e7">IWDG_PR_PR_Pos</a>)</td></tr>
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<tr class="separator:ga75390b0bbc7eb3073a88536fe7f1c5ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4de39c5672f17d326fceb5adc9adc090" id="r_ga4de39c5672f17d326fceb5adc9adc090"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4de39c5672f17d326fceb5adc9adc090">IWDG_PR_PR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga75390b0bbc7eb3073a88536fe7f1c5ff">IWDG_PR_PR_Msk</a></td></tr>
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<tr class="separator:ga4de39c5672f17d326fceb5adc9adc090"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b727e7882603df1684cbf230520ca76" id="r_ga9b727e7882603df1684cbf230520ca76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b727e7882603df1684cbf230520ca76">IWDG_PR_PR_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25d9c482d27bbc46b08d321c79d058e7">IWDG_PR_PR_Pos</a>)</td></tr>
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<tr class="separator:ga9b727e7882603df1684cbf230520ca76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafba2551b90c68d95c736a116224b473e" id="r_gafba2551b90c68d95c736a116224b473e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafba2551b90c68d95c736a116224b473e">IWDG_PR_PR_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25d9c482d27bbc46b08d321c79d058e7">IWDG_PR_PR_Pos</a>)</td></tr>
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<tr class="separator:gafba2551b90c68d95c736a116224b473e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55a1d7fde4e3e724a8644652ba9bb2b9" id="r_ga55a1d7fde4e3e724a8644652ba9bb2b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55a1d7fde4e3e724a8644652ba9bb2b9">IWDG_PR_PR_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25d9c482d27bbc46b08d321c79d058e7">IWDG_PR_PR_Pos</a>)</td></tr>
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<tr class="separator:ga55a1d7fde4e3e724a8644652ba9bb2b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57519650f213ae6a72cf9983d64b8618" id="r_ga57519650f213ae6a72cf9983d64b8618"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57519650f213ae6a72cf9983d64b8618">IWDG_RLR_RL_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga57519650f213ae6a72cf9983d64b8618"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga797562ce090da2d4b6576ba3ec62ad12" id="r_ga797562ce090da2d4b6576ba3ec62ad12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga797562ce090da2d4b6576ba3ec62ad12">IWDG_RLR_RL_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57519650f213ae6a72cf9983d64b8618">IWDG_RLR_RL_Pos</a>)</td></tr>
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<tr class="separator:ga797562ce090da2d4b6576ba3ec62ad12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87024bbb19f26def4c4c1510b22d3033" id="r_ga87024bbb19f26def4c4c1510b22d3033"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87024bbb19f26def4c4c1510b22d3033">IWDG_RLR_RL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga797562ce090da2d4b6576ba3ec62ad12">IWDG_RLR_RL_Msk</a></td></tr>
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<tr class="separator:ga87024bbb19f26def4c4c1510b22d3033"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8174d249dcd092b42f36a09e5e04def1" id="r_ga8174d249dcd092b42f36a09e5e04def1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8174d249dcd092b42f36a09e5e04def1">IWDG_SR_PVU_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8174d249dcd092b42f36a09e5e04def1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e966837f97df9cde2383682f0234a96" id="r_ga7e966837f97df9cde2383682f0234a96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e966837f97df9cde2383682f0234a96">IWDG_SR_PVU_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8174d249dcd092b42f36a09e5e04def1">IWDG_SR_PVU_Pos</a>)</td></tr>
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<tr class="separator:ga7e966837f97df9cde2383682f0234a96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga269bd5618ba773d32275b93be004c554" id="r_ga269bd5618ba773d32275b93be004c554"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga269bd5618ba773d32275b93be004c554">IWDG_SR_PVU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e966837f97df9cde2383682f0234a96">IWDG_SR_PVU_Msk</a></td></tr>
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<tr class="separator:ga269bd5618ba773d32275b93be004c554"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4aeb9bcef7e84f6760608f5fcd052fec" id="r_ga4aeb9bcef7e84f6760608f5fcd052fec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4aeb9bcef7e84f6760608f5fcd052fec">IWDG_SR_RVU_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga4aeb9bcef7e84f6760608f5fcd052fec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab984dca55296c6bc7aef24d356909c28" id="r_gab984dca55296c6bc7aef24d356909c28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab984dca55296c6bc7aef24d356909c28">IWDG_SR_RVU_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4aeb9bcef7e84f6760608f5fcd052fec">IWDG_SR_RVU_Pos</a>)</td></tr>
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<tr class="separator:gab984dca55296c6bc7aef24d356909c28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadffb8339e556a3b10120b15f0dacc232" id="r_gadffb8339e556a3b10120b15f0dacc232"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadffb8339e556a3b10120b15f0dacc232">IWDG_SR_RVU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab984dca55296c6bc7aef24d356909c28">IWDG_SR_RVU_Msk</a></td></tr>
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<tr class="separator:gadffb8339e556a3b10120b15f0dacc232"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeff985ca572b03cb2b8fb57d72f04163" id="r_gaeff985ca572b03cb2b8fb57d72f04163"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeff985ca572b03cb2b8fb57d72f04163">PWR_CR_LPDS_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaeff985ca572b03cb2b8fb57d72f04163"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15a3e5d29f5816a97918b938fe9882d8" id="r_ga15a3e5d29f5816a97918b938fe9882d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15a3e5d29f5816a97918b938fe9882d8">PWR_CR_LPDS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeff985ca572b03cb2b8fb57d72f04163">PWR_CR_LPDS_Pos</a>)</td></tr>
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<tr class="separator:ga15a3e5d29f5816a97918b938fe9882d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3aeb8d6f2539b0a3a4b851aeba0eea66" id="r_ga3aeb8d6f2539b0a3a4b851aeba0eea66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3aeb8d6f2539b0a3a4b851aeba0eea66">PWR_CR_LPDS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga15a3e5d29f5816a97918b938fe9882d8">PWR_CR_LPDS_Msk</a></td></tr>
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<tr class="memitem:gaf1038bf2ac726320cfe05865bda0a07e" id="r_gaf1038bf2ac726320cfe05865bda0a07e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1038bf2ac726320cfe05865bda0a07e">PWR_CR_PDDS_Pos</a>   (1U)</td></tr>
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<tr class="memitem:gabc8e1dc6252707c24412500e6695fd05" id="r_gabc8e1dc6252707c24412500e6695fd05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc8e1dc6252707c24412500e6695fd05">PWR_CR_PDDS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1038bf2ac726320cfe05865bda0a07e">PWR_CR_PDDS_Pos</a>)</td></tr>
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<tr class="separator:gabc8e1dc6252707c24412500e6695fd05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c8075e98772470804c9e3fe74984115" id="r_ga8c8075e98772470804c9e3fe74984115"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c8075e98772470804c9e3fe74984115">PWR_CR_PDDS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabc8e1dc6252707c24412500e6695fd05">PWR_CR_PDDS_Msk</a></td></tr>
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<tr class="separator:ga8c8075e98772470804c9e3fe74984115"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8725c4a6e67a667c4de1087c9639221f" id="r_ga8725c4a6e67a667c4de1087c9639221f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8725c4a6e67a667c4de1087c9639221f">PWR_CR_CWUF_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga8725c4a6e67a667c4de1087c9639221f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b3f54b99913b0d6413df2b3d2e4790a" id="r_ga0b3f54b99913b0d6413df2b3d2e4790a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b3f54b99913b0d6413df2b3d2e4790a">PWR_CR_CWUF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8725c4a6e67a667c4de1087c9639221f">PWR_CR_CWUF_Pos</a>)</td></tr>
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<tr class="separator:ga0b3f54b99913b0d6413df2b3d2e4790a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3928de64f633b84770b1cfecea702fa7" id="r_ga3928de64f633b84770b1cfecea702fa7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3928de64f633b84770b1cfecea702fa7">PWR_CR_CWUF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b3f54b99913b0d6413df2b3d2e4790a">PWR_CR_CWUF_Msk</a></td></tr>
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<tr class="separator:ga3928de64f633b84770b1cfecea702fa7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga657c1dc4aa1d976d5cb8870ad7791a09" id="r_ga657c1dc4aa1d976d5cb8870ad7791a09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga657c1dc4aa1d976d5cb8870ad7791a09">PWR_CR_CSBF_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga657c1dc4aa1d976d5cb8870ad7791a09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e25040e042ac06128a8cd5f858d8912" id="r_ga8e25040e042ac06128a8cd5f858d8912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e25040e042ac06128a8cd5f858d8912">PWR_CR_CSBF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga657c1dc4aa1d976d5cb8870ad7791a09">PWR_CR_CSBF_Pos</a>)</td></tr>
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<tr class="separator:ga8e25040e042ac06128a8cd5f858d8912"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab44484cacc35c80cf82eb011d6cbe13a" id="r_gab44484cacc35c80cf82eb011d6cbe13a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab44484cacc35c80cf82eb011d6cbe13a">PWR_CR_CSBF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e25040e042ac06128a8cd5f858d8912">PWR_CR_CSBF_Msk</a></td></tr>
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<tr class="separator:gab44484cacc35c80cf82eb011d6cbe13a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb4073cd8adfdba51b106072bab82fc3" id="r_gadb4073cd8adfdba51b106072bab82fc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb4073cd8adfdba51b106072bab82fc3">PWR_CR_PVDE_Pos</a>   (4U)</td></tr>
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<tr class="separator:gadb4073cd8adfdba51b106072bab82fc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f556d56181a41dc59ba75be574155ad" id="r_ga1f556d56181a41dc59ba75be574155ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f556d56181a41dc59ba75be574155ad">PWR_CR_PVDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb4073cd8adfdba51b106072bab82fc3">PWR_CR_PVDE_Pos</a>)</td></tr>
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<tr class="separator:ga1f556d56181a41dc59ba75be574155ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05d5c39759e69a294c0ab9bea8f142e5" id="r_ga05d5c39759e69a294c0ab9bea8f142e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05d5c39759e69a294c0ab9bea8f142e5">PWR_CR_PVDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f556d56181a41dc59ba75be574155ad">PWR_CR_PVDE_Msk</a></td></tr>
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<tr class="separator:ga05d5c39759e69a294c0ab9bea8f142e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73dc96cce80c352f7bda9a3919023eef" id="r_ga73dc96cce80c352f7bda9a3919023eef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73dc96cce80c352f7bda9a3919023eef">PWR_CR_PLS_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga73dc96cce80c352f7bda9a3919023eef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c4e8550b3c0d62156604ce5cdb659a7" id="r_ga5c4e8550b3c0d62156604ce5cdb659a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c4e8550b3c0d62156604ce5cdb659a7">PWR_CR_PLS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga73dc96cce80c352f7bda9a3919023eef">PWR_CR_PLS_Pos</a>)</td></tr>
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<tr class="separator:ga5c4e8550b3c0d62156604ce5cdb659a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac73c24d43953c7598e42acdd4c4e7435" id="r_gac73c24d43953c7598e42acdd4c4e7435"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac73c24d43953c7598e42acdd4c4e7435">PWR_CR_PLS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c4e8550b3c0d62156604ce5cdb659a7">PWR_CR_PLS_Msk</a></td></tr>
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<tr class="separator:gac73c24d43953c7598e42acdd4c4e7435"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacef447510818c468c202e3b4991ea08e" id="r_gacef447510818c468c202e3b4991ea08e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacef447510818c468c202e3b4991ea08e">PWR_CR_PLS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga73dc96cce80c352f7bda9a3919023eef">PWR_CR_PLS_Pos</a>)</td></tr>
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<tr class="separator:gacef447510818c468c202e3b4991ea08e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcd19d78943514a2f695a39b45594623" id="r_gafcd19d78943514a2f695a39b45594623"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcd19d78943514a2f695a39b45594623">PWR_CR_PLS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga73dc96cce80c352f7bda9a3919023eef">PWR_CR_PLS_Pos</a>)</td></tr>
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<tr class="separator:gafcd19d78943514a2f695a39b45594623"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a8986ee557f443d4a8eebf68026bd52" id="r_ga1a8986ee557f443d4a8eebf68026bd52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a8986ee557f443d4a8eebf68026bd52">PWR_CR_PLS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga73dc96cce80c352f7bda9a3919023eef">PWR_CR_PLS_Pos</a>)</td></tr>
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<tr class="separator:ga1a8986ee557f443d4a8eebf68026bd52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb6b904b20d7e4fff958c75748861216" id="r_gacb6b904b20d7e4fff958c75748861216"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb6b904b20d7e4fff958c75748861216">PWR_CR_PLS_LEV0</a>   0x00000000U</td></tr>
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<tr class="separator:gacb6b904b20d7e4fff958c75748861216"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15b71263f73f0c4e53ca91fc8d096818" id="r_ga15b71263f73f0c4e53ca91fc8d096818"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15b71263f73f0c4e53ca91fc8d096818">PWR_CR_PLS_LEV1</a>   0x00000020U</td></tr>
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<tr class="separator:ga15b71263f73f0c4e53ca91fc8d096818"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ea128abc2fc4252b53d09ca2850e69e" id="r_ga2ea128abc2fc4252b53d09ca2850e69e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ea128abc2fc4252b53d09ca2850e69e">PWR_CR_PLS_LEV2</a>   0x00000040U</td></tr>
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<tr class="separator:ga2ea128abc2fc4252b53d09ca2850e69e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c1782980a2fb12de80058729a74f174" id="r_ga9c1782980a2fb12de80058729a74f174"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c1782980a2fb12de80058729a74f174">PWR_CR_PLS_LEV3</a>   0x00000060U</td></tr>
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<tr class="separator:ga9c1782980a2fb12de80058729a74f174"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fe79f097ea6c30a4ccf69ed3e177f85" id="r_ga0fe79f097ea6c30a4ccf69ed3e177f85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fe79f097ea6c30a4ccf69ed3e177f85">PWR_CR_PLS_LEV4</a>   0x00000080U</td></tr>
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<tr class="separator:ga0fe79f097ea6c30a4ccf69ed3e177f85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga326781d09a07b4d215424fbbae11b7b2" id="r_ga326781d09a07b4d215424fbbae11b7b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga326781d09a07b4d215424fbbae11b7b2">PWR_CR_PLS_LEV5</a>   0x000000A0U</td></tr>
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<tr class="separator:ga326781d09a07b4d215424fbbae11b7b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaff17e9c7fe7d837523b1e9a2f4e9baf" id="r_gaaff17e9c7fe7d837523b1e9a2f4e9baf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaff17e9c7fe7d837523b1e9a2f4e9baf">PWR_CR_PLS_LEV6</a>   0x000000C0U</td></tr>
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<tr class="separator:gaaff17e9c7fe7d837523b1e9a2f4e9baf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95e3b301b5470ae94d32c53a9fbdfc8b" id="r_ga95e3b301b5470ae94d32c53a9fbdfc8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95e3b301b5470ae94d32c53a9fbdfc8b">PWR_CR_PLS_LEV7</a>   0x000000E0U</td></tr>
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<tr class="separator:ga95e3b301b5470ae94d32c53a9fbdfc8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3c90e817e3ccc0031b20014ef7d434e" id="r_gaa3c90e817e3ccc0031b20014ef7d434e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3c90e817e3ccc0031b20014ef7d434e">PWR_CR_DBP_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaa3c90e817e3ccc0031b20014ef7d434e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4dc0f910dd014d87bdb0259f89de5f8" id="r_gae4dc0f910dd014d87bdb0259f89de5f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4dc0f910dd014d87bdb0259f89de5f8">PWR_CR_DBP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3c90e817e3ccc0031b20014ef7d434e">PWR_CR_DBP_Pos</a>)</td></tr>
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<tr class="separator:gae4dc0f910dd014d87bdb0259f89de5f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5c65ab845794ef48f09faa2ee44f718" id="r_gaf5c65ab845794ef48f09faa2ee44f718"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5c65ab845794ef48f09faa2ee44f718">PWR_CR_DBP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae4dc0f910dd014d87bdb0259f89de5f8">PWR_CR_DBP_Msk</a></td></tr>
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<tr class="separator:gaf5c65ab845794ef48f09faa2ee44f718"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7d09308d258629a5feea487cf8746c3" id="r_gaa7d09308d258629a5feea487cf8746c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7d09308d258629a5feea487cf8746c3">PWR_CR_FPDS_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaa7d09308d258629a5feea487cf8746c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86e13d0b0eb3f05a11893752cc372677" id="r_ga86e13d0b0eb3f05a11893752cc372677"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86e13d0b0eb3f05a11893752cc372677">PWR_CR_FPDS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7d09308d258629a5feea487cf8746c3">PWR_CR_FPDS_Pos</a>)</td></tr>
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<tr class="separator:ga86e13d0b0eb3f05a11893752cc372677"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc01f8b6d4bd0294f745fde6d8e57002" id="r_gafc01f8b6d4bd0294f745fde6d8e57002"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc01f8b6d4bd0294f745fde6d8e57002">PWR_CR_FPDS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86e13d0b0eb3f05a11893752cc372677">PWR_CR_FPDS_Msk</a></td></tr>
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<tr class="separator:gafc01f8b6d4bd0294f745fde6d8e57002"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f4f27bd20dad692917746ce1f184d28" id="r_ga2f4f27bd20dad692917746ce1f184d28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f4f27bd20dad692917746ce1f184d28">PWR_CR_VOS_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga2f4f27bd20dad692917746ce1f184d28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e94ecdd78a53924cc35417d24fc974a" id="r_ga3e94ecdd78a53924cc35417d24fc974a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e94ecdd78a53924cc35417d24fc974a">PWR_CR_VOS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f4f27bd20dad692917746ce1f184d28">PWR_CR_VOS_Pos</a>)</td></tr>
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<tr class="separator:ga3e94ecdd78a53924cc35417d24fc974a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccc33f1ba4e374e116ffa50f3a503030" id="r_gaccc33f1ba4e374e116ffa50f3a503030"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccc33f1ba4e374e116ffa50f3a503030">PWR_CR_VOS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e94ecdd78a53924cc35417d24fc974a">PWR_CR_VOS_Msk</a></td></tr>
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<tr class="memitem:ga56b78f2f76a841d2e8ddd56299b8d3e2" id="r_ga56b78f2f76a841d2e8ddd56299b8d3e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56b78f2f76a841d2e8ddd56299b8d3e2">PWR_CR_PMODE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaccc33f1ba4e374e116ffa50f3a503030">PWR_CR_VOS</a></td></tr>
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<tr class="separator:ga56b78f2f76a841d2e8ddd56299b8d3e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7e519f8bd84379dc4a94dd5acaff305" id="r_gae7e519f8bd84379dc4a94dd5acaff305"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7e519f8bd84379dc4a94dd5acaff305">PWR_CSR_WUF_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae7e519f8bd84379dc4a94dd5acaff305"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga506641083e85de1202465b9be1712c24" id="r_ga506641083e85de1202465b9be1712c24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga506641083e85de1202465b9be1712c24">PWR_CSR_WUF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae7e519f8bd84379dc4a94dd5acaff305">PWR_CSR_WUF_Pos</a>)</td></tr>
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<tr class="separator:ga506641083e85de1202465b9be1712c24"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9465bb7ad9ca936688344e2a077539e6" id="r_ga9465bb7ad9ca936688344e2a077539e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9465bb7ad9ca936688344e2a077539e6">PWR_CSR_WUF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga506641083e85de1202465b9be1712c24">PWR_CSR_WUF_Msk</a></td></tr>
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<tr class="separator:ga9465bb7ad9ca936688344e2a077539e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28df9eb1abdd9d2f29b3f471f9aa096f" id="r_ga28df9eb1abdd9d2f29b3f471f9aa096f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28df9eb1abdd9d2f29b3f471f9aa096f">PWR_CSR_SBF_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga28df9eb1abdd9d2f29b3f471f9aa096f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab46cab51c4455b5ab8264684e0ca5783" id="r_gab46cab51c4455b5ab8264684e0ca5783"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab46cab51c4455b5ab8264684e0ca5783">PWR_CSR_SBF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga28df9eb1abdd9d2f29b3f471f9aa096f">PWR_CSR_SBF_Pos</a>)</td></tr>
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<tr class="separator:gab46cab51c4455b5ab8264684e0ca5783"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4fd42f153660593cad6f4fe22ff76bb" id="r_gab4fd42f153660593cad6f4fe22ff76bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4fd42f153660593cad6f4fe22ff76bb">PWR_CSR_SBF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab46cab51c4455b5ab8264684e0ca5783">PWR_CSR_SBF_Msk</a></td></tr>
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<tr class="separator:gab4fd42f153660593cad6f4fe22ff76bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdec9406a561d29e05ca2e2f69fd4532" id="r_gacdec9406a561d29e05ca2e2f69fd4532"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdec9406a561d29e05ca2e2f69fd4532">PWR_CSR_PVDO_Pos</a>   (2U)</td></tr>
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<tr class="separator:gacdec9406a561d29e05ca2e2f69fd4532"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c27c44a96fdf582f2b25d00666a9548" id="r_ga4c27c44a96fdf582f2b25d00666a9548"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c27c44a96fdf582f2b25d00666a9548">PWR_CSR_PVDO_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacdec9406a561d29e05ca2e2f69fd4532">PWR_CSR_PVDO_Pos</a>)</td></tr>
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<tr class="separator:ga4c27c44a96fdf582f2b25d00666a9548"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3535ce181895cc00afeb28dcac68d04c" id="r_ga3535ce181895cc00afeb28dcac68d04c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3535ce181895cc00afeb28dcac68d04c">PWR_CSR_PVDO</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c27c44a96fdf582f2b25d00666a9548">PWR_CSR_PVDO_Msk</a></td></tr>
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<tr class="separator:ga3535ce181895cc00afeb28dcac68d04c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa51171d8f6200d89b50ebd63f678b7c1" id="r_gaa51171d8f6200d89b50ebd63f678b7c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa51171d8f6200d89b50ebd63f678b7c1">PWR_CSR_BRR_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaa51171d8f6200d89b50ebd63f678b7c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06752058548d6fbcc57dbc032fdde76d" id="r_ga06752058548d6fbcc57dbc032fdde76d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06752058548d6fbcc57dbc032fdde76d">PWR_CSR_BRR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa51171d8f6200d89b50ebd63f678b7c1">PWR_CSR_BRR_Pos</a>)</td></tr>
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<tr class="separator:ga06752058548d6fbcc57dbc032fdde76d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga939410de980c5bc297ff04bcf30875cc" id="r_ga939410de980c5bc297ff04bcf30875cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga939410de980c5bc297ff04bcf30875cc">PWR_CSR_BRR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06752058548d6fbcc57dbc032fdde76d">PWR_CSR_BRR_Msk</a></td></tr>
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<tr class="separator:ga939410de980c5bc297ff04bcf30875cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20d629ea754e9d5942a97e037d515816" id="r_ga20d629ea754e9d5942a97e037d515816"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20d629ea754e9d5942a97e037d515816">PWR_CSR_EWUP_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga20d629ea754e9d5942a97e037d515816"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac0b862445449f084acf74d1105f687da" id="r_gac0b862445449f084acf74d1105f687da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0b862445449f084acf74d1105f687da">PWR_CSR_EWUP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20d629ea754e9d5942a97e037d515816">PWR_CSR_EWUP_Pos</a>)</td></tr>
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<tr class="separator:gac0b862445449f084acf74d1105f687da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ac8c15a08bbee754ea720b0d4a4f580" id="r_ga7ac8c15a08bbee754ea720b0d4a4f580"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac8c15a08bbee754ea720b0d4a4f580">PWR_CSR_EWUP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac0b862445449f084acf74d1105f687da">PWR_CSR_EWUP_Msk</a></td></tr>
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<tr class="separator:ga7ac8c15a08bbee754ea720b0d4a4f580"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa593af0ab76fabc71e48dce7b04f8acf" id="r_gaa593af0ab76fabc71e48dce7b04f8acf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa593af0ab76fabc71e48dce7b04f8acf">PWR_CSR_BRE_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaa593af0ab76fabc71e48dce7b04f8acf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacaed35bfe3de356d9e6def115ef87b9d" id="r_gacaed35bfe3de356d9e6def115ef87b9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacaed35bfe3de356d9e6def115ef87b9d">PWR_CSR_BRE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa593af0ab76fabc71e48dce7b04f8acf">PWR_CSR_BRE_Pos</a>)</td></tr>
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<tr class="separator:gacaed35bfe3de356d9e6def115ef87b9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f99becaceb185431dbf46fb22718d0a" id="r_ga0f99becaceb185431dbf46fb22718d0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f99becaceb185431dbf46fb22718d0a">PWR_CSR_BRE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacaed35bfe3de356d9e6def115ef87b9d">PWR_CSR_BRE_Msk</a></td></tr>
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<tr class="separator:ga0f99becaceb185431dbf46fb22718d0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2938c00bca7b4425b8289498e781b48" id="r_gad2938c00bca7b4425b8289498e781b48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2938c00bca7b4425b8289498e781b48">PWR_CSR_VOSRDY_Pos</a>   (14U)</td></tr>
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<tr class="separator:gad2938c00bca7b4425b8289498e781b48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac90d2b7cd8836e014ee405815273ba9" id="r_gaac90d2b7cd8836e014ee405815273ba9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac90d2b7cd8836e014ee405815273ba9">PWR_CSR_VOSRDY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2938c00bca7b4425b8289498e781b48">PWR_CSR_VOSRDY_Pos</a>)</td></tr>
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<tr class="separator:gaac90d2b7cd8836e014ee405815273ba9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4126ed19cce54a5411ff8dd440171695" id="r_ga4126ed19cce54a5411ff8dd440171695"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4126ed19cce54a5411ff8dd440171695">PWR_CSR_VOSRDY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac90d2b7cd8836e014ee405815273ba9">PWR_CSR_VOSRDY_Msk</a></td></tr>
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<tr class="separator:ga4126ed19cce54a5411ff8dd440171695"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga017220a84cc5ab813eee18edd6309827" id="r_ga017220a84cc5ab813eee18edd6309827"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga017220a84cc5ab813eee18edd6309827">PWR_CSR_REGRDY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4126ed19cce54a5411ff8dd440171695">PWR_CSR_VOSRDY</a></td></tr>
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<tr class="separator:ga017220a84cc5ab813eee18edd6309827"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24995a185bfa02f4ed0624e1a5921585" id="r_ga24995a185bfa02f4ed0624e1a5921585"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24995a185bfa02f4ed0624e1a5921585">RCC_CR_HSION_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga24995a185bfa02f4ed0624e1a5921585"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21adcb31640b6407baff549c0e7d1af0" id="r_ga21adcb31640b6407baff549c0e7d1af0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21adcb31640b6407baff549c0e7d1af0">RCC_CR_HSION_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24995a185bfa02f4ed0624e1a5921585">RCC_CR_HSION_Pos</a>)</td></tr>
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<tr class="separator:ga21adcb31640b6407baff549c0e7d1af0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4fcacf94a97f7d49a70e089b39cf474" id="r_gaf4fcacf94a97f7d49a70e089b39cf474"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4fcacf94a97f7d49a70e089b39cf474">RCC_CR_HSION</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga21adcb31640b6407baff549c0e7d1af0">RCC_CR_HSION_Msk</a></td></tr>
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<tr class="separator:gaf4fcacf94a97f7d49a70e089b39cf474"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77c32f27431ef9437aa34fb0f1d41da9" id="r_ga77c32f27431ef9437aa34fb0f1d41da9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77c32f27431ef9437aa34fb0f1d41da9">RCC_CR_HSIRDY_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga77c32f27431ef9437aa34fb0f1d41da9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55c613573a83b8399c228dca39063947" id="r_ga55c613573a83b8399c228dca39063947"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55c613573a83b8399c228dca39063947">RCC_CR_HSIRDY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga77c32f27431ef9437aa34fb0f1d41da9">RCC_CR_HSIRDY_Pos</a>)</td></tr>
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<tr class="separator:ga55c613573a83b8399c228dca39063947"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9dbac3f2bc04f04ebafe1e66ae3fcf0d" id="r_ga9dbac3f2bc04f04ebafe1e66ae3fcf0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9dbac3f2bc04f04ebafe1e66ae3fcf0d">RCC_CR_HSIRDY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga55c613573a83b8399c228dca39063947">RCC_CR_HSIRDY_Msk</a></td></tr>
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<tr class="separator:ga9dbac3f2bc04f04ebafe1e66ae3fcf0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1eb6ab7cdd2569af23f9688384d577bb" id="r_ga1eb6ab7cdd2569af23f9688384d577bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1eb6ab7cdd2569af23f9688384d577bb">RCC_CR_HSITRIM_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga1eb6ab7cdd2569af23f9688384d577bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47c875ded980268c8d87803fde1d3add" id="r_ga47c875ded980268c8d87803fde1d3add"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47c875ded980268c8d87803fde1d3add">RCC_CR_HSITRIM_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1eb6ab7cdd2569af23f9688384d577bb">RCC_CR_HSITRIM_Pos</a>)</td></tr>
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<tr class="memitem:ga5cb4397b2095c31660a01b748386aa70" id="r_ga5cb4397b2095c31660a01b748386aa70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5cb4397b2095c31660a01b748386aa70">RCC_CR_HSITRIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47c875ded980268c8d87803fde1d3add">RCC_CR_HSITRIM_Msk</a></td></tr>
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<tr class="memitem:gaab999bbbc1d365d0100d34eaa9f426eb" id="r_gaab999bbbc1d365d0100d34eaa9f426eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab999bbbc1d365d0100d34eaa9f426eb">RCC_CR_HSITRIM_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1eb6ab7cdd2569af23f9688384d577bb">RCC_CR_HSITRIM_Pos</a>)</td></tr>
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<tr class="memitem:ga569d6a29d774e0f125b0c2b3671fae3c" id="r_ga569d6a29d774e0f125b0c2b3671fae3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga569d6a29d774e0f125b0c2b3671fae3c">RCC_CR_HSITRIM_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1eb6ab7cdd2569af23f9688384d577bb">RCC_CR_HSITRIM_Pos</a>)</td></tr>
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<tr class="memitem:ga10d80d64137e36f5183f6aa7002de6f5" id="r_ga10d80d64137e36f5183f6aa7002de6f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10d80d64137e36f5183f6aa7002de6f5">RCC_CR_HSITRIM_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1eb6ab7cdd2569af23f9688384d577bb">RCC_CR_HSITRIM_Pos</a>)</td></tr>
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<tr class="memitem:gafe20245d2d971238dba9ee371a299ba9" id="r_gafe20245d2d971238dba9ee371a299ba9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe20245d2d971238dba9ee371a299ba9">RCC_CR_HSITRIM_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1eb6ab7cdd2569af23f9688384d577bb">RCC_CR_HSITRIM_Pos</a>)</td></tr>
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<tr class="memitem:ga1f9ab2e93a0b9b70d33812bcc5e920c1" id="r_ga1f9ab2e93a0b9b70d33812bcc5e920c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f9ab2e93a0b9b70d33812bcc5e920c1">RCC_CR_HSITRIM_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1eb6ab7cdd2569af23f9688384d577bb">RCC_CR_HSITRIM_Pos</a>)</td></tr>
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<tr class="memitem:gaaca19ae5be8263a15a6122f80820ddab" id="r_gaaca19ae5be8263a15a6122f80820ddab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab">RCC_CR_HSICAL_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga6b0cd0084e6349428abdb91755f0a3d3" id="r_ga6b0cd0084e6349428abdb91755f0a3d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b0cd0084e6349428abdb91755f0a3d3">RCC_CR_HSICAL_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab">RCC_CR_HSICAL_Pos</a>)</td></tr>
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<tr class="memitem:ga67ae770db9851f14ad7c14a693f0f6d3" id="r_ga67ae770db9851f14ad7c14a693f0f6d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67ae770db9851f14ad7c14a693f0f6d3">RCC_CR_HSICAL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b0cd0084e6349428abdb91755f0a3d3">RCC_CR_HSICAL_Msk</a></td></tr>
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<tr class="separator:ga67ae770db9851f14ad7c14a693f0f6d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7daa7754e54d65916ddc54f37274d3a" id="r_gad7daa7754e54d65916ddc54f37274d3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7daa7754e54d65916ddc54f37274d3a">RCC_CR_HSICAL_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab">RCC_CR_HSICAL_Pos</a>)</td></tr>
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<tr class="memitem:ga78054087161dee567cadbb4b4b96fb08" id="r_ga78054087161dee567cadbb4b4b96fb08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78054087161dee567cadbb4b4b96fb08">RCC_CR_HSICAL_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab">RCC_CR_HSICAL_Pos</a>)</td></tr>
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<tr class="memitem:gab0c4bac85beb7de5916897f88150dc3f" id="r_gab0c4bac85beb7de5916897f88150dc3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0c4bac85beb7de5916897f88150dc3f">RCC_CR_HSICAL_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab">RCC_CR_HSICAL_Pos</a>)</td></tr>
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<tr class="memitem:ga03f71cd53f075e9d35fcbfe7ed3f6e12" id="r_ga03f71cd53f075e9d35fcbfe7ed3f6e12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03f71cd53f075e9d35fcbfe7ed3f6e12">RCC_CR_HSICAL_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab">RCC_CR_HSICAL_Pos</a>)</td></tr>
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<tr class="separator:ga03f71cd53f075e9d35fcbfe7ed3f6e12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf26eb00e1872a3754f200a3c32019e50" id="r_gaf26eb00e1872a3754f200a3c32019e50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf26eb00e1872a3754f200a3c32019e50">RCC_CR_HSICAL_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab">RCC_CR_HSICAL_Pos</a>)</td></tr>
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<tr class="separator:gaf26eb00e1872a3754f200a3c32019e50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c5b733061a3c4c6d69a7a15cbcb0b87" id="r_ga4c5b733061a3c4c6d69a7a15cbcb0b87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c5b733061a3c4c6d69a7a15cbcb0b87">RCC_CR_HSICAL_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab">RCC_CR_HSICAL_Pos</a>)</td></tr>
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<tr class="separator:ga4c5b733061a3c4c6d69a7a15cbcb0b87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee2d6b30ee4bf41d2b171adf273a6ee7" id="r_gaee2d6b30ee4bf41d2b171adf273a6ee7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee2d6b30ee4bf41d2b171adf273a6ee7">RCC_CR_HSICAL_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab">RCC_CR_HSICAL_Pos</a>)</td></tr>
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<tr class="separator:gaee2d6b30ee4bf41d2b171adf273a6ee7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab42d5e412867df093ec2ea4b8dc2bf29" id="r_gab42d5e412867df093ec2ea4b8dc2bf29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab42d5e412867df093ec2ea4b8dc2bf29">RCC_CR_HSICAL_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab">RCC_CR_HSICAL_Pos</a>)</td></tr>
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<tr class="separator:gab42d5e412867df093ec2ea4b8dc2bf29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf45a431682229e7131fab4a9df6bb8a" id="r_gacf45a431682229e7131fab4a9df6bb8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf45a431682229e7131fab4a9df6bb8a">RCC_CR_HSEON_Pos</a>   (16U)</td></tr>
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<tr class="separator:gacf45a431682229e7131fab4a9df6bb8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71f5167bea85df0b393de9d3846ea8d1" id="r_ga71f5167bea85df0b393de9d3846ea8d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71f5167bea85df0b393de9d3846ea8d1">RCC_CR_HSEON_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf45a431682229e7131fab4a9df6bb8a">RCC_CR_HSEON_Pos</a>)</td></tr>
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<tr class="separator:ga71f5167bea85df0b393de9d3846ea8d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb8228c9020595b4cf9995137b8c9a7d" id="r_gadb8228c9020595b4cf9995137b8c9a7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb8228c9020595b4cf9995137b8c9a7d">RCC_CR_HSEON</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71f5167bea85df0b393de9d3846ea8d1">RCC_CR_HSEON_Msk</a></td></tr>
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<tr class="separator:gadb8228c9020595b4cf9995137b8c9a7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b35f100d3353d0d73ef1f9099a70285" id="r_ga0b35f100d3353d0d73ef1f9099a70285"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b35f100d3353d0d73ef1f9099a70285">RCC_CR_HSERDY_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga0b35f100d3353d0d73ef1f9099a70285"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga993e8ee50d7049e18ec9ee1e5ddcaa64" id="r_ga993e8ee50d7049e18ec9ee1e5ddcaa64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga993e8ee50d7049e18ec9ee1e5ddcaa64">RCC_CR_HSERDY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b35f100d3353d0d73ef1f9099a70285">RCC_CR_HSERDY_Pos</a>)</td></tr>
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<tr class="separator:ga993e8ee50d7049e18ec9ee1e5ddcaa64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86a34e00182c83409d89ff566cb02cc4" id="r_ga86a34e00182c83409d89ff566cb02cc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86a34e00182c83409d89ff566cb02cc4">RCC_CR_HSERDY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga993e8ee50d7049e18ec9ee1e5ddcaa64">RCC_CR_HSERDY_Msk</a></td></tr>
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<tr class="memitem:gac11714ac23d6cbef2f25c8b6c38e07f9" id="r_gac11714ac23d6cbef2f25c8b6c38e07f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac11714ac23d6cbef2f25c8b6c38e07f9">RCC_CR_HSEBYP_Pos</a>   (18U)</td></tr>
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<tr class="separator:gac11714ac23d6cbef2f25c8b6c38e07f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac04d2021b54bf9a1b66578c67a436b45" id="r_gac04d2021b54bf9a1b66578c67a436b45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac04d2021b54bf9a1b66578c67a436b45">RCC_CR_HSEBYP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac11714ac23d6cbef2f25c8b6c38e07f9">RCC_CR_HSEBYP_Pos</a>)</td></tr>
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<tr class="separator:gac04d2021b54bf9a1b66578c67a436b45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3288090671af5a959aae4d7f7696d55" id="r_gaa3288090671af5a959aae4d7f7696d55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3288090671af5a959aae4d7f7696d55">RCC_CR_HSEBYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac04d2021b54bf9a1b66578c67a436b45">RCC_CR_HSEBYP_Msk</a></td></tr>
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<tr class="separator:gaa3288090671af5a959aae4d7f7696d55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf8f4f358e06d0c2b8a040474c0c75aa" id="r_gabf8f4f358e06d0c2b8a040474c0c75aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf8f4f358e06d0c2b8a040474c0c75aa">RCC_CR_CSSON_Pos</a>   (19U)</td></tr>
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<tr class="separator:gabf8f4f358e06d0c2b8a040474c0c75aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf02f4983b7cd9e1b664729cf6abb1f5" id="r_gaaf02f4983b7cd9e1b664729cf6abb1f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf02f4983b7cd9e1b664729cf6abb1f5">RCC_CR_CSSON_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf8f4f358e06d0c2b8a040474c0c75aa">RCC_CR_CSSON_Pos</a>)</td></tr>
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<tr class="separator:gaaf02f4983b7cd9e1b664729cf6abb1f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc05308869ad055e1e6f2c32d738aecd" id="r_gacc05308869ad055e1e6f2c32d738aecd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc05308869ad055e1e6f2c32d738aecd">RCC_CR_CSSON</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf02f4983b7cd9e1b664729cf6abb1f5">RCC_CR_CSSON_Msk</a></td></tr>
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<tr class="separator:gacc05308869ad055e1e6f2c32d738aecd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9969597c000e9ed714c2472e019f7df3" id="r_ga9969597c000e9ed714c2472e019f7df3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9969597c000e9ed714c2472e019f7df3">RCC_CR_PLLON_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga9969597c000e9ed714c2472e019f7df3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60dd7c471ec3ba4587e0cecdc8238f87" id="r_ga60dd7c471ec3ba4587e0cecdc8238f87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60dd7c471ec3ba4587e0cecdc8238f87">RCC_CR_PLLON_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9969597c000e9ed714c2472e019f7df3">RCC_CR_PLLON_Pos</a>)</td></tr>
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<tr class="separator:ga60dd7c471ec3ba4587e0cecdc8238f87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0e73d5b0a4883e074d40029b49ee47e" id="r_gad0e73d5b0a4883e074d40029b49ee47e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0e73d5b0a4883e074d40029b49ee47e">RCC_CR_PLLON</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga60dd7c471ec3ba4587e0cecdc8238f87">RCC_CR_PLLON_Msk</a></td></tr>
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<tr class="separator:gad0e73d5b0a4883e074d40029b49ee47e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa99ebf56183320b517b804fbc76e8ce4" id="r_gaa99ebf56183320b517b804fbc76e8ce4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa99ebf56183320b517b804fbc76e8ce4">RCC_CR_PLLRDY_Pos</a>   (25U)</td></tr>
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<tr class="memitem:ga237ae9216a3ae5c1f6833a52995413df" id="r_ga237ae9216a3ae5c1f6833a52995413df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga237ae9216a3ae5c1f6833a52995413df">RCC_CR_PLLRDY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa99ebf56183320b517b804fbc76e8ce4">RCC_CR_PLLRDY_Pos</a>)</td></tr>
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<tr class="memitem:gafa12d7ac6a7f0f91d066aeb2c6071888" id="r_gafa12d7ac6a7f0f91d066aeb2c6071888"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa12d7ac6a7f0f91d066aeb2c6071888">RCC_CR_PLLRDY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga237ae9216a3ae5c1f6833a52995413df">RCC_CR_PLLRDY_Msk</a></td></tr>
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<tr class="memitem:gac48c0893e590b49fa8079830a0ae8abb" id="r_gac48c0893e590b49fa8079830a0ae8abb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac48c0893e590b49fa8079830a0ae8abb">RCC_PLLI2S_SUPPORT</a></td></tr>
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<tr class="memitem:ga6c0b3e1822ce926499c6912929b96733" id="r_ga6c0b3e1822ce926499c6912929b96733"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c0b3e1822ce926499c6912929b96733">RCC_CR_PLLI2SON_Pos</a>   (26U)</td></tr>
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<tr class="memitem:ga82caf73e368dd6e0af79ffff40c4c158" id="r_ga82caf73e368dd6e0af79ffff40c4c158"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82caf73e368dd6e0af79ffff40c4c158">RCC_CR_PLLI2SON_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c0b3e1822ce926499c6912929b96733">RCC_CR_PLLI2SON_Pos</a>)</td></tr>
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<tr class="memitem:ga3ccb8964b640530f1080f9ea549d8133" id="r_ga3ccb8964b640530f1080f9ea549d8133"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ccb8964b640530f1080f9ea549d8133">RCC_CR_PLLI2SON</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga82caf73e368dd6e0af79ffff40c4c158">RCC_CR_PLLI2SON_Msk</a></td></tr>
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<tr class="memitem:gadcd54f910af8002a097dd8f827960112" id="r_gadcd54f910af8002a097dd8f827960112"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcd54f910af8002a097dd8f827960112">RCC_CR_PLLI2SRDY_Pos</a>   (27U)</td></tr>
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<tr class="memitem:gac102f1739d82c9f002f6d107e37c6d63" id="r_gac102f1739d82c9f002f6d107e37c6d63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac102f1739d82c9f002f6d107e37c6d63">RCC_CR_PLLI2SRDY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadcd54f910af8002a097dd8f827960112">RCC_CR_PLLI2SRDY_Pos</a>)</td></tr>
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<tr class="memitem:ga7354703f289244a71753debf3ae26e46" id="r_ga7354703f289244a71753debf3ae26e46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7354703f289244a71753debf3ae26e46">RCC_CR_PLLI2SRDY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac102f1739d82c9f002f6d107e37c6d63">RCC_CR_PLLI2SRDY_Msk</a></td></tr>
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<tr class="memitem:ga681f0ec251dffb419df8fa23137fe810" id="r_ga681f0ec251dffb419df8fa23137fe810"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga681f0ec251dffb419df8fa23137fe810">RCC_PLLCFGR_PLLM_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga04d893187396788d18a3eb1cc7028686" id="r_ga04d893187396788d18a3eb1cc7028686"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04d893187396788d18a3eb1cc7028686">RCC_PLLCFGR_PLLM_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga681f0ec251dffb419df8fa23137fe810">RCC_PLLCFGR_PLLM_Pos</a>)</td></tr>
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<tr class="memitem:ga9a42e8b9ee60126976d9be056e5e66b1" id="r_ga9a42e8b9ee60126976d9be056e5e66b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a42e8b9ee60126976d9be056e5e66b1">RCC_PLLCFGR_PLLM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga04d893187396788d18a3eb1cc7028686">RCC_PLLCFGR_PLLM_Msk</a></td></tr>
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<tr class="memitem:ga813e3d6b41b4338ae5aea47a2bdbab01" id="r_ga813e3d6b41b4338ae5aea47a2bdbab01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga813e3d6b41b4338ae5aea47a2bdbab01">RCC_PLLCFGR_PLLM_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga681f0ec251dffb419df8fa23137fe810">RCC_PLLCFGR_PLLM_Pos</a>)</td></tr>
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<tr class="memitem:ga84ae6e7405926717249a9852acda1f10" id="r_ga84ae6e7405926717249a9852acda1f10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84ae6e7405926717249a9852acda1f10">RCC_PLLCFGR_PLLM_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga681f0ec251dffb419df8fa23137fe810">RCC_PLLCFGR_PLLM_Pos</a>)</td></tr>
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<tr class="memitem:ga989f5ea1ac0275a2c15bf09408c8a4c6" id="r_ga989f5ea1ac0275a2c15bf09408c8a4c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga989f5ea1ac0275a2c15bf09408c8a4c6">RCC_PLLCFGR_PLLM_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga681f0ec251dffb419df8fa23137fe810">RCC_PLLCFGR_PLLM_Pos</a>)</td></tr>
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<tr class="memitem:ga9cdeab6a08889692656228ab1186e28c" id="r_ga9cdeab6a08889692656228ab1186e28c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cdeab6a08889692656228ab1186e28c">RCC_PLLCFGR_PLLM_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga681f0ec251dffb419df8fa23137fe810">RCC_PLLCFGR_PLLM_Pos</a>)</td></tr>
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<tr class="memitem:ga20af5f07ceef21b957db9391fd8bd898" id="r_ga20af5f07ceef21b957db9391fd8bd898"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20af5f07ceef21b957db9391fd8bd898">RCC_PLLCFGR_PLLM_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga681f0ec251dffb419df8fa23137fe810">RCC_PLLCFGR_PLLM_Pos</a>)</td></tr>
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<tr class="memitem:ga195dfe1b9b158aa00996867bebd9c225" id="r_ga195dfe1b9b158aa00996867bebd9c225"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga195dfe1b9b158aa00996867bebd9c225">RCC_PLLCFGR_PLLM_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga681f0ec251dffb419df8fa23137fe810">RCC_PLLCFGR_PLLM_Pos</a>)</td></tr>
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<tr class="memitem:ga78a5913e3fc53a740fe874ece04b2d84" id="r_ga78a5913e3fc53a740fe874ece04b2d84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>   (6U)</td></tr>
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<tr class="memitem:gafc41ec903faa2ebee1356f88451a70be" id="r_gafc41ec903faa2ebee1356f88451a70be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc41ec903faa2ebee1356f88451a70be">RCC_PLLCFGR_PLLN_Msk</a>   (0x1FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>)</td></tr>
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<tr class="memitem:ga4b571901d7cdc93ca1ecc1531f26ba6a" id="r_ga4b571901d7cdc93ca1ecc1531f26ba6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b571901d7cdc93ca1ecc1531f26ba6a">RCC_PLLCFGR_PLLN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafc41ec903faa2ebee1356f88451a70be">RCC_PLLCFGR_PLLN_Msk</a></td></tr>
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<tr class="memitem:gade84dfb497ed82c0cbbc40049ef3da2c" id="r_gade84dfb497ed82c0cbbc40049ef3da2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade84dfb497ed82c0cbbc40049ef3da2c">RCC_PLLCFGR_PLLN_0</a>   (0x001UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>)</td></tr>
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<tr class="memitem:gad54b80f8edb3a1f34d390382580edaf3" id="r_gad54b80f8edb3a1f34d390382580edaf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad54b80f8edb3a1f34d390382580edaf3">RCC_PLLCFGR_PLLN_1</a>   (0x002UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>)</td></tr>
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<tr class="memitem:ga6c165a47d134f31f9dff12d1e6f709f3" id="r_ga6c165a47d134f31f9dff12d1e6f709f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c165a47d134f31f9dff12d1e6f709f3">RCC_PLLCFGR_PLLN_2</a>   (0x004UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>)</td></tr>
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<tr class="memitem:ga5b19e3e1f2dbe4c2327ebee7e9647365" id="r_ga5b19e3e1f2dbe4c2327ebee7e9647365"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b19e3e1f2dbe4c2327ebee7e9647365">RCC_PLLCFGR_PLLN_3</a>   (0x008UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>)</td></tr>
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<tr class="memitem:gaeb4707942496f45d3cf85acfdeb37475" id="r_gaeb4707942496f45d3cf85acfdeb37475"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb4707942496f45d3cf85acfdeb37475">RCC_PLLCFGR_PLLN_4</a>   (0x010UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>)</td></tr>
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<tr class="memitem:gaefb9ac3678faab95ddc7d42b2316b8ab" id="r_gaefb9ac3678faab95ddc7d42b2316b8ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefb9ac3678faab95ddc7d42b2316b8ab">RCC_PLLCFGR_PLLN_5</a>   (0x020UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>)</td></tr>
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<tr class="memitem:gaddfba8f0f4b9b772986a0d214dcced39" id="r_gaddfba8f0f4b9b772986a0d214dcced39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddfba8f0f4b9b772986a0d214dcced39">RCC_PLLCFGR_PLLN_6</a>   (0x040UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>)</td></tr>
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<tr class="memitem:ga0df4b12cec2263d6acec32015035fe54" id="r_ga0df4b12cec2263d6acec32015035fe54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0df4b12cec2263d6acec32015035fe54">RCC_PLLCFGR_PLLN_7</a>   (0x080UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>)</td></tr>
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<tr class="memitem:gaff473b6dc417ef6fa361017b2f107c06" id="r_gaff473b6dc417ef6fa361017b2f107c06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff473b6dc417ef6fa361017b2f107c06">RCC_PLLCFGR_PLLN_8</a>   (0x100UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84">RCC_PLLCFGR_PLLN_Pos</a>)</td></tr>
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<tr class="memitem:gaa67d9c488f8ce7cc078b2c7ca607d742" id="r_gaa67d9c488f8ce7cc078b2c7ca607d742"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa67d9c488f8ce7cc078b2c7ca607d742">RCC_PLLCFGR_PLLP_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga944643170311f50335c87c581ee11eca" id="r_ga944643170311f50335c87c581ee11eca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga944643170311f50335c87c581ee11eca">RCC_PLLCFGR_PLLP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa67d9c488f8ce7cc078b2c7ca607d742">RCC_PLLCFGR_PLLP_Pos</a>)</td></tr>
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<tr class="memitem:ga2561745be271ee828e26de601f72162d" id="r_ga2561745be271ee828e26de601f72162d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2561745be271ee828e26de601f72162d">RCC_PLLCFGR_PLLP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga944643170311f50335c87c581ee11eca">RCC_PLLCFGR_PLLP_Msk</a></td></tr>
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<tr class="memitem:ga46e5cb0fc1122e12425c26b5ed91bcfd" id="r_ga46e5cb0fc1122e12425c26b5ed91bcfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46e5cb0fc1122e12425c26b5ed91bcfd">RCC_PLLCFGR_PLLP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa67d9c488f8ce7cc078b2c7ca607d742">RCC_PLLCFGR_PLLP_Pos</a>)</td></tr>
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<tr class="memitem:gaba4ddc9eb3b629852127551eeae77f73" id="r_gaba4ddc9eb3b629852127551eeae77f73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba4ddc9eb3b629852127551eeae77f73">RCC_PLLCFGR_PLLP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa67d9c488f8ce7cc078b2c7ca607d742">RCC_PLLCFGR_PLLP_Pos</a>)</td></tr>
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<tr class="memitem:gae44f5b0b3eaa9d6f11eac2a8b1328cd7" id="r_gae44f5b0b3eaa9d6f11eac2a8b1328cd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae44f5b0b3eaa9d6f11eac2a8b1328cd7">RCC_PLLCFGR_PLLSRC_Pos</a>   (22U)</td></tr>
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<tr class="memitem:ga30516f483e85323f76dab980af3be393" id="r_ga30516f483e85323f76dab980af3be393"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30516f483e85323f76dab980af3be393">RCC_PLLCFGR_PLLSRC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae44f5b0b3eaa9d6f11eac2a8b1328cd7">RCC_PLLCFGR_PLLSRC_Pos</a>)</td></tr>
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<tr class="memitem:ga92cb53ea81d2c47537eb217cc6659a2e" id="r_ga92cb53ea81d2c47537eb217cc6659a2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92cb53ea81d2c47537eb217cc6659a2e">RCC_PLLCFGR_PLLSRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga30516f483e85323f76dab980af3be393">RCC_PLLCFGR_PLLSRC_Msk</a></td></tr>
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<tr class="memitem:ga21e65d80de700a9c5f202f1c7c777679" id="r_ga21e65d80de700a9c5f202f1c7c777679"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21e65d80de700a9c5f202f1c7c777679">RCC_PLLCFGR_PLLSRC_HSE_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga21e65d80de700a9c5f202f1c7c777679"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga858f2c21bc43e423136f370f6c410909" id="r_ga858f2c21bc43e423136f370f6c410909"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga858f2c21bc43e423136f370f6c410909">RCC_PLLCFGR_PLLSRC_HSE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21e65d80de700a9c5f202f1c7c777679">RCC_PLLCFGR_PLLSRC_HSE_Pos</a>)</td></tr>
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<tr class="memitem:gae3a86c3918526efe2258ecbb34b91587" id="r_gae3a86c3918526efe2258ecbb34b91587"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3a86c3918526efe2258ecbb34b91587">RCC_PLLCFGR_PLLSRC_HSE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga858f2c21bc43e423136f370f6c410909">RCC_PLLCFGR_PLLSRC_HSE_Msk</a></td></tr>
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<tr class="memitem:gadf688c4f038f29247cc0280dbdda24a7" id="r_gadf688c4f038f29247cc0280dbdda24a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf688c4f038f29247cc0280dbdda24a7">RCC_PLLCFGR_PLLSRC_HSI</a>   0x00000000U</td></tr>
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<tr class="memitem:gac574324eee39c3dcee75b37d7728c9ae" id="r_gac574324eee39c3dcee75b37d7728c9ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac574324eee39c3dcee75b37d7728c9ae">RCC_PLLCFGR_PLLQ_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga61e97c300a1e833572204b270398158f" id="r_ga61e97c300a1e833572204b270398158f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61e97c300a1e833572204b270398158f">RCC_PLLCFGR_PLLQ_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac574324eee39c3dcee75b37d7728c9ae">RCC_PLLCFGR_PLLQ_Pos</a>)</td></tr>
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<tr class="memitem:ga546495f69f570cb4b81d4a59054c7ed1" id="r_ga546495f69f570cb4b81d4a59054c7ed1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga546495f69f570cb4b81d4a59054c7ed1">RCC_PLLCFGR_PLLQ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga61e97c300a1e833572204b270398158f">RCC_PLLCFGR_PLLQ_Msk</a></td></tr>
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<tr class="memitem:ga56fe140a22f66d2dd7250bb1f39ab451" id="r_ga56fe140a22f66d2dd7250bb1f39ab451"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56fe140a22f66d2dd7250bb1f39ab451">RCC_PLLCFGR_PLLQ_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac574324eee39c3dcee75b37d7728c9ae">RCC_PLLCFGR_PLLQ_Pos</a>)</td></tr>
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<tr class="memitem:ga7703def670b8ef3ec634f8f09a56ce00" id="r_ga7703def670b8ef3ec634f8f09a56ce00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7703def670b8ef3ec634f8f09a56ce00">RCC_PLLCFGR_PLLQ_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac574324eee39c3dcee75b37d7728c9ae">RCC_PLLCFGR_PLLQ_Pos</a>)</td></tr>
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<tr class="memitem:ga45ab5c1d1a26d34915a53de7013f6cf6" id="r_ga45ab5c1d1a26d34915a53de7013f6cf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45ab5c1d1a26d34915a53de7013f6cf6">RCC_PLLCFGR_PLLQ_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac574324eee39c3dcee75b37d7728c9ae">RCC_PLLCFGR_PLLQ_Pos</a>)</td></tr>
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<tr class="memitem:ga182a9e6e5d5e1c63a1d20daf9b1874b5" id="r_ga182a9e6e5d5e1c63a1d20daf9b1874b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga182a9e6e5d5e1c63a1d20daf9b1874b5">RCC_PLLCFGR_PLLQ_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac574324eee39c3dcee75b37d7728c9ae">RCC_PLLCFGR_PLLQ_Pos</a>)</td></tr>
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<tr class="memitem:ga0cf9dd749ab13a3b9d55308e24f60160" id="r_ga0cf9dd749ab13a3b9d55308e24f60160"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cf9dd749ab13a3b9d55308e24f60160">RCC_CFGR_SW_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0cf9dd749ab13a3b9d55308e24f60160"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06ad7777386bbf5555ef8b02939197aa" id="r_ga06ad7777386bbf5555ef8b02939197aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06ad7777386bbf5555ef8b02939197aa">RCC_CFGR_SW_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cf9dd749ab13a3b9d55308e24f60160">RCC_CFGR_SW_Pos</a>)</td></tr>
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<tr class="separator:ga06ad7777386bbf5555ef8b02939197aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0eea5e5f7743a7e8995b8beeb18355c1" id="r_ga0eea5e5f7743a7e8995b8beeb18355c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0eea5e5f7743a7e8995b8beeb18355c1">RCC_CFGR_SW</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06ad7777386bbf5555ef8b02939197aa">RCC_CFGR_SW_Msk</a></td></tr>
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<tr class="memitem:ga99f08d86fd41824058a7fdf817f7e2fd" id="r_ga99f08d86fd41824058a7fdf817f7e2fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99f08d86fd41824058a7fdf817f7e2fd">RCC_CFGR_SW_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cf9dd749ab13a3b9d55308e24f60160">RCC_CFGR_SW_Pos</a>)</td></tr>
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<tr class="memitem:ga72d51cb5d66ee1aa4d2c6f14796a072f" id="r_ga72d51cb5d66ee1aa4d2c6f14796a072f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72d51cb5d66ee1aa4d2c6f14796a072f">RCC_CFGR_SW_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cf9dd749ab13a3b9d55308e24f60160">RCC_CFGR_SW_Pos</a>)</td></tr>
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<tr class="separator:ga72d51cb5d66ee1aa4d2c6f14796a072f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbac8bae4f0808b3c3a5185aa10081fb" id="r_gacbac8bae4f0808b3c3a5185aa10081fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbac8bae4f0808b3c3a5185aa10081fb">RCC_CFGR_SW_HSI</a>   0x00000000U</td></tr>
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<tr class="separator:gacbac8bae4f0808b3c3a5185aa10081fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb563f217242d969f4355d0818fde705" id="r_gafb563f217242d969f4355d0818fde705"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb563f217242d969f4355d0818fde705">RCC_CFGR_SW_HSE</a>   0x00000001U</td></tr>
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<tr class="separator:gafb563f217242d969f4355d0818fde705"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87389cacb2eaf53730da13a2a33cd487" id="r_ga87389cacb2eaf53730da13a2a33cd487"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87389cacb2eaf53730da13a2a33cd487">RCC_CFGR_SW_PLL</a>   0x00000002U</td></tr>
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<tr class="memitem:gab79d13a977d5b0c2e132b4939663158d" id="r_gab79d13a977d5b0c2e132b4939663158d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab79d13a977d5b0c2e132b4939663158d">RCC_CFGR_SWS_Pos</a>   (2U)</td></tr>
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<tr class="separator:gab79d13a977d5b0c2e132b4939663158d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef0b6cd7629c047bcc4ac3e88d920e25" id="r_gaef0b6cd7629c047bcc4ac3e88d920e25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef0b6cd7629c047bcc4ac3e88d920e25">RCC_CFGR_SWS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab79d13a977d5b0c2e132b4939663158d">RCC_CFGR_SWS_Pos</a>)</td></tr>
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<tr class="separator:gaef0b6cd7629c047bcc4ac3e88d920e25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15bf2269500dc97e137315f44aa015c9" id="r_ga15bf2269500dc97e137315f44aa015c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15bf2269500dc97e137315f44aa015c9">RCC_CFGR_SWS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaef0b6cd7629c047bcc4ac3e88d920e25">RCC_CFGR_SWS_Msk</a></td></tr>
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<tr class="separator:ga15bf2269500dc97e137315f44aa015c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1eae59112c51def51979e31e8695b39f" id="r_ga1eae59112c51def51979e31e8695b39f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1eae59112c51def51979e31e8695b39f">RCC_CFGR_SWS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab79d13a977d5b0c2e132b4939663158d">RCC_CFGR_SWS_Pos</a>)</td></tr>
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<tr class="memitem:gaad3a5718999d7259f216137a23c2a379" id="r_gaad3a5718999d7259f216137a23c2a379"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad3a5718999d7259f216137a23c2a379">RCC_CFGR_SWS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab79d13a977d5b0c2e132b4939663158d">RCC_CFGR_SWS_Pos</a>)</td></tr>
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<tr class="memitem:ga6764639cf221e1ebc0b5448dcaed590a" id="r_ga6764639cf221e1ebc0b5448dcaed590a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6764639cf221e1ebc0b5448dcaed590a">RCC_CFGR_SWS_HSI</a>   0x00000000U</td></tr>
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<tr class="memitem:gae09a0202f441c1a43e69c62331d50a08" id="r_gae09a0202f441c1a43e69c62331d50a08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae09a0202f441c1a43e69c62331d50a08">RCC_CFGR_SWS_HSE</a>   0x00000004U</td></tr>
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<tr class="separator:gae09a0202f441c1a43e69c62331d50a08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c67e2279804a83ef24438267d9d4a6c" id="r_ga2c67e2279804a83ef24438267d9d4a6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c67e2279804a83ef24438267d9d4a6c">RCC_CFGR_SWS_PLL</a>   0x00000008U</td></tr>
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<tr class="memitem:ga2447eb7ab6388f0446e7550df8f50d90" id="r_ga2447eb7ab6388f0446e7550df8f50d90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2447eb7ab6388f0446e7550df8f50d90">RCC_CFGR_HPRE_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga2447eb7ab6388f0446e7550df8f50d90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65804e0ce7ec3204e9a56bb848428460" id="r_ga65804e0ce7ec3204e9a56bb848428460"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65804e0ce7ec3204e9a56bb848428460">RCC_CFGR_HPRE_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2447eb7ab6388f0446e7550df8f50d90">RCC_CFGR_HPRE_Pos</a>)</td></tr>
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<tr class="memitem:gafe10e66938644ee8054a2426ff23efea" id="r_gafe10e66938644ee8054a2426ff23efea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe10e66938644ee8054a2426ff23efea">RCC_CFGR_HPRE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65804e0ce7ec3204e9a56bb848428460">RCC_CFGR_HPRE_Msk</a></td></tr>
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<tr class="memitem:ga88ece6ca270b3ecf6f63bf20893bc172" id="r_ga88ece6ca270b3ecf6f63bf20893bc172"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88ece6ca270b3ecf6f63bf20893bc172">RCC_CFGR_HPRE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2447eb7ab6388f0446e7550df8f50d90">RCC_CFGR_HPRE_Pos</a>)</td></tr>
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<tr class="memitem:gacbdd3a02814178ba02b8ebbaccd91599" id="r_gacbdd3a02814178ba02b8ebbaccd91599"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbdd3a02814178ba02b8ebbaccd91599">RCC_CFGR_HPRE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2447eb7ab6388f0446e7550df8f50d90">RCC_CFGR_HPRE_Pos</a>)</td></tr>
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<tr class="separator:gacbdd3a02814178ba02b8ebbaccd91599"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadac734bddb507eed4a62a0af4cef74a3" id="r_gadac734bddb507eed4a62a0af4cef74a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadac734bddb507eed4a62a0af4cef74a3">RCC_CFGR_HPRE_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2447eb7ab6388f0446e7550df8f50d90">RCC_CFGR_HPRE_Pos</a>)</td></tr>
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<tr class="separator:gadac734bddb507eed4a62a0af4cef74a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a1180512cc5f3dde7895040a9037286" id="r_ga5a1180512cc5f3dde7895040a9037286"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a1180512cc5f3dde7895040a9037286">RCC_CFGR_HPRE_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2447eb7ab6388f0446e7550df8f50d90">RCC_CFGR_HPRE_Pos</a>)</td></tr>
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<tr class="separator:ga5a1180512cc5f3dde7895040a9037286"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b7d7f29b09a49c31404fc0d44645c84" id="r_ga2b7d7f29b09a49c31404fc0d44645c84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b7d7f29b09a49c31404fc0d44645c84">RCC_CFGR_HPRE_DIV1</a>   0x00000000U</td></tr>
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<tr class="separator:ga2b7d7f29b09a49c31404fc0d44645c84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9eeb5e38e53e79b08a4ac438497ebea" id="r_gaa9eeb5e38e53e79b08a4ac438497ebea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9eeb5e38e53e79b08a4ac438497ebea">RCC_CFGR_HPRE_DIV2</a>   0x00000080U</td></tr>
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<tr class="separator:gaa9eeb5e38e53e79b08a4ac438497ebea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffe860867ae4b1b6d28473ded1546d91" id="r_gaffe860867ae4b1b6d28473ded1546d91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffe860867ae4b1b6d28473ded1546d91">RCC_CFGR_HPRE_DIV4</a>   0x00000090U</td></tr>
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<tr class="separator:gaffe860867ae4b1b6d28473ded1546d91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca71d6b42bdb83b5ff5320578869a058" id="r_gaca71d6b42bdb83b5ff5320578869a058"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca71d6b42bdb83b5ff5320578869a058">RCC_CFGR_HPRE_DIV8</a>   0x000000A0U</td></tr>
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<tr class="separator:gaca71d6b42bdb83b5ff5320578869a058"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3806da4f1afc9e5be0fca001c8c57815" id="r_ga3806da4f1afc9e5be0fca001c8c57815"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3806da4f1afc9e5be0fca001c8c57815">RCC_CFGR_HPRE_DIV16</a>   0x000000B0U</td></tr>
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<tr class="separator:ga3806da4f1afc9e5be0fca001c8c57815"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1caeba8dc2b4c0bb11be600e983e3370" id="r_ga1caeba8dc2b4c0bb11be600e983e3370"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1caeba8dc2b4c0bb11be600e983e3370">RCC_CFGR_HPRE_DIV64</a>   0x000000C0U</td></tr>
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<tr class="separator:ga1caeba8dc2b4c0bb11be600e983e3370"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga280da821f0da1bec1f4c0e132ddf8eab" id="r_ga280da821f0da1bec1f4c0e132ddf8eab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga280da821f0da1bec1f4c0e132ddf8eab">RCC_CFGR_HPRE_DIV128</a>   0x000000D0U</td></tr>
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<tr class="separator:ga280da821f0da1bec1f4c0e132ddf8eab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga089930cedd5b2cb201e717438f29d25b" id="r_ga089930cedd5b2cb201e717438f29d25b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga089930cedd5b2cb201e717438f29d25b">RCC_CFGR_HPRE_DIV256</a>   0x000000E0U</td></tr>
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<tr class="separator:ga089930cedd5b2cb201e717438f29d25b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5088dcbaefc55d4b6693e9b1e595ed0" id="r_gae5088dcbaefc55d4b6693e9b1e595ed0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5088dcbaefc55d4b6693e9b1e595ed0">RCC_CFGR_HPRE_DIV512</a>   0x000000F0U</td></tr>
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<tr class="separator:gae5088dcbaefc55d4b6693e9b1e595ed0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0f0825acc89712f58b97844fbac93ca" id="r_gaf0f0825acc89712f58b97844fbac93ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0f0825acc89712f58b97844fbac93ca">RCC_CFGR_PPRE1_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaf0f0825acc89712f58b97844fbac93ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48842716ad7c2280b8ddbac071cdc773" id="r_ga48842716ad7c2280b8ddbac071cdc773"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48842716ad7c2280b8ddbac071cdc773">RCC_CFGR_PPRE1_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0f0825acc89712f58b97844fbac93ca">RCC_CFGR_PPRE1_Pos</a>)</td></tr>
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<tr class="separator:ga48842716ad7c2280b8ddbac071cdc773"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50b2423a5fea74a47b9eb8ab51869412" id="r_ga50b2423a5fea74a47b9eb8ab51869412"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50b2423a5fea74a47b9eb8ab51869412">RCC_CFGR_PPRE1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga48842716ad7c2280b8ddbac071cdc773">RCC_CFGR_PPRE1_Msk</a></td></tr>
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<tr class="separator:ga50b2423a5fea74a47b9eb8ab51869412"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d37c20686faa340a77021117f5908b7" id="r_ga2d37c20686faa340a77021117f5908b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d37c20686faa340a77021117f5908b7">RCC_CFGR_PPRE1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0f0825acc89712f58b97844fbac93ca">RCC_CFGR_PPRE1_Pos</a>)</td></tr>
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<tr class="separator:ga2d37c20686faa340a77021117f5908b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad41049f8a28fdced6bb4d9267845ffa2" id="r_gad41049f8a28fdced6bb4d9267845ffa2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad41049f8a28fdced6bb4d9267845ffa2">RCC_CFGR_PPRE1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0f0825acc89712f58b97844fbac93ca">RCC_CFGR_PPRE1_Pos</a>)</td></tr>
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<tr class="separator:gad41049f8a28fdced6bb4d9267845ffa2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fcb524f6ca203ddff1862c124d4f89f" id="r_ga5fcb524f6ca203ddff1862c124d4f89f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fcb524f6ca203ddff1862c124d4f89f">RCC_CFGR_PPRE1_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0f0825acc89712f58b97844fbac93ca">RCC_CFGR_PPRE1_Pos</a>)</td></tr>
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<tr class="separator:ga5fcb524f6ca203ddff1862c124d4f89f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8f6562bb2ecf65055a2f42cbb48ef11" id="r_gac8f6562bb2ecf65055a2f42cbb48ef11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8f6562bb2ecf65055a2f42cbb48ef11">RCC_CFGR_PPRE1_DIV1</a>   0x00000000U</td></tr>
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<tr class="separator:gac8f6562bb2ecf65055a2f42cbb48ef11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf832ad6844c907d9bb37c1536defcb0d" id="r_gaf832ad6844c907d9bb37c1536defcb0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf832ad6844c907d9bb37c1536defcb0d">RCC_CFGR_PPRE1_DIV2</a>   0x00001000U</td></tr>
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<tr class="separator:gaf832ad6844c907d9bb37c1536defcb0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e340725f46e9462d9b02a079b9fa8ae" id="r_ga0e340725f46e9462d9b02a079b9fa8ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e340725f46e9462d9b02a079b9fa8ae">RCC_CFGR_PPRE1_DIV4</a>   0x00001400U</td></tr>
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<tr class="separator:ga0e340725f46e9462d9b02a079b9fa8ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ddd6d657837e1971bb86e3bf1c15e72" id="r_ga9ddd6d657837e1971bb86e3bf1c15e72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ddd6d657837e1971bb86e3bf1c15e72">RCC_CFGR_PPRE1_DIV8</a>   0x00001800U</td></tr>
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<tr class="separator:ga9ddd6d657837e1971bb86e3bf1c15e72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c38ba326bde7c7a18c4f7f2aacf823f" id="r_ga5c38ba326bde7c7a18c4f7f2aacf823f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c38ba326bde7c7a18c4f7f2aacf823f">RCC_CFGR_PPRE1_DIV16</a>   0x00001C00U</td></tr>
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<tr class="separator:ga5c38ba326bde7c7a18c4f7f2aacf823f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga562db8b1e75fa862a3652b56a29b9fb6" id="r_ga562db8b1e75fa862a3652b56a29b9fb6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga562db8b1e75fa862a3652b56a29b9fb6">RCC_CFGR_PPRE2_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga562db8b1e75fa862a3652b56a29b9fb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga489e055e843ee5090c0174bbb9af9a67" id="r_ga489e055e843ee5090c0174bbb9af9a67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga489e055e843ee5090c0174bbb9af9a67">RCC_CFGR_PPRE2_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga562db8b1e75fa862a3652b56a29b9fb6">RCC_CFGR_PPRE2_Pos</a>)</td></tr>
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<tr class="separator:ga489e055e843ee5090c0174bbb9af9a67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad61bd4f9f345ba41806813b0bfff1311" id="r_gad61bd4f9f345ba41806813b0bfff1311"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad61bd4f9f345ba41806813b0bfff1311">RCC_CFGR_PPRE2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga489e055e843ee5090c0174bbb9af9a67">RCC_CFGR_PPRE2_Msk</a></td></tr>
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<tr class="separator:gad61bd4f9f345ba41806813b0bfff1311"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82ca63155494ed59eb5e34bec1e5f4e9" id="r_ga82ca63155494ed59eb5e34bec1e5f4e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82ca63155494ed59eb5e34bec1e5f4e9">RCC_CFGR_PPRE2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga562db8b1e75fa862a3652b56a29b9fb6">RCC_CFGR_PPRE2_Pos</a>)</td></tr>
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<tr class="separator:ga82ca63155494ed59eb5e34bec1e5f4e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdb19c9e76fe8e8a7c991714c92e937f" id="r_gafdb19c9e76fe8e8a7c991714c92e937f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdb19c9e76fe8e8a7c991714c92e937f">RCC_CFGR_PPRE2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga562db8b1e75fa862a3652b56a29b9fb6">RCC_CFGR_PPRE2_Pos</a>)</td></tr>
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<tr class="separator:gafdb19c9e76fe8e8a7c991714c92e937f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9adc802687eab5b6ece99a20793219db" id="r_ga9adc802687eab5b6ece99a20793219db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9adc802687eab5b6ece99a20793219db">RCC_CFGR_PPRE2_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga562db8b1e75fa862a3652b56a29b9fb6">RCC_CFGR_PPRE2_Pos</a>)</td></tr>
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<tr class="separator:ga9adc802687eab5b6ece99a20793219db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga247aebf1999a38ea07785558d277bb1a" id="r_ga247aebf1999a38ea07785558d277bb1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga247aebf1999a38ea07785558d277bb1a">RCC_CFGR_PPRE2_DIV1</a>   0x00000000U</td></tr>
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<tr class="memitem:ga99d9c91eaad122460d324a71cc939d1b" id="r_ga99d9c91eaad122460d324a71cc939d1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99d9c91eaad122460d324a71cc939d1b">RCC_CFGR_PPRE2_DIV2</a>   0x00008000U</td></tr>
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<tr class="separator:ga99d9c91eaad122460d324a71cc939d1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4340fc3fc52eca36eb302959fbecb715" id="r_ga4340fc3fc52eca36eb302959fbecb715"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4340fc3fc52eca36eb302959fbecb715">RCC_CFGR_PPRE2_DIV4</a>   0x0000A000U</td></tr>
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<tr class="separator:ga4340fc3fc52eca36eb302959fbecb715"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga412b382a1134e0ee5614e0f4bcf97552" id="r_ga412b382a1134e0ee5614e0f4bcf97552"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga412b382a1134e0ee5614e0f4bcf97552">RCC_CFGR_PPRE2_DIV8</a>   0x0000C000U</td></tr>
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<tr class="separator:ga412b382a1134e0ee5614e0f4bcf97552"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaece3ee58d4138f7452733bfa1ad37eb9" id="r_gaece3ee58d4138f7452733bfa1ad37eb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaece3ee58d4138f7452733bfa1ad37eb9">RCC_CFGR_PPRE2_DIV16</a>   0x0000E000U</td></tr>
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<tr class="memitem:ga2eaafc6a34ae561f23f1139a746cbfd8" id="r_ga2eaafc6a34ae561f23f1139a746cbfd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2eaafc6a34ae561f23f1139a746cbfd8">RCC_CFGR_RTCPRE_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga2eaafc6a34ae561f23f1139a746cbfd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga850304b36d321ade71b90ca011ee5f74" id="r_ga850304b36d321ade71b90ca011ee5f74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga850304b36d321ade71b90ca011ee5f74">RCC_CFGR_RTCPRE_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2eaafc6a34ae561f23f1139a746cbfd8">RCC_CFGR_RTCPRE_Pos</a>)</td></tr>
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<tr class="separator:ga850304b36d321ade71b90ca011ee5f74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7c067c52ecd135252c691aad32c0b83" id="r_gad7c067c52ecd135252c691aad32c0b83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7c067c52ecd135252c691aad32c0b83">RCC_CFGR_RTCPRE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga850304b36d321ade71b90ca011ee5f74">RCC_CFGR_RTCPRE_Msk</a></td></tr>
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<tr class="separator:gad7c067c52ecd135252c691aad32c0b83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga702f887571365eeb42d74b9b9cc6fe0d" id="r_ga702f887571365eeb42d74b9b9cc6fe0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga702f887571365eeb42d74b9b9cc6fe0d">RCC_CFGR_RTCPRE_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2eaafc6a34ae561f23f1139a746cbfd8">RCC_CFGR_RTCPRE_Pos</a>)</td></tr>
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<tr class="separator:ga702f887571365eeb42d74b9b9cc6fe0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1191ba4a2e089f9921d77be57394dec4" id="r_ga1191ba4a2e089f9921d77be57394dec4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1191ba4a2e089f9921d77be57394dec4">RCC_CFGR_RTCPRE_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2eaafc6a34ae561f23f1139a746cbfd8">RCC_CFGR_RTCPRE_Pos</a>)</td></tr>
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<tr class="separator:ga1191ba4a2e089f9921d77be57394dec4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae62885f29418cc83a57964fe631282cb" id="r_gae62885f29418cc83a57964fe631282cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae62885f29418cc83a57964fe631282cb">RCC_CFGR_RTCPRE_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2eaafc6a34ae561f23f1139a746cbfd8">RCC_CFGR_RTCPRE_Pos</a>)</td></tr>
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<tr class="separator:gae62885f29418cc83a57964fe631282cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c703b8d9827f58e7ea783c6a9b74e41" id="r_ga9c703b8d9827f58e7ea783c6a9b74e41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c703b8d9827f58e7ea783c6a9b74e41">RCC_CFGR_RTCPRE_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2eaafc6a34ae561f23f1139a746cbfd8">RCC_CFGR_RTCPRE_Pos</a>)</td></tr>
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<tr class="separator:ga9c703b8d9827f58e7ea783c6a9b74e41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02b93e5154259a1a201bbb9c9b903c0a" id="r_ga02b93e5154259a1a201bbb9c9b903c0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02b93e5154259a1a201bbb9c9b903c0a">RCC_CFGR_RTCPRE_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2eaafc6a34ae561f23f1139a746cbfd8">RCC_CFGR_RTCPRE_Pos</a>)</td></tr>
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<tr class="separator:ga02b93e5154259a1a201bbb9c9b903c0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf44071a1145774e7c5a5ea41cc709c42" id="r_gaf44071a1145774e7c5a5ea41cc709c42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf44071a1145774e7c5a5ea41cc709c42">RCC_CFGR_MCO1_Pos</a>   (21U)</td></tr>
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<tr class="separator:gaf44071a1145774e7c5a5ea41cc709c42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83b21a49230470856ce978e05fb9c47b" id="r_ga83b21a49230470856ce978e05fb9c47b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83b21a49230470856ce978e05fb9c47b">RCC_CFGR_MCO1_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf44071a1145774e7c5a5ea41cc709c42">RCC_CFGR_MCO1_Pos</a>)</td></tr>
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<tr class="separator:ga83b21a49230470856ce978e05fb9c47b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26eb4a66eeff0ba17e9d2a06cf937ca4" id="r_ga26eb4a66eeff0ba17e9d2a06cf937ca4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26eb4a66eeff0ba17e9d2a06cf937ca4">RCC_CFGR_MCO1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga83b21a49230470856ce978e05fb9c47b">RCC_CFGR_MCO1_Msk</a></td></tr>
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<tr class="separator:ga26eb4a66eeff0ba17e9d2a06cf937ca4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe73b3ad484eeecfa1556021677ecf4a" id="r_gafe73b3ad484eeecfa1556021677ecf4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe73b3ad484eeecfa1556021677ecf4a">RCC_CFGR_MCO1_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf44071a1145774e7c5a5ea41cc709c42">RCC_CFGR_MCO1_Pos</a>)</td></tr>
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<tr class="memitem:ga1c7e8d1da534f052ce835f06227a9b7a" id="r_ga1c7e8d1da534f052ce835f06227a9b7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c7e8d1da534f052ce835f06227a9b7a">RCC_CFGR_MCO1_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf44071a1145774e7c5a5ea41cc709c42">RCC_CFGR_MCO1_Pos</a>)</td></tr>
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<tr class="separator:ga1c7e8d1da534f052ce835f06227a9b7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3345cb612da061eb09e7f41b42409e42" id="r_ga3345cb612da061eb09e7f41b42409e42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3345cb612da061eb09e7f41b42409e42">RCC_CFGR_I2SSRC_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga3345cb612da061eb09e7f41b42409e42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadaa5cae9d2b4ddc11fbe5a1858ead900" id="r_gadaa5cae9d2b4ddc11fbe5a1858ead900"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadaa5cae9d2b4ddc11fbe5a1858ead900">RCC_CFGR_I2SSRC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3345cb612da061eb09e7f41b42409e42">RCC_CFGR_I2SSRC_Pos</a>)</td></tr>
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<tr class="separator:gadaa5cae9d2b4ddc11fbe5a1858ead900"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d43413fd6b17bd988ccae9e34296412" id="r_ga5d43413fd6b17bd988ccae9e34296412"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d43413fd6b17bd988ccae9e34296412">RCC_CFGR_I2SSRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadaa5cae9d2b4ddc11fbe5a1858ead900">RCC_CFGR_I2SSRC_Msk</a></td></tr>
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<tr class="separator:ga5d43413fd6b17bd988ccae9e34296412"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12578e7f44e1e03ec5c4fd5987303b1e" id="r_ga12578e7f44e1e03ec5c4fd5987303b1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12578e7f44e1e03ec5c4fd5987303b1e">RCC_CFGR_MCO1PRE_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga12578e7f44e1e03ec5c4fd5987303b1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada571dab4e704e380153b6e901b60ba8" id="r_gada571dab4e704e380153b6e901b60ba8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada571dab4e704e380153b6e901b60ba8">RCC_CFGR_MCO1PRE_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga12578e7f44e1e03ec5c4fd5987303b1e">RCC_CFGR_MCO1PRE_Pos</a>)</td></tr>
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<tr class="separator:gada571dab4e704e380153b6e901b60ba8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23171ca70972a106109a6e0804385ec5" id="r_ga23171ca70972a106109a6e0804385ec5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23171ca70972a106109a6e0804385ec5">RCC_CFGR_MCO1PRE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada571dab4e704e380153b6e901b60ba8">RCC_CFGR_MCO1PRE_Msk</a></td></tr>
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<tr class="separator:ga23171ca70972a106109a6e0804385ec5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8007a9d6ee3fd88912aaf290746ae0e" id="r_gac8007a9d6ee3fd88912aaf290746ae0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8007a9d6ee3fd88912aaf290746ae0e">RCC_CFGR_MCO1PRE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga12578e7f44e1e03ec5c4fd5987303b1e">RCC_CFGR_MCO1PRE_Pos</a>)</td></tr>
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<tr class="separator:gac8007a9d6ee3fd88912aaf290746ae0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf7c1280f61d56b4897f9c876987e092" id="r_gaaf7c1280f61d56b4897f9c876987e092"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf7c1280f61d56b4897f9c876987e092">RCC_CFGR_MCO1PRE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga12578e7f44e1e03ec5c4fd5987303b1e">RCC_CFGR_MCO1PRE_Pos</a>)</td></tr>
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<tr class="separator:gaaf7c1280f61d56b4897f9c876987e092"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11e1d10d1b55e0d88d24212ea2c8ba6e" id="r_ga11e1d10d1b55e0d88d24212ea2c8ba6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11e1d10d1b55e0d88d24212ea2c8ba6e">RCC_CFGR_MCO1PRE_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga12578e7f44e1e03ec5c4fd5987303b1e">RCC_CFGR_MCO1PRE_Pos</a>)</td></tr>
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<tr class="separator:ga11e1d10d1b55e0d88d24212ea2c8ba6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d6ccde3c82ee001935b7cf3d5273923" id="r_ga1d6ccde3c82ee001935b7cf3d5273923"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d6ccde3c82ee001935b7cf3d5273923">RCC_CFGR_MCO2PRE_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga1d6ccde3c82ee001935b7cf3d5273923"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56af08fd6ae55e0047d84c2e5cb44877" id="r_ga56af08fd6ae55e0047d84c2e5cb44877"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56af08fd6ae55e0047d84c2e5cb44877">RCC_CFGR_MCO2PRE_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d6ccde3c82ee001935b7cf3d5273923">RCC_CFGR_MCO2PRE_Pos</a>)</td></tr>
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<tr class="separator:ga56af08fd6ae55e0047d84c2e5cb44877"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae387252f29b6f98cc1fffc4fa0719b6e" id="r_gae387252f29b6f98cc1fffc4fa0719b6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae387252f29b6f98cc1fffc4fa0719b6e">RCC_CFGR_MCO2PRE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga56af08fd6ae55e0047d84c2e5cb44877">RCC_CFGR_MCO2PRE_Msk</a></td></tr>
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<tr class="separator:gae387252f29b6f98cc1fffc4fa0719b6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83dfcd5a1ce89869c82723f7eb9223ed" id="r_ga83dfcd5a1ce89869c82723f7eb9223ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83dfcd5a1ce89869c82723f7eb9223ed">RCC_CFGR_MCO2PRE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d6ccde3c82ee001935b7cf3d5273923">RCC_CFGR_MCO2PRE_Pos</a>)</td></tr>
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<tr class="separator:ga83dfcd5a1ce89869c82723f7eb9223ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e8d7cb746efc7511fa97ddfef2df793" id="r_ga0e8d7cb746efc7511fa97ddfef2df793"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e8d7cb746efc7511fa97ddfef2df793">RCC_CFGR_MCO2PRE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d6ccde3c82ee001935b7cf3d5273923">RCC_CFGR_MCO2PRE_Pos</a>)</td></tr>
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<tr class="separator:ga0e8d7cb746efc7511fa97ddfef2df793"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8773dfae91e6576d490fbee4aa2a639" id="r_gac8773dfae91e6576d490fbee4aa2a639"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8773dfae91e6576d490fbee4aa2a639">RCC_CFGR_MCO2PRE_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d6ccde3c82ee001935b7cf3d5273923">RCC_CFGR_MCO2PRE_Pos</a>)</td></tr>
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<tr class="memitem:ga06b28dad6a8c9bd84cf1f659ddb976a8" id="r_ga06b28dad6a8c9bd84cf1f659ddb976a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06b28dad6a8c9bd84cf1f659ddb976a8">RCC_CFGR_MCO2_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga06b28dad6a8c9bd84cf1f659ddb976a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga193bf927828d92f9249975a792c738d5" id="r_ga193bf927828d92f9249975a792c738d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga193bf927828d92f9249975a792c738d5">RCC_CFGR_MCO2_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga06b28dad6a8c9bd84cf1f659ddb976a8">RCC_CFGR_MCO2_Pos</a>)</td></tr>
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<tr class="memitem:ga022248a1167714f4d847b89243dc5244" id="r_ga022248a1167714f4d847b89243dc5244"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga022248a1167714f4d847b89243dc5244">RCC_CFGR_MCO2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga193bf927828d92f9249975a792c738d5">RCC_CFGR_MCO2_Msk</a></td></tr>
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<tr class="separator:ga022248a1167714f4d847b89243dc5244"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga203156a3f57e2c4498999c7901e0defd" id="r_ga203156a3f57e2c4498999c7901e0defd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga203156a3f57e2c4498999c7901e0defd">RCC_CFGR_MCO2_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga06b28dad6a8c9bd84cf1f659ddb976a8">RCC_CFGR_MCO2_Pos</a>)</td></tr>
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<tr class="memitem:ga2fdba9682ff474255248f84e6851932a" id="r_ga2fdba9682ff474255248f84e6851932a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fdba9682ff474255248f84e6851932a">RCC_CFGR_MCO2_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga06b28dad6a8c9bd84cf1f659ddb976a8">RCC_CFGR_MCO2_Pos</a>)</td></tr>
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<tr class="separator:ga2fdba9682ff474255248f84e6851932a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e24ddcd9380a97107db8d483fdd9cb2" id="r_ga9e24ddcd9380a97107db8d483fdd9cb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e24ddcd9380a97107db8d483fdd9cb2">RCC_CIR_LSIRDYF_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga9e24ddcd9380a97107db8d483fdd9cb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2542dd9dbe634971278d2f4e24c3091" id="r_gac2542dd9dbe634971278d2f4e24c3091"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2542dd9dbe634971278d2f4e24c3091">RCC_CIR_LSIRDYF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e24ddcd9380a97107db8d483fdd9cb2">RCC_CIR_LSIRDYF_Pos</a>)</td></tr>
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<tr class="separator:gac2542dd9dbe634971278d2f4e24c3091"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb94ccfe6a212f020e732d1dd787a6fb" id="r_gacb94ccfe6a212f020e732d1dd787a6fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb94ccfe6a212f020e732d1dd787a6fb">RCC_CIR_LSIRDYF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac2542dd9dbe634971278d2f4e24c3091">RCC_CIR_LSIRDYF_Msk</a></td></tr>
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<tr class="separator:gacb94ccfe6a212f020e732d1dd787a6fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a2be1b77680f922f877e6d1b56287f3" id="r_ga9a2be1b77680f922f877e6d1b56287f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a2be1b77680f922f877e6d1b56287f3">RCC_CIR_LSERDYF_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga9a2be1b77680f922f877e6d1b56287f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58e246b3d87483bf3ca4a55d470acf4f" id="r_ga58e246b3d87483bf3ca4a55d470acf4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58e246b3d87483bf3ca4a55d470acf4f">RCC_CIR_LSERDYF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a2be1b77680f922f877e6d1b56287f3">RCC_CIR_LSERDYF_Pos</a>)</td></tr>
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<tr class="separator:ga58e246b3d87483bf3ca4a55d470acf4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabfc100e7ae673dfcec7be79af0d91dfe" id="r_gabfc100e7ae673dfcec7be79af0d91dfe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfc100e7ae673dfcec7be79af0d91dfe">RCC_CIR_LSERDYF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga58e246b3d87483bf3ca4a55d470acf4f">RCC_CIR_LSERDYF_Msk</a></td></tr>
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<tr class="separator:gabfc100e7ae673dfcec7be79af0d91dfe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8f2d94fb254c9a2fe2c9aadcef7e147" id="r_gab8f2d94fb254c9a2fe2c9aadcef7e147"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8f2d94fb254c9a2fe2c9aadcef7e147">RCC_CIR_HSIRDYF_Pos</a>   (2U)</td></tr>
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<tr class="separator:gab8f2d94fb254c9a2fe2c9aadcef7e147"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c72d692b99c4539982fea718b2ba8a6" id="r_ga8c72d692b99c4539982fea718b2ba8a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c72d692b99c4539982fea718b2ba8a6">RCC_CIR_HSIRDYF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8f2d94fb254c9a2fe2c9aadcef7e147">RCC_CIR_HSIRDYF_Pos</a>)</td></tr>
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<tr class="separator:ga8c72d692b99c4539982fea718b2ba8a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad38877547c4cbbb94659d5726f377163" id="r_gad38877547c4cbbb94659d5726f377163"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad38877547c4cbbb94659d5726f377163">RCC_CIR_HSIRDYF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c72d692b99c4539982fea718b2ba8a6">RCC_CIR_HSIRDYF_Msk</a></td></tr>
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<tr class="separator:gad38877547c4cbbb94659d5726f377163"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37a0fe34b1b1c44c6982a69fa082f6c0" id="r_ga37a0fe34b1b1c44c6982a69fa082f6c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37a0fe34b1b1c44c6982a69fa082f6c0">RCC_CIR_HSERDYF_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga37a0fe34b1b1c44c6982a69fa082f6c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cbcd4b04177bd2420126b0de418de2e" id="r_ga1cbcd4b04177bd2420126b0de418de2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cbcd4b04177bd2420126b0de418de2e">RCC_CIR_HSERDYF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga37a0fe34b1b1c44c6982a69fa082f6c0">RCC_CIR_HSERDYF_Pos</a>)</td></tr>
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<tr class="separator:ga1cbcd4b04177bd2420126b0de418de2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11ea196450aac9ac35e283a66afc3da6" id="r_ga11ea196450aac9ac35e283a66afc3da6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11ea196450aac9ac35e283a66afc3da6">RCC_CIR_HSERDYF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1cbcd4b04177bd2420126b0de418de2e">RCC_CIR_HSERDYF_Msk</a></td></tr>
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<tr class="separator:ga11ea196450aac9ac35e283a66afc3da6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4be890d102ccff40b4e370d575940af5" id="r_ga4be890d102ccff40b4e370d575940af5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4be890d102ccff40b4e370d575940af5">RCC_CIR_PLLRDYF_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga4be890d102ccff40b4e370d575940af5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88d53f154b50703f3ab18f017b7ace1c" id="r_ga88d53f154b50703f3ab18f017b7ace1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88d53f154b50703f3ab18f017b7ace1c">RCC_CIR_PLLRDYF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4be890d102ccff40b4e370d575940af5">RCC_CIR_PLLRDYF_Pos</a>)</td></tr>
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<tr class="separator:ga88d53f154b50703f3ab18f017b7ace1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f007895a17e668f22f7b8b24ca90aec" id="r_ga0f007895a17e668f22f7b8b24ca90aec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f007895a17e668f22f7b8b24ca90aec">RCC_CIR_PLLRDYF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga88d53f154b50703f3ab18f017b7ace1c">RCC_CIR_PLLRDYF_Msk</a></td></tr>
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<tr class="separator:ga0f007895a17e668f22f7b8b24ca90aec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23921a147e121d49592e590f773f3c6c" id="r_ga23921a147e121d49592e590f773f3c6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23921a147e121d49592e590f773f3c6c">RCC_CIR_PLLI2SRDYF_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga23921a147e121d49592e590f773f3c6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61e88621c6cbc397e6c0872c98f11151" id="r_ga61e88621c6cbc397e6c0872c98f11151"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61e88621c6cbc397e6c0872c98f11151">RCC_CIR_PLLI2SRDYF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga23921a147e121d49592e590f773f3c6c">RCC_CIR_PLLI2SRDYF_Pos</a>)</td></tr>
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<tr class="separator:ga61e88621c6cbc397e6c0872c98f11151"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad338d8663c078cf3d73e4bfaa44da093" id="r_gad338d8663c078cf3d73e4bfaa44da093"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad338d8663c078cf3d73e4bfaa44da093">RCC_CIR_PLLI2SRDYF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga61e88621c6cbc397e6c0872c98f11151">RCC_CIR_PLLI2SRDYF_Msk</a></td></tr>
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<tr class="separator:gad338d8663c078cf3d73e4bfaa44da093"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab82aae1efb70d76f85bcad7ec0632d4c" id="r_gab82aae1efb70d76f85bcad7ec0632d4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab82aae1efb70d76f85bcad7ec0632d4c">RCC_CIR_CSSF_Pos</a>   (7U)</td></tr>
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<tr class="separator:gab82aae1efb70d76f85bcad7ec0632d4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8eb3ec455be7a5e4ffbe0abc9e2a77eb" id="r_ga8eb3ec455be7a5e4ffbe0abc9e2a77eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8eb3ec455be7a5e4ffbe0abc9e2a77eb">RCC_CIR_CSSF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab82aae1efb70d76f85bcad7ec0632d4c">RCC_CIR_CSSF_Pos</a>)</td></tr>
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<tr class="separator:ga8eb3ec455be7a5e4ffbe0abc9e2a77eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad66b719e4061294de35af58cc27aba7f" id="r_gad66b719e4061294de35af58cc27aba7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad66b719e4061294de35af58cc27aba7f">RCC_CIR_CSSF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8eb3ec455be7a5e4ffbe0abc9e2a77eb">RCC_CIR_CSSF_Msk</a></td></tr>
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<tr class="separator:gad66b719e4061294de35af58cc27aba7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga085c2d83db641a456df4a5f67582bff5" id="r_ga085c2d83db641a456df4a5f67582bff5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga085c2d83db641a456df4a5f67582bff5">RCC_CIR_LSIRDYIE_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga085c2d83db641a456df4a5f67582bff5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ba1782e2e14efd1bd9feabf1608fd5a" id="r_ga7ba1782e2e14efd1bd9feabf1608fd5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ba1782e2e14efd1bd9feabf1608fd5a">RCC_CIR_LSIRDYIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga085c2d83db641a456df4a5f67582bff5">RCC_CIR_LSIRDYIE_Pos</a>)</td></tr>
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<tr class="separator:ga7ba1782e2e14efd1bd9feabf1608fd5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga872ba937149a7372138df06f8188ab56" id="r_ga872ba937149a7372138df06f8188ab56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga872ba937149a7372138df06f8188ab56">RCC_CIR_LSIRDYIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ba1782e2e14efd1bd9feabf1608fd5a">RCC_CIR_LSIRDYIE_Msk</a></td></tr>
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<tr class="separator:ga872ba937149a7372138df06f8188ab56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7eabf777f7d12a95038d5408cd9a3225" id="r_ga7eabf777f7d12a95038d5408cd9a3225"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7eabf777f7d12a95038d5408cd9a3225">RCC_CIR_LSERDYIE_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga7eabf777f7d12a95038d5408cd9a3225"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24446323cbae3ab353f248d23655b822" id="r_ga24446323cbae3ab353f248d23655b822"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24446323cbae3ab353f248d23655b822">RCC_CIR_LSERDYIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7eabf777f7d12a95038d5408cd9a3225">RCC_CIR_LSERDYIE_Pos</a>)</td></tr>
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<tr class="separator:ga24446323cbae3ab353f248d23655b822"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a0ad2672c9ba1b26012cbc6d423dff8" id="r_ga6a0ad2672c9ba1b26012cbc6d423dff8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a0ad2672c9ba1b26012cbc6d423dff8">RCC_CIR_LSERDYIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga24446323cbae3ab353f248d23655b822">RCC_CIR_LSERDYIE_Msk</a></td></tr>
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<tr class="separator:ga6a0ad2672c9ba1b26012cbc6d423dff8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc61d466aac29f7fbd88b0245d6cf8c1" id="r_gafc61d466aac29f7fbd88b0245d6cf8c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc61d466aac29f7fbd88b0245d6cf8c1">RCC_CIR_HSIRDYIE_Pos</a>   (10U)</td></tr>
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<tr class="separator:gafc61d466aac29f7fbd88b0245d6cf8c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7aeb42d0a5ef8e7bac1876e0689814e" id="r_gac7aeb42d0a5ef8e7bac1876e0689814e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7aeb42d0a5ef8e7bac1876e0689814e">RCC_CIR_HSIRDYIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafc61d466aac29f7fbd88b0245d6cf8c1">RCC_CIR_HSIRDYIE_Pos</a>)</td></tr>
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<tr class="separator:gac7aeb42d0a5ef8e7bac1876e0689814e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac714351a6f9dab4741354fb017638580" id="r_gac714351a6f9dab4741354fb017638580"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac714351a6f9dab4741354fb017638580">RCC_CIR_HSIRDYIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac7aeb42d0a5ef8e7bac1876e0689814e">RCC_CIR_HSIRDYIE_Msk</a></td></tr>
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<tr class="separator:gac714351a6f9dab4741354fb017638580"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a258b8f9041e6a3e30a12f371e1e289" id="r_ga8a258b8f9041e6a3e30a12f371e1e289"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a258b8f9041e6a3e30a12f371e1e289">RCC_CIR_HSERDYIE_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga8a258b8f9041e6a3e30a12f371e1e289"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f6db5519f1bbb1d42ee0f43367e7fd9" id="r_ga2f6db5519f1bbb1d42ee0f43367e7fd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f6db5519f1bbb1d42ee0f43367e7fd9">RCC_CIR_HSERDYIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a258b8f9041e6a3e30a12f371e1e289">RCC_CIR_HSERDYIE_Pos</a>)</td></tr>
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<tr class="separator:ga2f6db5519f1bbb1d42ee0f43367e7fd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5492f9b58600cf66616eb931b48b3c11" id="r_ga5492f9b58600cf66616eb931b48b3c11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5492f9b58600cf66616eb931b48b3c11">RCC_CIR_HSERDYIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f6db5519f1bbb1d42ee0f43367e7fd9">RCC_CIR_HSERDYIE_Msk</a></td></tr>
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<tr class="separator:ga5492f9b58600cf66616eb931b48b3c11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54f619655facb49336e0baf439ef130b" id="r_ga54f619655facb49336e0baf439ef130b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54f619655facb49336e0baf439ef130b">RCC_CIR_PLLRDYIE_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga54f619655facb49336e0baf439ef130b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6fdb478ae8c7d99d780c78bb68830dd5" id="r_ga6fdb478ae8c7d99d780c78bb68830dd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fdb478ae8c7d99d780c78bb68830dd5">RCC_CIR_PLLRDYIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga54f619655facb49336e0baf439ef130b">RCC_CIR_PLLRDYIE_Pos</a>)</td></tr>
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<tr class="separator:ga6fdb478ae8c7d99d780c78bb68830dd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b70927cab2ba9cf82d1620cf88b0f95" id="r_ga1b70927cab2ba9cf82d1620cf88b0f95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b70927cab2ba9cf82d1620cf88b0f95">RCC_CIR_PLLRDYIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6fdb478ae8c7d99d780c78bb68830dd5">RCC_CIR_PLLRDYIE_Msk</a></td></tr>
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<tr class="separator:ga1b70927cab2ba9cf82d1620cf88b0f95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac69e15926ecae3167dfbc860e784e7f3" id="r_gac69e15926ecae3167dfbc860e784e7f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac69e15926ecae3167dfbc860e784e7f3">RCC_CIR_PLLI2SRDYIE_Pos</a>   (13U)</td></tr>
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<tr class="separator:gac69e15926ecae3167dfbc860e784e7f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6af4a5b0b017c2dde04fa660950578cc" id="r_ga6af4a5b0b017c2dde04fa660950578cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6af4a5b0b017c2dde04fa660950578cc">RCC_CIR_PLLI2SRDYIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac69e15926ecae3167dfbc860e784e7f3">RCC_CIR_PLLI2SRDYIE_Pos</a>)</td></tr>
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<tr class="separator:ga6af4a5b0b017c2dde04fa660950578cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ca3cbf69c7cce53e974316dbf38d3dc" id="r_ga1ca3cbf69c7cce53e974316dbf38d3dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ca3cbf69c7cce53e974316dbf38d3dc">RCC_CIR_PLLI2SRDYIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6af4a5b0b017c2dde04fa660950578cc">RCC_CIR_PLLI2SRDYIE_Msk</a></td></tr>
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<tr class="separator:ga1ca3cbf69c7cce53e974316dbf38d3dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1baeac3a2504113deb0a65d46d7314e2" id="r_ga1baeac3a2504113deb0a65d46d7314e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1baeac3a2504113deb0a65d46d7314e2">RCC_CIR_LSIRDYC_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga1baeac3a2504113deb0a65d46d7314e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11edf191b118ca860e0eca011f113ad9" id="r_ga11edf191b118ca860e0eca011f113ad9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11edf191b118ca860e0eca011f113ad9">RCC_CIR_LSIRDYC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1baeac3a2504113deb0a65d46d7314e2">RCC_CIR_LSIRDYC_Pos</a>)</td></tr>
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<tr class="separator:ga11edf191b118ca860e0eca011f113ad9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga982989563f1a95c89bf7f4a25d99f704" id="r_ga982989563f1a95c89bf7f4a25d99f704"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga982989563f1a95c89bf7f4a25d99f704">RCC_CIR_LSIRDYC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga11edf191b118ca860e0eca011f113ad9">RCC_CIR_LSIRDYC_Msk</a></td></tr>
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<tr class="separator:ga982989563f1a95c89bf7f4a25d99f704"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f106e06b78f78c5a520faa1b180de2e" id="r_ga0f106e06b78f78c5a520faa1b180de2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f106e06b78f78c5a520faa1b180de2e">RCC_CIR_LSERDYC_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga0f106e06b78f78c5a520faa1b180de2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba1367e36a992aae85f9e8f9921e9426" id="r_gaba1367e36a992aae85f9e8f9921e9426"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba1367e36a992aae85f9e8f9921e9426">RCC_CIR_LSERDYC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f106e06b78f78c5a520faa1b180de2e">RCC_CIR_LSERDYC_Pos</a>)</td></tr>
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<tr class="separator:gaba1367e36a992aae85f9e8f9921e9426"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga144b5147f3a8d0bfda04618e301986aa" id="r_ga144b5147f3a8d0bfda04618e301986aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga144b5147f3a8d0bfda04618e301986aa">RCC_CIR_LSERDYC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba1367e36a992aae85f9e8f9921e9426">RCC_CIR_LSERDYC_Msk</a></td></tr>
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<tr class="separator:ga144b5147f3a8d0bfda04618e301986aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2ccc89ed1b4d16c5f2804c216c5adc3" id="r_gaf2ccc89ed1b4d16c5f2804c216c5adc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2ccc89ed1b4d16c5f2804c216c5adc3">RCC_CIR_HSIRDYC_Pos</a>   (18U)</td></tr>
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<tr class="separator:gaf2ccc89ed1b4d16c5f2804c216c5adc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga657cffa4be41e26f7b5383719dd7781a" id="r_ga657cffa4be41e26f7b5383719dd7781a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga657cffa4be41e26f7b5383719dd7781a">RCC_CIR_HSIRDYC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2ccc89ed1b4d16c5f2804c216c5adc3">RCC_CIR_HSIRDYC_Pos</a>)</td></tr>
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<tr class="separator:ga657cffa4be41e26f7b5383719dd7781a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1b58377908e5c31a684747d0a80ecb2" id="r_gad1b58377908e5c31a684747d0a80ecb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1b58377908e5c31a684747d0a80ecb2">RCC_CIR_HSIRDYC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga657cffa4be41e26f7b5383719dd7781a">RCC_CIR_HSIRDYC_Msk</a></td></tr>
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<tr class="separator:gad1b58377908e5c31a684747d0a80ecb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34e713e2755ef1c9210e3b8c8f2c718e" id="r_ga34e713e2755ef1c9210e3b8c8f2c718e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34e713e2755ef1c9210e3b8c8f2c718e">RCC_CIR_HSERDYC_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga34e713e2755ef1c9210e3b8c8f2c718e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2211dd40005f6152d0e8258d380a6713" id="r_ga2211dd40005f6152d0e8258d380a6713"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2211dd40005f6152d0e8258d380a6713">RCC_CIR_HSERDYC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34e713e2755ef1c9210e3b8c8f2c718e">RCC_CIR_HSERDYC_Pos</a>)</td></tr>
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<tr class="separator:ga2211dd40005f6152d0e8258d380a6713"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9464e8188d717902990b467a9396d238" id="r_ga9464e8188d717902990b467a9396d238"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9464e8188d717902990b467a9396d238">RCC_CIR_HSERDYC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2211dd40005f6152d0e8258d380a6713">RCC_CIR_HSERDYC_Msk</a></td></tr>
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<tr class="separator:ga9464e8188d717902990b467a9396d238"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2884b24e49761690cfc68a9929c7b10d" id="r_ga2884b24e49761690cfc68a9929c7b10d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2884b24e49761690cfc68a9929c7b10d">RCC_CIR_PLLRDYC_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga2884b24e49761690cfc68a9929c7b10d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ee90d2a5649fe386ba87eeead64ada1" id="r_ga1ee90d2a5649fe386ba87eeead64ada1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ee90d2a5649fe386ba87eeead64ada1">RCC_CIR_PLLRDYC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2884b24e49761690cfc68a9929c7b10d">RCC_CIR_PLLRDYC_Pos</a>)</td></tr>
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<tr class="separator:ga1ee90d2a5649fe386ba87eeead64ada1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga245af864b194f0c2b2389ea1ee49a396" id="r_ga245af864b194f0c2b2389ea1ee49a396"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga245af864b194f0c2b2389ea1ee49a396">RCC_CIR_PLLRDYC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ee90d2a5649fe386ba87eeead64ada1">RCC_CIR_PLLRDYC_Msk</a></td></tr>
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<tr class="separator:ga245af864b194f0c2b2389ea1ee49a396"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadca4503c3752588bd3efeea2b5f0c99a" id="r_gadca4503c3752588bd3efeea2b5f0c99a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadca4503c3752588bd3efeea2b5f0c99a">RCC_CIR_PLLI2SRDYC_Pos</a>   (21U)</td></tr>
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<tr class="separator:gadca4503c3752588bd3efeea2b5f0c99a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6a1a17873c5e712e9ed47d92fbc99cd" id="r_gad6a1a17873c5e712e9ed47d92fbc99cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6a1a17873c5e712e9ed47d92fbc99cd">RCC_CIR_PLLI2SRDYC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadca4503c3752588bd3efeea2b5f0c99a">RCC_CIR_PLLI2SRDYC_Pos</a>)</td></tr>
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<tr class="separator:gad6a1a17873c5e712e9ed47d92fbc99cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73e79cc7236f5f76cb97c8012771e6bb" id="r_ga73e79cc7236f5f76cb97c8012771e6bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73e79cc7236f5f76cb97c8012771e6bb">RCC_CIR_PLLI2SRDYC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad6a1a17873c5e712e9ed47d92fbc99cd">RCC_CIR_PLLI2SRDYC_Msk</a></td></tr>
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<tr class="separator:ga73e79cc7236f5f76cb97c8012771e6bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c7cf29f8c4b46a59751e6fdc44f8153" id="r_ga5c7cf29f8c4b46a59751e6fdc44f8153"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c7cf29f8c4b46a59751e6fdc44f8153">RCC_CIR_CSSC_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga5c7cf29f8c4b46a59751e6fdc44f8153"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66a9cf76bbf90f432815527965cb5c3e" id="r_ga66a9cf76bbf90f432815527965cb5c3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66a9cf76bbf90f432815527965cb5c3e">RCC_CIR_CSSC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c7cf29f8c4b46a59751e6fdc44f8153">RCC_CIR_CSSC_Pos</a>)</td></tr>
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<tr class="memitem:ga46edb2b9568f002feba7b4312ed92c1f" id="r_ga46edb2b9568f002feba7b4312ed92c1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46edb2b9568f002feba7b4312ed92c1f">RCC_CIR_CSSC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga66a9cf76bbf90f432815527965cb5c3e">RCC_CIR_CSSC_Msk</a></td></tr>
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<tr class="separator:ga46edb2b9568f002feba7b4312ed92c1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1a30c30184844a5d3a71f73669375e7" id="r_gac1a30c30184844a5d3a71f73669375e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1a30c30184844a5d3a71f73669375e7">RCC_AHB1RSTR_GPIOARST_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac1a30c30184844a5d3a71f73669375e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ca733a89ed0ddeb8c6ad7d4df334baf" id="r_ga1ca733a89ed0ddeb8c6ad7d4df334baf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ca733a89ed0ddeb8c6ad7d4df334baf">RCC_AHB1RSTR_GPIOARST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac1a30c30184844a5d3a71f73669375e7">RCC_AHB1RSTR_GPIOARST_Pos</a>)</td></tr>
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<tr class="separator:ga1ca733a89ed0ddeb8c6ad7d4df334baf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c171937e46c2b9a58f16ee82010509e" id="r_ga6c171937e46c2b9a58f16ee82010509e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c171937e46c2b9a58f16ee82010509e">RCC_AHB1RSTR_GPIOARST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ca733a89ed0ddeb8c6ad7d4df334baf">RCC_AHB1RSTR_GPIOARST_Msk</a></td></tr>
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<tr class="separator:ga6c171937e46c2b9a58f16ee82010509e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3154d462e29e472394d62113b4a3fadc" id="r_ga3154d462e29e472394d62113b4a3fadc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3154d462e29e472394d62113b4a3fadc">RCC_AHB1RSTR_GPIOBRST_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga3154d462e29e472394d62113b4a3fadc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70a227671a2b417929ad0959d9e899c8" id="r_ga70a227671a2b417929ad0959d9e899c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70a227671a2b417929ad0959d9e899c8">RCC_AHB1RSTR_GPIOBRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3154d462e29e472394d62113b4a3fadc">RCC_AHB1RSTR_GPIOBRST_Pos</a>)</td></tr>
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<tr class="separator:ga70a227671a2b417929ad0959d9e899c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e60d32cb67768339fc47a2ba11b7a97" id="r_ga8e60d32cb67768339fc47a2ba11b7a97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e60d32cb67768339fc47a2ba11b7a97">RCC_AHB1RSTR_GPIOBRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga70a227671a2b417929ad0959d9e899c8">RCC_AHB1RSTR_GPIOBRST_Msk</a></td></tr>
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<tr class="separator:ga8e60d32cb67768339fc47a2ba11b7a97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23de6a59e935f9e205e35aa713204d77" id="r_ga23de6a59e935f9e205e35aa713204d77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23de6a59e935f9e205e35aa713204d77">RCC_AHB1RSTR_GPIOCRST_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga23de6a59e935f9e205e35aa713204d77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f25d081a1bb38f34f8d11fc32bdc7d7" id="r_ga1f25d081a1bb38f34f8d11fc32bdc7d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f25d081a1bb38f34f8d11fc32bdc7d7">RCC_AHB1RSTR_GPIOCRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga23de6a59e935f9e205e35aa713204d77">RCC_AHB1RSTR_GPIOCRST_Pos</a>)</td></tr>
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<tr class="separator:ga1f25d081a1bb38f34f8d11fc32bdc7d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d02a09e1dafda744c7b27dca99fa3ef" id="r_ga8d02a09e1dafda744c7b27dca99fa3ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d02a09e1dafda744c7b27dca99fa3ef">RCC_AHB1RSTR_GPIOCRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f25d081a1bb38f34f8d11fc32bdc7d7">RCC_AHB1RSTR_GPIOCRST_Msk</a></td></tr>
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<tr class="separator:ga8d02a09e1dafda744c7b27dca99fa3ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga296b1b5d6eaac638fc714115bb8fb79b" id="r_ga296b1b5d6eaac638fc714115bb8fb79b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga296b1b5d6eaac638fc714115bb8fb79b">RCC_AHB1RSTR_GPIODRST_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga296b1b5d6eaac638fc714115bb8fb79b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45e4b57d9e0d9c72055b51a222d388f5" id="r_ga45e4b57d9e0d9c72055b51a222d388f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45e4b57d9e0d9c72055b51a222d388f5">RCC_AHB1RSTR_GPIODRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga296b1b5d6eaac638fc714115bb8fb79b">RCC_AHB1RSTR_GPIODRST_Pos</a>)</td></tr>
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<tr class="separator:ga45e4b57d9e0d9c72055b51a222d388f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad16f3ce75bba03d8de4f5bc89c561337" id="r_gad16f3ce75bba03d8de4f5bc89c561337"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad16f3ce75bba03d8de4f5bc89c561337">RCC_AHB1RSTR_GPIODRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45e4b57d9e0d9c72055b51a222d388f5">RCC_AHB1RSTR_GPIODRST_Msk</a></td></tr>
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<tr class="separator:gad16f3ce75bba03d8de4f5bc89c561337"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9d31d86453dfa221ced7ff4668a4b40" id="r_gac9d31d86453dfa221ced7ff4668a4b40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9d31d86453dfa221ced7ff4668a4b40">RCC_AHB1RSTR_GPIOERST_Pos</a>   (4U)</td></tr>
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<tr class="separator:gac9d31d86453dfa221ced7ff4668a4b40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2330cc824d6e097fc95f311730778243" id="r_ga2330cc824d6e097fc95f311730778243"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2330cc824d6e097fc95f311730778243">RCC_AHB1RSTR_GPIOERST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9d31d86453dfa221ced7ff4668a4b40">RCC_AHB1RSTR_GPIOERST_Pos</a>)</td></tr>
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<tr class="separator:ga2330cc824d6e097fc95f311730778243"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9baeb0fd247300501274a9259a4b184" id="r_gad9baeb0fd247300501274a9259a4b184"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9baeb0fd247300501274a9259a4b184">RCC_AHB1RSTR_GPIOERST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2330cc824d6e097fc95f311730778243">RCC_AHB1RSTR_GPIOERST_Msk</a></td></tr>
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<tr class="separator:gad9baeb0fd247300501274a9259a4b184"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc279604f2a9a7f4bc29702d784cf22c" id="r_gabc279604f2a9a7f4bc29702d784cf22c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc279604f2a9a7f4bc29702d784cf22c">RCC_AHB1RSTR_GPIOFRST_Pos</a>   (5U)</td></tr>
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<tr class="separator:gabc279604f2a9a7f4bc29702d784cf22c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5758110647b39258af5b6c4259a59c0" id="r_gae5758110647b39258af5b6c4259a59c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5758110647b39258af5b6c4259a59c0">RCC_AHB1RSTR_GPIOFRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc279604f2a9a7f4bc29702d784cf22c">RCC_AHB1RSTR_GPIOFRST_Pos</a>)</td></tr>
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<tr class="separator:gae5758110647b39258af5b6c4259a59c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab00b21dc4408295d374a4970ea5ae751" id="r_gab00b21dc4408295d374a4970ea5ae751"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab00b21dc4408295d374a4970ea5ae751">RCC_AHB1RSTR_GPIOFRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae5758110647b39258af5b6c4259a59c0">RCC_AHB1RSTR_GPIOFRST_Msk</a></td></tr>
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<tr class="separator:gab00b21dc4408295d374a4970ea5ae751"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b38704ba9c53025641de7d5ed93add4" id="r_ga5b38704ba9c53025641de7d5ed93add4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b38704ba9c53025641de7d5ed93add4">RCC_AHB1RSTR_GPIOGRST_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga5b38704ba9c53025641de7d5ed93add4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ca12c8d01be2d47518003a30d836a68" id="r_ga7ca12c8d01be2d47518003a30d836a68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ca12c8d01be2d47518003a30d836a68">RCC_AHB1RSTR_GPIOGRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b38704ba9c53025641de7d5ed93add4">RCC_AHB1RSTR_GPIOGRST_Pos</a>)</td></tr>
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<tr class="separator:ga7ca12c8d01be2d47518003a30d836a68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50322b0db25b2204aa114c4c29847051" id="r_ga50322b0db25b2204aa114c4c29847051"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50322b0db25b2204aa114c4c29847051">RCC_AHB1RSTR_GPIOGRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ca12c8d01be2d47518003a30d836a68">RCC_AHB1RSTR_GPIOGRST_Msk</a></td></tr>
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<tr class="separator:ga50322b0db25b2204aa114c4c29847051"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada3768676df15e5d248404ba29df27ce" id="r_gada3768676df15e5d248404ba29df27ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada3768676df15e5d248404ba29df27ce">RCC_AHB1RSTR_GPIOHRST_Pos</a>   (7U)</td></tr>
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<tr class="separator:gada3768676df15e5d248404ba29df27ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6853aabc577ec17d0d7f894e520a693" id="r_gaa6853aabc577ec17d0d7f894e520a693"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6853aabc577ec17d0d7f894e520a693">RCC_AHB1RSTR_GPIOHRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada3768676df15e5d248404ba29df27ce">RCC_AHB1RSTR_GPIOHRST_Pos</a>)</td></tr>
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<tr class="separator:gaa6853aabc577ec17d0d7f894e520a693"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga587e3e32701cbd127d2afb19b9bff5fd" id="r_ga587e3e32701cbd127d2afb19b9bff5fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga587e3e32701cbd127d2afb19b9bff5fd">RCC_AHB1RSTR_GPIOHRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6853aabc577ec17d0d7f894e520a693">RCC_AHB1RSTR_GPIOHRST_Msk</a></td></tr>
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<tr class="separator:ga587e3e32701cbd127d2afb19b9bff5fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf265743558660a1035f0456bede8322" id="r_gacf265743558660a1035f0456bede8322"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf265743558660a1035f0456bede8322">RCC_AHB1RSTR_GPIOIRST_Pos</a>   (8U)</td></tr>
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<tr class="separator:gacf265743558660a1035f0456bede8322"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad771106a6653644a43c7d3d572d70220" id="r_gad771106a6653644a43c7d3d572d70220"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad771106a6653644a43c7d3d572d70220">RCC_AHB1RSTR_GPIOIRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf265743558660a1035f0456bede8322">RCC_AHB1RSTR_GPIOIRST_Pos</a>)</td></tr>
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<tr class="separator:gad771106a6653644a43c7d3d572d70220"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5180658a02a87b501ab3f250593905b" id="r_gab5180658a02a87b501ab3f250593905b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5180658a02a87b501ab3f250593905b">RCC_AHB1RSTR_GPIOIRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad771106a6653644a43c7d3d572d70220">RCC_AHB1RSTR_GPIOIRST_Msk</a></td></tr>
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<tr class="separator:gab5180658a02a87b501ab3f250593905b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga250ad2c8a4d0fbfd4360afcdce858075" id="r_ga250ad2c8a4d0fbfd4360afcdce858075"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga250ad2c8a4d0fbfd4360afcdce858075">RCC_AHB1RSTR_CRCRST_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga250ad2c8a4d0fbfd4360afcdce858075"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf0f9e76b934af78155abddaacf568e4" id="r_gaaf0f9e76b934af78155abddaacf568e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf0f9e76b934af78155abddaacf568e4">RCC_AHB1RSTR_CRCRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga250ad2c8a4d0fbfd4360afcdce858075">RCC_AHB1RSTR_CRCRST_Pos</a>)</td></tr>
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<tr class="separator:gaaf0f9e76b934af78155abddaacf568e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94f45f591e5e217833c6ab36a958543b" id="r_ga94f45f591e5e217833c6ab36a958543b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94f45f591e5e217833c6ab36a958543b">RCC_AHB1RSTR_CRCRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf0f9e76b934af78155abddaacf568e4">RCC_AHB1RSTR_CRCRST_Msk</a></td></tr>
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<tr class="separator:ga94f45f591e5e217833c6ab36a958543b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga577ac0ee66f5e320ea4450234e709a03" id="r_ga577ac0ee66f5e320ea4450234e709a03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga577ac0ee66f5e320ea4450234e709a03">RCC_AHB1RSTR_DMA1RST_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga577ac0ee66f5e320ea4450234e709a03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c336fca84fc656b8412d0a0dab8317e" id="r_ga9c336fca84fc656b8412d0a0dab8317e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c336fca84fc656b8412d0a0dab8317e">RCC_AHB1RSTR_DMA1RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga577ac0ee66f5e320ea4450234e709a03">RCC_AHB1RSTR_DMA1RST_Pos</a>)</td></tr>
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<tr class="separator:ga9c336fca84fc656b8412d0a0dab8317e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d1655ddfb777fce28b1d6b9a9c2d0e0" id="r_ga4d1655ddfb777fce28b1d6b9a9c2d0e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d1655ddfb777fce28b1d6b9a9c2d0e0">RCC_AHB1RSTR_DMA1RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c336fca84fc656b8412d0a0dab8317e">RCC_AHB1RSTR_DMA1RST_Msk</a></td></tr>
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<tr class="separator:ga4d1655ddfb777fce28b1d6b9a9c2d0e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16e38f17a99cc2e1f91d622f11ac8c89" id="r_ga16e38f17a99cc2e1f91d622f11ac8c89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16e38f17a99cc2e1f91d622f11ac8c89">RCC_AHB1RSTR_DMA2RST_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga16e38f17a99cc2e1f91d622f11ac8c89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5e2d5af9f21f5df26e53863392f46ce" id="r_gae5e2d5af9f21f5df26e53863392f46ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5e2d5af9f21f5df26e53863392f46ce">RCC_AHB1RSTR_DMA2RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16e38f17a99cc2e1f91d622f11ac8c89">RCC_AHB1RSTR_DMA2RST_Pos</a>)</td></tr>
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<tr class="separator:gae5e2d5af9f21f5df26e53863392f46ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga827aea44c35a0c3eb815a5d7d8546c7b" id="r_ga827aea44c35a0c3eb815a5d7d8546c7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga827aea44c35a0c3eb815a5d7d8546c7b">RCC_AHB1RSTR_DMA2RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae5e2d5af9f21f5df26e53863392f46ce">RCC_AHB1RSTR_DMA2RST_Msk</a></td></tr>
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<tr class="separator:ga827aea44c35a0c3eb815a5d7d8546c7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e5a9384f957af95226d03414e7500e3" id="r_ga9e5a9384f957af95226d03414e7500e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e5a9384f957af95226d03414e7500e3">RCC_AHB1RSTR_ETHMACRST_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga9e5a9384f957af95226d03414e7500e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c088bbef40582644da68cebbce2c455" id="r_ga9c088bbef40582644da68cebbce2c455"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c088bbef40582644da68cebbce2c455">RCC_AHB1RSTR_ETHMACRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e5a9384f957af95226d03414e7500e3">RCC_AHB1RSTR_ETHMACRST_Pos</a>)</td></tr>
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<tr class="separator:ga9c088bbef40582644da68cebbce2c455"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e1dca7f08a971d2c3bf39a928c49586" id="r_ga1e1dca7f08a971d2c3bf39a928c49586"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e1dca7f08a971d2c3bf39a928c49586">RCC_AHB1RSTR_ETHMACRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c088bbef40582644da68cebbce2c455">RCC_AHB1RSTR_ETHMACRST_Msk</a></td></tr>
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<tr class="separator:ga1e1dca7f08a971d2c3bf39a928c49586"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga355532707d1260d362e518e645be8753" id="r_ga355532707d1260d362e518e645be8753"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga355532707d1260d362e518e645be8753">RCC_AHB1RSTR_OTGHRST_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga355532707d1260d362e518e645be8753"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga351abffe0a0e32b6e74378a5e4b82a9e" id="r_ga351abffe0a0e32b6e74378a5e4b82a9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga351abffe0a0e32b6e74378a5e4b82a9e">RCC_AHB1RSTR_OTGHRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga355532707d1260d362e518e645be8753">RCC_AHB1RSTR_OTGHRST_Pos</a>)</td></tr>
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<tr class="separator:ga351abffe0a0e32b6e74378a5e4b82a9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga236682929d2641e851f175ab3aa1f520" id="r_ga236682929d2641e851f175ab3aa1f520"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga236682929d2641e851f175ab3aa1f520">RCC_AHB1RSTR_OTGHRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga351abffe0a0e32b6e74378a5e4b82a9e">RCC_AHB1RSTR_OTGHRST_Msk</a></td></tr>
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<tr class="separator:ga236682929d2641e851f175ab3aa1f520"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga457063d004551e2cce80472b190372c2" id="r_ga457063d004551e2cce80472b190372c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga457063d004551e2cce80472b190372c2">RCC_AHB2RSTR_DCMIRST_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga457063d004551e2cce80472b190372c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad65d3d99d10ccb38170740b9dbc30f0f" id="r_gad65d3d99d10ccb38170740b9dbc30f0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad65d3d99d10ccb38170740b9dbc30f0f">RCC_AHB2RSTR_DCMIRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga457063d004551e2cce80472b190372c2">RCC_AHB2RSTR_DCMIRST_Pos</a>)</td></tr>
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<tr class="separator:gad65d3d99d10ccb38170740b9dbc30f0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae909f90338c129e116b7d49bebfb31c5" id="r_gae909f90338c129e116b7d49bebfb31c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae909f90338c129e116b7d49bebfb31c5">RCC_AHB2RSTR_DCMIRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad65d3d99d10ccb38170740b9dbc30f0f">RCC_AHB2RSTR_DCMIRST_Msk</a></td></tr>
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<tr class="separator:gae909f90338c129e116b7d49bebfb31c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadeefbc7de6773eedfba70fb6cd83890" id="r_gaadeefbc7de6773eedfba70fb6cd83890"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadeefbc7de6773eedfba70fb6cd83890">RCC_AHB2RSTR_RNGRST_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaadeefbc7de6773eedfba70fb6cd83890"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ac557e9b39e599539fb5cc2a100de60" id="r_ga7ac557e9b39e599539fb5cc2a100de60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac557e9b39e599539fb5cc2a100de60">RCC_AHB2RSTR_RNGRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaadeefbc7de6773eedfba70fb6cd83890">RCC_AHB2RSTR_RNGRST_Pos</a>)</td></tr>
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<tr class="separator:ga7ac557e9b39e599539fb5cc2a100de60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace46c6461c8b4ddd78510bc2c529c91b" id="r_gace46c6461c8b4ddd78510bc2c529c91b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace46c6461c8b4ddd78510bc2c529c91b">RCC_AHB2RSTR_RNGRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac557e9b39e599539fb5cc2a100de60">RCC_AHB2RSTR_RNGRST_Msk</a></td></tr>
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<tr class="separator:gace46c6461c8b4ddd78510bc2c529c91b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f5fe9c74c695fe79917ce4828d2e24b" id="r_ga5f5fe9c74c695fe79917ce4828d2e24b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f5fe9c74c695fe79917ce4828d2e24b">RCC_AHB2RSTR_OTGFSRST_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga5f5fe9c74c695fe79917ce4828d2e24b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacba439d5c37535fc904630d55dd8d204" id="r_gacba439d5c37535fc904630d55dd8d204"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacba439d5c37535fc904630d55dd8d204">RCC_AHB2RSTR_OTGFSRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f5fe9c74c695fe79917ce4828d2e24b">RCC_AHB2RSTR_OTGFSRST_Pos</a>)</td></tr>
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<tr class="separator:gacba439d5c37535fc904630d55dd8d204"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1b8b894a2f1ea24b4799c7a30abbb5a" id="r_gae1b8b894a2f1ea24b4799c7a30abbb5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1b8b894a2f1ea24b4799c7a30abbb5a">RCC_AHB2RSTR_OTGFSRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacba439d5c37535fc904630d55dd8d204">RCC_AHB2RSTR_OTGFSRST_Msk</a></td></tr>
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<tr class="separator:gae1b8b894a2f1ea24b4799c7a30abbb5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3aa38c40a38fe2a2e7d7bb26cdbfff36" id="r_ga3aa38c40a38fe2a2e7d7bb26cdbfff36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3aa38c40a38fe2a2e7d7bb26cdbfff36">RCC_AHB3RSTR_FSMCRST_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3aa38c40a38fe2a2e7d7bb26cdbfff36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab498285653979d8739b94dcbe1a32048" id="r_gab498285653979d8739b94dcbe1a32048"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab498285653979d8739b94dcbe1a32048">RCC_AHB3RSTR_FSMCRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3aa38c40a38fe2a2e7d7bb26cdbfff36">RCC_AHB3RSTR_FSMCRST_Pos</a>)</td></tr>
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<tr class="separator:gab498285653979d8739b94dcbe1a32048"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga915aa42b819649f5ee7abdf5319d6bb8" id="r_ga915aa42b819649f5ee7abdf5319d6bb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga915aa42b819649f5ee7abdf5319d6bb8">RCC_AHB3RSTR_FSMCRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab498285653979d8739b94dcbe1a32048">RCC_AHB3RSTR_FSMCRST_Msk</a></td></tr>
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<tr class="separator:ga915aa42b819649f5ee7abdf5319d6bb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef7278dbd9406107fbccefa358501f2c" id="r_gaef7278dbd9406107fbccefa358501f2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef7278dbd9406107fbccefa358501f2c">RCC_APB1RSTR_TIM2RST_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaef7278dbd9406107fbccefa358501f2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4b0f4bc33ed5d6d5806e5074349bedb" id="r_gaf4b0f4bc33ed5d6d5806e5074349bedb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4b0f4bc33ed5d6d5806e5074349bedb">RCC_APB1RSTR_TIM2RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef7278dbd9406107fbccefa358501f2c">RCC_APB1RSTR_TIM2RST_Pos</a>)</td></tr>
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<tr class="separator:gaf4b0f4bc33ed5d6d5806e5074349bedb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51ca4659706d0e00333d4abff049dc0d" id="r_ga51ca4659706d0e00333d4abff049dc0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51ca4659706d0e00333d4abff049dc0d">RCC_APB1RSTR_TIM2RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4b0f4bc33ed5d6d5806e5074349bedb">RCC_APB1RSTR_TIM2RST_Msk</a></td></tr>
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<tr class="separator:ga51ca4659706d0e00333d4abff049dc0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28531a8d644672fa950cce78175c3fc0" id="r_ga28531a8d644672fa950cce78175c3fc0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28531a8d644672fa950cce78175c3fc0">RCC_APB1RSTR_TIM3RST_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga28531a8d644672fa950cce78175c3fc0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f1a098d575d81ac443b3d6f837a09e1" id="r_ga6f1a098d575d81ac443b3d6f837a09e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f1a098d575d81ac443b3d6f837a09e1">RCC_APB1RSTR_TIM3RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga28531a8d644672fa950cce78175c3fc0">RCC_APB1RSTR_TIM3RST_Pos</a>)</td></tr>
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<tr class="separator:ga6f1a098d575d81ac443b3d6f837a09e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8680c562fd372b494a160594525d7ce9" id="r_ga8680c562fd372b494a160594525d7ce9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8680c562fd372b494a160594525d7ce9">RCC_APB1RSTR_TIM3RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f1a098d575d81ac443b3d6f837a09e1">RCC_APB1RSTR_TIM3RST_Msk</a></td></tr>
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<tr class="separator:ga8680c562fd372b494a160594525d7ce9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfd941245012a7ff32409d3858a0c369" id="r_gacfd941245012a7ff32409d3858a0c369"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfd941245012a7ff32409d3858a0c369">RCC_APB1RSTR_TIM4RST_Pos</a>   (2U)</td></tr>
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<tr class="separator:gacfd941245012a7ff32409d3858a0c369"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1adc26ee7ca9aeb6316ca372633c95e" id="r_gaa1adc26ee7ca9aeb6316ca372633c95e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1adc26ee7ca9aeb6316ca372633c95e">RCC_APB1RSTR_TIM4RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacfd941245012a7ff32409d3858a0c369">RCC_APB1RSTR_TIM4RST_Pos</a>)</td></tr>
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<tr class="separator:gaa1adc26ee7ca9aeb6316ca372633c95e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a720364de988965b6d2f91ed6519570" id="r_ga6a720364de988965b6d2f91ed6519570"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a720364de988965b6d2f91ed6519570">RCC_APB1RSTR_TIM4RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1adc26ee7ca9aeb6316ca372633c95e">RCC_APB1RSTR_TIM4RST_Msk</a></td></tr>
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<tr class="memitem:ga6ec5440469b072778617b76dd55faf23" id="r_ga6ec5440469b072778617b76dd55faf23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ec5440469b072778617b76dd55faf23">RCC_APB1RSTR_TIM5RST_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga6ec5440469b072778617b76dd55faf23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a5cfd79c37096bf00916e7bda1df220" id="r_ga9a5cfd79c37096bf00916e7bda1df220"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a5cfd79c37096bf00916e7bda1df220">RCC_APB1RSTR_TIM5RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ec5440469b072778617b76dd55faf23">RCC_APB1RSTR_TIM5RST_Pos</a>)</td></tr>
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<tr class="separator:ga9a5cfd79c37096bf00916e7bda1df220"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d1233dd5266ba55d9951e3b1a334552" id="r_ga1d1233dd5266ba55d9951e3b1a334552"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d1233dd5266ba55d9951e3b1a334552">RCC_APB1RSTR_TIM5RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a5cfd79c37096bf00916e7bda1df220">RCC_APB1RSTR_TIM5RST_Msk</a></td></tr>
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<tr class="separator:ga1d1233dd5266ba55d9951e3b1a334552"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f910529f471272ed5218c5067115cc8" id="r_ga4f910529f471272ed5218c5067115cc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f910529f471272ed5218c5067115cc8">RCC_APB1RSTR_TIM6RST_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga4f222bd16fca5ae0a0475a83f9a69d0f" id="r_ga4f222bd16fca5ae0a0475a83f9a69d0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f222bd16fca5ae0a0475a83f9a69d0f">RCC_APB1RSTR_TIM6RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f910529f471272ed5218c5067115cc8">RCC_APB1RSTR_TIM6RST_Pos</a>)</td></tr>
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<tr class="separator:ga4f222bd16fca5ae0a0475a83f9a69d0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d64bd82cf47a209afebc7d663e28383" id="r_ga8d64bd82cf47a209afebc7d663e28383"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d64bd82cf47a209afebc7d663e28383">RCC_APB1RSTR_TIM6RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f222bd16fca5ae0a0475a83f9a69d0f">RCC_APB1RSTR_TIM6RST_Msk</a></td></tr>
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<tr class="separator:ga8d64bd82cf47a209afebc7d663e28383"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga033243ec3d5cdaa7030b8b38d39e9989" id="r_ga033243ec3d5cdaa7030b8b38d39e9989"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga033243ec3d5cdaa7030b8b38d39e9989">RCC_APB1RSTR_TIM7RST_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga033243ec3d5cdaa7030b8b38d39e9989"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9af08f1ff685c0027708d909086b748" id="r_gab9af08f1ff685c0027708d909086b748"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9af08f1ff685c0027708d909086b748">RCC_APB1RSTR_TIM7RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga033243ec3d5cdaa7030b8b38d39e9989">RCC_APB1RSTR_TIM7RST_Pos</a>)</td></tr>
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<tr class="separator:gab9af08f1ff685c0027708d909086b748"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40b1d355ee76ad9a044ad37f1629e760" id="r_ga40b1d355ee76ad9a044ad37f1629e760"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40b1d355ee76ad9a044ad37f1629e760">RCC_APB1RSTR_TIM7RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9af08f1ff685c0027708d909086b748">RCC_APB1RSTR_TIM7RST_Msk</a></td></tr>
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<tr class="separator:ga40b1d355ee76ad9a044ad37f1629e760"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5874ca2fef163308e575153b945eaa53" id="r_ga5874ca2fef163308e575153b945eaa53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5874ca2fef163308e575153b945eaa53">RCC_APB1RSTR_TIM12RST_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga5874ca2fef163308e575153b945eaa53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91170571df0e2ed7675a5b3091736507" id="r_ga91170571df0e2ed7675a5b3091736507"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91170571df0e2ed7675a5b3091736507">RCC_APB1RSTR_TIM12RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5874ca2fef163308e575153b945eaa53">RCC_APB1RSTR_TIM12RST_Pos</a>)</td></tr>
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<tr class="separator:ga91170571df0e2ed7675a5b3091736507"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga067deb756dd4100c901c6b25229678e4" id="r_ga067deb756dd4100c901c6b25229678e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga067deb756dd4100c901c6b25229678e4">RCC_APB1RSTR_TIM12RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga91170571df0e2ed7675a5b3091736507">RCC_APB1RSTR_TIM12RST_Msk</a></td></tr>
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<tr class="separator:ga067deb756dd4100c901c6b25229678e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4a9d1c4213a8dc4484ba58f49433806" id="r_gac4a9d1c4213a8dc4484ba58f49433806"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4a9d1c4213a8dc4484ba58f49433806">RCC_APB1RSTR_TIM13RST_Pos</a>   (7U)</td></tr>
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<tr class="separator:gac4a9d1c4213a8dc4484ba58f49433806"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1b75cafab3889092a34ddfb502c5d6a" id="r_gac1b75cafab3889092a34ddfb502c5d6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1b75cafab3889092a34ddfb502c5d6a">RCC_APB1RSTR_TIM13RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4a9d1c4213a8dc4484ba58f49433806">RCC_APB1RSTR_TIM13RST_Pos</a>)</td></tr>
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<tr class="separator:gac1b75cafab3889092a34ddfb502c5d6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad59f66b35bdc0953428eb8c345397a7f" id="r_gad59f66b35bdc0953428eb8c345397a7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad59f66b35bdc0953428eb8c345397a7f">RCC_APB1RSTR_TIM13RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac1b75cafab3889092a34ddfb502c5d6a">RCC_APB1RSTR_TIM13RST_Msk</a></td></tr>
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<tr class="separator:gad59f66b35bdc0953428eb8c345397a7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafced8b214c9803f4961f1f4f1324f28f" id="r_gafced8b214c9803f4961f1f4f1324f28f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafced8b214c9803f4961f1f4f1324f28f">RCC_APB1RSTR_TIM14RST_Pos</a>   (8U)</td></tr>
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<tr class="separator:gafced8b214c9803f4961f1f4f1324f28f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1887a28578dd003746b62f95b48d06a" id="r_gac1887a28578dd003746b62f95b48d06a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1887a28578dd003746b62f95b48d06a">RCC_APB1RSTR_TIM14RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafced8b214c9803f4961f1f4f1324f28f">RCC_APB1RSTR_TIM14RST_Pos</a>)</td></tr>
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<tr class="separator:gac1887a28578dd003746b62f95b48d06a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga773e6d5b419eb2d4b6291c862e04b002" id="r_ga773e6d5b419eb2d4b6291c862e04b002"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga773e6d5b419eb2d4b6291c862e04b002">RCC_APB1RSTR_TIM14RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac1887a28578dd003746b62f95b48d06a">RCC_APB1RSTR_TIM14RST_Msk</a></td></tr>
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<tr class="separator:ga773e6d5b419eb2d4b6291c862e04b002"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9d96e880c3040ba8dbe155a6129ca69" id="r_gaf9d96e880c3040ba8dbe155a6129ca69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9d96e880c3040ba8dbe155a6129ca69">RCC_APB1RSTR_WWDGRST_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaf9d96e880c3040ba8dbe155a6129ca69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga919c04abb655aa94b244dcebbf647748" id="r_ga919c04abb655aa94b244dcebbf647748"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga919c04abb655aa94b244dcebbf647748">RCC_APB1RSTR_WWDGRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9d96e880c3040ba8dbe155a6129ca69">RCC_APB1RSTR_WWDGRST_Pos</a>)</td></tr>
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<tr class="separator:ga919c04abb655aa94b244dcebbf647748"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d2591ac0655a8798f4c16cef97e6f94" id="r_ga0d2591ac0655a8798f4c16cef97e6f94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d2591ac0655a8798f4c16cef97e6f94">RCC_APB1RSTR_WWDGRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga919c04abb655aa94b244dcebbf647748">RCC_APB1RSTR_WWDGRST_Msk</a></td></tr>
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<tr class="separator:ga0d2591ac0655a8798f4c16cef97e6f94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga148b63aa15907eac1bd4894a7c157100" id="r_ga148b63aa15907eac1bd4894a7c157100"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga148b63aa15907eac1bd4894a7c157100">RCC_APB1RSTR_SPI2RST_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga148b63aa15907eac1bd4894a7c157100"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae378c28cf590c56f5487bd92705d6d54" id="r_gae378c28cf590c56f5487bd92705d6d54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae378c28cf590c56f5487bd92705d6d54">RCC_APB1RSTR_SPI2RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga148b63aa15907eac1bd4894a7c157100">RCC_APB1RSTR_SPI2RST_Pos</a>)</td></tr>
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<tr class="separator:gae378c28cf590c56f5487bd92705d6d54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a6289a35547cf0d5300706f9baa18ea" id="r_ga0a6289a35547cf0d5300706f9baa18ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a6289a35547cf0d5300706f9baa18ea">RCC_APB1RSTR_SPI2RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae378c28cf590c56f5487bd92705d6d54">RCC_APB1RSTR_SPI2RST_Msk</a></td></tr>
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<tr class="separator:ga0a6289a35547cf0d5300706f9baa18ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9458442b1f7afb7bb8c858eceb8a7e22" id="r_ga9458442b1f7afb7bb8c858eceb8a7e22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9458442b1f7afb7bb8c858eceb8a7e22">RCC_APB1RSTR_SPI3RST_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga9458442b1f7afb7bb8c858eceb8a7e22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0566a08a6cbd33046ff893d7c3b7bf1" id="r_gae0566a08a6cbd33046ff893d7c3b7bf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0566a08a6cbd33046ff893d7c3b7bf1">RCC_APB1RSTR_SPI3RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9458442b1f7afb7bb8c858eceb8a7e22">RCC_APB1RSTR_SPI3RST_Pos</a>)</td></tr>
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<tr class="separator:gae0566a08a6cbd33046ff893d7c3b7bf1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga261e0f1b39cd1cab41ec6bf40c21867b" id="r_ga261e0f1b39cd1cab41ec6bf40c21867b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga261e0f1b39cd1cab41ec6bf40c21867b">RCC_APB1RSTR_SPI3RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae0566a08a6cbd33046ff893d7c3b7bf1">RCC_APB1RSTR_SPI3RST_Msk</a></td></tr>
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<tr class="separator:ga261e0f1b39cd1cab41ec6bf40c21867b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2ca9ee6dbf794ec18d25721123a1119" id="r_gaa2ca9ee6dbf794ec18d25721123a1119"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2ca9ee6dbf794ec18d25721123a1119">RCC_APB1RSTR_USART2RST_Pos</a>   (17U)</td></tr>
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<tr class="separator:gaa2ca9ee6dbf794ec18d25721123a1119"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0beb24842078f8a070ba7f96ca579f43" id="r_ga0beb24842078f8a070ba7f96ca579f43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0beb24842078f8a070ba7f96ca579f43">RCC_APB1RSTR_USART2RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2ca9ee6dbf794ec18d25721123a1119">RCC_APB1RSTR_USART2RST_Pos</a>)</td></tr>
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<tr class="separator:ga0beb24842078f8a070ba7f96ca579f43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga195c39f08384ca1fa13b53a31d65d0a5" id="r_ga195c39f08384ca1fa13b53a31d65d0a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga195c39f08384ca1fa13b53a31d65d0a5">RCC_APB1RSTR_USART2RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0beb24842078f8a070ba7f96ca579f43">RCC_APB1RSTR_USART2RST_Msk</a></td></tr>
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<tr class="separator:ga195c39f08384ca1fa13b53a31d65d0a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d88961277f1aaaaa0088ee671319522" id="r_ga8d88961277f1aaaaa0088ee671319522"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d88961277f1aaaaa0088ee671319522">RCC_APB1RSTR_USART3RST_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga8d88961277f1aaaaa0088ee671319522"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaafe9da843ef3eb19c556b8eeed4e56bf" id="r_gaafe9da843ef3eb19c556b8eeed4e56bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafe9da843ef3eb19c556b8eeed4e56bf">RCC_APB1RSTR_USART3RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d88961277f1aaaaa0088ee671319522">RCC_APB1RSTR_USART3RST_Pos</a>)</td></tr>
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<tr class="memitem:ga766478ebdcbb647eb3f32962543bd194" id="r_ga766478ebdcbb647eb3f32962543bd194"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga766478ebdcbb647eb3f32962543bd194">RCC_APB1RSTR_USART3RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaafe9da843ef3eb19c556b8eeed4e56bf">RCC_APB1RSTR_USART3RST_Msk</a></td></tr>
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<tr class="separator:ga766478ebdcbb647eb3f32962543bd194"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff8420398d7b2ac7a1845643b0e2010b" id="r_gaff8420398d7b2ac7a1845643b0e2010b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff8420398d7b2ac7a1845643b0e2010b">RCC_APB1RSTR_UART4RST_Pos</a>   (19U)</td></tr>
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<tr class="separator:gaff8420398d7b2ac7a1845643b0e2010b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c84c3ac04f075c4571c4518e9dc6f5d" id="r_ga1c84c3ac04f075c4571c4518e9dc6f5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c84c3ac04f075c4571c4518e9dc6f5d">RCC_APB1RSTR_UART4RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaff8420398d7b2ac7a1845643b0e2010b">RCC_APB1RSTR_UART4RST_Pos</a>)</td></tr>
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<tr class="separator:ga1c84c3ac04f075c4571c4518e9dc6f5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0802e99fa9eb9388393af3135ca2cb2b" id="r_ga0802e99fa9eb9388393af3135ca2cb2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0802e99fa9eb9388393af3135ca2cb2b">RCC_APB1RSTR_UART4RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c84c3ac04f075c4571c4518e9dc6f5d">RCC_APB1RSTR_UART4RST_Msk</a></td></tr>
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<tr class="separator:ga0802e99fa9eb9388393af3135ca2cb2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaddedfda3a5db9ea42104b43d23a64495" id="r_gaddedfda3a5db9ea42104b43d23a64495"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddedfda3a5db9ea42104b43d23a64495">RCC_APB1RSTR_UART5RST_Pos</a>   (20U)</td></tr>
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<tr class="separator:gaddedfda3a5db9ea42104b43d23a64495"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5aaecac95d9e201eb6a3ee127881381b" id="r_ga5aaecac95d9e201eb6a3ee127881381b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5aaecac95d9e201eb6a3ee127881381b">RCC_APB1RSTR_UART5RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaddedfda3a5db9ea42104b43d23a64495">RCC_APB1RSTR_UART5RST_Pos</a>)</td></tr>
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<tr class="separator:ga5aaecac95d9e201eb6a3ee127881381b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e4d54359192c58725e5ece2b539f8ee" id="r_ga5e4d54359192c58725e5ece2b539f8ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e4d54359192c58725e5ece2b539f8ee">RCC_APB1RSTR_UART5RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5aaecac95d9e201eb6a3ee127881381b">RCC_APB1RSTR_UART5RST_Msk</a></td></tr>
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<tr class="separator:ga5e4d54359192c58725e5ece2b539f8ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3f6df08a3eae853a3fc8b2d0fcc0882" id="r_gac3f6df08a3eae853a3fc8b2d0fcc0882"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3f6df08a3eae853a3fc8b2d0fcc0882">RCC_APB1RSTR_I2C1RST_Pos</a>   (21U)</td></tr>
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<tr class="separator:gac3f6df08a3eae853a3fc8b2d0fcc0882"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95fda0adab6e9d4daa6417c17d905214" id="r_ga95fda0adab6e9d4daa6417c17d905214"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95fda0adab6e9d4daa6417c17d905214">RCC_APB1RSTR_I2C1RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3f6df08a3eae853a3fc8b2d0fcc0882">RCC_APB1RSTR_I2C1RST_Pos</a>)</td></tr>
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<tr class="separator:ga95fda0adab6e9d4daa6417c17d905214"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcd25346a7d7b0009090adfbca899b93" id="r_gadcd25346a7d7b0009090adfbca899b93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcd25346a7d7b0009090adfbca899b93">RCC_APB1RSTR_I2C1RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga95fda0adab6e9d4daa6417c17d905214">RCC_APB1RSTR_I2C1RST_Msk</a></td></tr>
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<tr class="separator:gadcd25346a7d7b0009090adfbca899b93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a1c1f07b2b2cc274c0b297d779b936f" id="r_ga0a1c1f07b2b2cc274c0b297d779b936f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a1c1f07b2b2cc274c0b297d779b936f">RCC_APB1RSTR_I2C2RST_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga0a1c1f07b2b2cc274c0b297d779b936f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga914a46fcb3b028610d9badb471c82bd3" id="r_ga914a46fcb3b028610d9badb471c82bd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga914a46fcb3b028610d9badb471c82bd3">RCC_APB1RSTR_I2C2RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a1c1f07b2b2cc274c0b297d779b936f">RCC_APB1RSTR_I2C2RST_Pos</a>)</td></tr>
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<tr class="separator:ga914a46fcb3b028610d9badb471c82bd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga412d59407e5dad43cf8ae1ea6f8bc5c3" id="r_ga412d59407e5dad43cf8ae1ea6f8bc5c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga412d59407e5dad43cf8ae1ea6f8bc5c3">RCC_APB1RSTR_I2C2RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga914a46fcb3b028610d9badb471c82bd3">RCC_APB1RSTR_I2C2RST_Msk</a></td></tr>
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<tr class="separator:ga412d59407e5dad43cf8ae1ea6f8bc5c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53079edbe7a089db7497d49b242b7e53" id="r_ga53079edbe7a089db7497d49b242b7e53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53079edbe7a089db7497d49b242b7e53">RCC_APB1RSTR_I2C3RST_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga53079edbe7a089db7497d49b242b7e53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49214147f146965ef75c3bfa906cd3d9" id="r_ga49214147f146965ef75c3bfa906cd3d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49214147f146965ef75c3bfa906cd3d9">RCC_APB1RSTR_I2C3RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga53079edbe7a089db7497d49b242b7e53">RCC_APB1RSTR_I2C3RST_Pos</a>)</td></tr>
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<tr class="separator:ga49214147f146965ef75c3bfa906cd3d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8dd6bd89cdf6b6b7affee5594bda87f" id="r_gab8dd6bd89cdf6b6b7affee5594bda87f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8dd6bd89cdf6b6b7affee5594bda87f">RCC_APB1RSTR_I2C3RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga49214147f146965ef75c3bfa906cd3d9">RCC_APB1RSTR_I2C3RST_Msk</a></td></tr>
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<tr class="separator:gab8dd6bd89cdf6b6b7affee5594bda87f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ac1f35767bba5fa2ab823d17dcf9b31" id="r_ga4ac1f35767bba5fa2ab823d17dcf9b31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ac1f35767bba5fa2ab823d17dcf9b31">RCC_APB1RSTR_CAN1RST_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga4ac1f35767bba5fa2ab823d17dcf9b31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91aa2d3e18674c6f02c7112da9a2e30c" id="r_ga91aa2d3e18674c6f02c7112da9a2e30c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91aa2d3e18674c6f02c7112da9a2e30c">RCC_APB1RSTR_CAN1RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ac1f35767bba5fa2ab823d17dcf9b31">RCC_APB1RSTR_CAN1RST_Pos</a>)</td></tr>
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<tr class="separator:ga91aa2d3e18674c6f02c7112da9a2e30c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23f9a8bfc02baedd992d13e489234242" id="r_ga23f9a8bfc02baedd992d13e489234242"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23f9a8bfc02baedd992d13e489234242">RCC_APB1RSTR_CAN1RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga91aa2d3e18674c6f02c7112da9a2e30c">RCC_APB1RSTR_CAN1RST_Msk</a></td></tr>
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<tr class="separator:ga23f9a8bfc02baedd992d13e489234242"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5695d6d01e07d1aba83edb9614fd108" id="r_gad5695d6d01e07d1aba83edb9614fd108"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5695d6d01e07d1aba83edb9614fd108">RCC_APB1RSTR_CAN2RST_Pos</a>   (26U)</td></tr>
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<tr class="separator:gad5695d6d01e07d1aba83edb9614fd108"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86dc2776b9926f9335e72b433290bb8a" id="r_ga86dc2776b9926f9335e72b433290bb8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86dc2776b9926f9335e72b433290bb8a">RCC_APB1RSTR_CAN2RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad5695d6d01e07d1aba83edb9614fd108">RCC_APB1RSTR_CAN2RST_Pos</a>)</td></tr>
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<tr class="separator:ga86dc2776b9926f9335e72b433290bb8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86b5d7042e23d54c7ecfcef2fbedad6e" id="r_ga86b5d7042e23d54c7ecfcef2fbedad6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86b5d7042e23d54c7ecfcef2fbedad6e">RCC_APB1RSTR_CAN2RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86dc2776b9926f9335e72b433290bb8a">RCC_APB1RSTR_CAN2RST_Msk</a></td></tr>
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<tr class="separator:ga86b5d7042e23d54c7ecfcef2fbedad6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48d1ad283fb0cc11c6394cc28e4da4d0" id="r_ga48d1ad283fb0cc11c6394cc28e4da4d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48d1ad283fb0cc11c6394cc28e4da4d0">RCC_APB1RSTR_PWRRST_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga48d1ad283fb0cc11c6394cc28e4da4d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe9ed6c6cee6df40b16793fe7479ea7a" id="r_gabe9ed6c6cee6df40b16793fe7479ea7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe9ed6c6cee6df40b16793fe7479ea7a">RCC_APB1RSTR_PWRRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48d1ad283fb0cc11c6394cc28e4da4d0">RCC_APB1RSTR_PWRRST_Pos</a>)</td></tr>
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<tr class="separator:gabe9ed6c6cee6df40b16793fe7479ea7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga274d8cb48f0e89831efabea66d64af2a" id="r_ga274d8cb48f0e89831efabea66d64af2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga274d8cb48f0e89831efabea66d64af2a">RCC_APB1RSTR_PWRRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe9ed6c6cee6df40b16793fe7479ea7a">RCC_APB1RSTR_PWRRST_Msk</a></td></tr>
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<tr class="separator:ga274d8cb48f0e89831efabea66d64af2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0612cbad1c01508c2c3acd8502a16f76" id="r_ga0612cbad1c01508c2c3acd8502a16f76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0612cbad1c01508c2c3acd8502a16f76">RCC_APB1RSTR_DACRST_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga0612cbad1c01508c2c3acd8502a16f76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09759c3881f10d9210653490a651f995" id="r_ga09759c3881f10d9210653490a651f995"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09759c3881f10d9210653490a651f995">RCC_APB1RSTR_DACRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0612cbad1c01508c2c3acd8502a16f76">RCC_APB1RSTR_DACRST_Pos</a>)</td></tr>
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<tr class="separator:ga09759c3881f10d9210653490a651f995"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7fb9c125237cfe5b6436ca795e7f3564" id="r_ga7fb9c125237cfe5b6436ca795e7f3564"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fb9c125237cfe5b6436ca795e7f3564">RCC_APB1RSTR_DACRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga09759c3881f10d9210653490a651f995">RCC_APB1RSTR_DACRST_Msk</a></td></tr>
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<tr class="separator:ga7fb9c125237cfe5b6436ca795e7f3564"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3439757d01e0c351ad8bc0193e3d90e" id="r_gae3439757d01e0c351ad8bc0193e3d90e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3439757d01e0c351ad8bc0193e3d90e">RCC_APB2RSTR_TIM1RST_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae3439757d01e0c351ad8bc0193e3d90e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6fc9f88241816d51a87a8b4a537c5a2e" id="r_ga6fc9f88241816d51a87a8b4a537c5a2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fc9f88241816d51a87a8b4a537c5a2e">RCC_APB2RSTR_TIM1RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3439757d01e0c351ad8bc0193e3d90e">RCC_APB2RSTR_TIM1RST_Pos</a>)</td></tr>
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<tr class="separator:ga6fc9f88241816d51a87a8b4a537c5a2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bd060cbefaef05487963bbd6c48d7c6" id="r_ga5bd060cbefaef05487963bbd6c48d7c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bd060cbefaef05487963bbd6c48d7c6">RCC_APB2RSTR_TIM1RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6fc9f88241816d51a87a8b4a537c5a2e">RCC_APB2RSTR_TIM1RST_Msk</a></td></tr>
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<tr class="separator:ga5bd060cbefaef05487963bbd6c48d7c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaab98fc817a93527229f575e6b642969" id="r_gaaab98fc817a93527229f575e6b642969"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaab98fc817a93527229f575e6b642969">RCC_APB2RSTR_TIM8RST_Pos</a>   (1U)</td></tr>
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<tr class="memitem:gab14242f5f656c5860137bd75f2a0515e" id="r_gab14242f5f656c5860137bd75f2a0515e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab14242f5f656c5860137bd75f2a0515e">RCC_APB2RSTR_TIM8RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaab98fc817a93527229f575e6b642969">RCC_APB2RSTR_TIM8RST_Pos</a>)</td></tr>
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<tr class="memitem:gaa129b34dbaf6c5301f751410ab4668ca" id="r_gaa129b34dbaf6c5301f751410ab4668ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa129b34dbaf6c5301f751410ab4668ca">RCC_APB2RSTR_TIM8RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab14242f5f656c5860137bd75f2a0515e">RCC_APB2RSTR_TIM8RST_Msk</a></td></tr>
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<tr class="memitem:gac07b0f4aae1366a80486993aa71c6237" id="r_gac07b0f4aae1366a80486993aa71c6237"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac07b0f4aae1366a80486993aa71c6237">RCC_APB2RSTR_USART1RST_Pos</a>   (4U)</td></tr>
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<tr class="separator:gac07b0f4aae1366a80486993aa71c6237"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49f18e05ca4a63d5b8fe937eb8613005" id="r_ga49f18e05ca4a63d5b8fe937eb8613005"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49f18e05ca4a63d5b8fe937eb8613005">RCC_APB2RSTR_USART1RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac07b0f4aae1366a80486993aa71c6237">RCC_APB2RSTR_USART1RST_Pos</a>)</td></tr>
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<tr class="separator:ga49f18e05ca4a63d5b8fe937eb8613005"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7ae8e338b3b42ad037e9e5b6eeb2c41" id="r_gae7ae8e338b3b42ad037e9e5b6eeb2c41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7ae8e338b3b42ad037e9e5b6eeb2c41">RCC_APB2RSTR_USART1RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga49f18e05ca4a63d5b8fe937eb8613005">RCC_APB2RSTR_USART1RST_Msk</a></td></tr>
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<tr class="separator:gae7ae8e338b3b42ad037e9e5b6eeb2c41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1aa2e760b59afddec0efc53fd80e60bf" id="r_ga1aa2e760b59afddec0efc53fd80e60bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1aa2e760b59afddec0efc53fd80e60bf">RCC_APB2RSTR_USART6RST_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga1aa2e760b59afddec0efc53fd80e60bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63e37e8ac731047e3df29ca5c7e553cc" id="r_ga63e37e8ac731047e3df29ca5c7e553cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63e37e8ac731047e3df29ca5c7e553cc">RCC_APB2RSTR_USART6RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1aa2e760b59afddec0efc53fd80e60bf">RCC_APB2RSTR_USART6RST_Pos</a>)</td></tr>
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<tr class="separator:ga63e37e8ac731047e3df29ca5c7e553cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada1df682293e15ed44b081d626220178" id="r_gada1df682293e15ed44b081d626220178"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada1df682293e15ed44b081d626220178">RCC_APB2RSTR_USART6RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63e37e8ac731047e3df29ca5c7e553cc">RCC_APB2RSTR_USART6RST_Msk</a></td></tr>
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<tr class="memitem:gafb93c28e2b44e753d961ee83fb829ad0" id="r_gafb93c28e2b44e753d961ee83fb829ad0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb93c28e2b44e753d961ee83fb829ad0">RCC_APB2RSTR_ADCRST_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga1a4836f2cd9be43193d6eb4d19d5dde6" id="r_ga1a4836f2cd9be43193d6eb4d19d5dde6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a4836f2cd9be43193d6eb4d19d5dde6">RCC_APB2RSTR_ADCRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafb93c28e2b44e753d961ee83fb829ad0">RCC_APB2RSTR_ADCRST_Pos</a>)</td></tr>
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<tr class="separator:ga1a4836f2cd9be43193d6eb4d19d5dde6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1374d6eae8e7d02d1ad457b65f374a67" id="r_ga1374d6eae8e7d02d1ad457b65f374a67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1374d6eae8e7d02d1ad457b65f374a67">RCC_APB2RSTR_ADCRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a4836f2cd9be43193d6eb4d19d5dde6">RCC_APB2RSTR_ADCRST_Msk</a></td></tr>
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<tr class="separator:ga1374d6eae8e7d02d1ad457b65f374a67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga964b8835939769ac1b9bd4984854757d" id="r_ga964b8835939769ac1b9bd4984854757d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga964b8835939769ac1b9bd4984854757d">RCC_APB2RSTR_SDIORST_Pos</a>   (11U)</td></tr>
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<tr class="memitem:gae67f4f982e0636f1d86be7d4223cdaf1" id="r_gae67f4f982e0636f1d86be7d4223cdaf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae67f4f982e0636f1d86be7d4223cdaf1">RCC_APB2RSTR_SDIORST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga964b8835939769ac1b9bd4984854757d">RCC_APB2RSTR_SDIORST_Pos</a>)</td></tr>
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<tr class="separator:gae67f4f982e0636f1d86be7d4223cdaf1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga754451a96f4c4faf63a29ca1a132c64d" id="r_ga754451a96f4c4faf63a29ca1a132c64d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga754451a96f4c4faf63a29ca1a132c64d">RCC_APB2RSTR_SDIORST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae67f4f982e0636f1d86be7d4223cdaf1">RCC_APB2RSTR_SDIORST_Msk</a></td></tr>
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<tr class="separator:ga754451a96f4c4faf63a29ca1a132c64d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f284f64839f82231c3e375e01105946" id="r_ga5f284f64839f82231c3e375e01105946"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f284f64839f82231c3e375e01105946">RCC_APB2RSTR_SPI1RST_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga5f284f64839f82231c3e375e01105946"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fb7fb16a3052da4a7d11cbdbe838689" id="r_ga4fb7fb16a3052da4a7d11cbdbe838689"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fb7fb16a3052da4a7d11cbdbe838689">RCC_APB2RSTR_SPI1RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f284f64839f82231c3e375e01105946">RCC_APB2RSTR_SPI1RST_Pos</a>)</td></tr>
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<tr class="separator:ga4fb7fb16a3052da4a7d11cbdbe838689"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga345f05d3508a9fd5128208761feb29fb" id="r_ga345f05d3508a9fd5128208761feb29fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga345f05d3508a9fd5128208761feb29fb">RCC_APB2RSTR_SPI1RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4fb7fb16a3052da4a7d11cbdbe838689">RCC_APB2RSTR_SPI1RST_Msk</a></td></tr>
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<tr class="separator:ga345f05d3508a9fd5128208761feb29fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga613a32917030cbb38e7897bdec0cad47" id="r_ga613a32917030cbb38e7897bdec0cad47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga613a32917030cbb38e7897bdec0cad47">RCC_APB2RSTR_SYSCFGRST_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga613a32917030cbb38e7897bdec0cad47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89f656408c45d2f67a99cc1c093d3e45" id="r_ga89f656408c45d2f67a99cc1c093d3e45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89f656408c45d2f67a99cc1c093d3e45">RCC_APB2RSTR_SYSCFGRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga613a32917030cbb38e7897bdec0cad47">RCC_APB2RSTR_SYSCFGRST_Pos</a>)</td></tr>
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<tr class="separator:ga89f656408c45d2f67a99cc1c093d3e45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga813d42b8d48ae6379c053a44870af49d" id="r_ga813d42b8d48ae6379c053a44870af49d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga813d42b8d48ae6379c053a44870af49d">RCC_APB2RSTR_SYSCFGRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga89f656408c45d2f67a99cc1c093d3e45">RCC_APB2RSTR_SYSCFGRST_Msk</a></td></tr>
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<tr class="separator:ga813d42b8d48ae6379c053a44870af49d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed9b13161f4dbf0f960abe15c7f9f045" id="r_gaed9b13161f4dbf0f960abe15c7f9f045"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed9b13161f4dbf0f960abe15c7f9f045">RCC_APB2RSTR_TIM9RST_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaed9b13161f4dbf0f960abe15c7f9f045"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad71d516052c6afded3292ada76c392a2" id="r_gad71d516052c6afded3292ada76c392a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad71d516052c6afded3292ada76c392a2">RCC_APB2RSTR_TIM9RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed9b13161f4dbf0f960abe15c7f9f045">RCC_APB2RSTR_TIM9RST_Pos</a>)</td></tr>
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<tr class="separator:gad71d516052c6afded3292ada76c392a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3aa588d4814a289d939e111492724af" id="r_gab3aa588d4814a289d939e111492724af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3aa588d4814a289d939e111492724af">RCC_APB2RSTR_TIM9RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad71d516052c6afded3292ada76c392a2">RCC_APB2RSTR_TIM9RST_Msk</a></td></tr>
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<tr class="memitem:ga01379fcaf1119cd7a25cdf930fe10458" id="r_ga01379fcaf1119cd7a25cdf930fe10458"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01379fcaf1119cd7a25cdf930fe10458">RCC_APB2RSTR_TIM10RST_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga01379fcaf1119cd7a25cdf930fe10458"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga077ef7ed92b0241e49f2ecad1a8bd241" id="r_ga077ef7ed92b0241e49f2ecad1a8bd241"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga077ef7ed92b0241e49f2ecad1a8bd241">RCC_APB2RSTR_TIM10RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01379fcaf1119cd7a25cdf930fe10458">RCC_APB2RSTR_TIM10RST_Pos</a>)</td></tr>
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<tr class="separator:ga077ef7ed92b0241e49f2ecad1a8bd241"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac76155acdc99c8c6502ba3beba818f42" id="r_gac76155acdc99c8c6502ba3beba818f42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac76155acdc99c8c6502ba3beba818f42">RCC_APB2RSTR_TIM10RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga077ef7ed92b0241e49f2ecad1a8bd241">RCC_APB2RSTR_TIM10RST_Msk</a></td></tr>
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<tr class="separator:gac76155acdc99c8c6502ba3beba818f42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d1b402b6082b891cf838cc69119b2a1" id="r_ga8d1b402b6082b891cf838cc69119b2a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1b402b6082b891cf838cc69119b2a1">RCC_APB2RSTR_TIM11RST_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga8d1b402b6082b891cf838cc69119b2a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ffe8d460fb9abc55ec65d00d39564b3" id="r_ga6ffe8d460fb9abc55ec65d00d39564b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ffe8d460fb9abc55ec65d00d39564b3">RCC_APB2RSTR_TIM11RST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1b402b6082b891cf838cc69119b2a1">RCC_APB2RSTR_TIM11RST_Pos</a>)</td></tr>
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<tr class="separator:ga6ffe8d460fb9abc55ec65d00d39564b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9651c8201d42ba03bb1bf89d9d39e60c" id="r_ga9651c8201d42ba03bb1bf89d9d39e60c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9651c8201d42ba03bb1bf89d9d39e60c">RCC_APB2RSTR_TIM11RST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ffe8d460fb9abc55ec65d00d39564b3">RCC_APB2RSTR_TIM11RST_Msk</a></td></tr>
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<tr class="separator:ga9651c8201d42ba03bb1bf89d9d39e60c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38f676c6c842fc9471d51a50584fbe91" id="r_ga38f676c6c842fc9471d51a50584fbe91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38f676c6c842fc9471d51a50584fbe91">RCC_APB2RSTR_SPI1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga345f05d3508a9fd5128208761feb29fb">RCC_APB2RSTR_SPI1RST</a></td></tr>
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<tr class="separator:ga38f676c6c842fc9471d51a50584fbe91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46ac0ea3dfd9fd9dc25a6fc974c0b2e7" id="r_ga46ac0ea3dfd9fd9dc25a6fc974c0b2e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46ac0ea3dfd9fd9dc25a6fc974c0b2e7">RCC_AHB1ENR_GPIOAEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga46ac0ea3dfd9fd9dc25a6fc974c0b2e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1610c0bcc3f778000c9ffe4ceaaf7a8" id="r_gaa1610c0bcc3f778000c9ffe4ceaaf7a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1610c0bcc3f778000c9ffe4ceaaf7a8">RCC_AHB1ENR_GPIOAEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46ac0ea3dfd9fd9dc25a6fc974c0b2e7">RCC_AHB1ENR_GPIOAEN_Pos</a>)</td></tr>
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<tr class="memitem:ga6ff46fb3b30fc6792e4fd18fcb0941b5" id="r_ga6ff46fb3b30fc6792e4fd18fcb0941b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ff46fb3b30fc6792e4fd18fcb0941b5">RCC_AHB1ENR_GPIOAEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1610c0bcc3f778000c9ffe4ceaaf7a8">RCC_AHB1ENR_GPIOAEN_Msk</a></td></tr>
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<tr class="separator:ga6ff46fb3b30fc6792e4fd18fcb0941b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e283561bd4c7f47c8ba5a3affae294a" id="r_ga9e283561bd4c7f47c8ba5a3affae294a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e283561bd4c7f47c8ba5a3affae294a">RCC_AHB1ENR_GPIOBEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga9e283561bd4c7f47c8ba5a3affae294a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79f6e5e212dee1b54f1103aa6c5b63c8" id="r_ga79f6e5e212dee1b54f1103aa6c5b63c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79f6e5e212dee1b54f1103aa6c5b63c8">RCC_AHB1ENR_GPIOBEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e283561bd4c7f47c8ba5a3affae294a">RCC_AHB1ENR_GPIOBEN_Pos</a>)</td></tr>
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<tr class="separator:ga79f6e5e212dee1b54f1103aa6c5b63c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7f408f92e7fd49b0957b8cb4ff31ca5" id="r_gad7f408f92e7fd49b0957b8cb4ff31ca5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7f408f92e7fd49b0957b8cb4ff31ca5">RCC_AHB1ENR_GPIOBEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga79f6e5e212dee1b54f1103aa6c5b63c8">RCC_AHB1ENR_GPIOBEN_Msk</a></td></tr>
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<tr class="separator:gad7f408f92e7fd49b0957b8cb4ff31ca5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b008be82ceb7ff8fc8b5b89c42d5956" id="r_ga2b008be82ceb7ff8fc8b5b89c42d5956"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b008be82ceb7ff8fc8b5b89c42d5956">RCC_AHB1ENR_GPIOCEN_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga2b008be82ceb7ff8fc8b5b89c42d5956"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d7e8d23a1214b25dca4d0838324371b" id="r_ga6d7e8d23a1214b25dca4d0838324371b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d7e8d23a1214b25dca4d0838324371b">RCC_AHB1ENR_GPIOCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b008be82ceb7ff8fc8b5b89c42d5956">RCC_AHB1ENR_GPIOCEN_Pos</a>)</td></tr>
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<tr class="separator:ga6d7e8d23a1214b25dca4d0838324371b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8a8b42e33aef2a7bc2d41ad9d231733" id="r_gae8a8b42e33aef2a7bc2d41ad9d231733"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8a8b42e33aef2a7bc2d41ad9d231733">RCC_AHB1ENR_GPIOCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d7e8d23a1214b25dca4d0838324371b">RCC_AHB1ENR_GPIOCEN_Msk</a></td></tr>
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<tr class="separator:gae8a8b42e33aef2a7bc2d41ad9d231733"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57c3badb1f83e08ab09719c58d70e1b4" id="r_ga57c3badb1f83e08ab09719c58d70e1b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57c3badb1f83e08ab09719c58d70e1b4">RCC_AHB1ENR_GPIODEN_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga57c3badb1f83e08ab09719c58d70e1b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5da72a3a599290c99b251cf0e40d579a" id="r_ga5da72a3a599290c99b251cf0e40d579a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5da72a3a599290c99b251cf0e40d579a">RCC_AHB1ENR_GPIODEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57c3badb1f83e08ab09719c58d70e1b4">RCC_AHB1ENR_GPIODEN_Pos</a>)</td></tr>
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<tr class="separator:ga5da72a3a599290c99b251cf0e40d579a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebd8146e91c76f14af8dfe78a1c2d916" id="r_gaebd8146e91c76f14af8dfe78a1c2d916"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebd8146e91c76f14af8dfe78a1c2d916">RCC_AHB1ENR_GPIODEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5da72a3a599290c99b251cf0e40d579a">RCC_AHB1ENR_GPIODEN_Msk</a></td></tr>
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<tr class="separator:gaebd8146e91c76f14af8dfe78a1c2d916"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2313a0beb0ceb64be0c3c2906c9d11c1" id="r_ga2313a0beb0ceb64be0c3c2906c9d11c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2313a0beb0ceb64be0c3c2906c9d11c1">RCC_AHB1ENR_GPIOEEN_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga2313a0beb0ceb64be0c3c2906c9d11c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga574a0ff2d711679c81d62a365efe9b25" id="r_ga574a0ff2d711679c81d62a365efe9b25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga574a0ff2d711679c81d62a365efe9b25">RCC_AHB1ENR_GPIOEEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2313a0beb0ceb64be0c3c2906c9d11c1">RCC_AHB1ENR_GPIOEEN_Pos</a>)</td></tr>
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<tr class="separator:ga574a0ff2d711679c81d62a365efe9b25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67a9094e0e464eaa8e25f854f90abfc6" id="r_ga67a9094e0e464eaa8e25f854f90abfc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67a9094e0e464eaa8e25f854f90abfc6">RCC_AHB1ENR_GPIOEEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga574a0ff2d711679c81d62a365efe9b25">RCC_AHB1ENR_GPIOEEN_Msk</a></td></tr>
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<tr class="separator:ga67a9094e0e464eaa8e25f854f90abfc6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga086e36c7f473c1290b8b837dbb6cefbd" id="r_ga086e36c7f473c1290b8b837dbb6cefbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga086e36c7f473c1290b8b837dbb6cefbd">RCC_AHB1ENR_GPIOFEN_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga086e36c7f473c1290b8b837dbb6cefbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac40bd7a86de787e99ecf69881e8d8803" id="r_gac40bd7a86de787e99ecf69881e8d8803"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac40bd7a86de787e99ecf69881e8d8803">RCC_AHB1ENR_GPIOFEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga086e36c7f473c1290b8b837dbb6cefbd">RCC_AHB1ENR_GPIOFEN_Pos</a>)</td></tr>
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<tr class="separator:gac40bd7a86de787e99ecf69881e8d8803"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefa8e0fbecedb4167a4d7ef51e2a48b5" id="r_gaefa8e0fbecedb4167a4d7ef51e2a48b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefa8e0fbecedb4167a4d7ef51e2a48b5">RCC_AHB1ENR_GPIOFEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac40bd7a86de787e99ecf69881e8d8803">RCC_AHB1ENR_GPIOFEN_Msk</a></td></tr>
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<tr class="separator:gaefa8e0fbecedb4167a4d7ef51e2a48b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga746fd16f381b86d549e73d73977b408d" id="r_ga746fd16f381b86d549e73d73977b408d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga746fd16f381b86d549e73d73977b408d">RCC_AHB1ENR_GPIOGEN_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga746fd16f381b86d549e73d73977b408d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84f85f90ddfceebacab190e14cf0de75" id="r_ga84f85f90ddfceebacab190e14cf0de75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84f85f90ddfceebacab190e14cf0de75">RCC_AHB1ENR_GPIOGEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga746fd16f381b86d549e73d73977b408d">RCC_AHB1ENR_GPIOGEN_Pos</a>)</td></tr>
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<tr class="separator:ga84f85f90ddfceebacab190e14cf0de75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5304e897036391c916ef82258919a08b" id="r_ga5304e897036391c916ef82258919a08b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5304e897036391c916ef82258919a08b">RCC_AHB1ENR_GPIOGEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga84f85f90ddfceebacab190e14cf0de75">RCC_AHB1ENR_GPIOGEN_Msk</a></td></tr>
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<tr class="separator:ga5304e897036391c916ef82258919a08b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37d856370c08a4704127d615939510e8" id="r_ga37d856370c08a4704127d615939510e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37d856370c08a4704127d615939510e8">RCC_AHB1ENR_GPIOHEN_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga37d856370c08a4704127d615939510e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee11e4e6ddeff9db3ddd22873d1ca8d5" id="r_gaee11e4e6ddeff9db3ddd22873d1ca8d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee11e4e6ddeff9db3ddd22873d1ca8d5">RCC_AHB1ENR_GPIOHEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga37d856370c08a4704127d615939510e8">RCC_AHB1ENR_GPIOHEN_Pos</a>)</td></tr>
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<tr class="separator:gaee11e4e6ddeff9db3ddd22873d1ca8d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb16afc550121895822ebb22108196b6" id="r_gadb16afc550121895822ebb22108196b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb16afc550121895822ebb22108196b6">RCC_AHB1ENR_GPIOHEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaee11e4e6ddeff9db3ddd22873d1ca8d5">RCC_AHB1ENR_GPIOHEN_Msk</a></td></tr>
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<tr class="separator:gadb16afc550121895822ebb22108196b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea6afabe8b46415f972a1e54a605decf" id="r_gaea6afabe8b46415f972a1e54a605decf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea6afabe8b46415f972a1e54a605decf">RCC_AHB1ENR_GPIOIEN_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaea6afabe8b46415f972a1e54a605decf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d542abb9e4477f575afe1066062ce34" id="r_ga3d542abb9e4477f575afe1066062ce34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d542abb9e4477f575afe1066062ce34">RCC_AHB1ENR_GPIOIEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea6afabe8b46415f972a1e54a605decf">RCC_AHB1ENR_GPIOIEN_Pos</a>)</td></tr>
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<tr class="separator:ga3d542abb9e4477f575afe1066062ce34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadee44347a6a62429ee74753fe1dea5d7" id="r_gadee44347a6a62429ee74753fe1dea5d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadee44347a6a62429ee74753fe1dea5d7">RCC_AHB1ENR_GPIOIEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d542abb9e4477f575afe1066062ce34">RCC_AHB1ENR_GPIOIEN_Msk</a></td></tr>
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<tr class="separator:gadee44347a6a62429ee74753fe1dea5d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf0c26180146aedeec41861fd765a05c" id="r_gadf0c26180146aedeec41861fd765a05c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf0c26180146aedeec41861fd765a05c">RCC_AHB1ENR_CRCEN_Pos</a>   (12U)</td></tr>
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<tr class="separator:gadf0c26180146aedeec41861fd765a05c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b467a2c6329ecb8ca42c1d9e1116035" id="r_ga3b467a2c6329ecb8ca42c1d9e1116035"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b467a2c6329ecb8ca42c1d9e1116035">RCC_AHB1ENR_CRCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf0c26180146aedeec41861fd765a05c">RCC_AHB1ENR_CRCEN_Pos</a>)</td></tr>
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<tr class="separator:ga3b467a2c6329ecb8ca42c1d9e1116035"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa3d41f31401e812f839defee241df83" id="r_gafa3d41f31401e812f839defee241df83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa3d41f31401e812f839defee241df83">RCC_AHB1ENR_CRCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b467a2c6329ecb8ca42c1d9e1116035">RCC_AHB1ENR_CRCEN_Msk</a></td></tr>
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<tr class="separator:gafa3d41f31401e812f839defee241df83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6732dcee9b2bf278527a55f9c14d703c" id="r_ga6732dcee9b2bf278527a55f9c14d703c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6732dcee9b2bf278527a55f9c14d703c">RCC_AHB1ENR_BKPSRAMEN_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga6732dcee9b2bf278527a55f9c14d703c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67735d069e447a3cbd8b1cf0ac1e69ca" id="r_ga67735d069e447a3cbd8b1cf0ac1e69ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67735d069e447a3cbd8b1cf0ac1e69ca">RCC_AHB1ENR_BKPSRAMEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6732dcee9b2bf278527a55f9c14d703c">RCC_AHB1ENR_BKPSRAMEN_Pos</a>)</td></tr>
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<tr class="separator:ga67735d069e447a3cbd8b1cf0ac1e69ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee10e5e11a2043e4ff865c3d7b804233" id="r_gaee10e5e11a2043e4ff865c3d7b804233"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee10e5e11a2043e4ff865c3d7b804233">RCC_AHB1ENR_BKPSRAMEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67735d069e447a3cbd8b1cf0ac1e69ca">RCC_AHB1ENR_BKPSRAMEN_Msk</a></td></tr>
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<tr class="separator:gaee10e5e11a2043e4ff865c3d7b804233"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac74e8dc5505978a1b2cb109d0c77c559" id="r_gac74e8dc5505978a1b2cb109d0c77c559"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac74e8dc5505978a1b2cb109d0c77c559">RCC_AHB1ENR_CCMDATARAMEN_Pos</a>   (20U)</td></tr>
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<tr class="separator:gac74e8dc5505978a1b2cb109d0c77c559"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae56a123a2131232460f2a1d4d7b5fb87" id="r_gae56a123a2131232460f2a1d4d7b5fb87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae56a123a2131232460f2a1d4d7b5fb87">RCC_AHB1ENR_CCMDATARAMEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac74e8dc5505978a1b2cb109d0c77c559">RCC_AHB1ENR_CCMDATARAMEN_Pos</a>)</td></tr>
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<tr class="separator:gae56a123a2131232460f2a1d4d7b5fb87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29bbdcc191708a9e6a46ef197a3b2c65" id="r_ga29bbdcc191708a9e6a46ef197a3b2c65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29bbdcc191708a9e6a46ef197a3b2c65">RCC_AHB1ENR_CCMDATARAMEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae56a123a2131232460f2a1d4d7b5fb87">RCC_AHB1ENR_CCMDATARAMEN_Msk</a></td></tr>
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<tr class="separator:ga29bbdcc191708a9e6a46ef197a3b2c65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0114d8249d989c5ab3feac252e30509e" id="r_ga0114d8249d989c5ab3feac252e30509e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0114d8249d989c5ab3feac252e30509e">RCC_AHB1ENR_DMA1EN_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga0114d8249d989c5ab3feac252e30509e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab04b66dc0d69d098db894416722e9871" id="r_gab04b66dc0d69d098db894416722e9871"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab04b66dc0d69d098db894416722e9871">RCC_AHB1ENR_DMA1EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0114d8249d989c5ab3feac252e30509e">RCC_AHB1ENR_DMA1EN_Pos</a>)</td></tr>
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<tr class="separator:gab04b66dc0d69d098db894416722e9871"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae07b00778a51a4e52b911aeccb897aba" id="r_gae07b00778a51a4e52b911aeccb897aba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae07b00778a51a4e52b911aeccb897aba">RCC_AHB1ENR_DMA1EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab04b66dc0d69d098db894416722e9871">RCC_AHB1ENR_DMA1EN_Msk</a></td></tr>
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<tr class="separator:gae07b00778a51a4e52b911aeccb897aba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf754f312ede73c0d5d35e1a08b614f94" id="r_gaf754f312ede73c0d5d35e1a08b614f94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf754f312ede73c0d5d35e1a08b614f94">RCC_AHB1ENR_DMA2EN_Pos</a>   (22U)</td></tr>
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<tr class="separator:gaf754f312ede73c0d5d35e1a08b614f94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb95b569d5ea1d4c9483fbfd7df37f3a" id="r_gaeb95b569d5ea1d4c9483fbfd7df37f3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb95b569d5ea1d4c9483fbfd7df37f3a">RCC_AHB1ENR_DMA2EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf754f312ede73c0d5d35e1a08b614f94">RCC_AHB1ENR_DMA2EN_Pos</a>)</td></tr>
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<tr class="separator:gaeb95b569d5ea1d4c9483fbfd7df37f3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga664a5d572a39a0c084e4ee7c1cf7df0d" id="r_ga664a5d572a39a0c084e4ee7c1cf7df0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga664a5d572a39a0c084e4ee7c1cf7df0d">RCC_AHB1ENR_DMA2EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb95b569d5ea1d4c9483fbfd7df37f3a">RCC_AHB1ENR_DMA2EN_Msk</a></td></tr>
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<tr class="separator:ga664a5d572a39a0c084e4ee7c1cf7df0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43785491862d48d7a9f0651f6e94a388" id="r_ga43785491862d48d7a9f0651f6e94a388"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43785491862d48d7a9f0651f6e94a388">RCC_AHB1ENR_ETHMACEN_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga43785491862d48d7a9f0651f6e94a388"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7f4087101bf2a82c3ac9ea31ca3504f" id="r_gaf7f4087101bf2a82c3ac9ea31ca3504f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7f4087101bf2a82c3ac9ea31ca3504f">RCC_AHB1ENR_ETHMACEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga43785491862d48d7a9f0651f6e94a388">RCC_AHB1ENR_ETHMACEN_Pos</a>)</td></tr>
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<tr class="separator:gaf7f4087101bf2a82c3ac9ea31ca3504f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga507020c3c3945dfbf3d628ffa42afdba" id="r_ga507020c3c3945dfbf3d628ffa42afdba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga507020c3c3945dfbf3d628ffa42afdba">RCC_AHB1ENR_ETHMACEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7f4087101bf2a82c3ac9ea31ca3504f">RCC_AHB1ENR_ETHMACEN_Msk</a></td></tr>
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<tr class="separator:ga507020c3c3945dfbf3d628ffa42afdba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab032942ed246f6386d792915da6519e7" id="r_gab032942ed246f6386d792915da6519e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab032942ed246f6386d792915da6519e7">RCC_AHB1ENR_ETHMACTXEN_Pos</a>   (26U)</td></tr>
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<tr class="separator:gab032942ed246f6386d792915da6519e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7e9fa8c5b341bd2c8e1354ea0452990" id="r_gaf7e9fa8c5b341bd2c8e1354ea0452990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7e9fa8c5b341bd2c8e1354ea0452990">RCC_AHB1ENR_ETHMACTXEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab032942ed246f6386d792915da6519e7">RCC_AHB1ENR_ETHMACTXEN_Pos</a>)</td></tr>
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<tr class="separator:gaf7e9fa8c5b341bd2c8e1354ea0452990"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga001f617c29d950ee1aa91773331ae6f6" id="r_ga001f617c29d950ee1aa91773331ae6f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga001f617c29d950ee1aa91773331ae6f6">RCC_AHB1ENR_ETHMACTXEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7e9fa8c5b341bd2c8e1354ea0452990">RCC_AHB1ENR_ETHMACTXEN_Msk</a></td></tr>
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<tr class="separator:ga001f617c29d950ee1aa91773331ae6f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac12dfc1c179aa47c0bf97a005974182e" id="r_gac12dfc1c179aa47c0bf97a005974182e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac12dfc1c179aa47c0bf97a005974182e">RCC_AHB1ENR_ETHMACRXEN_Pos</a>   (27U)</td></tr>
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<tr class="separator:gac12dfc1c179aa47c0bf97a005974182e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9872ba78cf86d347267020336489be40" id="r_ga9872ba78cf86d347267020336489be40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9872ba78cf86d347267020336489be40">RCC_AHB1ENR_ETHMACRXEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac12dfc1c179aa47c0bf97a005974182e">RCC_AHB1ENR_ETHMACRXEN_Pos</a>)</td></tr>
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<tr class="separator:ga9872ba78cf86d347267020336489be40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8933482a90a769d0cdd332b170132b77" id="r_ga8933482a90a769d0cdd332b170132b77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8933482a90a769d0cdd332b170132b77">RCC_AHB1ENR_ETHMACRXEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9872ba78cf86d347267020336489be40">RCC_AHB1ENR_ETHMACRXEN_Msk</a></td></tr>
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<tr class="separator:ga8933482a90a769d0cdd332b170132b77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bedafca82770123ee737720df26612e" id="r_ga9bedafca82770123ee737720df26612e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bedafca82770123ee737720df26612e">RCC_AHB1ENR_ETHMACPTPEN_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga9bedafca82770123ee737720df26612e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41c39ec61603f15cf1916d743f1e3673" id="r_ga41c39ec61603f15cf1916d743f1e3673"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41c39ec61603f15cf1916d743f1e3673">RCC_AHB1ENR_ETHMACPTPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9bedafca82770123ee737720df26612e">RCC_AHB1ENR_ETHMACPTPEN_Pos</a>)</td></tr>
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<tr class="separator:ga41c39ec61603f15cf1916d743f1e3673"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bf11a8d105bc59e4f509d91cbf05e0e" id="r_ga2bf11a8d105bc59e4f509d91cbf05e0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf11a8d105bc59e4f509d91cbf05e0e">RCC_AHB1ENR_ETHMACPTPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga41c39ec61603f15cf1916d743f1e3673">RCC_AHB1ENR_ETHMACPTPEN_Msk</a></td></tr>
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<tr class="separator:ga2bf11a8d105bc59e4f509d91cbf05e0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd0aa66629d449a07dea64c30ca67c5e" id="r_gadd0aa66629d449a07dea64c30ca67c5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd0aa66629d449a07dea64c30ca67c5e">RCC_AHB1ENR_OTGHSEN_Pos</a>   (29U)</td></tr>
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<tr class="separator:gadd0aa66629d449a07dea64c30ca67c5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44e119c40f74b0caf89d18b8e784d7cd" id="r_ga44e119c40f74b0caf89d18b8e784d7cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44e119c40f74b0caf89d18b8e784d7cd">RCC_AHB1ENR_OTGHSEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadd0aa66629d449a07dea64c30ca67c5e">RCC_AHB1ENR_OTGHSEN_Pos</a>)</td></tr>
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<tr class="separator:ga44e119c40f74b0caf89d18b8e784d7cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab18d15ea68876f7a42ee7350074b05f4" id="r_gab18d15ea68876f7a42ee7350074b05f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab18d15ea68876f7a42ee7350074b05f4">RCC_AHB1ENR_OTGHSEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44e119c40f74b0caf89d18b8e784d7cd">RCC_AHB1ENR_OTGHSEN_Msk</a></td></tr>
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<tr class="separator:gab18d15ea68876f7a42ee7350074b05f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga073b5e5498b3a169555570dc126d11fb" id="r_ga073b5e5498b3a169555570dc126d11fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga073b5e5498b3a169555570dc126d11fb">RCC_AHB1ENR_OTGHSULPIEN_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga073b5e5498b3a169555570dc126d11fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga162543647ebac3ea7cf992bf229acb56" id="r_ga162543647ebac3ea7cf992bf229acb56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga162543647ebac3ea7cf992bf229acb56">RCC_AHB1ENR_OTGHSULPIEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga073b5e5498b3a169555570dc126d11fb">RCC_AHB1ENR_OTGHSULPIEN_Pos</a>)</td></tr>
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<tr class="separator:ga162543647ebac3ea7cf992bf229acb56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga784be313f54862d3670723f2334fa51f" id="r_ga784be313f54862d3670723f2334fa51f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga784be313f54862d3670723f2334fa51f">RCC_AHB1ENR_OTGHSULPIEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga162543647ebac3ea7cf992bf229acb56">RCC_AHB1ENR_OTGHSULPIEN_Msk</a></td></tr>
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<tr class="separator:ga784be313f54862d3670723f2334fa51f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad47614352bcc5025572abc4277cf28e9" id="r_gad47614352bcc5025572abc4277cf28e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad47614352bcc5025572abc4277cf28e9">RCC_AHB2_SUPPORT</a></td></tr>
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<tr class="separator:gad47614352bcc5025572abc4277cf28e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2491b75f6353ed39e93a2c9e8ea81052" id="r_ga2491b75f6353ed39e93a2c9e8ea81052"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2491b75f6353ed39e93a2c9e8ea81052">RCC_AHB2ENR_DCMIEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2491b75f6353ed39e93a2c9e8ea81052"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga392371f5ae1fc6417aa8111e46184b17" id="r_ga392371f5ae1fc6417aa8111e46184b17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga392371f5ae1fc6417aa8111e46184b17">RCC_AHB2ENR_DCMIEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2491b75f6353ed39e93a2c9e8ea81052">RCC_AHB2ENR_DCMIEN_Pos</a>)</td></tr>
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<tr class="separator:ga392371f5ae1fc6417aa8111e46184b17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe6b7edde44307072327fcae3c15c8d0" id="r_gafe6b7edde44307072327fcae3c15c8d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe6b7edde44307072327fcae3c15c8d0">RCC_AHB2ENR_DCMIEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga392371f5ae1fc6417aa8111e46184b17">RCC_AHB2ENR_DCMIEN_Msk</a></td></tr>
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<tr class="separator:gafe6b7edde44307072327fcae3c15c8d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf92e60b54c63999846b0e8392131a6c" id="r_gadf92e60b54c63999846b0e8392131a6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf92e60b54c63999846b0e8392131a6c">RCC_AHB2ENR_RNGEN_Pos</a>   (6U)</td></tr>
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<tr class="memitem:gabe2170ecd918ffe5d888e76c3dcd5cab" id="r_gabe2170ecd918ffe5d888e76c3dcd5cab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe2170ecd918ffe5d888e76c3dcd5cab">RCC_AHB2ENR_RNGEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf92e60b54c63999846b0e8392131a6c">RCC_AHB2ENR_RNGEN_Pos</a>)</td></tr>
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<tr class="separator:gabe2170ecd918ffe5d888e76c3dcd5cab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadea5123ece7df53e695697e3a7d11a6b" id="r_gadea5123ece7df53e695697e3a7d11a6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadea5123ece7df53e695697e3a7d11a6b">RCC_AHB2ENR_RNGEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe2170ecd918ffe5d888e76c3dcd5cab">RCC_AHB2ENR_RNGEN_Msk</a></td></tr>
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<tr class="separator:gadea5123ece7df53e695697e3a7d11a6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80a6b042ea1a1362cba76f697a2b941c" id="r_ga80a6b042ea1a1362cba76f697a2b941c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80a6b042ea1a1362cba76f697a2b941c">RCC_AHB2ENR_OTGFSEN_Pos</a>   (7U)</td></tr>
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<tr class="memitem:ga9c92c5e4271a2a493a92fb41fbc7e3fd" id="r_ga9c92c5e4271a2a493a92fb41fbc7e3fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c92c5e4271a2a493a92fb41fbc7e3fd">RCC_AHB2ENR_OTGFSEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga80a6b042ea1a1362cba76f697a2b941c">RCC_AHB2ENR_OTGFSEN_Pos</a>)</td></tr>
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<tr class="separator:ga9c92c5e4271a2a493a92fb41fbc7e3fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22576caeba7c7a1e6afdd0b90394c76d" id="r_ga22576caeba7c7a1e6afdd0b90394c76d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22576caeba7c7a1e6afdd0b90394c76d">RCC_AHB2ENR_OTGFSEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c92c5e4271a2a493a92fb41fbc7e3fd">RCC_AHB2ENR_OTGFSEN_Msk</a></td></tr>
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<tr class="separator:ga22576caeba7c7a1e6afdd0b90394c76d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab59e70532c57e0a7917acac00de9db57" id="r_gab59e70532c57e0a7917acac00de9db57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab59e70532c57e0a7917acac00de9db57">RCC_AHB3_SUPPORT</a></td></tr>
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<tr class="memitem:gaa90ab430537857e2683deb2c628a4ca7" id="r_gaa90ab430537857e2683deb2c628a4ca7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa90ab430537857e2683deb2c628a4ca7">RCC_AHB3ENR_FSMCEN_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga518c0730a8f98a8b8ed6f75f0101f7fb" id="r_ga518c0730a8f98a8b8ed6f75f0101f7fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga518c0730a8f98a8b8ed6f75f0101f7fb">RCC_AHB3ENR_FSMCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa90ab430537857e2683deb2c628a4ca7">RCC_AHB3ENR_FSMCEN_Pos</a>)</td></tr>
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<tr class="separator:ga518c0730a8f98a8b8ed6f75f0101f7fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30d723abc39a230a71760dff91bb6d7b" id="r_ga30d723abc39a230a71760dff91bb6d7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30d723abc39a230a71760dff91bb6d7b">RCC_AHB3ENR_FSMCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga518c0730a8f98a8b8ed6f75f0101f7fb">RCC_AHB3ENR_FSMCEN_Msk</a></td></tr>
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<tr class="separator:ga30d723abc39a230a71760dff91bb6d7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7c1e030bdf85faeae65b74850497e29" id="r_gaa7c1e030bdf85faeae65b74850497e29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7c1e030bdf85faeae65b74850497e29">RCC_APB1ENR_TIM2EN_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa7c1e030bdf85faeae65b74850497e29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ed542e8a186c731ad3221c61b4aa81a" id="r_ga7ed542e8a186c731ad3221c61b4aa81a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ed542e8a186c731ad3221c61b4aa81a">RCC_APB1ENR_TIM2EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7c1e030bdf85faeae65b74850497e29">RCC_APB1ENR_TIM2EN_Pos</a>)</td></tr>
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<tr class="separator:ga7ed542e8a186c731ad3221c61b4aa81a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd3966a4d6ae47f06b3c095eaf26a610" id="r_gacd3966a4d6ae47f06b3c095eaf26a610"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd3966a4d6ae47f06b3c095eaf26a610">RCC_APB1ENR_TIM2EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ed542e8a186c731ad3221c61b4aa81a">RCC_APB1ENR_TIM2EN_Msk</a></td></tr>
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<tr class="separator:gacd3966a4d6ae47f06b3c095eaf26a610"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga512bf591e0527e83b8ae823c42da2f1e" id="r_ga512bf591e0527e83b8ae823c42da2f1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga512bf591e0527e83b8ae823c42da2f1e">RCC_APB1ENR_TIM3EN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga512bf591e0527e83b8ae823c42da2f1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39d58d377cd38e5685344b7d9a88ce1c" id="r_ga39d58d377cd38e5685344b7d9a88ce1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39d58d377cd38e5685344b7d9a88ce1c">RCC_APB1ENR_TIM3EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga512bf591e0527e83b8ae823c42da2f1e">RCC_APB1ENR_TIM3EN_Pos</a>)</td></tr>
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<tr class="separator:ga39d58d377cd38e5685344b7d9a88ce1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75bfa33eb00ee30c6e22f7ceea464ac7" id="r_ga75bfa33eb00ee30c6e22f7ceea464ac7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75bfa33eb00ee30c6e22f7ceea464ac7">RCC_APB1ENR_TIM3EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga39d58d377cd38e5685344b7d9a88ce1c">RCC_APB1ENR_TIM3EN_Msk</a></td></tr>
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<tr class="separator:ga75bfa33eb00ee30c6e22f7ceea464ac7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad32ced9621c44cd74f36cbfdec22582e" id="r_gad32ced9621c44cd74f36cbfdec22582e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad32ced9621c44cd74f36cbfdec22582e">RCC_APB1ENR_TIM4EN_Pos</a>   (2U)</td></tr>
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<tr class="separator:gad32ced9621c44cd74f36cbfdec22582e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef489da1fe7bd776d2fc27eb689fd9c4" id="r_gaef489da1fe7bd776d2fc27eb689fd9c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef489da1fe7bd776d2fc27eb689fd9c4">RCC_APB1ENR_TIM4EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad32ced9621c44cd74f36cbfdec22582e">RCC_APB1ENR_TIM4EN_Pos</a>)</td></tr>
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<tr class="separator:gaef489da1fe7bd776d2fc27eb689fd9c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4fbbf6b1beeec92c7d80e9e05bd1461" id="r_gad4fbbf6b1beeec92c7d80e9e05bd1461"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4fbbf6b1beeec92c7d80e9e05bd1461">RCC_APB1ENR_TIM4EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaef489da1fe7bd776d2fc27eb689fd9c4">RCC_APB1ENR_TIM4EN_Msk</a></td></tr>
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<tr class="separator:gad4fbbf6b1beeec92c7d80e9e05bd1461"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9022ea1b9729864c70216a4f04326f22" id="r_ga9022ea1b9729864c70216a4f04326f22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9022ea1b9729864c70216a4f04326f22">RCC_APB1ENR_TIM5EN_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga9022ea1b9729864c70216a4f04326f22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50e3f7f788191131f045cd40594e5c15" id="r_ga50e3f7f788191131f045cd40594e5c15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50e3f7f788191131f045cd40594e5c15">RCC_APB1ENR_TIM5EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9022ea1b9729864c70216a4f04326f22">RCC_APB1ENR_TIM5EN_Pos</a>)</td></tr>
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<tr class="separator:ga50e3f7f788191131f045cd40594e5c15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49abbbc8fd297c544df2d337b28f80e4" id="r_ga49abbbc8fd297c544df2d337b28f80e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49abbbc8fd297c544df2d337b28f80e4">RCC_APB1ENR_TIM5EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga50e3f7f788191131f045cd40594e5c15">RCC_APB1ENR_TIM5EN_Msk</a></td></tr>
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<tr class="separator:ga49abbbc8fd297c544df2d337b28f80e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae48475ae28539f1a2ce3852fbd7c1e71" id="r_gae48475ae28539f1a2ce3852fbd7c1e71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae48475ae28539f1a2ce3852fbd7c1e71">RCC_APB1ENR_TIM6EN_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae48475ae28539f1a2ce3852fbd7c1e71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34240ad1a5f4eb5ed19e7104da631d1e" id="r_ga34240ad1a5f4eb5ed19e7104da631d1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34240ad1a5f4eb5ed19e7104da631d1e">RCC_APB1ENR_TIM6EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae48475ae28539f1a2ce3852fbd7c1e71">RCC_APB1ENR_TIM6EN_Pos</a>)</td></tr>
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<tr class="separator:ga34240ad1a5f4eb5ed19e7104da631d1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb0279b1f0ff35c2df728d9653cabc0c" id="r_gafb0279b1f0ff35c2df728d9653cabc0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb0279b1f0ff35c2df728d9653cabc0c">RCC_APB1ENR_TIM6EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34240ad1a5f4eb5ed19e7104da631d1e">RCC_APB1ENR_TIM6EN_Msk</a></td></tr>
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<tr class="separator:gafb0279b1f0ff35c2df728d9653cabc0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c3d0403cb8a2a9daa5f789e3547d27d" id="r_ga4c3d0403cb8a2a9daa5f789e3547d27d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c3d0403cb8a2a9daa5f789e3547d27d">RCC_APB1ENR_TIM7EN_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga4c3d0403cb8a2a9daa5f789e3547d27d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d3160c7aa3480db783e4cc7f50ed721" id="r_ga6d3160c7aa3480db783e4cc7f50ed721"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d3160c7aa3480db783e4cc7f50ed721">RCC_APB1ENR_TIM7EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c3d0403cb8a2a9daa5f789e3547d27d">RCC_APB1ENR_TIM7EN_Pos</a>)</td></tr>
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<tr class="separator:ga6d3160c7aa3480db783e4cc7f50ed721"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab595fbaf4167297d8fe2825e41f41990" id="r_gab595fbaf4167297d8fe2825e41f41990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab595fbaf4167297d8fe2825e41f41990">RCC_APB1ENR_TIM7EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d3160c7aa3480db783e4cc7f50ed721">RCC_APB1ENR_TIM7EN_Msk</a></td></tr>
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<tr class="separator:gab595fbaf4167297d8fe2825e41f41990"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec84991ddba58f7037cd8113725a26f7" id="r_gaec84991ddba58f7037cd8113725a26f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec84991ddba58f7037cd8113725a26f7">RCC_APB1ENR_TIM12EN_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaec84991ddba58f7037cd8113725a26f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabca933b42794cadbf3580851e625779e" id="r_gabca933b42794cadbf3580851e625779e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabca933b42794cadbf3580851e625779e">RCC_APB1ENR_TIM12EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaec84991ddba58f7037cd8113725a26f7">RCC_APB1ENR_TIM12EN_Pos</a>)</td></tr>
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<tr class="memitem:gaecd88b56485ee4ee3e406b1d6c062081" id="r_gaecd88b56485ee4ee3e406b1d6c062081"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecd88b56485ee4ee3e406b1d6c062081">RCC_APB1ENR_TIM12EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabca933b42794cadbf3580851e625779e">RCC_APB1ENR_TIM12EN_Msk</a></td></tr>
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<tr class="separator:gaecd88b56485ee4ee3e406b1d6c062081"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3865266fac7bea00e89cd1c19eb3b39f" id="r_ga3865266fac7bea00e89cd1c19eb3b39f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3865266fac7bea00e89cd1c19eb3b39f">RCC_APB1ENR_TIM13EN_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga3865266fac7bea00e89cd1c19eb3b39f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c6f74911cd1852c3a58e969e48013d8" id="r_ga7c6f74911cd1852c3a58e969e48013d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c6f74911cd1852c3a58e969e48013d8">RCC_APB1ENR_TIM13EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3865266fac7bea00e89cd1c19eb3b39f">RCC_APB1ENR_TIM13EN_Pos</a>)</td></tr>
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<tr class="memitem:ga1a95079e68e7c76584ef0b3de371288a" id="r_ga1a95079e68e7c76584ef0b3de371288a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a95079e68e7c76584ef0b3de371288a">RCC_APB1ENR_TIM13EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c6f74911cd1852c3a58e969e48013d8">RCC_APB1ENR_TIM13EN_Msk</a></td></tr>
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<tr class="separator:ga1a95079e68e7c76584ef0b3de371288a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3341bca36df7d92a24e7e1355265421c" id="r_ga3341bca36df7d92a24e7e1355265421c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3341bca36df7d92a24e7e1355265421c">RCC_APB1ENR_TIM14EN_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gaecb332ea40285657d968307a8cef8951" id="r_gaecb332ea40285657d968307a8cef8951"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecb332ea40285657d968307a8cef8951">RCC_APB1ENR_TIM14EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3341bca36df7d92a24e7e1355265421c">RCC_APB1ENR_TIM14EN_Pos</a>)</td></tr>
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<tr class="separator:gaecb332ea40285657d968307a8cef8951"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca040bd66d4a54d4d9e9b261c8102799" id="r_gaca040bd66d4a54d4d9e9b261c8102799"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca040bd66d4a54d4d9e9b261c8102799">RCC_APB1ENR_TIM14EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaecb332ea40285657d968307a8cef8951">RCC_APB1ENR_TIM14EN_Msk</a></td></tr>
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<tr class="separator:gaca040bd66d4a54d4d9e9b261c8102799"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3fd18a8801d86093018dfe2ea3b2b4a" id="r_gaf3fd18a8801d86093018dfe2ea3b2b4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3fd18a8801d86093018dfe2ea3b2b4a">RCC_APB1ENR_WWDGEN_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga09ad274a2f953fdb7c7ce0e6d69e8798" id="r_ga09ad274a2f953fdb7c7ce0e6d69e8798"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09ad274a2f953fdb7c7ce0e6d69e8798">RCC_APB1ENR_WWDGEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3fd18a8801d86093018dfe2ea3b2b4a">RCC_APB1ENR_WWDGEN_Pos</a>)</td></tr>
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<tr class="separator:ga09ad274a2f953fdb7c7ce0e6d69e8798"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf712b922ee776a972d2efa3da0ea4733" id="r_gaf712b922ee776a972d2efa3da0ea4733"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf712b922ee776a972d2efa3da0ea4733">RCC_APB1ENR_WWDGEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga09ad274a2f953fdb7c7ce0e6d69e8798">RCC_APB1ENR_WWDGEN_Msk</a></td></tr>
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<tr class="separator:gaf712b922ee776a972d2efa3da0ea4733"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea7eb0710266a43edcd813440b159f8e" id="r_gaea7eb0710266a43edcd813440b159f8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea7eb0710266a43edcd813440b159f8e">RCC_APB1ENR_SPI2EN_Pos</a>   (14U)</td></tr>
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<tr class="memitem:ga5fd0ff191b4b6253b499258e4625cc65" id="r_ga5fd0ff191b4b6253b499258e4625cc65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fd0ff191b4b6253b499258e4625cc65">RCC_APB1ENR_SPI2EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea7eb0710266a43edcd813440b159f8e">RCC_APB1ENR_SPI2EN_Pos</a>)</td></tr>
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<tr class="separator:ga5fd0ff191b4b6253b499258e4625cc65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdce64692c44bf95efbf2fed054e59be" id="r_gafdce64692c44bf95efbf2fed054e59be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdce64692c44bf95efbf2fed054e59be">RCC_APB1ENR_SPI2EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fd0ff191b4b6253b499258e4625cc65">RCC_APB1ENR_SPI2EN_Msk</a></td></tr>
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<tr class="separator:gafdce64692c44bf95efbf2fed054e59be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59915518ddf7e60fc5da8072b3ce6dd9" id="r_ga59915518ddf7e60fc5da8072b3ce6dd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59915518ddf7e60fc5da8072b3ce6dd9">RCC_APB1ENR_SPI3EN_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga59915518ddf7e60fc5da8072b3ce6dd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3852cf58a863e5b0133d5bc84bcede3f" id="r_ga3852cf58a863e5b0133d5bc84bcede3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3852cf58a863e5b0133d5bc84bcede3f">RCC_APB1ENR_SPI3EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga59915518ddf7e60fc5da8072b3ce6dd9">RCC_APB1ENR_SPI3EN_Pos</a>)</td></tr>
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<tr class="separator:ga3852cf58a863e5b0133d5bc84bcede3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8757f8d1e1ff1447e08e5abea4615083" id="r_ga8757f8d1e1ff1447e08e5abea4615083"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8757f8d1e1ff1447e08e5abea4615083">RCC_APB1ENR_SPI3EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3852cf58a863e5b0133d5bc84bcede3f">RCC_APB1ENR_SPI3EN_Msk</a></td></tr>
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<tr class="separator:ga8757f8d1e1ff1447e08e5abea4615083"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a410d2ae7f9133227d2a35cde9188d6" id="r_ga9a410d2ae7f9133227d2a35cde9188d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a410d2ae7f9133227d2a35cde9188d6">RCC_APB1ENR_USART2EN_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga9a410d2ae7f9133227d2a35cde9188d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga510e179108a8914b0830b1ff30951caf" id="r_ga510e179108a8914b0830b1ff30951caf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga510e179108a8914b0830b1ff30951caf">RCC_APB1ENR_USART2EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a410d2ae7f9133227d2a35cde9188d6">RCC_APB1ENR_USART2EN_Pos</a>)</td></tr>
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<tr class="separator:ga510e179108a8914b0830b1ff30951caf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab840af4f735ec36419d61c7db3cfa00d" id="r_gab840af4f735ec36419d61c7db3cfa00d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab840af4f735ec36419d61c7db3cfa00d">RCC_APB1ENR_USART2EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga510e179108a8914b0830b1ff30951caf">RCC_APB1ENR_USART2EN_Msk</a></td></tr>
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<tr class="separator:gab840af4f735ec36419d61c7db3cfa00d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bfba28e5987744972af99c83dfd0a68" id="r_ga5bfba28e5987744972af99c83dfd0a68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bfba28e5987744972af99c83dfd0a68">RCC_APB1ENR_USART3EN_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga5bfba28e5987744972af99c83dfd0a68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac98f52fa1ae42a405334a2cc84f993b2" id="r_gac98f52fa1ae42a405334a2cc84f993b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac98f52fa1ae42a405334a2cc84f993b2">RCC_APB1ENR_USART3EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bfba28e5987744972af99c83dfd0a68">RCC_APB1ENR_USART3EN_Pos</a>)</td></tr>
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<tr class="separator:gac98f52fa1ae42a405334a2cc84f993b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8033e0312aea02ae7eb2d57da13e8298" id="r_ga8033e0312aea02ae7eb2d57da13e8298"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8033e0312aea02ae7eb2d57da13e8298">RCC_APB1ENR_USART3EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac98f52fa1ae42a405334a2cc84f993b2">RCC_APB1ENR_USART3EN_Msk</a></td></tr>
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<tr class="separator:ga8033e0312aea02ae7eb2d57da13e8298"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadad62b6567db40949d10c876718780f6" id="r_gadad62b6567db40949d10c876718780f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadad62b6567db40949d10c876718780f6">RCC_APB1ENR_UART4EN_Pos</a>   (19U)</td></tr>
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<tr class="separator:gadad62b6567db40949d10c876718780f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33f02158e2eaba91c9cbc6e499aa4471" id="r_ga33f02158e2eaba91c9cbc6e499aa4471"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33f02158e2eaba91c9cbc6e499aa4471">RCC_APB1ENR_UART4EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadad62b6567db40949d10c876718780f6">RCC_APB1ENR_UART4EN_Pos</a>)</td></tr>
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<tr class="separator:ga33f02158e2eaba91c9cbc6e499aa4471"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6b0fe571aa29ed30389f87bdbf37b46" id="r_gae6b0fe571aa29ed30389f87bdbf37b46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6b0fe571aa29ed30389f87bdbf37b46">RCC_APB1ENR_UART4EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga33f02158e2eaba91c9cbc6e499aa4471">RCC_APB1ENR_UART4EN_Msk</a></td></tr>
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<tr class="separator:gae6b0fe571aa29ed30389f87bdbf37b46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99f56067e63f26f0ecb64bdf36be19df" id="r_ga99f56067e63f26f0ecb64bdf36be19df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99f56067e63f26f0ecb64bdf36be19df">RCC_APB1ENR_UART5EN_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga99f56067e63f26f0ecb64bdf36be19df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab01815c1b0ced6d002d1b7590e9b8b15" id="r_gab01815c1b0ced6d002d1b7590e9b8b15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab01815c1b0ced6d002d1b7590e9b8b15">RCC_APB1ENR_UART5EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga99f56067e63f26f0ecb64bdf36be19df">RCC_APB1ENR_UART5EN_Pos</a>)</td></tr>
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<tr class="separator:gab01815c1b0ced6d002d1b7590e9b8b15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24a9eea153892405f53007f521efee2e" id="r_ga24a9eea153892405f53007f521efee2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24a9eea153892405f53007f521efee2e">RCC_APB1ENR_UART5EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab01815c1b0ced6d002d1b7590e9b8b15">RCC_APB1ENR_UART5EN_Msk</a></td></tr>
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<tr class="separator:ga24a9eea153892405f53007f521efee2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f1cab341f8320372dfd95bce3d2d918" id="r_ga0f1cab341f8320372dfd95bce3d2d918"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f1cab341f8320372dfd95bce3d2d918">RCC_APB1ENR_I2C1EN_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga0f1cab341f8320372dfd95bce3d2d918"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b2a4e92cb0eba09a147ee9770195eee" id="r_ga2b2a4e92cb0eba09a147ee9770195eee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b2a4e92cb0eba09a147ee9770195eee">RCC_APB1ENR_I2C1EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f1cab341f8320372dfd95bce3d2d918">RCC_APB1ENR_I2C1EN_Pos</a>)</td></tr>
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<tr class="separator:ga2b2a4e92cb0eba09a147ee9770195eee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ca3afe0c517702b2d1366b692c8db0e" id="r_ga5ca3afe0c517702b2d1366b692c8db0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ca3afe0c517702b2d1366b692c8db0e">RCC_APB1ENR_I2C1EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b2a4e92cb0eba09a147ee9770195eee">RCC_APB1ENR_I2C1EN_Msk</a></td></tr>
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<tr class="separator:ga5ca3afe0c517702b2d1366b692c8db0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94ad0c869b4e644dacba6b170797fcf6" id="r_ga94ad0c869b4e644dacba6b170797fcf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94ad0c869b4e644dacba6b170797fcf6">RCC_APB1ENR_I2C2EN_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga94ad0c869b4e644dacba6b170797fcf6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb344f4fbe0d1286860e8c47f73339ce" id="r_gadb344f4fbe0d1286860e8c47f73339ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb344f4fbe0d1286860e8c47f73339ce">RCC_APB1ENR_I2C2EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga94ad0c869b4e644dacba6b170797fcf6">RCC_APB1ENR_I2C2EN_Pos</a>)</td></tr>
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<tr class="separator:gadb344f4fbe0d1286860e8c47f73339ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd7d1c3c7dbe20aea87a694ae15840f6" id="r_gafd7d1c3c7dbe20aea87a694ae15840f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd7d1c3c7dbe20aea87a694ae15840f6">RCC_APB1ENR_I2C2EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadb344f4fbe0d1286860e8c47f73339ce">RCC_APB1ENR_I2C2EN_Msk</a></td></tr>
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<tr class="separator:gafd7d1c3c7dbe20aea87a694ae15840f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga007431fc8e6cbe66fff71273e9245ad3" id="r_ga007431fc8e6cbe66fff71273e9245ad3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga007431fc8e6cbe66fff71273e9245ad3">RCC_APB1ENR_I2C3EN_Pos</a>   (23U)</td></tr>
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<tr class="memitem:ga3287ea960eceb4499698cfc8e4ffbf36" id="r_ga3287ea960eceb4499698cfc8e4ffbf36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3287ea960eceb4499698cfc8e4ffbf36">RCC_APB1ENR_I2C3EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga007431fc8e6cbe66fff71273e9245ad3">RCC_APB1ENR_I2C3EN_Pos</a>)</td></tr>
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<tr class="separator:ga3287ea960eceb4499698cfc8e4ffbf36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96621806b8fb96891efa9364e370f3f7" id="r_ga96621806b8fb96891efa9364e370f3f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96621806b8fb96891efa9364e370f3f7">RCC_APB1ENR_I2C3EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3287ea960eceb4499698cfc8e4ffbf36">RCC_APB1ENR_I2C3EN_Msk</a></td></tr>
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<tr class="separator:ga96621806b8fb96891efa9364e370f3f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1a9a8c0f5081081046044070e17d93b" id="r_gad1a9a8c0f5081081046044070e17d93b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1a9a8c0f5081081046044070e17d93b">RCC_APB1ENR_CAN1EN_Pos</a>   (25U)</td></tr>
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<tr class="separator:gad1a9a8c0f5081081046044070e17d93b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8adf13f0648b09c215dfd69d3ef933b5" id="r_ga8adf13f0648b09c215dfd69d3ef933b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8adf13f0648b09c215dfd69d3ef933b5">RCC_APB1ENR_CAN1EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad1a9a8c0f5081081046044070e17d93b">RCC_APB1ENR_CAN1EN_Pos</a>)</td></tr>
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<tr class="separator:ga8adf13f0648b09c215dfd69d3ef933b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66b5172158cf0170d29091064ea63a29" id="r_ga66b5172158cf0170d29091064ea63a29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66b5172158cf0170d29091064ea63a29">RCC_APB1ENR_CAN1EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8adf13f0648b09c215dfd69d3ef933b5">RCC_APB1ENR_CAN1EN_Msk</a></td></tr>
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<tr class="separator:ga66b5172158cf0170d29091064ea63a29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace880a61cc0e55b67c8d4bf47374cf49" id="r_gace880a61cc0e55b67c8d4bf47374cf49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace880a61cc0e55b67c8d4bf47374cf49">RCC_APB1ENR_CAN2EN_Pos</a>   (26U)</td></tr>
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<tr class="separator:gace880a61cc0e55b67c8d4bf47374cf49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bffa56c0080897dc6cbe28ad888f22b" id="r_ga4bffa56c0080897dc6cbe28ad888f22b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bffa56c0080897dc6cbe28ad888f22b">RCC_APB1ENR_CAN2EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gace880a61cc0e55b67c8d4bf47374cf49">RCC_APB1ENR_CAN2EN_Pos</a>)</td></tr>
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<tr class="separator:ga4bffa56c0080897dc6cbe28ad888f22b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae64f792b7a3401cff4d95e31d3867422" id="r_gae64f792b7a3401cff4d95e31d3867422"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae64f792b7a3401cff4d95e31d3867422">RCC_APB1ENR_CAN2EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bffa56c0080897dc6cbe28ad888f22b">RCC_APB1ENR_CAN2EN_Msk</a></td></tr>
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<tr class="separator:gae64f792b7a3401cff4d95e31d3867422"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d869630ea19b70ec5c740cc6b37f49c" id="r_ga9d869630ea19b70ec5c740cc6b37f49c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d869630ea19b70ec5c740cc6b37f49c">RCC_APB1ENR_PWREN_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga9d869630ea19b70ec5c740cc6b37f49c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ba08580eae539419497cdd62c530bad" id="r_ga4ba08580eae539419497cdd62c530bad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ba08580eae539419497cdd62c530bad">RCC_APB1ENR_PWREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d869630ea19b70ec5c740cc6b37f49c">RCC_APB1ENR_PWREN_Pos</a>)</td></tr>
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<tr class="separator:ga4ba08580eae539419497cdd62c530bad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c19997ccd28464b80a7c3325da0ca60" id="r_ga5c19997ccd28464b80a7c3325da0ca60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c19997ccd28464b80a7c3325da0ca60">RCC_APB1ENR_PWREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ba08580eae539419497cdd62c530bad">RCC_APB1ENR_PWREN_Msk</a></td></tr>
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<tr class="separator:ga5c19997ccd28464b80a7c3325da0ca60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7982505dca41bc51c29dcdcc03eb789" id="r_gac7982505dca41bc51c29dcdcc03eb789"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7982505dca41bc51c29dcdcc03eb789">RCC_APB1ENR_DACEN_Pos</a>   (29U)</td></tr>
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<tr class="separator:gac7982505dca41bc51c29dcdcc03eb789"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd51394bb1f7c10cef36c5dd2e19766d" id="r_gacd51394bb1f7c10cef36c5dd2e19766d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd51394bb1f7c10cef36c5dd2e19766d">RCC_APB1ENR_DACEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac7982505dca41bc51c29dcdcc03eb789">RCC_APB1ENR_DACEN_Pos</a>)</td></tr>
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<tr class="separator:gacd51394bb1f7c10cef36c5dd2e19766d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga087968e2786321fb8645c46b22eea132" id="r_ga087968e2786321fb8645c46b22eea132"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga087968e2786321fb8645c46b22eea132">RCC_APB1ENR_DACEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacd51394bb1f7c10cef36c5dd2e19766d">RCC_APB1ENR_DACEN_Msk</a></td></tr>
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<tr class="separator:ga087968e2786321fb8645c46b22eea132"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b330cc86756aa87e3f7466e82eaf64b" id="r_ga5b330cc86756aa87e3f7466e82eaf64b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b330cc86756aa87e3f7466e82eaf64b">RCC_APB2ENR_TIM1EN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5b330cc86756aa87e3f7466e82eaf64b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1216bf89d48094b55a4abcc859b037fa" id="r_ga1216bf89d48094b55a4abcc859b037fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1216bf89d48094b55a4abcc859b037fa">RCC_APB2ENR_TIM1EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b330cc86756aa87e3f7466e82eaf64b">RCC_APB2ENR_TIM1EN_Pos</a>)</td></tr>
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<tr class="separator:ga1216bf89d48094b55a4abcc859b037fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25852ad4ebc09edc724814de967816bc" id="r_ga25852ad4ebc09edc724814de967816bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25852ad4ebc09edc724814de967816bc">RCC_APB2ENR_TIM1EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1216bf89d48094b55a4abcc859b037fa">RCC_APB2ENR_TIM1EN_Msk</a></td></tr>
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<tr class="separator:ga25852ad4ebc09edc724814de967816bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadddecaa60d969169a1ba2944371b2414" id="r_gadddecaa60d969169a1ba2944371b2414"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadddecaa60d969169a1ba2944371b2414">RCC_APB2ENR_TIM8EN_Pos</a>   (1U)</td></tr>
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<tr class="separator:gadddecaa60d969169a1ba2944371b2414"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace08df04fccb33baccbda0fa4697dc04" id="r_gace08df04fccb33baccbda0fa4697dc04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace08df04fccb33baccbda0fa4697dc04">RCC_APB2ENR_TIM8EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadddecaa60d969169a1ba2944371b2414">RCC_APB2ENR_TIM8EN_Pos</a>)</td></tr>
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<tr class="separator:gace08df04fccb33baccbda0fa4697dc04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3669393b3538bc4543184d4bccd0b292" id="r_ga3669393b3538bc4543184d4bccd0b292"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3669393b3538bc4543184d4bccd0b292">RCC_APB2ENR_TIM8EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gace08df04fccb33baccbda0fa4697dc04">RCC_APB2ENR_TIM8EN_Msk</a></td></tr>
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<tr class="separator:ga3669393b3538bc4543184d4bccd0b292"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga603eb3c42e7ee50f31fb6fade0b4e43b" id="r_ga603eb3c42e7ee50f31fb6fade0b4e43b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga603eb3c42e7ee50f31fb6fade0b4e43b">RCC_APB2ENR_USART1EN_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga603eb3c42e7ee50f31fb6fade0b4e43b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a185f9bf1e72599fc7d2e02716ee40b" id="r_ga6a185f9bf1e72599fc7d2e02716ee40b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a185f9bf1e72599fc7d2e02716ee40b">RCC_APB2ENR_USART1EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga603eb3c42e7ee50f31fb6fade0b4e43b">RCC_APB2ENR_USART1EN_Pos</a>)</td></tr>
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<tr class="separator:ga6a185f9bf1e72599fc7d2e02716ee40b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4666bb90842e8134b32e6a34a0f165f3" id="r_ga4666bb90842e8134b32e6a34a0f165f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4666bb90842e8134b32e6a34a0f165f3">RCC_APB2ENR_USART1EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a185f9bf1e72599fc7d2e02716ee40b">RCC_APB2ENR_USART1EN_Msk</a></td></tr>
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<tr class="separator:ga4666bb90842e8134b32e6a34a0f165f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e600f524eab6bd8a909babd0dde5466" id="r_ga7e600f524eab6bd8a909babd0dde5466"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e600f524eab6bd8a909babd0dde5466">RCC_APB2ENR_USART6EN_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga7e600f524eab6bd8a909babd0dde5466"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d196a71620aa24b125657dfdc9c85bf" id="r_ga3d196a71620aa24b125657dfdc9c85bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d196a71620aa24b125657dfdc9c85bf">RCC_APB2ENR_USART6EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e600f524eab6bd8a909babd0dde5466">RCC_APB2ENR_USART6EN_Pos</a>)</td></tr>
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<tr class="separator:ga3d196a71620aa24b125657dfdc9c85bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0569d91f3b18ae130b7a09e0100c4459" id="r_ga0569d91f3b18ae130b7a09e0100c4459"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0569d91f3b18ae130b7a09e0100c4459">RCC_APB2ENR_USART6EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d196a71620aa24b125657dfdc9c85bf">RCC_APB2ENR_USART6EN_Msk</a></td></tr>
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<tr class="separator:ga0569d91f3b18ae130b7a09e0100c4459"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabad54999d05c830541de19027fb92c97" id="r_gabad54999d05c830541de19027fb92c97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabad54999d05c830541de19027fb92c97">RCC_APB2ENR_ADC1EN_Pos</a>   (8U)</td></tr>
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<tr class="separator:gabad54999d05c830541de19027fb92c97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11c50e2378b7a8d15c9a2eb89f561efe" id="r_ga11c50e2378b7a8d15c9a2eb89f561efe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11c50e2378b7a8d15c9a2eb89f561efe">RCC_APB2ENR_ADC1EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabad54999d05c830541de19027fb92c97">RCC_APB2ENR_ADC1EN_Pos</a>)</td></tr>
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<tr class="separator:ga11c50e2378b7a8d15c9a2eb89f561efe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57b9f50cb96a2e4ceba37728b4a32a42" id="r_ga57b9f50cb96a2e4ceba37728b4a32a42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57b9f50cb96a2e4ceba37728b4a32a42">RCC_APB2ENR_ADC1EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga11c50e2378b7a8d15c9a2eb89f561efe">RCC_APB2ENR_ADC1EN_Msk</a></td></tr>
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<tr class="separator:ga57b9f50cb96a2e4ceba37728b4a32a42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa0ab86ac5dc8b87216901e91c950cc0" id="r_gaaa0ab86ac5dc8b87216901e91c950cc0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa0ab86ac5dc8b87216901e91c950cc0">RCC_APB2ENR_ADC2EN_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaaa0ab86ac5dc8b87216901e91c950cc0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55e486391860d774ac8613c6848b62de" id="r_ga55e486391860d774ac8613c6848b62de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55e486391860d774ac8613c6848b62de">RCC_APB2ENR_ADC2EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa0ab86ac5dc8b87216901e91c950cc0">RCC_APB2ENR_ADC2EN_Pos</a>)</td></tr>
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<tr class="separator:ga55e486391860d774ac8613c6848b62de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11a9732e1cef24f107e815caecdbb445" id="r_ga11a9732e1cef24f107e815caecdbb445"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11a9732e1cef24f107e815caecdbb445">RCC_APB2ENR_ADC2EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga55e486391860d774ac8613c6848b62de">RCC_APB2ENR_ADC2EN_Msk</a></td></tr>
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<tr class="separator:ga11a9732e1cef24f107e815caecdbb445"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a7fff458c028a5b1d43cd3a5e299121" id="r_ga5a7fff458c028a5b1d43cd3a5e299121"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a7fff458c028a5b1d43cd3a5e299121">RCC_APB2ENR_ADC3EN_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga5a7fff458c028a5b1d43cd3a5e299121"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3126f80244d91d2d13c1a40e5f64df0" id="r_gaa3126f80244d91d2d13c1a40e5f64df0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3126f80244d91d2d13c1a40e5f64df0">RCC_APB2ENR_ADC3EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a7fff458c028a5b1d43cd3a5e299121">RCC_APB2ENR_ADC3EN_Pos</a>)</td></tr>
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<tr class="separator:gaa3126f80244d91d2d13c1a40e5f64df0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5df23f931ddad97274ce7e2050b90a5a" id="r_ga5df23f931ddad97274ce7e2050b90a5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5df23f931ddad97274ce7e2050b90a5a">RCC_APB2ENR_ADC3EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3126f80244d91d2d13c1a40e5f64df0">RCC_APB2ENR_ADC3EN_Msk</a></td></tr>
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<tr class="separator:ga5df23f931ddad97274ce7e2050b90a5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fd687b860d719def07032d6cfd1cc3a" id="r_ga4fd687b860d719def07032d6cfd1cc3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fd687b860d719def07032d6cfd1cc3a">RCC_APB2ENR_SDIOEN_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga4fd687b860d719def07032d6cfd1cc3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06f570456b6725105e600c0700cdc0bd" id="r_ga06f570456b6725105e600c0700cdc0bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06f570456b6725105e600c0700cdc0bd">RCC_APB2ENR_SDIOEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4fd687b860d719def07032d6cfd1cc3a">RCC_APB2ENR_SDIOEN_Pos</a>)</td></tr>
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<tr class="separator:ga06f570456b6725105e600c0700cdc0bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf714bbe5b378910693dbfe824b70de8" id="r_gabf714bbe5b378910693dbfe824b70de8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf714bbe5b378910693dbfe824b70de8">RCC_APB2ENR_SDIOEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06f570456b6725105e600c0700cdc0bd">RCC_APB2ENR_SDIOEN_Msk</a></td></tr>
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<tr class="separator:gabf714bbe5b378910693dbfe824b70de8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77b08db44a4ccc823a4ecaf89c3b4309" id="r_ga77b08db44a4ccc823a4ecaf89c3b4309"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77b08db44a4ccc823a4ecaf89c3b4309">RCC_APB2ENR_SPI1EN_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga77b08db44a4ccc823a4ecaf89c3b4309"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefba87e52830d0d82cd94eb11089aa1b" id="r_gaefba87e52830d0d82cd94eb11089aa1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefba87e52830d0d82cd94eb11089aa1b">RCC_APB2ENR_SPI1EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga77b08db44a4ccc823a4ecaf89c3b4309">RCC_APB2ENR_SPI1EN_Pos</a>)</td></tr>
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<tr class="separator:gaefba87e52830d0d82cd94eb11089aa1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae08a3510371b9234eb96369c91d3552f" id="r_gae08a3510371b9234eb96369c91d3552f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae08a3510371b9234eb96369c91d3552f">RCC_APB2ENR_SPI1EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaefba87e52830d0d82cd94eb11089aa1b">RCC_APB2ENR_SPI1EN_Msk</a></td></tr>
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<tr class="separator:gae08a3510371b9234eb96369c91d3552f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e61727e044998a6ebee3dcf48614554" id="r_ga2e61727e044998a6ebee3dcf48614554"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e61727e044998a6ebee3dcf48614554">RCC_APB2ENR_SYSCFGEN_Pos</a>   (14U)</td></tr>
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<tr class="memitem:ga781c030e54df45c8f190c9f03d20f4a5" id="r_ga781c030e54df45c8f190c9f03d20f4a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga781c030e54df45c8f190c9f03d20f4a5">RCC_APB2ENR_SYSCFGEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e61727e044998a6ebee3dcf48614554">RCC_APB2ENR_SYSCFGEN_Pos</a>)</td></tr>
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<tr class="separator:ga781c030e54df45c8f190c9f03d20f4a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a9d56a8aa1fa0f519ecbdf0d19dd4da" id="r_ga7a9d56a8aa1fa0f519ecbdf0d19dd4da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a9d56a8aa1fa0f519ecbdf0d19dd4da">RCC_APB2ENR_SYSCFGEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga781c030e54df45c8f190c9f03d20f4a5">RCC_APB2ENR_SYSCFGEN_Msk</a></td></tr>
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<tr class="separator:ga7a9d56a8aa1fa0f519ecbdf0d19dd4da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1023b40804156535a7fd0b0fd17da26" id="r_gac1023b40804156535a7fd0b0fd17da26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1023b40804156535a7fd0b0fd17da26">RCC_APB2ENR_TIM9EN_Pos</a>   (16U)</td></tr>
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<tr class="separator:gac1023b40804156535a7fd0b0fd17da26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7973b960b45268bd0160c1f5f21acf2" id="r_gad7973b960b45268bd0160c1f5f21acf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7973b960b45268bd0160c1f5f21acf2">RCC_APB2ENR_TIM9EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac1023b40804156535a7fd0b0fd17da26">RCC_APB2ENR_TIM9EN_Pos</a>)</td></tr>
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<tr class="separator:gad7973b960b45268bd0160c1f5f21acf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga987ebd8255dc8f9c09127e1d608d1065" id="r_ga987ebd8255dc8f9c09127e1d608d1065"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga987ebd8255dc8f9c09127e1d608d1065">RCC_APB2ENR_TIM9EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad7973b960b45268bd0160c1f5f21acf2">RCC_APB2ENR_TIM9EN_Msk</a></td></tr>
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<tr class="separator:ga987ebd8255dc8f9c09127e1d608d1065"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga595f4318939fac8cef4cfb6a886a0811" id="r_ga595f4318939fac8cef4cfb6a886a0811"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga595f4318939fac8cef4cfb6a886a0811">RCC_APB2ENR_TIM10EN_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga595f4318939fac8cef4cfb6a886a0811"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga539dc20498c8b8abdf208bd2b98a46c6" id="r_ga539dc20498c8b8abdf208bd2b98a46c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga539dc20498c8b8abdf208bd2b98a46c6">RCC_APB2ENR_TIM10EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga595f4318939fac8cef4cfb6a886a0811">RCC_APB2ENR_TIM10EN_Pos</a>)</td></tr>
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<tr class="separator:ga539dc20498c8b8abdf208bd2b98a46c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa98e28e157787e24b93af95273ab3055" id="r_gaa98e28e157787e24b93af95273ab3055"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa98e28e157787e24b93af95273ab3055">RCC_APB2ENR_TIM10EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga539dc20498c8b8abdf208bd2b98a46c6">RCC_APB2ENR_TIM10EN_Msk</a></td></tr>
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<tr class="separator:gaa98e28e157787e24b93af95273ab3055"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4175c4afc573a7bdd6fa19faaaf9f735" id="r_ga4175c4afc573a7bdd6fa19faaaf9f735"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4175c4afc573a7bdd6fa19faaaf9f735">RCC_APB2ENR_TIM11EN_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga4175c4afc573a7bdd6fa19faaaf9f735"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5273bcf1abc8db0bf1617c747bab5ec" id="r_gaa5273bcf1abc8db0bf1617c747bab5ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5273bcf1abc8db0bf1617c747bab5ec">RCC_APB2ENR_TIM11EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4175c4afc573a7bdd6fa19faaaf9f735">RCC_APB2ENR_TIM11EN_Pos</a>)</td></tr>
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<tr class="separator:gaa5273bcf1abc8db0bf1617c747bab5ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1d2aeebc8ccf4e2ee18f4d924a35188" id="r_gab1d2aeebc8ccf4e2ee18f4d924a35188"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1d2aeebc8ccf4e2ee18f4d924a35188">RCC_APB2ENR_TIM11EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5273bcf1abc8db0bf1617c747bab5ec">RCC_APB2ENR_TIM11EN_Msk</a></td></tr>
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<tr class="separator:gab1d2aeebc8ccf4e2ee18f4d924a35188"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacded6b0f52a7b9ef3bde81ce8d4cd657" id="r_gacded6b0f52a7b9ef3bde81ce8d4cd657"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacded6b0f52a7b9ef3bde81ce8d4cd657">RCC_AHB1LPENR_GPIOALPEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:gacded6b0f52a7b9ef3bde81ce8d4cd657"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab01076ddb6708e4c0ff9d6c4f22fa809" id="r_gab01076ddb6708e4c0ff9d6c4f22fa809"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab01076ddb6708e4c0ff9d6c4f22fa809">RCC_AHB1LPENR_GPIOALPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacded6b0f52a7b9ef3bde81ce8d4cd657">RCC_AHB1LPENR_GPIOALPEN_Pos</a>)</td></tr>
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<tr class="separator:gab01076ddb6708e4c0ff9d6c4f22fa809"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1076b0644c026ab480efdb6aa8c74fb" id="r_gaf1076b0644c026ab480efdb6aa8c74fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1076b0644c026ab480efdb6aa8c74fb">RCC_AHB1LPENR_GPIOALPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab01076ddb6708e4c0ff9d6c4f22fa809">RCC_AHB1LPENR_GPIOALPEN_Msk</a></td></tr>
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<tr class="memitem:ga1408e65a8ca8d481d713a171adb4a8b9" id="r_ga1408e65a8ca8d481d713a171adb4a8b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1408e65a8ca8d481d713a171adb4a8b9">RCC_AHB1LPENR_GPIOBLPEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga1408e65a8ca8d481d713a171adb4a8b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad765dcf02bb5f215ff3a77a63c16f746" id="r_gad765dcf02bb5f215ff3a77a63c16f746"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad765dcf02bb5f215ff3a77a63c16f746">RCC_AHB1LPENR_GPIOBLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1408e65a8ca8d481d713a171adb4a8b9">RCC_AHB1LPENR_GPIOBLPEN_Pos</a>)</td></tr>
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<tr class="separator:gad765dcf02bb5f215ff3a77a63c16f746"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55f6ff35a37c4b9106c9e8aa18ab4545" id="r_ga55f6ff35a37c4b9106c9e8aa18ab4545"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55f6ff35a37c4b9106c9e8aa18ab4545">RCC_AHB1LPENR_GPIOBLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad765dcf02bb5f215ff3a77a63c16f746">RCC_AHB1LPENR_GPIOBLPEN_Msk</a></td></tr>
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<tr class="separator:ga55f6ff35a37c4b9106c9e8aa18ab4545"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30cd4b8a99bb64ebbcac917ea64ccacc" id="r_ga30cd4b8a99bb64ebbcac917ea64ccacc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30cd4b8a99bb64ebbcac917ea64ccacc">RCC_AHB1LPENR_GPIOCLPEN_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga30cd4b8a99bb64ebbcac917ea64ccacc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26ff370d6adef4823a87bd98c5767a42" id="r_ga26ff370d6adef4823a87bd98c5767a42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26ff370d6adef4823a87bd98c5767a42">RCC_AHB1LPENR_GPIOCLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30cd4b8a99bb64ebbcac917ea64ccacc">RCC_AHB1LPENR_GPIOCLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga26ff370d6adef4823a87bd98c5767a42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac86ad592684edae0ba2cafd22a4f04d1" id="r_gac86ad592684edae0ba2cafd22a4f04d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac86ad592684edae0ba2cafd22a4f04d1">RCC_AHB1LPENR_GPIOCLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga26ff370d6adef4823a87bd98c5767a42">RCC_AHB1LPENR_GPIOCLPEN_Msk</a></td></tr>
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<tr class="separator:gac86ad592684edae0ba2cafd22a4f04d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaceb2e30709973666017a04023286fb71" id="r_gaceb2e30709973666017a04023286fb71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaceb2e30709973666017a04023286fb71">RCC_AHB1LPENR_GPIODLPEN_Pos</a>   (3U)</td></tr>
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<tr class="memitem:ga4b81052c9334056e60b2b47e12d8ccef" id="r_ga4b81052c9334056e60b2b47e12d8ccef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b81052c9334056e60b2b47e12d8ccef">RCC_AHB1LPENR_GPIODLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaceb2e30709973666017a04023286fb71">RCC_AHB1LPENR_GPIODLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga4b81052c9334056e60b2b47e12d8ccef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89002894839d323b05c4b3f674b54470" id="r_ga89002894839d323b05c4b3f674b54470"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89002894839d323b05c4b3f674b54470">RCC_AHB1LPENR_GPIODLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b81052c9334056e60b2b47e12d8ccef">RCC_AHB1LPENR_GPIODLPEN_Msk</a></td></tr>
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<tr class="separator:ga89002894839d323b05c4b3f674b54470"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76748b3f35e4bc4481110d4be1ebdef9" id="r_ga76748b3f35e4bc4481110d4be1ebdef9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76748b3f35e4bc4481110d4be1ebdef9">RCC_AHB1LPENR_GPIOELPEN_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga379b06aa2db224e0e6e2812e33e5bc88" id="r_ga379b06aa2db224e0e6e2812e33e5bc88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga379b06aa2db224e0e6e2812e33e5bc88">RCC_AHB1LPENR_GPIOELPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga76748b3f35e4bc4481110d4be1ebdef9">RCC_AHB1LPENR_GPIOELPEN_Pos</a>)</td></tr>
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<tr class="separator:ga379b06aa2db224e0e6e2812e33e5bc88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2980a6e02550369d05e121ff6f16505c" id="r_ga2980a6e02550369d05e121ff6f16505c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2980a6e02550369d05e121ff6f16505c">RCC_AHB1LPENR_GPIOELPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga379b06aa2db224e0e6e2812e33e5bc88">RCC_AHB1LPENR_GPIOELPEN_Msk</a></td></tr>
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<tr class="separator:ga2980a6e02550369d05e121ff6f16505c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bdc53d83d3aec2d5c5fb2ae6a97b268" id="r_ga0bdc53d83d3aec2d5c5fb2ae6a97b268"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bdc53d83d3aec2d5c5fb2ae6a97b268">RCC_AHB1LPENR_GPIOFLPEN_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga0bdc53d83d3aec2d5c5fb2ae6a97b268"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1d321cff7127cb7bee72a680b40bcaf" id="r_gad1d321cff7127cb7bee72a680b40bcaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1d321cff7127cb7bee72a680b40bcaf">RCC_AHB1LPENR_GPIOFLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bdc53d83d3aec2d5c5fb2ae6a97b268">RCC_AHB1LPENR_GPIOFLPEN_Pos</a>)</td></tr>
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<tr class="separator:gad1d321cff7127cb7bee72a680b40bcaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7a50c0506b1014d89224933c6c42e6f" id="r_gaa7a50c0506b1014d89224933c6c42e6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7a50c0506b1014d89224933c6c42e6f">RCC_AHB1LPENR_GPIOFLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad1d321cff7127cb7bee72a680b40bcaf">RCC_AHB1LPENR_GPIOFLPEN_Msk</a></td></tr>
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<tr class="separator:gaa7a50c0506b1014d89224933c6c42e6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2050b38f2df4a69119c402d384e5b862" id="r_ga2050b38f2df4a69119c402d384e5b862"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2050b38f2df4a69119c402d384e5b862">RCC_AHB1LPENR_GPIOGLPEN_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga2050b38f2df4a69119c402d384e5b862"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8cbc273b51b62d59dbe58f68a330231" id="r_gab8cbc273b51b62d59dbe58f68a330231"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8cbc273b51b62d59dbe58f68a330231">RCC_AHB1LPENR_GPIOGLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2050b38f2df4a69119c402d384e5b862">RCC_AHB1LPENR_GPIOGLPEN_Pos</a>)</td></tr>
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<tr class="separator:gab8cbc273b51b62d59dbe58f68a330231"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1dc004ecb0a2950100a062cda47586f" id="r_gab1dc004ecb0a2950100a062cda47586f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1dc004ecb0a2950100a062cda47586f">RCC_AHB1LPENR_GPIOGLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab8cbc273b51b62d59dbe58f68a330231">RCC_AHB1LPENR_GPIOGLPEN_Msk</a></td></tr>
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<tr class="separator:gab1dc004ecb0a2950100a062cda47586f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64e54771be85afdd10ad93c3acdef080" id="r_ga64e54771be85afdd10ad93c3acdef080"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64e54771be85afdd10ad93c3acdef080">RCC_AHB1LPENR_GPIOHLPEN_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga64e54771be85afdd10ad93c3acdef080"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5420182a12449790d9316927e05bab4b" id="r_ga5420182a12449790d9316927e05bab4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5420182a12449790d9316927e05bab4b">RCC_AHB1LPENR_GPIOHLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga64e54771be85afdd10ad93c3acdef080">RCC_AHB1LPENR_GPIOHLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga5420182a12449790d9316927e05bab4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga197be77b89e9eae127a536bd2601ded9" id="r_ga197be77b89e9eae127a536bd2601ded9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga197be77b89e9eae127a536bd2601ded9">RCC_AHB1LPENR_GPIOHLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5420182a12449790d9316927e05bab4b">RCC_AHB1LPENR_GPIOHLPEN_Msk</a></td></tr>
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<tr class="separator:ga197be77b89e9eae127a536bd2601ded9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6334fbcfede5da166dab8b2e15d69d9" id="r_gaa6334fbcfede5da166dab8b2e15d69d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6334fbcfede5da166dab8b2e15d69d9">RCC_AHB1LPENR_GPIOILPEN_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaa6334fbcfede5da166dab8b2e15d69d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga285f894641272c773dac56c0eb5d14cc" id="r_ga285f894641272c773dac56c0eb5d14cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga285f894641272c773dac56c0eb5d14cc">RCC_AHB1LPENR_GPIOILPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6334fbcfede5da166dab8b2e15d69d9">RCC_AHB1LPENR_GPIOILPEN_Pos</a>)</td></tr>
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<tr class="separator:ga285f894641272c773dac56c0eb5d14cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70d927cfb1d110133bd64989b216a375" id="r_ga70d927cfb1d110133bd64989b216a375"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70d927cfb1d110133bd64989b216a375">RCC_AHB1LPENR_GPIOILPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga285f894641272c773dac56c0eb5d14cc">RCC_AHB1LPENR_GPIOILPEN_Msk</a></td></tr>
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<tr class="separator:ga70d927cfb1d110133bd64989b216a375"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2fb1b796b4ad84e3dd60b14b958d6f98" id="r_ga2fb1b796b4ad84e3dd60b14b958d6f98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fb1b796b4ad84e3dd60b14b958d6f98">RCC_AHB1LPENR_CRCLPEN_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga2fb1b796b4ad84e3dd60b14b958d6f98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87b177e8246a207541fbce277d4f48ab" id="r_ga87b177e8246a207541fbce277d4f48ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87b177e8246a207541fbce277d4f48ab">RCC_AHB1LPENR_CRCLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2fb1b796b4ad84e3dd60b14b958d6f98">RCC_AHB1LPENR_CRCLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga87b177e8246a207541fbce277d4f48ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7333e14b5ccf6d608232ea52a10f7052" id="r_ga7333e14b5ccf6d608232ea52a10f7052"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7333e14b5ccf6d608232ea52a10f7052">RCC_AHB1LPENR_CRCLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga87b177e8246a207541fbce277d4f48ab">RCC_AHB1LPENR_CRCLPEN_Msk</a></td></tr>
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<tr class="separator:ga7333e14b5ccf6d608232ea52a10f7052"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07b410fb7c23f0ee3f8d100c5a409078" id="r_ga07b410fb7c23f0ee3f8d100c5a409078"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07b410fb7c23f0ee3f8d100c5a409078">RCC_AHB1LPENR_FLITFLPEN_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga07b410fb7c23f0ee3f8d100c5a409078"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaafb7485a44d40e2da16270de53aa8171" id="r_gaafb7485a44d40e2da16270de53aa8171"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafb7485a44d40e2da16270de53aa8171">RCC_AHB1LPENR_FLITFLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07b410fb7c23f0ee3f8d100c5a409078">RCC_AHB1LPENR_FLITFLPEN_Pos</a>)</td></tr>
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<tr class="separator:gaafb7485a44d40e2da16270de53aa8171"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga378f6e2ad9fef59f28db829d2074e796" id="r_ga378f6e2ad9fef59f28db829d2074e796"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga378f6e2ad9fef59f28db829d2074e796">RCC_AHB1LPENR_FLITFLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaafb7485a44d40e2da16270de53aa8171">RCC_AHB1LPENR_FLITFLPEN_Msk</a></td></tr>
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<tr class="separator:ga378f6e2ad9fef59f28db829d2074e796"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1719fa2c00b2554e679b7bd52e648b3" id="r_gab1719fa2c00b2554e679b7bd52e648b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1719fa2c00b2554e679b7bd52e648b3">RCC_AHB1LPENR_SRAM1LPEN_Pos</a>   (16U)</td></tr>
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<tr class="separator:gab1719fa2c00b2554e679b7bd52e648b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3165c825e9a88a606803cd08a85d9dd9" id="r_ga3165c825e9a88a606803cd08a85d9dd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3165c825e9a88a606803cd08a85d9dd9">RCC_AHB1LPENR_SRAM1LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab1719fa2c00b2554e679b7bd52e648b3">RCC_AHB1LPENR_SRAM1LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga3165c825e9a88a606803cd08a85d9dd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4cd1fbd9113809a6a3c904617647219c" id="r_ga4cd1fbd9113809a6a3c904617647219c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4cd1fbd9113809a6a3c904617647219c">RCC_AHB1LPENR_SRAM1LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3165c825e9a88a606803cd08a85d9dd9">RCC_AHB1LPENR_SRAM1LPEN_Msk</a></td></tr>
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<tr class="separator:ga4cd1fbd9113809a6a3c904617647219c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14b6f62bdc1eeab17de120a32d3ef25e" id="r_ga14b6f62bdc1eeab17de120a32d3ef25e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14b6f62bdc1eeab17de120a32d3ef25e">RCC_AHB1LPENR_SRAM2LPEN_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga14b6f62bdc1eeab17de120a32d3ef25e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54ed7528aecee29c5498e649bb9851eb" id="r_ga54ed7528aecee29c5498e649bb9851eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54ed7528aecee29c5498e649bb9851eb">RCC_AHB1LPENR_SRAM2LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14b6f62bdc1eeab17de120a32d3ef25e">RCC_AHB1LPENR_SRAM2LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga54ed7528aecee29c5498e649bb9851eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf7a4c822fa3073035a04487c4cca320" id="r_gaaf7a4c822fa3073035a04487c4cca320"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf7a4c822fa3073035a04487c4cca320">RCC_AHB1LPENR_SRAM2LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga54ed7528aecee29c5498e649bb9851eb">RCC_AHB1LPENR_SRAM2LPEN_Msk</a></td></tr>
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<tr class="separator:gaaf7a4c822fa3073035a04487c4cca320"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3100beebfa0db32c2c193e8fbad16cec" id="r_ga3100beebfa0db32c2c193e8fbad16cec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3100beebfa0db32c2c193e8fbad16cec">RCC_AHB1LPENR_BKPSRAMLPEN_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga3100beebfa0db32c2c193e8fbad16cec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga192203e1375323694da43336c59f036e" id="r_ga192203e1375323694da43336c59f036e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga192203e1375323694da43336c59f036e">RCC_AHB1LPENR_BKPSRAMLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3100beebfa0db32c2c193e8fbad16cec">RCC_AHB1LPENR_BKPSRAMLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga192203e1375323694da43336c59f036e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga777dc76d2a216f8b51b360e8054342e4" id="r_ga777dc76d2a216f8b51b360e8054342e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga777dc76d2a216f8b51b360e8054342e4">RCC_AHB1LPENR_BKPSRAMLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga192203e1375323694da43336c59f036e">RCC_AHB1LPENR_BKPSRAMLPEN_Msk</a></td></tr>
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<tr class="separator:ga777dc76d2a216f8b51b360e8054342e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga014095a10051377b3cbdd6e5392d4625" id="r_ga014095a10051377b3cbdd6e5392d4625"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga014095a10051377b3cbdd6e5392d4625">RCC_AHB1LPENR_DMA1LPEN_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga014095a10051377b3cbdd6e5392d4625"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c9b77b3b402f07fd5196bc6ced33032" id="r_ga8c9b77b3b402f07fd5196bc6ced33032"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c9b77b3b402f07fd5196bc6ced33032">RCC_AHB1LPENR_DMA1LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga014095a10051377b3cbdd6e5392d4625">RCC_AHB1LPENR_DMA1LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga8c9b77b3b402f07fd5196bc6ced33032"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d6c8ae1441d545d18c54b30c6a0da77" id="r_ga7d6c8ae1441d545d18c54b30c6a0da77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d6c8ae1441d545d18c54b30c6a0da77">RCC_AHB1LPENR_DMA1LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c9b77b3b402f07fd5196bc6ced33032">RCC_AHB1LPENR_DMA1LPEN_Msk</a></td></tr>
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<tr class="separator:ga7d6c8ae1441d545d18c54b30c6a0da77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b8cac0542554d72d2b230feed936194" id="r_ga7b8cac0542554d72d2b230feed936194"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b8cac0542554d72d2b230feed936194">RCC_AHB1LPENR_DMA2LPEN_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga7b8cac0542554d72d2b230feed936194"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a4daa369b439dbff3744661225897bc" id="r_ga8a4daa369b439dbff3744661225897bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a4daa369b439dbff3744661225897bc">RCC_AHB1LPENR_DMA2LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b8cac0542554d72d2b230feed936194">RCC_AHB1LPENR_DMA2LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga8a4daa369b439dbff3744661225897bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e2d376f6c7db4266a5b039a3aa6c207" id="r_ga9e2d376f6c7db4266a5b039a3aa6c207"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e2d376f6c7db4266a5b039a3aa6c207">RCC_AHB1LPENR_DMA2LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a4daa369b439dbff3744661225897bc">RCC_AHB1LPENR_DMA2LPEN_Msk</a></td></tr>
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<tr class="separator:ga9e2d376f6c7db4266a5b039a3aa6c207"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05fd12d343bf91b0cb39a9db295f1c72" id="r_ga05fd12d343bf91b0cb39a9db295f1c72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05fd12d343bf91b0cb39a9db295f1c72">RCC_AHB1LPENR_ETHMACLPEN_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga05fd12d343bf91b0cb39a9db295f1c72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1da28307db95580ebba7ee61b0a8f9cb" id="r_ga1da28307db95580ebba7ee61b0a8f9cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1da28307db95580ebba7ee61b0a8f9cb">RCC_AHB1LPENR_ETHMACLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05fd12d343bf91b0cb39a9db295f1c72">RCC_AHB1LPENR_ETHMACLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga1da28307db95580ebba7ee61b0a8f9cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga421fd0aec3671e054ef18cd290bc164e" id="r_ga421fd0aec3671e054ef18cd290bc164e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga421fd0aec3671e054ef18cd290bc164e">RCC_AHB1LPENR_ETHMACLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1da28307db95580ebba7ee61b0a8f9cb">RCC_AHB1LPENR_ETHMACLPEN_Msk</a></td></tr>
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<tr class="separator:ga421fd0aec3671e054ef18cd290bc164e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga748b751a0809106ddb4c874b11bf36fa" id="r_ga748b751a0809106ddb4c874b11bf36fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga748b751a0809106ddb4c874b11bf36fa">RCC_AHB1LPENR_ETHMACTXLPEN_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga748b751a0809106ddb4c874b11bf36fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a38ff160774afae91d03db40b2cfde1" id="r_ga7a38ff160774afae91d03db40b2cfde1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a38ff160774afae91d03db40b2cfde1">RCC_AHB1LPENR_ETHMACTXLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga748b751a0809106ddb4c874b11bf36fa">RCC_AHB1LPENR_ETHMACTXLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga7a38ff160774afae91d03db40b2cfde1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09935984b92821f18c3e00f7e4fbeb62" id="r_ga09935984b92821f18c3e00f7e4fbeb62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09935984b92821f18c3e00f7e4fbeb62">RCC_AHB1LPENR_ETHMACTXLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a38ff160774afae91d03db40b2cfde1">RCC_AHB1LPENR_ETHMACTXLPEN_Msk</a></td></tr>
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<tr class="separator:ga09935984b92821f18c3e00f7e4fbeb62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe363b3bbbef9025b6b05d007d8e3423" id="r_gabe363b3bbbef9025b6b05d007d8e3423"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe363b3bbbef9025b6b05d007d8e3423">RCC_AHB1LPENR_ETHMACRXLPEN_Pos</a>   (27U)</td></tr>
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<tr class="separator:gabe363b3bbbef9025b6b05d007d8e3423"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga793010bfe42e5e13b9ebed488352b3b3" id="r_ga793010bfe42e5e13b9ebed488352b3b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga793010bfe42e5e13b9ebed488352b3b3">RCC_AHB1LPENR_ETHMACRXLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabe363b3bbbef9025b6b05d007d8e3423">RCC_AHB1LPENR_ETHMACRXLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga793010bfe42e5e13b9ebed488352b3b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga28dc3cec4693215c0db36dcfd8a55ee8" id="r_ga28dc3cec4693215c0db36dcfd8a55ee8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28dc3cec4693215c0db36dcfd8a55ee8">RCC_AHB1LPENR_ETHMACRXLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga793010bfe42e5e13b9ebed488352b3b3">RCC_AHB1LPENR_ETHMACRXLPEN_Msk</a></td></tr>
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<tr class="separator:ga28dc3cec4693215c0db36dcfd8a55ee8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea2001b38e0bac5fd64303d9bb8df6a5" id="r_gaea2001b38e0bac5fd64303d9bb8df6a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea2001b38e0bac5fd64303d9bb8df6a5">RCC_AHB1LPENR_ETHMACPTPLPEN_Pos</a>   (28U)</td></tr>
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<tr class="separator:gaea2001b38e0bac5fd64303d9bb8df6a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9db17131964299ee8997a3bd9f4d5544" id="r_ga9db17131964299ee8997a3bd9f4d5544"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9db17131964299ee8997a3bd9f4d5544">RCC_AHB1LPENR_ETHMACPTPLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea2001b38e0bac5fd64303d9bb8df6a5">RCC_AHB1LPENR_ETHMACPTPLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga9db17131964299ee8997a3bd9f4d5544"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa04c4dfda05aebb5efe66518a28e29de" id="r_gaa04c4dfda05aebb5efe66518a28e29de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa04c4dfda05aebb5efe66518a28e29de">RCC_AHB1LPENR_ETHMACPTPLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9db17131964299ee8997a3bd9f4d5544">RCC_AHB1LPENR_ETHMACPTPLPEN_Msk</a></td></tr>
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<tr class="separator:gaa04c4dfda05aebb5efe66518a28e29de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f86b4c6131db2afce3db43a4b5242c9" id="r_ga4f86b4c6131db2afce3db43a4b5242c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f86b4c6131db2afce3db43a4b5242c9">RCC_AHB1LPENR_OTGHSLPEN_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga4f86b4c6131db2afce3db43a4b5242c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf645b65fa1f722e0909ea5768f5e39d1" id="r_gaf645b65fa1f722e0909ea5768f5e39d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf645b65fa1f722e0909ea5768f5e39d1">RCC_AHB1LPENR_OTGHSLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f86b4c6131db2afce3db43a4b5242c9">RCC_AHB1LPENR_OTGHSLPEN_Pos</a>)</td></tr>
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<tr class="separator:gaf645b65fa1f722e0909ea5768f5e39d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga934a7c19bd6f6b34941058c5c3552b91" id="r_ga934a7c19bd6f6b34941058c5c3552b91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga934a7c19bd6f6b34941058c5c3552b91">RCC_AHB1LPENR_OTGHSLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf645b65fa1f722e0909ea5768f5e39d1">RCC_AHB1LPENR_OTGHSLPEN_Msk</a></td></tr>
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<tr class="separator:ga934a7c19bd6f6b34941058c5c3552b91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7f913b7278276c84700eba1ab154d16" id="r_gaa7f913b7278276c84700eba1ab154d16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7f913b7278276c84700eba1ab154d16">RCC_AHB1LPENR_OTGHSULPILPEN_Pos</a>   (30U)</td></tr>
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<tr class="separator:gaa7f913b7278276c84700eba1ab154d16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9468c1e5269479e8009174e2dbdfd871" id="r_ga9468c1e5269479e8009174e2dbdfd871"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9468c1e5269479e8009174e2dbdfd871">RCC_AHB1LPENR_OTGHSULPILPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7f913b7278276c84700eba1ab154d16">RCC_AHB1LPENR_OTGHSULPILPEN_Pos</a>)</td></tr>
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<tr class="separator:ga9468c1e5269479e8009174e2dbdfd871"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9567cabb8058c53bae64ed4b77c05dd" id="r_gab9567cabb8058c53bae64ed4b77c05dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9567cabb8058c53bae64ed4b77c05dd">RCC_AHB1LPENR_OTGHSULPILPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9468c1e5269479e8009174e2dbdfd871">RCC_AHB1LPENR_OTGHSULPILPEN_Msk</a></td></tr>
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<tr class="separator:gab9567cabb8058c53bae64ed4b77c05dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88eed976ee3304bdf4ba0a514d2f9d17" id="r_ga88eed976ee3304bdf4ba0a514d2f9d17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88eed976ee3304bdf4ba0a514d2f9d17">RCC_AHB2LPENR_DCMILPEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga88eed976ee3304bdf4ba0a514d2f9d17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e9e48b4b6b730a3fc71ecc7bad6f4c7" id="r_ga9e9e48b4b6b730a3fc71ecc7bad6f4c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e9e48b4b6b730a3fc71ecc7bad6f4c7">RCC_AHB2LPENR_DCMILPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga88eed976ee3304bdf4ba0a514d2f9d17">RCC_AHB2LPENR_DCMILPEN_Pos</a>)</td></tr>
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<tr class="separator:ga9e9e48b4b6b730a3fc71ecc7bad6f4c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51ec4f41dcfdedeedef75a64ec65863a" id="r_ga51ec4f41dcfdedeedef75a64ec65863a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51ec4f41dcfdedeedef75a64ec65863a">RCC_AHB2LPENR_DCMILPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e9e48b4b6b730a3fc71ecc7bad6f4c7">RCC_AHB2LPENR_DCMILPEN_Msk</a></td></tr>
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<tr class="separator:ga51ec4f41dcfdedeedef75a64ec65863a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad53ba64643a3daa4220a3515ae089822" id="r_gad53ba64643a3daa4220a3515ae089822"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad53ba64643a3daa4220a3515ae089822">RCC_AHB2LPENR_RNGLPEN_Pos</a>   (6U)</td></tr>
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<tr class="separator:gad53ba64643a3daa4220a3515ae089822"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga082f00df13212bc37c2528b69330a304" id="r_ga082f00df13212bc37c2528b69330a304"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga082f00df13212bc37c2528b69330a304">RCC_AHB2LPENR_RNGLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad53ba64643a3daa4220a3515ae089822">RCC_AHB2LPENR_RNGLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga082f00df13212bc37c2528b69330a304"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab54623c517f1450a7fde279c2cae864" id="r_gaab54623c517f1450a7fde279c2cae864"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab54623c517f1450a7fde279c2cae864">RCC_AHB2LPENR_RNGLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga082f00df13212bc37c2528b69330a304">RCC_AHB2LPENR_RNGLPEN_Msk</a></td></tr>
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<tr class="separator:gaab54623c517f1450a7fde279c2cae864"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3383a619f30eef365e0f6031aaf2423" id="r_gad3383a619f30eef365e0f6031aaf2423"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3383a619f30eef365e0f6031aaf2423">RCC_AHB2LPENR_OTGFSLPEN_Pos</a>   (7U)</td></tr>
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<tr class="separator:gad3383a619f30eef365e0f6031aaf2423"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga235d86e1b22afa92651c1cb0c31660cd" id="r_ga235d86e1b22afa92651c1cb0c31660cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga235d86e1b22afa92651c1cb0c31660cd">RCC_AHB2LPENR_OTGFSLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad3383a619f30eef365e0f6031aaf2423">RCC_AHB2LPENR_OTGFSLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga235d86e1b22afa92651c1cb0c31660cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac0fd858d073b14216ae0d716ba4f1dd3" id="r_gac0fd858d073b14216ae0d716ba4f1dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0fd858d073b14216ae0d716ba4f1dd3">RCC_AHB2LPENR_OTGFSLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga235d86e1b22afa92651c1cb0c31660cd">RCC_AHB2LPENR_OTGFSLPEN_Msk</a></td></tr>
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<tr class="separator:gac0fd858d073b14216ae0d716ba4f1dd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25502d2b4fe408f7fb0238bbe4595754" id="r_ga25502d2b4fe408f7fb0238bbe4595754"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25502d2b4fe408f7fb0238bbe4595754">RCC_AHB3LPENR_FSMCLPEN_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga7d006571ef2ef5c0fb68621fdb5835b7" id="r_ga7d006571ef2ef5c0fb68621fdb5835b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d006571ef2ef5c0fb68621fdb5835b7">RCC_AHB3LPENR_FSMCLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25502d2b4fe408f7fb0238bbe4595754">RCC_AHB3LPENR_FSMCLPEN_Pos</a>)</td></tr>
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<tr class="memitem:gabf56147909fa8e7f8629c7fd7349ecb3" id="r_gabf56147909fa8e7f8629c7fd7349ecb3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf56147909fa8e7f8629c7fd7349ecb3">RCC_AHB3LPENR_FSMCLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d006571ef2ef5c0fb68621fdb5835b7">RCC_AHB3LPENR_FSMCLPEN_Msk</a></td></tr>
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<tr class="separator:gabf56147909fa8e7f8629c7fd7349ecb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66d7d011a4a85de1091644162d0fea68" id="r_ga66d7d011a4a85de1091644162d0fea68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66d7d011a4a85de1091644162d0fea68">RCC_APB1LPENR_TIM2LPEN_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga1ef88837af2b396c012ec1225a4d8a65" id="r_ga1ef88837af2b396c012ec1225a4d8a65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ef88837af2b396c012ec1225a4d8a65">RCC_APB1LPENR_TIM2LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d7d011a4a85de1091644162d0fea68">RCC_APB1LPENR_TIM2LPEN_Pos</a>)</td></tr>
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<tr class="memitem:ga1f561f8bfc556b52335ec2a32ba81c44" id="r_ga1f561f8bfc556b52335ec2a32ba81c44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f561f8bfc556b52335ec2a32ba81c44">RCC_APB1LPENR_TIM2LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ef88837af2b396c012ec1225a4d8a65">RCC_APB1LPENR_TIM2LPEN_Msk</a></td></tr>
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<tr class="separator:ga1f561f8bfc556b52335ec2a32ba81c44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00f72d8c0899d67b6a428e4ed6167630" id="r_ga00f72d8c0899d67b6a428e4ed6167630"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00f72d8c0899d67b6a428e4ed6167630">RCC_APB1LPENR_TIM3LPEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga00f72d8c0899d67b6a428e4ed6167630"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0231e0f1fbb26813e6a67b4e17d2578" id="r_gab0231e0f1fbb26813e6a67b4e17d2578"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0231e0f1fbb26813e6a67b4e17d2578">RCC_APB1LPENR_TIM3LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga00f72d8c0899d67b6a428e4ed6167630">RCC_APB1LPENR_TIM3LPEN_Pos</a>)</td></tr>
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<tr class="separator:gab0231e0f1fbb26813e6a67b4e17d2578"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9391d99885a0a6fbaf3447117ac0f7aa" id="r_ga9391d99885a0a6fbaf3447117ac0f7aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9391d99885a0a6fbaf3447117ac0f7aa">RCC_APB1LPENR_TIM3LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab0231e0f1fbb26813e6a67b4e17d2578">RCC_APB1LPENR_TIM3LPEN_Msk</a></td></tr>
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<tr class="separator:ga9391d99885a0a6fbaf3447117ac0f7aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafaff851f048550c86bb301ed2e1dac9d" id="r_gafaff851f048550c86bb301ed2e1dac9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafaff851f048550c86bb301ed2e1dac9d">RCC_APB1LPENR_TIM4LPEN_Pos</a>   (2U)</td></tr>
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<tr class="separator:gafaff851f048550c86bb301ed2e1dac9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a807ed1ed77d84c24ad990e689b1600" id="r_ga4a807ed1ed77d84c24ad990e689b1600"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a807ed1ed77d84c24ad990e689b1600">RCC_APB1LPENR_TIM4LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafaff851f048550c86bb301ed2e1dac9d">RCC_APB1LPENR_TIM4LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga4a807ed1ed77d84c24ad990e689b1600"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f04aff278b72fbf6acbe0ad947b06ae" id="r_ga6f04aff278b72fbf6acbe0ad947b06ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f04aff278b72fbf6acbe0ad947b06ae">RCC_APB1LPENR_TIM4LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a807ed1ed77d84c24ad990e689b1600">RCC_APB1LPENR_TIM4LPEN_Msk</a></td></tr>
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<tr class="separator:ga6f04aff278b72fbf6acbe0ad947b06ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93219e40400c9b6541b633c0412ac43c" id="r_ga93219e40400c9b6541b633c0412ac43c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93219e40400c9b6541b633c0412ac43c">RCC_APB1LPENR_TIM5LPEN_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga93219e40400c9b6541b633c0412ac43c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73c7205ba8d0f5e12584ccf932efbc74" id="r_ga73c7205ba8d0f5e12584ccf932efbc74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73c7205ba8d0f5e12584ccf932efbc74">RCC_APB1LPENR_TIM5LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga93219e40400c9b6541b633c0412ac43c">RCC_APB1LPENR_TIM5LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga73c7205ba8d0f5e12584ccf932efbc74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5741a6c45b9de1d0c927beb87f399dd9" id="r_ga5741a6c45b9de1d0c927beb87f399dd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5741a6c45b9de1d0c927beb87f399dd9">RCC_APB1LPENR_TIM5LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga73c7205ba8d0f5e12584ccf932efbc74">RCC_APB1LPENR_TIM5LPEN_Msk</a></td></tr>
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<tr class="separator:ga5741a6c45b9de1d0c927beb87f399dd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36d3ba67d01b7993c45c0888a25ba77c" id="r_ga36d3ba67d01b7993c45c0888a25ba77c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36d3ba67d01b7993c45c0888a25ba77c">RCC_APB1LPENR_TIM6LPEN_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga36d3ba67d01b7993c45c0888a25ba77c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec6b200cfb1a2c2d2dd473b4d19213b7" id="r_gaec6b200cfb1a2c2d2dd473b4d19213b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec6b200cfb1a2c2d2dd473b4d19213b7">RCC_APB1LPENR_TIM6LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga36d3ba67d01b7993c45c0888a25ba77c">RCC_APB1LPENR_TIM6LPEN_Pos</a>)</td></tr>
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<tr class="separator:gaec6b200cfb1a2c2d2dd473b4d19213b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga439a5998fd60c3375411c7db2129ac89" id="r_ga439a5998fd60c3375411c7db2129ac89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga439a5998fd60c3375411c7db2129ac89">RCC_APB1LPENR_TIM6LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec6b200cfb1a2c2d2dd473b4d19213b7">RCC_APB1LPENR_TIM6LPEN_Msk</a></td></tr>
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<tr class="separator:ga439a5998fd60c3375411c7db2129ac89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32da6d7364c7a5e303c22098fd748078" id="r_ga32da6d7364c7a5e303c22098fd748078"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32da6d7364c7a5e303c22098fd748078">RCC_APB1LPENR_TIM7LPEN_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga32da6d7364c7a5e303c22098fd748078"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e9c974f3ef148d502bb9898a230dd71" id="r_ga0e9c974f3ef148d502bb9898a230dd71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e9c974f3ef148d502bb9898a230dd71">RCC_APB1LPENR_TIM7LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga32da6d7364c7a5e303c22098fd748078">RCC_APB1LPENR_TIM7LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga0e9c974f3ef148d502bb9898a230dd71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7867dc2695855fa9084a13d06a4299f" id="r_gab7867dc2695855fa9084a13d06a4299f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7867dc2695855fa9084a13d06a4299f">RCC_APB1LPENR_TIM7LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e9c974f3ef148d502bb9898a230dd71">RCC_APB1LPENR_TIM7LPEN_Msk</a></td></tr>
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<tr class="separator:gab7867dc2695855fa9084a13d06a4299f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5108a41416096f47d46c7fd69e810e50" id="r_ga5108a41416096f47d46c7fd69e810e50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5108a41416096f47d46c7fd69e810e50">RCC_APB1LPENR_TIM12LPEN_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga5108a41416096f47d46c7fd69e810e50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe9cf962cc29a62ff4cc27ac9984f1d1" id="r_gafe9cf962cc29a62ff4cc27ac9984f1d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe9cf962cc29a62ff4cc27ac9984f1d1">RCC_APB1LPENR_TIM12LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5108a41416096f47d46c7fd69e810e50">RCC_APB1LPENR_TIM12LPEN_Pos</a>)</td></tr>
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<tr class="separator:gafe9cf962cc29a62ff4cc27ac9984f1d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b47fde44967a5a600a042398a9cf3c6" id="r_ga3b47fde44967a5a600a042398a9cf3c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b47fde44967a5a600a042398a9cf3c6">RCC_APB1LPENR_TIM12LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafe9cf962cc29a62ff4cc27ac9984f1d1">RCC_APB1LPENR_TIM12LPEN_Msk</a></td></tr>
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<tr class="separator:ga3b47fde44967a5a600a042398a9cf3c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2d2664523f65db375f5883e6fba692c" id="r_gaa2d2664523f65db375f5883e6fba692c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2d2664523f65db375f5883e6fba692c">RCC_APB1LPENR_TIM13LPEN_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaa2d2664523f65db375f5883e6fba692c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5df15d5e47024a72fe127a81d8a2e3cf" id="r_ga5df15d5e47024a72fe127a81d8a2e3cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5df15d5e47024a72fe127a81d8a2e3cf">RCC_APB1LPENR_TIM13LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2d2664523f65db375f5883e6fba692c">RCC_APB1LPENR_TIM13LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga5df15d5e47024a72fe127a81d8a2e3cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9897d5f0033623a05997ca222d3a132b" id="r_ga9897d5f0033623a05997ca222d3a132b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9897d5f0033623a05997ca222d3a132b">RCC_APB1LPENR_TIM13LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5df15d5e47024a72fe127a81d8a2e3cf">RCC_APB1LPENR_TIM13LPEN_Msk</a></td></tr>
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<tr class="separator:ga9897d5f0033623a05997ca222d3a132b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a961758cd246c0ef98ffbb703feef88" id="r_ga7a961758cd246c0ef98ffbb703feef88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a961758cd246c0ef98ffbb703feef88">RCC_APB1LPENR_TIM14LPEN_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga7a961758cd246c0ef98ffbb703feef88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e28132e6a8eb793e4e21b4334c56ee7" id="r_ga8e28132e6a8eb793e4e21b4334c56ee7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e28132e6a8eb793e4e21b4334c56ee7">RCC_APB1LPENR_TIM14LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a961758cd246c0ef98ffbb703feef88">RCC_APB1LPENR_TIM14LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga8e28132e6a8eb793e4e21b4334c56ee7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd1af8912fedadb9edead5b31167a310" id="r_gacd1af8912fedadb9edead5b31167a310"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd1af8912fedadb9edead5b31167a310">RCC_APB1LPENR_TIM14LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e28132e6a8eb793e4e21b4334c56ee7">RCC_APB1LPENR_TIM14LPEN_Msk</a></td></tr>
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<tr class="separator:gacd1af8912fedadb9edead5b31167a310"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96ef3e58ec8ebab942b958e1efc365a2" id="r_ga96ef3e58ec8ebab942b958e1efc365a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96ef3e58ec8ebab942b958e1efc365a2">RCC_APB1LPENR_WWDGLPEN_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga24b3760635c135839bffebcdce62aa90" id="r_ga24b3760635c135839bffebcdce62aa90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24b3760635c135839bffebcdce62aa90">RCC_APB1LPENR_WWDGLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96ef3e58ec8ebab942b958e1efc365a2">RCC_APB1LPENR_WWDGLPEN_Pos</a>)</td></tr>
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<tr class="memitem:ga13f3db4ac67bf32c994364cc43f4fe8b" id="r_ga13f3db4ac67bf32c994364cc43f4fe8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13f3db4ac67bf32c994364cc43f4fe8b">RCC_APB1LPENR_WWDGLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga24b3760635c135839bffebcdce62aa90">RCC_APB1LPENR_WWDGLPEN_Msk</a></td></tr>
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<tr class="memitem:ga6c7bc3dcdc95f9245977cc4de874bb1f" id="r_ga6c7bc3dcdc95f9245977cc4de874bb1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c7bc3dcdc95f9245977cc4de874bb1f">RCC_APB1LPENR_SPI2LPEN_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga6c7bc3dcdc95f9245977cc4de874bb1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada9dd21c62e16d73115a855bffc5a98a" id="r_gada9dd21c62e16d73115a855bffc5a98a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada9dd21c62e16d73115a855bffc5a98a">RCC_APB1LPENR_SPI2LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c7bc3dcdc95f9245977cc4de874bb1f">RCC_APB1LPENR_SPI2LPEN_Pos</a>)</td></tr>
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<tr class="separator:gada9dd21c62e16d73115a855bffc5a98a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41dcbf845448cbb1b75c0ad7e83b77cb" id="r_ga41dcbf845448cbb1b75c0ad7e83b77cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41dcbf845448cbb1b75c0ad7e83b77cb">RCC_APB1LPENR_SPI2LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada9dd21c62e16d73115a855bffc5a98a">RCC_APB1LPENR_SPI2LPEN_Msk</a></td></tr>
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<tr class="separator:ga41dcbf845448cbb1b75c0ad7e83b77cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf82b15d2ca1965ca72eb372345bb4dc1" id="r_gaf82b15d2ca1965ca72eb372345bb4dc1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf82b15d2ca1965ca72eb372345bb4dc1">RCC_APB1LPENR_SPI3LPEN_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga7a00b05657ebd904eb04349ce6625799" id="r_ga7a00b05657ebd904eb04349ce6625799"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a00b05657ebd904eb04349ce6625799">RCC_APB1LPENR_SPI3LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf82b15d2ca1965ca72eb372345bb4dc1">RCC_APB1LPENR_SPI3LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga7a00b05657ebd904eb04349ce6625799"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8acbff235a15b58d1be0f065cdb5472" id="r_gae8acbff235a15b58d1be0f065cdb5472"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8acbff235a15b58d1be0f065cdb5472">RCC_APB1LPENR_SPI3LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a00b05657ebd904eb04349ce6625799">RCC_APB1LPENR_SPI3LPEN_Msk</a></td></tr>
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<tr class="separator:gae8acbff235a15b58d1be0f065cdb5472"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36666e20226da8c9ddb2cbeb2aef1330" id="r_ga36666e20226da8c9ddb2cbeb2aef1330"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36666e20226da8c9ddb2cbeb2aef1330">RCC_APB1LPENR_USART2LPEN_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga36666e20226da8c9ddb2cbeb2aef1330"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaffb3fa84a480055b7b9547cc09ed8cb" id="r_gaaffb3fa84a480055b7b9547cc09ed8cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaffb3fa84a480055b7b9547cc09ed8cb">RCC_APB1LPENR_USART2LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga36666e20226da8c9ddb2cbeb2aef1330">RCC_APB1LPENR_USART2LPEN_Pos</a>)</td></tr>
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<tr class="memitem:ga6055c39af369463e14d6ff2017043671" id="r_ga6055c39af369463e14d6ff2017043671"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6055c39af369463e14d6ff2017043671">RCC_APB1LPENR_USART2LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaffb3fa84a480055b7b9547cc09ed8cb">RCC_APB1LPENR_USART2LPEN_Msk</a></td></tr>
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<tr class="memitem:ga215925022960bd4c07052109c70bc999" id="r_ga215925022960bd4c07052109c70bc999"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga215925022960bd4c07052109c70bc999">RCC_APB1LPENR_USART3LPEN_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga215925022960bd4c07052109c70bc999"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabeccde78822839765663f2482e0fd3f2" id="r_gabeccde78822839765663f2482e0fd3f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabeccde78822839765663f2482e0fd3f2">RCC_APB1LPENR_USART3LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga215925022960bd4c07052109c70bc999">RCC_APB1LPENR_USART3LPEN_Pos</a>)</td></tr>
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<tr class="memitem:gae11baa29f4e6d122dabdd54c6b4be052" id="r_gae11baa29f4e6d122dabdd54c6b4be052"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae11baa29f4e6d122dabdd54c6b4be052">RCC_APB1LPENR_USART3LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabeccde78822839765663f2482e0fd3f2">RCC_APB1LPENR_USART3LPEN_Msk</a></td></tr>
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<tr class="memitem:gac8a9e913d67a5976a41240ccacbe6e14" id="r_gac8a9e913d67a5976a41240ccacbe6e14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8a9e913d67a5976a41240ccacbe6e14">RCC_APB1LPENR_UART4LPEN_Pos</a>   (19U)</td></tr>
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<tr class="separator:gac8a9e913d67a5976a41240ccacbe6e14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff134f37108abd0d043c9f62eb250bbc" id="r_gaff134f37108abd0d043c9f62eb250bbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff134f37108abd0d043c9f62eb250bbc">RCC_APB1LPENR_UART4LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8a9e913d67a5976a41240ccacbe6e14">RCC_APB1LPENR_UART4LPEN_Pos</a>)</td></tr>
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<tr class="separator:gaff134f37108abd0d043c9f62eb250bbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88fe1e9cf93caa4e02de35e92e55834d" id="r_ga88fe1e9cf93caa4e02de35e92e55834d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88fe1e9cf93caa4e02de35e92e55834d">RCC_APB1LPENR_UART4LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaff134f37108abd0d043c9f62eb250bbc">RCC_APB1LPENR_UART4LPEN_Msk</a></td></tr>
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<tr class="separator:ga88fe1e9cf93caa4e02de35e92e55834d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c9f855673b672b235461f4cc6480beb" id="r_ga4c9f855673b672b235461f4cc6480beb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c9f855673b672b235461f4cc6480beb">RCC_APB1LPENR_UART5LPEN_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga4c9f855673b672b235461f4cc6480beb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab22aca4251bd69be2f39c31e27344975" id="r_gab22aca4251bd69be2f39c31e27344975"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab22aca4251bd69be2f39c31e27344975">RCC_APB1LPENR_UART5LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c9f855673b672b235461f4cc6480beb">RCC_APB1LPENR_UART5LPEN_Pos</a>)</td></tr>
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<tr class="separator:gab22aca4251bd69be2f39c31e27344975"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3de908135d9c9e74c598f7bf1e88fb34" id="r_ga3de908135d9c9e74c598f7bf1e88fb34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3de908135d9c9e74c598f7bf1e88fb34">RCC_APB1LPENR_UART5LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab22aca4251bd69be2f39c31e27344975">RCC_APB1LPENR_UART5LPEN_Msk</a></td></tr>
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<tr class="separator:ga3de908135d9c9e74c598f7bf1e88fb34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a099cd3cde1ab16cb0a8805d15df425" id="r_ga3a099cd3cde1ab16cb0a8805d15df425"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a099cd3cde1ab16cb0a8805d15df425">RCC_APB1LPENR_I2C1LPEN_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga3a099cd3cde1ab16cb0a8805d15df425"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1afe0c2a2e36921403357bb10f168790" id="r_ga1afe0c2a2e36921403357bb10f168790"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1afe0c2a2e36921403357bb10f168790">RCC_APB1LPENR_I2C1LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a099cd3cde1ab16cb0a8805d15df425">RCC_APB1LPENR_I2C1LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga1afe0c2a2e36921403357bb10f168790"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33286469d0a9b9fedbc2b60aa6cd7da7" id="r_ga33286469d0a9b9fedbc2b60aa6cd7da7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33286469d0a9b9fedbc2b60aa6cd7da7">RCC_APB1LPENR_I2C1LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1afe0c2a2e36921403357bb10f168790">RCC_APB1LPENR_I2C1LPEN_Msk</a></td></tr>
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<tr class="separator:ga33286469d0a9b9fedbc2b60aa6cd7da7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaede8bc79a31bfe414f4c9bb6829b5804" id="r_gaede8bc79a31bfe414f4c9bb6829b5804"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaede8bc79a31bfe414f4c9bb6829b5804">RCC_APB1LPENR_I2C2LPEN_Pos</a>   (22U)</td></tr>
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<tr class="separator:gaede8bc79a31bfe414f4c9bb6829b5804"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76e2c1200c865395531d57931327097d" id="r_ga76e2c1200c865395531d57931327097d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76e2c1200c865395531d57931327097d">RCC_APB1LPENR_I2C2LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaede8bc79a31bfe414f4c9bb6829b5804">RCC_APB1LPENR_I2C2LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga76e2c1200c865395531d57931327097d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6a53d37df11a56412ae06f73626f637" id="r_gaf6a53d37df11a56412ae06f73626f637"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6a53d37df11a56412ae06f73626f637">RCC_APB1LPENR_I2C2LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga76e2c1200c865395531d57931327097d">RCC_APB1LPENR_I2C2LPEN_Msk</a></td></tr>
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<tr class="separator:gaf6a53d37df11a56412ae06f73626f637"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59cb6740257f6c8f1a40b9ce6e5bf498" id="r_ga59cb6740257f6c8f1a40b9ce6e5bf498"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59cb6740257f6c8f1a40b9ce6e5bf498">RCC_APB1LPENR_I2C3LPEN_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga59cb6740257f6c8f1a40b9ce6e5bf498"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga336e724329c3f2adaba3ed13af63de09" id="r_ga336e724329c3f2adaba3ed13af63de09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga336e724329c3f2adaba3ed13af63de09">RCC_APB1LPENR_I2C3LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga59cb6740257f6c8f1a40b9ce6e5bf498">RCC_APB1LPENR_I2C3LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga336e724329c3f2adaba3ed13af63de09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5abf01e4149d71e8427eefcd2e429fe9" id="r_ga5abf01e4149d71e8427eefcd2e429fe9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5abf01e4149d71e8427eefcd2e429fe9">RCC_APB1LPENR_I2C3LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga336e724329c3f2adaba3ed13af63de09">RCC_APB1LPENR_I2C3LPEN_Msk</a></td></tr>
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<tr class="separator:ga5abf01e4149d71e8427eefcd2e429fe9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f780db5faed548d72f11abf461502e6" id="r_ga6f780db5faed548d72f11abf461502e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f780db5faed548d72f11abf461502e6">RCC_APB1LPENR_CAN1LPEN_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga6f780db5faed548d72f11abf461502e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b99fe06fe55b8c9df8e192df0caf4fa" id="r_ga8b99fe06fe55b8c9df8e192df0caf4fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b99fe06fe55b8c9df8e192df0caf4fa">RCC_APB1LPENR_CAN1LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f780db5faed548d72f11abf461502e6">RCC_APB1LPENR_CAN1LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga8b99fe06fe55b8c9df8e192df0caf4fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb93b42a94b988f4a03bed9ea78b4519" id="r_gafb93b42a94b988f4a03bed9ea78b4519"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb93b42a94b988f4a03bed9ea78b4519">RCC_APB1LPENR_CAN1LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b99fe06fe55b8c9df8e192df0caf4fa">RCC_APB1LPENR_CAN1LPEN_Msk</a></td></tr>
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<tr class="separator:gafb93b42a94b988f4a03bed9ea78b4519"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee1a0ced3d5d4088ba28a34e150ffaee" id="r_gaee1a0ced3d5d4088ba28a34e150ffaee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee1a0ced3d5d4088ba28a34e150ffaee">RCC_APB1LPENR_CAN2LPEN_Pos</a>   (26U)</td></tr>
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<tr class="memitem:ga6da195ab0281bf251ae19040f072b8ac" id="r_ga6da195ab0281bf251ae19040f072b8ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6da195ab0281bf251ae19040f072b8ac">RCC_APB1LPENR_CAN2LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee1a0ced3d5d4088ba28a34e150ffaee">RCC_APB1LPENR_CAN2LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga6da195ab0281bf251ae19040f072b8ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga167ad9fc43674d6993a9550ac3b6e70f" id="r_ga167ad9fc43674d6993a9550ac3b6e70f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga167ad9fc43674d6993a9550ac3b6e70f">RCC_APB1LPENR_CAN2LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6da195ab0281bf251ae19040f072b8ac">RCC_APB1LPENR_CAN2LPEN_Msk</a></td></tr>
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<tr class="separator:ga167ad9fc43674d6993a9550ac3b6e70f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67fd356139c695e461be99af8aafa297" id="r_ga67fd356139c695e461be99af8aafa297"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67fd356139c695e461be99af8aafa297">RCC_APB1LPENR_PWRLPEN_Pos</a>   (28U)</td></tr>
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<tr class="memitem:ga653ef9d97213f971b3ace653a8f7f4f0" id="r_ga653ef9d97213f971b3ace653a8f7f4f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga653ef9d97213f971b3ace653a8f7f4f0">RCC_APB1LPENR_PWRLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67fd356139c695e461be99af8aafa297">RCC_APB1LPENR_PWRLPEN_Pos</a>)</td></tr>
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<tr class="memitem:ga274fa282ad1ff40b747644bf9360feb4" id="r_ga274fa282ad1ff40b747644bf9360feb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga274fa282ad1ff40b747644bf9360feb4">RCC_APB1LPENR_PWRLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga653ef9d97213f971b3ace653a8f7f4f0">RCC_APB1LPENR_PWRLPEN_Msk</a></td></tr>
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<tr class="memitem:gad83f868ee37a8885c4ff2e293e4df4f6" id="r_gad83f868ee37a8885c4ff2e293e4df4f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad83f868ee37a8885c4ff2e293e4df4f6">RCC_APB1LPENR_DACLPEN_Pos</a>   (29U)</td></tr>
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<tr class="separator:gad83f868ee37a8885c4ff2e293e4df4f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaecbfaa2f91227a9bdb7c6dcabddb75c7" id="r_gaecbfaa2f91227a9bdb7c6dcabddb75c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecbfaa2f91227a9bdb7c6dcabddb75c7">RCC_APB1LPENR_DACLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad83f868ee37a8885c4ff2e293e4df4f6">RCC_APB1LPENR_DACLPEN_Pos</a>)</td></tr>
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<tr class="separator:gaecbfaa2f91227a9bdb7c6dcabddb75c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf36a11e89644548702385d548f3f9ec4" id="r_gaf36a11e89644548702385d548f3f9ec4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf36a11e89644548702385d548f3f9ec4">RCC_APB1LPENR_DACLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaecbfaa2f91227a9bdb7c6dcabddb75c7">RCC_APB1LPENR_DACLPEN_Msk</a></td></tr>
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<tr class="separator:gaf36a11e89644548702385d548f3f9ec4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ac0ea3808afc94624b680e8b3749a66" id="r_ga5ac0ea3808afc94624b680e8b3749a66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ac0ea3808afc94624b680e8b3749a66">RCC_APB2LPENR_TIM1LPEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5ac0ea3808afc94624b680e8b3749a66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga858c7e6effbead8e2953c8af89451f05" id="r_ga858c7e6effbead8e2953c8af89451f05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga858c7e6effbead8e2953c8af89451f05">RCC_APB2LPENR_TIM1LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ac0ea3808afc94624b680e8b3749a66">RCC_APB2LPENR_TIM1LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga858c7e6effbead8e2953c8af89451f05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82580245686c32761e8354fb174ba5dd" id="r_ga82580245686c32761e8354fb174ba5dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82580245686c32761e8354fb174ba5dd">RCC_APB2LPENR_TIM1LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga858c7e6effbead8e2953c8af89451f05">RCC_APB2LPENR_TIM1LPEN_Msk</a></td></tr>
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<tr class="separator:ga82580245686c32761e8354fb174ba5dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04afe23491647fcdf2a0cfeadce36cf0" id="r_ga04afe23491647fcdf2a0cfeadce36cf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04afe23491647fcdf2a0cfeadce36cf0">RCC_APB2LPENR_TIM8LPEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga04afe23491647fcdf2a0cfeadce36cf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga193680b82d9cdcefad8ff2ac9e7ed2da" id="r_ga193680b82d9cdcefad8ff2ac9e7ed2da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga193680b82d9cdcefad8ff2ac9e7ed2da">RCC_APB2LPENR_TIM8LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga04afe23491647fcdf2a0cfeadce36cf0">RCC_APB2LPENR_TIM8LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga193680b82d9cdcefad8ff2ac9e7ed2da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a1a808f511ff563f05f32ad3ae6d7c1" id="r_ga8a1a808f511ff563f05f32ad3ae6d7c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a1a808f511ff563f05f32ad3ae6d7c1">RCC_APB2LPENR_TIM8LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga193680b82d9cdcefad8ff2ac9e7ed2da">RCC_APB2LPENR_TIM8LPEN_Msk</a></td></tr>
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<tr class="separator:ga8a1a808f511ff563f05f32ad3ae6d7c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bcb3fc3f4b2e68f667724cdd2e04ce8" id="r_ga4bcb3fc3f4b2e68f667724cdd2e04ce8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bcb3fc3f4b2e68f667724cdd2e04ce8">RCC_APB2LPENR_USART1LPEN_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga4bcb3fc3f4b2e68f667724cdd2e04ce8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga294b9579075d948ff613d153a7a3c3ca" id="r_ga294b9579075d948ff613d153a7a3c3ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga294b9579075d948ff613d153a7a3c3ca">RCC_APB2LPENR_USART1LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bcb3fc3f4b2e68f667724cdd2e04ce8">RCC_APB2LPENR_USART1LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga294b9579075d948ff613d153a7a3c3ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8b429bc8d52abd1ba3818a82542bb98" id="r_gab8b429bc8d52abd1ba3818a82542bb98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8b429bc8d52abd1ba3818a82542bb98">RCC_APB2LPENR_USART1LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga294b9579075d948ff613d153a7a3c3ca">RCC_APB2LPENR_USART1LPEN_Msk</a></td></tr>
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<tr class="separator:gab8b429bc8d52abd1ba3818a82542bb98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa70231e7e2fbbac64535106f4aa48e3f" id="r_gaa70231e7e2fbbac64535106f4aa48e3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa70231e7e2fbbac64535106f4aa48e3f">RCC_APB2LPENR_USART6LPEN_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaa70231e7e2fbbac64535106f4aa48e3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4262d6ef04c2c0ebe14c133021f0ae03" id="r_ga4262d6ef04c2c0ebe14c133021f0ae03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4262d6ef04c2c0ebe14c133021f0ae03">RCC_APB2LPENR_USART6LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa70231e7e2fbbac64535106f4aa48e3f">RCC_APB2LPENR_USART6LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga4262d6ef04c2c0ebe14c133021f0ae03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b82eb1986da9ed32e6701d01fffe55d" id="r_ga2b82eb1986da9ed32e6701d01fffe55d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b82eb1986da9ed32e6701d01fffe55d">RCC_APB2LPENR_USART6LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4262d6ef04c2c0ebe14c133021f0ae03">RCC_APB2LPENR_USART6LPEN_Msk</a></td></tr>
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<tr class="separator:ga2b82eb1986da9ed32e6701d01fffe55d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae30aac03ac0c319cc528d35e7f459997" id="r_gae30aac03ac0c319cc528d35e7f459997"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae30aac03ac0c319cc528d35e7f459997">RCC_APB2LPENR_ADC1LPEN_Pos</a>   (8U)</td></tr>
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<tr class="separator:gae30aac03ac0c319cc528d35e7f459997"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga116ac44e1a83643de5be822458c9f42b" id="r_ga116ac44e1a83643de5be822458c9f42b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga116ac44e1a83643de5be822458c9f42b">RCC_APB2LPENR_ADC1LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae30aac03ac0c319cc528d35e7f459997">RCC_APB2LPENR_ADC1LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga116ac44e1a83643de5be822458c9f42b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga126a8791f77cecc599e32d2c882a4dab" id="r_ga126a8791f77cecc599e32d2c882a4dab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga126a8791f77cecc599e32d2c882a4dab">RCC_APB2LPENR_ADC1LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga116ac44e1a83643de5be822458c9f42b">RCC_APB2LPENR_ADC1LPEN_Msk</a></td></tr>
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<tr class="separator:ga126a8791f77cecc599e32d2c882a4dab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20aaf3952e7679b2535befd5db14781b" id="r_ga20aaf3952e7679b2535befd5db14781b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20aaf3952e7679b2535befd5db14781b">RCC_APB2LPENR_ADC2LPEN_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga20aaf3952e7679b2535befd5db14781b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab6de7661abce7e5d9b3d9d47938095b0" id="r_gab6de7661abce7e5d9b3d9d47938095b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6de7661abce7e5d9b3d9d47938095b0">RCC_APB2LPENR_ADC2LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20aaf3952e7679b2535befd5db14781b">RCC_APB2LPENR_ADC2LPEN_Pos</a>)</td></tr>
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<tr class="separator:gab6de7661abce7e5d9b3d9d47938095b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7d578d9d9a12e3f0b4246e196040c13" id="r_gab7d578d9d9a12e3f0b4246e196040c13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7d578d9d9a12e3f0b4246e196040c13">RCC_APB2LPENR_ADC2LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab6de7661abce7e5d9b3d9d47938095b0">RCC_APB2LPENR_ADC2LPEN_Msk</a></td></tr>
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<tr class="separator:gab7d578d9d9a12e3f0b4246e196040c13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga287cf6c970a88095bdabcb50dbebd196" id="r_ga287cf6c970a88095bdabcb50dbebd196"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga287cf6c970a88095bdabcb50dbebd196">RCC_APB2LPENR_ADC3LPEN_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga287cf6c970a88095bdabcb50dbebd196"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94f89563dfe984830b279fe3d358ca27" id="r_ga94f89563dfe984830b279fe3d358ca27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94f89563dfe984830b279fe3d358ca27">RCC_APB2LPENR_ADC3LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga287cf6c970a88095bdabcb50dbebd196">RCC_APB2LPENR_ADC3LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga94f89563dfe984830b279fe3d358ca27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12c8300ba9b1ce9b14fc8e0f3ec4c127" id="r_ga12c8300ba9b1ce9b14fc8e0f3ec4c127"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12c8300ba9b1ce9b14fc8e0f3ec4c127">RCC_APB2LPENR_ADC3LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga94f89563dfe984830b279fe3d358ca27">RCC_APB2LPENR_ADC3LPEN_Msk</a></td></tr>
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<tr class="separator:ga12c8300ba9b1ce9b14fc8e0f3ec4c127"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e852d24cc37b0873db77eec05211616" id="r_ga7e852d24cc37b0873db77eec05211616"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e852d24cc37b0873db77eec05211616">RCC_APB2LPENR_SDIOLPEN_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga407fda261b548cac4ba4f70d13250a0e" id="r_ga407fda261b548cac4ba4f70d13250a0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga407fda261b548cac4ba4f70d13250a0e">RCC_APB2LPENR_SDIOLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e852d24cc37b0873db77eec05211616">RCC_APB2LPENR_SDIOLPEN_Pos</a>)</td></tr>
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<tr class="separator:ga407fda261b548cac4ba4f70d13250a0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a740fdf8313fbdd00dd97eb73afc4dc" id="r_ga7a740fdf8313fbdd00dd97eb73afc4dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a740fdf8313fbdd00dd97eb73afc4dc">RCC_APB2LPENR_SDIOLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga407fda261b548cac4ba4f70d13250a0e">RCC_APB2LPENR_SDIOLPEN_Msk</a></td></tr>
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<tr class="memitem:ga2ddb35d5536b1e28be09ba48b0726721" id="r_ga2ddb35d5536b1e28be09ba48b0726721"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ddb35d5536b1e28be09ba48b0726721">RCC_APB2LPENR_SPI1LPEN_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga2ddb35d5536b1e28be09ba48b0726721"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3b71e51ae5bffdaf53ceb522f147892" id="r_gae3b71e51ae5bffdaf53ceb522f147892"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3b71e51ae5bffdaf53ceb522f147892">RCC_APB2LPENR_SPI1LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ddb35d5536b1e28be09ba48b0726721">RCC_APB2LPENR_SPI1LPEN_Pos</a>)</td></tr>
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<tr class="memitem:ga2c6729058e54f4b8f8ae01d5b3586aaa" id="r_ga2c6729058e54f4b8f8ae01d5b3586aaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c6729058e54f4b8f8ae01d5b3586aaa">RCC_APB2LPENR_SPI1LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3b71e51ae5bffdaf53ceb522f147892">RCC_APB2LPENR_SPI1LPEN_Msk</a></td></tr>
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<tr class="separator:ga2c6729058e54f4b8f8ae01d5b3586aaa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4bb28885c56bf8b04da2633393c5b47" id="r_gaa4bb28885c56bf8b04da2633393c5b47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4bb28885c56bf8b04da2633393c5b47">RCC_APB2LPENR_SYSCFGLPEN_Pos</a>   (14U)</td></tr>
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<tr class="separator:gaa4bb28885c56bf8b04da2633393c5b47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4d070a25b830752decd55b74a452cda" id="r_gab4d070a25b830752decd55b74a452cda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4d070a25b830752decd55b74a452cda">RCC_APB2LPENR_SYSCFGLPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4bb28885c56bf8b04da2633393c5b47">RCC_APB2LPENR_SYSCFGLPEN_Pos</a>)</td></tr>
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<tr class="separator:gab4d070a25b830752decd55b74a452cda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa82cfc33f0cf71220398bbe1c4b412e" id="r_gaaa82cfc33f0cf71220398bbe1c4b412e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa82cfc33f0cf71220398bbe1c4b412e">RCC_APB2LPENR_SYSCFGLPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab4d070a25b830752decd55b74a452cda">RCC_APB2LPENR_SYSCFGLPEN_Msk</a></td></tr>
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<tr class="memitem:gae087736e445764bceba754d1d424f8d1" id="r_gae087736e445764bceba754d1d424f8d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae087736e445764bceba754d1d424f8d1">RCC_APB2LPENR_TIM9LPEN_Pos</a>   (16U)</td></tr>
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<tr class="separator:gae087736e445764bceba754d1d424f8d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3d30a083acde66ba393ef2e7e2d3424" id="r_gae3d30a083acde66ba393ef2e7e2d3424"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3d30a083acde66ba393ef2e7e2d3424">RCC_APB2LPENR_TIM9LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae087736e445764bceba754d1d424f8d1">RCC_APB2LPENR_TIM9LPEN_Pos</a>)</td></tr>
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<tr class="separator:gae3d30a083acde66ba393ef2e7e2d3424"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91b882f3dc2b939a53ed3f4caa537de1" id="r_ga91b882f3dc2b939a53ed3f4caa537de1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91b882f3dc2b939a53ed3f4caa537de1">RCC_APB2LPENR_TIM9LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3d30a083acde66ba393ef2e7e2d3424">RCC_APB2LPENR_TIM9LPEN_Msk</a></td></tr>
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<tr class="separator:ga91b882f3dc2b939a53ed3f4caa537de1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf74626f4a9c7d80ee37c80c18b76c9af" id="r_gaf74626f4a9c7d80ee37c80c18b76c9af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf74626f4a9c7d80ee37c80c18b76c9af">RCC_APB2LPENR_TIM10LPEN_Pos</a>   (17U)</td></tr>
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<tr class="memitem:gac8e04154247e0db474da2cc8eccac1f2" id="r_gac8e04154247e0db474da2cc8eccac1f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8e04154247e0db474da2cc8eccac1f2">RCC_APB2LPENR_TIM10LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf74626f4a9c7d80ee37c80c18b76c9af">RCC_APB2LPENR_TIM10LPEN_Pos</a>)</td></tr>
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<tr class="separator:gac8e04154247e0db474da2cc8eccac1f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7999e2ebeb1300d0cf6a59ad92c41b6" id="r_gae7999e2ebeb1300d0cf6a59ad92c41b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7999e2ebeb1300d0cf6a59ad92c41b6">RCC_APB2LPENR_TIM10LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac8e04154247e0db474da2cc8eccac1f2">RCC_APB2LPENR_TIM10LPEN_Msk</a></td></tr>
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<tr class="separator:gae7999e2ebeb1300d0cf6a59ad92c41b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabcc3b8ef34620fa6f4e82cbbf527fc27" id="r_gabcc3b8ef34620fa6f4e82cbbf527fc27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabcc3b8ef34620fa6f4e82cbbf527fc27">RCC_APB2LPENR_TIM11LPEN_Pos</a>   (18U)</td></tr>
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<tr class="separator:gabcc3b8ef34620fa6f4e82cbbf527fc27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4cabf028115d0694b1bba23610d23da8" id="r_ga4cabf028115d0694b1bba23610d23da8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4cabf028115d0694b1bba23610d23da8">RCC_APB2LPENR_TIM11LPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabcc3b8ef34620fa6f4e82cbbf527fc27">RCC_APB2LPENR_TIM11LPEN_Pos</a>)</td></tr>
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<tr class="separator:ga4cabf028115d0694b1bba23610d23da8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad43fcaa4f4d6fb2b590a6ffee31f8c94" id="r_gad43fcaa4f4d6fb2b590a6ffee31f8c94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad43fcaa4f4d6fb2b590a6ffee31f8c94">RCC_APB2LPENR_TIM11LPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4cabf028115d0694b1bba23610d23da8">RCC_APB2LPENR_TIM11LPEN_Msk</a></td></tr>
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<tr class="separator:gad43fcaa4f4d6fb2b590a6ffee31f8c94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga016de845d59f61611054d27511a3fa68" id="r_ga016de845d59f61611054d27511a3fa68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga016de845d59f61611054d27511a3fa68">RCC_BDCR_LSEON_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga85556465021c4272f4788d52251b29f4" id="r_ga85556465021c4272f4788d52251b29f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85556465021c4272f4788d52251b29f4">RCC_BDCR_LSEON_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga016de845d59f61611054d27511a3fa68">RCC_BDCR_LSEON_Pos</a>)</td></tr>
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<tr class="memitem:ga00145f8814cb9a5b180d76499d97aead" id="r_ga00145f8814cb9a5b180d76499d97aead"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00145f8814cb9a5b180d76499d97aead">RCC_BDCR_LSEON</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga85556465021c4272f4788d52251b29f4">RCC_BDCR_LSEON_Msk</a></td></tr>
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<tr class="separator:ga00145f8814cb9a5b180d76499d97aead"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d373419116fa0446eee779da5292b02" id="r_ga1d373419116fa0446eee779da5292b02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d373419116fa0446eee779da5292b02">RCC_BDCR_LSERDY_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga35093bcccacfeda073a2fb815687549c" id="r_ga35093bcccacfeda073a2fb815687549c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35093bcccacfeda073a2fb815687549c">RCC_BDCR_LSERDY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d373419116fa0446eee779da5292b02">RCC_BDCR_LSERDY_Pos</a>)</td></tr>
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<tr class="memitem:gaafca81172ed857ce6b94582fcaada87c" id="r_gaafca81172ed857ce6b94582fcaada87c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafca81172ed857ce6b94582fcaada87c">RCC_BDCR_LSERDY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga35093bcccacfeda073a2fb815687549c">RCC_BDCR_LSERDY_Msk</a></td></tr>
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<tr class="separator:gaafca81172ed857ce6b94582fcaada87c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8900b556c097b54266370f197517c2b4" id="r_ga8900b556c097b54266370f197517c2b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8900b556c097b54266370f197517c2b4">RCC_BDCR_LSEBYP_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga7e5eba5220ddabddf14901a8d44abaf2" id="r_ga7e5eba5220ddabddf14901a8d44abaf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e5eba5220ddabddf14901a8d44abaf2">RCC_BDCR_LSEBYP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8900b556c097b54266370f197517c2b4">RCC_BDCR_LSEBYP_Pos</a>)</td></tr>
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<tr class="memitem:ga542dffd7f8dc4da5401b54d822a22af0" id="r_ga542dffd7f8dc4da5401b54d822a22af0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga542dffd7f8dc4da5401b54d822a22af0">RCC_BDCR_LSEBYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e5eba5220ddabddf14901a8d44abaf2">RCC_BDCR_LSEBYP_Msk</a></td></tr>
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<tr class="separator:ga542dffd7f8dc4da5401b54d822a22af0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ba11e8b21a7165e4b8e9a2cbf5a323d" id="r_ga1ba11e8b21a7165e4b8e9a2cbf5a323d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ba11e8b21a7165e4b8e9a2cbf5a323d">RCC_BDCR_RTCSEL_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga1ba11e8b21a7165e4b8e9a2cbf5a323d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57377b1880634589201dfe8887287e0e" id="r_ga57377b1880634589201dfe8887287e0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57377b1880634589201dfe8887287e0e">RCC_BDCR_RTCSEL_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ba11e8b21a7165e4b8e9a2cbf5a323d">RCC_BDCR_RTCSEL_Pos</a>)</td></tr>
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<tr class="memitem:gabe30dbd38f6456990ee641648bc05d40" id="r_gabe30dbd38f6456990ee641648bc05d40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe30dbd38f6456990ee641648bc05d40">RCC_BDCR_RTCSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57377b1880634589201dfe8887287e0e">RCC_BDCR_RTCSEL_Msk</a></td></tr>
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<tr class="memitem:ga6701d58e40e4c16e9be49436fcbe23d0" id="r_ga6701d58e40e4c16e9be49436fcbe23d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6701d58e40e4c16e9be49436fcbe23d0">RCC_BDCR_RTCSEL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ba11e8b21a7165e4b8e9a2cbf5a323d">RCC_BDCR_RTCSEL_Pos</a>)</td></tr>
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<tr class="separator:ga6701d58e40e4c16e9be49436fcbe23d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac4e378027f3293ec520ed6d18c633f4" id="r_gaac4e378027f3293ec520ed6d18c633f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac4e378027f3293ec520ed6d18c633f4">RCC_BDCR_RTCSEL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ba11e8b21a7165e4b8e9a2cbf5a323d">RCC_BDCR_RTCSEL_Pos</a>)</td></tr>
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<tr class="separator:gaac4e378027f3293ec520ed6d18c633f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad32e3fd78eebb6ac9bb446a9fdda3d0d" id="r_gad32e3fd78eebb6ac9bb446a9fdda3d0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad32e3fd78eebb6ac9bb446a9fdda3d0d">RCC_BDCR_RTCEN_Pos</a>   (15U)</td></tr>
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<tr class="memitem:gad4b2e482dc6f5c75861f08de8057d1e2" id="r_gad4b2e482dc6f5c75861f08de8057d1e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4b2e482dc6f5c75861f08de8057d1e2">RCC_BDCR_RTCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad32e3fd78eebb6ac9bb446a9fdda3d0d">RCC_BDCR_RTCEN_Pos</a>)</td></tr>
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<tr class="separator:gad4b2e482dc6f5c75861f08de8057d1e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79ea6f2df75f09b17df9582037ed6a53" id="r_ga79ea6f2df75f09b17df9582037ed6a53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79ea6f2df75f09b17df9582037ed6a53">RCC_BDCR_RTCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad4b2e482dc6f5c75861f08de8057d1e2">RCC_BDCR_RTCEN_Msk</a></td></tr>
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<tr class="separator:ga79ea6f2df75f09b17df9582037ed6a53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac787de49ce5fa9a2e0123ddf33f4e26e" id="r_gac787de49ce5fa9a2e0123ddf33f4e26e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac787de49ce5fa9a2e0123ddf33f4e26e">RCC_BDCR_BDRST_Pos</a>   (16U)</td></tr>
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<tr class="separator:gac787de49ce5fa9a2e0123ddf33f4e26e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a3b3c81018daa0d5b80480a86bc7a17" id="r_ga0a3b3c81018daa0d5b80480a86bc7a17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a3b3c81018daa0d5b80480a86bc7a17">RCC_BDCR_BDRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac787de49ce5fa9a2e0123ddf33f4e26e">RCC_BDCR_BDRST_Pos</a>)</td></tr>
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<tr class="separator:ga0a3b3c81018daa0d5b80480a86bc7a17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b85b3ab656dfa2809b15e6e530c17a2" id="r_ga2b85b3ab656dfa2809b15e6e530c17a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b85b3ab656dfa2809b15e6e530c17a2">RCC_BDCR_BDRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a3b3c81018daa0d5b80480a86bc7a17">RCC_BDCR_BDRST_Msk</a></td></tr>
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<tr class="separator:ga2b85b3ab656dfa2809b15e6e530c17a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc156654e34b1b6206760ba8d864c6c8" id="r_gafc156654e34b1b6206760ba8d864c6c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc156654e34b1b6206760ba8d864c6c8">RCC_CSR_LSION_Pos</a>   (0U)</td></tr>
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<tr class="separator:gafc156654e34b1b6206760ba8d864c6c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe63b332158f8886948205ff9edcf248" id="r_gabe63b332158f8886948205ff9edcf248"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe63b332158f8886948205ff9edcf248">RCC_CSR_LSION_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafc156654e34b1b6206760ba8d864c6c8">RCC_CSR_LSION_Pos</a>)</td></tr>
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<tr class="separator:gabe63b332158f8886948205ff9edcf248"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga803cbf97bda1ebaf9afee2a3c9f0851b" id="r_ga803cbf97bda1ebaf9afee2a3c9f0851b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga803cbf97bda1ebaf9afee2a3c9f0851b">RCC_CSR_LSION</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe63b332158f8886948205ff9edcf248">RCC_CSR_LSION_Msk</a></td></tr>
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<tr class="separator:ga803cbf97bda1ebaf9afee2a3c9f0851b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68272a20b7fe83a0e08b1deb4aeacf55" id="r_ga68272a20b7fe83a0e08b1deb4aeacf55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68272a20b7fe83a0e08b1deb4aeacf55">RCC_CSR_LSIRDY_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga68272a20b7fe83a0e08b1deb4aeacf55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49a5c93576efd3e5d284351db6125373" id="r_ga49a5c93576efd3e5d284351db6125373"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49a5c93576efd3e5d284351db6125373">RCC_CSR_LSIRDY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68272a20b7fe83a0e08b1deb4aeacf55">RCC_CSR_LSIRDY_Pos</a>)</td></tr>
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<tr class="separator:ga49a5c93576efd3e5d284351db6125373"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab569110e757aee573ebf9ad80812e8bb" id="r_gab569110e757aee573ebf9ad80812e8bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab569110e757aee573ebf9ad80812e8bb">RCC_CSR_LSIRDY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga49a5c93576efd3e5d284351db6125373">RCC_CSR_LSIRDY_Msk</a></td></tr>
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<tr class="separator:gab569110e757aee573ebf9ad80812e8bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae97ee308ed96cdb97bc991b34aa95be4" id="r_gae97ee308ed96cdb97bc991b34aa95be4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae97ee308ed96cdb97bc991b34aa95be4">RCC_CSR_RMVF_Pos</a>   (24U)</td></tr>
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<tr class="separator:gae97ee308ed96cdb97bc991b34aa95be4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82a7f8a2897bcc1313d58389fc18ad4c" id="r_ga82a7f8a2897bcc1313d58389fc18ad4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82a7f8a2897bcc1313d58389fc18ad4c">RCC_CSR_RMVF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae97ee308ed96cdb97bc991b34aa95be4">RCC_CSR_RMVF_Pos</a>)</td></tr>
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<tr class="separator:ga82a7f8a2897bcc1313d58389fc18ad4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc26c5996b14005a70afbeaa29aae716" id="r_gafc26c5996b14005a70afbeaa29aae716"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc26c5996b14005a70afbeaa29aae716">RCC_CSR_RMVF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga82a7f8a2897bcc1313d58389fc18ad4c">RCC_CSR_RMVF_Msk</a></td></tr>
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<tr class="separator:gafc26c5996b14005a70afbeaa29aae716"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c08aed9f0628271098706c4b46be813" id="r_ga9c08aed9f0628271098706c4b46be813"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c08aed9f0628271098706c4b46be813">RCC_CSR_BORRSTF_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga9c08aed9f0628271098706c4b46be813"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55345f6a3e5c36cad82d85c3c7c9114c" id="r_ga55345f6a3e5c36cad82d85c3c7c9114c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55345f6a3e5c36cad82d85c3c7c9114c">RCC_CSR_BORRSTF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c08aed9f0628271098706c4b46be813">RCC_CSR_BORRSTF_Pos</a>)</td></tr>
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<tr class="separator:ga55345f6a3e5c36cad82d85c3c7c9114c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6685c7bd94a46c82c7ca69afa1707c39" id="r_ga6685c7bd94a46c82c7ca69afa1707c39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6685c7bd94a46c82c7ca69afa1707c39">RCC_CSR_BORRSTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga55345f6a3e5c36cad82d85c3c7c9114c">RCC_CSR_BORRSTF_Msk</a></td></tr>
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<tr class="separator:ga6685c7bd94a46c82c7ca69afa1707c39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47a45faed934912e57c0dea6d6af8227" id="r_ga47a45faed934912e57c0dea6d6af8227"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47a45faed934912e57c0dea6d6af8227">RCC_CSR_PINRSTF_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga47a45faed934912e57c0dea6d6af8227"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13e888e00c5b2226b70179c6c69b77a6" id="r_ga13e888e00c5b2226b70179c6c69b77a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13e888e00c5b2226b70179c6c69b77a6">RCC_CSR_PINRSTF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga47a45faed934912e57c0dea6d6af8227">RCC_CSR_PINRSTF_Pos</a>)</td></tr>
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<tr class="separator:ga13e888e00c5b2226b70179c6c69b77a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e26d2902d11e638cd0b702332f53ab1" id="r_ga4e26d2902d11e638cd0b702332f53ab1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e26d2902d11e638cd0b702332f53ab1">RCC_CSR_PINRSTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga13e888e00c5b2226b70179c6c69b77a6">RCC_CSR_PINRSTF_Msk</a></td></tr>
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<tr class="separator:ga4e26d2902d11e638cd0b702332f53ab1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8d531dd5cf68eb67b1bce22ceddaac4" id="r_gab8d531dd5cf68eb67b1bce22ceddaac4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8d531dd5cf68eb67b1bce22ceddaac4">RCC_CSR_PORRSTF_Pos</a>   (27U)</td></tr>
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<tr class="separator:gab8d531dd5cf68eb67b1bce22ceddaac4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ea00bd02372ecbc60c5fa71a37dc8dd" id="r_ga6ea00bd02372ecbc60c5fa71a37dc8dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ea00bd02372ecbc60c5fa71a37dc8dd">RCC_CSR_PORRSTF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8d531dd5cf68eb67b1bce22ceddaac4">RCC_CSR_PORRSTF_Pos</a>)</td></tr>
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<tr class="separator:ga6ea00bd02372ecbc60c5fa71a37dc8dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga837e2d7e2395ac45ebe2aea95ecde9bf" id="r_ga837e2d7e2395ac45ebe2aea95ecde9bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga837e2d7e2395ac45ebe2aea95ecde9bf">RCC_CSR_PORRSTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ea00bd02372ecbc60c5fa71a37dc8dd">RCC_CSR_PORRSTF_Msk</a></td></tr>
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<tr class="separator:ga837e2d7e2395ac45ebe2aea95ecde9bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02078fdb0a3610702b75d5e05dbb92af" id="r_ga02078fdb0a3610702b75d5e05dbb92af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02078fdb0a3610702b75d5e05dbb92af">RCC_CSR_SFTRSTF_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga02078fdb0a3610702b75d5e05dbb92af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7217efb6cbdb6fbf39721fe496249225" id="r_ga7217efb6cbdb6fbf39721fe496249225"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7217efb6cbdb6fbf39721fe496249225">RCC_CSR_SFTRSTF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02078fdb0a3610702b75d5e05dbb92af">RCC_CSR_SFTRSTF_Pos</a>)</td></tr>
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<tr class="separator:ga7217efb6cbdb6fbf39721fe496249225"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16e89534934436ee8958440882b71e6f" id="r_ga16e89534934436ee8958440882b71e6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16e89534934436ee8958440882b71e6f">RCC_CSR_SFTRSTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7217efb6cbdb6fbf39721fe496249225">RCC_CSR_SFTRSTF_Msk</a></td></tr>
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<tr class="separator:ga16e89534934436ee8958440882b71e6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fbb93c907ec9ca631e6657eb22b85a3" id="r_ga8fbb93c907ec9ca631e6657eb22b85a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fbb93c907ec9ca631e6657eb22b85a3">RCC_CSR_IWDGRSTF_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga8fbb93c907ec9ca631e6657eb22b85a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb81cb1777e6e846b6199b64132bcb97" id="r_gabb81cb1777e6e846b6199b64132bcb97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb81cb1777e6e846b6199b64132bcb97">RCC_CSR_IWDGRSTF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8fbb93c907ec9ca631e6657eb22b85a3">RCC_CSR_IWDGRSTF_Pos</a>)</td></tr>
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<tr class="separator:gabb81cb1777e6e846b6199b64132bcb97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22a7079ba87dd7acd5ed7fe7b704e85f" id="r_ga22a7079ba87dd7acd5ed7fe7b704e85f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22a7079ba87dd7acd5ed7fe7b704e85f">RCC_CSR_IWDGRSTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabb81cb1777e6e846b6199b64132bcb97">RCC_CSR_IWDGRSTF_Msk</a></td></tr>
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<tr class="separator:ga22a7079ba87dd7acd5ed7fe7b704e85f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3b146c508145d8e03143a991615ed81" id="r_gac3b146c508145d8e03143a991615ed81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3b146c508145d8e03143a991615ed81">RCC_CSR_WWDGRSTF_Pos</a>   (30U)</td></tr>
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<tr class="separator:gac3b146c508145d8e03143a991615ed81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d9afc0a5d27d08ef63dde9f0a39514d" id="r_ga6d9afc0a5d27d08ef63dde9f0a39514d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d9afc0a5d27d08ef63dde9f0a39514d">RCC_CSR_WWDGRSTF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3b146c508145d8e03143a991615ed81">RCC_CSR_WWDGRSTF_Pos</a>)</td></tr>
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<tr class="separator:ga6d9afc0a5d27d08ef63dde9f0a39514d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacabd7bbde7e78c9c8f5fd46e34771826" id="r_gacabd7bbde7e78c9c8f5fd46e34771826"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacabd7bbde7e78c9c8f5fd46e34771826">RCC_CSR_WWDGRSTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d9afc0a5d27d08ef63dde9f0a39514d">RCC_CSR_WWDGRSTF_Msk</a></td></tr>
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<tr class="separator:gacabd7bbde7e78c9c8f5fd46e34771826"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2761b43e9b00d52102efb7375a86e6e0" id="r_ga2761b43e9b00d52102efb7375a86e6e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2761b43e9b00d52102efb7375a86e6e0">RCC_CSR_LPWRRSTF_Pos</a>   (31U)</td></tr>
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<tr class="memitem:ga8b42e835fb77d45779cdf4d22a0ea22a" id="r_ga8b42e835fb77d45779cdf4d22a0ea22a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b42e835fb77d45779cdf4d22a0ea22a">RCC_CSR_LPWRRSTF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2761b43e9b00d52102efb7375a86e6e0">RCC_CSR_LPWRRSTF_Pos</a>)</td></tr>
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<tr class="memitem:ga675455250b91f125d52f5d347c2c0fbf" id="r_ga675455250b91f125d52f5d347c2c0fbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga675455250b91f125d52f5d347c2c0fbf">RCC_CSR_LPWRRSTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b42e835fb77d45779cdf4d22a0ea22a">RCC_CSR_LPWRRSTF_Msk</a></td></tr>
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<tr class="memitem:gaf600bc53fc80265347f6c76c6b8b728a" id="r_gaf600bc53fc80265347f6c76c6b8b728a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf600bc53fc80265347f6c76c6b8b728a">RCC_CSR_PADRSTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e26d2902d11e638cd0b702332f53ab1">RCC_CSR_PINRSTF</a></td></tr>
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<tr class="memitem:ga1507e79ffc475547f2a9c9238965b57f" id="r_ga1507e79ffc475547f2a9c9238965b57f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1507e79ffc475547f2a9c9238965b57f">RCC_CSR_WDGRSTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga22a7079ba87dd7acd5ed7fe7b704e85f">RCC_CSR_IWDGRSTF</a></td></tr>
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<tr class="separator:ga1507e79ffc475547f2a9c9238965b57f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76dd9dc93a74d66a6cb8241d11fb2bf5" id="r_ga76dd9dc93a74d66a6cb8241d11fb2bf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76dd9dc93a74d66a6cb8241d11fb2bf5">RCC_SSCGR_MODPER_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga76dd9dc93a74d66a6cb8241d11fb2bf5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4446b54ba7ada897a42e3311b946182" id="r_gaa4446b54ba7ada897a42e3311b946182"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4446b54ba7ada897a42e3311b946182">RCC_SSCGR_MODPER_Msk</a>   (0x1FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga76dd9dc93a74d66a6cb8241d11fb2bf5">RCC_SSCGR_MODPER_Pos</a>)</td></tr>
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<tr class="memitem:gaf6fd9fde5cf03700de4c304b9c5dfb7c" id="r_gaf6fd9fde5cf03700de4c304b9c5dfb7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6fd9fde5cf03700de4c304b9c5dfb7c">RCC_SSCGR_MODPER</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4446b54ba7ada897a42e3311b946182">RCC_SSCGR_MODPER_Msk</a></td></tr>
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<tr class="separator:gaf6fd9fde5cf03700de4c304b9c5dfb7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0dee22588439c5aa7bc9ee69cb89cce9" id="r_ga0dee22588439c5aa7bc9ee69cb89cce9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dee22588439c5aa7bc9ee69cb89cce9">RCC_SSCGR_INCSTEP_Pos</a>   (13U)</td></tr>
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<tr class="memitem:gaea77ceb4a2430c2d297ac24a7ad9303d" id="r_gaea77ceb4a2430c2d297ac24a7ad9303d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea77ceb4a2430c2d297ac24a7ad9303d">RCC_SSCGR_INCSTEP_Msk</a>   (0x7FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dee22588439c5aa7bc9ee69cb89cce9">RCC_SSCGR_INCSTEP_Pos</a>)</td></tr>
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<tr class="separator:gaea77ceb4a2430c2d297ac24a7ad9303d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f801e25eb841262467f54e7325b7806" id="r_ga0f801e25eb841262467f54e7325b7806"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f801e25eb841262467f54e7325b7806">RCC_SSCGR_INCSTEP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaea77ceb4a2430c2d297ac24a7ad9303d">RCC_SSCGR_INCSTEP_Msk</a></td></tr>
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<tr class="separator:ga0f801e25eb841262467f54e7325b7806"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25f92667802ad9c8dc1549d65666a03f" id="r_ga25f92667802ad9c8dc1549d65666a03f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25f92667802ad9c8dc1549d65666a03f">RCC_SSCGR_SPREADSEL_Pos</a>   (30U)</td></tr>
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<tr class="memitem:ga0a8dce731d21ecb6c8bcb873023b979b" id="r_ga0a8dce731d21ecb6c8bcb873023b979b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a8dce731d21ecb6c8bcb873023b979b">RCC_SSCGR_SPREADSEL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25f92667802ad9c8dc1549d65666a03f">RCC_SSCGR_SPREADSEL_Pos</a>)</td></tr>
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<tr class="separator:ga0a8dce731d21ecb6c8bcb873023b979b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga392689f6486224a7f19d7ad0cd195687" id="r_ga392689f6486224a7f19d7ad0cd195687"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga392689f6486224a7f19d7ad0cd195687">RCC_SSCGR_SPREADSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a8dce731d21ecb6c8bcb873023b979b">RCC_SSCGR_SPREADSEL_Msk</a></td></tr>
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<tr class="separator:ga392689f6486224a7f19d7ad0cd195687"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae934eed92c2081acbeee062e1932943d" id="r_gae934eed92c2081acbeee062e1932943d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae934eed92c2081acbeee062e1932943d">RCC_SSCGR_SSCGEN_Pos</a>   (31U)</td></tr>
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<tr class="memitem:ga77656e179e5741014ea95703f65a4f99" id="r_ga77656e179e5741014ea95703f65a4f99"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77656e179e5741014ea95703f65a4f99">RCC_SSCGR_SSCGEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae934eed92c2081acbeee062e1932943d">RCC_SSCGR_SSCGEN_Pos</a>)</td></tr>
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<tr class="memitem:ga8885c04bcb786b89e26f066f4ccf06e0" id="r_ga8885c04bcb786b89e26f066f4ccf06e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8885c04bcb786b89e26f066f4ccf06e0">RCC_SSCGR_SSCGEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga77656e179e5741014ea95703f65a4f99">RCC_SSCGR_SSCGEN_Msk</a></td></tr>
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<tr class="separator:ga8885c04bcb786b89e26f066f4ccf06e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3cf5415c0debb40f8932d59677103a2" id="r_gab3cf5415c0debb40f8932d59677103a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>   (6U)</td></tr>
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<tr class="separator:gab3cf5415c0debb40f8932d59677103a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb8781000aaf194d241cee23a637e95e" id="r_gafb8781000aaf194d241cee23a637e95e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb8781000aaf194d241cee23a637e95e">RCC_PLLI2SCFGR_PLLI2SN_Msk</a>   (0x1FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>)</td></tr>
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<tr class="memitem:ga68db5b1d90f9b62359888ed1175a0cef" id="r_ga68db5b1d90f9b62359888ed1175a0cef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68db5b1d90f9b62359888ed1175a0cef">RCC_PLLI2SCFGR_PLLI2SN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb8781000aaf194d241cee23a637e95e">RCC_PLLI2SCFGR_PLLI2SN_Msk</a></td></tr>
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<tr class="separator:ga68db5b1d90f9b62359888ed1175a0cef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee6ea60de76e294b8ba23d229b2c8a1d" id="r_gaee6ea60de76e294b8ba23d229b2c8a1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee6ea60de76e294b8ba23d229b2c8a1d">RCC_PLLI2SCFGR_PLLI2SN_0</a>   (0x001UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>)</td></tr>
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<tr class="separator:gaee6ea60de76e294b8ba23d229b2c8a1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60eec842a298febfaadd7b5f79898b00" id="r_ga60eec842a298febfaadd7b5f79898b00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60eec842a298febfaadd7b5f79898b00">RCC_PLLI2SCFGR_PLLI2SN_1</a>   (0x002UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>)</td></tr>
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<tr class="separator:ga60eec842a298febfaadd7b5f79898b00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2be70f723d8e89b4566a9438a671f49" id="r_gae2be70f723d8e89b4566a9438a671f49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2be70f723d8e89b4566a9438a671f49">RCC_PLLI2SCFGR_PLLI2SN_2</a>   (0x004UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>)</td></tr>
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<tr class="separator:gae2be70f723d8e89b4566a9438a671f49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63743438e947f632c0757a6daf2838af" id="r_ga63743438e947f632c0757a6daf2838af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63743438e947f632c0757a6daf2838af">RCC_PLLI2SCFGR_PLLI2SN_3</a>   (0x008UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>)</td></tr>
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<tr class="separator:ga63743438e947f632c0757a6daf2838af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1f94003cdc00380b298b54c485ca743" id="r_gae1f94003cdc00380b298b54c485ca743"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1f94003cdc00380b298b54c485ca743">RCC_PLLI2SCFGR_PLLI2SN_4</a>   (0x010UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>)</td></tr>
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<tr class="memitem:ga03c368d0e6199b212e7c185663dd2aa8" id="r_ga03c368d0e6199b212e7c185663dd2aa8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03c368d0e6199b212e7c185663dd2aa8">RCC_PLLI2SCFGR_PLLI2SN_5</a>   (0x020UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>)</td></tr>
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<tr class="memitem:ga32d9931c3638779af7042d901a01aabf" id="r_ga32d9931c3638779af7042d901a01aabf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32d9931c3638779af7042d901a01aabf">RCC_PLLI2SCFGR_PLLI2SN_6</a>   (0x040UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>)</td></tr>
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<tr class="memitem:ga8dc32ee35e426332598db98b5e0b230b" id="r_ga8dc32ee35e426332598db98b5e0b230b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8dc32ee35e426332598db98b5e0b230b">RCC_PLLI2SCFGR_PLLI2SN_7</a>   (0x080UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>)</td></tr>
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<tr class="separator:ga8dc32ee35e426332598db98b5e0b230b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ec1c1bad2b7126f36b2ba26e657e84a" id="r_ga9ec1c1bad2b7126f36b2ba26e657e84a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ec1c1bad2b7126f36b2ba26e657e84a">RCC_PLLI2SCFGR_PLLI2SN_8</a>   (0x100UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">RCC_PLLI2SCFGR_PLLI2SN_Pos</a>)</td></tr>
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<tr class="separator:ga9ec1c1bad2b7126f36b2ba26e657e84a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93e7478c8a17f7d07b937e180f8f13f4" id="r_ga93e7478c8a17f7d07b937e180f8f13f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93e7478c8a17f7d07b937e180f8f13f4">RCC_PLLI2SCFGR_PLLI2SR_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga93e7478c8a17f7d07b937e180f8f13f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8ab724070f564a647a4a1ef4e46183e" id="r_gad8ab724070f564a647a4a1ef4e46183e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8ab724070f564a647a4a1ef4e46183e">RCC_PLLI2SCFGR_PLLI2SR_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga93e7478c8a17f7d07b937e180f8f13f4">RCC_PLLI2SCFGR_PLLI2SR_Pos</a>)</td></tr>
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<tr class="memitem:ga0c599fc84dcde859974ed5b334e90f50" id="r_ga0c599fc84dcde859974ed5b334e90f50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c599fc84dcde859974ed5b334e90f50">RCC_PLLI2SCFGR_PLLI2SR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad8ab724070f564a647a4a1ef4e46183e">RCC_PLLI2SCFGR_PLLI2SR_Msk</a></td></tr>
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<tr class="separator:ga0c599fc84dcde859974ed5b334e90f50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2b9c8dc6b0e853ace99e16818d55d12" id="r_gab2b9c8dc6b0e853ace99e16818d55d12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2b9c8dc6b0e853ace99e16818d55d12">RCC_PLLI2SCFGR_PLLI2SR_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga93e7478c8a17f7d07b937e180f8f13f4">RCC_PLLI2SCFGR_PLLI2SR_Pos</a>)</td></tr>
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<tr class="separator:gab2b9c8dc6b0e853ace99e16818d55d12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb49236fe3c41edb56f8ffb8ab505d86" id="r_gabb49236fe3c41edb56f8ffb8ab505d86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb49236fe3c41edb56f8ffb8ab505d86">RCC_PLLI2SCFGR_PLLI2SR_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga93e7478c8a17f7d07b937e180f8f13f4">RCC_PLLI2SCFGR_PLLI2SR_Pos</a>)</td></tr>
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<tr class="separator:gabb49236fe3c41edb56f8ffb8ab505d86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03e58dd5ac710e271fc6ca9113b7e846" id="r_ga03e58dd5ac710e271fc6ca9113b7e846"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03e58dd5ac710e271fc6ca9113b7e846">RCC_PLLI2SCFGR_PLLI2SR_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga93e7478c8a17f7d07b937e180f8f13f4">RCC_PLLI2SCFGR_PLLI2SR_Pos</a>)</td></tr>
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<tr class="separator:ga03e58dd5ac710e271fc6ca9113b7e846"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2013ef5a17240897df5b7bf00b7b290" id="r_gaf2013ef5a17240897df5b7bf00b7b290"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2013ef5a17240897df5b7bf00b7b290">RNG_CR_RNGEN_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaf2013ef5a17240897df5b7bf00b7b290"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeee66d4dd5c33fa16a98b001dd63bd73" id="r_gaeee66d4dd5c33fa16a98b001dd63bd73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeee66d4dd5c33fa16a98b001dd63bd73">RNG_CR_RNGEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2013ef5a17240897df5b7bf00b7b290">RNG_CR_RNGEN_Pos</a>)</td></tr>
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<tr class="separator:gaeee66d4dd5c33fa16a98b001dd63bd73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ee81827bb1d78e84e78a74449c8d56a" id="r_ga6ee81827bb1d78e84e78a74449c8d56a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ee81827bb1d78e84e78a74449c8d56a">RNG_CR_RNGEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeee66d4dd5c33fa16a98b001dd63bd73">RNG_CR_RNGEN_Msk</a></td></tr>
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<tr class="separator:ga6ee81827bb1d78e84e78a74449c8d56a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d1a529728903ae8659aa26f869f6537" id="r_ga8d1a529728903ae8659aa26f869f6537"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1a529728903ae8659aa26f869f6537">RNG_CR_IE_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga8d1a529728903ae8659aa26f869f6537"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8253017bd1f0d7652f107266ffb0297b" id="r_ga8253017bd1f0d7652f107266ffb0297b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8253017bd1f0d7652f107266ffb0297b">RNG_CR_IE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1a529728903ae8659aa26f869f6537">RNG_CR_IE_Pos</a>)</td></tr>
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<tr class="separator:ga8253017bd1f0d7652f107266ffb0297b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27424b682bcee7fff22f92a2dbcea57a" id="r_ga27424b682bcee7fff22f92a2dbcea57a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27424b682bcee7fff22f92a2dbcea57a">RNG_CR_IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8253017bd1f0d7652f107266ffb0297b">RNG_CR_IE_Msk</a></td></tr>
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<tr class="separator:ga27424b682bcee7fff22f92a2dbcea57a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17cb7add2587efeea18a208c76d73727" id="r_ga17cb7add2587efeea18a208c76d73727"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17cb7add2587efeea18a208c76d73727">RNG_SR_DRDY_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga17cb7add2587efeea18a208c76d73727"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd19bcfa8894faf2ac5f57d287f00a8b" id="r_gafd19bcfa8894faf2ac5f57d287f00a8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd19bcfa8894faf2ac5f57d287f00a8b">RNG_SR_DRDY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17cb7add2587efeea18a208c76d73727">RNG_SR_DRDY_Pos</a>)</td></tr>
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<tr class="separator:gafd19bcfa8894faf2ac5f57d287f00a8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54434ed74bdb00fd0f13422d3e85a2fc" id="r_ga54434ed74bdb00fd0f13422d3e85a2fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54434ed74bdb00fd0f13422d3e85a2fc">RNG_SR_DRDY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafd19bcfa8894faf2ac5f57d287f00a8b">RNG_SR_DRDY_Msk</a></td></tr>
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<tr class="separator:ga54434ed74bdb00fd0f13422d3e85a2fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga164b5050473dff67a5cd6ca400bb5a89" id="r_ga164b5050473dff67a5cd6ca400bb5a89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga164b5050473dff67a5cd6ca400bb5a89">RNG_SR_CECS_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga164b5050473dff67a5cd6ca400bb5a89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga699d24eb133814c5be46fe6e588cc093" id="r_ga699d24eb133814c5be46fe6e588cc093"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga699d24eb133814c5be46fe6e588cc093">RNG_SR_CECS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga164b5050473dff67a5cd6ca400bb5a89">RNG_SR_CECS_Pos</a>)</td></tr>
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<tr class="separator:ga699d24eb133814c5be46fe6e588cc093"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bb49d327474c3c61877bb20290f51d0" id="r_ga4bb49d327474c3c61877bb20290f51d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bb49d327474c3c61877bb20290f51d0">RNG_SR_CECS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga699d24eb133814c5be46fe6e588cc093">RNG_SR_CECS_Msk</a></td></tr>
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<tr class="separator:ga4bb49d327474c3c61877bb20290f51d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51e0238194c400f9c6ac0b34826e55eb" id="r_ga51e0238194c400f9c6ac0b34826e55eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51e0238194c400f9c6ac0b34826e55eb">RNG_SR_SECS_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga51e0238194c400f9c6ac0b34826e55eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a312837097b7b3c2528e17a2cfc5f7d" id="r_ga8a312837097b7b3c2528e17a2cfc5f7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a312837097b7b3c2528e17a2cfc5f7d">RNG_SR_SECS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga51e0238194c400f9c6ac0b34826e55eb">RNG_SR_SECS_Pos</a>)</td></tr>
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<tr class="separator:ga8a312837097b7b3c2528e17a2cfc5f7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5562bc13afe295893dc3997a4917fee2" id="r_ga5562bc13afe295893dc3997a4917fee2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5562bc13afe295893dc3997a4917fee2">RNG_SR_SECS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a312837097b7b3c2528e17a2cfc5f7d">RNG_SR_SECS_Msk</a></td></tr>
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<tr class="separator:ga5562bc13afe295893dc3997a4917fee2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga341c152f61c352b96fb0c3c245e3d958" id="r_ga341c152f61c352b96fb0c3c245e3d958"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga341c152f61c352b96fb0c3c245e3d958">RNG_SR_CEIS_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga341c152f61c352b96fb0c3c245e3d958"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3efcca0c0381982a8044d09aaa6b6df9" id="r_ga3efcca0c0381982a8044d09aaa6b6df9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3efcca0c0381982a8044d09aaa6b6df9">RNG_SR_CEIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga341c152f61c352b96fb0c3c245e3d958">RNG_SR_CEIS_Pos</a>)</td></tr>
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<tr class="separator:ga3efcca0c0381982a8044d09aaa6b6df9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b89a08bcc8a7a6078bd9f5f2f34bb53" id="r_ga3b89a08bcc8a7a6078bd9f5f2f34bb53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b89a08bcc8a7a6078bd9f5f2f34bb53">RNG_SR_CEIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3efcca0c0381982a8044d09aaa6b6df9">RNG_SR_CEIS_Msk</a></td></tr>
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<tr class="separator:ga3b89a08bcc8a7a6078bd9f5f2f34bb53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaecf22f4de968dc9aa29d55760ebdb980" id="r_gaecf22f4de968dc9aa29d55760ebdb980"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecf22f4de968dc9aa29d55760ebdb980">RNG_SR_SEIS_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaecf22f4de968dc9aa29d55760ebdb980"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d78e80e064c7746b98ed89304aab367" id="r_ga1d78e80e064c7746b98ed89304aab367"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d78e80e064c7746b98ed89304aab367">RNG_SR_SEIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaecf22f4de968dc9aa29d55760ebdb980">RNG_SR_SEIS_Pos</a>)</td></tr>
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<tr class="separator:ga1d78e80e064c7746b98ed89304aab367"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6b0e11930f20484f0d0aca79959d9b2" id="r_gaa6b0e11930f20484f0d0aca79959d9b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6b0e11930f20484f0d0aca79959d9b2">RNG_SR_SEIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d78e80e064c7746b98ed89304aab367">RNG_SR_SEIS_Msk</a></td></tr>
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<tr class="separator:gaa6b0e11930f20484f0d0aca79959d9b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c33bacdb5372bad482df029d77a9e5e" id="r_ga8c33bacdb5372bad482df029d77a9e5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c33bacdb5372bad482df029d77a9e5e">RTC_TAMPER2_SUPPORT</a></td></tr>
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<tr class="separator:ga8c33bacdb5372bad482df029d77a9e5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b082d5bb4b8d9801fc7370e813b1b3c" id="r_ga8b082d5bb4b8d9801fc7370e813b1b3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b082d5bb4b8d9801fc7370e813b1b3c">RTC_AF2_SUPPORT</a></td></tr>
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<tr class="separator:ga8b082d5bb4b8d9801fc7370e813b1b3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2920dc4e941e569491e856c74f655a73" id="r_ga2920dc4e941e569491e856c74f655a73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2920dc4e941e569491e856c74f655a73">RTC_TR_PM_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga2920dc4e941e569491e856c74f655a73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa98be62b42b64aa8dee5df4f84ec1679" id="r_gaa98be62b42b64aa8dee5df4f84ec1679"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa98be62b42b64aa8dee5df4f84ec1679">RTC_TR_PM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2920dc4e941e569491e856c74f655a73">RTC_TR_PM_Pos</a>)</td></tr>
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<tr class="separator:gaa98be62b42b64aa8dee5df4f84ec1679"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3152952ac385ee1ce8dd868978d3fce9" id="r_ga3152952ac385ee1ce8dd868978d3fce9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3152952ac385ee1ce8dd868978d3fce9">RTC_TR_PM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa98be62b42b64aa8dee5df4f84ec1679">RTC_TR_PM_Msk</a></td></tr>
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<tr class="separator:ga3152952ac385ee1ce8dd868978d3fce9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26458edfa3da49a421547e540b7fef0c" id="r_ga26458edfa3da49a421547e540b7fef0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26458edfa3da49a421547e540b7fef0c">RTC_TR_HT_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga26458edfa3da49a421547e540b7fef0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3f00fc20610b447daa4b2fcf4730e94" id="r_gab3f00fc20610b447daa4b2fcf4730e94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3f00fc20610b447daa4b2fcf4730e94">RTC_TR_HT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga26458edfa3da49a421547e540b7fef0c">RTC_TR_HT_Pos</a>)</td></tr>
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<tr class="separator:gab3f00fc20610b447daa4b2fcf4730e94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad42435e015e9f5052245c366ae08d655" id="r_gad42435e015e9f5052245c366ae08d655"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad42435e015e9f5052245c366ae08d655">RTC_TR_HT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab3f00fc20610b447daa4b2fcf4730e94">RTC_TR_HT_Msk</a></td></tr>
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<tr class="memitem:ga1c9af54381689d893ba1b11eb33cd866" id="r_ga1c9af54381689d893ba1b11eb33cd866"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c9af54381689d893ba1b11eb33cd866">RTC_TR_HT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga26458edfa3da49a421547e540b7fef0c">RTC_TR_HT_Pos</a>)</td></tr>
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<tr class="memitem:ga7b3ba2cc471b86d041df3c2a1a9ef121" id="r_ga7b3ba2cc471b86d041df3c2a1a9ef121"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b3ba2cc471b86d041df3c2a1a9ef121">RTC_TR_HT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga26458edfa3da49a421547e540b7fef0c">RTC_TR_HT_Pos</a>)</td></tr>
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<tr class="separator:ga7b3ba2cc471b86d041df3c2a1a9ef121"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1412e72836e362ccfe5a927b7760fd14" id="r_ga1412e72836e362ccfe5a927b7760fd14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1412e72836e362ccfe5a927b7760fd14">RTC_TR_HU_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga4be6ca68f00b9467ddad84d37f1b6a63" id="r_ga4be6ca68f00b9467ddad84d37f1b6a63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4be6ca68f00b9467ddad84d37f1b6a63">RTC_TR_HU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1412e72836e362ccfe5a927b7760fd14">RTC_TR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga4be6ca68f00b9467ddad84d37f1b6a63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8211df481853649722383e0d8fb06d5" id="r_gac8211df481853649722383e0d8fb06d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8211df481853649722383e0d8fb06d5">RTC_TR_HU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4be6ca68f00b9467ddad84d37f1b6a63">RTC_TR_HU_Msk</a></td></tr>
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<tr class="memitem:gaddad920d5681960fa702b988ef1f82be" id="r_gaddad920d5681960fa702b988ef1f82be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddad920d5681960fa702b988ef1f82be">RTC_TR_HU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1412e72836e362ccfe5a927b7760fd14">RTC_TR_HU_Pos</a>)</td></tr>
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<tr class="separator:gaddad920d5681960fa702b988ef1f82be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6206d385d3b3e127b1e63be48f83a63" id="r_gae6206d385d3b3e127b1e63be48f83a63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6206d385d3b3e127b1e63be48f83a63">RTC_TR_HU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1412e72836e362ccfe5a927b7760fd14">RTC_TR_HU_Pos</a>)</td></tr>
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<tr class="separator:gae6206d385d3b3e127b1e63be48f83a63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e264504542ec2d9b06036e938f7f79d" id="r_ga6e264504542ec2d9b06036e938f7f79d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e264504542ec2d9b06036e938f7f79d">RTC_TR_HU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1412e72836e362ccfe5a927b7760fd14">RTC_TR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga6e264504542ec2d9b06036e938f7f79d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40763d3ed48e9f707784bdfd65a9c3ca" id="r_ga40763d3ed48e9f707784bdfd65a9c3ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40763d3ed48e9f707784bdfd65a9c3ca">RTC_TR_HU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1412e72836e362ccfe5a927b7760fd14">RTC_TR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga40763d3ed48e9f707784bdfd65a9c3ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf169c6a3845063073e546f372e90a61a" id="r_gaf169c6a3845063073e546f372e90a61a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf169c6a3845063073e546f372e90a61a">RTC_TR_MNT_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaf169c6a3845063073e546f372e90a61a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87978332f15306d7db05c3bce2df2c7f" id="r_ga87978332f15306d7db05c3bce2df2c7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87978332f15306d7db05c3bce2df2c7f">RTC_TR_MNT_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf169c6a3845063073e546f372e90a61a">RTC_TR_MNT_Pos</a>)</td></tr>
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<tr class="separator:ga87978332f15306d7db05c3bce2df2c7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64cf91576871a8108d6ee2f48970bb4a" id="r_ga64cf91576871a8108d6ee2f48970bb4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64cf91576871a8108d6ee2f48970bb4a">RTC_TR_MNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga87978332f15306d7db05c3bce2df2c7f">RTC_TR_MNT_Msk</a></td></tr>
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<tr class="separator:ga64cf91576871a8108d6ee2f48970bb4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga752747aa90bf35bd57b16bffc7294dfc" id="r_ga752747aa90bf35bd57b16bffc7294dfc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga752747aa90bf35bd57b16bffc7294dfc">RTC_TR_MNT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf169c6a3845063073e546f372e90a61a">RTC_TR_MNT_Pos</a>)</td></tr>
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<tr class="separator:ga752747aa90bf35bd57b16bffc7294dfc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1837f65a11192dd9b8bf249c31ccef7" id="r_gaa1837f65a11192dd9b8bf249c31ccef7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1837f65a11192dd9b8bf249c31ccef7">RTC_TR_MNT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf169c6a3845063073e546f372e90a61a">RTC_TR_MNT_Pos</a>)</td></tr>
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<tr class="separator:gaa1837f65a11192dd9b8bf249c31ccef7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f27fb43718df0797664acd2d9c95c1a" id="r_ga5f27fb43718df0797664acd2d9c95c1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f27fb43718df0797664acd2d9c95c1a">RTC_TR_MNT_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf169c6a3845063073e546f372e90a61a">RTC_TR_MNT_Pos</a>)</td></tr>
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<tr class="separator:ga5f27fb43718df0797664acd2d9c95c1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5d682cf0198141f2a323981ec266173" id="r_gab5d682cf0198141f2a323981ec266173"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5d682cf0198141f2a323981ec266173">RTC_TR_MNU_Pos</a>   (8U)</td></tr>
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<tr class="separator:gab5d682cf0198141f2a323981ec266173"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8240cd693ae8c3bf069e10ab08f3adcd" id="r_ga8240cd693ae8c3bf069e10ab08f3adcd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8240cd693ae8c3bf069e10ab08f3adcd">RTC_TR_MNU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5d682cf0198141f2a323981ec266173">RTC_TR_MNU_Pos</a>)</td></tr>
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<tr class="separator:ga8240cd693ae8c3bf069e10ab08f3adcd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84e86f4fc04232fd0294966434708e06" id="r_ga84e86f4fc04232fd0294966434708e06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84e86f4fc04232fd0294966434708e06">RTC_TR_MNU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8240cd693ae8c3bf069e10ab08f3adcd">RTC_TR_MNU_Msk</a></td></tr>
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<tr class="memitem:gad91d7700822050a352e53aff372a697b" id="r_gad91d7700822050a352e53aff372a697b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad91d7700822050a352e53aff372a697b">RTC_TR_MNU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5d682cf0198141f2a323981ec266173">RTC_TR_MNU_Pos</a>)</td></tr>
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<tr class="memitem:gad9c3087e3d4cd490af8334e99467f1dc" id="r_gad9c3087e3d4cd490af8334e99467f1dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9c3087e3d4cd490af8334e99467f1dc">RTC_TR_MNU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5d682cf0198141f2a323981ec266173">RTC_TR_MNU_Pos</a>)</td></tr>
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<tr class="separator:gad9c3087e3d4cd490af8334e99467f1dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac01a9e4b358ea062bf1c66069a28c126" id="r_gac01a9e4b358ea062bf1c66069a28c126"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac01a9e4b358ea062bf1c66069a28c126">RTC_TR_MNU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5d682cf0198141f2a323981ec266173">RTC_TR_MNU_Pos</a>)</td></tr>
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<tr class="separator:gac01a9e4b358ea062bf1c66069a28c126"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75b76249e63af249061c0c5532a2a4e5" id="r_ga75b76249e63af249061c0c5532a2a4e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75b76249e63af249061c0c5532a2a4e5">RTC_TR_MNU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5d682cf0198141f2a323981ec266173">RTC_TR_MNU_Pos</a>)</td></tr>
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<tr class="separator:ga75b76249e63af249061c0c5532a2a4e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga641ca04f0ccdab58ac9fe27211719a66" id="r_ga641ca04f0ccdab58ac9fe27211719a66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga641ca04f0ccdab58ac9fe27211719a66">RTC_TR_ST_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga641ca04f0ccdab58ac9fe27211719a66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3ae841c3e4f90face971c95f1228419" id="r_gaf3ae841c3e4f90face971c95f1228419"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3ae841c3e4f90face971c95f1228419">RTC_TR_ST_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga641ca04f0ccdab58ac9fe27211719a66">RTC_TR_ST_Pos</a>)</td></tr>
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<tr class="separator:gaf3ae841c3e4f90face971c95f1228419"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae39b22025a36d1e4e185e4be2bf326f" id="r_gaae39b22025a36d1e4e185e4be2bf326f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae39b22025a36d1e4e185e4be2bf326f">RTC_TR_ST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3ae841c3e4f90face971c95f1228419">RTC_TR_ST_Msk</a></td></tr>
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<tr class="separator:gaae39b22025a36d1e4e185e4be2bf326f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0a53dc60816e0790ba69eaff3e87cb0" id="r_gaf0a53dc60816e0790ba69eaff3e87cb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0a53dc60816e0790ba69eaff3e87cb0">RTC_TR_ST_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga641ca04f0ccdab58ac9fe27211719a66">RTC_TR_ST_Pos</a>)</td></tr>
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<tr class="separator:gaf0a53dc60816e0790ba69eaff3e87cb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga948beb7166b70f1fa9e9148a8b6bd3f9" id="r_ga948beb7166b70f1fa9e9148a8b6bd3f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga948beb7166b70f1fa9e9148a8b6bd3f9">RTC_TR_ST_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga641ca04f0ccdab58ac9fe27211719a66">RTC_TR_ST_Pos</a>)</td></tr>
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<tr class="separator:ga948beb7166b70f1fa9e9148a8b6bd3f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d5f0413990c26a5cf9a857d10243e9b" id="r_ga4d5f0413990c26a5cf9a857d10243e9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d5f0413990c26a5cf9a857d10243e9b">RTC_TR_ST_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga641ca04f0ccdab58ac9fe27211719a66">RTC_TR_ST_Pos</a>)</td></tr>
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<tr class="separator:ga4d5f0413990c26a5cf9a857d10243e9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a5251e75005627144d7a044045484ca" id="r_ga2a5251e75005627144d7a044045484ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5251e75005627144d7a044045484ca">RTC_TR_SU_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2a5251e75005627144d7a044045484ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac65138b7d68cf4db6e391a5e3d31d4a5" id="r_gac65138b7d68cf4db6e391a5e3d31d4a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac65138b7d68cf4db6e391a5e3d31d4a5">RTC_TR_SU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5251e75005627144d7a044045484ca">RTC_TR_SU_Pos</a>)</td></tr>
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<tr class="separator:gac65138b7d68cf4db6e391a5e3d31d4a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga747711823db36121b78c0eebb6140ca1" id="r_ga747711823db36121b78c0eebb6140ca1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga747711823db36121b78c0eebb6140ca1">RTC_TR_SU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac65138b7d68cf4db6e391a5e3d31d4a5">RTC_TR_SU_Msk</a></td></tr>
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<tr class="memitem:ga4132b0e9d72ff72df7e0062a1e081ca3" id="r_ga4132b0e9d72ff72df7e0062a1e081ca3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4132b0e9d72ff72df7e0062a1e081ca3">RTC_TR_SU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5251e75005627144d7a044045484ca">RTC_TR_SU_Pos</a>)</td></tr>
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<tr class="separator:ga4132b0e9d72ff72df7e0062a1e081ca3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6eef03c1de3719d801c970eec53e7500" id="r_ga6eef03c1de3719d801c970eec53e7500"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6eef03c1de3719d801c970eec53e7500">RTC_TR_SU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5251e75005627144d7a044045484ca">RTC_TR_SU_Pos</a>)</td></tr>
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<tr class="memitem:gabbe7e738c8adaaf24f6faca467d6fde2" id="r_gabbe7e738c8adaaf24f6faca467d6fde2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbe7e738c8adaaf24f6faca467d6fde2">RTC_TR_SU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5251e75005627144d7a044045484ca">RTC_TR_SU_Pos</a>)</td></tr>
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<tr class="memitem:gab44e19720b6691f63ba4f0c38a1fd7f3" id="r_gab44e19720b6691f63ba4f0c38a1fd7f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab44e19720b6691f63ba4f0c38a1fd7f3">RTC_TR_SU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5251e75005627144d7a044045484ca">RTC_TR_SU_Pos</a>)</td></tr>
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<tr class="memitem:gaee7ed9c50764bdf02c200c9acf963609" id="r_gaee7ed9c50764bdf02c200c9acf963609"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee7ed9c50764bdf02c200c9acf963609">RTC_DR_YT_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga0ad13d2dbed87fd51194b4d7b080f759" id="r_ga0ad13d2dbed87fd51194b4d7b080f759"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ad13d2dbed87fd51194b4d7b080f759">RTC_DR_YT_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee7ed9c50764bdf02c200c9acf963609">RTC_DR_YT_Pos</a>)</td></tr>
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<tr class="memitem:ga14d55b6d841825ec65736e08c09b1d83" id="r_ga14d55b6d841825ec65736e08c09b1d83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14d55b6d841825ec65736e08c09b1d83">RTC_DR_YT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ad13d2dbed87fd51194b4d7b080f759">RTC_DR_YT_Msk</a></td></tr>
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<tr class="separator:ga14d55b6d841825ec65736e08c09b1d83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a733698a85cc8f26d346ec8c61c7937" id="r_ga4a733698a85cc8f26d346ec8c61c7937"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a733698a85cc8f26d346ec8c61c7937">RTC_DR_YT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee7ed9c50764bdf02c200c9acf963609">RTC_DR_YT_Pos</a>)</td></tr>
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<tr class="separator:ga4a733698a85cc8f26d346ec8c61c7937"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa48c7c9f31a74b6d3b04443ce0414ce9" id="r_gaa48c7c9f31a74b6d3b04443ce0414ce9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa48c7c9f31a74b6d3b04443ce0414ce9">RTC_DR_YT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee7ed9c50764bdf02c200c9acf963609">RTC_DR_YT_Pos</a>)</td></tr>
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<tr class="separator:gaa48c7c9f31a74b6d3b04443ce0414ce9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c15cd22daf2ef6f9ea6f7341897a435" id="r_ga5c15cd22daf2ef6f9ea6f7341897a435"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c15cd22daf2ef6f9ea6f7341897a435">RTC_DR_YT_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee7ed9c50764bdf02c200c9acf963609">RTC_DR_YT_Pos</a>)</td></tr>
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<tr class="separator:ga5c15cd22daf2ef6f9ea6f7341897a435"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e7cf7875d489f89d949178e0294d555" id="r_ga4e7cf7875d489f89d949178e0294d555"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e7cf7875d489f89d949178e0294d555">RTC_DR_YT_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee7ed9c50764bdf02c200c9acf963609">RTC_DR_YT_Pos</a>)</td></tr>
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<tr class="separator:ga4e7cf7875d489f89d949178e0294d555"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2a117731b1eddef15cf9fa4f3c7a062" id="r_gaf2a117731b1eddef15cf9fa4f3c7a062"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2a117731b1eddef15cf9fa4f3c7a062">RTC_DR_YU_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga261de093e10c99df510d650bea7b65bb" id="r_ga261de093e10c99df510d650bea7b65bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga261de093e10c99df510d650bea7b65bb">RTC_DR_YU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2a117731b1eddef15cf9fa4f3c7a062">RTC_DR_YU_Pos</a>)</td></tr>
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<tr class="memitem:gafd1bdc8fad3fdeb14058c9158f39ae9e" id="r_gafd1bdc8fad3fdeb14058c9158f39ae9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd1bdc8fad3fdeb14058c9158f39ae9e">RTC_DR_YU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga261de093e10c99df510d650bea7b65bb">RTC_DR_YU_Msk</a></td></tr>
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<tr class="separator:gafd1bdc8fad3fdeb14058c9158f39ae9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeda03e9857e9009b6212df5f97a5d09f" id="r_gaeda03e9857e9009b6212df5f97a5d09f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeda03e9857e9009b6212df5f97a5d09f">RTC_DR_YU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2a117731b1eddef15cf9fa4f3c7a062">RTC_DR_YU_Pos</a>)</td></tr>
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<tr class="separator:gaeda03e9857e9009b6212df5f97a5d09f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb0b5f7684e31cb1665a848b91601249" id="r_gadb0b5f7684e31cb1665a848b91601249"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb0b5f7684e31cb1665a848b91601249">RTC_DR_YU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2a117731b1eddef15cf9fa4f3c7a062">RTC_DR_YU_Pos</a>)</td></tr>
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<tr class="separator:gadb0b5f7684e31cb1665a848b91601249"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01f200469dbc8159adc3b4f25375b601" id="r_ga01f200469dbc8159adc3b4f25375b601"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01f200469dbc8159adc3b4f25375b601">RTC_DR_YU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2a117731b1eddef15cf9fa4f3c7a062">RTC_DR_YU_Pos</a>)</td></tr>
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<tr class="separator:ga01f200469dbc8159adc3b4f25375b601"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga592372ccddc93b10e81ed705c9c0f9bc" id="r_ga592372ccddc93b10e81ed705c9c0f9bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga592372ccddc93b10e81ed705c9c0f9bc">RTC_DR_YU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2a117731b1eddef15cf9fa4f3c7a062">RTC_DR_YU_Pos</a>)</td></tr>
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<tr class="separator:ga592372ccddc93b10e81ed705c9c0f9bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga751a29a9ead0d70b6104bd366b7ab6af" id="r_ga751a29a9ead0d70b6104bd366b7ab6af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga751a29a9ead0d70b6104bd366b7ab6af">RTC_DR_WDU_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga751a29a9ead0d70b6104bd366b7ab6af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacaa60c7147ae02cf5d6e2ee2c87fb5e7" id="r_gacaa60c7147ae02cf5d6e2ee2c87fb5e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacaa60c7147ae02cf5d6e2ee2c87fb5e7">RTC_DR_WDU_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga751a29a9ead0d70b6104bd366b7ab6af">RTC_DR_WDU_Pos</a>)</td></tr>
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<tr class="separator:gacaa60c7147ae02cf5d6e2ee2c87fb5e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f46c349f75a31973e094729fe96543f" id="r_ga6f46c349f75a31973e094729fe96543f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f46c349f75a31973e094729fe96543f">RTC_DR_WDU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacaa60c7147ae02cf5d6e2ee2c87fb5e7">RTC_DR_WDU_Msk</a></td></tr>
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<tr class="separator:ga6f46c349f75a31973e094729fe96543f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30cb803b191670a41aea89a91e53fe61" id="r_ga30cb803b191670a41aea89a91e53fe61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30cb803b191670a41aea89a91e53fe61">RTC_DR_WDU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga751a29a9ead0d70b6104bd366b7ab6af">RTC_DR_WDU_Pos</a>)</td></tr>
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<tr class="separator:ga30cb803b191670a41aea89a91e53fe61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd26d3601bf8b119af8f96a65a1de60e" id="r_gabd26d3601bf8b119af8f96a65a1de60e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd26d3601bf8b119af8f96a65a1de60e">RTC_DR_WDU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga751a29a9ead0d70b6104bd366b7ab6af">RTC_DR_WDU_Pos</a>)</td></tr>
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<tr class="separator:gabd26d3601bf8b119af8f96a65a1de60e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77e907e5efced7628e9933e7cfb4cac6" id="r_ga77e907e5efced7628e9933e7cfb4cac6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77e907e5efced7628e9933e7cfb4cac6">RTC_DR_WDU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga751a29a9ead0d70b6104bd366b7ab6af">RTC_DR_WDU_Pos</a>)</td></tr>
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<tr class="separator:ga77e907e5efced7628e9933e7cfb4cac6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d26f621d89bd024ff988b5ecab316ab" id="r_ga1d26f621d89bd024ff988b5ecab316ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d26f621d89bd024ff988b5ecab316ab">RTC_DR_MT_Pos</a>   (12U)</td></tr>
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<tr class="memitem:ga5358d94c842b122b8bd260a855afb483" id="r_ga5358d94c842b122b8bd260a855afb483"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5358d94c842b122b8bd260a855afb483">RTC_DR_MT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d26f621d89bd024ff988b5ecab316ab">RTC_DR_MT_Pos</a>)</td></tr>
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<tr class="separator:ga5358d94c842b122b8bd260a855afb483"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26f0d3ce1c6c6785bd8fbae556f68b31" id="r_ga26f0d3ce1c6c6785bd8fbae556f68b31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26f0d3ce1c6c6785bd8fbae556f68b31">RTC_DR_MT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5358d94c842b122b8bd260a855afb483">RTC_DR_MT_Msk</a></td></tr>
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<tr class="separator:ga26f0d3ce1c6c6785bd8fbae556f68b31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5781bd4d99f08d25b2741a43c0e694a4" id="r_ga5781bd4d99f08d25b2741a43c0e694a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5781bd4d99f08d25b2741a43c0e694a4">RTC_DR_MU_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga5781bd4d99f08d25b2741a43c0e694a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga614964ed52cb7da4ee76a0f3d16e57bb" id="r_ga614964ed52cb7da4ee76a0f3d16e57bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga614964ed52cb7da4ee76a0f3d16e57bb">RTC_DR_MU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5781bd4d99f08d25b2741a43c0e694a4">RTC_DR_MU_Pos</a>)</td></tr>
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<tr class="separator:ga614964ed52cb7da4ee76a0f3d16e57bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9221f60ccf3581f3c543fdedddf4372" id="r_gac9221f60ccf3581f3c543fdedddf4372"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9221f60ccf3581f3c543fdedddf4372">RTC_DR_MU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga614964ed52cb7da4ee76a0f3d16e57bb">RTC_DR_MU_Msk</a></td></tr>
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<tr class="separator:gac9221f60ccf3581f3c543fdedddf4372"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54f64678df9fe08a2afd732c275ae7a0" id="r_ga54f64678df9fe08a2afd732c275ae7a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54f64678df9fe08a2afd732c275ae7a0">RTC_DR_MU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5781bd4d99f08d25b2741a43c0e694a4">RTC_DR_MU_Pos</a>)</td></tr>
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<tr class="separator:ga54f64678df9fe08a2afd732c275ae7a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7845ded502c4cc9faeeb6215955f6f1" id="r_gac7845ded502c4cc9faeeb6215955f6f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7845ded502c4cc9faeeb6215955f6f1">RTC_DR_MU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5781bd4d99f08d25b2741a43c0e694a4">RTC_DR_MU_Pos</a>)</td></tr>
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<tr class="separator:gac7845ded502c4cc9faeeb6215955f6f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47a14479cfe6791d300b9a556d158abe" id="r_ga47a14479cfe6791d300b9a556d158abe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47a14479cfe6791d300b9a556d158abe">RTC_DR_MU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5781bd4d99f08d25b2741a43c0e694a4">RTC_DR_MU_Pos</a>)</td></tr>
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<tr class="memitem:ga2a420b221dec229c053295c44bcac1b1" id="r_ga2a420b221dec229c053295c44bcac1b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a420b221dec229c053295c44bcac1b1">RTC_DR_MU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5781bd4d99f08d25b2741a43c0e694a4">RTC_DR_MU_Pos</a>)</td></tr>
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<tr class="memitem:gab12b2bb2b80f5a17c4d6717708cf9d5a" id="r_gab12b2bb2b80f5a17c4d6717708cf9d5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab12b2bb2b80f5a17c4d6717708cf9d5a">RTC_DR_DT_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga47c3834615b1c186a5122c0735e03e09" id="r_ga47c3834615b1c186a5122c0735e03e09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47c3834615b1c186a5122c0735e03e09">RTC_DR_DT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab12b2bb2b80f5a17c4d6717708cf9d5a">RTC_DR_DT_Pos</a>)</td></tr>
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<tr class="memitem:ga52e40cec8161ee20176d92d547fef350" id="r_ga52e40cec8161ee20176d92d547fef350"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52e40cec8161ee20176d92d547fef350">RTC_DR_DT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47c3834615b1c186a5122c0735e03e09">RTC_DR_DT_Msk</a></td></tr>
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<tr class="memitem:ga8823ee9be7a191912aeef8252517b8a6" id="r_ga8823ee9be7a191912aeef8252517b8a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8823ee9be7a191912aeef8252517b8a6">RTC_DR_DT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab12b2bb2b80f5a17c4d6717708cf9d5a">RTC_DR_DT_Pos</a>)</td></tr>
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<tr class="memitem:ga546b218e45c1297e39a586204268cf9d" id="r_ga546b218e45c1297e39a586204268cf9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga546b218e45c1297e39a586204268cf9d">RTC_DR_DT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab12b2bb2b80f5a17c4d6717708cf9d5a">RTC_DR_DT_Pos</a>)</td></tr>
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<tr class="separator:ga546b218e45c1297e39a586204268cf9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4689a554a699f3df0a5939efdbebb94d" id="r_ga4689a554a699f3df0a5939efdbebb94d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4689a554a699f3df0a5939efdbebb94d">RTC_DR_DU_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4689a554a699f3df0a5939efdbebb94d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4549c0127eff71ac5e1e3b7ef07bf158" id="r_ga4549c0127eff71ac5e1e3b7ef07bf158"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4549c0127eff71ac5e1e3b7ef07bf158">RTC_DR_DU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4689a554a699f3df0a5939efdbebb94d">RTC_DR_DU_Pos</a>)</td></tr>
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<tr class="separator:ga4549c0127eff71ac5e1e3b7ef07bf158"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba04cbc99cf442c7e6155bef625c5663" id="r_gaba04cbc99cf442c7e6155bef625c5663"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba04cbc99cf442c7e6155bef625c5663">RTC_DR_DU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4549c0127eff71ac5e1e3b7ef07bf158">RTC_DR_DU_Msk</a></td></tr>
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<tr class="memitem:ga0ffd9b610a0ba3f1caad707ff2fb0a3f" id="r_ga0ffd9b610a0ba3f1caad707ff2fb0a3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ffd9b610a0ba3f1caad707ff2fb0a3f">RTC_DR_DU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4689a554a699f3df0a5939efdbebb94d">RTC_DR_DU_Pos</a>)</td></tr>
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<tr class="separator:ga0ffd9b610a0ba3f1caad707ff2fb0a3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79b5d9f674be2ecf85c964da6ac0a2a4" id="r_ga79b5d9f674be2ecf85c964da6ac0a2a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79b5d9f674be2ecf85c964da6ac0a2a4">RTC_DR_DU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4689a554a699f3df0a5939efdbebb94d">RTC_DR_DU_Pos</a>)</td></tr>
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<tr class="memitem:ga1668f84ec4ddec10f6bcff65983df05b" id="r_ga1668f84ec4ddec10f6bcff65983df05b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1668f84ec4ddec10f6bcff65983df05b">RTC_DR_DU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4689a554a699f3df0a5939efdbebb94d">RTC_DR_DU_Pos</a>)</td></tr>
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<tr class="memitem:gad54e249241aebdda778618f35dce9f66" id="r_gad54e249241aebdda778618f35dce9f66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad54e249241aebdda778618f35dce9f66">RTC_DR_DU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4689a554a699f3df0a5939efdbebb94d">RTC_DR_DU_Pos</a>)</td></tr>
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<tr class="separator:gad54e249241aebdda778618f35dce9f66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga12e2706cb9754f06d60cb87d3ec364ac" id="r_ga12e2706cb9754f06d60cb87d3ec364ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12e2706cb9754f06d60cb87d3ec364ac">RTC_CR_COE_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga12e2706cb9754f06d60cb87d3ec364ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35471924ed2a9a83b6af8bd8e2251f8b" id="r_ga35471924ed2a9a83b6af8bd8e2251f8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35471924ed2a9a83b6af8bd8e2251f8b">RTC_CR_COE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga12e2706cb9754f06d60cb87d3ec364ac">RTC_CR_COE_Pos</a>)</td></tr>
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<tr class="separator:ga35471924ed2a9a83b6af8bd8e2251f8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cdfa862acfa6068b7ba847f77269d60" id="r_ga3cdfa862acfa6068b7ba847f77269d60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cdfa862acfa6068b7ba847f77269d60">RTC_CR_COE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga35471924ed2a9a83b6af8bd8e2251f8b">RTC_CR_COE_Msk</a></td></tr>
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<tr class="separator:ga3cdfa862acfa6068b7ba847f77269d60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6513acc17cb4c17769ed5dcd03ebde8c" id="r_ga6513acc17cb4c17769ed5dcd03ebde8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6513acc17cb4c17769ed5dcd03ebde8c">RTC_CR_OSEL_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga6513acc17cb4c17769ed5dcd03ebde8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb684c910bd8e726378e0b51732f952f" id="r_gaeb684c910bd8e726378e0b51732f952f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb684c910bd8e726378e0b51732f952f">RTC_CR_OSEL_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6513acc17cb4c17769ed5dcd03ebde8c">RTC_CR_OSEL_Pos</a>)</td></tr>
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<tr class="separator:gaeb684c910bd8e726378e0b51732f952f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f81115ef3fd366de73e84ab667d369b" id="r_ga8f81115ef3fd366de73e84ab667d369b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f81115ef3fd366de73e84ab667d369b">RTC_CR_OSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb684c910bd8e726378e0b51732f952f">RTC_CR_OSEL_Msk</a></td></tr>
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<tr class="separator:ga8f81115ef3fd366de73e84ab667d369b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe506838823e3b172a9ed4a3fec7321a" id="r_gabe506838823e3b172a9ed4a3fec7321a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe506838823e3b172a9ed4a3fec7321a">RTC_CR_OSEL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6513acc17cb4c17769ed5dcd03ebde8c">RTC_CR_OSEL_Pos</a>)</td></tr>
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<tr class="separator:gabe506838823e3b172a9ed4a3fec7321a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15fb33aaad62c71bbba2f96652eefb8c" id="r_ga15fb33aaad62c71bbba2f96652eefb8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15fb33aaad62c71bbba2f96652eefb8c">RTC_CR_OSEL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6513acc17cb4c17769ed5dcd03ebde8c">RTC_CR_OSEL_Pos</a>)</td></tr>
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<tr class="separator:ga15fb33aaad62c71bbba2f96652eefb8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga013304c1d6002a7c9ec57de637def511" id="r_ga013304c1d6002a7c9ec57de637def511"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga013304c1d6002a7c9ec57de637def511">RTC_CR_POL_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga013304c1d6002a7c9ec57de637def511"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga717b2d78f96be49ba9d262f3a0eb09e4" id="r_ga717b2d78f96be49ba9d262f3a0eb09e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga717b2d78f96be49ba9d262f3a0eb09e4">RTC_CR_POL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga013304c1d6002a7c9ec57de637def511">RTC_CR_POL_Pos</a>)</td></tr>
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<tr class="separator:ga717b2d78f96be49ba9d262f3a0eb09e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53f21b5adadbcc5eb255683d5decc9cb" id="r_ga53f21b5adadbcc5eb255683d5decc9cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53f21b5adadbcc5eb255683d5decc9cb">RTC_CR_POL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga717b2d78f96be49ba9d262f3a0eb09e4">RTC_CR_POL_Msk</a></td></tr>
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<tr class="separator:ga53f21b5adadbcc5eb255683d5decc9cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3ae962f1f8c748682a3136ea5ab76e1" id="r_gac3ae962f1f8c748682a3136ea5ab76e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3ae962f1f8c748682a3136ea5ab76e1">RTC_CR_COSEL_Pos</a>   (19U)</td></tr>
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<tr class="separator:gac3ae962f1f8c748682a3136ea5ab76e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8dc824636e99382fcd50b39a6fce8dc" id="r_gad8dc824636e99382fcd50b39a6fce8dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8dc824636e99382fcd50b39a6fce8dc">RTC_CR_COSEL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3ae962f1f8c748682a3136ea5ab76e1">RTC_CR_COSEL_Pos</a>)</td></tr>
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<tr class="separator:gad8dc824636e99382fcd50b39a6fce8dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga197c587884b9c1dcb2970e9ec2589b41" id="r_ga197c587884b9c1dcb2970e9ec2589b41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga197c587884b9c1dcb2970e9ec2589b41">RTC_CR_COSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad8dc824636e99382fcd50b39a6fce8dc">RTC_CR_COSEL_Msk</a></td></tr>
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<tr class="separator:ga197c587884b9c1dcb2970e9ec2589b41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd9f44a96fafedd6c89600a0a14fe87f" id="r_gafd9f44a96fafedd6c89600a0a14fe87f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd9f44a96fafedd6c89600a0a14fe87f">RTC_CR_BKP_Pos</a>   (18U)</td></tr>
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<tr class="separator:gafd9f44a96fafedd6c89600a0a14fe87f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3675c7d64de46ab9f1cf279d7abaffe2" id="r_ga3675c7d64de46ab9f1cf279d7abaffe2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3675c7d64de46ab9f1cf279d7abaffe2">RTC_CR_BKP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafd9f44a96fafedd6c89600a0a14fe87f">RTC_CR_BKP_Pos</a>)</td></tr>
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<tr class="separator:ga3675c7d64de46ab9f1cf279d7abaffe2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e7a474de1a01816bc9d9b6fa7272289" id="r_ga0e7a474de1a01816bc9d9b6fa7272289"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e7a474de1a01816bc9d9b6fa7272289">RTC_CR_BKP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3675c7d64de46ab9f1cf279d7abaffe2">RTC_CR_BKP_Msk</a></td></tr>
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<tr class="separator:ga0e7a474de1a01816bc9d9b6fa7272289"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7614f35a94291525f1dd8cc8f41f960f" id="r_ga7614f35a94291525f1dd8cc8f41f960f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7614f35a94291525f1dd8cc8f41f960f">RTC_CR_SUB1H_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga7614f35a94291525f1dd8cc8f41f960f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62402c843252c70670b4b6c9ffec5880" id="r_ga62402c843252c70670b4b6c9ffec5880"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62402c843252c70670b4b6c9ffec5880">RTC_CR_SUB1H_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7614f35a94291525f1dd8cc8f41f960f">RTC_CR_SUB1H_Pos</a>)</td></tr>
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<tr class="separator:ga62402c843252c70670b4b6c9ffec5880"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga220cf6237eac208acc8ae4c55e0b5e6f" id="r_ga220cf6237eac208acc8ae4c55e0b5e6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga220cf6237eac208acc8ae4c55e0b5e6f">RTC_CR_SUB1H</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga62402c843252c70670b4b6c9ffec5880">RTC_CR_SUB1H_Msk</a></td></tr>
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<tr class="separator:ga220cf6237eac208acc8ae4c55e0b5e6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab04a33865dc30af95c633750711fc6d0" id="r_gab04a33865dc30af95c633750711fc6d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab04a33865dc30af95c633750711fc6d0">RTC_CR_ADD1H_Pos</a>   (16U)</td></tr>
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<tr class="separator:gab04a33865dc30af95c633750711fc6d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01aac32ee74fbafd54de75ee53bf1417" id="r_ga01aac32ee74fbafd54de75ee53bf1417"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01aac32ee74fbafd54de75ee53bf1417">RTC_CR_ADD1H_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab04a33865dc30af95c633750711fc6d0">RTC_CR_ADD1H_Pos</a>)</td></tr>
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<tr class="separator:ga01aac32ee74fbafd54de75ee53bf1417"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae1a8439d08e28289398dcf3c2b4b47b" id="r_gaae1a8439d08e28289398dcf3c2b4b47b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae1a8439d08e28289398dcf3c2b4b47b">RTC_CR_ADD1H</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga01aac32ee74fbafd54de75ee53bf1417">RTC_CR_ADD1H_Msk</a></td></tr>
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<tr class="separator:gaae1a8439d08e28289398dcf3c2b4b47b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82db8f745799c761201a13235132a700" id="r_ga82db8f745799c761201a13235132a700"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82db8f745799c761201a13235132a700">RTC_CR_TSIE_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga82db8f745799c761201a13235132a700"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b81fdfb0dbd9719e0eee7b39450bb31" id="r_ga4b81fdfb0dbd9719e0eee7b39450bb31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b81fdfb0dbd9719e0eee7b39450bb31">RTC_CR_TSIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga82db8f745799c761201a13235132a700">RTC_CR_TSIE_Pos</a>)</td></tr>
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<tr class="separator:ga4b81fdfb0dbd9719e0eee7b39450bb31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf376dffb9f2777ef275f23410e35600d" id="r_gaf376dffb9f2777ef275f23410e35600d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf376dffb9f2777ef275f23410e35600d">RTC_CR_TSIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b81fdfb0dbd9719e0eee7b39450bb31">RTC_CR_TSIE_Msk</a></td></tr>
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<tr class="separator:gaf376dffb9f2777ef275f23410e35600d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1432b0a0a031fe1143d153fe3073d7d2" id="r_ga1432b0a0a031fe1143d153fe3073d7d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1432b0a0a031fe1143d153fe3073d7d2">RTC_CR_WUTIE_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga1432b0a0a031fe1143d153fe3073d7d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83d862c5a5e56813b86246d22821ac9b" id="r_ga83d862c5a5e56813b86246d22821ac9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83d862c5a5e56813b86246d22821ac9b">RTC_CR_WUTIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1432b0a0a031fe1143d153fe3073d7d2">RTC_CR_WUTIE_Pos</a>)</td></tr>
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<tr class="separator:ga83d862c5a5e56813b86246d22821ac9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e0a1419830a16667cea4f6454913226" id="r_ga5e0a1419830a16667cea4f6454913226"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e0a1419830a16667cea4f6454913226">RTC_CR_WUTIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga83d862c5a5e56813b86246d22821ac9b">RTC_CR_WUTIE_Msk</a></td></tr>
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<tr class="separator:ga5e0a1419830a16667cea4f6454913226"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad21245a52288246fbca5b954f38c65e8" id="r_gad21245a52288246fbca5b954f38c65e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad21245a52288246fbca5b954f38c65e8">RTC_CR_ALRBIE_Pos</a>   (13U)</td></tr>
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<tr class="separator:gad21245a52288246fbca5b954f38c65e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e79f603f18cfbc266cc55162b739260" id="r_ga1e79f603f18cfbc266cc55162b739260"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e79f603f18cfbc266cc55162b739260">RTC_CR_ALRBIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad21245a52288246fbca5b954f38c65e8">RTC_CR_ALRBIE_Pos</a>)</td></tr>
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<tr class="separator:ga1e79f603f18cfbc266cc55162b739260"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6269c9dd5cee650024ede0b0c42e87d" id="r_gac6269c9dd5cee650024ede0b0c42e87d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6269c9dd5cee650024ede0b0c42e87d">RTC_CR_ALRBIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e79f603f18cfbc266cc55162b739260">RTC_CR_ALRBIE_Msk</a></td></tr>
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<tr class="separator:gac6269c9dd5cee650024ede0b0c42e87d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd69cebbc7fc4a81655a7e53a7284b70" id="r_gacd69cebbc7fc4a81655a7e53a7284b70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd69cebbc7fc4a81655a7e53a7284b70">RTC_CR_ALRAIE_Pos</a>   (12U)</td></tr>
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<tr class="separator:gacd69cebbc7fc4a81655a7e53a7284b70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0efcbd64f981117d73fe6d631c48f45e" id="r_ga0efcbd64f981117d73fe6d631c48f45e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0efcbd64f981117d73fe6d631c48f45e">RTC_CR_ALRAIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacd69cebbc7fc4a81655a7e53a7284b70">RTC_CR_ALRAIE_Pos</a>)</td></tr>
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<tr class="separator:ga0efcbd64f981117d73fe6d631c48f45e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9138f75267bd93f8de6738225217d583" id="r_ga9138f75267bd93f8de6738225217d583"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9138f75267bd93f8de6738225217d583">RTC_CR_ALRAIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0efcbd64f981117d73fe6d631c48f45e">RTC_CR_ALRAIE_Msk</a></td></tr>
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<tr class="separator:ga9138f75267bd93f8de6738225217d583"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf95c6afbdb29aa5241dc3e52d28ce884" id="r_gaf95c6afbdb29aa5241dc3e52d28ce884"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf95c6afbdb29aa5241dc3e52d28ce884">RTC_CR_TSE_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaf95c6afbdb29aa5241dc3e52d28ce884"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2675d723ea5e54a4e6a7c7bd975efcc" id="r_gab2675d723ea5e54a4e6a7c7bd975efcc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2675d723ea5e54a4e6a7c7bd975efcc">RTC_CR_TSE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf95c6afbdb29aa5241dc3e52d28ce884">RTC_CR_TSE_Pos</a>)</td></tr>
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<tr class="separator:gab2675d723ea5e54a4e6a7c7bd975efcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94fa98ca8cac9078b9bb82c89593d3c0" id="r_ga94fa98ca8cac9078b9bb82c89593d3c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94fa98ca8cac9078b9bb82c89593d3c0">RTC_CR_TSE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab2675d723ea5e54a4e6a7c7bd975efcc">RTC_CR_TSE_Msk</a></td></tr>
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<tr class="separator:ga94fa98ca8cac9078b9bb82c89593d3c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf919254119ed634798f3b936dc01e66d" id="r_gaf919254119ed634798f3b936dc01e66d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf919254119ed634798f3b936dc01e66d">RTC_CR_WUTE_Pos</a>   (10U)</td></tr>
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<tr class="separator:gaf919254119ed634798f3b936dc01e66d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5b45d595cd44d31a7f34609b6e7bf1a" id="r_gac5b45d595cd44d31a7f34609b6e7bf1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5b45d595cd44d31a7f34609b6e7bf1a">RTC_CR_WUTE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf919254119ed634798f3b936dc01e66d">RTC_CR_WUTE_Pos</a>)</td></tr>
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<tr class="separator:gac5b45d595cd44d31a7f34609b6e7bf1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga061be0d3cdea721e5cb695cda0699bc3" id="r_ga061be0d3cdea721e5cb695cda0699bc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga061be0d3cdea721e5cb695cda0699bc3">RTC_CR_WUTE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac5b45d595cd44d31a7f34609b6e7bf1a">RTC_CR_WUTE_Msk</a></td></tr>
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<tr class="separator:ga061be0d3cdea721e5cb695cda0699bc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae534f6bb5933c05bc2b63aa70907bfb2" id="r_gae534f6bb5933c05bc2b63aa70907bfb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae534f6bb5933c05bc2b63aa70907bfb2">RTC_CR_ALRBE_Pos</a>   (9U)</td></tr>
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<tr class="separator:gae534f6bb5933c05bc2b63aa70907bfb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae811bd5a731a4d12d5fabc1c1701e7a" id="r_gaae811bd5a731a4d12d5fabc1c1701e7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae811bd5a731a4d12d5fabc1c1701e7a">RTC_CR_ALRBE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae534f6bb5933c05bc2b63aa70907bfb2">RTC_CR_ALRBE_Pos</a>)</td></tr>
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<tr class="separator:gaae811bd5a731a4d12d5fabc1c1701e7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17d0850002ed42742ff75a82dc4e8586" id="r_ga17d0850002ed42742ff75a82dc4e8586"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17d0850002ed42742ff75a82dc4e8586">RTC_CR_ALRBE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae811bd5a731a4d12d5fabc1c1701e7a">RTC_CR_ALRBE_Msk</a></td></tr>
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<tr class="separator:ga17d0850002ed42742ff75a82dc4e8586"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54e3cfdf0409a6e26568fa59c9b5283b" id="r_ga54e3cfdf0409a6e26568fa59c9b5283b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54e3cfdf0409a6e26568fa59c9b5283b">RTC_CR_ALRAE_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga54e3cfdf0409a6e26568fa59c9b5283b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1adc6f86be463291c228b8a2bd3cfa40" id="r_ga1adc6f86be463291c228b8a2bd3cfa40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1adc6f86be463291c228b8a2bd3cfa40">RTC_CR_ALRAE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga54e3cfdf0409a6e26568fa59c9b5283b">RTC_CR_ALRAE_Pos</a>)</td></tr>
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<tr class="separator:ga1adc6f86be463291c228b8a2bd3cfa40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a8cdeac61f06e4737800b64a901d584" id="r_ga8a8cdeac61f06e4737800b64a901d584"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a8cdeac61f06e4737800b64a901d584">RTC_CR_ALRAE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1adc6f86be463291c228b8a2bd3cfa40">RTC_CR_ALRAE_Msk</a></td></tr>
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<tr class="separator:ga8a8cdeac61f06e4737800b64a901d584"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab362e94b8e99714082eb0981045a28b7" id="r_gab362e94b8e99714082eb0981045a28b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab362e94b8e99714082eb0981045a28b7">RTC_CR_DCE_Pos</a>   (7U)</td></tr>
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<tr class="separator:gab362e94b8e99714082eb0981045a28b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga005e60bfb5de91f5d9635d1e8e63f6d3" id="r_ga005e60bfb5de91f5d9635d1e8e63f6d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga005e60bfb5de91f5d9635d1e8e63f6d3">RTC_CR_DCE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab362e94b8e99714082eb0981045a28b7">RTC_CR_DCE_Pos</a>)</td></tr>
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<tr class="separator:ga005e60bfb5de91f5d9635d1e8e63f6d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ce7cb8b575142e125863d61ea4765ba" id="r_ga4ce7cb8b575142e125863d61ea4765ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ce7cb8b575142e125863d61ea4765ba">RTC_CR_DCE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga005e60bfb5de91f5d9635d1e8e63f6d3">RTC_CR_DCE_Msk</a></td></tr>
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<tr class="separator:ga4ce7cb8b575142e125863d61ea4765ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga262f18e12c214c9f172860b3a1234f0e" id="r_ga262f18e12c214c9f172860b3a1234f0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga262f18e12c214c9f172860b3a1234f0e">RTC_CR_FMT_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga262f18e12c214c9f172860b3a1234f0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6634873135b509b3a483abcbd1e0f347" id="r_ga6634873135b509b3a483abcbd1e0f347"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6634873135b509b3a483abcbd1e0f347">RTC_CR_FMT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga262f18e12c214c9f172860b3a1234f0e">RTC_CR_FMT_Pos</a>)</td></tr>
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<tr class="separator:ga6634873135b509b3a483abcbd1e0f347"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2706e31a1bc8d95b682fe47611e0dd3" id="r_gab2706e31a1bc8d95b682fe47611e0dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2706e31a1bc8d95b682fe47611e0dd3">RTC_CR_FMT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6634873135b509b3a483abcbd1e0f347">RTC_CR_FMT_Msk</a></td></tr>
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<tr class="memitem:gace008c8514db9131ae301e7577979130" id="r_gace008c8514db9131ae301e7577979130"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace008c8514db9131ae301e7577979130">RTC_CR_BYPSHAD_Pos</a>   (5U)</td></tr>
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<tr class="memitem:ga93e690c1dc87dff6f36fea71cf6bb57c" id="r_ga93e690c1dc87dff6f36fea71cf6bb57c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93e690c1dc87dff6f36fea71cf6bb57c">RTC_CR_BYPSHAD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gace008c8514db9131ae301e7577979130">RTC_CR_BYPSHAD_Pos</a>)</td></tr>
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<tr class="separator:ga93e690c1dc87dff6f36fea71cf6bb57c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34d50a3eff3364e6da4fefed9962a054" id="r_ga34d50a3eff3364e6da4fefed9962a054"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34d50a3eff3364e6da4fefed9962a054">RTC_CR_BYPSHAD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga93e690c1dc87dff6f36fea71cf6bb57c">RTC_CR_BYPSHAD_Msk</a></td></tr>
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<tr class="separator:ga34d50a3eff3364e6da4fefed9962a054"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae970d1c321c777685111e4a4f70ce44c" id="r_gae970d1c321c777685111e4a4f70ce44c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae970d1c321c777685111e4a4f70ce44c">RTC_CR_REFCKON_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae970d1c321c777685111e4a4f70ce44c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd611d89bc17e379525602d5ea3a7d54" id="r_gabd611d89bc17e379525602d5ea3a7d54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd611d89bc17e379525602d5ea3a7d54">RTC_CR_REFCKON_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae970d1c321c777685111e4a4f70ce44c">RTC_CR_REFCKON_Pos</a>)</td></tr>
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<tr class="separator:gabd611d89bc17e379525602d5ea3a7d54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga646ef1071cacc2d30bbef5597c817021" id="r_ga646ef1071cacc2d30bbef5597c817021"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga646ef1071cacc2d30bbef5597c817021">RTC_CR_REFCKON</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd611d89bc17e379525602d5ea3a7d54">RTC_CR_REFCKON_Msk</a></td></tr>
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<tr class="separator:ga646ef1071cacc2d30bbef5597c817021"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18a34610d5a2a22e66b027341ac6191b" id="r_ga18a34610d5a2a22e66b027341ac6191b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18a34610d5a2a22e66b027341ac6191b">RTC_CR_TSEDGE_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga18a34610d5a2a22e66b027341ac6191b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ea0c6b68ad8797d97693cbc7fe76d8e" id="r_ga3ea0c6b68ad8797d97693cbc7fe76d8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ea0c6b68ad8797d97693cbc7fe76d8e">RTC_CR_TSEDGE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga18a34610d5a2a22e66b027341ac6191b">RTC_CR_TSEDGE_Pos</a>)</td></tr>
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<tr class="separator:ga3ea0c6b68ad8797d97693cbc7fe76d8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad076bde34be7d24f088fd2c003b7a7f7" id="r_gad076bde34be7d24f088fd2c003b7a7f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad076bde34be7d24f088fd2c003b7a7f7">RTC_CR_TSEDGE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ea0c6b68ad8797d97693cbc7fe76d8e">RTC_CR_TSEDGE_Msk</a></td></tr>
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<tr class="separator:gad076bde34be7d24f088fd2c003b7a7f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad30da1c2029c23889c4dd29ee8fa7eea" id="r_gad30da1c2029c23889c4dd29ee8fa7eea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad30da1c2029c23889c4dd29ee8fa7eea">RTC_CR_WUCKSEL_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad30da1c2029c23889c4dd29ee8fa7eea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1961b22823e4f592ac8d1733e079e2a" id="r_gad1961b22823e4f592ac8d1733e079e2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1961b22823e4f592ac8d1733e079e2a">RTC_CR_WUCKSEL_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad30da1c2029c23889c4dd29ee8fa7eea">RTC_CR_WUCKSEL_Pos</a>)</td></tr>
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<tr class="separator:gad1961b22823e4f592ac8d1733e079e2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54a2d55571417d9dfb05826b40d997b0" id="r_ga54a2d55571417d9dfb05826b40d997b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54a2d55571417d9dfb05826b40d997b0">RTC_CR_WUCKSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad1961b22823e4f592ac8d1733e079e2a">RTC_CR_WUCKSEL_Msk</a></td></tr>
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<tr class="separator:ga54a2d55571417d9dfb05826b40d997b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f03056e9aa78c133af90b60af72ba79" id="r_ga6f03056e9aa78c133af90b60af72ba79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f03056e9aa78c133af90b60af72ba79">RTC_CR_WUCKSEL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad30da1c2029c23889c4dd29ee8fa7eea">RTC_CR_WUCKSEL_Pos</a>)</td></tr>
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<tr class="separator:ga6f03056e9aa78c133af90b60af72ba79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga360f7ccf7a89c5091f4affe6d1019215" id="r_ga360f7ccf7a89c5091f4affe6d1019215"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga360f7ccf7a89c5091f4affe6d1019215">RTC_CR_WUCKSEL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad30da1c2029c23889c4dd29ee8fa7eea">RTC_CR_WUCKSEL_Pos</a>)</td></tr>
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<tr class="separator:ga360f7ccf7a89c5091f4affe6d1019215"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad247ac722f6900744cdc16f8f45ed923" id="r_gad247ac722f6900744cdc16f8f45ed923"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad247ac722f6900744cdc16f8f45ed923">RTC_CR_WUCKSEL_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad30da1c2029c23889c4dd29ee8fa7eea">RTC_CR_WUCKSEL_Pos</a>)</td></tr>
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<tr class="separator:gad247ac722f6900744cdc16f8f45ed923"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a793580db48c66a98e44cbda6e0daef" id="r_ga2a793580db48c66a98e44cbda6e0daef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a793580db48c66a98e44cbda6e0daef">RTC_CR_BCK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e7a474de1a01816bc9d9b6fa7272289">RTC_CR_BKP</a></td></tr>
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<tr class="separator:ga2a793580db48c66a98e44cbda6e0daef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa59397ca25b1fc9fbc43cfca986c14e4" id="r_gaa59397ca25b1fc9fbc43cfca986c14e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa59397ca25b1fc9fbc43cfca986c14e4">RTC_ISR_RECALPF_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaa59397ca25b1fc9fbc43cfca986c14e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ab18f49ac6ab32322ebb58131a456ea" id="r_ga8ab18f49ac6ab32322ebb58131a456ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ab18f49ac6ab32322ebb58131a456ea">RTC_ISR_RECALPF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa59397ca25b1fc9fbc43cfca986c14e4">RTC_ISR_RECALPF_Pos</a>)</td></tr>
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<tr class="separator:ga8ab18f49ac6ab32322ebb58131a456ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05189137cfd0e73903d9b70d071656b9" id="r_ga05189137cfd0e73903d9b70d071656b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05189137cfd0e73903d9b70d071656b9">RTC_ISR_RECALPF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ab18f49ac6ab32322ebb58131a456ea">RTC_ISR_RECALPF_Msk</a></td></tr>
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<tr class="separator:ga05189137cfd0e73903d9b70d071656b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf18fa672ae72db52c7a6c5a2658a5190" id="r_gaf18fa672ae72db52c7a6c5a2658a5190"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf18fa672ae72db52c7a6c5a2658a5190">RTC_ISR_TAMP1F_Pos</a>   (13U)</td></tr>
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<tr class="separator:gaf18fa672ae72db52c7a6c5a2658a5190"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84bbb84dba6aef26a16b2410c3a3ec5d" id="r_ga84bbb84dba6aef26a16b2410c3a3ec5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84bbb84dba6aef26a16b2410c3a3ec5d">RTC_ISR_TAMP1F_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf18fa672ae72db52c7a6c5a2658a5190">RTC_ISR_TAMP1F_Pos</a>)</td></tr>
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<tr class="separator:ga84bbb84dba6aef26a16b2410c3a3ec5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae738b22f6a8123026921a1d14f9547c0" id="r_gae738b22f6a8123026921a1d14f9547c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae738b22f6a8123026921a1d14f9547c0">RTC_ISR_TAMP1F</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga84bbb84dba6aef26a16b2410c3a3ec5d">RTC_ISR_TAMP1F_Msk</a></td></tr>
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<tr class="separator:gae738b22f6a8123026921a1d14f9547c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0347e70fa9f25a6a52d3ceac1713ccee" id="r_ga0347e70fa9f25a6a52d3ceac1713ccee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0347e70fa9f25a6a52d3ceac1713ccee">RTC_ISR_TAMP2F_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga0347e70fa9f25a6a52d3ceac1713ccee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga436cbba9b17ad91735e876596c8a6914" id="r_ga436cbba9b17ad91735e876596c8a6914"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga436cbba9b17ad91735e876596c8a6914">RTC_ISR_TAMP2F_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0347e70fa9f25a6a52d3ceac1713ccee">RTC_ISR_TAMP2F_Pos</a>)</td></tr>
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<tr class="separator:ga436cbba9b17ad91735e876596c8a6914"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabdb176578e53b2d8e24a94c8d0212845" id="r_gabdb176578e53b2d8e24a94c8d0212845"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabdb176578e53b2d8e24a94c8d0212845">RTC_ISR_TAMP2F</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga436cbba9b17ad91735e876596c8a6914">RTC_ISR_TAMP2F_Msk</a></td></tr>
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<tr class="separator:gabdb176578e53b2d8e24a94c8d0212845"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa38f2ee43244798276792a0c5a64f41e" id="r_gaa38f2ee43244798276792a0c5a64f41e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa38f2ee43244798276792a0c5a64f41e">RTC_ISR_TSOVF_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaa38f2ee43244798276792a0c5a64f41e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a44c6cf950526be3f768c9175e3e62e" id="r_ga1a44c6cf950526be3f768c9175e3e62e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a44c6cf950526be3f768c9175e3e62e">RTC_ISR_TSOVF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa38f2ee43244798276792a0c5a64f41e">RTC_ISR_TSOVF_Pos</a>)</td></tr>
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<tr class="separator:ga1a44c6cf950526be3f768c9175e3e62e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga766c238f964072decba204c7fce850ff" id="r_ga766c238f964072decba204c7fce850ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga766c238f964072decba204c7fce850ff">RTC_ISR_TSOVF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a44c6cf950526be3f768c9175e3e62e">RTC_ISR_TSOVF_Msk</a></td></tr>
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<tr class="separator:ga766c238f964072decba204c7fce850ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09bb6ceebab0b76cd2121816e787749a" id="r_ga09bb6ceebab0b76cd2121816e787749a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09bb6ceebab0b76cd2121816e787749a">RTC_ISR_TSF_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga09bb6ceebab0b76cd2121816e787749a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f5151d79a2761d423ddbc0b6c3cca1f" id="r_ga8f5151d79a2761d423ddbc0b6c3cca1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f5151d79a2761d423ddbc0b6c3cca1f">RTC_ISR_TSF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga09bb6ceebab0b76cd2121816e787749a">RTC_ISR_TSF_Pos</a>)</td></tr>
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<tr class="separator:ga8f5151d79a2761d423ddbc0b6c3cca1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68c0a60dbfc5f1570a48afe450395484" id="r_ga68c0a60dbfc5f1570a48afe450395484"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68c0a60dbfc5f1570a48afe450395484">RTC_ISR_TSF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f5151d79a2761d423ddbc0b6c3cca1f">RTC_ISR_TSF_Msk</a></td></tr>
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<tr class="separator:ga68c0a60dbfc5f1570a48afe450395484"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6c5050a881336d0a8710d096fe4b01a" id="r_gae6c5050a881336d0a8710d096fe4b01a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6c5050a881336d0a8710d096fe4b01a">RTC_ISR_WUTF_Pos</a>   (10U)</td></tr>
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<tr class="separator:gae6c5050a881336d0a8710d096fe4b01a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53360cc2baf2a2142289493b2a16c372" id="r_ga53360cc2baf2a2142289493b2a16c372"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53360cc2baf2a2142289493b2a16c372">RTC_ISR_WUTF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae6c5050a881336d0a8710d096fe4b01a">RTC_ISR_WUTF_Pos</a>)</td></tr>
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<tr class="separator:ga53360cc2baf2a2142289493b2a16c372"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4eb5960300a402210e5378d78ce22766" id="r_ga4eb5960300a402210e5378d78ce22766"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4eb5960300a402210e5378d78ce22766">RTC_ISR_WUTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga53360cc2baf2a2142289493b2a16c372">RTC_ISR_WUTF_Msk</a></td></tr>
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<tr class="memitem:ga4891bf442ab59fa4488bc0ed308c56c2" id="r_ga4891bf442ab59fa4488bc0ed308c56c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4891bf442ab59fa4488bc0ed308c56c2">RTC_ISR_ALRBF_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga4891bf442ab59fa4488bc0ed308c56c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac80e30a64a34bd547229f68b76d63a87" id="r_gac80e30a64a34bd547229f68b76d63a87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac80e30a64a34bd547229f68b76d63a87">RTC_ISR_ALRBF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4891bf442ab59fa4488bc0ed308c56c2">RTC_ISR_ALRBF_Pos</a>)</td></tr>
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<tr class="separator:gac80e30a64a34bd547229f68b76d63a87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7976972a5fc6705fede85536520367d6" id="r_ga7976972a5fc6705fede85536520367d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7976972a5fc6705fede85536520367d6">RTC_ISR_ALRBF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac80e30a64a34bd547229f68b76d63a87">RTC_ISR_ALRBF_Msk</a></td></tr>
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<tr class="separator:ga7976972a5fc6705fede85536520367d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bbb887fab178f2ad6c26fe28bd16cd6" id="r_ga4bbb887fab178f2ad6c26fe28bd16cd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bbb887fab178f2ad6c26fe28bd16cd6">RTC_ISR_ALRAF_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga4bbb887fab178f2ad6c26fe28bd16cd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5aeb3a57686a3bca74ebce43559161e" id="r_gaf5aeb3a57686a3bca74ebce43559161e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5aeb3a57686a3bca74ebce43559161e">RTC_ISR_ALRAF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bbb887fab178f2ad6c26fe28bd16cd6">RTC_ISR_ALRAF_Pos</a>)</td></tr>
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<tr class="separator:gaf5aeb3a57686a3bca74ebce43559161e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96605e50a347507b7f274e9cd894a02c" id="r_ga96605e50a347507b7f274e9cd894a02c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96605e50a347507b7f274e9cd894a02c">RTC_ISR_ALRAF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5aeb3a57686a3bca74ebce43559161e">RTC_ISR_ALRAF_Msk</a></td></tr>
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<tr class="separator:ga96605e50a347507b7f274e9cd894a02c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9a0e0b639b59be3c662267184bddf69" id="r_gab9a0e0b639b59be3c662267184bddf69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9a0e0b639b59be3c662267184bddf69">RTC_ISR_INIT_Pos</a>   (7U)</td></tr>
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<tr class="separator:gab9a0e0b639b59be3c662267184bddf69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5e864e670cc4643c1e65b21da150c74" id="r_gae5e864e670cc4643c1e65b21da150c74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5e864e670cc4643c1e65b21da150c74">RTC_ISR_INIT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab9a0e0b639b59be3c662267184bddf69">RTC_ISR_INIT_Pos</a>)</td></tr>
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<tr class="separator:gae5e864e670cc4643c1e65b21da150c74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0eb2f998cd3e7325974347cb2a3d25a" id="r_gae0eb2f998cd3e7325974347cb2a3d25a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0eb2f998cd3e7325974347cb2a3d25a">RTC_ISR_INIT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae5e864e670cc4643c1e65b21da150c74">RTC_ISR_INIT_Msk</a></td></tr>
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<tr class="separator:gae0eb2f998cd3e7325974347cb2a3d25a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga601564e925eefdbde3aafdcbf0a978c5" id="r_ga601564e925eefdbde3aafdcbf0a978c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga601564e925eefdbde3aafdcbf0a978c5">RTC_ISR_INITF_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga601564e925eefdbde3aafdcbf0a978c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a29ce1f3e261024726679c17f42a9b1" id="r_ga6a29ce1f3e261024726679c17f42a9b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a29ce1f3e261024726679c17f42a9b1">RTC_ISR_INITF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga601564e925eefdbde3aafdcbf0a978c5">RTC_ISR_INITF_Pos</a>)</td></tr>
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<tr class="separator:ga6a29ce1f3e261024726679c17f42a9b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab16dcc6973c611e087030cdb15203972" id="r_gab16dcc6973c611e087030cdb15203972"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab16dcc6973c611e087030cdb15203972">RTC_ISR_INITF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a29ce1f3e261024726679c17f42a9b1">RTC_ISR_INITF_Msk</a></td></tr>
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<tr class="separator:gab16dcc6973c611e087030cdb15203972"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8dd0bed53ed3cc1bbc70efa82bcac846" id="r_ga8dd0bed53ed3cc1bbc70efa82bcac846"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8dd0bed53ed3cc1bbc70efa82bcac846">RTC_ISR_RSF_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga8dd0bed53ed3cc1bbc70efa82bcac846"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f87ecd7737391a4ff0c236a17dbfd32" id="r_ga3f87ecd7737391a4ff0c236a17dbfd32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f87ecd7737391a4ff0c236a17dbfd32">RTC_ISR_RSF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8dd0bed53ed3cc1bbc70efa82bcac846">RTC_ISR_RSF_Pos</a>)</td></tr>
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<tr class="separator:ga3f87ecd7737391a4ff0c236a17dbfd32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bd683e789841f7d3f138709ffdbfbf8" id="r_ga9bd683e789841f7d3f138709ffdbfbf8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bd683e789841f7d3f138709ffdbfbf8">RTC_ISR_RSF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f87ecd7737391a4ff0c236a17dbfd32">RTC_ISR_RSF_Msk</a></td></tr>
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<tr class="separator:ga9bd683e789841f7d3f138709ffdbfbf8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6f7e11d89c6480d68013ce7c0478045" id="r_gae6f7e11d89c6480d68013ce7c0478045"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6f7e11d89c6480d68013ce7c0478045">RTC_ISR_INITS_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae6f7e11d89c6480d68013ce7c0478045"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25131777233cef2dfffdc178667559e4" id="r_ga25131777233cef2dfffdc178667559e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25131777233cef2dfffdc178667559e4">RTC_ISR_INITS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae6f7e11d89c6480d68013ce7c0478045">RTC_ISR_INITS_Pos</a>)</td></tr>
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<tr class="separator:ga25131777233cef2dfffdc178667559e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b229bace5ba0c0b48bfeb5efc445292" id="r_ga7b229bace5ba0c0b48bfeb5efc445292"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b229bace5ba0c0b48bfeb5efc445292">RTC_ISR_INITS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga25131777233cef2dfffdc178667559e4">RTC_ISR_INITS_Msk</a></td></tr>
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<tr class="separator:ga7b229bace5ba0c0b48bfeb5efc445292"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4312f68d569942ac8d1b6abfb0f5aad" id="r_gad4312f68d569942ac8d1b6abfb0f5aad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4312f68d569942ac8d1b6abfb0f5aad">RTC_ISR_SHPF_Pos</a>   (3U)</td></tr>
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<tr class="separator:gad4312f68d569942ac8d1b6abfb0f5aad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36cc41c7b626c5047f97fac12337395d" id="r_ga36cc41c7b626c5047f97fac12337395d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36cc41c7b626c5047f97fac12337395d">RTC_ISR_SHPF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad4312f68d569942ac8d1b6abfb0f5aad">RTC_ISR_SHPF_Pos</a>)</td></tr>
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<tr class="separator:ga36cc41c7b626c5047f97fac12337395d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c4536a874336778ac11109f14573eb9" id="r_ga1c4536a874336778ac11109f14573eb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c4536a874336778ac11109f14573eb9">RTC_ISR_SHPF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36cc41c7b626c5047f97fac12337395d">RTC_ISR_SHPF_Msk</a></td></tr>
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<tr class="separator:ga1c4536a874336778ac11109f14573eb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d75a29fa323d93d3d0bb2cb60b24474" id="r_ga8d75a29fa323d93d3d0bb2cb60b24474"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d75a29fa323d93d3d0bb2cb60b24474">RTC_ISR_WUTWF_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga8d75a29fa323d93d3d0bb2cb60b24474"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga673f0ff6267142391ca1d37289b305f2" id="r_ga673f0ff6267142391ca1d37289b305f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga673f0ff6267142391ca1d37289b305f2">RTC_ISR_WUTWF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d75a29fa323d93d3d0bb2cb60b24474">RTC_ISR_WUTWF_Pos</a>)</td></tr>
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<tr class="separator:ga673f0ff6267142391ca1d37289b305f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e753321211e19bc48736fe0d30a7f40" id="r_ga0e753321211e19bc48736fe0d30a7f40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e753321211e19bc48736fe0d30a7f40">RTC_ISR_WUTWF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga673f0ff6267142391ca1d37289b305f2">RTC_ISR_WUTWF_Msk</a></td></tr>
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<tr class="separator:ga0e753321211e19bc48736fe0d30a7f40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga011f9bc215e39c91f33f0472e0b59643" id="r_ga011f9bc215e39c91f33f0472e0b59643"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga011f9bc215e39c91f33f0472e0b59643">RTC_ISR_ALRBWF_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga011f9bc215e39c91f33f0472e0b59643"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cf9f3b0159c2f29749babdc55ef1a1b" id="r_ga6cf9f3b0159c2f29749babdc55ef1a1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cf9f3b0159c2f29749babdc55ef1a1b">RTC_ISR_ALRBWF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga011f9bc215e39c91f33f0472e0b59643">RTC_ISR_ALRBWF_Pos</a>)</td></tr>
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<tr class="separator:ga6cf9f3b0159c2f29749babdc55ef1a1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a0c34bff6dc9fce29e2be35d32d9d05" id="r_ga5a0c34bff6dc9fce29e2be35d32d9d05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a0c34bff6dc9fce29e2be35d32d9d05">RTC_ISR_ALRBWF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cf9f3b0159c2f29749babdc55ef1a1b">RTC_ISR_ALRBWF_Msk</a></td></tr>
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<tr class="separator:ga5a0c34bff6dc9fce29e2be35d32d9d05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab296f795ad4fa25ad0cb3c92967f9565" id="r_gab296f795ad4fa25ad0cb3c92967f9565"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab296f795ad4fa25ad0cb3c92967f9565">RTC_ISR_ALRAWF_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab296f795ad4fa25ad0cb3c92967f9565"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4d96dae4fdd343fe6e9ebc7c5f7d80d" id="r_gac4d96dae4fdd343fe6e9ebc7c5f7d80d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4d96dae4fdd343fe6e9ebc7c5f7d80d">RTC_ISR_ALRAWF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab296f795ad4fa25ad0cb3c92967f9565">RTC_ISR_ALRAWF_Pos</a>)</td></tr>
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<tr class="separator:gac4d96dae4fdd343fe6e9ebc7c5f7d80d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d420b5c3f8623cf1116d42fa164be7e" id="r_ga4d420b5c3f8623cf1116d42fa164be7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d420b5c3f8623cf1116d42fa164be7e">RTC_ISR_ALRAWF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4d96dae4fdd343fe6e9ebc7c5f7d80d">RTC_ISR_ALRAWF_Msk</a></td></tr>
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<tr class="separator:ga4d420b5c3f8623cf1116d42fa164be7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8240c029696ad91531c3fec1ef1e7fe" id="r_gae8240c029696ad91531c3fec1ef1e7fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8240c029696ad91531c3fec1ef1e7fe">RTC_PRER_PREDIV_A_Pos</a>   (16U)</td></tr>
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<tr class="separator:gae8240c029696ad91531c3fec1ef1e7fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f883861bb963a097885c5773f3c0b15" id="r_ga2f883861bb963a097885c5773f3c0b15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f883861bb963a097885c5773f3c0b15">RTC_PRER_PREDIV_A_Msk</a>   (0x7FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae8240c029696ad91531c3fec1ef1e7fe">RTC_PRER_PREDIV_A_Pos</a>)</td></tr>
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<tr class="separator:ga2f883861bb963a097885c5773f3c0b15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad248dca1e9532ba31f98d3ec9d2f8711" id="r_gad248dca1e9532ba31f98d3ec9d2f8711"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad248dca1e9532ba31f98d3ec9d2f8711">RTC_PRER_PREDIV_A</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f883861bb963a097885c5773f3c0b15">RTC_PRER_PREDIV_A_Msk</a></td></tr>
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<tr class="separator:gad248dca1e9532ba31f98d3ec9d2f8711"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga234f46098c91b34aa12502d70cdb93bf" id="r_ga234f46098c91b34aa12502d70cdb93bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga234f46098c91b34aa12502d70cdb93bf">RTC_PRER_PREDIV_S_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga234f46098c91b34aa12502d70cdb93bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga776acde6c1789c37371eb440492825ab" id="r_ga776acde6c1789c37371eb440492825ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga776acde6c1789c37371eb440492825ab">RTC_PRER_PREDIV_S_Msk</a>   (0x7FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga234f46098c91b34aa12502d70cdb93bf">RTC_PRER_PREDIV_S_Pos</a>)</td></tr>
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<tr class="separator:ga776acde6c1789c37371eb440492825ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17bbd4e569a76446df089752cb41b1cb" id="r_ga17bbd4e569a76446df089752cb41b1cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17bbd4e569a76446df089752cb41b1cb">RTC_PRER_PREDIV_S</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga776acde6c1789c37371eb440492825ab">RTC_PRER_PREDIV_S_Msk</a></td></tr>
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<tr class="separator:ga17bbd4e569a76446df089752cb41b1cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae50a0fcd154d36aa0b506a875e8d100e" id="r_gae50a0fcd154d36aa0b506a875e8d100e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae50a0fcd154d36aa0b506a875e8d100e">RTC_WUTR_WUT_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae50a0fcd154d36aa0b506a875e8d100e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c2d178daf42c0febdbf67583a83b6a0" id="r_ga1c2d178daf42c0febdbf67583a83b6a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c2d178daf42c0febdbf67583a83b6a0">RTC_WUTR_WUT_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae50a0fcd154d36aa0b506a875e8d100e">RTC_WUTR_WUT_Pos</a>)</td></tr>
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<tr class="separator:ga1c2d178daf42c0febdbf67583a83b6a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e412c1448a7e20974f5b46129799eeb" id="r_ga2e412c1448a7e20974f5b46129799eeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e412c1448a7e20974f5b46129799eeb">RTC_WUTR_WUT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c2d178daf42c0febdbf67583a83b6a0">RTC_WUTR_WUT_Msk</a></td></tr>
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<tr class="separator:ga2e412c1448a7e20974f5b46129799eeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79b734efd7f580384b76364f8159ce2a" id="r_ga79b734efd7f580384b76364f8159ce2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79b734efd7f580384b76364f8159ce2a">RTC_CALIBR_DCS_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga79b734efd7f580384b76364f8159ce2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac975f6abc1ae98deb38d1c523a564431" id="r_gac975f6abc1ae98deb38d1c523a564431"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac975f6abc1ae98deb38d1c523a564431">RTC_CALIBR_DCS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga79b734efd7f580384b76364f8159ce2a">RTC_CALIBR_DCS_Pos</a>)</td></tr>
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<tr class="separator:gac975f6abc1ae98deb38d1c523a564431"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa63841fd7262fd307f211ee8e9e8a6f0" id="r_gaa63841fd7262fd307f211ee8e9e8a6f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa63841fd7262fd307f211ee8e9e8a6f0">RTC_CALIBR_DCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac975f6abc1ae98deb38d1c523a564431">RTC_CALIBR_DCS_Msk</a></td></tr>
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<tr class="separator:gaa63841fd7262fd307f211ee8e9e8a6f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga612c3ec0e88f91fd34cfb4910b5b46fb" id="r_ga612c3ec0e88f91fd34cfb4910b5b46fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga612c3ec0e88f91fd34cfb4910b5b46fb">RTC_CALIBR_DC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga612c3ec0e88f91fd34cfb4910b5b46fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb0820dbde8c1188a5c045e6e264c1f8" id="r_gabb0820dbde8c1188a5c045e6e264c1f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb0820dbde8c1188a5c045e6e264c1f8">RTC_CALIBR_DC_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga612c3ec0e88f91fd34cfb4910b5b46fb">RTC_CALIBR_DC_Pos</a>)</td></tr>
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<tr class="separator:gabb0820dbde8c1188a5c045e6e264c1f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5523cf582ebc0a987c6a2c2007bc10d" id="r_gab5523cf582ebc0a987c6a2c2007bc10d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5523cf582ebc0a987c6a2c2007bc10d">RTC_CALIBR_DC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabb0820dbde8c1188a5c045e6e264c1f8">RTC_CALIBR_DC_Msk</a></td></tr>
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<tr class="separator:gab5523cf582ebc0a987c6a2c2007bc10d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4c443ed6c81b3ce75dd5e8dd97939fb" id="r_gaf4c443ed6c81b3ce75dd5e8dd97939fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4c443ed6c81b3ce75dd5e8dd97939fb">RTC_ALRMAR_MSK4_Pos</a>   (31U)</td></tr>
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<tr class="separator:gaf4c443ed6c81b3ce75dd5e8dd97939fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ade8f686276ed4761f3741cd928b500" id="r_ga4ade8f686276ed4761f3741cd928b500"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ade8f686276ed4761f3741cd928b500">RTC_ALRMAR_MSK4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf4c443ed6c81b3ce75dd5e8dd97939fb">RTC_ALRMAR_MSK4_Pos</a>)</td></tr>
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<tr class="separator:ga4ade8f686276ed4761f3741cd928b500"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ed557e4451ffd3e869bb9ca393d47f9" id="r_ga8ed557e4451ffd3e869bb9ca393d47f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ed557e4451ffd3e869bb9ca393d47f9">RTC_ALRMAR_MSK4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ade8f686276ed4761f3741cd928b500">RTC_ALRMAR_MSK4_Msk</a></td></tr>
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<tr class="separator:ga8ed557e4451ffd3e869bb9ca393d47f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd589f750a310c033dafdab213642649" id="r_gadd589f750a310c033dafdab213642649"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd589f750a310c033dafdab213642649">RTC_ALRMAR_WDSEL_Pos</a>   (30U)</td></tr>
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<tr class="separator:gadd589f750a310c033dafdab213642649"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccf0424c522933862730917c9c79f81b" id="r_gaccf0424c522933862730917c9c79f81b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccf0424c522933862730917c9c79f81b">RTC_ALRMAR_WDSEL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadd589f750a310c033dafdab213642649">RTC_ALRMAR_WDSEL_Pos</a>)</td></tr>
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<tr class="separator:gaccf0424c522933862730917c9c79f81b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a7fdc1719b3159e099c3979da26dd92" id="r_ga5a7fdc1719b3159e099c3979da26dd92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a7fdc1719b3159e099c3979da26dd92">RTC_ALRMAR_WDSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaccf0424c522933862730917c9c79f81b">RTC_ALRMAR_WDSEL_Msk</a></td></tr>
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<tr class="separator:ga5a7fdc1719b3159e099c3979da26dd92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4d605cd74901b7544c8a6cc9f446436" id="r_gab4d605cd74901b7544c8a6cc9f446436"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4d605cd74901b7544c8a6cc9f446436">RTC_ALRMAR_DT_Pos</a>   (28U)</td></tr>
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<tr class="separator:gab4d605cd74901b7544c8a6cc9f446436"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b864018e7de62c954d6fff34bde926f" id="r_ga5b864018e7de62c954d6fff34bde926f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b864018e7de62c954d6fff34bde926f">RTC_ALRMAR_DT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab4d605cd74901b7544c8a6cc9f446436">RTC_ALRMAR_DT_Pos</a>)</td></tr>
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<tr class="separator:ga5b864018e7de62c954d6fff34bde926f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga934ea7910b5f5988f6c46ae4703dc29b" id="r_ga934ea7910b5f5988f6c46ae4703dc29b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga934ea7910b5f5988f6c46ae4703dc29b">RTC_ALRMAR_DT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b864018e7de62c954d6fff34bde926f">RTC_ALRMAR_DT_Msk</a></td></tr>
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<tr class="separator:ga934ea7910b5f5988f6c46ae4703dc29b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cb880cece843ba5314120abcf14e9fc" id="r_ga0cb880cece843ba5314120abcf14e9fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cb880cece843ba5314120abcf14e9fc">RTC_ALRMAR_DT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab4d605cd74901b7544c8a6cc9f446436">RTC_ALRMAR_DT_Pos</a>)</td></tr>
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<tr class="separator:ga0cb880cece843ba5314120abcf14e9fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e2e76ce2645d0c9d2587d4172edcd58" id="r_ga6e2e76ce2645d0c9d2587d4172edcd58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e2e76ce2645d0c9d2587d4172edcd58">RTC_ALRMAR_DT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab4d605cd74901b7544c8a6cc9f446436">RTC_ALRMAR_DT_Pos</a>)</td></tr>
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<tr class="separator:ga6e2e76ce2645d0c9d2587d4172edcd58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab5a8a73b82a0e8c16f7f5dc35166622" id="r_gaab5a8a73b82a0e8c16f7f5dc35166622"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab5a8a73b82a0e8c16f7f5dc35166622">RTC_ALRMAR_DU_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaab5a8a73b82a0e8c16f7f5dc35166622"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f818fa2666247ad93611752020097b1" id="r_ga6f818fa2666247ad93611752020097b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f818fa2666247ad93611752020097b1">RTC_ALRMAR_DU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab5a8a73b82a0e8c16f7f5dc35166622">RTC_ALRMAR_DU_Pos</a>)</td></tr>
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<tr class="separator:ga6f818fa2666247ad93611752020097b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga784589946bdf3ca0d675cc22d9bafbbf" id="r_ga784589946bdf3ca0d675cc22d9bafbbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga784589946bdf3ca0d675cc22d9bafbbf">RTC_ALRMAR_DU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f818fa2666247ad93611752020097b1">RTC_ALRMAR_DU_Msk</a></td></tr>
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<tr class="separator:ga784589946bdf3ca0d675cc22d9bafbbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga687a85ed4e7623bdb60196f706ab62e9" id="r_ga687a85ed4e7623bdb60196f706ab62e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga687a85ed4e7623bdb60196f706ab62e9">RTC_ALRMAR_DU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab5a8a73b82a0e8c16f7f5dc35166622">RTC_ALRMAR_DU_Pos</a>)</td></tr>
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<tr class="separator:ga687a85ed4e7623bdb60196f706ab62e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d2ec65de047fdece20083f030cc6cfd" id="r_ga8d2ec65de047fdece20083f030cc6cfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d2ec65de047fdece20083f030cc6cfd">RTC_ALRMAR_DU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab5a8a73b82a0e8c16f7f5dc35166622">RTC_ALRMAR_DU_Pos</a>)</td></tr>
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<tr class="separator:ga8d2ec65de047fdece20083f030cc6cfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb0050d5e8d64e4f684e325446ea173a" id="r_gaeb0050d5e8d64e4f684e325446ea173a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb0050d5e8d64e4f684e325446ea173a">RTC_ALRMAR_DU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab5a8a73b82a0e8c16f7f5dc35166622">RTC_ALRMAR_DU_Pos</a>)</td></tr>
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<tr class="separator:gaeb0050d5e8d64e4f684e325446ea173a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79a55db963d0707fc0ae14bffc51c297" id="r_ga79a55db963d0707fc0ae14bffc51c297"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79a55db963d0707fc0ae14bffc51c297">RTC_ALRMAR_DU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab5a8a73b82a0e8c16f7f5dc35166622">RTC_ALRMAR_DU_Pos</a>)</td></tr>
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<tr class="memitem:ga4744abec80afe01487c6133d9325f47b" id="r_ga4744abec80afe01487c6133d9325f47b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4744abec80afe01487c6133d9325f47b">RTC_ALRMAR_MSK3_Pos</a>   (23U)</td></tr>
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<tr class="memitem:ga9b72eca3af2788a6df2aab8efdf48c7e" id="r_ga9b72eca3af2788a6df2aab8efdf48c7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b72eca3af2788a6df2aab8efdf48c7e">RTC_ALRMAR_MSK3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4744abec80afe01487c6133d9325f47b">RTC_ALRMAR_MSK3_Pos</a>)</td></tr>
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<tr class="separator:ga9b72eca3af2788a6df2aab8efdf48c7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga337fba397cab4beb204f4f6e6ddc4bf3" id="r_ga337fba397cab4beb204f4f6e6ddc4bf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga337fba397cab4beb204f4f6e6ddc4bf3">RTC_ALRMAR_MSK3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b72eca3af2788a6df2aab8efdf48c7e">RTC_ALRMAR_MSK3_Msk</a></td></tr>
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<tr class="separator:ga337fba397cab4beb204f4f6e6ddc4bf3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85bfa4c2296c553269373a411323b21f" id="r_ga85bfa4c2296c553269373a411323b21f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85bfa4c2296c553269373a411323b21f">RTC_ALRMAR_PM_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga85bfa4c2296c553269373a411323b21f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ed4ff622a2ac83edfaadc596995c61a" id="r_ga1ed4ff622a2ac83edfaadc596995c61a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ed4ff622a2ac83edfaadc596995c61a">RTC_ALRMAR_PM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga85bfa4c2296c553269373a411323b21f">RTC_ALRMAR_PM_Pos</a>)</td></tr>
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<tr class="memitem:gaab68dc30427951b19aecf399b0ae2900" id="r_gaab68dc30427951b19aecf399b0ae2900"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab68dc30427951b19aecf399b0ae2900">RTC_ALRMAR_PM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ed4ff622a2ac83edfaadc596995c61a">RTC_ALRMAR_PM_Msk</a></td></tr>
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<tr class="memitem:gadeb1eb233c192d56b4a4f106b3fb4be2" id="r_gadeb1eb233c192d56b4a4f106b3fb4be2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadeb1eb233c192d56b4a4f106b3fb4be2">RTC_ALRMAR_HT_Pos</a>   (20U)</td></tr>
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<tr class="separator:gadeb1eb233c192d56b4a4f106b3fb4be2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfbc262cd63d3a1c5cdf4937cc57ec37" id="r_gacfbc262cd63d3a1c5cdf4937cc57ec37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfbc262cd63d3a1c5cdf4937cc57ec37">RTC_ALRMAR_HT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadeb1eb233c192d56b4a4f106b3fb4be2">RTC_ALRMAR_HT_Pos</a>)</td></tr>
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<tr class="separator:gacfbc262cd63d3a1c5cdf4937cc57ec37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55bc04190e9eaa916144fa2d1777cbfb" id="r_ga55bc04190e9eaa916144fa2d1777cbfb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55bc04190e9eaa916144fa2d1777cbfb">RTC_ALRMAR_HT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacfbc262cd63d3a1c5cdf4937cc57ec37">RTC_ALRMAR_HT_Msk</a></td></tr>
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<tr class="separator:ga55bc04190e9eaa916144fa2d1777cbfb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4165b904cdf6bdf4ed6c892d73953453" id="r_ga4165b904cdf6bdf4ed6c892d73953453"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4165b904cdf6bdf4ed6c892d73953453">RTC_ALRMAR_HT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadeb1eb233c192d56b4a4f106b3fb4be2">RTC_ALRMAR_HT_Pos</a>)</td></tr>
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<tr class="separator:ga4165b904cdf6bdf4ed6c892d73953453"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab50f98903ad0183c52c40375d45d4d77" id="r_gab50f98903ad0183c52c40375d45d4d77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab50f98903ad0183c52c40375d45d4d77">RTC_ALRMAR_HT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadeb1eb233c192d56b4a4f106b3fb4be2">RTC_ALRMAR_HT_Pos</a>)</td></tr>
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<tr class="separator:gab50f98903ad0183c52c40375d45d4d77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga914c62bbd3ce817fd1d6f871ed894222" id="r_ga914c62bbd3ce817fd1d6f871ed894222"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga914c62bbd3ce817fd1d6f871ed894222">RTC_ALRMAR_HU_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga914c62bbd3ce817fd1d6f871ed894222"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d3da70f04ca3c7c2f90ee0d0d3c9201" id="r_ga0d3da70f04ca3c7c2f90ee0d0d3c9201"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d3da70f04ca3c7c2f90ee0d0d3c9201">RTC_ALRMAR_HU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga914c62bbd3ce817fd1d6f871ed894222">RTC_ALRMAR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga0d3da70f04ca3c7c2f90ee0d0d3c9201"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga491fda42cfad244596737347fe157142" id="r_ga491fda42cfad244596737347fe157142"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga491fda42cfad244596737347fe157142">RTC_ALRMAR_HU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d3da70f04ca3c7c2f90ee0d0d3c9201">RTC_ALRMAR_HU_Msk</a></td></tr>
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<tr class="separator:ga491fda42cfad244596737347fe157142"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga756c2c137f6d1f89bba95347245b014c" id="r_ga756c2c137f6d1f89bba95347245b014c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga756c2c137f6d1f89bba95347245b014c">RTC_ALRMAR_HU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga914c62bbd3ce817fd1d6f871ed894222">RTC_ALRMAR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga756c2c137f6d1f89bba95347245b014c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2068b4116fca73a63b1c98f51902acef" id="r_ga2068b4116fca73a63b1c98f51902acef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2068b4116fca73a63b1c98f51902acef">RTC_ALRMAR_HU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga914c62bbd3ce817fd1d6f871ed894222">RTC_ALRMAR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga2068b4116fca73a63b1c98f51902acef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7642e83ff425a1fe2695d1100ce7c35" id="r_gab7642e83ff425a1fe2695d1100ce7c35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7642e83ff425a1fe2695d1100ce7c35">RTC_ALRMAR_HU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga914c62bbd3ce817fd1d6f871ed894222">RTC_ALRMAR_HU_Pos</a>)</td></tr>
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<tr class="separator:gab7642e83ff425a1fe2695d1100ce7c35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f516916142b3ea6110619e8dc600d2a" id="r_ga9f516916142b3ea6110619e8dc600d2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f516916142b3ea6110619e8dc600d2a">RTC_ALRMAR_HU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga914c62bbd3ce817fd1d6f871ed894222">RTC_ALRMAR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga9f516916142b3ea6110619e8dc600d2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae87ea1c4a907654aa4565047647afa30" id="r_gae87ea1c4a907654aa4565047647afa30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae87ea1c4a907654aa4565047647afa30">RTC_ALRMAR_MSK2_Pos</a>   (15U)</td></tr>
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<tr class="separator:gae87ea1c4a907654aa4565047647afa30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe0fda62acb0b820b859291e4b45e409" id="r_gabe0fda62acb0b820b859291e4b45e409"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe0fda62acb0b820b859291e4b45e409">RTC_ALRMAR_MSK2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae87ea1c4a907654aa4565047647afa30">RTC_ALRMAR_MSK2_Pos</a>)</td></tr>
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<tr class="separator:gabe0fda62acb0b820b859291e4b45e409"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga478d62d55a42779c558e9ba16aec74cc" id="r_ga478d62d55a42779c558e9ba16aec74cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga478d62d55a42779c558e9ba16aec74cc">RTC_ALRMAR_MSK2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe0fda62acb0b820b859291e4b45e409">RTC_ALRMAR_MSK2_Msk</a></td></tr>
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<tr class="memitem:gaee274022f516021cba28dede0ff60450" id="r_gaee274022f516021cba28dede0ff60450"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee274022f516021cba28dede0ff60450">RTC_ALRMAR_MNT_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaee274022f516021cba28dede0ff60450"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac320cc91348b22f3e5c0d6106594c09e" id="r_gac320cc91348b22f3e5c0d6106594c09e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac320cc91348b22f3e5c0d6106594c09e">RTC_ALRMAR_MNT_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee274022f516021cba28dede0ff60450">RTC_ALRMAR_MNT_Pos</a>)</td></tr>
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<tr class="separator:gac320cc91348b22f3e5c0d6106594c09e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02edb2d87b7fe9936a0cffa96d4a7297" id="r_ga02edb2d87b7fe9936a0cffa96d4a7297"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02edb2d87b7fe9936a0cffa96d4a7297">RTC_ALRMAR_MNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac320cc91348b22f3e5c0d6106594c09e">RTC_ALRMAR_MNT_Msk</a></td></tr>
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<tr class="separator:ga02edb2d87b7fe9936a0cffa96d4a7297"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0dab36fbc475b7ec4442020f159601c6" id="r_ga0dab36fbc475b7ec4442020f159601c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dab36fbc475b7ec4442020f159601c6">RTC_ALRMAR_MNT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee274022f516021cba28dede0ff60450">RTC_ALRMAR_MNT_Pos</a>)</td></tr>
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<tr class="memitem:ga6782f11cc7f8edf401dec2ff436d7968" id="r_ga6782f11cc7f8edf401dec2ff436d7968"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6782f11cc7f8edf401dec2ff436d7968">RTC_ALRMAR_MNT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee274022f516021cba28dede0ff60450">RTC_ALRMAR_MNT_Pos</a>)</td></tr>
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<tr class="memitem:gaf766f39637efe114b38a1aceb352328d" id="r_gaf766f39637efe114b38a1aceb352328d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf766f39637efe114b38a1aceb352328d">RTC_ALRMAR_MNT_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee274022f516021cba28dede0ff60450">RTC_ALRMAR_MNT_Pos</a>)</td></tr>
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<tr class="separator:gaf766f39637efe114b38a1aceb352328d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4fd9dea59596ad989af2bce818b1b93" id="r_gac4fd9dea59596ad989af2bce818b1b93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4fd9dea59596ad989af2bce818b1b93">RTC_ALRMAR_MNU_Pos</a>   (8U)</td></tr>
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<tr class="separator:gac4fd9dea59596ad989af2bce818b1b93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac05e67cdb4da1882dd5b8f5a8fe51bb2" id="r_gac05e67cdb4da1882dd5b8f5a8fe51bb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac05e67cdb4da1882dd5b8f5a8fe51bb2">RTC_ALRMAR_MNU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fd9dea59596ad989af2bce818b1b93">RTC_ALRMAR_MNU_Pos</a>)</td></tr>
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<tr class="separator:gac05e67cdb4da1882dd5b8f5a8fe51bb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22d67ff770aa27509d79afde1865c845" id="r_ga22d67ff770aa27509d79afde1865c845"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22d67ff770aa27509d79afde1865c845">RTC_ALRMAR_MNU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac05e67cdb4da1882dd5b8f5a8fe51bb2">RTC_ALRMAR_MNU_Msk</a></td></tr>
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<tr class="memitem:gaeb5ead84647f92b0d1efcf8decb0dd8f" id="r_gaeb5ead84647f92b0d1efcf8decb0dd8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb5ead84647f92b0d1efcf8decb0dd8f">RTC_ALRMAR_MNU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fd9dea59596ad989af2bce818b1b93">RTC_ALRMAR_MNU_Pos</a>)</td></tr>
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<tr class="memitem:ga656311cb5632dbc9b4fb5dd2288a6e66" id="r_ga656311cb5632dbc9b4fb5dd2288a6e66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga656311cb5632dbc9b4fb5dd2288a6e66">RTC_ALRMAR_MNU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fd9dea59596ad989af2bce818b1b93">RTC_ALRMAR_MNU_Pos</a>)</td></tr>
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<tr class="memitem:gadc164d7ff70842858281cfaff5f29374" id="r_gadc164d7ff70842858281cfaff5f29374"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc164d7ff70842858281cfaff5f29374">RTC_ALRMAR_MNU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fd9dea59596ad989af2bce818b1b93">RTC_ALRMAR_MNU_Pos</a>)</td></tr>
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<tr class="memitem:ga4e1199b4140613e8a1dbe283dd89c772" id="r_ga4e1199b4140613e8a1dbe283dd89c772"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e1199b4140613e8a1dbe283dd89c772">RTC_ALRMAR_MNU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fd9dea59596ad989af2bce818b1b93">RTC_ALRMAR_MNU_Pos</a>)</td></tr>
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<tr class="memitem:gacbad0bb69a65557c15042154b66eab52" id="r_gacbad0bb69a65557c15042154b66eab52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbad0bb69a65557c15042154b66eab52">RTC_ALRMAR_MSK1_Pos</a>   (7U)</td></tr>
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<tr class="memitem:ga838b33a3595df6fe68152bb31f812beb" id="r_ga838b33a3595df6fe68152bb31f812beb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga838b33a3595df6fe68152bb31f812beb">RTC_ALRMAR_MSK1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacbad0bb69a65557c15042154b66eab52">RTC_ALRMAR_MSK1_Pos</a>)</td></tr>
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<tr class="memitem:ga8862250866a358ff3095852f45a160c1" id="r_ga8862250866a358ff3095852f45a160c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8862250866a358ff3095852f45a160c1">RTC_ALRMAR_MSK1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga838b33a3595df6fe68152bb31f812beb">RTC_ALRMAR_MSK1_Msk</a></td></tr>
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<tr class="memitem:ga83d9812296958846b0fd24484b205ebd" id="r_ga83d9812296958846b0fd24484b205ebd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83d9812296958846b0fd24484b205ebd">RTC_ALRMAR_ST_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga5f558ae0134c82f7f64c31a4d8bb33f0" id="r_ga5f558ae0134c82f7f64c31a4d8bb33f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f558ae0134c82f7f64c31a4d8bb33f0">RTC_ALRMAR_ST_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83d9812296958846b0fd24484b205ebd">RTC_ALRMAR_ST_Pos</a>)</td></tr>
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<tr class="memitem:ga0b623884457edb89f48a2a100aff183a" id="r_ga0b623884457edb89f48a2a100aff183a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b623884457edb89f48a2a100aff183a">RTC_ALRMAR_ST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f558ae0134c82f7f64c31a4d8bb33f0">RTC_ALRMAR_ST_Msk</a></td></tr>
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<tr class="memitem:gaae5c1ad41702da26788f5ef52c0d05ca" id="r_gaae5c1ad41702da26788f5ef52c0d05ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae5c1ad41702da26788f5ef52c0d05ca">RTC_ALRMAR_ST_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83d9812296958846b0fd24484b205ebd">RTC_ALRMAR_ST_Pos</a>)</td></tr>
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<tr class="separator:gaae5c1ad41702da26788f5ef52c0d05ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e771d8055c52a1186d3f47dd567457a" id="r_ga2e771d8055c52a1186d3f47dd567457a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e771d8055c52a1186d3f47dd567457a">RTC_ALRMAR_ST_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83d9812296958846b0fd24484b205ebd">RTC_ALRMAR_ST_Pos</a>)</td></tr>
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<tr class="memitem:ga7fdfe4a92c7ab0c326dc9f2638318f97" id="r_ga7fdfe4a92c7ab0c326dc9f2638318f97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fdfe4a92c7ab0c326dc9f2638318f97">RTC_ALRMAR_ST_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83d9812296958846b0fd24484b205ebd">RTC_ALRMAR_ST_Pos</a>)</td></tr>
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<tr class="separator:ga7fdfe4a92c7ab0c326dc9f2638318f97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30f4084231cdc1f72bec8c63dac981a3" id="r_ga30f4084231cdc1f72bec8c63dac981a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30f4084231cdc1f72bec8c63dac981a3">RTC_ALRMAR_SU_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga30f4084231cdc1f72bec8c63dac981a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37bf69143ae7921782d1baa390c1c866" id="r_ga37bf69143ae7921782d1baa390c1c866"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37bf69143ae7921782d1baa390c1c866">RTC_ALRMAR_SU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30f4084231cdc1f72bec8c63dac981a3">RTC_ALRMAR_SU_Pos</a>)</td></tr>
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<tr class="separator:ga37bf69143ae7921782d1baa390c1c866"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8ec4171be73457bc3dba78bd246e35b" id="r_gab8ec4171be73457bc3dba78bd246e35b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8ec4171be73457bc3dba78bd246e35b">RTC_ALRMAR_SU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga37bf69143ae7921782d1baa390c1c866">RTC_ALRMAR_SU_Msk</a></td></tr>
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<tr class="memitem:gaaaf99585af681202a201178f8156dffe" id="r_gaaaf99585af681202a201178f8156dffe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaaf99585af681202a201178f8156dffe">RTC_ALRMAR_SU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30f4084231cdc1f72bec8c63dac981a3">RTC_ALRMAR_SU_Pos</a>)</td></tr>
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<tr class="separator:gaaaf99585af681202a201178f8156dffe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d7edbd0609415ca3a328f8498c4a63c" id="r_ga9d7edbd0609415ca3a328f8498c4a63c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d7edbd0609415ca3a328f8498c4a63c">RTC_ALRMAR_SU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30f4084231cdc1f72bec8c63dac981a3">RTC_ALRMAR_SU_Pos</a>)</td></tr>
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<tr class="separator:ga9d7edbd0609415ca3a328f8498c4a63c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga485a8c274aa56f705dc1363484d7085f" id="r_ga485a8c274aa56f705dc1363484d7085f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga485a8c274aa56f705dc1363484d7085f">RTC_ALRMAR_SU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30f4084231cdc1f72bec8c63dac981a3">RTC_ALRMAR_SU_Pos</a>)</td></tr>
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<tr class="separator:ga485a8c274aa56f705dc1363484d7085f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9d41833996dbd77a0bfbcd9889957a2" id="r_gad9d41833996dbd77a0bfbcd9889957a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9d41833996dbd77a0bfbcd9889957a2">RTC_ALRMAR_SU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30f4084231cdc1f72bec8c63dac981a3">RTC_ALRMAR_SU_Pos</a>)</td></tr>
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<tr class="separator:gad9d41833996dbd77a0bfbcd9889957a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2383d51761039ce9b70e6a33bfde165a" id="r_ga2383d51761039ce9b70e6a33bfde165a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2383d51761039ce9b70e6a33bfde165a">RTC_ALRMBR_MSK4_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga2383d51761039ce9b70e6a33bfde165a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6359d5b79cd667e4f7f093e0d0ee8320" id="r_ga6359d5b79cd667e4f7f093e0d0ee8320"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6359d5b79cd667e4f7f093e0d0ee8320">RTC_ALRMBR_MSK4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2383d51761039ce9b70e6a33bfde165a">RTC_ALRMBR_MSK4_Pos</a>)</td></tr>
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<tr class="separator:ga6359d5b79cd667e4f7f093e0d0ee8320"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga934df96e83f72268528e62c55c03b50d" id="r_ga934df96e83f72268528e62c55c03b50d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga934df96e83f72268528e62c55c03b50d">RTC_ALRMBR_MSK4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6359d5b79cd667e4f7f093e0d0ee8320">RTC_ALRMBR_MSK4_Msk</a></td></tr>
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<tr class="separator:ga934df96e83f72268528e62c55c03b50d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac975a5ed682b832e8600dba67aa9ad37" id="r_gac975a5ed682b832e8600dba67aa9ad37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac975a5ed682b832e8600dba67aa9ad37">RTC_ALRMBR_WDSEL_Pos</a>   (30U)</td></tr>
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<tr class="separator:gac975a5ed682b832e8600dba67aa9ad37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff53d89da5c55043f8d32e800319b0c0" id="r_gaff53d89da5c55043f8d32e800319b0c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff53d89da5c55043f8d32e800319b0c0">RTC_ALRMBR_WDSEL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac975a5ed682b832e8600dba67aa9ad37">RTC_ALRMBR_WDSEL_Pos</a>)</td></tr>
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<tr class="separator:gaff53d89da5c55043f8d32e800319b0c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3acc5db599b055a0c1eca04024bf0285" id="r_ga3acc5db599b055a0c1eca04024bf0285"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3acc5db599b055a0c1eca04024bf0285">RTC_ALRMBR_WDSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaff53d89da5c55043f8d32e800319b0c0">RTC_ALRMBR_WDSEL_Msk</a></td></tr>
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<tr class="memitem:gade6a75b6e4614f322bf046e07cabc022" id="r_gade6a75b6e4614f322bf046e07cabc022"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade6a75b6e4614f322bf046e07cabc022">RTC_ALRMBR_DT_Pos</a>   (28U)</td></tr>
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<tr class="separator:gade6a75b6e4614f322bf046e07cabc022"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf438133a0350e3c1f9e956ea59c165e" id="r_gadf438133a0350e3c1f9e956ea59c165e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf438133a0350e3c1f9e956ea59c165e">RTC_ALRMBR_DT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade6a75b6e4614f322bf046e07cabc022">RTC_ALRMBR_DT_Pos</a>)</td></tr>
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<tr class="separator:gadf438133a0350e3c1f9e956ea59c165e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f8662da4b5f9f0dc0cdd8eac037052b" id="r_ga9f8662da4b5f9f0dc0cdd8eac037052b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f8662da4b5f9f0dc0cdd8eac037052b">RTC_ALRMBR_DT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadf438133a0350e3c1f9e956ea59c165e">RTC_ALRMBR_DT_Msk</a></td></tr>
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<tr class="separator:ga9f8662da4b5f9f0dc0cdd8eac037052b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34531fadcc9d2a702b3b7138831fb4c8" id="r_ga34531fadcc9d2a702b3b7138831fb4c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34531fadcc9d2a702b3b7138831fb4c8">RTC_ALRMBR_DT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade6a75b6e4614f322bf046e07cabc022">RTC_ALRMBR_DT_Pos</a>)</td></tr>
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<tr class="separator:ga34531fadcc9d2a702b3b7138831fb4c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabeb8410cfd578e600049846a694dc00d" id="r_gabeb8410cfd578e600049846a694dc00d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabeb8410cfd578e600049846a694dc00d">RTC_ALRMBR_DT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade6a75b6e4614f322bf046e07cabc022">RTC_ALRMBR_DT_Pos</a>)</td></tr>
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<tr class="separator:gabeb8410cfd578e600049846a694dc00d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga553d2edb82ee8d85c71f795276bb4bba" id="r_ga553d2edb82ee8d85c71f795276bb4bba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga553d2edb82ee8d85c71f795276bb4bba">RTC_ALRMBR_DU_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga553d2edb82ee8d85c71f795276bb4bba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba5234dbab35f4bcc6b1a49b633c9d83" id="r_gaba5234dbab35f4bcc6b1a49b633c9d83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba5234dbab35f4bcc6b1a49b633c9d83">RTC_ALRMBR_DU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga553d2edb82ee8d85c71f795276bb4bba">RTC_ALRMBR_DU_Pos</a>)</td></tr>
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<tr class="separator:gaba5234dbab35f4bcc6b1a49b633c9d83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0beeb5e7c9237d688d5784dba0a5c671" id="r_ga0beeb5e7c9237d688d5784dba0a5c671"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0beeb5e7c9237d688d5784dba0a5c671">RTC_ALRMBR_DU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba5234dbab35f4bcc6b1a49b633c9d83">RTC_ALRMBR_DU_Msk</a></td></tr>
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<tr class="memitem:gaf9886cb39e9c89c40ddc33c6e7659db5" id="r_gaf9886cb39e9c89c40ddc33c6e7659db5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9886cb39e9c89c40ddc33c6e7659db5">RTC_ALRMBR_DU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga553d2edb82ee8d85c71f795276bb4bba">RTC_ALRMBR_DU_Pos</a>)</td></tr>
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<tr class="memitem:ga121e8284bdc7ebd634f71e5810dc4f85" id="r_ga121e8284bdc7ebd634f71e5810dc4f85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga121e8284bdc7ebd634f71e5810dc4f85">RTC_ALRMBR_DU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga553d2edb82ee8d85c71f795276bb4bba">RTC_ALRMBR_DU_Pos</a>)</td></tr>
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<tr class="memitem:ga78b99f99d3666212ab673dbc9f7f3192" id="r_ga78b99f99d3666212ab673dbc9f7f3192"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78b99f99d3666212ab673dbc9f7f3192">RTC_ALRMBR_DU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga553d2edb82ee8d85c71f795276bb4bba">RTC_ALRMBR_DU_Pos</a>)</td></tr>
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<tr class="memitem:ga8551995a404be9f58511ea22dca71f1a" id="r_ga8551995a404be9f58511ea22dca71f1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8551995a404be9f58511ea22dca71f1a">RTC_ALRMBR_DU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga553d2edb82ee8d85c71f795276bb4bba">RTC_ALRMBR_DU_Pos</a>)</td></tr>
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<tr class="memitem:ga2424f9d237a98722a6276d7effa078b7" id="r_ga2424f9d237a98722a6276d7effa078b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2424f9d237a98722a6276d7effa078b7">RTC_ALRMBR_MSK3_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga2424f9d237a98722a6276d7effa078b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a10ef06416ab43ddcc978f7c484fd30" id="r_ga8a10ef06416ab43ddcc978f7c484fd30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a10ef06416ab43ddcc978f7c484fd30">RTC_ALRMBR_MSK3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2424f9d237a98722a6276d7effa078b7">RTC_ALRMBR_MSK3_Pos</a>)</td></tr>
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<tr class="memitem:gaca7cd93178102c8769d0874d5b8394c4" id="r_gaca7cd93178102c8769d0874d5b8394c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca7cd93178102c8769d0874d5b8394c4">RTC_ALRMBR_MSK3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a10ef06416ab43ddcc978f7c484fd30">RTC_ALRMBR_MSK3_Msk</a></td></tr>
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<tr class="separator:gaca7cd93178102c8769d0874d5b8394c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b091bf9f116760614f434cd54a8132e" id="r_ga7b091bf9f116760614f434cd54a8132e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b091bf9f116760614f434cd54a8132e">RTC_ALRMBR_PM_Pos</a>   (22U)</td></tr>
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<tr class="memitem:gafb73d11c2f8f01d03b143bf0eb50a3c1" id="r_gafb73d11c2f8f01d03b143bf0eb50a3c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb73d11c2f8f01d03b143bf0eb50a3c1">RTC_ALRMBR_PM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b091bf9f116760614f434cd54a8132e">RTC_ALRMBR_PM_Pos</a>)</td></tr>
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<tr class="memitem:ga4fc947f41bd2a091b13ffeff4312b67b" id="r_ga4fc947f41bd2a091b13ffeff4312b67b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fc947f41bd2a091b13ffeff4312b67b">RTC_ALRMBR_PM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb73d11c2f8f01d03b143bf0eb50a3c1">RTC_ALRMBR_PM_Msk</a></td></tr>
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<tr class="separator:ga4fc947f41bd2a091b13ffeff4312b67b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbe2cd364c4d4701876832245cf20ce1" id="r_gadbe2cd364c4d4701876832245cf20ce1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbe2cd364c4d4701876832245cf20ce1">RTC_ALRMBR_HT_Pos</a>   (20U)</td></tr>
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<tr class="memitem:gad1a64e9998a2032590d32d8e93ac89ad" id="r_gad1a64e9998a2032590d32d8e93ac89ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1a64e9998a2032590d32d8e93ac89ad">RTC_ALRMBR_HT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadbe2cd364c4d4701876832245cf20ce1">RTC_ALRMBR_HT_Pos</a>)</td></tr>
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<tr class="separator:gad1a64e9998a2032590d32d8e93ac89ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga552fbb873fbab8cefd1c5c3536d0989d" id="r_ga552fbb873fbab8cefd1c5c3536d0989d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga552fbb873fbab8cefd1c5c3536d0989d">RTC_ALRMBR_HT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad1a64e9998a2032590d32d8e93ac89ad">RTC_ALRMBR_HT_Msk</a></td></tr>
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<tr class="memitem:gabbddfb1b1ff41f1b76f5ccfb6eb29362" id="r_gabbddfb1b1ff41f1b76f5ccfb6eb29362"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbddfb1b1ff41f1b76f5ccfb6eb29362">RTC_ALRMBR_HT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadbe2cd364c4d4701876832245cf20ce1">RTC_ALRMBR_HT_Pos</a>)</td></tr>
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<tr class="separator:gabbddfb1b1ff41f1b76f5ccfb6eb29362"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3219c5b314ca459c8dcb93c140b210cb" id="r_ga3219c5b314ca459c8dcb93c140b210cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3219c5b314ca459c8dcb93c140b210cb">RTC_ALRMBR_HT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadbe2cd364c4d4701876832245cf20ce1">RTC_ALRMBR_HT_Pos</a>)</td></tr>
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<tr class="separator:ga3219c5b314ca459c8dcb93c140b210cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5880949c342cf52cc4596e73dc1f84e" id="r_gaf5880949c342cf52cc4596e73dc1f84e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5880949c342cf52cc4596e73dc1f84e">RTC_ALRMBR_HU_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga16f950667f6001e8b23b88b355cc072a" id="r_ga16f950667f6001e8b23b88b355cc072a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16f950667f6001e8b23b88b355cc072a">RTC_ALRMBR_HU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5880949c342cf52cc4596e73dc1f84e">RTC_ALRMBR_HU_Pos</a>)</td></tr>
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<tr class="memitem:ga1a01e42db93b9bc9097766d7ccf2d21d" id="r_ga1a01e42db93b9bc9097766d7ccf2d21d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a01e42db93b9bc9097766d7ccf2d21d">RTC_ALRMBR_HU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga16f950667f6001e8b23b88b355cc072a">RTC_ALRMBR_HU_Msk</a></td></tr>
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<tr class="memitem:ga0223058b7ae0a4ae57a7a7997440385e" id="r_ga0223058b7ae0a4ae57a7a7997440385e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0223058b7ae0a4ae57a7a7997440385e">RTC_ALRMBR_HU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5880949c342cf52cc4596e73dc1f84e">RTC_ALRMBR_HU_Pos</a>)</td></tr>
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<tr class="memitem:ga9a7c34c4e83f374790e3ed27a3e23443" id="r_ga9a7c34c4e83f374790e3ed27a3e23443"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a7c34c4e83f374790e3ed27a3e23443">RTC_ALRMBR_HU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5880949c342cf52cc4596e73dc1f84e">RTC_ALRMBR_HU_Pos</a>)</td></tr>
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<tr class="memitem:gad5e6d673134918e74d9a0f06ca4dc479" id="r_gad5e6d673134918e74d9a0f06ca4dc479"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5e6d673134918e74d9a0f06ca4dc479">RTC_ALRMBR_HU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5880949c342cf52cc4596e73dc1f84e">RTC_ALRMBR_HU_Pos</a>)</td></tr>
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<tr class="separator:gad5e6d673134918e74d9a0f06ca4dc479"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae538b44aa24031a294442dc47f6849f5" id="r_gae538b44aa24031a294442dc47f6849f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae538b44aa24031a294442dc47f6849f5">RTC_ALRMBR_HU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5880949c342cf52cc4596e73dc1f84e">RTC_ALRMBR_HU_Pos</a>)</td></tr>
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<tr class="separator:gae538b44aa24031a294442dc47f6849f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga757c08763995ee18cb34d7dd04a8f2d0" id="r_ga757c08763995ee18cb34d7dd04a8f2d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga757c08763995ee18cb34d7dd04a8f2d0">RTC_ALRMBR_MSK2_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga757c08763995ee18cb34d7dd04a8f2d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a678de5920eddb36f8edc45c992aa10" id="r_ga8a678de5920eddb36f8edc45c992aa10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a678de5920eddb36f8edc45c992aa10">RTC_ALRMBR_MSK2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga757c08763995ee18cb34d7dd04a8f2d0">RTC_ALRMBR_MSK2_Pos</a>)</td></tr>
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<tr class="memitem:ga124c24eb148681777758f1298776f5a1" id="r_ga124c24eb148681777758f1298776f5a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga124c24eb148681777758f1298776f5a1">RTC_ALRMBR_MSK2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a678de5920eddb36f8edc45c992aa10">RTC_ALRMBR_MSK2_Msk</a></td></tr>
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<tr class="memitem:ga995f7d294d4b202db6a6c06c0c40b325" id="r_ga995f7d294d4b202db6a6c06c0c40b325"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga995f7d294d4b202db6a6c06c0c40b325">RTC_ALRMBR_MNT_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga995f7d294d4b202db6a6c06c0c40b325"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4abe6f205a3aafc2fdd5930b06ca5250" id="r_ga4abe6f205a3aafc2fdd5930b06ca5250"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4abe6f205a3aafc2fdd5930b06ca5250">RTC_ALRMBR_MNT_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga995f7d294d4b202db6a6c06c0c40b325">RTC_ALRMBR_MNT_Pos</a>)</td></tr>
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<tr class="separator:ga4abe6f205a3aafc2fdd5930b06ca5250"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05e2ef0960c04023b98a104202f44571" id="r_ga05e2ef0960c04023b98a104202f44571"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05e2ef0960c04023b98a104202f44571">RTC_ALRMBR_MNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4abe6f205a3aafc2fdd5930b06ca5250">RTC_ALRMBR_MNT_Msk</a></td></tr>
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<tr class="memitem:gaf1170e6bedeafe4da96568080fe3bbe3" id="r_gaf1170e6bedeafe4da96568080fe3bbe3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1170e6bedeafe4da96568080fe3bbe3">RTC_ALRMBR_MNT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga995f7d294d4b202db6a6c06c0c40b325">RTC_ALRMBR_MNT_Pos</a>)</td></tr>
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<tr class="memitem:ga56977652001bc709e4c37fce5647eb40" id="r_ga56977652001bc709e4c37fce5647eb40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56977652001bc709e4c37fce5647eb40">RTC_ALRMBR_MNT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga995f7d294d4b202db6a6c06c0c40b325">RTC_ALRMBR_MNT_Pos</a>)</td></tr>
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<tr class="separator:ga56977652001bc709e4c37fce5647eb40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbdfd2b2b1fc039fe8efdd6df612b220" id="r_gafbdfd2b2b1fc039fe8efdd6df612b220"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbdfd2b2b1fc039fe8efdd6df612b220">RTC_ALRMBR_MNT_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga995f7d294d4b202db6a6c06c0c40b325">RTC_ALRMBR_MNT_Pos</a>)</td></tr>
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<tr class="memitem:gabec1334e452f9f973603fa7de232ec93" id="r_gabec1334e452f9f973603fa7de232ec93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabec1334e452f9f973603fa7de232ec93">RTC_ALRMBR_MNU_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga14ee879ec288fff19824ee589b54972b" id="r_ga14ee879ec288fff19824ee589b54972b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14ee879ec288fff19824ee589b54972b">RTC_ALRMBR_MNU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabec1334e452f9f973603fa7de232ec93">RTC_ALRMBR_MNU_Pos</a>)</td></tr>
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<tr class="memitem:ga3ca0feaf431b9f9dde4a9d97cae39056" id="r_ga3ca0feaf431b9f9dde4a9d97cae39056"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ca0feaf431b9f9dde4a9d97cae39056">RTC_ALRMBR_MNU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga14ee879ec288fff19824ee589b54972b">RTC_ALRMBR_MNU_Msk</a></td></tr>
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<tr class="memitem:ga93830709da4736a2e8da1cf3a3596dda" id="r_ga93830709da4736a2e8da1cf3a3596dda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93830709da4736a2e8da1cf3a3596dda">RTC_ALRMBR_MNU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabec1334e452f9f973603fa7de232ec93">RTC_ALRMBR_MNU_Pos</a>)</td></tr>
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<tr class="memitem:gae9cab4a9df6a1e45e2a3212b357e1bef" id="r_gae9cab4a9df6a1e45e2a3212b357e1bef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9cab4a9df6a1e45e2a3212b357e1bef">RTC_ALRMBR_MNU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabec1334e452f9f973603fa7de232ec93">RTC_ALRMBR_MNU_Pos</a>)</td></tr>
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<tr class="memitem:ga869e14a514b3d140a2dcad669e2ab3e0" id="r_ga869e14a514b3d140a2dcad669e2ab3e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga869e14a514b3d140a2dcad669e2ab3e0">RTC_ALRMBR_MNU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabec1334e452f9f973603fa7de232ec93">RTC_ALRMBR_MNU_Pos</a>)</td></tr>
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<tr class="memitem:gaec666ddc3d2c205d46d4e1e5bdcf9243" id="r_gaec666ddc3d2c205d46d4e1e5bdcf9243"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec666ddc3d2c205d46d4e1e5bdcf9243">RTC_ALRMBR_MNU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabec1334e452f9f973603fa7de232ec93">RTC_ALRMBR_MNU_Pos</a>)</td></tr>
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<tr class="separator:gaec666ddc3d2c205d46d4e1e5bdcf9243"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46564dcbbf9eec8854fa091155045f90" id="r_ga46564dcbbf9eec8854fa091155045f90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46564dcbbf9eec8854fa091155045f90">RTC_ALRMBR_MSK1_Pos</a>   (7U)</td></tr>
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<tr class="memitem:ga7f741db655cf45b9b6b254c491f3738d" id="r_ga7f741db655cf45b9b6b254c491f3738d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f741db655cf45b9b6b254c491f3738d">RTC_ALRMBR_MSK1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46564dcbbf9eec8854fa091155045f90">RTC_ALRMBR_MSK1_Pos</a>)</td></tr>
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<tr class="separator:ga7f741db655cf45b9b6b254c491f3738d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa472193eb2ace80c95874c850236b489" id="r_gaa472193eb2ace80c95874c850236b489"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa472193eb2ace80c95874c850236b489">RTC_ALRMBR_MSK1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f741db655cf45b9b6b254c491f3738d">RTC_ALRMBR_MSK1_Msk</a></td></tr>
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<tr class="memitem:ga62ce834a2d4f2d1b2d338b1e8da054d5" id="r_ga62ce834a2d4f2d1b2d338b1e8da054d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62ce834a2d4f2d1b2d338b1e8da054d5">RTC_ALRMBR_ST_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga62ce834a2d4f2d1b2d338b1e8da054d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c1a51469b2ad8675eeee8a39ea29ff7" id="r_ga2c1a51469b2ad8675eeee8a39ea29ff7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c1a51469b2ad8675eeee8a39ea29ff7">RTC_ALRMBR_ST_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga62ce834a2d4f2d1b2d338b1e8da054d5">RTC_ALRMBR_ST_Pos</a>)</td></tr>
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<tr class="separator:ga2c1a51469b2ad8675eeee8a39ea29ff7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7a6c70156cd32b6aa855e4f2e32406c" id="r_gad7a6c70156cd32b6aa855e4f2e32406c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7a6c70156cd32b6aa855e4f2e32406c">RTC_ALRMBR_ST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c1a51469b2ad8675eeee8a39ea29ff7">RTC_ALRMBR_ST_Msk</a></td></tr>
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<tr class="separator:gad7a6c70156cd32b6aa855e4f2e32406c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2514a54011c9ff7b48939e9cbd13f859" id="r_ga2514a54011c9ff7b48939e9cbd13f859"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2514a54011c9ff7b48939e9cbd13f859">RTC_ALRMBR_ST_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga62ce834a2d4f2d1b2d338b1e8da054d5">RTC_ALRMBR_ST_Pos</a>)</td></tr>
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<tr class="separator:ga2514a54011c9ff7b48939e9cbd13f859"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6b6e10efeaeac2898a754e2a360fb27" id="r_gad6b6e10efeaeac2898a754e2a360fb27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6b6e10efeaeac2898a754e2a360fb27">RTC_ALRMBR_ST_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga62ce834a2d4f2d1b2d338b1e8da054d5">RTC_ALRMBR_ST_Pos</a>)</td></tr>
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<tr class="separator:gad6b6e10efeaeac2898a754e2a360fb27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga423e1673ab928b5e43e9fa9b65d2122c" id="r_ga423e1673ab928b5e43e9fa9b65d2122c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga423e1673ab928b5e43e9fa9b65d2122c">RTC_ALRMBR_ST_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga62ce834a2d4f2d1b2d338b1e8da054d5">RTC_ALRMBR_ST_Pos</a>)</td></tr>
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<tr class="separator:ga423e1673ab928b5e43e9fa9b65d2122c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef14da4012b4e250c549154393537c3b" id="r_gaef14da4012b4e250c549154393537c3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef14da4012b4e250c549154393537c3b">RTC_ALRMBR_SU_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaef14da4012b4e250c549154393537c3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b09e067d4a36bd9c6a85ec3193da6d2" id="r_ga8b09e067d4a36bd9c6a85ec3193da6d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b09e067d4a36bd9c6a85ec3193da6d2">RTC_ALRMBR_SU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef14da4012b4e250c549154393537c3b">RTC_ALRMBR_SU_Pos</a>)</td></tr>
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<tr class="separator:ga8b09e067d4a36bd9c6a85ec3193da6d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2fdd1ad6a4b7db36ece6145cba49ccf" id="r_gae2fdd1ad6a4b7db36ece6145cba49ccf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2fdd1ad6a4b7db36ece6145cba49ccf">RTC_ALRMBR_SU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b09e067d4a36bd9c6a85ec3193da6d2">RTC_ALRMBR_SU_Msk</a></td></tr>
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<tr class="separator:gae2fdd1ad6a4b7db36ece6145cba49ccf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1aa325b93084bf6fdc494842e1f0b652" id="r_ga1aa325b93084bf6fdc494842e1f0b652"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1aa325b93084bf6fdc494842e1f0b652">RTC_ALRMBR_SU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef14da4012b4e250c549154393537c3b">RTC_ALRMBR_SU_Pos</a>)</td></tr>
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<tr class="separator:ga1aa325b93084bf6fdc494842e1f0b652"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72ed3dd8ae6a59462a99f8c3d8c316e5" id="r_ga72ed3dd8ae6a59462a99f8c3d8c316e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72ed3dd8ae6a59462a99f8c3d8c316e5">RTC_ALRMBR_SU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef14da4012b4e250c549154393537c3b">RTC_ALRMBR_SU_Pos</a>)</td></tr>
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<tr class="separator:ga72ed3dd8ae6a59462a99f8c3d8c316e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac21f97b7b207139ffb0d1e6ede81bb91" id="r_gac21f97b7b207139ffb0d1e6ede81bb91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac21f97b7b207139ffb0d1e6ede81bb91">RTC_ALRMBR_SU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef14da4012b4e250c549154393537c3b">RTC_ALRMBR_SU_Pos</a>)</td></tr>
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<tr class="separator:gac21f97b7b207139ffb0d1e6ede81bb91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b548175b400ee92c11c2c446d6d129b" id="r_ga9b548175b400ee92c11c2c446d6d129b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b548175b400ee92c11c2c446d6d129b">RTC_ALRMBR_SU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef14da4012b4e250c549154393537c3b">RTC_ALRMBR_SU_Pos</a>)</td></tr>
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<tr class="separator:ga9b548175b400ee92c11c2c446d6d129b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8567138f5a3dddde68b6cdda56e41846" id="r_ga8567138f5a3dddde68b6cdda56e41846"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8567138f5a3dddde68b6cdda56e41846">RTC_WPR_KEY_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8567138f5a3dddde68b6cdda56e41846"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81983eda15eb251ae9e94a8290450cb1" id="r_ga81983eda15eb251ae9e94a8290450cb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81983eda15eb251ae9e94a8290450cb1">RTC_WPR_KEY_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8567138f5a3dddde68b6cdda56e41846">RTC_WPR_KEY_Pos</a>)</td></tr>
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<tr class="separator:ga81983eda15eb251ae9e94a8290450cb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d21f29da0e92b2744719aab37278b07" id="r_ga2d21f29da0e92b2744719aab37278b07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d21f29da0e92b2744719aab37278b07">RTC_WPR_KEY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga81983eda15eb251ae9e94a8290450cb1">RTC_WPR_KEY_Msk</a></td></tr>
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<tr class="separator:ga2d21f29da0e92b2744719aab37278b07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8cf2c5e2058a406fcb12ef8263f4bf7" id="r_gaf8cf2c5e2058a406fcb12ef8263f4bf7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8cf2c5e2058a406fcb12ef8263f4bf7">RTC_SSR_SS_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf8cf2c5e2058a406fcb12ef8263f4bf7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e04530ca01c9863f847c09f51f64304" id="r_ga7e04530ca01c9863f847c09f51f64304"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e04530ca01c9863f847c09f51f64304">RTC_SSR_SS_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8cf2c5e2058a406fcb12ef8263f4bf7">RTC_SSR_SS_Pos</a>)</td></tr>
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<tr class="separator:ga7e04530ca01c9863f847c09f51f64304"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3881f27b6c7a5c7609b1393682144aed" id="r_ga3881f27b6c7a5c7609b1393682144aed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3881f27b6c7a5c7609b1393682144aed">RTC_SSR_SS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e04530ca01c9863f847c09f51f64304">RTC_SSR_SS_Msk</a></td></tr>
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<tr class="separator:ga3881f27b6c7a5c7609b1393682144aed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga043d4cba6c3d17ce136ed8e8fc6ae318" id="r_ga043d4cba6c3d17ce136ed8e8fc6ae318"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga043d4cba6c3d17ce136ed8e8fc6ae318">RTC_SHIFTR_SUBFS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga043d4cba6c3d17ce136ed8e8fc6ae318"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58c15ddd7f663060a1e540ded10aab86" id="r_ga58c15ddd7f663060a1e540ded10aab86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58c15ddd7f663060a1e540ded10aab86">RTC_SHIFTR_SUBFS_Msk</a>   (0x7FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga043d4cba6c3d17ce136ed8e8fc6ae318">RTC_SHIFTR_SUBFS_Pos</a>)</td></tr>
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<tr class="separator:ga58c15ddd7f663060a1e540ded10aab86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6131eb8c293b98bc5a6c7a4bb1920450" id="r_ga6131eb8c293b98bc5a6c7a4bb1920450"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6131eb8c293b98bc5a6c7a4bb1920450">RTC_SHIFTR_SUBFS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga58c15ddd7f663060a1e540ded10aab86">RTC_SHIFTR_SUBFS_Msk</a></td></tr>
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<tr class="memitem:gab0fdeb64a850c9840a1c140203e61d2f" id="r_gab0fdeb64a850c9840a1c140203e61d2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0fdeb64a850c9840a1c140203e61d2f">RTC_SHIFTR_ADD1S_Pos</a>   (31U)</td></tr>
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<tr class="memitem:ga145edd31d622a96121168d7f54af1f63" id="r_ga145edd31d622a96121168d7f54af1f63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga145edd31d622a96121168d7f54af1f63">RTC_SHIFTR_ADD1S_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab0fdeb64a850c9840a1c140203e61d2f">RTC_SHIFTR_ADD1S_Pos</a>)</td></tr>
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<tr class="separator:ga145edd31d622a96121168d7f54af1f63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fee932563d21382db9ecad458356af2" id="r_ga8fee932563d21382db9ecad458356af2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fee932563d21382db9ecad458356af2">RTC_SHIFTR_ADD1S</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga145edd31d622a96121168d7f54af1f63">RTC_SHIFTR_ADD1S_Msk</a></td></tr>
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<tr class="memitem:ga9c6a72f9bab0b1783762c3c612d5a0e6" id="r_ga9c6a72f9bab0b1783762c3c612d5a0e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c6a72f9bab0b1783762c3c612d5a0e6">RTC_TSTR_PM_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga9c6a72f9bab0b1783762c3c612d5a0e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga844125f323c84655caa5d09de90d676a" id="r_ga844125f323c84655caa5d09de90d676a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga844125f323c84655caa5d09de90d676a">RTC_TSTR_PM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c6a72f9bab0b1783762c3c612d5a0e6">RTC_TSTR_PM_Pos</a>)</td></tr>
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<tr class="memitem:ga84b3d044be3e63573a5f0d4d14d8e3b0" id="r_ga84b3d044be3e63573a5f0d4d14d8e3b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84b3d044be3e63573a5f0d4d14d8e3b0">RTC_TSTR_PM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga844125f323c84655caa5d09de90d676a">RTC_TSTR_PM_Msk</a></td></tr>
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<tr class="memitem:ga380cea6fd8d7736ad8d83bce9c6f4379" id="r_ga380cea6fd8d7736ad8d83bce9c6f4379"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga380cea6fd8d7736ad8d83bce9c6f4379">RTC_TSTR_HT_Pos</a>   (20U)</td></tr>
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<tr class="memitem:gae1c592f62a64ad486af67101a02badba" id="r_gae1c592f62a64ad486af67101a02badba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1c592f62a64ad486af67101a02badba">RTC_TSTR_HT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga380cea6fd8d7736ad8d83bce9c6f4379">RTC_TSTR_HT_Pos</a>)</td></tr>
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<tr class="memitem:ga5765274cda5284899563191cb505235a" id="r_ga5765274cda5284899563191cb505235a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5765274cda5284899563191cb505235a">RTC_TSTR_HT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae1c592f62a64ad486af67101a02badba">RTC_TSTR_HT_Msk</a></td></tr>
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<tr class="separator:ga5765274cda5284899563191cb505235a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b682daaa79917786d55c2bf44a80325" id="r_ga3b682daaa79917786d55c2bf44a80325"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b682daaa79917786d55c2bf44a80325">RTC_TSTR_HT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga380cea6fd8d7736ad8d83bce9c6f4379">RTC_TSTR_HT_Pos</a>)</td></tr>
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<tr class="memitem:ga9a35c1a1f98f2aeb73235d940922f9cf" id="r_ga9a35c1a1f98f2aeb73235d940922f9cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a35c1a1f98f2aeb73235d940922f9cf">RTC_TSTR_HT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga380cea6fd8d7736ad8d83bce9c6f4379">RTC_TSTR_HT_Pos</a>)</td></tr>
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<tr class="separator:ga9a35c1a1f98f2aeb73235d940922f9cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab82c3482dd42a99d0a28d52cfb89be11" id="r_gab82c3482dd42a99d0a28d52cfb89be11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab82c3482dd42a99d0a28d52cfb89be11">RTC_TSTR_HU_Pos</a>   (16U)</td></tr>
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<tr class="separator:gab82c3482dd42a99d0a28d52cfb89be11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bd9c8067bccd2967bbbb5cd3bad9375" id="r_ga4bd9c8067bccd2967bbbb5cd3bad9375"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bd9c8067bccd2967bbbb5cd3bad9375">RTC_TSTR_HU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab82c3482dd42a99d0a28d52cfb89be11">RTC_TSTR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga4bd9c8067bccd2967bbbb5cd3bad9375"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf12107fe82e4f9de5ae4fdd6c169a846" id="r_gaf12107fe82e4f9de5ae4fdd6c169a846"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf12107fe82e4f9de5ae4fdd6c169a846">RTC_TSTR_HU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bd9c8067bccd2967bbbb5cd3bad9375">RTC_TSTR_HU_Msk</a></td></tr>
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<tr class="separator:gaf12107fe82e4f9de5ae4fdd6c169a846"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a235fd8965c706e7f57327f6e5ce72d" id="r_ga1a235fd8965c706e7f57327f6e5ce72d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a235fd8965c706e7f57327f6e5ce72d">RTC_TSTR_HU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab82c3482dd42a99d0a28d52cfb89be11">RTC_TSTR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga1a235fd8965c706e7f57327f6e5ce72d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56f2bc31a8d01d7621de40d146b15fb7" id="r_ga56f2bc31a8d01d7621de40d146b15fb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56f2bc31a8d01d7621de40d146b15fb7">RTC_TSTR_HU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab82c3482dd42a99d0a28d52cfb89be11">RTC_TSTR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga56f2bc31a8d01d7621de40d146b15fb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d848f11cf3130bb6560d117f97b7da3" id="r_ga5d848f11cf3130bb6560d117f97b7da3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d848f11cf3130bb6560d117f97b7da3">RTC_TSTR_HU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab82c3482dd42a99d0a28d52cfb89be11">RTC_TSTR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga5d848f11cf3130bb6560d117f97b7da3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga703c813d88b2c9ab350cb0218ff4bbe7" id="r_ga703c813d88b2c9ab350cb0218ff4bbe7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga703c813d88b2c9ab350cb0218ff4bbe7">RTC_TSTR_HU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab82c3482dd42a99d0a28d52cfb89be11">RTC_TSTR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga703c813d88b2c9ab350cb0218ff4bbe7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae41110f902c7d1b538021d157da48a23" id="r_gae41110f902c7d1b538021d157da48a23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae41110f902c7d1b538021d157da48a23">RTC_TSTR_MNT_Pos</a>   (12U)</td></tr>
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<tr class="separator:gae41110f902c7d1b538021d157da48a23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7eefd1e26e643f63b5550cebcfb7a597" id="r_ga7eefd1e26e643f63b5550cebcfb7a597"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7eefd1e26e643f63b5550cebcfb7a597">RTC_TSTR_MNT_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae41110f902c7d1b538021d157da48a23">RTC_TSTR_MNT_Pos</a>)</td></tr>
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<tr class="separator:ga7eefd1e26e643f63b5550cebcfb7a597"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9743a3843868c712945a7c408183ad73" id="r_ga9743a3843868c712945a7c408183ad73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9743a3843868c712945a7c408183ad73">RTC_TSTR_MNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7eefd1e26e643f63b5550cebcfb7a597">RTC_TSTR_MNT_Msk</a></td></tr>
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<tr class="separator:ga9743a3843868c712945a7c408183ad73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf04bea9e3f4645257b8bd955f3ba80ce" id="r_gaf04bea9e3f4645257b8bd955f3ba80ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf04bea9e3f4645257b8bd955f3ba80ce">RTC_TSTR_MNT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae41110f902c7d1b538021d157da48a23">RTC_TSTR_MNT_Pos</a>)</td></tr>
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<tr class="separator:gaf04bea9e3f4645257b8bd955f3ba80ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf30459ae8455ad0fb382dd866446c83" id="r_gadf30459ae8455ad0fb382dd866446c83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf30459ae8455ad0fb382dd866446c83">RTC_TSTR_MNT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae41110f902c7d1b538021d157da48a23">RTC_TSTR_MNT_Pos</a>)</td></tr>
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<tr class="separator:gadf30459ae8455ad0fb382dd866446c83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga513f78562b18cfc36f52e80be9cb20d5" id="r_ga513f78562b18cfc36f52e80be9cb20d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga513f78562b18cfc36f52e80be9cb20d5">RTC_TSTR_MNT_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae41110f902c7d1b538021d157da48a23">RTC_TSTR_MNT_Pos</a>)</td></tr>
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<tr class="separator:ga513f78562b18cfc36f52e80be9cb20d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada4e4f24245be3e28d06c606bb1bd9e8" id="r_gada4e4f24245be3e28d06c606bb1bd9e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada4e4f24245be3e28d06c606bb1bd9e8">RTC_TSTR_MNU_Pos</a>   (8U)</td></tr>
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<tr class="separator:gada4e4f24245be3e28d06c606bb1bd9e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga989ebeea3d902970e5189c667f08dd57" id="r_ga989ebeea3d902970e5189c667f08dd57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga989ebeea3d902970e5189c667f08dd57">RTC_TSTR_MNU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada4e4f24245be3e28d06c606bb1bd9e8">RTC_TSTR_MNU_Pos</a>)</td></tr>
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<tr class="separator:ga989ebeea3d902970e5189c667f08dd57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64b186af486822cc015cfec613f5cba9" id="r_ga64b186af486822cc015cfec613f5cba9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64b186af486822cc015cfec613f5cba9">RTC_TSTR_MNU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga989ebeea3d902970e5189c667f08dd57">RTC_TSTR_MNU_Msk</a></td></tr>
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<tr class="separator:ga64b186af486822cc015cfec613f5cba9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8ff1f79f2ab33d00a979979d486bc44" id="r_gab8ff1f79f2ab33d00a979979d486bc44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8ff1f79f2ab33d00a979979d486bc44">RTC_TSTR_MNU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada4e4f24245be3e28d06c606bb1bd9e8">RTC_TSTR_MNU_Pos</a>)</td></tr>
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<tr class="separator:gab8ff1f79f2ab33d00a979979d486bc44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga506d192fef16558c9b0b7ed9e1a9147c" id="r_ga506d192fef16558c9b0b7ed9e1a9147c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga506d192fef16558c9b0b7ed9e1a9147c">RTC_TSTR_MNU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada4e4f24245be3e28d06c606bb1bd9e8">RTC_TSTR_MNU_Pos</a>)</td></tr>
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<tr class="separator:ga506d192fef16558c9b0b7ed9e1a9147c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga407a93c758b95a1ebf3c41c36fb6f07e" id="r_ga407a93c758b95a1ebf3c41c36fb6f07e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga407a93c758b95a1ebf3c41c36fb6f07e">RTC_TSTR_MNU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada4e4f24245be3e28d06c606bb1bd9e8">RTC_TSTR_MNU_Pos</a>)</td></tr>
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<tr class="separator:ga407a93c758b95a1ebf3c41c36fb6f07e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac55cd85d2e58a819637d15f70f7179a0" id="r_gac55cd85d2e58a819637d15f70f7179a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac55cd85d2e58a819637d15f70f7179a0">RTC_TSTR_MNU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada4e4f24245be3e28d06c606bb1bd9e8">RTC_TSTR_MNU_Pos</a>)</td></tr>
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<tr class="memitem:ga8a4e53ced662f212e19f30ccf60fdf74" id="r_ga8a4e53ced662f212e19f30ccf60fdf74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a4e53ced662f212e19f30ccf60fdf74">RTC_TSTR_ST_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga653df3d0cdd6c8235762f5152dda55c9" id="r_ga653df3d0cdd6c8235762f5152dda55c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga653df3d0cdd6c8235762f5152dda55c9">RTC_TSTR_ST_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a4e53ced662f212e19f30ccf60fdf74">RTC_TSTR_ST_Pos</a>)</td></tr>
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<tr class="memitem:ga9fbdebcd1da2ea191cca51c222345f15" id="r_ga9fbdebcd1da2ea191cca51c222345f15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fbdebcd1da2ea191cca51c222345f15">RTC_TSTR_ST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga653df3d0cdd6c8235762f5152dda55c9">RTC_TSTR_ST_Msk</a></td></tr>
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<tr class="memitem:ga90d733a561ad71ee4c63c4e0a3ed5f32" id="r_ga90d733a561ad71ee4c63c4e0a3ed5f32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90d733a561ad71ee4c63c4e0a3ed5f32">RTC_TSTR_ST_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a4e53ced662f212e19f30ccf60fdf74">RTC_TSTR_ST_Pos</a>)</td></tr>
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<tr class="memitem:ga807073dc98612721530a79df5b5c265a" id="r_ga807073dc98612721530a79df5b5c265a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga807073dc98612721530a79df5b5c265a">RTC_TSTR_ST_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a4e53ced662f212e19f30ccf60fdf74">RTC_TSTR_ST_Pos</a>)</td></tr>
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<tr class="memitem:gaee05d278bdd457b4f61d797e45520d13" id="r_gaee05d278bdd457b4f61d797e45520d13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee05d278bdd457b4f61d797e45520d13">RTC_TSTR_ST_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a4e53ced662f212e19f30ccf60fdf74">RTC_TSTR_ST_Pos</a>)</td></tr>
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<tr class="memitem:ga24f2a25eab6521118adf40765216cfe4" id="r_ga24f2a25eab6521118adf40765216cfe4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24f2a25eab6521118adf40765216cfe4">RTC_TSTR_SU_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gaf868c2dda50075428856aa7551f712c4" id="r_gaf868c2dda50075428856aa7551f712c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf868c2dda50075428856aa7551f712c4">RTC_TSTR_SU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24f2a25eab6521118adf40765216cfe4">RTC_TSTR_SU_Pos</a>)</td></tr>
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<tr class="memitem:gac0d8fa76d45faccfe931d6227b29565a" id="r_gac0d8fa76d45faccfe931d6227b29565a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0d8fa76d45faccfe931d6227b29565a">RTC_TSTR_SU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf868c2dda50075428856aa7551f712c4">RTC_TSTR_SU_Msk</a></td></tr>
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<tr class="memitem:ga8990f4d1d493012289778e854c52e97e" id="r_ga8990f4d1d493012289778e854c52e97e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8990f4d1d493012289778e854c52e97e">RTC_TSTR_SU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24f2a25eab6521118adf40765216cfe4">RTC_TSTR_SU_Pos</a>)</td></tr>
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<tr class="memitem:gaab6f4275d2a15e7307363124c03a64a4" id="r_gaab6f4275d2a15e7307363124c03a64a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab6f4275d2a15e7307363124c03a64a4">RTC_TSTR_SU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24f2a25eab6521118adf40765216cfe4">RTC_TSTR_SU_Pos</a>)</td></tr>
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<tr class="memitem:ga5610b3103a8a6653204f4fe7e9ea8587" id="r_ga5610b3103a8a6653204f4fe7e9ea8587"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5610b3103a8a6653204f4fe7e9ea8587">RTC_TSTR_SU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24f2a25eab6521118adf40765216cfe4">RTC_TSTR_SU_Pos</a>)</td></tr>
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<tr class="memitem:ga28790ae937a50ba6fb4aff5a9f5afbcb" id="r_ga28790ae937a50ba6fb4aff5a9f5afbcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28790ae937a50ba6fb4aff5a9f5afbcb">RTC_TSTR_SU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24f2a25eab6521118adf40765216cfe4">RTC_TSTR_SU_Pos</a>)</td></tr>
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<tr class="separator:ga28790ae937a50ba6fb4aff5a9f5afbcb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac365337a0d8e54ad40e3d4abeba10d33" id="r_gac365337a0d8e54ad40e3d4abeba10d33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac365337a0d8e54ad40e3d4abeba10d33">RTC_TSDR_WDU_Pos</a>   (13U)</td></tr>
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<tr class="memitem:gaa9022409e82c29cf18da7efe49032caf" id="r_gaa9022409e82c29cf18da7efe49032caf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9022409e82c29cf18da7efe49032caf">RTC_TSDR_WDU_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac365337a0d8e54ad40e3d4abeba10d33">RTC_TSDR_WDU_Pos</a>)</td></tr>
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<tr class="memitem:ga4c76ea431470b87f22e7854bd5438d2f" id="r_ga4c76ea431470b87f22e7854bd5438d2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c76ea431470b87f22e7854bd5438d2f">RTC_TSDR_WDU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9022409e82c29cf18da7efe49032caf">RTC_TSDR_WDU_Msk</a></td></tr>
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<tr class="memitem:ga4e9cbf062e41eecacccde522e24452c1" id="r_ga4e9cbf062e41eecacccde522e24452c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e9cbf062e41eecacccde522e24452c1">RTC_TSDR_WDU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac365337a0d8e54ad40e3d4abeba10d33">RTC_TSDR_WDU_Pos</a>)</td></tr>
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<tr class="separator:ga4e9cbf062e41eecacccde522e24452c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44259df3c6dc88e8168c7dcd5e6abf91" id="r_ga44259df3c6dc88e8168c7dcd5e6abf91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44259df3c6dc88e8168c7dcd5e6abf91">RTC_TSDR_WDU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac365337a0d8e54ad40e3d4abeba10d33">RTC_TSDR_WDU_Pos</a>)</td></tr>
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<tr class="separator:ga44259df3c6dc88e8168c7dcd5e6abf91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f2add59486679cc53f521c139d72852" id="r_ga7f2add59486679cc53f521c139d72852"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f2add59486679cc53f521c139d72852">RTC_TSDR_WDU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac365337a0d8e54ad40e3d4abeba10d33">RTC_TSDR_WDU_Pos</a>)</td></tr>
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<tr class="memitem:ga2b1a8d81075b72d48e99990de9a22f98" id="r_ga2b1a8d81075b72d48e99990de9a22f98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b1a8d81075b72d48e99990de9a22f98">RTC_TSDR_MT_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga2b1a8d81075b72d48e99990de9a22f98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab11fc35bffeed3dbfb7f08e75f8319da" id="r_gab11fc35bffeed3dbfb7f08e75f8319da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab11fc35bffeed3dbfb7f08e75f8319da">RTC_TSDR_MT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b1a8d81075b72d48e99990de9a22f98">RTC_TSDR_MT_Pos</a>)</td></tr>
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<tr class="separator:gab11fc35bffeed3dbfb7f08e75f8319da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7bce43482443f2038a8eebc681067dd7" id="r_ga7bce43482443f2038a8eebc681067dd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7bce43482443f2038a8eebc681067dd7">RTC_TSDR_MT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab11fc35bffeed3dbfb7f08e75f8319da">RTC_TSDR_MT_Msk</a></td></tr>
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<tr class="separator:ga7bce43482443f2038a8eebc681067dd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30556fea7362882afb160a1108ef0539" id="r_ga30556fea7362882afb160a1108ef0539"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30556fea7362882afb160a1108ef0539">RTC_TSDR_MU_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga30556fea7362882afb160a1108ef0539"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85638fe2912aec33b38fcfc51e97aa2e" id="r_ga85638fe2912aec33b38fcfc51e97aa2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85638fe2912aec33b38fcfc51e97aa2e">RTC_TSDR_MU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30556fea7362882afb160a1108ef0539">RTC_TSDR_MU_Pos</a>)</td></tr>
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<tr class="separator:ga85638fe2912aec33b38fcfc51e97aa2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a5912337df16624b4703d2065c5fdf4" id="r_ga2a5912337df16624b4703d2065c5fdf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5912337df16624b4703d2065c5fdf4">RTC_TSDR_MU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga85638fe2912aec33b38fcfc51e97aa2e">RTC_TSDR_MU_Msk</a></td></tr>
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<tr class="separator:ga2a5912337df16624b4703d2065c5fdf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9cf9d23d49e121268a25445a7eed2f35" id="r_ga9cf9d23d49e121268a25445a7eed2f35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cf9d23d49e121268a25445a7eed2f35">RTC_TSDR_MU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30556fea7362882afb160a1108ef0539">RTC_TSDR_MU_Pos</a>)</td></tr>
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<tr class="separator:ga9cf9d23d49e121268a25445a7eed2f35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49093134e4ead8b4990e5e1628db0692" id="r_ga49093134e4ead8b4990e5e1628db0692"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49093134e4ead8b4990e5e1628db0692">RTC_TSDR_MU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30556fea7362882afb160a1108ef0539">RTC_TSDR_MU_Pos</a>)</td></tr>
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<tr class="separator:ga49093134e4ead8b4990e5e1628db0692"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7f31eb674f5a67402b6a3eb578b70a5" id="r_gad7f31eb674f5a67402b6a3eb578b70a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7f31eb674f5a67402b6a3eb578b70a5">RTC_TSDR_MU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30556fea7362882afb160a1108ef0539">RTC_TSDR_MU_Pos</a>)</td></tr>
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<tr class="separator:gad7f31eb674f5a67402b6a3eb578b70a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad67666c54ef1be79a500484a5e755827" id="r_gad67666c54ef1be79a500484a5e755827"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad67666c54ef1be79a500484a5e755827">RTC_TSDR_MU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30556fea7362882afb160a1108ef0539">RTC_TSDR_MU_Pos</a>)</td></tr>
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<tr class="separator:gad67666c54ef1be79a500484a5e755827"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02d8e7630640b836002e20b25726e7f8" id="r_ga02d8e7630640b836002e20b25726e7f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02d8e7630640b836002e20b25726e7f8">RTC_TSDR_DT_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga02d8e7630640b836002e20b25726e7f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4e5fcdf15ef6bff31a9fa1857f88811" id="r_gaa4e5fcdf15ef6bff31a9fa1857f88811"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4e5fcdf15ef6bff31a9fa1857f88811">RTC_TSDR_DT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02d8e7630640b836002e20b25726e7f8">RTC_TSDR_DT_Pos</a>)</td></tr>
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<tr class="separator:gaa4e5fcdf15ef6bff31a9fa1857f88811"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39c9ff61f3b622b829aa9354ca84e44e" id="r_ga39c9ff61f3b622b829aa9354ca84e44e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39c9ff61f3b622b829aa9354ca84e44e">RTC_TSDR_DT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4e5fcdf15ef6bff31a9fa1857f88811">RTC_TSDR_DT_Msk</a></td></tr>
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<tr class="memitem:ga81e02a917946bddaa027a04538576533" id="r_ga81e02a917946bddaa027a04538576533"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81e02a917946bddaa027a04538576533">RTC_TSDR_DT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02d8e7630640b836002e20b25726e7f8">RTC_TSDR_DT_Pos</a>)</td></tr>
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<tr class="memitem:ga886739ae0e8c0f6144dbd774c203ed5f" id="r_ga886739ae0e8c0f6144dbd774c203ed5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga886739ae0e8c0f6144dbd774c203ed5f">RTC_TSDR_DT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02d8e7630640b836002e20b25726e7f8">RTC_TSDR_DT_Pos</a>)</td></tr>
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<tr class="memitem:ga031ca4fddcc1f40b7db8b46ec32ed60c" id="r_ga031ca4fddcc1f40b7db8b46ec32ed60c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga031ca4fddcc1f40b7db8b46ec32ed60c">RTC_TSDR_DU_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga031ca4fddcc1f40b7db8b46ec32ed60c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f1e801e7d2a8c93a4ac5272a6037dde" id="r_ga3f1e801e7d2a8c93a4ac5272a6037dde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1e801e7d2a8c93a4ac5272a6037dde">RTC_TSDR_DU_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga031ca4fddcc1f40b7db8b46ec32ed60c">RTC_TSDR_DU_Pos</a>)</td></tr>
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<tr class="separator:ga3f1e801e7d2a8c93a4ac5272a6037dde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace7ca73ebca21ed3a17315f06757042a" id="r_gace7ca73ebca21ed3a17315f06757042a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace7ca73ebca21ed3a17315f06757042a">RTC_TSDR_DU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1e801e7d2a8c93a4ac5272a6037dde">RTC_TSDR_DU_Msk</a></td></tr>
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<tr class="memitem:ga08b7eccac0c3cd20a3f3cd8bce1693ad" id="r_ga08b7eccac0c3cd20a3f3cd8bce1693ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08b7eccac0c3cd20a3f3cd8bce1693ad">RTC_TSDR_DU_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga031ca4fddcc1f40b7db8b46ec32ed60c">RTC_TSDR_DU_Pos</a>)</td></tr>
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<tr class="memitem:gaa43ed53b8109ff32755885127ba987ce" id="r_gaa43ed53b8109ff32755885127ba987ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa43ed53b8109ff32755885127ba987ce">RTC_TSDR_DU_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga031ca4fddcc1f40b7db8b46ec32ed60c">RTC_TSDR_DU_Pos</a>)</td></tr>
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<tr class="memitem:ga1b3d774b7df9cff6e6eecafa7c42a059" id="r_ga1b3d774b7df9cff6e6eecafa7c42a059"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b3d774b7df9cff6e6eecafa7c42a059">RTC_TSDR_DU_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga031ca4fddcc1f40b7db8b46ec32ed60c">RTC_TSDR_DU_Pos</a>)</td></tr>
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<tr class="memitem:ga209573a43dd1f21ef569d75593ad03f8" id="r_ga209573a43dd1f21ef569d75593ad03f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga209573a43dd1f21ef569d75593ad03f8">RTC_TSDR_DU_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga031ca4fddcc1f40b7db8b46ec32ed60c">RTC_TSDR_DU_Pos</a>)</td></tr>
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<tr class="memitem:gac381e2fe1c99a95a6a41f1845d6f207f" id="r_gac381e2fe1c99a95a6a41f1845d6f207f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac381e2fe1c99a95a6a41f1845d6f207f">RTC_TSSSR_SS_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac381e2fe1c99a95a6a41f1845d6f207f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d13c3c83f99d3bdf8fc33ea42b3aecd" id="r_ga1d13c3c83f99d3bdf8fc33ea42b3aecd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d13c3c83f99d3bdf8fc33ea42b3aecd">RTC_TSSSR_SS_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac381e2fe1c99a95a6a41f1845d6f207f">RTC_TSSSR_SS_Pos</a>)</td></tr>
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<tr class="memitem:ga2fb913ce5f1c0e341b308d9b5858bfa9" id="r_ga2fb913ce5f1c0e341b308d9b5858bfa9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fb913ce5f1c0e341b308d9b5858bfa9">RTC_TSSSR_SS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d13c3c83f99d3bdf8fc33ea42b3aecd">RTC_TSSSR_SS_Msk</a></td></tr>
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<tr class="separator:ga2fb913ce5f1c0e341b308d9b5858bfa9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5458d41d3893259a7c1adcb12626552d" id="r_ga5458d41d3893259a7c1adcb12626552d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5458d41d3893259a7c1adcb12626552d">RTC_CALR_CALP_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga5632e54eb1a07b95a3024c2a52665a24" id="r_ga5632e54eb1a07b95a3024c2a52665a24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5632e54eb1a07b95a3024c2a52665a24">RTC_CALR_CALP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5458d41d3893259a7c1adcb12626552d">RTC_CALR_CALP_Pos</a>)</td></tr>
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<tr class="separator:ga5632e54eb1a07b95a3024c2a52665a24"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b13b9724302c25fbca76684f5968528" id="r_ga9b13b9724302c25fbca76684f5968528"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b13b9724302c25fbca76684f5968528">RTC_CALR_CALP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5632e54eb1a07b95a3024c2a52665a24">RTC_CALR_CALP_Msk</a></td></tr>
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<tr class="memitem:ga4ad4a6054ae32e1332b456d59e0aa36c" id="r_ga4ad4a6054ae32e1332b456d59e0aa36c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ad4a6054ae32e1332b456d59e0aa36c">RTC_CALR_CALW8_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gac4a1d426d16a747f07e8d8cf98c7275e" id="r_gac4a1d426d16a747f07e8d8cf98c7275e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4a1d426d16a747f07e8d8cf98c7275e">RTC_CALR_CALW8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4ad4a6054ae32e1332b456d59e0aa36c">RTC_CALR_CALW8_Pos</a>)</td></tr>
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<tr class="memitem:ga28f8c7f5f5bf772c81170a2eab055557" id="r_ga28f8c7f5f5bf772c81170a2eab055557"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28f8c7f5f5bf772c81170a2eab055557">RTC_CALR_CALW8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4a1d426d16a747f07e8d8cf98c7275e">RTC_CALR_CALW8_Msk</a></td></tr>
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<tr class="separator:ga28f8c7f5f5bf772c81170a2eab055557"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ac54a062e43b815b226acdb30888ca9" id="r_ga9ac54a062e43b815b226acdb30888ca9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ac54a062e43b815b226acdb30888ca9">RTC_CALR_CALW16_Pos</a>   (13U)</td></tr>
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<tr class="memitem:gaa75bb89101a1da73b2d78c1486dbf2e2" id="r_gaa75bb89101a1da73b2d78c1486dbf2e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa75bb89101a1da73b2d78c1486dbf2e2">RTC_CALR_CALW16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ac54a062e43b815b226acdb30888ca9">RTC_CALR_CALW16_Pos</a>)</td></tr>
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<tr class="separator:gaa75bb89101a1da73b2d78c1486dbf2e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70857526590d6f7e25d9551187105583" id="r_ga70857526590d6f7e25d9551187105583"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70857526590d6f7e25d9551187105583">RTC_CALR_CALW16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa75bb89101a1da73b2d78c1486dbf2e2">RTC_CALR_CALW16_Msk</a></td></tr>
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<tr class="memitem:ga702670ae12e1600fea81ef41ea485fd6" id="r_ga702670ae12e1600fea81ef41ea485fd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga702670ae12e1600fea81ef41ea485fd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga347a7b8bed29029bd0d8a78ce03268c8" id="r_ga347a7b8bed29029bd0d8a78ce03268c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga347a7b8bed29029bd0d8a78ce03268c8">RTC_CALR_CALM_Msk</a>   (0x1FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>)</td></tr>
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<tr class="separator:ga347a7b8bed29029bd0d8a78ce03268c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44fcacd12e1cfc1fa823c798cb6a7663" id="r_ga44fcacd12e1cfc1fa823c798cb6a7663"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44fcacd12e1cfc1fa823c798cb6a7663">RTC_CALR_CALM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga347a7b8bed29029bd0d8a78ce03268c8">RTC_CALR_CALM_Msk</a></td></tr>
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<tr class="separator:ga44fcacd12e1cfc1fa823c798cb6a7663"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeffec95cc4cbbdbc77e907818b8c7ebd" id="r_gaeffec95cc4cbbdbc77e907818b8c7ebd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeffec95cc4cbbdbc77e907818b8c7ebd">RTC_CALR_CALM_0</a>   (0x001UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>)</td></tr>
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<tr class="separator:gaeffec95cc4cbbdbc77e907818b8c7ebd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b908b77786838e5e2e8a1ee2cbbeeff" id="r_ga4b908b77786838e5e2e8a1ee2cbbeeff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b908b77786838e5e2e8a1ee2cbbeeff">RTC_CALR_CALM_1</a>   (0x002UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>)</td></tr>
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<tr class="separator:ga4b908b77786838e5e2e8a1ee2cbbeeff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad09f14c1ff24a01d51d5b6c0bba220d6" id="r_gad09f14c1ff24a01d51d5b6c0bba220d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad09f14c1ff24a01d51d5b6c0bba220d6">RTC_CALR_CALM_2</a>   (0x004UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>)</td></tr>
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<tr class="separator:gad09f14c1ff24a01d51d5b6c0bba220d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9146fbef6a53896f3160c89ed651b90" id="r_gac9146fbef6a53896f3160c89ed651b90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9146fbef6a53896f3160c89ed651b90">RTC_CALR_CALM_3</a>   (0x008UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>)</td></tr>
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<tr class="separator:gac9146fbef6a53896f3160c89ed651b90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fe04fc9762d3f680f9145a50898c27b" id="r_ga5fe04fc9762d3f680f9145a50898c27b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe04fc9762d3f680f9145a50898c27b">RTC_CALR_CALM_4</a>   (0x010UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>)</td></tr>
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<tr class="separator:ga5fe04fc9762d3f680f9145a50898c27b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc4966c71cab83be4069e0566222d375" id="r_gadc4966c71cab83be4069e0566222d375"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc4966c71cab83be4069e0566222d375">RTC_CALR_CALM_5</a>   (0x020UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>)</td></tr>
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<tr class="memitem:gae240b185d0c9c6e314a456627e6e4834" id="r_gae240b185d0c9c6e314a456627e6e4834"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae240b185d0c9c6e314a456627e6e4834">RTC_CALR_CALM_6</a>   (0x040UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>)</td></tr>
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<tr class="memitem:gab8880325073e167137366402f15d5683" id="r_gab8880325073e167137366402f15d5683"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8880325073e167137366402f15d5683">RTC_CALR_CALM_7</a>   (0x080UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>)</td></tr>
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<tr class="memitem:ga8381cc75166acfc4b4c686ad7e5e599a" id="r_ga8381cc75166acfc4b4c686ad7e5e599a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8381cc75166acfc4b4c686ad7e5e599a">RTC_CALR_CALM_8</a>   (0x100UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">RTC_CALR_CALM_Pos</a>)</td></tr>
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<tr class="memitem:ga288c98bc30ac4f55ee038b66deef21eb" id="r_ga288c98bc30ac4f55ee038b66deef21eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga288c98bc30ac4f55ee038b66deef21eb">RTC_TAFCR_ALARMOUTTYPE_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga288c98bc30ac4f55ee038b66deef21eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga070badc7e2d642aeff89371370f5cb7d" id="r_ga070badc7e2d642aeff89371370f5cb7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga070badc7e2d642aeff89371370f5cb7d">RTC_TAFCR_ALARMOUTTYPE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga288c98bc30ac4f55ee038b66deef21eb">RTC_TAFCR_ALARMOUTTYPE_Pos</a>)</td></tr>
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<tr class="separator:ga070badc7e2d642aeff89371370f5cb7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d9515fd74e3bcf03f4e62d8c7e1b070" id="r_ga8d9515fd74e3bcf03f4e62d8c7e1b070"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d9515fd74e3bcf03f4e62d8c7e1b070">RTC_TAFCR_ALARMOUTTYPE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga070badc7e2d642aeff89371370f5cb7d">RTC_TAFCR_ALARMOUTTYPE_Msk</a></td></tr>
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<tr class="separator:ga8d9515fd74e3bcf03f4e62d8c7e1b070"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5a7a74b471a19d3b24624ed76c9123d" id="r_gab5a7a74b471a19d3b24624ed76c9123d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5a7a74b471a19d3b24624ed76c9123d">RTC_TAFCR_TSINSEL_Pos</a>   (17U)</td></tr>
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<tr class="separator:gab5a7a74b471a19d3b24624ed76c9123d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafffa3d4d97beee57ef7c1b80a20fee7e" id="r_gafffa3d4d97beee57ef7c1b80a20fee7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafffa3d4d97beee57ef7c1b80a20fee7e">RTC_TAFCR_TSINSEL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5a7a74b471a19d3b24624ed76c9123d">RTC_TAFCR_TSINSEL_Pos</a>)</td></tr>
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<tr class="separator:gafffa3d4d97beee57ef7c1b80a20fee7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga872cbfe2e79e7fe2a4bfad6086f4ac49" id="r_ga872cbfe2e79e7fe2a4bfad6086f4ac49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga872cbfe2e79e7fe2a4bfad6086f4ac49">RTC_TAFCR_TSINSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafffa3d4d97beee57ef7c1b80a20fee7e">RTC_TAFCR_TSINSEL_Msk</a></td></tr>
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<tr class="separator:ga872cbfe2e79e7fe2a4bfad6086f4ac49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b8c154291563140f9ab1b938b20e39a" id="r_ga0b8c154291563140f9ab1b938b20e39a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b8c154291563140f9ab1b938b20e39a">RTC_TAFCR_TAMP1INSEL_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga0b8c154291563140f9ab1b938b20e39a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6032dc793590fd715ea61340429b1848" id="r_ga6032dc793590fd715ea61340429b1848"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6032dc793590fd715ea61340429b1848">RTC_TAFCR_TAMP1INSEL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b8c154291563140f9ab1b938b20e39a">RTC_TAFCR_TAMP1INSEL_Pos</a>)</td></tr>
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<tr class="separator:ga6032dc793590fd715ea61340429b1848"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5934e2b2ada22a92862a9ea5356a2665" id="r_ga5934e2b2ada22a92862a9ea5356a2665"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5934e2b2ada22a92862a9ea5356a2665">RTC_TAFCR_TAMP1INSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6032dc793590fd715ea61340429b1848">RTC_TAFCR_TAMP1INSEL_Msk</a></td></tr>
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<tr class="separator:ga5934e2b2ada22a92862a9ea5356a2665"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad46c537f405a4424f17cf6f47a0bdc7c" id="r_gad46c537f405a4424f17cf6f47a0bdc7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad46c537f405a4424f17cf6f47a0bdc7c">RTC_TAFCR_TAMPPUDIS_Pos</a>   (15U)</td></tr>
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<tr class="separator:gad46c537f405a4424f17cf6f47a0bdc7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabaa57d1e8d33a2b5c8ab6aad4ec6fba0" id="r_gabaa57d1e8d33a2b5c8ab6aad4ec6fba0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabaa57d1e8d33a2b5c8ab6aad4ec6fba0">RTC_TAFCR_TAMPPUDIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad46c537f405a4424f17cf6f47a0bdc7c">RTC_TAFCR_TAMPPUDIS_Pos</a>)</td></tr>
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<tr class="separator:gabaa57d1e8d33a2b5c8ab6aad4ec6fba0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ef294e75771913e4a47386f42a23f72" id="r_ga9ef294e75771913e4a47386f42a23f72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ef294e75771913e4a47386f42a23f72">RTC_TAFCR_TAMPPUDIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabaa57d1e8d33a2b5c8ab6aad4ec6fba0">RTC_TAFCR_TAMPPUDIS_Msk</a></td></tr>
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<tr class="separator:ga9ef294e75771913e4a47386f42a23f72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0650b78abfcc5a3a6b247fb9791b9292" id="r_ga0650b78abfcc5a3a6b247fb9791b9292"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0650b78abfcc5a3a6b247fb9791b9292">RTC_TAFCR_TAMPPRCH_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0650b78abfcc5a3a6b247fb9791b9292"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76638587b6e5989ffe219851a96e4f8f" id="r_ga76638587b6e5989ffe219851a96e4f8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76638587b6e5989ffe219851a96e4f8f">RTC_TAFCR_TAMPPRCH_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0650b78abfcc5a3a6b247fb9791b9292">RTC_TAFCR_TAMPPRCH_Pos</a>)</td></tr>
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<tr class="separator:ga76638587b6e5989ffe219851a96e4f8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b73d2b8da78967a6f594dbffe58c222" id="r_ga7b73d2b8da78967a6f594dbffe58c222"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b73d2b8da78967a6f594dbffe58c222">RTC_TAFCR_TAMPPRCH</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga76638587b6e5989ffe219851a96e4f8f">RTC_TAFCR_TAMPPRCH_Msk</a></td></tr>
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<tr class="separator:ga7b73d2b8da78967a6f594dbffe58c222"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae010ed965c1e968cc14f988d50662546" id="r_gae010ed965c1e968cc14f988d50662546"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae010ed965c1e968cc14f988d50662546">RTC_TAFCR_TAMPPRCH_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0650b78abfcc5a3a6b247fb9791b9292">RTC_TAFCR_TAMPPRCH_Pos</a>)</td></tr>
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<tr class="separator:gae010ed965c1e968cc14f988d50662546"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16f0faa59aa4490d696d1fec767aae41" id="r_ga16f0faa59aa4490d696d1fec767aae41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16f0faa59aa4490d696d1fec767aae41">RTC_TAFCR_TAMPPRCH_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0650b78abfcc5a3a6b247fb9791b9292">RTC_TAFCR_TAMPPRCH_Pos</a>)</td></tr>
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<tr class="separator:ga16f0faa59aa4490d696d1fec767aae41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga978ec86db46d77d83e1627a563e5a622" id="r_ga978ec86db46d77d83e1627a563e5a622"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga978ec86db46d77d83e1627a563e5a622">RTC_TAFCR_TAMPFLT_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga978ec86db46d77d83e1627a563e5a622"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf978c259714ae9072766be91c8d982c" id="r_gacf978c259714ae9072766be91c8d982c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf978c259714ae9072766be91c8d982c">RTC_TAFCR_TAMPFLT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga978ec86db46d77d83e1627a563e5a622">RTC_TAFCR_TAMPFLT_Pos</a>)</td></tr>
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<tr class="separator:gacf978c259714ae9072766be91c8d982c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1cb37c43747c779f7db2842a2582e67" id="r_gab1cb37c43747c779f7db2842a2582e67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1cb37c43747c779f7db2842a2582e67">RTC_TAFCR_TAMPFLT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacf978c259714ae9072766be91c8d982c">RTC_TAFCR_TAMPFLT_Msk</a></td></tr>
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<tr class="separator:gab1cb37c43747c779f7db2842a2582e67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa356fb5db5ab398728afef0ae39214c4" id="r_gaa356fb5db5ab398728afef0ae39214c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa356fb5db5ab398728afef0ae39214c4">RTC_TAFCR_TAMPFLT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga978ec86db46d77d83e1627a563e5a622">RTC_TAFCR_TAMPFLT_Pos</a>)</td></tr>
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<tr class="separator:gaa356fb5db5ab398728afef0ae39214c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga472efa1bd3c9462cbd058d73a7d6525e" id="r_ga472efa1bd3c9462cbd058d73a7d6525e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga472efa1bd3c9462cbd058d73a7d6525e">RTC_TAFCR_TAMPFLT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga978ec86db46d77d83e1627a563e5a622">RTC_TAFCR_TAMPFLT_Pos</a>)</td></tr>
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<tr class="separator:ga472efa1bd3c9462cbd058d73a7d6525e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga487bd3ad7900df341c4fe63fb409d2bd" id="r_ga487bd3ad7900df341c4fe63fb409d2bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga487bd3ad7900df341c4fe63fb409d2bd">RTC_TAFCR_TAMPFREQ_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga487bd3ad7900df341c4fe63fb409d2bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e169834a26329219aa2271781756dfb" id="r_ga2e169834a26329219aa2271781756dfb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e169834a26329219aa2271781756dfb">RTC_TAFCR_TAMPFREQ_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga487bd3ad7900df341c4fe63fb409d2bd">RTC_TAFCR_TAMPFREQ_Pos</a>)</td></tr>
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<tr class="memitem:ga8ad84446486b8c9f640fa54d50ecc0e1" id="r_ga8ad84446486b8c9f640fa54d50ecc0e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ad84446486b8c9f640fa54d50ecc0e1">RTC_TAFCR_TAMPFREQ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e169834a26329219aa2271781756dfb">RTC_TAFCR_TAMPFREQ_Msk</a></td></tr>
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<tr class="separator:ga8ad84446486b8c9f640fa54d50ecc0e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54e7f69e04759d1b0667e56830a6f2ea" id="r_ga54e7f69e04759d1b0667e56830a6f2ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54e7f69e04759d1b0667e56830a6f2ea">RTC_TAFCR_TAMPFREQ_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga487bd3ad7900df341c4fe63fb409d2bd">RTC_TAFCR_TAMPFREQ_Pos</a>)</td></tr>
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<tr class="separator:ga54e7f69e04759d1b0667e56830a6f2ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb533067640fcf87ad77027ce936e9b7" id="r_gabb533067640fcf87ad77027ce936e9b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb533067640fcf87ad77027ce936e9b7">RTC_TAFCR_TAMPFREQ_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga487bd3ad7900df341c4fe63fb409d2bd">RTC_TAFCR_TAMPFREQ_Pos</a>)</td></tr>
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<tr class="separator:gabb533067640fcf87ad77027ce936e9b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf532e727bfe6c7fc7822d15f9436e1b5" id="r_gaf532e727bfe6c7fc7822d15f9436e1b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf532e727bfe6c7fc7822d15f9436e1b5">RTC_TAFCR_TAMPFREQ_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga487bd3ad7900df341c4fe63fb409d2bd">RTC_TAFCR_TAMPFREQ_Pos</a>)</td></tr>
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<tr class="separator:gaf532e727bfe6c7fc7822d15f9436e1b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73e4ad22e6610c5c39fbc548b621b244" id="r_ga73e4ad22e6610c5c39fbc548b621b244"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73e4ad22e6610c5c39fbc548b621b244">RTC_TAFCR_TAMPTS_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga73e4ad22e6610c5c39fbc548b621b244"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga195a1c8285f2826479b6afb75576ac3d" id="r_ga195a1c8285f2826479b6afb75576ac3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga195a1c8285f2826479b6afb75576ac3d">RTC_TAFCR_TAMPTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga73e4ad22e6610c5c39fbc548b621b244">RTC_TAFCR_TAMPTS_Pos</a>)</td></tr>
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<tr class="memitem:gac929fab94fdca2d1b3b3cf7c93fe6e49" id="r_gac929fab94fdca2d1b3b3cf7c93fe6e49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac929fab94fdca2d1b3b3cf7c93fe6e49">RTC_TAFCR_TAMPTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga195a1c8285f2826479b6afb75576ac3d">RTC_TAFCR_TAMPTS_Msk</a></td></tr>
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<tr class="memitem:ga5d0e27811bd76fcf94c2f802df2a742f" id="r_ga5d0e27811bd76fcf94c2f802df2a742f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d0e27811bd76fcf94c2f802df2a742f">RTC_TAFCR_TAMP2TRG_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga92f7e43c7127ffa0dac5c94233360852" id="r_ga92f7e43c7127ffa0dac5c94233360852"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92f7e43c7127ffa0dac5c94233360852">RTC_TAFCR_TAMP2TRG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5d0e27811bd76fcf94c2f802df2a742f">RTC_TAFCR_TAMP2TRG_Pos</a>)</td></tr>
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<tr class="separator:ga92f7e43c7127ffa0dac5c94233360852"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2c4d227971b56e3160c71b7479c769d" id="r_gad2c4d227971b56e3160c71b7479c769d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2c4d227971b56e3160c71b7479c769d">RTC_TAFCR_TAMP2TRG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga92f7e43c7127ffa0dac5c94233360852">RTC_TAFCR_TAMP2TRG_Msk</a></td></tr>
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<tr class="separator:gad2c4d227971b56e3160c71b7479c769d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac46ab34c29b3dfa1dc0c3866cb52ce9f" id="r_gac46ab34c29b3dfa1dc0c3866cb52ce9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac46ab34c29b3dfa1dc0c3866cb52ce9f">RTC_TAFCR_TAMP2E_Pos</a>   (3U)</td></tr>
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<tr class="memitem:gad539217084c83e84eb27ec76eca40152" id="r_gad539217084c83e84eb27ec76eca40152"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad539217084c83e84eb27ec76eca40152">RTC_TAFCR_TAMP2E_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac46ab34c29b3dfa1dc0c3866cb52ce9f">RTC_TAFCR_TAMP2E_Pos</a>)</td></tr>
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<tr class="separator:gad539217084c83e84eb27ec76eca40152"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e98a0062ef81bcbc790a8d77720a61c" id="r_ga7e98a0062ef81bcbc790a8d77720a61c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e98a0062ef81bcbc790a8d77720a61c">RTC_TAFCR_TAMP2E</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad539217084c83e84eb27ec76eca40152">RTC_TAFCR_TAMP2E_Msk</a></td></tr>
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<tr class="memitem:ga9b58fa23a2a04d3a4a46d42fa4673ec5" id="r_ga9b58fa23a2a04d3a4a46d42fa4673ec5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b58fa23a2a04d3a4a46d42fa4673ec5">RTC_TAFCR_TAMPIE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga9b58fa23a2a04d3a4a46d42fa4673ec5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga028b4854bd356dc30a8b02ab5ed1eb48" id="r_ga028b4854bd356dc30a8b02ab5ed1eb48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga028b4854bd356dc30a8b02ab5ed1eb48">RTC_TAFCR_TAMPIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b58fa23a2a04d3a4a46d42fa4673ec5">RTC_TAFCR_TAMPIE_Pos</a>)</td></tr>
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<tr class="memitem:gaa0fb33b24d2ebc19e7fe52f0661a3085" id="r_gaa0fb33b24d2ebc19e7fe52f0661a3085"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0fb33b24d2ebc19e7fe52f0661a3085">RTC_TAFCR_TAMPIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga028b4854bd356dc30a8b02ab5ed1eb48">RTC_TAFCR_TAMPIE_Msk</a></td></tr>
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<tr class="separator:gaa0fb33b24d2ebc19e7fe52f0661a3085"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6904e60d49c241ecb2347a3da9df8054" id="r_ga6904e60d49c241ecb2347a3da9df8054"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6904e60d49c241ecb2347a3da9df8054">RTC_TAFCR_TAMP1TRG_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga6904e60d49c241ecb2347a3da9df8054"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81d7cfb15da3ed9689baa85471ff2f02" id="r_ga81d7cfb15da3ed9689baa85471ff2f02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81d7cfb15da3ed9689baa85471ff2f02">RTC_TAFCR_TAMP1TRG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6904e60d49c241ecb2347a3da9df8054">RTC_TAFCR_TAMP1TRG_Pos</a>)</td></tr>
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<tr class="separator:ga81d7cfb15da3ed9689baa85471ff2f02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76f85925873bcd3f795417053bfc5f33" id="r_ga76f85925873bcd3f795417053bfc5f33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76f85925873bcd3f795417053bfc5f33">RTC_TAFCR_TAMP1TRG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga81d7cfb15da3ed9689baa85471ff2f02">RTC_TAFCR_TAMP1TRG_Msk</a></td></tr>
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<tr class="separator:ga76f85925873bcd3f795417053bfc5f33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae207869690b2ec429b0422006ecae9ee" id="r_gae207869690b2ec429b0422006ecae9ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae207869690b2ec429b0422006ecae9ee">RTC_TAFCR_TAMP1E_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae207869690b2ec429b0422006ecae9ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad775a4255d5762b8871f79826d48e5cb" id="r_gad775a4255d5762b8871f79826d48e5cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad775a4255d5762b8871f79826d48e5cb">RTC_TAFCR_TAMP1E_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae207869690b2ec429b0422006ecae9ee">RTC_TAFCR_TAMP1E_Pos</a>)</td></tr>
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<tr class="memitem:gaa68c195cf709d18cd426560302b97852" id="r_gaa68c195cf709d18cd426560302b97852"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa68c195cf709d18cd426560302b97852">RTC_TAFCR_TAMP1E</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad775a4255d5762b8871f79826d48e5cb">RTC_TAFCR_TAMP1E_Msk</a></td></tr>
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<tr class="separator:gaa68c195cf709d18cd426560302b97852"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga989cde7332b2ec0b3934cb909514938d" id="r_ga989cde7332b2ec0b3934cb909514938d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga989cde7332b2ec0b3934cb909514938d">RTC_TAFCR_TAMPINSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5934e2b2ada22a92862a9ea5356a2665">RTC_TAFCR_TAMP1INSEL</a></td></tr>
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<tr class="memitem:ga97b73051e1ea4d40a4877f9580c2eb63" id="r_ga97b73051e1ea4d40a4877f9580c2eb63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97b73051e1ea4d40a4877f9580c2eb63">RTC_ALRMASSR_MASKSS_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga97b73051e1ea4d40a4877f9580c2eb63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77d71d0606814b6d20253a645bdb5936" id="r_ga77d71d0606814b6d20253a645bdb5936"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77d71d0606814b6d20253a645bdb5936">RTC_ALRMASSR_MASKSS_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97b73051e1ea4d40a4877f9580c2eb63">RTC_ALRMASSR_MASKSS_Pos</a>)</td></tr>
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<tr class="memitem:ga7b0550ccc175ff54e560cc5fb96fbb2c" id="r_ga7b0550ccc175ff54e560cc5fb96fbb2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b0550ccc175ff54e560cc5fb96fbb2c">RTC_ALRMASSR_MASKSS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga77d71d0606814b6d20253a645bdb5936">RTC_ALRMASSR_MASKSS_Msk</a></td></tr>
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<tr class="memitem:gaeebbc0dfc0a20887ef3582feaa5f1c2b" id="r_gaeebbc0dfc0a20887ef3582feaa5f1c2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeebbc0dfc0a20887ef3582feaa5f1c2b">RTC_ALRMASSR_MASKSS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97b73051e1ea4d40a4877f9580c2eb63">RTC_ALRMASSR_MASKSS_Pos</a>)</td></tr>
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<tr class="separator:gaeebbc0dfc0a20887ef3582feaa5f1c2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabbdb202f388835593843f480c3b3af57" id="r_gabbdb202f388835593843f480c3b3af57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbdb202f388835593843f480c3b3af57">RTC_ALRMASSR_MASKSS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97b73051e1ea4d40a4877f9580c2eb63">RTC_ALRMASSR_MASKSS_Pos</a>)</td></tr>
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<tr class="memitem:ga95feb5de45a74d7c75c1fc6515c32870" id="r_ga95feb5de45a74d7c75c1fc6515c32870"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95feb5de45a74d7c75c1fc6515c32870">RTC_ALRMASSR_MASKSS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97b73051e1ea4d40a4877f9580c2eb63">RTC_ALRMASSR_MASKSS_Pos</a>)</td></tr>
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<tr class="separator:ga95feb5de45a74d7c75c1fc6515c32870"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae94c65876a1baf0984a6f85aa836b8d0" id="r_gae94c65876a1baf0984a6f85aa836b8d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae94c65876a1baf0984a6f85aa836b8d0">RTC_ALRMASSR_MASKSS_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97b73051e1ea4d40a4877f9580c2eb63">RTC_ALRMASSR_MASKSS_Pos</a>)</td></tr>
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<tr class="separator:gae94c65876a1baf0984a6f85aa836b8d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5c69419fc862f5012e842942dd755be" id="r_gaf5c69419fc862f5012e842942dd755be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5c69419fc862f5012e842942dd755be">RTC_ALRMASSR_SS_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf5c69419fc862f5012e842942dd755be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadba25e1519a8aa3222912425ae4c4229" id="r_gadba25e1519a8aa3222912425ae4c4229"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadba25e1519a8aa3222912425ae4c4229">RTC_ALRMASSR_SS_Msk</a>   (0x7FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5c69419fc862f5012e842942dd755be">RTC_ALRMASSR_SS_Pos</a>)</td></tr>
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<tr class="memitem:ga4a6b683531fded4e2a77d047da7eb203" id="r_ga4a6b683531fded4e2a77d047da7eb203"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a6b683531fded4e2a77d047da7eb203">RTC_ALRMASSR_SS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadba25e1519a8aa3222912425ae4c4229">RTC_ALRMASSR_SS_Msk</a></td></tr>
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<tr class="separator:ga4a6b683531fded4e2a77d047da7eb203"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bedfef79d265b81f561e7f2c5a6249a" id="r_ga0bedfef79d265b81f561e7f2c5a6249a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bedfef79d265b81f561e7f2c5a6249a">RTC_ALRMBSSR_MASKSS_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga0bedfef79d265b81f561e7f2c5a6249a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54f65537e9a664f30ca7f3099c6fcc5f" id="r_ga54f65537e9a664f30ca7f3099c6fcc5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54f65537e9a664f30ca7f3099c6fcc5f">RTC_ALRMBSSR_MASKSS_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bedfef79d265b81f561e7f2c5a6249a">RTC_ALRMBSSR_MASKSS_Pos</a>)</td></tr>
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<tr class="separator:ga54f65537e9a664f30ca7f3099c6fcc5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf287b0ec7dbf8e9d436cb78da287b244" id="r_gaf287b0ec7dbf8e9d436cb78da287b244"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf287b0ec7dbf8e9d436cb78da287b244">RTC_ALRMBSSR_MASKSS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga54f65537e9a664f30ca7f3099c6fcc5f">RTC_ALRMBSSR_MASKSS_Msk</a></td></tr>
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<tr class="separator:gaf287b0ec7dbf8e9d436cb78da287b244"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4d60185d1ac432b24b0a95e2918902f" id="r_gad4d60185d1ac432b24b0a95e2918902f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4d60185d1ac432b24b0a95e2918902f">RTC_ALRMBSSR_MASKSS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bedfef79d265b81f561e7f2c5a6249a">RTC_ALRMBSSR_MASKSS_Pos</a>)</td></tr>
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<tr class="separator:gad4d60185d1ac432b24b0a95e2918902f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9763a1a382e40cc2ebfa6d84369580df" id="r_ga9763a1a382e40cc2ebfa6d84369580df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9763a1a382e40cc2ebfa6d84369580df">RTC_ALRMBSSR_MASKSS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bedfef79d265b81f561e7f2c5a6249a">RTC_ALRMBSSR_MASKSS_Pos</a>)</td></tr>
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<tr class="separator:ga9763a1a382e40cc2ebfa6d84369580df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga598283f8a8926f0dcb7916a2224f79bc" id="r_ga598283f8a8926f0dcb7916a2224f79bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga598283f8a8926f0dcb7916a2224f79bc">RTC_ALRMBSSR_MASKSS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bedfef79d265b81f561e7f2c5a6249a">RTC_ALRMBSSR_MASKSS_Pos</a>)</td></tr>
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<tr class="separator:ga598283f8a8926f0dcb7916a2224f79bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf017c71fc7eb34519de3945a028677b" id="r_gadf017c71fc7eb34519de3945a028677b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf017c71fc7eb34519de3945a028677b">RTC_ALRMBSSR_MASKSS_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bedfef79d265b81f561e7f2c5a6249a">RTC_ALRMBSSR_MASKSS_Pos</a>)</td></tr>
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<tr class="separator:gadf017c71fc7eb34519de3945a028677b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f2a25c58bddba6df25d75825eff3f76" id="r_ga2f2a25c58bddba6df25d75825eff3f76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f2a25c58bddba6df25d75825eff3f76">RTC_ALRMBSSR_SS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2f2a25c58bddba6df25d75825eff3f76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaea93544826ca1a8e920ffd0f46c2bbe" id="r_gaaea93544826ca1a8e920ffd0f46c2bbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaea93544826ca1a8e920ffd0f46c2bbe">RTC_ALRMBSSR_SS_Msk</a>   (0x7FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f2a25c58bddba6df25d75825eff3f76">RTC_ALRMBSSR_SS_Pos</a>)</td></tr>
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<tr class="separator:gaaea93544826ca1a8e920ffd0f46c2bbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33ae74f38392431aa631d397a7e7c305" id="r_ga33ae74f38392431aa631d397a7e7c305"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33ae74f38392431aa631d397a7e7c305">RTC_ALRMBSSR_SS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaea93544826ca1a8e920ffd0f46c2bbe">RTC_ALRMBSSR_SS_Msk</a></td></tr>
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<tr class="separator:ga33ae74f38392431aa631d397a7e7c305"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d2a1d81a7e8f12510f865312caea186" id="r_ga8d2a1d81a7e8f12510f865312caea186"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d2a1d81a7e8f12510f865312caea186">RTC_BKP0R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8d2a1d81a7e8f12510f865312caea186"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65152adac13a55042ab984b782cf785b" id="r_ga65152adac13a55042ab984b782cf785b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65152adac13a55042ab984b782cf785b">RTC_BKP0R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d2a1d81a7e8f12510f865312caea186">RTC_BKP0R_Pos</a>)</td></tr>
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<tr class="separator:ga65152adac13a55042ab984b782cf785b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0d7c3115465079f04cfb97a7faabc59" id="r_gae0d7c3115465079f04cfb97a7faabc59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0d7c3115465079f04cfb97a7faabc59">RTC_BKP0R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65152adac13a55042ab984b782cf785b">RTC_BKP0R_Msk</a></td></tr>
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<tr class="separator:gae0d7c3115465079f04cfb97a7faabc59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2eff670c07a820b705ec3745683dc75" id="r_gaa2eff670c07a820b705ec3745683dc75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2eff670c07a820b705ec3745683dc75">RTC_BKP1R_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa2eff670c07a820b705ec3745683dc75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1232543b3a22da7aac7131e173182686" id="r_ga1232543b3a22da7aac7131e173182686"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1232543b3a22da7aac7131e173182686">RTC_BKP1R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2eff670c07a820b705ec3745683dc75">RTC_BKP1R_Pos</a>)</td></tr>
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<tr class="separator:ga1232543b3a22da7aac7131e173182686"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbc4b6dfeff87332124f271b86eb0c56" id="r_gafbc4b6dfeff87332124f271b86eb0c56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbc4b6dfeff87332124f271b86eb0c56">RTC_BKP1R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1232543b3a22da7aac7131e173182686">RTC_BKP1R_Msk</a></td></tr>
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<tr class="separator:gafbc4b6dfeff87332124f271b86eb0c56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61b179787d35514914d2e103e3cc5388" id="r_ga61b179787d35514914d2e103e3cc5388"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61b179787d35514914d2e103e3cc5388">RTC_BKP2R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga61b179787d35514914d2e103e3cc5388"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe778fc6aa04076af499bfe4eef8f5e1" id="r_gafe778fc6aa04076af499bfe4eef8f5e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe778fc6aa04076af499bfe4eef8f5e1">RTC_BKP2R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61b179787d35514914d2e103e3cc5388">RTC_BKP2R_Pos</a>)</td></tr>
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<tr class="separator:gafe778fc6aa04076af499bfe4eef8f5e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34fda9ee6115f0de9588e22c46602d89" id="r_ga34fda9ee6115f0de9588e22c46602d89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34fda9ee6115f0de9588e22c46602d89">RTC_BKP2R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafe778fc6aa04076af499bfe4eef8f5e1">RTC_BKP2R_Msk</a></td></tr>
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<tr class="separator:ga34fda9ee6115f0de9588e22c46602d89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad53baa189d917e48c2c274655adc9483" id="r_gad53baa189d917e48c2c274655adc9483"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad53baa189d917e48c2c274655adc9483">RTC_BKP3R_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad53baa189d917e48c2c274655adc9483"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e99106bc39a8e81bf48352827d0ddaf" id="r_ga6e99106bc39a8e81bf48352827d0ddaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e99106bc39a8e81bf48352827d0ddaf">RTC_BKP3R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad53baa189d917e48c2c274655adc9483">RTC_BKP3R_Pos</a>)</td></tr>
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<tr class="separator:ga6e99106bc39a8e81bf48352827d0ddaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90403ff99c08f0abc379447823e5e841" id="r_ga90403ff99c08f0abc379447823e5e841"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90403ff99c08f0abc379447823e5e841">RTC_BKP3R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e99106bc39a8e81bf48352827d0ddaf">RTC_BKP3R_Msk</a></td></tr>
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<tr class="separator:ga90403ff99c08f0abc379447823e5e841"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad62cbb0c17b02ce23ca2bdd29b0ed349" id="r_gad62cbb0c17b02ce23ca2bdd29b0ed349"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad62cbb0c17b02ce23ca2bdd29b0ed349">RTC_BKP4R_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad62cbb0c17b02ce23ca2bdd29b0ed349"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64613b1fe898ececd40ffe481df742ab" id="r_ga64613b1fe898ececd40ffe481df742ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64613b1fe898ececd40ffe481df742ab">RTC_BKP4R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad62cbb0c17b02ce23ca2bdd29b0ed349">RTC_BKP4R_Pos</a>)</td></tr>
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<tr class="separator:ga64613b1fe898ececd40ffe481df742ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeed1b338e9526d817a1fd01304b8851c" id="r_gaeed1b338e9526d817a1fd01304b8851c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeed1b338e9526d817a1fd01304b8851c">RTC_BKP4R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64613b1fe898ececd40ffe481df742ab">RTC_BKP4R_Msk</a></td></tr>
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<tr class="separator:gaeed1b338e9526d817a1fd01304b8851c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga025745144302ad1dd444f09687634674" id="r_ga025745144302ad1dd444f09687634674"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga025745144302ad1dd444f09687634674">RTC_BKP5R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga025745144302ad1dd444f09687634674"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2335682b85414d8d53d4fffdfc3bf190" id="r_ga2335682b85414d8d53d4fffdfc3bf190"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2335682b85414d8d53d4fffdfc3bf190">RTC_BKP5R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga025745144302ad1dd444f09687634674">RTC_BKP5R_Pos</a>)</td></tr>
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<tr class="separator:ga2335682b85414d8d53d4fffdfc3bf190"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e8954ab0ead8bb788d5d8eebf2f5c4c" id="r_ga4e8954ab0ead8bb788d5d8eebf2f5c4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e8954ab0ead8bb788d5d8eebf2f5c4c">RTC_BKP5R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2335682b85414d8d53d4fffdfc3bf190">RTC_BKP5R_Msk</a></td></tr>
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<tr class="separator:ga4e8954ab0ead8bb788d5d8eebf2f5c4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2e7347300206d08a294ba300b9dcdfd" id="r_gac2e7347300206d08a294ba300b9dcdfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2e7347300206d08a294ba300b9dcdfd">RTC_BKP6R_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac2e7347300206d08a294ba300b9dcdfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cca326be267e10381f4d4f9d5951c32" id="r_ga2cca326be267e10381f4d4f9d5951c32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cca326be267e10381f4d4f9d5951c32">RTC_BKP6R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2e7347300206d08a294ba300b9dcdfd">RTC_BKP6R_Pos</a>)</td></tr>
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<tr class="separator:ga2cca326be267e10381f4d4f9d5951c32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b9ee9eb5d024ccd5809fcc20fd51f5b" id="r_ga4b9ee9eb5d024ccd5809fcc20fd51f5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b9ee9eb5d024ccd5809fcc20fd51f5b">RTC_BKP6R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cca326be267e10381f4d4f9d5951c32">RTC_BKP6R_Msk</a></td></tr>
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<tr class="separator:ga4b9ee9eb5d024ccd5809fcc20fd51f5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab37f3f4b5f12182f8fd48431c5b5d9fb" id="r_gab37f3f4b5f12182f8fd48431c5b5d9fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab37f3f4b5f12182f8fd48431c5b5d9fb">RTC_BKP7R_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab37f3f4b5f12182f8fd48431c5b5d9fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3ad5bf67535cba7d3de78d72ae79d79" id="r_gaf3ad5bf67535cba7d3de78d72ae79d79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3ad5bf67535cba7d3de78d72ae79d79">RTC_BKP7R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab37f3f4b5f12182f8fd48431c5b5d9fb">RTC_BKP7R_Pos</a>)</td></tr>
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<tr class="separator:gaf3ad5bf67535cba7d3de78d72ae79d79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0f1ae07f7b1815bf58b464dc7366731" id="r_gab0f1ae07f7b1815bf58b464dc7366731"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0f1ae07f7b1815bf58b464dc7366731">RTC_BKP7R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3ad5bf67535cba7d3de78d72ae79d79">RTC_BKP7R_Msk</a></td></tr>
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<tr class="separator:gab0f1ae07f7b1815bf58b464dc7366731"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a01cc89fbe70d722025ba445143da77" id="r_ga0a01cc89fbe70d722025ba445143da77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a01cc89fbe70d722025ba445143da77">RTC_BKP8R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0a01cc89fbe70d722025ba445143da77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61ae366e9c0ad90225479d0d6d4e1544" id="r_ga61ae366e9c0ad90225479d0d6d4e1544"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61ae366e9c0ad90225479d0d6d4e1544">RTC_BKP8R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a01cc89fbe70d722025ba445143da77">RTC_BKP8R_Pos</a>)</td></tr>
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<tr class="separator:ga61ae366e9c0ad90225479d0d6d4e1544"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bd10acb9e5ce5225af4ff895bd3bb82" id="r_ga2bd10acb9e5ce5225af4ff895bd3bb82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bd10acb9e5ce5225af4ff895bd3bb82">RTC_BKP8R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga61ae366e9c0ad90225479d0d6d4e1544">RTC_BKP8R_Msk</a></td></tr>
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<tr class="separator:ga2bd10acb9e5ce5225af4ff895bd3bb82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf98c5146f622b5e7a9aef16b75f0a76f" id="r_gaf98c5146f622b5e7a9aef16b75f0a76f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf98c5146f622b5e7a9aef16b75f0a76f">RTC_BKP9R_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf98c5146f622b5e7a9aef16b75f0a76f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf039d5e2bf31dc293bd3b84a186bd8c8" id="r_gaf039d5e2bf31dc293bd3b84a186bd8c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf039d5e2bf31dc293bd3b84a186bd8c8">RTC_BKP9R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf98c5146f622b5e7a9aef16b75f0a76f">RTC_BKP9R_Pos</a>)</td></tr>
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<tr class="separator:gaf039d5e2bf31dc293bd3b84a186bd8c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9aa3d0d90de22a1dbf3b6de2b7ed4c9e" id="r_ga9aa3d0d90de22a1dbf3b6de2b7ed4c9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9aa3d0d90de22a1dbf3b6de2b7ed4c9e">RTC_BKP9R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf039d5e2bf31dc293bd3b84a186bd8c8">RTC_BKP9R_Msk</a></td></tr>
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<tr class="separator:ga9aa3d0d90de22a1dbf3b6de2b7ed4c9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68a6b8b6fd6e38bcbb396de36791b97d" id="r_ga68a6b8b6fd6e38bcbb396de36791b97d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68a6b8b6fd6e38bcbb396de36791b97d">RTC_BKP10R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga68a6b8b6fd6e38bcbb396de36791b97d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga425836775a344f3d199760028c01b22f" id="r_ga425836775a344f3d199760028c01b22f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga425836775a344f3d199760028c01b22f">RTC_BKP10R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68a6b8b6fd6e38bcbb396de36791b97d">RTC_BKP10R_Pos</a>)</td></tr>
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<tr class="separator:ga425836775a344f3d199760028c01b22f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2179063a3078a211c3b697ce012ab5a0" id="r_ga2179063a3078a211c3b697ce012ab5a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2179063a3078a211c3b697ce012ab5a0">RTC_BKP10R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga425836775a344f3d199760028c01b22f">RTC_BKP10R_Msk</a></td></tr>
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<tr class="separator:ga2179063a3078a211c3b697ce012ab5a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71f7a489ec11b5547afa3470d76ea62a" id="r_ga71f7a489ec11b5547afa3470d76ea62a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71f7a489ec11b5547afa3470d76ea62a">RTC_BKP11R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga71f7a489ec11b5547afa3470d76ea62a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga803ec730ae4020d5b80df83b21990b31" id="r_ga803ec730ae4020d5b80df83b21990b31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga803ec730ae4020d5b80df83b21990b31">RTC_BKP11R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71f7a489ec11b5547afa3470d76ea62a">RTC_BKP11R_Pos</a>)</td></tr>
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<tr class="separator:ga803ec730ae4020d5b80df83b21990b31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab250f9423dee41b165aa8f02d2fc1fe7" id="r_gab250f9423dee41b165aa8f02d2fc1fe7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab250f9423dee41b165aa8f02d2fc1fe7">RTC_BKP11R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga803ec730ae4020d5b80df83b21990b31">RTC_BKP11R_Msk</a></td></tr>
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<tr class="separator:gab250f9423dee41b165aa8f02d2fc1fe7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e64139e8db6dcca0efbb9e3a4e6a524" id="r_ga2e64139e8db6dcca0efbb9e3a4e6a524"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e64139e8db6dcca0efbb9e3a4e6a524">RTC_BKP12R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2e64139e8db6dcca0efbb9e3a4e6a524"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaed050277146eb1c2fa2a8e8eb778888" id="r_gaaed050277146eb1c2fa2a8e8eb778888"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaed050277146eb1c2fa2a8e8eb778888">RTC_BKP12R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e64139e8db6dcca0efbb9e3a4e6a524">RTC_BKP12R_Pos</a>)</td></tr>
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<tr class="separator:gaaed050277146eb1c2fa2a8e8eb778888"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefe1b6108ac49197b28c9bee31bbaf3b" id="r_gaefe1b6108ac49197b28c9bee31bbaf3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefe1b6108ac49197b28c9bee31bbaf3b">RTC_BKP12R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaed050277146eb1c2fa2a8e8eb778888">RTC_BKP12R_Msk</a></td></tr>
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<tr class="separator:gaefe1b6108ac49197b28c9bee31bbaf3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga704dac9c54b7afd7e51c026ef0093eed" id="r_ga704dac9c54b7afd7e51c026ef0093eed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga704dac9c54b7afd7e51c026ef0093eed">RTC_BKP13R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga704dac9c54b7afd7e51c026ef0093eed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f1c04da88aaae10d0bcf45816608b8e" id="r_ga2f1c04da88aaae10d0bcf45816608b8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f1c04da88aaae10d0bcf45816608b8e">RTC_BKP13R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga704dac9c54b7afd7e51c026ef0093eed">RTC_BKP13R_Pos</a>)</td></tr>
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<tr class="separator:ga2f1c04da88aaae10d0bcf45816608b8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e77435e16bdebf3491eb0e30bd10b0d" id="r_ga0e77435e16bdebf3491eb0e30bd10b0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e77435e16bdebf3491eb0e30bd10b0d">RTC_BKP13R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f1c04da88aaae10d0bcf45816608b8e">RTC_BKP13R_Msk</a></td></tr>
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<tr class="separator:ga0e77435e16bdebf3491eb0e30bd10b0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga35ea3d3c00bb891b7702428ab6b13526" id="r_ga35ea3d3c00bb891b7702428ab6b13526"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35ea3d3c00bb891b7702428ab6b13526">RTC_BKP14R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga35ea3d3c00bb891b7702428ab6b13526"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaceeefc705b2bd138b6ec84bd606dbe86" id="r_gaceeefc705b2bd138b6ec84bd606dbe86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaceeefc705b2bd138b6ec84bd606dbe86">RTC_BKP14R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga35ea3d3c00bb891b7702428ab6b13526">RTC_BKP14R_Pos</a>)</td></tr>
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<tr class="separator:gaceeefc705b2bd138b6ec84bd606dbe86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f07ee6d227deaa11e0ae035121185b0" id="r_ga5f07ee6d227deaa11e0ae035121185b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f07ee6d227deaa11e0ae035121185b0">RTC_BKP14R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaceeefc705b2bd138b6ec84bd606dbe86">RTC_BKP14R_Msk</a></td></tr>
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<tr class="separator:ga5f07ee6d227deaa11e0ae035121185b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab300e7778a3b5f5e69b9e3c6a2f00244" id="r_gab300e7778a3b5f5e69b9e3c6a2f00244"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab300e7778a3b5f5e69b9e3c6a2f00244">RTC_BKP15R_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab300e7778a3b5f5e69b9e3c6a2f00244"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae55844e319f165ba23ba0b2d5a9ff2ee" id="r_gae55844e319f165ba23ba0b2d5a9ff2ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae55844e319f165ba23ba0b2d5a9ff2ee">RTC_BKP15R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab300e7778a3b5f5e69b9e3c6a2f00244">RTC_BKP15R_Pos</a>)</td></tr>
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<tr class="separator:gae55844e319f165ba23ba0b2d5a9ff2ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae543b0dd58f03c2f70bb6b3b65232863" id="r_gae543b0dd58f03c2f70bb6b3b65232863"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae543b0dd58f03c2f70bb6b3b65232863">RTC_BKP15R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae55844e319f165ba23ba0b2d5a9ff2ee">RTC_BKP15R_Msk</a></td></tr>
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<tr class="separator:gae543b0dd58f03c2f70bb6b3b65232863"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8a577b0955f75ea83804f5d16b7361a" id="r_gae8a577b0955f75ea83804f5d16b7361a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8a577b0955f75ea83804f5d16b7361a">RTC_BKP16R_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae8a577b0955f75ea83804f5d16b7361a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad53cd82e4d08160a2169cf0d6122ba7a" id="r_gad53cd82e4d08160a2169cf0d6122ba7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad53cd82e4d08160a2169cf0d6122ba7a">RTC_BKP16R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae8a577b0955f75ea83804f5d16b7361a">RTC_BKP16R_Pos</a>)</td></tr>
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<tr class="separator:gad53cd82e4d08160a2169cf0d6122ba7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0add0c768094f0de71bb4e50fbcce6e" id="r_gaf0add0c768094f0de71bb4e50fbcce6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0add0c768094f0de71bb4e50fbcce6e">RTC_BKP16R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad53cd82e4d08160a2169cf0d6122ba7a">RTC_BKP16R_Msk</a></td></tr>
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<tr class="separator:gaf0add0c768094f0de71bb4e50fbcce6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6036f283574a87f4d27610040c53eb1e" id="r_ga6036f283574a87f4d27610040c53eb1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6036f283574a87f4d27610040c53eb1e">RTC_BKP17R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga6036f283574a87f4d27610040c53eb1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb00d71ec7bae68636740347f971bb05" id="r_gaeb00d71ec7bae68636740347f971bb05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb00d71ec7bae68636740347f971bb05">RTC_BKP17R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6036f283574a87f4d27610040c53eb1e">RTC_BKP17R_Pos</a>)</td></tr>
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<tr class="separator:gaeb00d71ec7bae68636740347f971bb05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga059aaedb55963f39e8724d50d55d5282" id="r_ga059aaedb55963f39e8724d50d55d5282"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga059aaedb55963f39e8724d50d55d5282">RTC_BKP17R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb00d71ec7bae68636740347f971bb05">RTC_BKP17R_Msk</a></td></tr>
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<tr class="separator:ga059aaedb55963f39e8724d50d55d5282"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad55ca335d5c133a1b773affcb87e421c" id="r_gad55ca335d5c133a1b773affcb87e421c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad55ca335d5c133a1b773affcb87e421c">RTC_BKP18R_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad55ca335d5c133a1b773affcb87e421c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad06553479e94b2bbd23fde19bbcf0667" id="r_gad06553479e94b2bbd23fde19bbcf0667"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad06553479e94b2bbd23fde19bbcf0667">RTC_BKP18R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad55ca335d5c133a1b773affcb87e421c">RTC_BKP18R_Pos</a>)</td></tr>
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<tr class="separator:gad06553479e94b2bbd23fde19bbcf0667"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66154eb091275e87a4bd53e87ef9214e" id="r_ga66154eb091275e87a4bd53e87ef9214e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66154eb091275e87a4bd53e87ef9214e">RTC_BKP18R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad06553479e94b2bbd23fde19bbcf0667">RTC_BKP18R_Msk</a></td></tr>
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<tr class="separator:ga66154eb091275e87a4bd53e87ef9214e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5eee6977105e1d1972deedeeb87efe2c" id="r_ga5eee6977105e1d1972deedeeb87efe2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5eee6977105e1d1972deedeeb87efe2c">RTC_BKP19R_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5eee6977105e1d1972deedeeb87efe2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9dd25b421b61fc893df921c7ea4d58f1" id="r_ga9dd25b421b61fc893df921c7ea4d58f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9dd25b421b61fc893df921c7ea4d58f1">RTC_BKP19R_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5eee6977105e1d1972deedeeb87efe2c">RTC_BKP19R_Pos</a>)</td></tr>
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<tr class="separator:ga9dd25b421b61fc893df921c7ea4d58f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa4c31e33d851fde2715059ea28dac6f" id="r_gafa4c31e33d851fde2715059ea28dac6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa4c31e33d851fde2715059ea28dac6f">RTC_BKP19R</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9dd25b421b61fc893df921c7ea4d58f1">RTC_BKP19R_Msk</a></td></tr>
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<tr class="separator:gafa4c31e33d851fde2715059ea28dac6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70de60adf3ddd7d029bb2c6ae26d9584" id="r_ga70de60adf3ddd7d029bb2c6ae26d9584"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70de60adf3ddd7d029bb2c6ae26d9584">RTC_BKP_NUMBER</a>   0x000000014U</td></tr>
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<tr class="memitem:ga980203971a9f5f4c5e02733c6106249f" id="r_ga980203971a9f5f4c5e02733c6106249f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga980203971a9f5f4c5e02733c6106249f">SDIO_POWER_PWRCTRL_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga85685239a200e250d95c38f310fb9609" id="r_ga85685239a200e250d95c38f310fb9609"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85685239a200e250d95c38f310fb9609">SDIO_POWER_PWRCTRL_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga980203971a9f5f4c5e02733c6106249f">SDIO_POWER_PWRCTRL_Pos</a>)</td></tr>
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<tr class="separator:ga85685239a200e250d95c38f310fb9609"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf125c56eeb40163b617c9fb6329da67f" id="r_gaf125c56eeb40163b617c9fb6329da67f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf125c56eeb40163b617c9fb6329da67f">SDIO_POWER_PWRCTRL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga85685239a200e250d95c38f310fb9609">SDIO_POWER_PWRCTRL_Msk</a></td></tr>
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<tr class="separator:gaf125c56eeb40163b617c9fb6329da67f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa82b7689b02f54318d3f629d70b85098" id="r_gaa82b7689b02f54318d3f629d70b85098"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa82b7689b02f54318d3f629d70b85098">SDIO_POWER_PWRCTRL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga980203971a9f5f4c5e02733c6106249f">SDIO_POWER_PWRCTRL_Pos</a>)</td></tr>
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<tr class="separator:gaa82b7689b02f54318d3f629d70b85098"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd149efb1d6062f37165ac01268a875e" id="r_gadd149efb1d6062f37165ac01268a875e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd149efb1d6062f37165ac01268a875e">SDIO_POWER_PWRCTRL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga980203971a9f5f4c5e02733c6106249f">SDIO_POWER_PWRCTRL_Pos</a>)</td></tr>
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<tr class="memitem:ga5b024ad152edaf86ad825ab3fe7450dd" id="r_ga5b024ad152edaf86ad825ab3fe7450dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b024ad152edaf86ad825ab3fe7450dd">SDIO_CLKCR_CLKDIV_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gaa9207dc12eed614d38a8faa4397a6c27" id="r_gaa9207dc12eed614d38a8faa4397a6c27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9207dc12eed614d38a8faa4397a6c27">SDIO_CLKCR_CLKDIV_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b024ad152edaf86ad825ab3fe7450dd">SDIO_CLKCR_CLKDIV_Pos</a>)</td></tr>
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<tr class="memitem:ga316271d0147b22c6267fc563d4c24424" id="r_ga316271d0147b22c6267fc563d4c24424"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga316271d0147b22c6267fc563d4c24424">SDIO_CLKCR_CLKDIV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9207dc12eed614d38a8faa4397a6c27">SDIO_CLKCR_CLKDIV_Msk</a></td></tr>
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<tr class="memitem:ga44234ca6af02a8e44da30f14f77acf09" id="r_ga44234ca6af02a8e44da30f14f77acf09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44234ca6af02a8e44da30f14f77acf09">SDIO_CLKCR_CLKEN_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga44234ca6af02a8e44da30f14f77acf09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0952e49876e16cf5b7a15c2523b210d7" id="r_ga0952e49876e16cf5b7a15c2523b210d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0952e49876e16cf5b7a15c2523b210d7">SDIO_CLKCR_CLKEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga44234ca6af02a8e44da30f14f77acf09">SDIO_CLKCR_CLKEN_Pos</a>)</td></tr>
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<tr class="separator:ga0952e49876e16cf5b7a15c2523b210d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf27847573683f91dbfe387a2571b514f" id="r_gaf27847573683f91dbfe387a2571b514f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf27847573683f91dbfe387a2571b514f">SDIO_CLKCR_CLKEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0952e49876e16cf5b7a15c2523b210d7">SDIO_CLKCR_CLKEN_Msk</a></td></tr>
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<tr class="separator:gaf27847573683f91dbfe387a2571b514f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72c1fdc5e585d2846743b06743c76639" id="r_ga72c1fdc5e585d2846743b06743c76639"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72c1fdc5e585d2846743b06743c76639">SDIO_CLKCR_PWRSAV_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga72c1fdc5e585d2846743b06743c76639"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga258035422cd74f19e644272dc0eb2fa8" id="r_ga258035422cd74f19e644272dc0eb2fa8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga258035422cd74f19e644272dc0eb2fa8">SDIO_CLKCR_PWRSAV_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga72c1fdc5e585d2846743b06743c76639">SDIO_CLKCR_PWRSAV_Pos</a>)</td></tr>
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<tr class="separator:ga258035422cd74f19e644272dc0eb2fa8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbb618f32aef2970fd8b8b285f7b4118" id="r_gafbb618f32aef2970fd8b8b285f7b4118"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbb618f32aef2970fd8b8b285f7b4118">SDIO_CLKCR_PWRSAV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga258035422cd74f19e644272dc0eb2fa8">SDIO_CLKCR_PWRSAV_Msk</a></td></tr>
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<tr class="separator:gafbb618f32aef2970fd8b8b285f7b4118"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d2200f69dd69acf657ed6f3711d5dad" id="r_ga1d2200f69dd69acf657ed6f3711d5dad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d2200f69dd69acf657ed6f3711d5dad">SDIO_CLKCR_BYPASS_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga1d2200f69dd69acf657ed6f3711d5dad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga590aa2168f77032139685f5880229c2d" id="r_ga590aa2168f77032139685f5880229c2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga590aa2168f77032139685f5880229c2d">SDIO_CLKCR_BYPASS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d2200f69dd69acf657ed6f3711d5dad">SDIO_CLKCR_BYPASS_Pos</a>)</td></tr>
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<tr class="separator:ga590aa2168f77032139685f5880229c2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f362c1d228156c50639d79b9be99c9b" id="r_ga1f362c1d228156c50639d79b9be99c9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f362c1d228156c50639d79b9be99c9b">SDIO_CLKCR_BYPASS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga590aa2168f77032139685f5880229c2d">SDIO_CLKCR_BYPASS_Msk</a></td></tr>
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<tr class="separator:ga1f362c1d228156c50639d79b9be99c9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d70e8c1461dadda0df1d84176764b6d" id="r_ga9d70e8c1461dadda0df1d84176764b6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d70e8c1461dadda0df1d84176764b6d">SDIO_CLKCR_WIDBUS_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga9d70e8c1461dadda0df1d84176764b6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d6f1ccab2c96629906dcf01ed68439f" id="r_ga9d6f1ccab2c96629906dcf01ed68439f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d6f1ccab2c96629906dcf01ed68439f">SDIO_CLKCR_WIDBUS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d70e8c1461dadda0df1d84176764b6d">SDIO_CLKCR_WIDBUS_Pos</a>)</td></tr>
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<tr class="separator:ga9d6f1ccab2c96629906dcf01ed68439f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9d57d7917c39bdc5309506e8c28b7d7" id="r_gae9d57d7917c39bdc5309506e8c28b7d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9d57d7917c39bdc5309506e8c28b7d7">SDIO_CLKCR_WIDBUS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d6f1ccab2c96629906dcf01ed68439f">SDIO_CLKCR_WIDBUS_Msk</a></td></tr>
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<tr class="separator:gae9d57d7917c39bdc5309506e8c28b7d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab532dbf366c3fb731488017b0a794151" id="r_gab532dbf366c3fb731488017b0a794151"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab532dbf366c3fb731488017b0a794151">SDIO_CLKCR_WIDBUS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d70e8c1461dadda0df1d84176764b6d">SDIO_CLKCR_WIDBUS_Pos</a>)</td></tr>
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<tr class="separator:gab532dbf366c3fb731488017b0a794151"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49f3e7998bca487f5354ef6f8dffbb21" id="r_ga49f3e7998bca487f5354ef6f8dffbb21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49f3e7998bca487f5354ef6f8dffbb21">SDIO_CLKCR_WIDBUS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d70e8c1461dadda0df1d84176764b6d">SDIO_CLKCR_WIDBUS_Pos</a>)</td></tr>
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<tr class="separator:ga49f3e7998bca487f5354ef6f8dffbb21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3e9d0be4756855a1e5e9753a6605077" id="r_gae3e9d0be4756855a1e5e9753a6605077"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3e9d0be4756855a1e5e9753a6605077">SDIO_CLKCR_NEGEDGE_Pos</a>   (13U)</td></tr>
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<tr class="separator:gae3e9d0be4756855a1e5e9753a6605077"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a4df6f204feaf9a52a36b6bbf8987ef" id="r_ga5a4df6f204feaf9a52a36b6bbf8987ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a4df6f204feaf9a52a36b6bbf8987ef">SDIO_CLKCR_NEGEDGE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3e9d0be4756855a1e5e9753a6605077">SDIO_CLKCR_NEGEDGE_Pos</a>)</td></tr>
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<tr class="separator:ga5a4df6f204feaf9a52a36b6bbf8987ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad124bd76f6543497c90372e182ec48a2" id="r_gad124bd76f6543497c90372e182ec48a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad124bd76f6543497c90372e182ec48a2">SDIO_CLKCR_NEGEDGE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a4df6f204feaf9a52a36b6bbf8987ef">SDIO_CLKCR_NEGEDGE_Msk</a></td></tr>
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<tr class="separator:gad124bd76f6543497c90372e182ec48a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1318e107062a376681c0d8cdc18332f3" id="r_ga1318e107062a376681c0d8cdc18332f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1318e107062a376681c0d8cdc18332f3">SDIO_CLKCR_HWFC_EN_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga1318e107062a376681c0d8cdc18332f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae43747a95ebebe7388114ed6990b976" id="r_gaae43747a95ebebe7388114ed6990b976"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae43747a95ebebe7388114ed6990b976">SDIO_CLKCR_HWFC_EN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1318e107062a376681c0d8cdc18332f3">SDIO_CLKCR_HWFC_EN_Pos</a>)</td></tr>
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<tr class="separator:gaae43747a95ebebe7388114ed6990b976"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga693d7b533dd5a5a668bc13b4365b18dc" id="r_ga693d7b533dd5a5a668bc13b4365b18dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga693d7b533dd5a5a668bc13b4365b18dc">SDIO_CLKCR_HWFC_EN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae43747a95ebebe7388114ed6990b976">SDIO_CLKCR_HWFC_EN_Msk</a></td></tr>
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<tr class="separator:ga693d7b533dd5a5a668bc13b4365b18dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd212d9a3891e8c282f50e82c207cce7" id="r_gafd212d9a3891e8c282f50e82c207cce7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd212d9a3891e8c282f50e82c207cce7">SDIO_ARG_CMDARG_Pos</a>   (0U)</td></tr>
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<tr class="separator:gafd212d9a3891e8c282f50e82c207cce7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c0c162d6eb9a15399e1fdc00a8a711f" id="r_ga2c0c162d6eb9a15399e1fdc00a8a711f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c0c162d6eb9a15399e1fdc00a8a711f">SDIO_ARG_CMDARG_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafd212d9a3891e8c282f50e82c207cce7">SDIO_ARG_CMDARG_Pos</a>)</td></tr>
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<tr class="separator:ga2c0c162d6eb9a15399e1fdc00a8a711f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d917a4fdc7442e270c2c727df78b819" id="r_ga2d917a4fdc7442e270c2c727df78b819"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d917a4fdc7442e270c2c727df78b819">SDIO_ARG_CMDARG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c0c162d6eb9a15399e1fdc00a8a711f">SDIO_ARG_CMDARG_Msk</a></td></tr>
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<tr class="separator:ga2d917a4fdc7442e270c2c727df78b819"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63a301afc3b24e6825aca5911f2292f7" id="r_ga63a301afc3b24e6825aca5911f2292f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63a301afc3b24e6825aca5911f2292f7">SDIO_CMD_CMDINDEX_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga5864df752017e82b545ecbef7a434000" id="r_ga5864df752017e82b545ecbef7a434000"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5864df752017e82b545ecbef7a434000">SDIO_CMD_CMDINDEX_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga63a301afc3b24e6825aca5911f2292f7">SDIO_CMD_CMDINDEX_Pos</a>)</td></tr>
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<tr class="memitem:gaf91b593b5681a68db5ff9fd11600c9c8" id="r_gaf91b593b5681a68db5ff9fd11600c9c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf91b593b5681a68db5ff9fd11600c9c8">SDIO_CMD_CMDINDEX</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5864df752017e82b545ecbef7a434000">SDIO_CMD_CMDINDEX_Msk</a></td></tr>
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<tr class="memitem:gada8d884fac89d07c59f335635ba5cc6a" id="r_gada8d884fac89d07c59f335635ba5cc6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada8d884fac89d07c59f335635ba5cc6a">SDIO_CMD_WAITRESP_Pos</a>   (6U)</td></tr>
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<tr class="memitem:ga41c83bc85012033738be4722741c644e" id="r_ga41c83bc85012033738be4722741c644e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41c83bc85012033738be4722741c644e">SDIO_CMD_WAITRESP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada8d884fac89d07c59f335635ba5cc6a">SDIO_CMD_WAITRESP_Pos</a>)</td></tr>
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<tr class="memitem:ga5d617f0e08d697c3b263e6a79f417d0f" id="r_ga5d617f0e08d697c3b263e6a79f417d0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d617f0e08d697c3b263e6a79f417d0f">SDIO_CMD_WAITRESP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga41c83bc85012033738be4722741c644e">SDIO_CMD_WAITRESP_Msk</a></td></tr>
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<tr class="memitem:gae5797a389fecf611dccd483658b822fa" id="r_gae5797a389fecf611dccd483658b822fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5797a389fecf611dccd483658b822fa">SDIO_CMD_WAITRESP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada8d884fac89d07c59f335635ba5cc6a">SDIO_CMD_WAITRESP_Pos</a>)</td></tr>
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<tr class="memitem:ga8f5457b48feda0056466e5c380c44373" id="r_ga8f5457b48feda0056466e5c380c44373"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f5457b48feda0056466e5c380c44373">SDIO_CMD_WAITRESP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada8d884fac89d07c59f335635ba5cc6a">SDIO_CMD_WAITRESP_Pos</a>)</td></tr>
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<tr class="memitem:gad6a63d6e5b6dbabf23b6c8da0a3582c9" id="r_gad6a63d6e5b6dbabf23b6c8da0a3582c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6a63d6e5b6dbabf23b6c8da0a3582c9">SDIO_CMD_WAITINT_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga214e7747364d52fe038e33df70453c7b" id="r_ga214e7747364d52fe038e33df70453c7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga214e7747364d52fe038e33df70453c7b">SDIO_CMD_WAITINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad6a63d6e5b6dbabf23b6c8da0a3582c9">SDIO_CMD_WAITINT_Pos</a>)</td></tr>
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<tr class="memitem:ga4b037f34e297f38d56b14d46d008ef58" id="r_ga4b037f34e297f38d56b14d46d008ef58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b037f34e297f38d56b14d46d008ef58">SDIO_CMD_WAITINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga214e7747364d52fe038e33df70453c7b">SDIO_CMD_WAITINT_Msk</a></td></tr>
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<tr class="memitem:ga5a1219464c590ed80ea38fcf28c8335a" id="r_ga5a1219464c590ed80ea38fcf28c8335a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a1219464c590ed80ea38fcf28c8335a">SDIO_CMD_WAITPEND_Pos</a>   (9U)</td></tr>
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<tr class="memitem:gae565c2ebe48768e1e6a8638c5f8df583" id="r_gae565c2ebe48768e1e6a8638c5f8df583"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae565c2ebe48768e1e6a8638c5f8df583">SDIO_CMD_WAITPEND_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a1219464c590ed80ea38fcf28c8335a">SDIO_CMD_WAITPEND_Pos</a>)</td></tr>
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<tr class="memitem:gaf4118c9200bae6732764f6c87a0962a9" id="r_gaf4118c9200bae6732764f6c87a0962a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4118c9200bae6732764f6c87a0962a9">SDIO_CMD_WAITPEND</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae565c2ebe48768e1e6a8638c5f8df583">SDIO_CMD_WAITPEND_Msk</a></td></tr>
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<tr class="separator:gaf4118c9200bae6732764f6c87a0962a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bcdcc89ef5863164462de6750a74caf" id="r_ga0bcdcc89ef5863164462de6750a74caf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bcdcc89ef5863164462de6750a74caf">SDIO_CMD_CPSMEN_Pos</a>   (10U)</td></tr>
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<tr class="memitem:ga6f7c4c45069c802f2118cc0135d12dfe" id="r_ga6f7c4c45069c802f2118cc0135d12dfe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f7c4c45069c802f2118cc0135d12dfe">SDIO_CMD_CPSMEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bcdcc89ef5863164462de6750a74caf">SDIO_CMD_CPSMEN_Pos</a>)</td></tr>
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<tr class="memitem:ga982f3fd09ce7e31709e0628b1fae86b8" id="r_ga982f3fd09ce7e31709e0628b1fae86b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga982f3fd09ce7e31709e0628b1fae86b8">SDIO_CMD_CPSMEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f7c4c45069c802f2118cc0135d12dfe">SDIO_CMD_CPSMEN_Msk</a></td></tr>
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<tr class="memitem:ga69aeafb35e44b4b432e71cd4cc29e15b" id="r_ga69aeafb35e44b4b432e71cd4cc29e15b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69aeafb35e44b4b432e71cd4cc29e15b">SDIO_CMD_SDIOSUSPEND_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga69aeafb35e44b4b432e71cd4cc29e15b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeecad1b553de683cb5cf9010d84b70d6" id="r_gaeecad1b553de683cb5cf9010d84b70d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeecad1b553de683cb5cf9010d84b70d6">SDIO_CMD_SDIOSUSPEND_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69aeafb35e44b4b432e71cd4cc29e15b">SDIO_CMD_SDIOSUSPEND_Pos</a>)</td></tr>
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<tr class="memitem:gad560080c3e7ab5aeafe151dafcc64368" id="r_gad560080c3e7ab5aeafe151dafcc64368"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad560080c3e7ab5aeafe151dafcc64368">SDIO_CMD_SDIOSUSPEND</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeecad1b553de683cb5cf9010d84b70d6">SDIO_CMD_SDIOSUSPEND_Msk</a></td></tr>
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<tr class="memitem:gae2bceb6b0e29e84ad08434948b17059c" id="r_gae2bceb6b0e29e84ad08434948b17059c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2bceb6b0e29e84ad08434948b17059c">SDIO_CMD_ENCMDCOMPL_Pos</a>   (12U)</td></tr>
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<tr class="memitem:gafcf48c2b726056d5e994836644481617" id="r_gafcf48c2b726056d5e994836644481617"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcf48c2b726056d5e994836644481617">SDIO_CMD_ENCMDCOMPL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae2bceb6b0e29e84ad08434948b17059c">SDIO_CMD_ENCMDCOMPL_Pos</a>)</td></tr>
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<tr class="memitem:ga905b78ecf464857e6501ef5fd5e6ef1b" id="r_ga905b78ecf464857e6501ef5fd5e6ef1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga905b78ecf464857e6501ef5fd5e6ef1b">SDIO_CMD_ENCMDCOMPL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafcf48c2b726056d5e994836644481617">SDIO_CMD_ENCMDCOMPL_Msk</a></td></tr>
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<tr class="separator:ga905b78ecf464857e6501ef5fd5e6ef1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdc4381d56669dc173b95c161cf92954" id="r_gacdc4381d56669dc173b95c161cf92954"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdc4381d56669dc173b95c161cf92954">SDIO_CMD_NIEN_Pos</a>   (13U)</td></tr>
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<tr class="memitem:gaa07629f3e99beeb0e3d2ec96a6584f5a" id="r_gaa07629f3e99beeb0e3d2ec96a6584f5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa07629f3e99beeb0e3d2ec96a6584f5a">SDIO_CMD_NIEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacdc4381d56669dc173b95c161cf92954">SDIO_CMD_NIEN_Pos</a>)</td></tr>
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<tr class="memitem:ga3a9d5b2366ec7ca38db9d6d9f0f63f81" id="r_ga3a9d5b2366ec7ca38db9d6d9f0f63f81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a9d5b2366ec7ca38db9d6d9f0f63f81">SDIO_CMD_NIEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa07629f3e99beeb0e3d2ec96a6584f5a">SDIO_CMD_NIEN_Msk</a></td></tr>
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<tr class="memitem:ga9e4c944917a79c48b8393a4ca0208580" id="r_ga9e4c944917a79c48b8393a4ca0208580"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e4c944917a79c48b8393a4ca0208580">SDIO_CMD_CEATACMD_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga9e4c944917a79c48b8393a4ca0208580"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68429f74d1213129ab97de545b433d83" id="r_ga68429f74d1213129ab97de545b433d83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68429f74d1213129ab97de545b433d83">SDIO_CMD_CEATACMD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e4c944917a79c48b8393a4ca0208580">SDIO_CMD_CEATACMD_Pos</a>)</td></tr>
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<tr class="memitem:ga87422225274de986e7abe6b2a91a79c5" id="r_ga87422225274de986e7abe6b2a91a79c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87422225274de986e7abe6b2a91a79c5">SDIO_CMD_CEATACMD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga68429f74d1213129ab97de545b433d83">SDIO_CMD_CEATACMD_Msk</a></td></tr>
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<tr class="memitem:ga53f5c709c72c524a03ed26cc6a246f1a" id="r_ga53f5c709c72c524a03ed26cc6a246f1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53f5c709c72c524a03ed26cc6a246f1a">SDIO_RESPCMD_RESPCMD_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga53f5c709c72c524a03ed26cc6a246f1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f937e878d203e9f9dda3e12cec73153" id="r_ga0f937e878d203e9f9dda3e12cec73153"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f937e878d203e9f9dda3e12cec73153">SDIO_RESPCMD_RESPCMD_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga53f5c709c72c524a03ed26cc6a246f1a">SDIO_RESPCMD_RESPCMD_Pos</a>)</td></tr>
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<tr class="separator:ga0f937e878d203e9f9dda3e12cec73153"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27f9a6cbfd364bbb050b526ebc01d2d7" id="r_ga27f9a6cbfd364bbb050b526ebc01d2d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27f9a6cbfd364bbb050b526ebc01d2d7">SDIO_RESPCMD_RESPCMD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f937e878d203e9f9dda3e12cec73153">SDIO_RESPCMD_RESPCMD_Msk</a></td></tr>
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<tr class="memitem:ga0050e8b5acaf5716002877e15744cea1" id="r_ga0050e8b5acaf5716002877e15744cea1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0050e8b5acaf5716002877e15744cea1">SDIO_RESP0_CARDSTATUS0_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga3f6aa725abdb56f38c3c8783b9f15e47" id="r_ga3f6aa725abdb56f38c3c8783b9f15e47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f6aa725abdb56f38c3c8783b9f15e47">SDIO_RESP0_CARDSTATUS0_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0050e8b5acaf5716002877e15744cea1">SDIO_RESP0_CARDSTATUS0_Pos</a>)</td></tr>
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<tr class="separator:ga3f6aa725abdb56f38c3c8783b9f15e47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56a55231f7a91cfd2cefaca0f6135cbc" id="r_ga56a55231f7a91cfd2cefaca0f6135cbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56a55231f7a91cfd2cefaca0f6135cbc">SDIO_RESP0_CARDSTATUS0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f6aa725abdb56f38c3c8783b9f15e47">SDIO_RESP0_CARDSTATUS0_Msk</a></td></tr>
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<tr class="separator:ga56a55231f7a91cfd2cefaca0f6135cbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdf3d65acd80e89c5b3a85759cbf11ae" id="r_gacdf3d65acd80e89c5b3a85759cbf11ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdf3d65acd80e89c5b3a85759cbf11ae">SDIO_RESP1_CARDSTATUS1_Pos</a>   (0U)</td></tr>
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<tr class="separator:gacdf3d65acd80e89c5b3a85759cbf11ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccbe896832554a212ce0eb8d7650b850" id="r_gaccbe896832554a212ce0eb8d7650b850"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccbe896832554a212ce0eb8d7650b850">SDIO_RESP1_CARDSTATUS1_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacdf3d65acd80e89c5b3a85759cbf11ae">SDIO_RESP1_CARDSTATUS1_Pos</a>)</td></tr>
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<tr class="separator:gaccbe896832554a212ce0eb8d7650b850"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d20abddfc99835a2954eda5899f6db1" id="r_ga1d20abddfc99835a2954eda5899f6db1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d20abddfc99835a2954eda5899f6db1">SDIO_RESP1_CARDSTATUS1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaccbe896832554a212ce0eb8d7650b850">SDIO_RESP1_CARDSTATUS1_Msk</a></td></tr>
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<tr class="separator:ga1d20abddfc99835a2954eda5899f6db1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4fe5348e4b89d1b8307a399d2696684" id="r_gac4fe5348e4b89d1b8307a399d2696684"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4fe5348e4b89d1b8307a399d2696684">SDIO_RESP2_CARDSTATUS2_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac4fe5348e4b89d1b8307a399d2696684"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb0ef49057b923f3518c6f055a79b605" id="r_gafb0ef49057b923f3518c6f055a79b605"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb0ef49057b923f3518c6f055a79b605">SDIO_RESP2_CARDSTATUS2_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4fe5348e4b89d1b8307a399d2696684">SDIO_RESP2_CARDSTATUS2_Pos</a>)</td></tr>
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<tr class="separator:gafb0ef49057b923f3518c6f055a79b605"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31a482ff36bde1df56ab603c864c4066" id="r_ga31a482ff36bde1df56ab603c864c4066"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31a482ff36bde1df56ab603c864c4066">SDIO_RESP2_CARDSTATUS2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb0ef49057b923f3518c6f055a79b605">SDIO_RESP2_CARDSTATUS2_Msk</a></td></tr>
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<tr class="separator:ga31a482ff36bde1df56ab603c864c4066"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cc1aa3203ce39c556e1631c05d911ea" id="r_ga6cc1aa3203ce39c556e1631c05d911ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cc1aa3203ce39c556e1631c05d911ea">SDIO_RESP3_CARDSTATUS3_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga6cc1aa3203ce39c556e1631c05d911ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab48a641918cdc42f1f8da11703329a04" id="r_gab48a641918cdc42f1f8da11703329a04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab48a641918cdc42f1f8da11703329a04">SDIO_RESP3_CARDSTATUS3_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cc1aa3203ce39c556e1631c05d911ea">SDIO_RESP3_CARDSTATUS3_Pos</a>)</td></tr>
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<tr class="separator:gab48a641918cdc42f1f8da11703329a04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1075c96b5818b0500d5cce231ace89cf" id="r_ga1075c96b5818b0500d5cce231ace89cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1075c96b5818b0500d5cce231ace89cf">SDIO_RESP3_CARDSTATUS3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab48a641918cdc42f1f8da11703329a04">SDIO_RESP3_CARDSTATUS3_Msk</a></td></tr>
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<tr class="separator:ga1075c96b5818b0500d5cce231ace89cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5fc053049c54b41a638649c8990c5b1" id="r_gae5fc053049c54b41a638649c8990c5b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5fc053049c54b41a638649c8990c5b1">SDIO_RESP4_CARDSTATUS4_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae5fc053049c54b41a638649c8990c5b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38cdffc0bf0950e987e8380d8f89f4c0" id="r_ga38cdffc0bf0950e987e8380d8f89f4c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38cdffc0bf0950e987e8380d8f89f4c0">SDIO_RESP4_CARDSTATUS4_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5fc053049c54b41a638649c8990c5b1">SDIO_RESP4_CARDSTATUS4_Pos</a>)</td></tr>
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<tr class="separator:ga38cdffc0bf0950e987e8380d8f89f4c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga407ab1e46a80426602ab36e86457da26" id="r_ga407ab1e46a80426602ab36e86457da26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga407ab1e46a80426602ab36e86457da26">SDIO_RESP4_CARDSTATUS4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38cdffc0bf0950e987e8380d8f89f4c0">SDIO_RESP4_CARDSTATUS4_Msk</a></td></tr>
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<tr class="separator:ga407ab1e46a80426602ab36e86457da26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fe60be41b16f6fb05af07517115eda1" id="r_ga5fe60be41b16f6fb05af07517115eda1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe60be41b16f6fb05af07517115eda1">SDIO_DTIMER_DATATIME_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5fe60be41b16f6fb05af07517115eda1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ca7786fe8c3ebf5bf4b107ad2693b77" id="r_ga8ca7786fe8c3ebf5bf4b107ad2693b77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ca7786fe8c3ebf5bf4b107ad2693b77">SDIO_DTIMER_DATATIME_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe60be41b16f6fb05af07517115eda1">SDIO_DTIMER_DATATIME_Pos</a>)</td></tr>
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<tr class="separator:ga8ca7786fe8c3ebf5bf4b107ad2693b77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27e45eea9ce17b7251f10ea763180690" id="r_ga27e45eea9ce17b7251f10ea763180690"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27e45eea9ce17b7251f10ea763180690">SDIO_DTIMER_DATATIME</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ca7786fe8c3ebf5bf4b107ad2693b77">SDIO_DTIMER_DATATIME_Msk</a></td></tr>
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<tr class="separator:ga27e45eea9ce17b7251f10ea763180690"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb3ed134b1944407d86a64baff57bfbc" id="r_gabb3ed134b1944407d86a64baff57bfbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb3ed134b1944407d86a64baff57bfbc">SDIO_DLEN_DATALENGTH_Pos</a>   (0U)</td></tr>
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<tr class="separator:gabb3ed134b1944407d86a64baff57bfbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c419dbe5ccdf09fe276a876c5b644cf" id="r_ga5c419dbe5ccdf09fe276a876c5b644cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c419dbe5ccdf09fe276a876c5b644cf">SDIO_DLEN_DATALENGTH_Msk</a>   (0x1FFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb3ed134b1944407d86a64baff57bfbc">SDIO_DLEN_DATALENGTH_Pos</a>)</td></tr>
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<tr class="separator:ga5c419dbe5ccdf09fe276a876c5b644cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d3b07bca9aec8ef5456ba9b73f13adb" id="r_ga4d3b07bca9aec8ef5456ba9b73f13adb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d3b07bca9aec8ef5456ba9b73f13adb">SDIO_DLEN_DATALENGTH</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c419dbe5ccdf09fe276a876c5b644cf">SDIO_DLEN_DATALENGTH_Msk</a></td></tr>
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<tr class="separator:ga4d3b07bca9aec8ef5456ba9b73f13adb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5833159c058fcd329336b2259f33d20" id="r_gac5833159c058fcd329336b2259f33d20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5833159c058fcd329336b2259f33d20">SDIO_DCTRL_DTEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac5833159c058fcd329336b2259f33d20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01116e33cb68129902284211af9f0e2e" id="r_ga01116e33cb68129902284211af9f0e2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01116e33cb68129902284211af9f0e2e">SDIO_DCTRL_DTEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac5833159c058fcd329336b2259f33d20">SDIO_DCTRL_DTEN_Pos</a>)</td></tr>
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<tr class="separator:ga01116e33cb68129902284211af9f0e2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa03ff8fb9ff70e0a623a5c1f7aa2bc9a" id="r_gaa03ff8fb9ff70e0a623a5c1f7aa2bc9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa03ff8fb9ff70e0a623a5c1f7aa2bc9a">SDIO_DCTRL_DTEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga01116e33cb68129902284211af9f0e2e">SDIO_DCTRL_DTEN_Msk</a></td></tr>
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<tr class="separator:gaa03ff8fb9ff70e0a623a5c1f7aa2bc9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga306751502891360398d0046e484e418b" id="r_ga306751502891360398d0046e484e418b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga306751502891360398d0046e484e418b">SDIO_DCTRL_DTDIR_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga306751502891360398d0046e484e418b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f8fcebfcdcd58383a72b8503f74597f" id="r_ga5f8fcebfcdcd58383a72b8503f74597f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f8fcebfcdcd58383a72b8503f74597f">SDIO_DCTRL_DTDIR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga306751502891360398d0046e484e418b">SDIO_DCTRL_DTDIR_Pos</a>)</td></tr>
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<tr class="separator:ga5f8fcebfcdcd58383a72b8503f74597f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga801fe27f7175a308d56776db19776c93" id="r_ga801fe27f7175a308d56776db19776c93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga801fe27f7175a308d56776db19776c93">SDIO_DCTRL_DTDIR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f8fcebfcdcd58383a72b8503f74597f">SDIO_DCTRL_DTDIR_Msk</a></td></tr>
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<tr class="separator:ga801fe27f7175a308d56776db19776c93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6f10964c5da8676885eda5000d33c1a" id="r_gaa6f10964c5da8676885eda5000d33c1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6f10964c5da8676885eda5000d33c1a">SDIO_DCTRL_DTMODE_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaa6f10964c5da8676885eda5000d33c1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78a712204e817e6ce1a96ffa421107fb" id="r_ga78a712204e817e6ce1a96ffa421107fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78a712204e817e6ce1a96ffa421107fb">SDIO_DCTRL_DTMODE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6f10964c5da8676885eda5000d33c1a">SDIO_DCTRL_DTMODE_Pos</a>)</td></tr>
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<tr class="separator:ga78a712204e817e6ce1a96ffa421107fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa90cd50ae364b992ca8ccab319eb5513" id="r_gaa90cd50ae364b992ca8ccab319eb5513"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa90cd50ae364b992ca8ccab319eb5513">SDIO_DCTRL_DTMODE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a712204e817e6ce1a96ffa421107fb">SDIO_DCTRL_DTMODE_Msk</a></td></tr>
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<tr class="separator:gaa90cd50ae364b992ca8ccab319eb5513"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69e2071d77bd39d1d206ad785ea4b1f7" id="r_ga69e2071d77bd39d1d206ad785ea4b1f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69e2071d77bd39d1d206ad785ea4b1f7">SDIO_DCTRL_DMAEN_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga69e2071d77bd39d1d206ad785ea4b1f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga947764dd929d0a703312d684ea22f214" id="r_ga947764dd929d0a703312d684ea22f214"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga947764dd929d0a703312d684ea22f214">SDIO_DCTRL_DMAEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69e2071d77bd39d1d206ad785ea4b1f7">SDIO_DCTRL_DMAEN_Pos</a>)</td></tr>
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<tr class="separator:ga947764dd929d0a703312d684ea22f214"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03a2148910ae02dde7e4cd63e0f5e008" id="r_ga03a2148910ae02dde7e4cd63e0f5e008"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03a2148910ae02dde7e4cd63e0f5e008">SDIO_DCTRL_DMAEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga947764dd929d0a703312d684ea22f214">SDIO_DCTRL_DMAEN_Msk</a></td></tr>
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<tr class="separator:ga03a2148910ae02dde7e4cd63e0f5e008"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga119e44ccdca8f6bad3f3ad773bdd37c4" id="r_ga119e44ccdca8f6bad3f3ad773bdd37c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga119e44ccdca8f6bad3f3ad773bdd37c4">SDIO_DCTRL_DBLOCKSIZE_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga119e44ccdca8f6bad3f3ad773bdd37c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed2493217bf1583aa33c8f1d755904a6" id="r_gaed2493217bf1583aa33c8f1d755904a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed2493217bf1583aa33c8f1d755904a6">SDIO_DCTRL_DBLOCKSIZE_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga119e44ccdca8f6bad3f3ad773bdd37c4">SDIO_DCTRL_DBLOCKSIZE_Pos</a>)</td></tr>
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<tr class="separator:gaed2493217bf1583aa33c8f1d755904a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga948072d8a6db53d0c377944523a4b15a" id="r_ga948072d8a6db53d0c377944523a4b15a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga948072d8a6db53d0c377944523a4b15a">SDIO_DCTRL_DBLOCKSIZE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaed2493217bf1583aa33c8f1d755904a6">SDIO_DCTRL_DBLOCKSIZE_Msk</a></td></tr>
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<tr class="separator:ga948072d8a6db53d0c377944523a4b15a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51e2cb99cf325bb32c8910204b1507db" id="r_ga51e2cb99cf325bb32c8910204b1507db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51e2cb99cf325bb32c8910204b1507db">SDIO_DCTRL_DBLOCKSIZE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga119e44ccdca8f6bad3f3ad773bdd37c4">SDIO_DCTRL_DBLOCKSIZE_Pos</a>)</td></tr>
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<tr class="memitem:ga0add3ad2b72a21e7f8d48da3ea0b3d0f" id="r_ga0add3ad2b72a21e7f8d48da3ea0b3d0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0add3ad2b72a21e7f8d48da3ea0b3d0f">SDIO_DCTRL_DBLOCKSIZE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga119e44ccdca8f6bad3f3ad773bdd37c4">SDIO_DCTRL_DBLOCKSIZE_Pos</a>)</td></tr>
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<tr class="separator:ga0add3ad2b72a21e7f8d48da3ea0b3d0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93825036eceb86872e2ca179c63163ec" id="r_ga93825036eceb86872e2ca179c63163ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93825036eceb86872e2ca179c63163ec">SDIO_DCTRL_DBLOCKSIZE_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga119e44ccdca8f6bad3f3ad773bdd37c4">SDIO_DCTRL_DBLOCKSIZE_Pos</a>)</td></tr>
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<tr class="memitem:gac2025aa63b595bfccc747b99caec8799" id="r_gac2025aa63b595bfccc747b99caec8799"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2025aa63b595bfccc747b99caec8799">SDIO_DCTRL_DBLOCKSIZE_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga119e44ccdca8f6bad3f3ad773bdd37c4">SDIO_DCTRL_DBLOCKSIZE_Pos</a>)</td></tr>
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<tr class="separator:gac2025aa63b595bfccc747b99caec8799"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2799704f4cb1d6a7165360302ad5487e" id="r_ga2799704f4cb1d6a7165360302ad5487e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2799704f4cb1d6a7165360302ad5487e">SDIO_DCTRL_RWSTART_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga2799704f4cb1d6a7165360302ad5487e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7c075ad5172d81d8a0ebbba7bd368a1" id="r_gad7c075ad5172d81d8a0ebbba7bd368a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7c075ad5172d81d8a0ebbba7bd368a1">SDIO_DCTRL_RWSTART_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2799704f4cb1d6a7165360302ad5487e">SDIO_DCTRL_RWSTART_Pos</a>)</td></tr>
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<tr class="separator:gad7c075ad5172d81d8a0ebbba7bd368a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe9600da3e751118d49ea14ce44e91b9" id="r_gafe9600da3e751118d49ea14ce44e91b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe9600da3e751118d49ea14ce44e91b9">SDIO_DCTRL_RWSTART</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad7c075ad5172d81d8a0ebbba7bd368a1">SDIO_DCTRL_RWSTART_Msk</a></td></tr>
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<tr class="separator:gafe9600da3e751118d49ea14ce44e91b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22dbec68a4c108406a71258aa0b42cba" id="r_ga22dbec68a4c108406a71258aa0b42cba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22dbec68a4c108406a71258aa0b42cba">SDIO_DCTRL_RWSTOP_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga22dbec68a4c108406a71258aa0b42cba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b25f8c2f40d6767bd6b61edb4891e7b" id="r_ga4b25f8c2f40d6767bd6b61edb4891e7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b25f8c2f40d6767bd6b61edb4891e7b">SDIO_DCTRL_RWSTOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga22dbec68a4c108406a71258aa0b42cba">SDIO_DCTRL_RWSTOP_Pos</a>)</td></tr>
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<tr class="separator:ga4b25f8c2f40d6767bd6b61edb4891e7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f1b5b6a32ce712fbb3767090b1b045e" id="r_ga3f1b5b6a32ce712fbb3767090b1b045e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f1b5b6a32ce712fbb3767090b1b045e">SDIO_DCTRL_RWSTOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b25f8c2f40d6767bd6b61edb4891e7b">SDIO_DCTRL_RWSTOP_Msk</a></td></tr>
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<tr class="separator:ga3f1b5b6a32ce712fbb3767090b1b045e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0745b75ed0809ab27ddee511b7821595" id="r_ga0745b75ed0809ab27ddee511b7821595"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0745b75ed0809ab27ddee511b7821595">SDIO_DCTRL_RWMOD_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga0745b75ed0809ab27ddee511b7821595"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cbe9685d3f55431f7492463b902655b" id="r_ga5cbe9685d3f55431f7492463b902655b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5cbe9685d3f55431f7492463b902655b">SDIO_DCTRL_RWMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0745b75ed0809ab27ddee511b7821595">SDIO_DCTRL_RWMOD_Pos</a>)</td></tr>
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<tr class="separator:ga5cbe9685d3f55431f7492463b902655b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bf721a25f656b3de6fa0b0fe32edb6a" id="r_ga4bf721a25f656b3de6fa0b0fe32edb6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bf721a25f656b3de6fa0b0fe32edb6a">SDIO_DCTRL_RWMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cbe9685d3f55431f7492463b902655b">SDIO_DCTRL_RWMOD_Msk</a></td></tr>
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<tr class="separator:ga4bf721a25f656b3de6fa0b0fe32edb6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga998b276365f499e3af5dc3e784c728bf" id="r_ga998b276365f499e3af5dc3e784c728bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga998b276365f499e3af5dc3e784c728bf">SDIO_DCTRL_SDIOEN_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga998b276365f499e3af5dc3e784c728bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbedb5de0b884547782c44dc914795c9" id="r_gafbedb5de0b884547782c44dc914795c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbedb5de0b884547782c44dc914795c9">SDIO_DCTRL_SDIOEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga998b276365f499e3af5dc3e784c728bf">SDIO_DCTRL_SDIOEN_Pos</a>)</td></tr>
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<tr class="separator:gafbedb5de0b884547782c44dc914795c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa16b4c4037cf974162a591aea753fc21" id="r_gaa16b4c4037cf974162a591aea753fc21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa16b4c4037cf974162a591aea753fc21">SDIO_DCTRL_SDIOEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafbedb5de0b884547782c44dc914795c9">SDIO_DCTRL_SDIOEN_Msk</a></td></tr>
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<tr class="memitem:ga403440b7adc8fe670be0dc8786a0911b" id="r_ga403440b7adc8fe670be0dc8786a0911b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga403440b7adc8fe670be0dc8786a0911b">SDIO_DCOUNT_DATACOUNT_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga403440b7adc8fe670be0dc8786a0911b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac482f1add1ce39f8fb7c3bc9d8653f77" id="r_gac482f1add1ce39f8fb7c3bc9d8653f77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac482f1add1ce39f8fb7c3bc9d8653f77">SDIO_DCOUNT_DATACOUNT_Msk</a>   (0x1FFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga403440b7adc8fe670be0dc8786a0911b">SDIO_DCOUNT_DATACOUNT_Pos</a>)</td></tr>
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<tr class="separator:gac482f1add1ce39f8fb7c3bc9d8653f77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f8ab9dfe9d4f809b61fa2b7826adbde" id="r_ga2f8ab9dfe9d4f809b61fa2b7826adbde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f8ab9dfe9d4f809b61fa2b7826adbde">SDIO_DCOUNT_DATACOUNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac482f1add1ce39f8fb7c3bc9d8653f77">SDIO_DCOUNT_DATACOUNT_Msk</a></td></tr>
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<tr class="separator:ga2f8ab9dfe9d4f809b61fa2b7826adbde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb2c0bead439847c163d2b4166d3b7c8" id="r_gaeb2c0bead439847c163d2b4166d3b7c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb2c0bead439847c163d2b4166d3b7c8">SDIO_STA_CCRCFAIL_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaeb2c0bead439847c163d2b4166d3b7c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae72a4ab40725d2063cb2900512f79e57" id="r_gae72a4ab40725d2063cb2900512f79e57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae72a4ab40725d2063cb2900512f79e57">SDIO_STA_CCRCFAIL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb2c0bead439847c163d2b4166d3b7c8">SDIO_STA_CCRCFAIL_Pos</a>)</td></tr>
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<tr class="memitem:gad6dbe59c4bdd8b9a12b092cf84a9daef" id="r_gad6dbe59c4bdd8b9a12b092cf84a9daef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6dbe59c4bdd8b9a12b092cf84a9daef">SDIO_STA_CCRCFAIL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae72a4ab40725d2063cb2900512f79e57">SDIO_STA_CCRCFAIL_Msk</a></td></tr>
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<tr class="memitem:gad788ced0bde93f188aed790a18cdde65" id="r_gad788ced0bde93f188aed790a18cdde65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad788ced0bde93f188aed790a18cdde65">SDIO_STA_DCRCFAIL_Pos</a>   (1U)</td></tr>
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<tr class="memitem:gad51a35e09d9332c7402e7db2dd3b63d2" id="r_gad51a35e09d9332c7402e7db2dd3b63d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad51a35e09d9332c7402e7db2dd3b63d2">SDIO_STA_DCRCFAIL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad788ced0bde93f188aed790a18cdde65">SDIO_STA_DCRCFAIL_Pos</a>)</td></tr>
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<tr class="separator:gad51a35e09d9332c7402e7db2dd3b63d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga554d1f9986bf5c715dd6f27a6493ce31" id="r_ga554d1f9986bf5c715dd6f27a6493ce31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga554d1f9986bf5c715dd6f27a6493ce31">SDIO_STA_DCRCFAIL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad51a35e09d9332c7402e7db2dd3b63d2">SDIO_STA_DCRCFAIL_Msk</a></td></tr>
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<tr class="separator:ga554d1f9986bf5c715dd6f27a6493ce31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c834436a9afa85d118ef4a83f7cb283" id="r_ga1c834436a9afa85d118ef4a83f7cb283"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c834436a9afa85d118ef4a83f7cb283">SDIO_STA_CTIMEOUT_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga1c834436a9afa85d118ef4a83f7cb283"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27433ab3bb7c09bfd6c7e65daee2c1c2" id="r_ga27433ab3bb7c09bfd6c7e65daee2c1c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27433ab3bb7c09bfd6c7e65daee2c1c2">SDIO_STA_CTIMEOUT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c834436a9afa85d118ef4a83f7cb283">SDIO_STA_CTIMEOUT_Pos</a>)</td></tr>
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<tr class="separator:ga27433ab3bb7c09bfd6c7e65daee2c1c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae72c4f34bb3ccffeef1d7cdcb7415bdc" id="r_gae72c4f34bb3ccffeef1d7cdcb7415bdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae72c4f34bb3ccffeef1d7cdcb7415bdc">SDIO_STA_CTIMEOUT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga27433ab3bb7c09bfd6c7e65daee2c1c2">SDIO_STA_CTIMEOUT_Msk</a></td></tr>
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<tr class="separator:gae72c4f34bb3ccffeef1d7cdcb7415bdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga889faf1ecb5ebaf770074f4228e0f372" id="r_ga889faf1ecb5ebaf770074f4228e0f372"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga889faf1ecb5ebaf770074f4228e0f372">SDIO_STA_DTIMEOUT_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga889faf1ecb5ebaf770074f4228e0f372"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9c4e52bb9c5041bd2be2eb216dd9e7c" id="r_gab9c4e52bb9c5041bd2be2eb216dd9e7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9c4e52bb9c5041bd2be2eb216dd9e7c">SDIO_STA_DTIMEOUT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga889faf1ecb5ebaf770074f4228e0f372">SDIO_STA_DTIMEOUT_Pos</a>)</td></tr>
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<tr class="memitem:ga8a2cad7ef3406a46ddba51f7ab5df94b" id="r_ga8a2cad7ef3406a46ddba51f7ab5df94b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a2cad7ef3406a46ddba51f7ab5df94b">SDIO_STA_DTIMEOUT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9c4e52bb9c5041bd2be2eb216dd9e7c">SDIO_STA_DTIMEOUT_Msk</a></td></tr>
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<tr class="separator:ga8a2cad7ef3406a46ddba51f7ab5df94b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c4f937a15d62a7e9a6d761104aab35e" id="r_ga3c4f937a15d62a7e9a6d761104aab35e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c4f937a15d62a7e9a6d761104aab35e">SDIO_STA_TXUNDERR_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga3c4f937a15d62a7e9a6d761104aab35e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac651b75734596780cc225b1c1688741d" id="r_gac651b75734596780cc225b1c1688741d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac651b75734596780cc225b1c1688741d">SDIO_STA_TXUNDERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c4f937a15d62a7e9a6d761104aab35e">SDIO_STA_TXUNDERR_Pos</a>)</td></tr>
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<tr class="separator:gac651b75734596780cc225b1c1688741d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b9dcdb8b90d8266eb0c5a2be81238aa" id="r_ga4b9dcdb8b90d8266eb0c5a2be81238aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b9dcdb8b90d8266eb0c5a2be81238aa">SDIO_STA_TXUNDERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac651b75734596780cc225b1c1688741d">SDIO_STA_TXUNDERR_Msk</a></td></tr>
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<tr class="separator:ga4b9dcdb8b90d8266eb0c5a2be81238aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae72faf7690680a4a9fbeb3da74699d0d" id="r_gae72faf7690680a4a9fbeb3da74699d0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae72faf7690680a4a9fbeb3da74699d0d">SDIO_STA_RXOVERR_Pos</a>   (5U)</td></tr>
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<tr class="separator:gae72faf7690680a4a9fbeb3da74699d0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cd1da9061309343205c1421250ec2ac" id="r_ga8cd1da9061309343205c1421250ec2ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cd1da9061309343205c1421250ec2ac">SDIO_STA_RXOVERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae72faf7690680a4a9fbeb3da74699d0d">SDIO_STA_RXOVERR_Pos</a>)</td></tr>
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<tr class="separator:ga8cd1da9061309343205c1421250ec2ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4b91289c9f6b773f928706ae8a5ddfc" id="r_gad4b91289c9f6b773f928706ae8a5ddfc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4b91289c9f6b773f928706ae8a5ddfc">SDIO_STA_RXOVERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8cd1da9061309343205c1421250ec2ac">SDIO_STA_RXOVERR_Msk</a></td></tr>
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<tr class="separator:gad4b91289c9f6b773f928706ae8a5ddfc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa10e00ee0c79b38dd2aa074d4d7d604" id="r_gafa10e00ee0c79b38dd2aa074d4d7d604"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa10e00ee0c79b38dd2aa074d4d7d604">SDIO_STA_CMDREND_Pos</a>   (6U)</td></tr>
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<tr class="separator:gafa10e00ee0c79b38dd2aa074d4d7d604"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ab895524d8a5cbf1b1104abcdf013fe" id="r_ga3ab895524d8a5cbf1b1104abcdf013fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ab895524d8a5cbf1b1104abcdf013fe">SDIO_STA_CMDREND_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafa10e00ee0c79b38dd2aa074d4d7d604">SDIO_STA_CMDREND_Pos</a>)</td></tr>
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<tr class="separator:ga3ab895524d8a5cbf1b1104abcdf013fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga096f11117736a2252f1cd5c4cccdc6e6" id="r_ga096f11117736a2252f1cd5c4cccdc6e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga096f11117736a2252f1cd5c4cccdc6e6">SDIO_STA_CMDREND</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ab895524d8a5cbf1b1104abcdf013fe">SDIO_STA_CMDREND_Msk</a></td></tr>
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<tr class="separator:ga096f11117736a2252f1cd5c4cccdc6e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeec49be725a39b21c24769feb4f43b89" id="r_gaeec49be725a39b21c24769feb4f43b89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeec49be725a39b21c24769feb4f43b89">SDIO_STA_CMDSENT_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaeec49be725a39b21c24769feb4f43b89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ff987cbe6f2afc731016591f7dca4f7" id="r_ga7ff987cbe6f2afc731016591f7dca4f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ff987cbe6f2afc731016591f7dca4f7">SDIO_STA_CMDSENT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec49be725a39b21c24769feb4f43b89">SDIO_STA_CMDSENT_Pos</a>)</td></tr>
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<tr class="separator:ga7ff987cbe6f2afc731016591f7dca4f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa550641dc6aa942e1b524ad0e557a284" id="r_gaa550641dc6aa942e1b524ad0e557a284"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa550641dc6aa942e1b524ad0e557a284">SDIO_STA_CMDSENT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ff987cbe6f2afc731016591f7dca4f7">SDIO_STA_CMDSENT_Msk</a></td></tr>
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<tr class="separator:gaa550641dc6aa942e1b524ad0e557a284"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaaa45c46418b926d742e8c557eca124d" id="r_gaaaa45c46418b926d742e8c557eca124d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaaa45c46418b926d742e8c557eca124d">SDIO_STA_DATAEND_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaaaa45c46418b926d742e8c557eca124d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39ffad41e1ac6eb225eb1f06f320a9c2" id="r_ga39ffad41e1ac6eb225eb1f06f320a9c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39ffad41e1ac6eb225eb1f06f320a9c2">SDIO_STA_DATAEND_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaaa45c46418b926d742e8c557eca124d">SDIO_STA_DATAEND_Pos</a>)</td></tr>
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<tr class="separator:ga39ffad41e1ac6eb225eb1f06f320a9c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe7e354a903b957943cf5b6bed4cdf6b" id="r_gafe7e354a903b957943cf5b6bed4cdf6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe7e354a903b957943cf5b6bed4cdf6b">SDIO_STA_DATAEND</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga39ffad41e1ac6eb225eb1f06f320a9c2">SDIO_STA_DATAEND_Msk</a></td></tr>
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<tr class="separator:gafe7e354a903b957943cf5b6bed4cdf6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2d7138c3bcb7ccf0d90c93daac3a43a" id="r_gac2d7138c3bcb7ccf0d90c93daac3a43a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2d7138c3bcb7ccf0d90c93daac3a43a">SDIO_STA_STBITERR_Pos</a>   (9U)</td></tr>
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<tr class="separator:gac2d7138c3bcb7ccf0d90c93daac3a43a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c826404242f6e6ff56c3b6b3e42863a" id="r_ga0c826404242f6e6ff56c3b6b3e42863a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c826404242f6e6ff56c3b6b3e42863a">SDIO_STA_STBITERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2d7138c3bcb7ccf0d90c93daac3a43a">SDIO_STA_STBITERR_Pos</a>)</td></tr>
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<tr class="separator:ga0c826404242f6e6ff56c3b6b3e42863a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a9ef8e72604e9997da23601a2dd84a4" id="r_ga7a9ef8e72604e9997da23601a2dd84a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a9ef8e72604e9997da23601a2dd84a4">SDIO_STA_STBITERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c826404242f6e6ff56c3b6b3e42863a">SDIO_STA_STBITERR_Msk</a></td></tr>
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<tr class="separator:ga7a9ef8e72604e9997da23601a2dd84a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56b7b1a0c443227a070222af9cd212f5" id="r_ga56b7b1a0c443227a070222af9cd212f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56b7b1a0c443227a070222af9cd212f5">SDIO_STA_DBCKEND_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga56b7b1a0c443227a070222af9cd212f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9c1646ceeca1e8e93ca1f4bbb2fd12f" id="r_gac9c1646ceeca1e8e93ca1f4bbb2fd12f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9c1646ceeca1e8e93ca1f4bbb2fd12f">SDIO_STA_DBCKEND_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga56b7b1a0c443227a070222af9cd212f5">SDIO_STA_DBCKEND_Pos</a>)</td></tr>
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<tr class="separator:gac9c1646ceeca1e8e93ca1f4bbb2fd12f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2fabf2c02cba6d4de1e90d8d1dc9793c" id="r_ga2fabf2c02cba6d4de1e90d8d1dc9793c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fabf2c02cba6d4de1e90d8d1dc9793c">SDIO_STA_DBCKEND</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9c1646ceeca1e8e93ca1f4bbb2fd12f">SDIO_STA_DBCKEND_Msk</a></td></tr>
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<tr class="separator:ga2fabf2c02cba6d4de1e90d8d1dc9793c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2390484299f14b720b5f5e3fa5811538" id="r_ga2390484299f14b720b5f5e3fa5811538"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2390484299f14b720b5f5e3fa5811538">SDIO_STA_CMDACT_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga2390484299f14b720b5f5e3fa5811538"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9c9c8a3be5f8615d36927da8c7152c2" id="r_gaa9c9c8a3be5f8615d36927da8c7152c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9c9c8a3be5f8615d36927da8c7152c2">SDIO_STA_CMDACT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2390484299f14b720b5f5e3fa5811538">SDIO_STA_CMDACT_Pos</a>)</td></tr>
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<tr class="separator:gaa9c9c8a3be5f8615d36927da8c7152c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99ccdac7a223635ee5b38a4bae8f30cc" id="r_ga99ccdac7a223635ee5b38a4bae8f30cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99ccdac7a223635ee5b38a4bae8f30cc">SDIO_STA_CMDACT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9c9c8a3be5f8615d36927da8c7152c2">SDIO_STA_CMDACT_Msk</a></td></tr>
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<tr class="separator:ga99ccdac7a223635ee5b38a4bae8f30cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47ef38c70701b9ca0d77927071bfdd10" id="r_ga47ef38c70701b9ca0d77927071bfdd10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47ef38c70701b9ca0d77927071bfdd10">SDIO_STA_TXACT_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga47ef38c70701b9ca0d77927071bfdd10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8013f5e0b7c82bd29351e0428af7240f" id="r_ga8013f5e0b7c82bd29351e0428af7240f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8013f5e0b7c82bd29351e0428af7240f">SDIO_STA_TXACT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga47ef38c70701b9ca0d77927071bfdd10">SDIO_STA_TXACT_Pos</a>)</td></tr>
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<tr class="separator:ga8013f5e0b7c82bd29351e0428af7240f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga908feb4957f48390bc2fc0bde47ac784" id="r_ga908feb4957f48390bc2fc0bde47ac784"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga908feb4957f48390bc2fc0bde47ac784">SDIO_STA_TXACT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8013f5e0b7c82bd29351e0428af7240f">SDIO_STA_TXACT_Msk</a></td></tr>
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<tr class="separator:ga908feb4957f48390bc2fc0bde47ac784"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a48d2dd6535975e9d584964067f41a6" id="r_ga3a48d2dd6535975e9d584964067f41a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a48d2dd6535975e9d584964067f41a6">SDIO_STA_RXACT_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga3a48d2dd6535975e9d584964067f41a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6804febb98fae68a60c58b4c1e0935e3" id="r_ga6804febb98fae68a60c58b4c1e0935e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6804febb98fae68a60c58b4c1e0935e3">SDIO_STA_RXACT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a48d2dd6535975e9d584964067f41a6">SDIO_STA_RXACT_Pos</a>)</td></tr>
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<tr class="separator:ga6804febb98fae68a60c58b4c1e0935e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad2f52b50765fa449dcfabc39b099796" id="r_gaad2f52b50765fa449dcfabc39b099796"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad2f52b50765fa449dcfabc39b099796">SDIO_STA_RXACT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6804febb98fae68a60c58b4c1e0935e3">SDIO_STA_RXACT_Msk</a></td></tr>
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<tr class="separator:gaad2f52b50765fa449dcfabc39b099796"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3a623bdff29b95c5a45c523a90fe12e" id="r_gaf3a623bdff29b95c5a45c523a90fe12e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3a623bdff29b95c5a45c523a90fe12e">SDIO_STA_TXFIFOHE_Pos</a>   (14U)</td></tr>
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<tr class="separator:gaf3a623bdff29b95c5a45c523a90fe12e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41135726ff869b6aa9a2f0ed1383ea53" id="r_ga41135726ff869b6aa9a2f0ed1383ea53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41135726ff869b6aa9a2f0ed1383ea53">SDIO_STA_TXFIFOHE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3a623bdff29b95c5a45c523a90fe12e">SDIO_STA_TXFIFOHE_Pos</a>)</td></tr>
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<tr class="separator:ga41135726ff869b6aa9a2f0ed1383ea53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62b9e38be5956dde69049154facc62fd" id="r_ga62b9e38be5956dde69049154facc62fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62b9e38be5956dde69049154facc62fd">SDIO_STA_TXFIFOHE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga41135726ff869b6aa9a2f0ed1383ea53">SDIO_STA_TXFIFOHE_Msk</a></td></tr>
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<tr class="separator:ga62b9e38be5956dde69049154facc62fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f8b161fe0ebbd71a38e85c8caa3a466" id="r_ga7f8b161fe0ebbd71a38e85c8caa3a466"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f8b161fe0ebbd71a38e85c8caa3a466">SDIO_STA_RXFIFOHF_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga7f8b161fe0ebbd71a38e85c8caa3a466"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a590a016f50e757d6eb58248f9af026" id="r_ga0a590a016f50e757d6eb58248f9af026"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a590a016f50e757d6eb58248f9af026">SDIO_STA_RXFIFOHF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f8b161fe0ebbd71a38e85c8caa3a466">SDIO_STA_RXFIFOHF_Pos</a>)</td></tr>
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<tr class="separator:ga0a590a016f50e757d6eb58248f9af026"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7916c47ee972376a0eaee584133ca36d" id="r_ga7916c47ee972376a0eaee584133ca36d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7916c47ee972376a0eaee584133ca36d">SDIO_STA_RXFIFOHF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a590a016f50e757d6eb58248f9af026">SDIO_STA_RXFIFOHF_Msk</a></td></tr>
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<tr class="separator:ga7916c47ee972376a0eaee584133ca36d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga634b30add702067001f17455bc691740" id="r_ga634b30add702067001f17455bc691740"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga634b30add702067001f17455bc691740">SDIO_STA_TXFIFOF_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga634b30add702067001f17455bc691740"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9d17bbac6dd7388ed367c5ccfa5be1c" id="r_gab9d17bbac6dd7388ed367c5ccfa5be1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9d17bbac6dd7388ed367c5ccfa5be1c">SDIO_STA_TXFIFOF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga634b30add702067001f17455bc691740">SDIO_STA_TXFIFOF_Pos</a>)</td></tr>
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<tr class="separator:gab9d17bbac6dd7388ed367c5ccfa5be1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1497b46f9a906001dabb7d7604f6c05" id="r_gae1497b46f9a906001dabb7d7604f6c05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1497b46f9a906001dabb7d7604f6c05">SDIO_STA_TXFIFOF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab9d17bbac6dd7388ed367c5ccfa5be1c">SDIO_STA_TXFIFOF_Msk</a></td></tr>
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<tr class="separator:gae1497b46f9a906001dabb7d7604f6c05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86b297852e15be2ce6b2c08b7432f868" id="r_ga86b297852e15be2ce6b2c08b7432f868"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86b297852e15be2ce6b2c08b7432f868">SDIO_STA_RXFIFOF_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga86b297852e15be2ce6b2c08b7432f868"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7af9ed233f8115b8d3123bb274d197ec" id="r_ga7af9ed233f8115b8d3123bb274d197ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7af9ed233f8115b8d3123bb274d197ec">SDIO_STA_RXFIFOF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga86b297852e15be2ce6b2c08b7432f868">SDIO_STA_RXFIFOF_Pos</a>)</td></tr>
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<tr class="separator:ga7af9ed233f8115b8d3123bb274d197ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85f46f873ca5fe91a1e8206d157b9446" id="r_ga85f46f873ca5fe91a1e8206d157b9446"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85f46f873ca5fe91a1e8206d157b9446">SDIO_STA_RXFIFOF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7af9ed233f8115b8d3123bb274d197ec">SDIO_STA_RXFIFOF_Msk</a></td></tr>
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<tr class="separator:ga85f46f873ca5fe91a1e8206d157b9446"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08db94989b17f7ad2e47a029afc89ae2" id="r_ga08db94989b17f7ad2e47a029afc89ae2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08db94989b17f7ad2e47a029afc89ae2">SDIO_STA_TXFIFOE_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga08db94989b17f7ad2e47a029afc89ae2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadae851570f79529e3027cd6ae80b9a19" id="r_gadae851570f79529e3027cd6ae80b9a19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadae851570f79529e3027cd6ae80b9a19">SDIO_STA_TXFIFOE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga08db94989b17f7ad2e47a029afc89ae2">SDIO_STA_TXFIFOE_Pos</a>)</td></tr>
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<tr class="separator:gadae851570f79529e3027cd6ae80b9a19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4624f95c5224c631f99571b5454acd86" id="r_ga4624f95c5224c631f99571b5454acd86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4624f95c5224c631f99571b5454acd86">SDIO_STA_TXFIFOE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadae851570f79529e3027cd6ae80b9a19">SDIO_STA_TXFIFOE_Msk</a></td></tr>
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<tr class="separator:ga4624f95c5224c631f99571b5454acd86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa66efed771cee7e43274a73357e77036" id="r_gaa66efed771cee7e43274a73357e77036"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa66efed771cee7e43274a73357e77036">SDIO_STA_RXFIFOE_Pos</a>   (19U)</td></tr>
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<tr class="separator:gaa66efed771cee7e43274a73357e77036"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad68af59ab8a514fc2ec9735db58bc4bf" id="r_gad68af59ab8a514fc2ec9735db58bc4bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad68af59ab8a514fc2ec9735db58bc4bf">SDIO_STA_RXFIFOE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa66efed771cee7e43274a73357e77036">SDIO_STA_RXFIFOE_Pos</a>)</td></tr>
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<tr class="separator:gad68af59ab8a514fc2ec9735db58bc4bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44bf9f7321d65a3effd2df469a58a464" id="r_ga44bf9f7321d65a3effd2df469a58a464"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44bf9f7321d65a3effd2df469a58a464">SDIO_STA_RXFIFOE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad68af59ab8a514fc2ec9735db58bc4bf">SDIO_STA_RXFIFOE_Msk</a></td></tr>
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<tr class="separator:ga44bf9f7321d65a3effd2df469a58a464"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae685d8223202af5aaf85779c9b9c33ce" id="r_gae685d8223202af5aaf85779c9b9c33ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae685d8223202af5aaf85779c9b9c33ce">SDIO_STA_TXDAVL_Pos</a>   (20U)</td></tr>
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<tr class="separator:gae685d8223202af5aaf85779c9b9c33ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ce2c8660375bdf8f10e49af1966f64f" id="r_ga5ce2c8660375bdf8f10e49af1966f64f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ce2c8660375bdf8f10e49af1966f64f">SDIO_STA_TXDAVL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae685d8223202af5aaf85779c9b9c33ce">SDIO_STA_TXDAVL_Pos</a>)</td></tr>
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<tr class="separator:ga5ce2c8660375bdf8f10e49af1966f64f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19b374518e813f7a1ac4aec3b24b7517" id="r_ga19b374518e813f7a1ac4aec3b24b7517"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19b374518e813f7a1ac4aec3b24b7517">SDIO_STA_TXDAVL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ce2c8660375bdf8f10e49af1966f64f">SDIO_STA_TXDAVL_Msk</a></td></tr>
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<tr class="separator:ga19b374518e813f7a1ac4aec3b24b7517"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5eff3fcfe1a6b51137bb2faa735ede8d" id="r_ga5eff3fcfe1a6b51137bb2faa735ede8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5eff3fcfe1a6b51137bb2faa735ede8d">SDIO_STA_RXDAVL_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga5eff3fcfe1a6b51137bb2faa735ede8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3c400c578bed5233c91c6e9570a651d" id="r_gaf3c400c578bed5233c91c6e9570a651d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3c400c578bed5233c91c6e9570a651d">SDIO_STA_RXDAVL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5eff3fcfe1a6b51137bb2faa735ede8d">SDIO_STA_RXDAVL_Pos</a>)</td></tr>
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<tr class="separator:gaf3c400c578bed5233c91c6e9570a651d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcad9b8c0e3ccba1aa389d7713db6803" id="r_gadcad9b8c0e3ccba1aa389d7713db6803"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcad9b8c0e3ccba1aa389d7713db6803">SDIO_STA_RXDAVL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3c400c578bed5233c91c6e9570a651d">SDIO_STA_RXDAVL_Msk</a></td></tr>
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<tr class="separator:gadcad9b8c0e3ccba1aa389d7713db6803"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1d1c55503940b44780c405d6e6f7581" id="r_gac1d1c55503940b44780c405d6e6f7581"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1d1c55503940b44780c405d6e6f7581">SDIO_STA_SDIOIT_Pos</a>   (22U)</td></tr>
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<tr class="separator:gac1d1c55503940b44780c405d6e6f7581"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae20bfd0933cc814ac479a82f720ab423" id="r_gae20bfd0933cc814ac479a82f720ab423"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae20bfd0933cc814ac479a82f720ab423">SDIO_STA_SDIOIT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac1d1c55503940b44780c405d6e6f7581">SDIO_STA_SDIOIT_Pos</a>)</td></tr>
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<tr class="separator:gae20bfd0933cc814ac479a82f720ab423"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5df3c10c37285faedb2d853aea4e63dc" id="r_ga5df3c10c37285faedb2d853aea4e63dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5df3c10c37285faedb2d853aea4e63dc">SDIO_STA_SDIOIT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae20bfd0933cc814ac479a82f720ab423">SDIO_STA_SDIOIT_Msk</a></td></tr>
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<tr class="separator:ga5df3c10c37285faedb2d853aea4e63dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66310759b05b535f231c7750a2cba57e" id="r_ga66310759b05b535f231c7750a2cba57e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66310759b05b535f231c7750a2cba57e">SDIO_STA_CEATAEND_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga66310759b05b535f231c7750a2cba57e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa51fdc310e3b16750da76a9d850278a3" id="r_gaa51fdc310e3b16750da76a9d850278a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa51fdc310e3b16750da76a9d850278a3">SDIO_STA_CEATAEND_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga66310759b05b535f231c7750a2cba57e">SDIO_STA_CEATAEND_Pos</a>)</td></tr>
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<tr class="separator:gaa51fdc310e3b16750da76a9d850278a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d8ef3b4157374fd2b5fc8ed12b77a0c" id="r_ga5d8ef3b4157374fd2b5fc8ed12b77a0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d8ef3b4157374fd2b5fc8ed12b77a0c">SDIO_STA_CEATAEND</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa51fdc310e3b16750da76a9d850278a3">SDIO_STA_CEATAEND_Msk</a></td></tr>
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<tr class="separator:ga5d8ef3b4157374fd2b5fc8ed12b77a0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab10c6948f7bdd82257df5c11a367162c" id="r_gab10c6948f7bdd82257df5c11a367162c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab10c6948f7bdd82257df5c11a367162c">SDIO_ICR_CCRCFAILC_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab10c6948f7bdd82257df5c11a367162c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9217341f3df0a8ff9f874c86a12ce2b" id="r_gac9217341f3df0a8ff9f874c86a12ce2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9217341f3df0a8ff9f874c86a12ce2b">SDIO_ICR_CCRCFAILC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab10c6948f7bdd82257df5c11a367162c">SDIO_ICR_CCRCFAILC_Pos</a>)</td></tr>
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<tr class="separator:gac9217341f3df0a8ff9f874c86a12ce2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44708c45f675cf065f1c7fc9311d6e43" id="r_ga44708c45f675cf065f1c7fc9311d6e43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44708c45f675cf065f1c7fc9311d6e43">SDIO_ICR_CCRCFAILC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9217341f3df0a8ff9f874c86a12ce2b">SDIO_ICR_CCRCFAILC_Msk</a></td></tr>
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<tr class="separator:ga44708c45f675cf065f1c7fc9311d6e43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b4ddca0c23778a5863dceeb2bbfbeb2" id="r_ga4b4ddca0c23778a5863dceeb2bbfbeb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b4ddca0c23778a5863dceeb2bbfbeb2">SDIO_ICR_DCRCFAILC_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga4b4ddca0c23778a5863dceeb2bbfbeb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1da8c0983fb1afa1403cbb59e453ad8" id="r_gab1da8c0983fb1afa1403cbb59e453ad8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1da8c0983fb1afa1403cbb59e453ad8">SDIO_ICR_DCRCFAILC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b4ddca0c23778a5863dceeb2bbfbeb2">SDIO_ICR_DCRCFAILC_Pos</a>)</td></tr>
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<tr class="separator:gab1da8c0983fb1afa1403cbb59e453ad8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cb6cde5f88a5d2b635a830dd401c4e0" id="r_ga2cb6cde5f88a5d2b635a830dd401c4e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cb6cde5f88a5d2b635a830dd401c4e0">SDIO_ICR_DCRCFAILC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab1da8c0983fb1afa1403cbb59e453ad8">SDIO_ICR_DCRCFAILC_Msk</a></td></tr>
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<tr class="separator:ga2cb6cde5f88a5d2b635a830dd401c4e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96cc705eed0b33038e018d6b72096de3" id="r_ga96cc705eed0b33038e018d6b72096de3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96cc705eed0b33038e018d6b72096de3">SDIO_ICR_CTIMEOUTC_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga5e808d2c69f391700674c1a5e438b453" id="r_ga5e808d2c69f391700674c1a5e438b453"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e808d2c69f391700674c1a5e438b453">SDIO_ICR_CTIMEOUTC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96cc705eed0b33038e018d6b72096de3">SDIO_ICR_CTIMEOUTC_Pos</a>)</td></tr>
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<tr class="separator:ga5e808d2c69f391700674c1a5e438b453"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4d128bee8a97ae9971d42f844d2e297" id="r_gac4d128bee8a97ae9971d42f844d2e297"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4d128bee8a97ae9971d42f844d2e297">SDIO_ICR_CTIMEOUTC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5e808d2c69f391700674c1a5e438b453">SDIO_ICR_CTIMEOUTC_Msk</a></td></tr>
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<tr class="separator:gac4d128bee8a97ae9971d42f844d2e297"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada71c35f6df85b0c2193cf39745308fd" id="r_gada71c35f6df85b0c2193cf39745308fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada71c35f6df85b0c2193cf39745308fd">SDIO_ICR_DTIMEOUTC_Pos</a>   (3U)</td></tr>
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<tr class="memitem:ga8ca4ee048763e8a5a9205b8e3238ac2d" id="r_ga8ca4ee048763e8a5a9205b8e3238ac2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ca4ee048763e8a5a9205b8e3238ac2d">SDIO_ICR_DTIMEOUTC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada71c35f6df85b0c2193cf39745308fd">SDIO_ICR_DTIMEOUTC_Pos</a>)</td></tr>
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<tr class="separator:ga8ca4ee048763e8a5a9205b8e3238ac2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcb64d3d07a5841ee9f18ff6bc75350b" id="r_gadcb64d3d07a5841ee9f18ff6bc75350b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcb64d3d07a5841ee9f18ff6bc75350b">SDIO_ICR_DTIMEOUTC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ca4ee048763e8a5a9205b8e3238ac2d">SDIO_ICR_DTIMEOUTC_Msk</a></td></tr>
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<tr class="separator:gadcb64d3d07a5841ee9f18ff6bc75350b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga991a111fad2d762541ba63c49ac2a8b8" id="r_ga991a111fad2d762541ba63c49ac2a8b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga991a111fad2d762541ba63c49ac2a8b8">SDIO_ICR_TXUNDERRC_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga991a111fad2d762541ba63c49ac2a8b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54a396bca8fa34f0e4d8387b814b9832" id="r_ga54a396bca8fa34f0e4d8387b814b9832"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54a396bca8fa34f0e4d8387b814b9832">SDIO_ICR_TXUNDERRC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga991a111fad2d762541ba63c49ac2a8b8">SDIO_ICR_TXUNDERRC_Pos</a>)</td></tr>
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<tr class="separator:ga54a396bca8fa34f0e4d8387b814b9832"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9628d77973f35d628924172831b029f8" id="r_ga9628d77973f35d628924172831b029f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9628d77973f35d628924172831b029f8">SDIO_ICR_TXUNDERRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga54a396bca8fa34f0e4d8387b814b9832">SDIO_ICR_TXUNDERRC_Msk</a></td></tr>
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<tr class="separator:ga9628d77973f35d628924172831b029f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8ed5c5350b9bc9edb9043d7cc0feda3" id="r_gae8ed5c5350b9bc9edb9043d7cc0feda3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8ed5c5350b9bc9edb9043d7cc0feda3">SDIO_ICR_RXOVERRC_Pos</a>   (5U)</td></tr>
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<tr class="separator:gae8ed5c5350b9bc9edb9043d7cc0feda3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafab6dbc8ca0e4e78139131e59683aad7" id="r_gafab6dbc8ca0e4e78139131e59683aad7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafab6dbc8ca0e4e78139131e59683aad7">SDIO_ICR_RXOVERRC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae8ed5c5350b9bc9edb9043d7cc0feda3">SDIO_ICR_RXOVERRC_Pos</a>)</td></tr>
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<tr class="separator:gafab6dbc8ca0e4e78139131e59683aad7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2513d040c7695b152b0b423ad6f5c81e" id="r_ga2513d040c7695b152b0b423ad6f5c81e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2513d040c7695b152b0b423ad6f5c81e">SDIO_ICR_RXOVERRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafab6dbc8ca0e4e78139131e59683aad7">SDIO_ICR_RXOVERRC_Msk</a></td></tr>
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<tr class="separator:ga2513d040c7695b152b0b423ad6f5c81e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24e00e57f1e28f8983ec21d94adbcdd7" id="r_ga24e00e57f1e28f8983ec21d94adbcdd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24e00e57f1e28f8983ec21d94adbcdd7">SDIO_ICR_CMDRENDC_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga24e00e57f1e28f8983ec21d94adbcdd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga338691a5f364aa9d5c2e31741bf5e520" id="r_ga338691a5f364aa9d5c2e31741bf5e520"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga338691a5f364aa9d5c2e31741bf5e520">SDIO_ICR_CMDRENDC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24e00e57f1e28f8983ec21d94adbcdd7">SDIO_ICR_CMDRENDC_Pos</a>)</td></tr>
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<tr class="separator:ga338691a5f364aa9d5c2e31741bf5e520"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fb5c67aef48d5ee27b60107d938a58f" id="r_ga8fb5c67aef48d5ee27b60107d938a58f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fb5c67aef48d5ee27b60107d938a58f">SDIO_ICR_CMDRENDC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga338691a5f364aa9d5c2e31741bf5e520">SDIO_ICR_CMDRENDC_Msk</a></td></tr>
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<tr class="separator:ga8fb5c67aef48d5ee27b60107d938a58f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbd31121662a8f43e9d1e93f7809a78c" id="r_gadbd31121662a8f43e9d1e93f7809a78c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbd31121662a8f43e9d1e93f7809a78c">SDIO_ICR_CMDSENTC_Pos</a>   (7U)</td></tr>
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<tr class="separator:gadbd31121662a8f43e9d1e93f7809a78c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f77128e853dcdb4202ef930d242cc80" id="r_ga5f77128e853dcdb4202ef930d242cc80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f77128e853dcdb4202ef930d242cc80">SDIO_ICR_CMDSENTC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadbd31121662a8f43e9d1e93f7809a78c">SDIO_ICR_CMDSENTC_Pos</a>)</td></tr>
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<tr class="separator:ga5f77128e853dcdb4202ef930d242cc80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa27fe45ef7461caf704186630b26a196" id="r_gaa27fe45ef7461caf704186630b26a196"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa27fe45ef7461caf704186630b26a196">SDIO_ICR_CMDSENTC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f77128e853dcdb4202ef930d242cc80">SDIO_ICR_CMDSENTC_Msk</a></td></tr>
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<tr class="separator:gaa27fe45ef7461caf704186630b26a196"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8762bbd49f834e5cda527dada339a4ca" id="r_ga8762bbd49f834e5cda527dada339a4ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8762bbd49f834e5cda527dada339a4ca">SDIO_ICR_DATAENDC_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga8762bbd49f834e5cda527dada339a4ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f3222f8b80e53b265fca0c903baaf3f" id="r_ga7f3222f8b80e53b265fca0c903baaf3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f3222f8b80e53b265fca0c903baaf3f">SDIO_ICR_DATAENDC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8762bbd49f834e5cda527dada339a4ca">SDIO_ICR_DATAENDC_Pos</a>)</td></tr>
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<tr class="separator:ga7f3222f8b80e53b265fca0c903baaf3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga527e1f9cd295845d5be9975cf26bae7e" id="r_ga527e1f9cd295845d5be9975cf26bae7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga527e1f9cd295845d5be9975cf26bae7e">SDIO_ICR_DATAENDC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f3222f8b80e53b265fca0c903baaf3f">SDIO_ICR_DATAENDC_Msk</a></td></tr>
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<tr class="separator:ga527e1f9cd295845d5be9975cf26bae7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga374e5a92d4f2de580f73d098bba0dc52" id="r_ga374e5a92d4f2de580f73d098bba0dc52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga374e5a92d4f2de580f73d098bba0dc52">SDIO_ICR_STBITERRC_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga374e5a92d4f2de580f73d098bba0dc52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccd50f6a808007427eec1f2c823e78c5" id="r_gaccd50f6a808007427eec1f2c823e78c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccd50f6a808007427eec1f2c823e78c5">SDIO_ICR_STBITERRC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga374e5a92d4f2de580f73d098bba0dc52">SDIO_ICR_STBITERRC_Pos</a>)</td></tr>
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<tr class="separator:gaccd50f6a808007427eec1f2c823e78c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae614b5ab8a8aecbc3c1ce74645cdc28c" id="r_gae614b5ab8a8aecbc3c1ce74645cdc28c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae614b5ab8a8aecbc3c1ce74645cdc28c">SDIO_ICR_STBITERRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaccd50f6a808007427eec1f2c823e78c5">SDIO_ICR_STBITERRC_Msk</a></td></tr>
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<tr class="separator:gae614b5ab8a8aecbc3c1ce74645cdc28c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a5675867470f147be32bd684344d6c5" id="r_ga5a5675867470f147be32bd684344d6c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a5675867470f147be32bd684344d6c5">SDIO_ICR_DBCKENDC_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga5a5675867470f147be32bd684344d6c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79f2c2204f0e3ea155189811ce855802" id="r_ga79f2c2204f0e3ea155189811ce855802"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79f2c2204f0e3ea155189811ce855802">SDIO_ICR_DBCKENDC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a5675867470f147be32bd684344d6c5">SDIO_ICR_DBCKENDC_Pos</a>)</td></tr>
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<tr class="separator:ga79f2c2204f0e3ea155189811ce855802"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc5518c07e39dc1f91603737d1a7180b" id="r_gadc5518c07e39dc1f91603737d1a7180b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc5518c07e39dc1f91603737d1a7180b">SDIO_ICR_DBCKENDC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga79f2c2204f0e3ea155189811ce855802">SDIO_ICR_DBCKENDC_Msk</a></td></tr>
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<tr class="separator:gadc5518c07e39dc1f91603737d1a7180b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f237d6521d4dcdcb4bdb5049b4d8c16" id="r_ga2f237d6521d4dcdcb4bdb5049b4d8c16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f237d6521d4dcdcb4bdb5049b4d8c16">SDIO_ICR_SDIOITC_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga2f237d6521d4dcdcb4bdb5049b4d8c16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6439a7e034a5af888f93c0e393119573" id="r_ga6439a7e034a5af888f93c0e393119573"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6439a7e034a5af888f93c0e393119573">SDIO_ICR_SDIOITC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f237d6521d4dcdcb4bdb5049b4d8c16">SDIO_ICR_SDIOITC_Pos</a>)</td></tr>
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<tr class="separator:ga6439a7e034a5af888f93c0e393119573"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2990db729fb017dfd659dc6cf8823761" id="r_ga2990db729fb017dfd659dc6cf8823761"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2990db729fb017dfd659dc6cf8823761">SDIO_ICR_SDIOITC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6439a7e034a5af888f93c0e393119573">SDIO_ICR_SDIOITC_Msk</a></td></tr>
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<tr class="memitem:ga3cb5a4fcac3d143b45a4a0092c3f3664" id="r_ga3cb5a4fcac3d143b45a4a0092c3f3664"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cb5a4fcac3d143b45a4a0092c3f3664">SDIO_ICR_CEATAENDC_Pos</a>   (23U)</td></tr>
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<tr class="memitem:ga51b6347d4f3229d35547e5ce5a27f481" id="r_ga51b6347d4f3229d35547e5ce5a27f481"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51b6347d4f3229d35547e5ce5a27f481">SDIO_ICR_CEATAENDC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cb5a4fcac3d143b45a4a0092c3f3664">SDIO_ICR_CEATAENDC_Pos</a>)</td></tr>
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<tr class="separator:ga51b6347d4f3229d35547e5ce5a27f481"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f1cebd40fd1eafb59635b284c5a3f34" id="r_ga6f1cebd40fd1eafb59635b284c5a3f34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f1cebd40fd1eafb59635b284c5a3f34">SDIO_ICR_CEATAENDC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga51b6347d4f3229d35547e5ce5a27f481">SDIO_ICR_CEATAENDC_Msk</a></td></tr>
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<tr class="separator:ga6f1cebd40fd1eafb59635b284c5a3f34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd6b95c5dfb466ba4fe1d6ba24a69167" id="r_gafd6b95c5dfb466ba4fe1d6ba24a69167"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd6b95c5dfb466ba4fe1d6ba24a69167">SDIO_MASK_CCRCFAILIE_Pos</a>   (0U)</td></tr>
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<tr class="separator:gafd6b95c5dfb466ba4fe1d6ba24a69167"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac74c97fa260e2834d977ab7537bdd4ef" id="r_gac74c97fa260e2834d977ab7537bdd4ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac74c97fa260e2834d977ab7537bdd4ef">SDIO_MASK_CCRCFAILIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafd6b95c5dfb466ba4fe1d6ba24a69167">SDIO_MASK_CCRCFAILIE_Pos</a>)</td></tr>
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<tr class="memitem:ga5e24d12a6c9af91337cb391d3ba698f3" id="r_ga5e24d12a6c9af91337cb391d3ba698f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e24d12a6c9af91337cb391d3ba698f3">SDIO_MASK_CCRCFAILIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac74c97fa260e2834d977ab7537bdd4ef">SDIO_MASK_CCRCFAILIE_Msk</a></td></tr>
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<tr class="separator:ga5e24d12a6c9af91337cb391d3ba698f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3cc4b96a34db55f9e9862e615f8c243" id="r_gaa3cc4b96a34db55f9e9862e615f8c243"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3cc4b96a34db55f9e9862e615f8c243">SDIO_MASK_DCRCFAILIE_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaa3cc4b96a34db55f9e9862e615f8c243"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd0eb870977ae895b80ac57187a1d112" id="r_gafd0eb870977ae895b80ac57187a1d112"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd0eb870977ae895b80ac57187a1d112">SDIO_MASK_DCRCFAILIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3cc4b96a34db55f9e9862e615f8c243">SDIO_MASK_DCRCFAILIE_Pos</a>)</td></tr>
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<tr class="separator:gafd0eb870977ae895b80ac57187a1d112"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e2e106a1f7792f054c6cc1f60906a09" id="r_ga5e2e106a1f7792f054c6cc1f60906a09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e2e106a1f7792f054c6cc1f60906a09">SDIO_MASK_DCRCFAILIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafd0eb870977ae895b80ac57187a1d112">SDIO_MASK_DCRCFAILIE_Msk</a></td></tr>
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<tr class="separator:ga5e2e106a1f7792f054c6cc1f60906a09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6023176201d68b77f056f32e85d5e4fc" id="r_ga6023176201d68b77f056f32e85d5e4fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6023176201d68b77f056f32e85d5e4fc">SDIO_MASK_CTIMEOUTIE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga6023176201d68b77f056f32e85d5e4fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01b92fda0043d94bfef382fb74bf588b" id="r_ga01b92fda0043d94bfef382fb74bf588b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01b92fda0043d94bfef382fb74bf588b">SDIO_MASK_CTIMEOUTIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6023176201d68b77f056f32e85d5e4fc">SDIO_MASK_CTIMEOUTIE_Pos</a>)</td></tr>
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<tr class="memitem:ga23f5a8c06e289522af0a679b08bdb014" id="r_ga23f5a8c06e289522af0a679b08bdb014"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23f5a8c06e289522af0a679b08bdb014">SDIO_MASK_CTIMEOUTIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga01b92fda0043d94bfef382fb74bf588b">SDIO_MASK_CTIMEOUTIE_Msk</a></td></tr>
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<tr class="separator:ga23f5a8c06e289522af0a679b08bdb014"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ee212e4944c5dd21acb553da80e84a5" id="r_ga6ee212e4944c5dd21acb553da80e84a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ee212e4944c5dd21acb553da80e84a5">SDIO_MASK_DTIMEOUTIE_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga6ee212e4944c5dd21acb553da80e84a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc92448e7adf15a3410f4c0a4c760eeb" id="r_gafc92448e7adf15a3410f4c0a4c760eeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc92448e7adf15a3410f4c0a4c760eeb">SDIO_MASK_DTIMEOUTIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ee212e4944c5dd21acb553da80e84a5">SDIO_MASK_DTIMEOUTIE_Pos</a>)</td></tr>
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<tr class="separator:gafc92448e7adf15a3410f4c0a4c760eeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b4cc63338fe72abd76e5b399c47379b" id="r_ga7b4cc63338fe72abd76e5b399c47379b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b4cc63338fe72abd76e5b399c47379b">SDIO_MASK_DTIMEOUTIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafc92448e7adf15a3410f4c0a4c760eeb">SDIO_MASK_DTIMEOUTIE_Msk</a></td></tr>
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<tr class="separator:ga7b4cc63338fe72abd76e5b399c47379b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0289babaca7a9d6ae404e78709152f20" id="r_ga0289babaca7a9d6ae404e78709152f20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0289babaca7a9d6ae404e78709152f20">SDIO_MASK_TXUNDERRIE_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga0289babaca7a9d6ae404e78709152f20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga245c0ebe407cfe97f42c98563070a7ef" id="r_ga245c0ebe407cfe97f42c98563070a7ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga245c0ebe407cfe97f42c98563070a7ef">SDIO_MASK_TXUNDERRIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0289babaca7a9d6ae404e78709152f20">SDIO_MASK_TXUNDERRIE_Pos</a>)</td></tr>
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<tr class="separator:ga245c0ebe407cfe97f42c98563070a7ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e02e525dc6ca1bb294b174e7391753d" id="r_ga1e02e525dc6ca1bb294b174e7391753d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e02e525dc6ca1bb294b174e7391753d">SDIO_MASK_TXUNDERRIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga245c0ebe407cfe97f42c98563070a7ef">SDIO_MASK_TXUNDERRIE_Msk</a></td></tr>
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<tr class="separator:ga1e02e525dc6ca1bb294b174e7391753d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15463333aaa2b90d2339b6dc4bd4e3ea" id="r_ga15463333aaa2b90d2339b6dc4bd4e3ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15463333aaa2b90d2339b6dc4bd4e3ea">SDIO_MASK_RXOVERRIE_Pos</a>   (5U)</td></tr>
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<tr class="memitem:ga1a0b758cbc6aed0e4a7633e451b55303" id="r_ga1a0b758cbc6aed0e4a7633e451b55303"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a0b758cbc6aed0e4a7633e451b55303">SDIO_MASK_RXOVERRIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga15463333aaa2b90d2339b6dc4bd4e3ea">SDIO_MASK_RXOVERRIE_Pos</a>)</td></tr>
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<tr class="separator:ga1a0b758cbc6aed0e4a7633e451b55303"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39f494cf2a6af6ced9eaeac751ea81e4" id="r_ga39f494cf2a6af6ced9eaeac751ea81e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39f494cf2a6af6ced9eaeac751ea81e4">SDIO_MASK_RXOVERRIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a0b758cbc6aed0e4a7633e451b55303">SDIO_MASK_RXOVERRIE_Msk</a></td></tr>
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<tr class="memitem:gafbd0400c13633977796a92dd74adeaf9" id="r_gafbd0400c13633977796a92dd74adeaf9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbd0400c13633977796a92dd74adeaf9">SDIO_MASK_CMDRENDIE_Pos</a>   (6U)</td></tr>
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<tr class="memitem:ga74564e18483f0efdea46c242d9c3b3a5" id="r_ga74564e18483f0efdea46c242d9c3b3a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74564e18483f0efdea46c242d9c3b3a5">SDIO_MASK_CMDRENDIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafbd0400c13633977796a92dd74adeaf9">SDIO_MASK_CMDRENDIE_Pos</a>)</td></tr>
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<tr class="memitem:ga5fdedfc60a2019ff5f64533fcdd0c3f1" id="r_ga5fdedfc60a2019ff5f64533fcdd0c3f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fdedfc60a2019ff5f64533fcdd0c3f1">SDIO_MASK_CMDRENDIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga74564e18483f0efdea46c242d9c3b3a5">SDIO_MASK_CMDRENDIE_Msk</a></td></tr>
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<tr class="memitem:ga6ad32e7a435cc2eaaf3fb38a908a206e" id="r_ga6ad32e7a435cc2eaaf3fb38a908a206e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad32e7a435cc2eaaf3fb38a908a206e">SDIO_MASK_CMDSENTIE_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga6ad32e7a435cc2eaaf3fb38a908a206e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cbd551da11e6e93c52b6727075baf9f" id="r_ga3cbd551da11e6e93c52b6727075baf9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cbd551da11e6e93c52b6727075baf9f">SDIO_MASK_CMDSENTIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad32e7a435cc2eaaf3fb38a908a206e">SDIO_MASK_CMDSENTIE_Pos</a>)</td></tr>
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<tr class="separator:ga3cbd551da11e6e93c52b6727075baf9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d541aea02974c03bd8a8426125c35ff" id="r_ga0d541aea02974c03bd8a8426125c35ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d541aea02974c03bd8a8426125c35ff">SDIO_MASK_CMDSENTIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cbd551da11e6e93c52b6727075baf9f">SDIO_MASK_CMDSENTIE_Msk</a></td></tr>
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<tr class="separator:ga0d541aea02974c03bd8a8426125c35ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6fa6436185588c5ea061ea7f214e81f" id="r_gae6fa6436185588c5ea061ea7f214e81f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6fa6436185588c5ea061ea7f214e81f">SDIO_MASK_DATAENDIE_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga28535e2fb4bbf3caf2764a47535e837f" id="r_ga28535e2fb4bbf3caf2764a47535e837f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28535e2fb4bbf3caf2764a47535e837f">SDIO_MASK_DATAENDIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae6fa6436185588c5ea061ea7f214e81f">SDIO_MASK_DATAENDIE_Pos</a>)</td></tr>
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<tr class="separator:ga28535e2fb4bbf3caf2764a47535e837f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6398bd3e8312eea3b986ab59b80b466" id="r_gae6398bd3e8312eea3b986ab59b80b466"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6398bd3e8312eea3b986ab59b80b466">SDIO_MASK_DATAENDIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga28535e2fb4bbf3caf2764a47535e837f">SDIO_MASK_DATAENDIE_Msk</a></td></tr>
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<tr class="separator:gae6398bd3e8312eea3b986ab59b80b466"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga962af1aaad7bc9eb55689d694b3949a4" id="r_ga962af1aaad7bc9eb55689d694b3949a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga962af1aaad7bc9eb55689d694b3949a4">SDIO_MASK_STBITERRIE_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga962af1aaad7bc9eb55689d694b3949a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0192872018530a05a2cec00d61a6a39" id="r_gad0192872018530a05a2cec00d61a6a39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0192872018530a05a2cec00d61a6a39">SDIO_MASK_STBITERRIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga962af1aaad7bc9eb55689d694b3949a4">SDIO_MASK_STBITERRIE_Pos</a>)</td></tr>
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<tr class="memitem:ga4194bed51eb4a951a58a5d4062ba978f" id="r_ga4194bed51eb4a951a58a5d4062ba978f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4194bed51eb4a951a58a5d4062ba978f">SDIO_MASK_STBITERRIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad0192872018530a05a2cec00d61a6a39">SDIO_MASK_STBITERRIE_Msk</a></td></tr>
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<tr class="memitem:ga75e2c1e3ade0e06784c004b34410e9ef" id="r_ga75e2c1e3ade0e06784c004b34410e9ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75e2c1e3ade0e06784c004b34410e9ef">SDIO_MASK_DBCKENDIE_Pos</a>   (10U)</td></tr>
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<tr class="memitem:gaafd5167ec8f17f72e3d604c3f628bd06" id="r_gaafd5167ec8f17f72e3d604c3f628bd06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafd5167ec8f17f72e3d604c3f628bd06">SDIO_MASK_DBCKENDIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga75e2c1e3ade0e06784c004b34410e9ef">SDIO_MASK_DBCKENDIE_Pos</a>)</td></tr>
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<tr class="separator:gaafd5167ec8f17f72e3d604c3f628bd06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga947e5da36c9eeca0b48f3356067dff00" id="r_ga947e5da36c9eeca0b48f3356067dff00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga947e5da36c9eeca0b48f3356067dff00">SDIO_MASK_DBCKENDIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaafd5167ec8f17f72e3d604c3f628bd06">SDIO_MASK_DBCKENDIE_Msk</a></td></tr>
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<tr class="separator:ga947e5da36c9eeca0b48f3356067dff00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2447a1963bd315c20f05574acd8efac0" id="r_ga2447a1963bd315c20f05574acd8efac0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2447a1963bd315c20f05574acd8efac0">SDIO_MASK_CMDACTIE_Pos</a>   (11U)</td></tr>
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<tr class="memitem:gae44d7772868e54b7a90f90a4a52520ec" id="r_gae44d7772868e54b7a90f90a4a52520ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae44d7772868e54b7a90f90a4a52520ec">SDIO_MASK_CMDACTIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2447a1963bd315c20f05574acd8efac0">SDIO_MASK_CMDACTIE_Pos</a>)</td></tr>
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<tr class="separator:gae44d7772868e54b7a90f90a4a52520ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad63b504f02ea0b1e5ec48962799fde88" id="r_gad63b504f02ea0b1e5ec48962799fde88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad63b504f02ea0b1e5ec48962799fde88">SDIO_MASK_CMDACTIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae44d7772868e54b7a90f90a4a52520ec">SDIO_MASK_CMDACTIE_Msk</a></td></tr>
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<tr class="memitem:ga985a6a5e37ed6fb963deb83f0acd457b" id="r_ga985a6a5e37ed6fb963deb83f0acd457b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga985a6a5e37ed6fb963deb83f0acd457b">SDIO_MASK_TXACTIE_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga985a6a5e37ed6fb963deb83f0acd457b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3bc5a7e08f3f427ccd7769c67233e5d" id="r_gad3bc5a7e08f3f427ccd7769c67233e5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3bc5a7e08f3f427ccd7769c67233e5d">SDIO_MASK_TXACTIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga985a6a5e37ed6fb963deb83f0acd457b">SDIO_MASK_TXACTIE_Pos</a>)</td></tr>
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<tr class="separator:gad3bc5a7e08f3f427ccd7769c67233e5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bbfbc3f69ab77171eb1a0058783b1e0" id="r_ga9bbfbc3f69ab77171eb1a0058783b1e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bbfbc3f69ab77171eb1a0058783b1e0">SDIO_MASK_TXACTIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad3bc5a7e08f3f427ccd7769c67233e5d">SDIO_MASK_TXACTIE_Msk</a></td></tr>
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<tr class="separator:ga9bbfbc3f69ab77171eb1a0058783b1e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga243af5a2aca3b596fa214416a70f969f" id="r_ga243af5a2aca3b596fa214416a70f969f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga243af5a2aca3b596fa214416a70f969f">SDIO_MASK_RXACTIE_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga70e765da34a593f616c4435093d0a1d8" id="r_ga70e765da34a593f616c4435093d0a1d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70e765da34a593f616c4435093d0a1d8">SDIO_MASK_RXACTIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga243af5a2aca3b596fa214416a70f969f">SDIO_MASK_RXACTIE_Pos</a>)</td></tr>
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<tr class="memitem:ga9768c39a5d9d3c5519eb522c62a75eae" id="r_ga9768c39a5d9d3c5519eb522c62a75eae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9768c39a5d9d3c5519eb522c62a75eae">SDIO_MASK_RXACTIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga70e765da34a593f616c4435093d0a1d8">SDIO_MASK_RXACTIE_Msk</a></td></tr>
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<tr class="separator:ga9768c39a5d9d3c5519eb522c62a75eae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad10c89cc7329707f9c9aa1c3ad259980" id="r_gad10c89cc7329707f9c9aa1c3ad259980"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad10c89cc7329707f9c9aa1c3ad259980">SDIO_MASK_TXFIFOHEIE_Pos</a>   (14U)</td></tr>
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<tr class="separator:gad10c89cc7329707f9c9aa1c3ad259980"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31a0538971e372ab926c3a9f935b2502" id="r_ga31a0538971e372ab926c3a9f935b2502"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31a0538971e372ab926c3a9f935b2502">SDIO_MASK_TXFIFOHEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad10c89cc7329707f9c9aa1c3ad259980">SDIO_MASK_TXFIFOHEIE_Pos</a>)</td></tr>
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<tr class="separator:ga31a0538971e372ab926c3a9f935b2502"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9cf28de8489fee023ea353df0e13fa7" id="r_gad9cf28de8489fee023ea353df0e13fa7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9cf28de8489fee023ea353df0e13fa7">SDIO_MASK_TXFIFOHEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31a0538971e372ab926c3a9f935b2502">SDIO_MASK_TXFIFOHEIE_Msk</a></td></tr>
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<tr class="separator:gad9cf28de8489fee023ea353df0e13fa7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad002b428c2d95c229b914fac2a620ef8" id="r_gad002b428c2d95c229b914fac2a620ef8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad002b428c2d95c229b914fac2a620ef8">SDIO_MASK_RXFIFOHFIE_Pos</a>   (15U)</td></tr>
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<tr class="separator:gad002b428c2d95c229b914fac2a620ef8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4590335a3dcdb764c68d8f31bc58d2ba" id="r_ga4590335a3dcdb764c68d8f31bc58d2ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4590335a3dcdb764c68d8f31bc58d2ba">SDIO_MASK_RXFIFOHFIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad002b428c2d95c229b914fac2a620ef8">SDIO_MASK_RXFIFOHFIE_Pos</a>)</td></tr>
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<tr class="separator:ga4590335a3dcdb764c68d8f31bc58d2ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04d50028fc671494508aecb04e727102" id="r_ga04d50028fc671494508aecb04e727102"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04d50028fc671494508aecb04e727102">SDIO_MASK_RXFIFOHFIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4590335a3dcdb764c68d8f31bc58d2ba">SDIO_MASK_RXFIFOHFIE_Msk</a></td></tr>
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<tr class="separator:ga04d50028fc671494508aecb04e727102"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadb33e583b2dd534458a807d4efa4d97" id="r_gaadb33e583b2dd534458a807d4efa4d97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadb33e583b2dd534458a807d4efa4d97">SDIO_MASK_TXFIFOFIE_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaadb33e583b2dd534458a807d4efa4d97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae60848e2a91f045224142d4a9ba87baf" id="r_gae60848e2a91f045224142d4a9ba87baf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae60848e2a91f045224142d4a9ba87baf">SDIO_MASK_TXFIFOFIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaadb33e583b2dd534458a807d4efa4d97">SDIO_MASK_TXFIFOFIE_Pos</a>)</td></tr>
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<tr class="separator:gae60848e2a91f045224142d4a9ba87baf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03a602b975ce16ef03083947aded0172" id="r_ga03a602b975ce16ef03083947aded0172"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03a602b975ce16ef03083947aded0172">SDIO_MASK_TXFIFOFIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae60848e2a91f045224142d4a9ba87baf">SDIO_MASK_TXFIFOFIE_Msk</a></td></tr>
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<tr class="memitem:gadcac0bf1f49c1677a8fee6aab994a453" id="r_gadcac0bf1f49c1677a8fee6aab994a453"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcac0bf1f49c1677a8fee6aab994a453">SDIO_MASK_RXFIFOFIE_Pos</a>   (17U)</td></tr>
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<tr class="separator:gadcac0bf1f49c1677a8fee6aab994a453"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4550fadc2377f998ad61c94f37047e41" id="r_ga4550fadc2377f998ad61c94f37047e41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4550fadc2377f998ad61c94f37047e41">SDIO_MASK_RXFIFOFIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadcac0bf1f49c1677a8fee6aab994a453">SDIO_MASK_RXFIFOFIE_Pos</a>)</td></tr>
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<tr class="separator:ga4550fadc2377f998ad61c94f37047e41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf18c4bdf8fa4ee85596a89de00158fbb" id="r_gaf18c4bdf8fa4ee85596a89de00158fbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf18c4bdf8fa4ee85596a89de00158fbb">SDIO_MASK_RXFIFOFIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4550fadc2377f998ad61c94f37047e41">SDIO_MASK_RXFIFOFIE_Msk</a></td></tr>
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<tr class="memitem:ga1c795dfbbb4b28e0acdec9ad9ec7f590" id="r_ga1c795dfbbb4b28e0acdec9ad9ec7f590"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c795dfbbb4b28e0acdec9ad9ec7f590">SDIO_MASK_TXFIFOEIE_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga1c795dfbbb4b28e0acdec9ad9ec7f590"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05690f47ab17f3296f9e7c1f775546f1" id="r_ga05690f47ab17f3296f9e7c1f775546f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05690f47ab17f3296f9e7c1f775546f1">SDIO_MASK_TXFIFOEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c795dfbbb4b28e0acdec9ad9ec7f590">SDIO_MASK_TXFIFOEIE_Pos</a>)</td></tr>
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<tr class="separator:ga05690f47ab17f3296f9e7c1f775546f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11e1d67150fad62dc1ca7783f3a19372" id="r_ga11e1d67150fad62dc1ca7783f3a19372"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11e1d67150fad62dc1ca7783f3a19372">SDIO_MASK_TXFIFOEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga05690f47ab17f3296f9e7c1f775546f1">SDIO_MASK_TXFIFOEIE_Msk</a></td></tr>
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<tr class="separator:ga11e1d67150fad62dc1ca7783f3a19372"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac80b2ced5391058cad7184a273b7c8fd" id="r_gac80b2ced5391058cad7184a273b7c8fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac80b2ced5391058cad7184a273b7c8fd">SDIO_MASK_RXFIFOEIE_Pos</a>   (19U)</td></tr>
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<tr class="separator:gac80b2ced5391058cad7184a273b7c8fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga432a6fa01c2c45135e5d7c43fef9f21b" id="r_ga432a6fa01c2c45135e5d7c43fef9f21b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga432a6fa01c2c45135e5d7c43fef9f21b">SDIO_MASK_RXFIFOEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac80b2ced5391058cad7184a273b7c8fd">SDIO_MASK_RXFIFOEIE_Pos</a>)</td></tr>
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<tr class="separator:ga432a6fa01c2c45135e5d7c43fef9f21b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbc23fa1c153a9e5216baeef7922e412" id="r_gadbc23fa1c153a9e5216baeef7922e412"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbc23fa1c153a9e5216baeef7922e412">SDIO_MASK_RXFIFOEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga432a6fa01c2c45135e5d7c43fef9f21b">SDIO_MASK_RXFIFOEIE_Msk</a></td></tr>
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<tr class="separator:gadbc23fa1c153a9e5216baeef7922e412"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5efa0b963adeda521a951841b9da44e5" id="r_ga5efa0b963adeda521a951841b9da44e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5efa0b963adeda521a951841b9da44e5">SDIO_MASK_TXDAVLIE_Pos</a>   (20U)</td></tr>
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<tr class="memitem:ga36e2a9aae5673ab117a1e33c2af0d801" id="r_ga36e2a9aae5673ab117a1e33c2af0d801"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36e2a9aae5673ab117a1e33c2af0d801">SDIO_MASK_TXDAVLIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5efa0b963adeda521a951841b9da44e5">SDIO_MASK_TXDAVLIE_Pos</a>)</td></tr>
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<tr class="separator:ga36e2a9aae5673ab117a1e33c2af0d801"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a1988093a6df087ebb8ff41a51962da" id="r_ga9a1988093a6df087ebb8ff41a51962da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a1988093a6df087ebb8ff41a51962da">SDIO_MASK_TXDAVLIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36e2a9aae5673ab117a1e33c2af0d801">SDIO_MASK_TXDAVLIE_Msk</a></td></tr>
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<tr class="memitem:gadb8703a3b6e980002afae732dc62f40e" id="r_gadb8703a3b6e980002afae732dc62f40e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb8703a3b6e980002afae732dc62f40e">SDIO_MASK_RXDAVLIE_Pos</a>   (21U)</td></tr>
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<tr class="memitem:ga20d7d199042e90d08b1542fbf551d756" id="r_ga20d7d199042e90d08b1542fbf551d756"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20d7d199042e90d08b1542fbf551d756">SDIO_MASK_RXDAVLIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb8703a3b6e980002afae732dc62f40e">SDIO_MASK_RXDAVLIE_Pos</a>)</td></tr>
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<tr class="separator:ga20d7d199042e90d08b1542fbf551d756"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa9da7d15902e6f94b79968a07250696" id="r_gafa9da7d15902e6f94b79968a07250696"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa9da7d15902e6f94b79968a07250696">SDIO_MASK_RXDAVLIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga20d7d199042e90d08b1542fbf551d756">SDIO_MASK_RXDAVLIE_Msk</a></td></tr>
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<tr class="memitem:gac5b99a0d2f0e9d1629e5fe9904c8d042" id="r_gac5b99a0d2f0e9d1629e5fe9904c8d042"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5b99a0d2f0e9d1629e5fe9904c8d042">SDIO_MASK_SDIOITIE_Pos</a>   (22U)</td></tr>
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<tr class="memitem:gab53292cf69bf87c65f8b41970b06c4fd" id="r_gab53292cf69bf87c65f8b41970b06c4fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab53292cf69bf87c65f8b41970b06c4fd">SDIO_MASK_SDIOITIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac5b99a0d2f0e9d1629e5fe9904c8d042">SDIO_MASK_SDIOITIE_Pos</a>)</td></tr>
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<tr class="memitem:gad73b7c7d480d2d71613995cfecc59138" id="r_gad73b7c7d480d2d71613995cfecc59138"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad73b7c7d480d2d71613995cfecc59138">SDIO_MASK_SDIOITIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab53292cf69bf87c65f8b41970b06c4fd">SDIO_MASK_SDIOITIE_Msk</a></td></tr>
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<tr class="memitem:gacc625ef424192b5a0875466d58b7d32a" id="r_gacc625ef424192b5a0875466d58b7d32a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc625ef424192b5a0875466d58b7d32a">SDIO_MASK_CEATAENDIE_Pos</a>   (23U)</td></tr>
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<tr class="memitem:ga7131c534b24505a7ec74cfbcd2d2fbca" id="r_ga7131c534b24505a7ec74cfbcd2d2fbca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7131c534b24505a7ec74cfbcd2d2fbca">SDIO_MASK_CEATAENDIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacc625ef424192b5a0875466d58b7d32a">SDIO_MASK_CEATAENDIE_Pos</a>)</td></tr>
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<tr class="memitem:ga0a19dd3039888ebdc40b2406be400749" id="r_ga0a19dd3039888ebdc40b2406be400749"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a19dd3039888ebdc40b2406be400749">SDIO_MASK_CEATAENDIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7131c534b24505a7ec74cfbcd2d2fbca">SDIO_MASK_CEATAENDIE_Msk</a></td></tr>
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<tr class="memitem:ga078938dbe175e28e4d3898a04db76fc9" id="r_ga078938dbe175e28e4d3898a04db76fc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga078938dbe175e28e4d3898a04db76fc9">SDIO_FIFOCNT_FIFOCOUNT_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga078938dbe175e28e4d3898a04db76fc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f6da07732f3b3e77ffabfed13a613ea" id="r_ga8f6da07732f3b3e77ffabfed13a613ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f6da07732f3b3e77ffabfed13a613ea">SDIO_FIFOCNT_FIFOCOUNT_Msk</a>   (0xFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga078938dbe175e28e4d3898a04db76fc9">SDIO_FIFOCNT_FIFOCOUNT_Pos</a>)</td></tr>
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<tr class="separator:ga8f6da07732f3b3e77ffabfed13a613ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa45f5e0a2be89267f79cad57f456f0a2" id="r_gaa45f5e0a2be89267f79cad57f456f0a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa45f5e0a2be89267f79cad57f456f0a2">SDIO_FIFOCNT_FIFOCOUNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f6da07732f3b3e77ffabfed13a613ea">SDIO_FIFOCNT_FIFOCOUNT_Msk</a></td></tr>
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<tr class="separator:gaa45f5e0a2be89267f79cad57f456f0a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga801e95e916e2fefcab25aad333e63c0c" id="r_ga801e95e916e2fefcab25aad333e63c0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga801e95e916e2fefcab25aad333e63c0c">SDIO_FIFO_FIFODATA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga801e95e916e2fefcab25aad333e63c0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2000ca9b6103ee2ad7588b34283cfff" id="r_gaf2000ca9b6103ee2ad7588b34283cfff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2000ca9b6103ee2ad7588b34283cfff">SDIO_FIFO_FIFODATA_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga801e95e916e2fefcab25aad333e63c0c">SDIO_FIFO_FIFODATA_Pos</a>)</td></tr>
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<tr class="memitem:ga5fc0d1e12c55398e2881fe917672da25" id="r_ga5fc0d1e12c55398e2881fe917672da25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fc0d1e12c55398e2881fe917672da25">SDIO_FIFO_FIFODATA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2000ca9b6103ee2ad7588b34283cfff">SDIO_FIFO_FIFODATA_Msk</a></td></tr>
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<tr class="memitem:gadf384b964839c07357ce8503464436ed" id="r_gadf384b964839c07357ce8503464436ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf384b964839c07357ce8503464436ed">SPI_I2S_FULLDUPLEX_SUPPORT</a></td></tr>
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<tr class="memitem:ga2f1d2c5a9e481ca06d0e29332f6f948a" id="r_ga2f1d2c5a9e481ca06d0e29332f6f948a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f1d2c5a9e481ca06d0e29332f6f948a">SPI_CR1_CPHA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2f1d2c5a9e481ca06d0e29332f6f948a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07233629d8982af09168080501d30522" id="r_ga07233629d8982af09168080501d30522"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07233629d8982af09168080501d30522">SPI_CR1_CPHA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f1d2c5a9e481ca06d0e29332f6f948a">SPI_CR1_CPHA_Pos</a>)</td></tr>
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<tr class="separator:ga07233629d8982af09168080501d30522"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97602d8ded14bbd2c1deadaf308755a3" id="r_ga97602d8ded14bbd2c1deadaf308755a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97602d8ded14bbd2c1deadaf308755a3">SPI_CR1_CPHA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga07233629d8982af09168080501d30522">SPI_CR1_CPHA_Msk</a></td></tr>
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<tr class="memitem:gadd3274c0dce6293370773c5050f9c4be" id="r_gadd3274c0dce6293370773c5050f9c4be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd3274c0dce6293370773c5050f9c4be">SPI_CR1_CPOL_Pos</a>   (1U)</td></tr>
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<tr class="separator:gadd3274c0dce6293370773c5050f9c4be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95caab18b821909a9547771f9316e2b0" id="r_ga95caab18b821909a9547771f9316e2b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95caab18b821909a9547771f9316e2b0">SPI_CR1_CPOL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadd3274c0dce6293370773c5050f9c4be">SPI_CR1_CPOL_Pos</a>)</td></tr>
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<tr class="memitem:ga2616a10f5118cdc68fbdf0582481e124" id="r_ga2616a10f5118cdc68fbdf0582481e124"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2616a10f5118cdc68fbdf0582481e124">SPI_CR1_CPOL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga95caab18b821909a9547771f9316e2b0">SPI_CR1_CPOL_Msk</a></td></tr>
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<tr class="memitem:ga27567886a2c76d088e01ad16851cdb71" id="r_ga27567886a2c76d088e01ad16851cdb71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27567886a2c76d088e01ad16851cdb71">SPI_CR1_MSTR_Pos</a>   (2U)</td></tr>
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<tr class="memitem:gab94621170d4ce16d6e7f2310461df97d" id="r_gab94621170d4ce16d6e7f2310461df97d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab94621170d4ce16d6e7f2310461df97d">SPI_CR1_MSTR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27567886a2c76d088e01ad16851cdb71">SPI_CR1_MSTR_Pos</a>)</td></tr>
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<tr class="memitem:ga5b3b6ae107fc37bf18e14506298d7a55" id="r_ga5b3b6ae107fc37bf18e14506298d7a55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b3b6ae107fc37bf18e14506298d7a55">SPI_CR1_MSTR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab94621170d4ce16d6e7f2310461df97d">SPI_CR1_MSTR_Msk</a></td></tr>
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<tr class="separator:ga5b3b6ae107fc37bf18e14506298d7a55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6a71c219a81b476e66c3579d72120b9" id="r_gac6a71c219a81b476e66c3579d72120b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6a71c219a81b476e66c3579d72120b9">SPI_CR1_BR_Pos</a>   (3U)</td></tr>
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<tr class="memitem:gaec378749f03998b5d2769c3d83deef23" id="r_gaec378749f03998b5d2769c3d83deef23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec378749f03998b5d2769c3d83deef23">SPI_CR1_BR_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac6a71c219a81b476e66c3579d72120b9">SPI_CR1_BR_Pos</a>)</td></tr>
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<tr class="memitem:ga261af22667719a32b3ce566c1e261936" id="r_ga261af22667719a32b3ce566c1e261936"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga261af22667719a32b3ce566c1e261936">SPI_CR1_BR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec378749f03998b5d2769c3d83deef23">SPI_CR1_BR_Msk</a></td></tr>
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<tr class="memitem:gaa364b123cf797044094cc229330ce321" id="r_gaa364b123cf797044094cc229330ce321"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa364b123cf797044094cc229330ce321">SPI_CR1_BR_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac6a71c219a81b476e66c3579d72120b9">SPI_CR1_BR_Pos</a>)</td></tr>
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<tr class="memitem:ga45e93d18c8966964ed1926d5ca87ef46" id="r_ga45e93d18c8966964ed1926d5ca87ef46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45e93d18c8966964ed1926d5ca87ef46">SPI_CR1_BR_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac6a71c219a81b476e66c3579d72120b9">SPI_CR1_BR_Pos</a>)</td></tr>
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<tr class="memitem:ga28b823d564e9d90150bcc6744b4ed622" id="r_ga28b823d564e9d90150bcc6744b4ed622"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28b823d564e9d90150bcc6744b4ed622">SPI_CR1_BR_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac6a71c219a81b476e66c3579d72120b9">SPI_CR1_BR_Pos</a>)</td></tr>
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<tr class="memitem:ga3f5515b536f82c1d91a64bd534030284" id="r_ga3f5515b536f82c1d91a64bd534030284"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f5515b536f82c1d91a64bd534030284">SPI_CR1_SPE_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga3f5515b536f82c1d91a64bd534030284"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cf4679f3fe8cfa50ecbac5b45d084bb" id="r_ga5cf4679f3fe8cfa50ecbac5b45d084bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5cf4679f3fe8cfa50ecbac5b45d084bb">SPI_CR1_SPE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f5515b536f82c1d91a64bd534030284">SPI_CR1_SPE_Pos</a>)</td></tr>
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<tr class="separator:ga5cf4679f3fe8cfa50ecbac5b45d084bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5a646d978d3b98eb7c6a5d95d75c3f9" id="r_gac5a646d978d3b98eb7c6a5d95d75c3f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5a646d978d3b98eb7c6a5d95d75c3f9">SPI_CR1_SPE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cf4679f3fe8cfa50ecbac5b45d084bb">SPI_CR1_SPE_Msk</a></td></tr>
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<tr class="separator:gac5a646d978d3b98eb7c6a5d95d75c3f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga982b564879d1dc60a3be787409df0c27" id="r_ga982b564879d1dc60a3be787409df0c27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga982b564879d1dc60a3be787409df0c27">SPI_CR1_LSBFIRST_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga982b564879d1dc60a3be787409df0c27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadfc0bbf312eaf7e0a5bbe54fdcc2f12e" id="r_gadfc0bbf312eaf7e0a5bbe54fdcc2f12e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfc0bbf312eaf7e0a5bbe54fdcc2f12e">SPI_CR1_LSBFIRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga982b564879d1dc60a3be787409df0c27">SPI_CR1_LSBFIRST_Pos</a>)</td></tr>
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<tr class="separator:gadfc0bbf312eaf7e0a5bbe54fdcc2f12e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab929e9d5ddbb66f229c501ab18d0e6e8" id="r_gab929e9d5ddbb66f229c501ab18d0e6e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab929e9d5ddbb66f229c501ab18d0e6e8">SPI_CR1_LSBFIRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadfc0bbf312eaf7e0a5bbe54fdcc2f12e">SPI_CR1_LSBFIRST_Msk</a></td></tr>
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<tr class="separator:gab929e9d5ddbb66f229c501ab18d0e6e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad99cf4909aa9307e01f61645451a9d0e" id="r_gad99cf4909aa9307e01f61645451a9d0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad99cf4909aa9307e01f61645451a9d0e">SPI_CR1_SSI_Pos</a>   (8U)</td></tr>
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<tr class="separator:gad99cf4909aa9307e01f61645451a9d0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0bfe153c59ffd52199d4b37e3287f89" id="r_gaf0bfe153c59ffd52199d4b37e3287f89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0bfe153c59ffd52199d4b37e3287f89">SPI_CR1_SSI_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad99cf4909aa9307e01f61645451a9d0e">SPI_CR1_SSI_Pos</a>)</td></tr>
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<tr class="separator:gaf0bfe153c59ffd52199d4b37e3287f89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f154374b58c0234f82ea326cb303a1e" id="r_ga5f154374b58c0234f82ea326cb303a1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f154374b58c0234f82ea326cb303a1e">SPI_CR1_SSI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0bfe153c59ffd52199d4b37e3287f89">SPI_CR1_SSI_Msk</a></td></tr>
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<tr class="separator:ga5f154374b58c0234f82ea326cb303a1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2909290fab17ee930afc335811f574c" id="r_gab2909290fab17ee930afc335811f574c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2909290fab17ee930afc335811f574c">SPI_CR1_SSM_Pos</a>   (9U)</td></tr>
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<tr class="separator:gab2909290fab17ee930afc335811f574c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43417092a8ed735def35b386a251a7bb" id="r_ga43417092a8ed735def35b386a251a7bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43417092a8ed735def35b386a251a7bb">SPI_CR1_SSM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab2909290fab17ee930afc335811f574c">SPI_CR1_SSM_Pos</a>)</td></tr>
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<tr class="separator:ga43417092a8ed735def35b386a251a7bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e236047e05106cf1ba7929766311382" id="r_ga0e236047e05106cf1ba7929766311382"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e236047e05106cf1ba7929766311382">SPI_CR1_SSM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga43417092a8ed735def35b386a251a7bb">SPI_CR1_SSM_Msk</a></td></tr>
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<tr class="separator:ga0e236047e05106cf1ba7929766311382"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd702fae4dcca65f3b43b2e02f67ee7b" id="r_gadd702fae4dcca65f3b43b2e02f67ee7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd702fae4dcca65f3b43b2e02f67ee7b">SPI_CR1_RXONLY_Pos</a>   (10U)</td></tr>
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<tr class="separator:gadd702fae4dcca65f3b43b2e02f67ee7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02d6321808ed988c60d703e062d58b64" id="r_ga02d6321808ed988c60d703e062d58b64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02d6321808ed988c60d703e062d58b64">SPI_CR1_RXONLY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadd702fae4dcca65f3b43b2e02f67ee7b">SPI_CR1_RXONLY_Pos</a>)</td></tr>
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<tr class="separator:ga02d6321808ed988c60d703e062d58b64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ffecf774b84a8cdc11ab1f931791883" id="r_ga9ffecf774b84a8cdc11ab1f931791883"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ffecf774b84a8cdc11ab1f931791883">SPI_CR1_RXONLY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga02d6321808ed988c60d703e062d58b64">SPI_CR1_RXONLY_Msk</a></td></tr>
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<tr class="separator:ga9ffecf774b84a8cdc11ab1f931791883"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5290662db14690d4bcf30ed9e4694462" id="r_ga5290662db14690d4bcf30ed9e4694462"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5290662db14690d4bcf30ed9e4694462">SPI_CR1_DFF_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga5290662db14690d4bcf30ed9e4694462"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a87fe55ac0f85e207a58fcd73610f46" id="r_ga3a87fe55ac0f85e207a58fcd73610f46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a87fe55ac0f85e207a58fcd73610f46">SPI_CR1_DFF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5290662db14690d4bcf30ed9e4694462">SPI_CR1_DFF_Pos</a>)</td></tr>
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<tr class="separator:ga3a87fe55ac0f85e207a58fcd73610f46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ffabea0de695a19198d906bf6a1d9fd" id="r_ga3ffabea0de695a19198d906bf6a1d9fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ffabea0de695a19198d906bf6a1d9fd">SPI_CR1_DFF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a87fe55ac0f85e207a58fcd73610f46">SPI_CR1_DFF_Msk</a></td></tr>
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<tr class="separator:ga3ffabea0de695a19198d906bf6a1d9fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4280bd0e8bcc3a268fa3a17b684499d7" id="r_ga4280bd0e8bcc3a268fa3a17b684499d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4280bd0e8bcc3a268fa3a17b684499d7">SPI_CR1_CRCNEXT_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga4280bd0e8bcc3a268fa3a17b684499d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebbf9ed4a9723901f5414654f151d816" id="r_gaebbf9ed4a9723901f5414654f151d816"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebbf9ed4a9723901f5414654f151d816">SPI_CR1_CRCNEXT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4280bd0e8bcc3a268fa3a17b684499d7">SPI_CR1_CRCNEXT_Pos</a>)</td></tr>
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<tr class="separator:gaebbf9ed4a9723901f5414654f151d816"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57072f13c2e54c12186ae8c5fdecb250" id="r_ga57072f13c2e54c12186ae8c5fdecb250"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57072f13c2e54c12186ae8c5fdecb250">SPI_CR1_CRCNEXT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaebbf9ed4a9723901f5414654f151d816">SPI_CR1_CRCNEXT_Msk</a></td></tr>
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<tr class="separator:ga57072f13c2e54c12186ae8c5fdecb250"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54cb3022c5e3d98cd81a7ff1cb087fac" id="r_ga54cb3022c5e3d98cd81a7ff1cb087fac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54cb3022c5e3d98cd81a7ff1cb087fac">SPI_CR1_CRCEN_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga54cb3022c5e3d98cd81a7ff1cb087fac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a5a712f31c65ea8ee829377edc5ede3" id="r_ga2a5a712f31c65ea8ee829377edc5ede3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5a712f31c65ea8ee829377edc5ede3">SPI_CR1_CRCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga54cb3022c5e3d98cd81a7ff1cb087fac">SPI_CR1_CRCEN_Pos</a>)</td></tr>
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<tr class="separator:ga2a5a712f31c65ea8ee829377edc5ede3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9339b7c6466f09ad26c26b3bb81c51b" id="r_gac9339b7c6466f09ad26c26b3bb81c51b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9339b7c6466f09ad26c26b3bb81c51b">SPI_CR1_CRCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5a712f31c65ea8ee829377edc5ede3">SPI_CR1_CRCEN_Msk</a></td></tr>
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<tr class="separator:gac9339b7c6466f09ad26c26b3bb81c51b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2975c27caad9e31aad719d78d591ac1d" id="r_ga2975c27caad9e31aad719d78d591ac1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2975c27caad9e31aad719d78d591ac1d">SPI_CR1_BIDIOE_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga2975c27caad9e31aad719d78d591ac1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bcee503ed5669187bb980faf90d57ca" id="r_ga5bcee503ed5669187bb980faf90d57ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bcee503ed5669187bb980faf90d57ca">SPI_CR1_BIDIOE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2975c27caad9e31aad719d78d591ac1d">SPI_CR1_BIDIOE_Pos</a>)</td></tr>
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<tr class="separator:ga5bcee503ed5669187bb980faf90d57ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga378953916b7701bd49f063c0366b703f" id="r_ga378953916b7701bd49f063c0366b703f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga378953916b7701bd49f063c0366b703f">SPI_CR1_BIDIOE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bcee503ed5669187bb980faf90d57ca">SPI_CR1_BIDIOE_Msk</a></td></tr>
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<tr class="separator:ga378953916b7701bd49f063c0366b703f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab07c9facbfdb0a7d5d89b1fd6a3ef711" id="r_gab07c9facbfdb0a7d5d89b1fd6a3ef711"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab07c9facbfdb0a7d5d89b1fd6a3ef711">SPI_CR1_BIDIMODE_Pos</a>   (15U)</td></tr>
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<tr class="separator:gab07c9facbfdb0a7d5d89b1fd6a3ef711"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2c9301aa73d6795e9739f8d12d42c15" id="r_gae2c9301aa73d6795e9739f8d12d42c15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2c9301aa73d6795e9739f8d12d42c15">SPI_CR1_BIDIMODE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab07c9facbfdb0a7d5d89b1fd6a3ef711">SPI_CR1_BIDIMODE_Pos</a>)</td></tr>
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<tr class="separator:gae2c9301aa73d6795e9739f8d12d42c15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43608d3c2959fc9ca64398d61cbf484e" id="r_ga43608d3c2959fc9ca64398d61cbf484e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43608d3c2959fc9ca64398d61cbf484e">SPI_CR1_BIDIMODE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae2c9301aa73d6795e9739f8d12d42c15">SPI_CR1_BIDIMODE_Msk</a></td></tr>
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<tr class="separator:ga43608d3c2959fc9ca64398d61cbf484e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3079c4eebd0aef7bd22817bb99f21021" id="r_ga3079c4eebd0aef7bd22817bb99f21021"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3079c4eebd0aef7bd22817bb99f21021">SPI_CR2_RXDMAEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3079c4eebd0aef7bd22817bb99f21021"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae038c9a5d545c01038bf6628492cdc6e" id="r_gae038c9a5d545c01038bf6628492cdc6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae038c9a5d545c01038bf6628492cdc6e">SPI_CR2_RXDMAEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3079c4eebd0aef7bd22817bb99f21021">SPI_CR2_RXDMAEN_Pos</a>)</td></tr>
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<tr class="memitem:gaf23c590d98279634af05550702a806da" id="r_gaf23c590d98279634af05550702a806da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf23c590d98279634af05550702a806da">SPI_CR2_RXDMAEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae038c9a5d545c01038bf6628492cdc6e">SPI_CR2_RXDMAEN_Msk</a></td></tr>
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<tr class="memitem:ga24ae89d7e48296566cd18fb7495a2c81" id="r_ga24ae89d7e48296566cd18fb7495a2c81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24ae89d7e48296566cd18fb7495a2c81">SPI_CR2_TXDMAEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga24ae89d7e48296566cd18fb7495a2c81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga884bb8bbd8b60cea7b7fb11a23231678" id="r_ga884bb8bbd8b60cea7b7fb11a23231678"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga884bb8bbd8b60cea7b7fb11a23231678">SPI_CR2_TXDMAEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24ae89d7e48296566cd18fb7495a2c81">SPI_CR2_TXDMAEN_Pos</a>)</td></tr>
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<tr class="separator:ga884bb8bbd8b60cea7b7fb11a23231678"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3eee671793983a3bd669c9173b2ce210" id="r_ga3eee671793983a3bd669c9173b2ce210"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3eee671793983a3bd669c9173b2ce210">SPI_CR2_TXDMAEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga884bb8bbd8b60cea7b7fb11a23231678">SPI_CR2_TXDMAEN_Msk</a></td></tr>
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<tr class="separator:ga3eee671793983a3bd669c9173b2ce210"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0d0f5f51a5804e1a204bf1643516896" id="r_gaa0d0f5f51a5804e1a204bf1643516896"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0d0f5f51a5804e1a204bf1643516896">SPI_CR2_SSOE_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaa0d0f5f51a5804e1a204bf1643516896"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4de245d8ff3e31709fd9a665e58f15c1" id="r_ga4de245d8ff3e31709fd9a665e58f15c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4de245d8ff3e31709fd9a665e58f15c1">SPI_CR2_SSOE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0d0f5f51a5804e1a204bf1643516896">SPI_CR2_SSOE_Pos</a>)</td></tr>
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<tr class="separator:ga4de245d8ff3e31709fd9a665e58f15c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae94612b95395eff626f5f3d7d28352dd" id="r_gae94612b95395eff626f5f3d7d28352dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae94612b95395eff626f5f3d7d28352dd">SPI_CR2_SSOE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4de245d8ff3e31709fd9a665e58f15c1">SPI_CR2_SSOE_Msk</a></td></tr>
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<tr class="separator:gae94612b95395eff626f5f3d7d28352dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa192ac1c1066c8867a6fec7de630d222" id="r_gaa192ac1c1066c8867a6fec7de630d222"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa192ac1c1066c8867a6fec7de630d222">SPI_CR2_FRF_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaa192ac1c1066c8867a6fec7de630d222"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47060f3941e2410bd9bc3b570f39a3d1" id="r_ga47060f3941e2410bd9bc3b570f39a3d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47060f3941e2410bd9bc3b570f39a3d1">SPI_CR2_FRF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa192ac1c1066c8867a6fec7de630d222">SPI_CR2_FRF_Pos</a>)</td></tr>
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<tr class="separator:ga47060f3941e2410bd9bc3b570f39a3d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09e3f41fa2150831afaac191046087f2" id="r_ga09e3f41fa2150831afaac191046087f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09e3f41fa2150831afaac191046087f2">SPI_CR2_FRF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga47060f3941e2410bd9bc3b570f39a3d1">SPI_CR2_FRF_Msk</a></td></tr>
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<tr class="separator:ga09e3f41fa2150831afaac191046087f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga632cdba8557df9c3bbd2561b93f4e0f7" id="r_ga632cdba8557df9c3bbd2561b93f4e0f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga632cdba8557df9c3bbd2561b93f4e0f7">SPI_CR2_ERRIE_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga632cdba8557df9c3bbd2561b93f4e0f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fb21a03a7b4e7bd38520e2909063c92" id="r_ga0fb21a03a7b4e7bd38520e2909063c92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fb21a03a7b4e7bd38520e2909063c92">SPI_CR2_ERRIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga632cdba8557df9c3bbd2561b93f4e0f7">SPI_CR2_ERRIE_Pos</a>)</td></tr>
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<tr class="separator:ga0fb21a03a7b4e7bd38520e2909063c92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf18705567de7ab52a62e5ef3ba27418b" id="r_gaf18705567de7ab52a62e5ef3ba27418b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf18705567de7ab52a62e5ef3ba27418b">SPI_CR2_ERRIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0fb21a03a7b4e7bd38520e2909063c92">SPI_CR2_ERRIE_Msk</a></td></tr>
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<tr class="separator:gaf18705567de7ab52a62e5ef3ba27418b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2e1e16fa6007b96880333d0321c5971" id="r_gaf2e1e16fa6007b96880333d0321c5971"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2e1e16fa6007b96880333d0321c5971">SPI_CR2_RXNEIE_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaf2e1e16fa6007b96880333d0321c5971"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ad371f3900a415251ab34cd186d9a44" id="r_ga3ad371f3900a415251ab34cd186d9a44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ad371f3900a415251ab34cd186d9a44">SPI_CR2_RXNEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2e1e16fa6007b96880333d0321c5971">SPI_CR2_RXNEIE_Pos</a>)</td></tr>
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<tr class="separator:ga3ad371f3900a415251ab34cd186d9a44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7d4c37fbbcced7f2a0421e6ffd103ea" id="r_gaa7d4c37fbbcced7f2a0421e6ffd103ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7d4c37fbbcced7f2a0421e6ffd103ea">SPI_CR2_RXNEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ad371f3900a415251ab34cd186d9a44">SPI_CR2_RXNEIE_Msk</a></td></tr>
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<tr class="separator:gaa7d4c37fbbcced7f2a0421e6ffd103ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01e9b00dc195c10d1baefd0687ab9262" id="r_ga01e9b00dc195c10d1baefd0687ab9262"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01e9b00dc195c10d1baefd0687ab9262">SPI_CR2_TXEIE_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga01e9b00dc195c10d1baefd0687ab9262"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64d3cd4fd2b7dca5e43332a3e2a36641" id="r_ga64d3cd4fd2b7dca5e43332a3e2a36641"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64d3cd4fd2b7dca5e43332a3e2a36641">SPI_CR2_TXEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga01e9b00dc195c10d1baefd0687ab9262">SPI_CR2_TXEIE_Pos</a>)</td></tr>
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<tr class="separator:ga64d3cd4fd2b7dca5e43332a3e2a36641"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23f683a1252ccaf625cae1a978989b2c" id="r_ga23f683a1252ccaf625cae1a978989b2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23f683a1252ccaf625cae1a978989b2c">SPI_CR2_TXEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64d3cd4fd2b7dca5e43332a3e2a36641">SPI_CR2_TXEIE_Msk</a></td></tr>
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<tr class="separator:ga23f683a1252ccaf625cae1a978989b2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga306a27b203d1275f848f2767d76c9e3b" id="r_ga306a27b203d1275f848f2767d76c9e3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga306a27b203d1275f848f2767d76c9e3b">SPI_SR_RXNE_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga306a27b203d1275f848f2767d76c9e3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85e7198d3d1f577cae637c8295e7691e" id="r_ga85e7198d3d1f577cae637c8295e7691e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85e7198d3d1f577cae637c8295e7691e">SPI_SR_RXNE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga306a27b203d1275f848f2767d76c9e3b">SPI_SR_RXNE_Pos</a>)</td></tr>
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<tr class="separator:ga85e7198d3d1f577cae637c8295e7691e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40e14de547aa06864abcd4b0422d8b48" id="r_ga40e14de547aa06864abcd4b0422d8b48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40e14de547aa06864abcd4b0422d8b48">SPI_SR_RXNE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga85e7198d3d1f577cae637c8295e7691e">SPI_SR_RXNE_Msk</a></td></tr>
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<tr class="separator:ga40e14de547aa06864abcd4b0422d8b48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92e10388eb117c22b63994b491d9ec9d" id="r_ga92e10388eb117c22b63994b491d9ec9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92e10388eb117c22b63994b491d9ec9d">SPI_SR_TXE_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga92e10388eb117c22b63994b491d9ec9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee9564d438c48424c767347324a2eb03" id="r_gaee9564d438c48424c767347324a2eb03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee9564d438c48424c767347324a2eb03">SPI_SR_TXE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92e10388eb117c22b63994b491d9ec9d">SPI_SR_TXE_Pos</a>)</td></tr>
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<tr class="separator:gaee9564d438c48424c767347324a2eb03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bd5d21816947fcb25ccae7d3bf8eb2c" id="r_ga5bd5d21816947fcb25ccae7d3bf8eb2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bd5d21816947fcb25ccae7d3bf8eb2c">SPI_SR_TXE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaee9564d438c48424c767347324a2eb03">SPI_SR_TXE_Msk</a></td></tr>
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<tr class="separator:ga5bd5d21816947fcb25ccae7d3bf8eb2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5b742da8b06539f6119d020885a6e0c" id="r_gae5b742da8b06539f6119d020885a6e0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5b742da8b06539f6119d020885a6e0c">SPI_SR_CHSIDE_Pos</a>   (2U)</td></tr>
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<tr class="separator:gae5b742da8b06539f6119d020885a6e0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga226666adbdbd46974bcc4a05772bbfc4" id="r_ga226666adbdbd46974bcc4a05772bbfc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga226666adbdbd46974bcc4a05772bbfc4">SPI_SR_CHSIDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5b742da8b06539f6119d020885a6e0c">SPI_SR_CHSIDE_Pos</a>)</td></tr>
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<tr class="separator:ga226666adbdbd46974bcc4a05772bbfc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81bd052f0b2e819ddd6bb16c2292a2de" id="r_ga81bd052f0b2e819ddd6bb16c2292a2de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81bd052f0b2e819ddd6bb16c2292a2de">SPI_SR_CHSIDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga226666adbdbd46974bcc4a05772bbfc4">SPI_SR_CHSIDE_Msk</a></td></tr>
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<tr class="separator:ga81bd052f0b2e819ddd6bb16c2292a2de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93586e3966e74b1df8dbda75e68b26f0" id="r_ga93586e3966e74b1df8dbda75e68b26f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93586e3966e74b1df8dbda75e68b26f0">SPI_SR_UDR_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga93586e3966e74b1df8dbda75e68b26f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ceaae6d492b8b844ff2b83e3251d28e" id="r_ga1ceaae6d492b8b844ff2b83e3251d28e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ceaae6d492b8b844ff2b83e3251d28e">SPI_SR_UDR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga93586e3966e74b1df8dbda75e68b26f0">SPI_SR_UDR_Pos</a>)</td></tr>
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<tr class="separator:ga1ceaae6d492b8b844ff2b83e3251d28e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13d3292e963499c0e9a36869909229e6" id="r_ga13d3292e963499c0e9a36869909229e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13d3292e963499c0e9a36869909229e6">SPI_SR_UDR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ceaae6d492b8b844ff2b83e3251d28e">SPI_SR_UDR_Msk</a></td></tr>
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<tr class="separator:ga13d3292e963499c0e9a36869909229e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga411b6a4aa85d06e425050130f82db35c" id="r_ga411b6a4aa85d06e425050130f82db35c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga411b6a4aa85d06e425050130f82db35c">SPI_SR_CRCERR_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga411b6a4aa85d06e425050130f82db35c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4f508924f9e531136bf0d4fadb68d48" id="r_gad4f508924f9e531136bf0d4fadb68d48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4f508924f9e531136bf0d4fadb68d48">SPI_SR_CRCERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga411b6a4aa85d06e425050130f82db35c">SPI_SR_CRCERR_Pos</a>)</td></tr>
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<tr class="separator:gad4f508924f9e531136bf0d4fadb68d48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69e543fa9584fd636032a3ee735f750b" id="r_ga69e543fa9584fd636032a3ee735f750b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69e543fa9584fd636032a3ee735f750b">SPI_SR_CRCERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad4f508924f9e531136bf0d4fadb68d48">SPI_SR_CRCERR_Msk</a></td></tr>
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<tr class="separator:ga69e543fa9584fd636032a3ee735f750b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb7ef73b03bbd542c54fc4e9c9124e73" id="r_gafb7ef73b03bbd542c54fc4e9c9124e73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb7ef73b03bbd542c54fc4e9c9124e73">SPI_SR_MODF_Pos</a>   (5U)</td></tr>
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<tr class="separator:gafb7ef73b03bbd542c54fc4e9c9124e73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3db9b07f317546b9f724067956b07e9c" id="r_ga3db9b07f317546b9f724067956b07e9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3db9b07f317546b9f724067956b07e9c">SPI_SR_MODF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafb7ef73b03bbd542c54fc4e9c9124e73">SPI_SR_MODF_Pos</a>)</td></tr>
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<tr class="separator:ga3db9b07f317546b9f724067956b07e9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabaa043349833dc7b8138969c64f63adf" id="r_gabaa043349833dc7b8138969c64f63adf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabaa043349833dc7b8138969c64f63adf">SPI_SR_MODF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3db9b07f317546b9f724067956b07e9c">SPI_SR_MODF_Msk</a></td></tr>
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<tr class="separator:gabaa043349833dc7b8138969c64f63adf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6137ac3afbbc8b50c7a998368d2cb9be" id="r_ga6137ac3afbbc8b50c7a998368d2cb9be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6137ac3afbbc8b50c7a998368d2cb9be">SPI_SR_OVR_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga6137ac3afbbc8b50c7a998368d2cb9be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73daf0783ad13468420bbf4d05e150dd" id="r_ga73daf0783ad13468420bbf4d05e150dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73daf0783ad13468420bbf4d05e150dd">SPI_SR_OVR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6137ac3afbbc8b50c7a998368d2cb9be">SPI_SR_OVR_Pos</a>)</td></tr>
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<tr class="separator:ga73daf0783ad13468420bbf4d05e150dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8d902302c5eb81ce4a57029de281232" id="r_gaa8d902302c5eb81ce4a57029de281232"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8d902302c5eb81ce4a57029de281232">SPI_SR_OVR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga73daf0783ad13468420bbf4d05e150dd">SPI_SR_OVR_Msk</a></td></tr>
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<tr class="separator:gaa8d902302c5eb81ce4a57029de281232"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8313629719f8dc81536dd8faa824e6c8" id="r_ga8313629719f8dc81536dd8faa824e6c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8313629719f8dc81536dd8faa824e6c8">SPI_SR_BSY_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga8313629719f8dc81536dd8faa824e6c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcecff7ba1632cf4035a83dd588c4421" id="r_gafcecff7ba1632cf4035a83dd588c4421"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcecff7ba1632cf4035a83dd588c4421">SPI_SR_BSY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8313629719f8dc81536dd8faa824e6c8">SPI_SR_BSY_Pos</a>)</td></tr>
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<tr class="separator:gafcecff7ba1632cf4035a83dd588c4421"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3498df67729ae048dc5f315ef7c16bf" id="r_gaa3498df67729ae048dc5f315ef7c16bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3498df67729ae048dc5f315ef7c16bf">SPI_SR_BSY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafcecff7ba1632cf4035a83dd588c4421">SPI_SR_BSY_Msk</a></td></tr>
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<tr class="separator:gaa3498df67729ae048dc5f315ef7c16bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb0e70677f5775a55044111eb83e1ba6" id="r_gafb0e70677f5775a55044111eb83e1ba6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb0e70677f5775a55044111eb83e1ba6">SPI_SR_FRE_Pos</a>   (8U)</td></tr>
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<tr class="separator:gafb0e70677f5775a55044111eb83e1ba6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd7e467f149f7b4f7c6eb2deb8be5338" id="r_gabd7e467f149f7b4f7c6eb2deb8be5338"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd7e467f149f7b4f7c6eb2deb8be5338">SPI_SR_FRE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafb0e70677f5775a55044111eb83e1ba6">SPI_SR_FRE_Pos</a>)</td></tr>
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<tr class="separator:gabd7e467f149f7b4f7c6eb2deb8be5338"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace2c7cac9431231663af42e6f5aabce6" id="r_gace2c7cac9431231663af42e6f5aabce6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace2c7cac9431231663af42e6f5aabce6">SPI_SR_FRE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd7e467f149f7b4f7c6eb2deb8be5338">SPI_SR_FRE_Msk</a></td></tr>
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<tr class="separator:gace2c7cac9431231663af42e6f5aabce6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b57ca6bca45cfdaed4a26fefc0da85f" id="r_ga5b57ca6bca45cfdaed4a26fefc0da85f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b57ca6bca45cfdaed4a26fefc0da85f">SPI_DR_DR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5b57ca6bca45cfdaed4a26fefc0da85f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf50021b52352481a497f21c72c33e966" id="r_gaf50021b52352481a497f21c72c33e966"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf50021b52352481a497f21c72c33e966">SPI_DR_DR_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b57ca6bca45cfdaed4a26fefc0da85f">SPI_DR_DR_Pos</a>)</td></tr>
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<tr class="separator:gaf50021b52352481a497f21c72c33e966"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4da7d7f05a28d1aaa52ec557e55e1ad" id="r_gaa4da7d7f05a28d1aaa52ec557e55e1ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4da7d7f05a28d1aaa52ec557e55e1ad">SPI_DR_DR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf50021b52352481a497f21c72c33e966">SPI_DR_DR_Msk</a></td></tr>
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<tr class="separator:gaa4da7d7f05a28d1aaa52ec557e55e1ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0244eb48f4c5158b03dd4b26cc0d2eac" id="r_ga0244eb48f4c5158b03dd4b26cc0d2eac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0244eb48f4c5158b03dd4b26cc0d2eac">SPI_CRCPR_CRCPOLY_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0244eb48f4c5158b03dd4b26cc0d2eac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67c234978a817dee4fc561201b3ef056" id="r_ga67c234978a817dee4fc561201b3ef056"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67c234978a817dee4fc561201b3ef056">SPI_CRCPR_CRCPOLY_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0244eb48f4c5158b03dd4b26cc0d2eac">SPI_CRCPR_CRCPOLY_Pos</a>)</td></tr>
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<tr class="separator:ga67c234978a817dee4fc561201b3ef056"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae968658ab837800723eafcc21af10247" id="r_gae968658ab837800723eafcc21af10247"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae968658ab837800723eafcc21af10247">SPI_CRCPR_CRCPOLY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67c234978a817dee4fc561201b3ef056">SPI_CRCPR_CRCPOLY_Msk</a></td></tr>
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<tr class="separator:gae968658ab837800723eafcc21af10247"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b80d92a2b51c4c61d5a646ac2b36129" id="r_ga2b80d92a2b51c4c61d5a646ac2b36129"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b80d92a2b51c4c61d5a646ac2b36129">SPI_RXCRCR_RXCRC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2b80d92a2b51c4c61d5a646ac2b36129"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3318f05b5d1bebf96434ae4bc88e46da" id="r_ga3318f05b5d1bebf96434ae4bc88e46da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3318f05b5d1bebf96434ae4bc88e46da">SPI_RXCRCR_RXCRC_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b80d92a2b51c4c61d5a646ac2b36129">SPI_RXCRCR_RXCRC_Pos</a>)</td></tr>
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<tr class="separator:ga3318f05b5d1bebf96434ae4bc88e46da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a01a578c2c7bb4e587a8f1610843181" id="r_ga3a01a578c2c7bb4e587a8f1610843181"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a01a578c2c7bb4e587a8f1610843181">SPI_RXCRCR_RXCRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3318f05b5d1bebf96434ae4bc88e46da">SPI_RXCRCR_RXCRC_Msk</a></td></tr>
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<tr class="separator:ga3a01a578c2c7bb4e587a8f1610843181"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a0e6e24778c36e45838350d052916d1" id="r_ga0a0e6e24778c36e45838350d052916d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a0e6e24778c36e45838350d052916d1">SPI_TXCRCR_TXCRC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0a0e6e24778c36e45838350d052916d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca1f646ca0bb6ae44744956b39b0702d" id="r_gaca1f646ca0bb6ae44744956b39b0702d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca1f646ca0bb6ae44744956b39b0702d">SPI_TXCRCR_TXCRC_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a0e6e24778c36e45838350d052916d1">SPI_TXCRCR_TXCRC_Pos</a>)</td></tr>
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<tr class="separator:gaca1f646ca0bb6ae44744956b39b0702d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c69dc721e89e40056999b64572dff09" id="r_ga1c69dc721e89e40056999b64572dff09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c69dc721e89e40056999b64572dff09">SPI_TXCRCR_TXCRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaca1f646ca0bb6ae44744956b39b0702d">SPI_TXCRCR_TXCRC_Msk</a></td></tr>
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<tr class="separator:ga1c69dc721e89e40056999b64572dff09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ea301a1a44423c53d2d388a9c7677bd" id="r_ga7ea301a1a44423c53d2d388a9c7677bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ea301a1a44423c53d2d388a9c7677bd">SPI_I2SCFGR_CHLEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7ea301a1a44423c53d2d388a9c7677bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a842b52587ad0e434153bf9df2ecc50" id="r_ga7a842b52587ad0e434153bf9df2ecc50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a842b52587ad0e434153bf9df2ecc50">SPI_I2SCFGR_CHLEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ea301a1a44423c53d2d388a9c7677bd">SPI_I2SCFGR_CHLEN_Pos</a>)</td></tr>
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<tr class="separator:ga7a842b52587ad0e434153bf9df2ecc50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c362b3d703698a7891f032f6b29056f" id="r_ga9c362b3d703698a7891f032f6b29056f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c362b3d703698a7891f032f6b29056f">SPI_I2SCFGR_CHLEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a842b52587ad0e434153bf9df2ecc50">SPI_I2SCFGR_CHLEN_Msk</a></td></tr>
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<tr class="separator:ga9c362b3d703698a7891f032f6b29056f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a60bd1db55a2dfcf20a834e9ad05a66" id="r_ga5a60bd1db55a2dfcf20a834e9ad05a66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a60bd1db55a2dfcf20a834e9ad05a66">SPI_I2SCFGR_DATLEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga5a60bd1db55a2dfcf20a834e9ad05a66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabbffb30650c0d4c84232813213271169" id="r_gabbffb30650c0d4c84232813213271169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbffb30650c0d4c84232813213271169">SPI_I2SCFGR_DATLEN_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a60bd1db55a2dfcf20a834e9ad05a66">SPI_I2SCFGR_DATLEN_Pos</a>)</td></tr>
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<tr class="separator:gabbffb30650c0d4c84232813213271169"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc12f9d2003ab169a3f68e9d809f84ae" id="r_gacc12f9d2003ab169a3f68e9d809f84ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc12f9d2003ab169a3f68e9d809f84ae">SPI_I2SCFGR_DATLEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabbffb30650c0d4c84232813213271169">SPI_I2SCFGR_DATLEN_Msk</a></td></tr>
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<tr class="separator:gacc12f9d2003ab169a3f68e9d809f84ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa20ad624085d2e533eea3662cb03d8fa" id="r_gaa20ad624085d2e533eea3662cb03d8fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa20ad624085d2e533eea3662cb03d8fa">SPI_I2SCFGR_DATLEN_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a60bd1db55a2dfcf20a834e9ad05a66">SPI_I2SCFGR_DATLEN_Pos</a>)</td></tr>
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<tr class="separator:gaa20ad624085d2e533eea3662cb03d8fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf6e940d195fa1633cb1b23414f00412" id="r_gadf6e940d195fa1633cb1b23414f00412"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf6e940d195fa1633cb1b23414f00412">SPI_I2SCFGR_DATLEN_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a60bd1db55a2dfcf20a834e9ad05a66">SPI_I2SCFGR_DATLEN_Pos</a>)</td></tr>
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<tr class="separator:gadf6e940d195fa1633cb1b23414f00412"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bf83ceaefcb4190b2fb5ae09f659d8d" id="r_ga2bf83ceaefcb4190b2fb5ae09f659d8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf83ceaefcb4190b2fb5ae09f659d8d">SPI_I2SCFGR_CKPOL_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga2bf83ceaefcb4190b2fb5ae09f659d8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b3b7c3f4fc9a499410bff94553534f5" id="r_ga7b3b7c3f4fc9a499410bff94553534f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b3b7c3f4fc9a499410bff94553534f5">SPI_I2SCFGR_CKPOL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf83ceaefcb4190b2fb5ae09f659d8d">SPI_I2SCFGR_CKPOL_Pos</a>)</td></tr>
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<tr class="separator:ga7b3b7c3f4fc9a499410bff94553534f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c5be1f1c8b4689643e04cd5034e7f5f" id="r_ga5c5be1f1c8b4689643e04cd5034e7f5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c5be1f1c8b4689643e04cd5034e7f5f">SPI_I2SCFGR_CKPOL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b3b7c3f4fc9a499410bff94553534f5">SPI_I2SCFGR_CKPOL_Msk</a></td></tr>
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<tr class="separator:ga5c5be1f1c8b4689643e04cd5034e7f5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d794bb7f4327025db354ad26bf83986" id="r_ga8d794bb7f4327025db354ad26bf83986"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d794bb7f4327025db354ad26bf83986">SPI_I2SCFGR_I2SSTD_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga8d794bb7f4327025db354ad26bf83986"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff08fac3bb90bd73b0bdadddb6a1411a" id="r_gaff08fac3bb90bd73b0bdadddb6a1411a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff08fac3bb90bd73b0bdadddb6a1411a">SPI_I2SCFGR_I2SSTD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d794bb7f4327025db354ad26bf83986">SPI_I2SCFGR_I2SSTD_Pos</a>)</td></tr>
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<tr class="separator:gaff08fac3bb90bd73b0bdadddb6a1411a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a822a80be3a51524b42491248f8031f" id="r_ga7a822a80be3a51524b42491248f8031f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a822a80be3a51524b42491248f8031f">SPI_I2SCFGR_I2SSTD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaff08fac3bb90bd73b0bdadddb6a1411a">SPI_I2SCFGR_I2SSTD_Msk</a></td></tr>
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<tr class="separator:ga7a822a80be3a51524b42491248f8031f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafeba0a45703463dfe05334364bdacbe8" id="r_gafeba0a45703463dfe05334364bdacbe8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafeba0a45703463dfe05334364bdacbe8">SPI_I2SCFGR_I2SSTD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d794bb7f4327025db354ad26bf83986">SPI_I2SCFGR_I2SSTD_Pos</a>)</td></tr>
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<tr class="separator:gafeba0a45703463dfe05334364bdacbe8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0142a3667f59bce9bae80d31e88a124a" id="r_ga0142a3667f59bce9bae80d31e88a124a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0142a3667f59bce9bae80d31e88a124a">SPI_I2SCFGR_I2SSTD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d794bb7f4327025db354ad26bf83986">SPI_I2SCFGR_I2SSTD_Pos</a>)</td></tr>
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<tr class="separator:ga0142a3667f59bce9bae80d31e88a124a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf486d8ce50abc465f372b6fcc7a0704d" id="r_gaf486d8ce50abc465f372b6fcc7a0704d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf486d8ce50abc465f372b6fcc7a0704d">SPI_I2SCFGR_PCMSYNC_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaf486d8ce50abc465f372b6fcc7a0704d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeecf52a47dc8d82d6e3d3951c51f4dc1" id="r_gaeecf52a47dc8d82d6e3d3951c51f4dc1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeecf52a47dc8d82d6e3d3951c51f4dc1">SPI_I2SCFGR_PCMSYNC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf486d8ce50abc465f372b6fcc7a0704d">SPI_I2SCFGR_PCMSYNC_Pos</a>)</td></tr>
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<tr class="separator:gaeecf52a47dc8d82d6e3d3951c51f4dc1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66a29efc32a31f903e89b7ddcd20857b" id="r_ga66a29efc32a31f903e89b7ddcd20857b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66a29efc32a31f903e89b7ddcd20857b">SPI_I2SCFGR_PCMSYNC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeecf52a47dc8d82d6e3d3951c51f4dc1">SPI_I2SCFGR_PCMSYNC_Msk</a></td></tr>
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<tr class="separator:ga66a29efc32a31f903e89b7ddcd20857b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c7f5184bc8db838c594b07965e81619" id="r_ga7c7f5184bc8db838c594b07965e81619"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c7f5184bc8db838c594b07965e81619">SPI_I2SCFGR_I2SCFG_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga7c7f5184bc8db838c594b07965e81619"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3ca3fbea0bb2c306c0d7f4bcaee8b0d" id="r_gac3ca3fbea0bb2c306c0d7f4bcaee8b0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3ca3fbea0bb2c306c0d7f4bcaee8b0d">SPI_I2SCFGR_I2SCFG_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c7f5184bc8db838c594b07965e81619">SPI_I2SCFGR_I2SCFG_Pos</a>)</td></tr>
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<tr class="separator:gac3ca3fbea0bb2c306c0d7f4bcaee8b0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf09fd11f6f97000266b30b015bf2cb68" id="r_gaf09fd11f6f97000266b30b015bf2cb68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf09fd11f6f97000266b30b015bf2cb68">SPI_I2SCFGR_I2SCFG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac3ca3fbea0bb2c306c0d7f4bcaee8b0d">SPI_I2SCFGR_I2SCFG_Msk</a></td></tr>
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<tr class="separator:gaf09fd11f6f97000266b30b015bf2cb68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga421c94680ee8a2583419e2b0c89e995e" id="r_ga421c94680ee8a2583419e2b0c89e995e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga421c94680ee8a2583419e2b0c89e995e">SPI_I2SCFGR_I2SCFG_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c7f5184bc8db838c594b07965e81619">SPI_I2SCFGR_I2SCFG_Pos</a>)</td></tr>
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<tr class="separator:ga421c94680ee8a2583419e2b0c89e995e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80c398b9e79fcc61a497f9d7dd910352" id="r_ga80c398b9e79fcc61a497f9d7dd910352"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80c398b9e79fcc61a497f9d7dd910352">SPI_I2SCFGR_I2SCFG_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c7f5184bc8db838c594b07965e81619">SPI_I2SCFGR_I2SCFG_Pos</a>)</td></tr>
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<tr class="separator:ga80c398b9e79fcc61a497f9d7dd910352"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga967de848b594a623b10019d912266ed3" id="r_ga967de848b594a623b10019d912266ed3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga967de848b594a623b10019d912266ed3">SPI_I2SCFGR_I2SE_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga967de848b594a623b10019d912266ed3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafefdd032e0fcf3d4d73f5bf167f74c6b" id="r_gafefdd032e0fcf3d4d73f5bf167f74c6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafefdd032e0fcf3d4d73f5bf167f74c6b">SPI_I2SCFGR_I2SE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga967de848b594a623b10019d912266ed3">SPI_I2SCFGR_I2SE_Pos</a>)</td></tr>
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<tr class="separator:gafefdd032e0fcf3d4d73f5bf167f74c6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30d76c7552c91bbd5cbac70d9c56ebb3" id="r_ga30d76c7552c91bbd5cbac70d9c56ebb3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30d76c7552c91bbd5cbac70d9c56ebb3">SPI_I2SCFGR_I2SE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafefdd032e0fcf3d4d73f5bf167f74c6b">SPI_I2SCFGR_I2SE_Msk</a></td></tr>
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<tr class="separator:ga30d76c7552c91bbd5cbac70d9c56ebb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga443830d47e0ebc5e0141dad4a7d43978" id="r_ga443830d47e0ebc5e0141dad4a7d43978"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga443830d47e0ebc5e0141dad4a7d43978">SPI_I2SCFGR_I2SMOD_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga443830d47e0ebc5e0141dad4a7d43978"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa67cab1dd9189de25a0aec2cce90479a" id="r_gaa67cab1dd9189de25a0aec2cce90479a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa67cab1dd9189de25a0aec2cce90479a">SPI_I2SCFGR_I2SMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga443830d47e0ebc5e0141dad4a7d43978">SPI_I2SCFGR_I2SMOD_Pos</a>)</td></tr>
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<tr class="separator:gaa67cab1dd9189de25a0aec2cce90479a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae99763414b3c2f11fcfecb1f93eb6701" id="r_gae99763414b3c2f11fcfecb1f93eb6701"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae99763414b3c2f11fcfecb1f93eb6701">SPI_I2SCFGR_I2SMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa67cab1dd9189de25a0aec2cce90479a">SPI_I2SCFGR_I2SMOD_Msk</a></td></tr>
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<tr class="separator:gae99763414b3c2f11fcfecb1f93eb6701"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab840a9d53e7de5f0de74d20d5e11e0fa" id="r_gab840a9d53e7de5f0de74d20d5e11e0fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab840a9d53e7de5f0de74d20d5e11e0fa">SPI_I2SPR_I2SDIV_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab840a9d53e7de5f0de74d20d5e11e0fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ae53c9d1c862f377fb76fb253324ac4" id="r_ga1ae53c9d1c862f377fb76fb253324ac4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ae53c9d1c862f377fb76fb253324ac4">SPI_I2SPR_I2SDIV_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab840a9d53e7de5f0de74d20d5e11e0fa">SPI_I2SPR_I2SDIV_Pos</a>)</td></tr>
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<tr class="separator:ga1ae53c9d1c862f377fb76fb253324ac4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga406ce88b2580a421f5b28bdbeb303543" id="r_ga406ce88b2580a421f5b28bdbeb303543"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga406ce88b2580a421f5b28bdbeb303543">SPI_I2SPR_I2SDIV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ae53c9d1c862f377fb76fb253324ac4">SPI_I2SPR_I2SDIV_Msk</a></td></tr>
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<tr class="separator:ga406ce88b2580a421f5b28bdbeb303543"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabfb7274ed8833e66663a995ca074c1d9" id="r_gabfb7274ed8833e66663a995ca074c1d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfb7274ed8833e66663a995ca074c1d9">SPI_I2SPR_ODD_Pos</a>   (8U)</td></tr>
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<tr class="separator:gabfb7274ed8833e66663a995ca074c1d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8892fa60c17ea6a9a645671d4d6ffdc" id="r_gad8892fa60c17ea6a9a645671d4d6ffdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8892fa60c17ea6a9a645671d4d6ffdc">SPI_I2SPR_ODD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabfb7274ed8833e66663a995ca074c1d9">SPI_I2SPR_ODD_Pos</a>)</td></tr>
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<tr class="separator:gad8892fa60c17ea6a9a645671d4d6ffdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d6d4136a5ae12f9bd5940324282355a" id="r_ga3d6d4136a5ae12f9bd5940324282355a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d6d4136a5ae12f9bd5940324282355a">SPI_I2SPR_ODD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad8892fa60c17ea6a9a645671d4d6ffdc">SPI_I2SPR_ODD_Msk</a></td></tr>
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<tr class="separator:ga3d6d4136a5ae12f9bd5940324282355a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1219b3f0097930dd635f434a019d38c6" id="r_ga1219b3f0097930dd635f434a019d38c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1219b3f0097930dd635f434a019d38c6">SPI_I2SPR_MCKOE_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga1219b3f0097930dd635f434a019d38c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa466ff1b4340cc07fd6362f7bfb173f4" id="r_gaa466ff1b4340cc07fd6362f7bfb173f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa466ff1b4340cc07fd6362f7bfb173f4">SPI_I2SPR_MCKOE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1219b3f0097930dd635f434a019d38c6">SPI_I2SPR_MCKOE_Pos</a>)</td></tr>
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<tr class="separator:gaa466ff1b4340cc07fd6362f7bfb173f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25669c3686c0c577d2d371ac09200ff0" id="r_ga25669c3686c0c577d2d371ac09200ff0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25669c3686c0c577d2d371ac09200ff0">SPI_I2SPR_MCKOE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa466ff1b4340cc07fd6362f7bfb173f4">SPI_I2SPR_MCKOE_Msk</a></td></tr>
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<tr class="separator:ga25669c3686c0c577d2d371ac09200ff0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20a445ef41a942b3ec617cfce8297931" id="r_ga20a445ef41a942b3ec617cfce8297931"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20a445ef41a942b3ec617cfce8297931">SYSCFG_MEMRMP_MEM_MODE_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga20a445ef41a942b3ec617cfce8297931"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1309dcedba4fee11e085cdfaf974cc3d" id="r_ga1309dcedba4fee11e085cdfaf974cc3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1309dcedba4fee11e085cdfaf974cc3d">SYSCFG_MEMRMP_MEM_MODE_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20a445ef41a942b3ec617cfce8297931">SYSCFG_MEMRMP_MEM_MODE_Pos</a>)</td></tr>
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<tr class="separator:ga1309dcedba4fee11e085cdfaf974cc3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c05039ec67573c00da29f58b914f258" id="r_ga3c05039ec67573c00da29f58b914f258"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c05039ec67573c00da29f58b914f258">SYSCFG_MEMRMP_MEM_MODE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1309dcedba4fee11e085cdfaf974cc3d">SYSCFG_MEMRMP_MEM_MODE_Msk</a></td></tr>
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<tr class="separator:ga3c05039ec67573c00da29f58b914f258"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30d5f406535f94faea2e7f924d50201b" id="r_ga30d5f406535f94faea2e7f924d50201b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30d5f406535f94faea2e7f924d50201b">SYSCFG_MEMRMP_MEM_MODE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20a445ef41a942b3ec617cfce8297931">SYSCFG_MEMRMP_MEM_MODE_Pos</a>)</td></tr>
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<tr class="separator:ga30d5f406535f94faea2e7f924d50201b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5d76e8b4d801b35c31ef352b33407be" id="r_gab5d76e8b4d801b35c31ef352b33407be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5d76e8b4d801b35c31ef352b33407be">SYSCFG_MEMRMP_MEM_MODE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20a445ef41a942b3ec617cfce8297931">SYSCFG_MEMRMP_MEM_MODE_Pos</a>)</td></tr>
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<tr class="separator:gab5d76e8b4d801b35c31ef352b33407be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f2f7440818b83b95e29d526516e8d27" id="r_ga1f2f7440818b83b95e29d526516e8d27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f2f7440818b83b95e29d526516e8d27">SYSCFG_PMC_MII_RMII_SEL_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga1f2f7440818b83b95e29d526516e8d27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf63c23642e3d3c0f1a2c67f6a60957e1" id="r_gaf63c23642e3d3c0f1a2c67f6a60957e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf63c23642e3d3c0f1a2c67f6a60957e1">SYSCFG_PMC_MII_RMII_SEL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f2f7440818b83b95e29d526516e8d27">SYSCFG_PMC_MII_RMII_SEL_Pos</a>)</td></tr>
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<tr class="separator:gaf63c23642e3d3c0f1a2c67f6a60957e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9d8ca35cdab213cb2400c49434de326" id="r_gae9d8ca35cdab213cb2400c49434de326"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9d8ca35cdab213cb2400c49434de326">SYSCFG_PMC_MII_RMII_SEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf63c23642e3d3c0f1a2c67f6a60957e1">SYSCFG_PMC_MII_RMII_SEL_Msk</a></td></tr>
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<tr class="separator:gae9d8ca35cdab213cb2400c49434de326"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf7af9191fbf95433bc0a76454118ce9" id="r_gaaf7af9191fbf95433bc0a76454118ce9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf7af9191fbf95433bc0a76454118ce9">SYSCFG_PMC_MII_RMII</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae9d8ca35cdab213cb2400c49434de326">SYSCFG_PMC_MII_RMII_SEL</a></td></tr>
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<tr class="separator:gaaf7af9191fbf95433bc0a76454118ce9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae40db3f75cc81dcb1b6b8c18194d07a8" id="r_gae40db3f75cc81dcb1b6b8c18194d07a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae40db3f75cc81dcb1b6b8c18194d07a8">SYSCFG_EXTICR1_EXTI0_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae40db3f75cc81dcb1b6b8c18194d07a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c2b219e4d77fac522233905dc0d8de8" id="r_ga7c2b219e4d77fac522233905dc0d8de8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c2b219e4d77fac522233905dc0d8de8">SYSCFG_EXTICR1_EXTI0_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae40db3f75cc81dcb1b6b8c18194d07a8">SYSCFG_EXTICR1_EXTI0_Pos</a>)</td></tr>
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<tr class="separator:ga7c2b219e4d77fac522233905dc0d8de8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75b70d07448c3037234bc2abb8e3d884" id="r_ga75b70d07448c3037234bc2abb8e3d884"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75b70d07448c3037234bc2abb8e3d884">SYSCFG_EXTICR1_EXTI0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c2b219e4d77fac522233905dc0d8de8">SYSCFG_EXTICR1_EXTI0_Msk</a></td></tr>
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<tr class="separator:ga75b70d07448c3037234bc2abb8e3d884"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e187825ececb74bc0dc9bb16a22e8af" id="r_ga1e187825ececb74bc0dc9bb16a22e8af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e187825ececb74bc0dc9bb16a22e8af">SYSCFG_EXTICR1_EXTI1_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga1e187825ececb74bc0dc9bb16a22e8af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac033e65cf79968349e0fa5e52ebf4ccd" id="r_gac033e65cf79968349e0fa5e52ebf4ccd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac033e65cf79968349e0fa5e52ebf4ccd">SYSCFG_EXTICR1_EXTI1_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e187825ececb74bc0dc9bb16a22e8af">SYSCFG_EXTICR1_EXTI1_Pos</a>)</td></tr>
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<tr class="separator:gac033e65cf79968349e0fa5e52ebf4ccd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7fc84838c77f799cb7e57d6e97c6c16d" id="r_ga7fc84838c77f799cb7e57d6e97c6c16d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fc84838c77f799cb7e57d6e97c6c16d">SYSCFG_EXTICR1_EXTI1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac033e65cf79968349e0fa5e52ebf4ccd">SYSCFG_EXTICR1_EXTI1_Msk</a></td></tr>
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<tr class="separator:ga7fc84838c77f799cb7e57d6e97c6c16d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga283584ecd69e2dfd310b2b09d1028457" id="r_ga283584ecd69e2dfd310b2b09d1028457"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga283584ecd69e2dfd310b2b09d1028457">SYSCFG_EXTICR1_EXTI2_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga283584ecd69e2dfd310b2b09d1028457"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1383ce11441c048c62e317e78eff0545" id="r_ga1383ce11441c048c62e317e78eff0545"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1383ce11441c048c62e317e78eff0545">SYSCFG_EXTICR1_EXTI2_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga283584ecd69e2dfd310b2b09d1028457">SYSCFG_EXTICR1_EXTI2_Pos</a>)</td></tr>
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<tr class="separator:ga1383ce11441c048c62e317e78eff0545"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d0a0a6b8223777937d8c9012658d6cd" id="r_ga6d0a0a6b8223777937d8c9012658d6cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d0a0a6b8223777937d8c9012658d6cd">SYSCFG_EXTICR1_EXTI2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1383ce11441c048c62e317e78eff0545">SYSCFG_EXTICR1_EXTI2_Msk</a></td></tr>
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<tr class="separator:ga6d0a0a6b8223777937d8c9012658d6cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08a505d92a83c5fc8d5d0c8202119f61" id="r_ga08a505d92a83c5fc8d5d0c8202119f61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08a505d92a83c5fc8d5d0c8202119f61">SYSCFG_EXTICR1_EXTI3_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga08a505d92a83c5fc8d5d0c8202119f61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90072fd2defc44f0975836484c9d9bbf" id="r_ga90072fd2defc44f0975836484c9d9bbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90072fd2defc44f0975836484c9d9bbf">SYSCFG_EXTICR1_EXTI3_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga08a505d92a83c5fc8d5d0c8202119f61">SYSCFG_EXTICR1_EXTI3_Pos</a>)</td></tr>
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<tr class="separator:ga90072fd2defc44f0975836484c9d9bbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3bf2306f79ebb709da5ecf83e59ded4" id="r_gac3bf2306f79ebb709da5ecf83e59ded4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3bf2306f79ebb709da5ecf83e59ded4">SYSCFG_EXTICR1_EXTI3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga90072fd2defc44f0975836484c9d9bbf">SYSCFG_EXTICR1_EXTI3_Msk</a></td></tr>
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<tr class="separator:gac3bf2306f79ebb709da5ecf83e59ded4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6de6aa8e32ae5cd07fd69e42e7226bd1" id="r_ga6de6aa8e32ae5cd07fd69e42e7226bd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6de6aa8e32ae5cd07fd69e42e7226bd1">SYSCFG_EXTICR1_EXTI0_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga6de6aa8e32ae5cd07fd69e42e7226bd1"><td class="mdescLeft"> </td><td class="mdescRight">EXTI0 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga6de6aa8e32ae5cd07fd69e42e7226bd1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf43c9ef6b61e39655cbe969967c79a69" id="r_gaf43c9ef6b61e39655cbe969967c79a69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf43c9ef6b61e39655cbe969967c79a69">SYSCFG_EXTICR1_EXTI0_PB</a>   0x0001U</td></tr>
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<tr class="separator:gaf43c9ef6b61e39655cbe969967c79a69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga861a4d7b48ffd93997267baaad12fd51" id="r_ga861a4d7b48ffd93997267baaad12fd51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga861a4d7b48ffd93997267baaad12fd51">SYSCFG_EXTICR1_EXTI0_PC</a>   0x0002U</td></tr>
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<tr class="separator:ga861a4d7b48ffd93997267baaad12fd51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6439042c8cd14f99fe3813cff47c0ee" id="r_gaf6439042c8cd14f99fe3813cff47c0ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6439042c8cd14f99fe3813cff47c0ee">SYSCFG_EXTICR1_EXTI0_PD</a>   0x0003U</td></tr>
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<tr class="separator:gaf6439042c8cd14f99fe3813cff47c0ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb087e2ded8ac927ee9e1fc0234bfdef" id="r_gacb087e2ded8ac927ee9e1fc0234bfdef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb087e2ded8ac927ee9e1fc0234bfdef">SYSCFG_EXTICR1_EXTI0_PE</a>   0x0004U</td></tr>
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<tr class="separator:gacb087e2ded8ac927ee9e1fc0234bfdef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa897f1ac8311e57339eaf7813239eaf4" id="r_gaa897f1ac8311e57339eaf7813239eaf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa897f1ac8311e57339eaf7813239eaf4">SYSCFG_EXTICR1_EXTI0_PF</a>   0x0005U</td></tr>
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<tr class="separator:gaa897f1ac8311e57339eaf7813239eaf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98b2d929e79e5cc2ee7961a75a0ab094" id="r_ga98b2d929e79e5cc2ee7961a75a0ab094"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98b2d929e79e5cc2ee7961a75a0ab094">SYSCFG_EXTICR1_EXTI0_PG</a>   0x0006U</td></tr>
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<tr class="separator:ga98b2d929e79e5cc2ee7961a75a0ab094"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga766d0bf3501e207b0baa066cf756688f" id="r_ga766d0bf3501e207b0baa066cf756688f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga766d0bf3501e207b0baa066cf756688f">SYSCFG_EXTICR1_EXTI0_PH</a>   0x0007U</td></tr>
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<tr class="separator:ga766d0bf3501e207b0baa066cf756688f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfc4b69ff5f5d9b35bf01f26d6aa4e60" id="r_gacfc4b69ff5f5d9b35bf01f26d6aa4e60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfc4b69ff5f5d9b35bf01f26d6aa4e60">SYSCFG_EXTICR1_EXTI0_PI</a>   0x0008U</td></tr>
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<tr class="separator:gacfc4b69ff5f5d9b35bf01f26d6aa4e60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4b78c30e4ef4fa441582eb3c102865d" id="r_gaf4b78c30e4ef4fa441582eb3c102865d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4b78c30e4ef4fa441582eb3c102865d">SYSCFG_EXTICR1_EXTI1_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:gaf4b78c30e4ef4fa441582eb3c102865d"><td class="mdescLeft"> </td><td class="mdescRight">EXTI1 configuration <br />
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<br /></td></tr>
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<tr class="separator:gaf4b78c30e4ef4fa441582eb3c102865d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19a11fce288d19546c76257483e0dcb6" id="r_ga19a11fce288d19546c76257483e0dcb6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19a11fce288d19546c76257483e0dcb6">SYSCFG_EXTICR1_EXTI1_PB</a>   0x0010U</td></tr>
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<tr class="separator:ga19a11fce288d19546c76257483e0dcb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae45a8c814b13fa19f157364dc715c08a" id="r_gae45a8c814b13fa19f157364dc715c08a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae45a8c814b13fa19f157364dc715c08a">SYSCFG_EXTICR1_EXTI1_PC</a>   0x0020U</td></tr>
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<tr class="separator:gae45a8c814b13fa19f157364dc715c08a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93cb136eaf357affc4a28a8d423cabbb" id="r_ga93cb136eaf357affc4a28a8d423cabbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93cb136eaf357affc4a28a8d423cabbb">SYSCFG_EXTICR1_EXTI1_PD</a>   0x0030U</td></tr>
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<tr class="separator:ga93cb136eaf357affc4a28a8d423cabbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f5c3d1e914af78112179a13e9c736d6" id="r_ga8f5c3d1e914af78112179a13e9c736d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f5c3d1e914af78112179a13e9c736d6">SYSCFG_EXTICR1_EXTI1_PE</a>   0x0040U</td></tr>
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<tr class="separator:ga8f5c3d1e914af78112179a13e9c736d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43ea410456aa31dfe6ec4889de62428b" id="r_ga43ea410456aa31dfe6ec4889de62428b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43ea410456aa31dfe6ec4889de62428b">SYSCFG_EXTICR1_EXTI1_PF</a>   0x0050U</td></tr>
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<tr class="separator:ga43ea410456aa31dfe6ec4889de62428b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9118efcafa89eeada012ff5ab98387d" id="r_gaf9118efcafa89eeada012ff5ab98387d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9118efcafa89eeada012ff5ab98387d">SYSCFG_EXTICR1_EXTI1_PG</a>   0x0060U</td></tr>
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<tr class="separator:gaf9118efcafa89eeada012ff5ab98387d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ac69d7f391e837d8e8adce27704d87d" id="r_ga0ac69d7f391e837d8e8adce27704d87d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ac69d7f391e837d8e8adce27704d87d">SYSCFG_EXTICR1_EXTI1_PH</a>   0x0070U</td></tr>
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<tr class="separator:ga0ac69d7f391e837d8e8adce27704d87d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga010784c7bdee3c742b48c500ee52e223" id="r_ga010784c7bdee3c742b48c500ee52e223"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga010784c7bdee3c742b48c500ee52e223">SYSCFG_EXTICR1_EXTI1_PI</a>   0x0080U</td></tr>
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<tr class="separator:ga010784c7bdee3c742b48c500ee52e223"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4096f472e87e021f4d4c94457ddaf5f1" id="r_ga4096f472e87e021f4d4c94457ddaf5f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4096f472e87e021f4d4c94457ddaf5f1">SYSCFG_EXTICR1_EXTI2_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga4096f472e87e021f4d4c94457ddaf5f1"><td class="mdescLeft"> </td><td class="mdescRight">EXTI2 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga4096f472e87e021f4d4c94457ddaf5f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cd240d61fd8a9666621f0dee07a08e5" id="r_ga8cd240d61fd8a9666621f0dee07a08e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cd240d61fd8a9666621f0dee07a08e5">SYSCFG_EXTICR1_EXTI2_PB</a>   0x0100U</td></tr>
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<tr class="separator:ga8cd240d61fd8a9666621f0dee07a08e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03ce7faaf56aa9efcc74af65619e275e" id="r_ga03ce7faaf56aa9efcc74af65619e275e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03ce7faaf56aa9efcc74af65619e275e">SYSCFG_EXTICR1_EXTI2_PC</a>   0x0200U</td></tr>
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<tr class="separator:ga03ce7faaf56aa9efcc74af65619e275e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc35fcdcc89b487fab2901e1f5a7f41b" id="r_gafc35fcdcc89b487fab2901e1f5a7f41b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc35fcdcc89b487fab2901e1f5a7f41b">SYSCFG_EXTICR1_EXTI2_PD</a>   0x0300U</td></tr>
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<tr class="separator:gafc35fcdcc89b487fab2901e1f5a7f41b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3f2b7465d81745f7a772e7689a29618" id="r_gac3f2b7465d81745f7a772e7689a29618"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3f2b7465d81745f7a772e7689a29618">SYSCFG_EXTICR1_EXTI2_PE</a>   0x0400U</td></tr>
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<tr class="separator:gac3f2b7465d81745f7a772e7689a29618"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab538769f1da056b3f57fb984adeef252" id="r_gab538769f1da056b3f57fb984adeef252"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab538769f1da056b3f57fb984adeef252">SYSCFG_EXTICR1_EXTI2_PF</a>   0x0500U</td></tr>
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<tr class="separator:gab538769f1da056b3f57fb984adeef252"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe4f5fa56e98b42b64e894f7a9216e05" id="r_gabe4f5fa56e98b42b64e894f7a9216e05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe4f5fa56e98b42b64e894f7a9216e05">SYSCFG_EXTICR1_EXTI2_PG</a>   0x0600U</td></tr>
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<tr class="separator:gabe4f5fa56e98b42b64e894f7a9216e05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada5ffab92c39cbfc695ce57a4e6177e5" id="r_gada5ffab92c39cbfc695ce57a4e6177e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada5ffab92c39cbfc695ce57a4e6177e5">SYSCFG_EXTICR1_EXTI2_PH</a>   0x0700U</td></tr>
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<tr class="separator:gada5ffab92c39cbfc695ce57a4e6177e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00bc1224b7bfd46dcec32676a601de51" id="r_ga00bc1224b7bfd46dcec32676a601de51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00bc1224b7bfd46dcec32676a601de51">SYSCFG_EXTICR1_EXTI2_PI</a>   0x0800U</td></tr>
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<tr class="separator:ga00bc1224b7bfd46dcec32676a601de51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45ed24773c389f4477944c2c43d106c0" id="r_ga45ed24773c389f4477944c2c43d106c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45ed24773c389f4477944c2c43d106c0">SYSCFG_EXTICR1_EXTI3_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga45ed24773c389f4477944c2c43d106c0"><td class="mdescLeft"> </td><td class="mdescRight">EXTI3 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga45ed24773c389f4477944c2c43d106c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga652183838bb096717551bf8a1917c257" id="r_ga652183838bb096717551bf8a1917c257"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga652183838bb096717551bf8a1917c257">SYSCFG_EXTICR1_EXTI3_PB</a>   0x1000U</td></tr>
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<tr class="separator:ga652183838bb096717551bf8a1917c257"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb1809e5b8a9ebc4b1cbc8967d985929" id="r_gacb1809e5b8a9ebc4b1cbc8967d985929"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb1809e5b8a9ebc4b1cbc8967d985929">SYSCFG_EXTICR1_EXTI3_PC</a>   0x2000U</td></tr>
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<tr class="separator:gacb1809e5b8a9ebc4b1cbc8967d985929"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga205440ffa174509d57c2b6a1814f8202" id="r_ga205440ffa174509d57c2b6a1814f8202"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga205440ffa174509d57c2b6a1814f8202">SYSCFG_EXTICR1_EXTI3_PD</a>   0x3000U</td></tr>
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<tr class="separator:ga205440ffa174509d57c2b6a1814f8202"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2b33beb6294fd7a257f0f3a36e0dcda" id="r_gab2b33beb6294fd7a257f0f3a36e0dcda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2b33beb6294fd7a257f0f3a36e0dcda">SYSCFG_EXTICR1_EXTI3_PE</a>   0x4000U</td></tr>
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<tr class="separator:gab2b33beb6294fd7a257f0f3a36e0dcda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40240ee616b6e06ecd8dabe9d8e56e71" id="r_ga40240ee616b6e06ecd8dabe9d8e56e71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40240ee616b6e06ecd8dabe9d8e56e71">SYSCFG_EXTICR1_EXTI3_PF</a>   0x5000U</td></tr>
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<tr class="separator:ga40240ee616b6e06ecd8dabe9d8e56e71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa73420dbafb7f20f16c350a12b0a0f5" id="r_gaaa73420dbafb7f20f16c350a12b0a0f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa73420dbafb7f20f16c350a12b0a0f5">SYSCFG_EXTICR1_EXTI3_PG</a>   0x6000U</td></tr>
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<tr class="separator:gaaa73420dbafb7f20f16c350a12b0a0f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae49def2961bf528448a4fbb4aa9c9d94" id="r_gae49def2961bf528448a4fbb4aa9c9d94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae49def2961bf528448a4fbb4aa9c9d94">SYSCFG_EXTICR1_EXTI3_PH</a>   0x7000U</td></tr>
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<tr class="separator:gae49def2961bf528448a4fbb4aa9c9d94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga337e37f58e8710ea8305a16c08e390b9" id="r_ga337e37f58e8710ea8305a16c08e390b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga337e37f58e8710ea8305a16c08e390b9">SYSCFG_EXTICR1_EXTI3_PI</a>   0x8000U</td></tr>
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<tr class="separator:ga337e37f58e8710ea8305a16c08e390b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2d0b453a61771de5591f5eb58ccb174" id="r_gae2d0b453a61771de5591f5eb58ccb174"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2d0b453a61771de5591f5eb58ccb174">SYSCFG_EXTICR2_EXTI4_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae2d0b453a61771de5591f5eb58ccb174"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf05f6030b07cf7ca730a2ea8325e7640" id="r_gaf05f6030b07cf7ca730a2ea8325e7640"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf05f6030b07cf7ca730a2ea8325e7640">SYSCFG_EXTICR2_EXTI4_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae2d0b453a61771de5591f5eb58ccb174">SYSCFG_EXTICR2_EXTI4_Pos</a>)</td></tr>
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<tr class="separator:gaf05f6030b07cf7ca730a2ea8325e7640"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2a57b4872977812e60d521268190e1e" id="r_gad2a57b4872977812e60d521268190e1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2a57b4872977812e60d521268190e1e">SYSCFG_EXTICR2_EXTI4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf05f6030b07cf7ca730a2ea8325e7640">SYSCFG_EXTICR2_EXTI4_Msk</a></td></tr>
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<tr class="separator:gad2a57b4872977812e60d521268190e1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade15c38da4f70df1a360337abac37314" id="r_gade15c38da4f70df1a360337abac37314"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade15c38da4f70df1a360337abac37314">SYSCFG_EXTICR2_EXTI5_Pos</a>   (4U)</td></tr>
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<tr class="separator:gade15c38da4f70df1a360337abac37314"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa47b595915b1cd571357a04f31c79656" id="r_gaa47b595915b1cd571357a04f31c79656"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa47b595915b1cd571357a04f31c79656">SYSCFG_EXTICR2_EXTI5_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gade15c38da4f70df1a360337abac37314">SYSCFG_EXTICR2_EXTI5_Pos</a>)</td></tr>
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<tr class="separator:gaa47b595915b1cd571357a04f31c79656"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6682a1b97b04c5c33085ffd2827ccd17" id="r_ga6682a1b97b04c5c33085ffd2827ccd17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6682a1b97b04c5c33085ffd2827ccd17">SYSCFG_EXTICR2_EXTI5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa47b595915b1cd571357a04f31c79656">SYSCFG_EXTICR2_EXTI5_Msk</a></td></tr>
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<tr class="separator:ga6682a1b97b04c5c33085ffd2827ccd17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab355e39e166c83c356999c3da7fd7893" id="r_gab355e39e166c83c356999c3da7fd7893"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab355e39e166c83c356999c3da7fd7893">SYSCFG_EXTICR2_EXTI6_Pos</a>   (8U)</td></tr>
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<tr class="separator:gab355e39e166c83c356999c3da7fd7893"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadbcd9e40a5da23a133cd3479d326c66" id="r_gaadbcd9e40a5da23a133cd3479d326c66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadbcd9e40a5da23a133cd3479d326c66">SYSCFG_EXTICR2_EXTI6_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab355e39e166c83c356999c3da7fd7893">SYSCFG_EXTICR2_EXTI6_Pos</a>)</td></tr>
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<tr class="separator:gaadbcd9e40a5da23a133cd3479d326c66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c50caf6019fd7d5038d77e61f57ad7b" id="r_ga6c50caf6019fd7d5038d77e61f57ad7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c50caf6019fd7d5038d77e61f57ad7b">SYSCFG_EXTICR2_EXTI6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaadbcd9e40a5da23a133cd3479d326c66">SYSCFG_EXTICR2_EXTI6_Msk</a></td></tr>
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<tr class="separator:ga6c50caf6019fd7d5038d77e61f57ad7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa503d2cda916e0b9d0f621317c3f1601" id="r_gaa503d2cda916e0b9d0f621317c3f1601"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa503d2cda916e0b9d0f621317c3f1601">SYSCFG_EXTICR2_EXTI7_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaa503d2cda916e0b9d0f621317c3f1601"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97160d2262cb4ab1ae9098809391f52e" id="r_ga97160d2262cb4ab1ae9098809391f52e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97160d2262cb4ab1ae9098809391f52e">SYSCFG_EXTICR2_EXTI7_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa503d2cda916e0b9d0f621317c3f1601">SYSCFG_EXTICR2_EXTI7_Pos</a>)</td></tr>
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<tr class="separator:ga97160d2262cb4ab1ae9098809391f52e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga638ea3bb014752813d064d37b3388950" id="r_ga638ea3bb014752813d064d37b3388950"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga638ea3bb014752813d064d37b3388950">SYSCFG_EXTICR2_EXTI7</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97160d2262cb4ab1ae9098809391f52e">SYSCFG_EXTICR2_EXTI7_Msk</a></td></tr>
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<tr class="separator:ga638ea3bb014752813d064d37b3388950"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51147f1747daf48dbcfad03285ae8889" id="r_ga51147f1747daf48dbcfad03285ae8889"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51147f1747daf48dbcfad03285ae8889">SYSCFG_EXTICR2_EXTI4_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga51147f1747daf48dbcfad03285ae8889"><td class="mdescLeft"> </td><td class="mdescRight">EXTI4 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga51147f1747daf48dbcfad03285ae8889"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga917aeb0df688d6b34785085fc85d9e47" id="r_ga917aeb0df688d6b34785085fc85d9e47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga917aeb0df688d6b34785085fc85d9e47">SYSCFG_EXTICR2_EXTI4_PB</a>   0x0001U</td></tr>
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<tr class="separator:ga917aeb0df688d6b34785085fc85d9e47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14ac312beeb19d3bb34a552546477613" id="r_ga14ac312beeb19d3bb34a552546477613"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14ac312beeb19d3bb34a552546477613">SYSCFG_EXTICR2_EXTI4_PC</a>   0x0002U</td></tr>
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<tr class="separator:ga14ac312beeb19d3bb34a552546477613"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec62164e18d1b525e8272169b1efe642" id="r_gaec62164e18d1b525e8272169b1efe642"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec62164e18d1b525e8272169b1efe642">SYSCFG_EXTICR2_EXTI4_PD</a>   0x0003U</td></tr>
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<tr class="separator:gaec62164e18d1b525e8272169b1efe642"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1d2292b6a856a8a71d82f595b580b9b" id="r_gac1d2292b6a856a8a71d82f595b580b9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1d2292b6a856a8a71d82f595b580b9b">SYSCFG_EXTICR2_EXTI4_PE</a>   0x0004U</td></tr>
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<tr class="separator:gac1d2292b6a856a8a71d82f595b580b9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0adc3c72bddc65977e3ef56df74ed40e" id="r_ga0adc3c72bddc65977e3ef56df74ed40e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0adc3c72bddc65977e3ef56df74ed40e">SYSCFG_EXTICR2_EXTI4_PF</a>   0x0005U</td></tr>
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<tr class="separator:ga0adc3c72bddc65977e3ef56df74ed40e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5aad8ed8589e28677332ea0b200617b" id="r_gad5aad8ed8589e28677332ea0b200617b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5aad8ed8589e28677332ea0b200617b">SYSCFG_EXTICR2_EXTI4_PG</a>   0x0006U</td></tr>
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<tr class="separator:gad5aad8ed8589e28677332ea0b200617b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga339f8994c317190a387a96b857aa79d0" id="r_ga339f8994c317190a387a96b857aa79d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga339f8994c317190a387a96b857aa79d0">SYSCFG_EXTICR2_EXTI4_PH</a>   0x0007U</td></tr>
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<tr class="separator:ga339f8994c317190a387a96b857aa79d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad36a509bf6deabd5446a07c20964f83" id="r_gaad36a509bf6deabd5446a07c20964f83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad36a509bf6deabd5446a07c20964f83">SYSCFG_EXTICR2_EXTI4_PI</a>   0x0008U</td></tr>
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<tr class="separator:gaad36a509bf6deabd5446a07c20964f83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb9581c515a4bdf1ed88fe96d8c24794" id="r_gafb9581c515a4bdf1ed88fe96d8c24794"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb9581c515a4bdf1ed88fe96d8c24794">SYSCFG_EXTICR2_EXTI5_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:gafb9581c515a4bdf1ed88fe96d8c24794"><td class="mdescLeft"> </td><td class="mdescRight">EXTI5 configuration <br />
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<br /></td></tr>
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<tr class="separator:gafb9581c515a4bdf1ed88fe96d8c24794"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90a3f610234dfa13f56e72c76a12be74" id="r_ga90a3f610234dfa13f56e72c76a12be74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90a3f610234dfa13f56e72c76a12be74">SYSCFG_EXTICR2_EXTI5_PB</a>   0x0010U</td></tr>
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<tr class="separator:ga90a3f610234dfa13f56e72c76a12be74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33b6bdc1b4bfeda0d4034dc67f1a6046" id="r_ga33b6bdc1b4bfeda0d4034dc67f1a6046"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33b6bdc1b4bfeda0d4034dc67f1a6046">SYSCFG_EXTICR2_EXTI5_PC</a>   0x0020U</td></tr>
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<tr class="separator:ga33b6bdc1b4bfeda0d4034dc67f1a6046"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0eea392f1530c7cb794a63d04e268a70" id="r_ga0eea392f1530c7cb794a63d04e268a70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0eea392f1530c7cb794a63d04e268a70">SYSCFG_EXTICR2_EXTI5_PD</a>   0x0030U</td></tr>
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<tr class="separator:ga0eea392f1530c7cb794a63d04e268a70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a4e6644d0144bfb0f913cf20eaf2f8e" id="r_ga8a4e6644d0144bfb0f913cf20eaf2f8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a4e6644d0144bfb0f913cf20eaf2f8e">SYSCFG_EXTICR2_EXTI5_PE</a>   0x0040U</td></tr>
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<tr class="separator:ga8a4e6644d0144bfb0f913cf20eaf2f8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga740e27c5bead2c914a134ac4ed4d05b3" id="r_ga740e27c5bead2c914a134ac4ed4d05b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga740e27c5bead2c914a134ac4ed4d05b3">SYSCFG_EXTICR2_EXTI5_PF</a>   0x0050U</td></tr>
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<tr class="separator:ga740e27c5bead2c914a134ac4ed4d05b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d78839e577ab90090abcdcff88e18c8" id="r_ga7d78839e577ab90090abcdcff88e18c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d78839e577ab90090abcdcff88e18c8">SYSCFG_EXTICR2_EXTI5_PG</a>   0x0060U</td></tr>
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<tr class="separator:ga7d78839e577ab90090abcdcff88e18c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a06842a64138b5010186d980cb594f9" id="r_ga4a06842a64138b5010186d980cb594f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a06842a64138b5010186d980cb594f9">SYSCFG_EXTICR2_EXTI5_PH</a>   0x0070U</td></tr>
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<tr class="separator:ga4a06842a64138b5010186d980cb594f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f3c4ebe4d750f89465acd067ab0ee30" id="r_ga4f3c4ebe4d750f89465acd067ab0ee30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f3c4ebe4d750f89465acd067ab0ee30">SYSCFG_EXTICR2_EXTI5_PI</a>   0x0080U</td></tr>
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<tr class="separator:ga4f3c4ebe4d750f89465acd067ab0ee30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e87c78fb6dfde7c8b7f81fe3b65aae9" id="r_ga3e87c78fb6dfde7c8b7f81fe3b65aae9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e87c78fb6dfde7c8b7f81fe3b65aae9">SYSCFG_EXTICR2_EXTI6_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga3e87c78fb6dfde7c8b7f81fe3b65aae9"><td class="mdescLeft"> </td><td class="mdescRight">EXTI6 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga3e87c78fb6dfde7c8b7f81fe3b65aae9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6528de8e4ca8741e86ae254e1d6b2a70" id="r_ga6528de8e4ca8741e86ae254e1d6b2a70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6528de8e4ca8741e86ae254e1d6b2a70">SYSCFG_EXTICR2_EXTI6_PB</a>   0x0100U</td></tr>
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<tr class="separator:ga6528de8e4ca8741e86ae254e1d6b2a70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53d8745705d5eb84c70a8554f61d59ac" id="r_ga53d8745705d5eb84c70a8554f61d59ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53d8745705d5eb84c70a8554f61d59ac">SYSCFG_EXTICR2_EXTI6_PC</a>   0x0200U</td></tr>
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<tr class="separator:ga53d8745705d5eb84c70a8554f61d59ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26c97cdece451441e49120e754020cdc" id="r_ga26c97cdece451441e49120e754020cdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26c97cdece451441e49120e754020cdc">SYSCFG_EXTICR2_EXTI6_PD</a>   0x0300U</td></tr>
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<tr class="separator:ga26c97cdece451441e49120e754020cdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga804218f2dd83c72e672143ec4f283ad3" id="r_ga804218f2dd83c72e672143ec4f283ad3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga804218f2dd83c72e672143ec4f283ad3">SYSCFG_EXTICR2_EXTI6_PE</a>   0x0400U</td></tr>
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<tr class="separator:ga804218f2dd83c72e672143ec4f283ad3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d36de53e52c8a4c7991513fec326df6" id="r_ga0d36de53e52c8a4c7991513fec326df6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d36de53e52c8a4c7991513fec326df6">SYSCFG_EXTICR2_EXTI6_PF</a>   0x0500U</td></tr>
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<tr class="separator:ga0d36de53e52c8a4c7991513fec326df6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga278997204184bfe7c951c1da327e6fb5" id="r_ga278997204184bfe7c951c1da327e6fb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga278997204184bfe7c951c1da327e6fb5">SYSCFG_EXTICR2_EXTI6_PG</a>   0x0600U</td></tr>
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<tr class="separator:ga278997204184bfe7c951c1da327e6fb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga283486dccd660fbf830e8c44b0161a63" id="r_ga283486dccd660fbf830e8c44b0161a63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga283486dccd660fbf830e8c44b0161a63">SYSCFG_EXTICR2_EXTI6_PH</a>   0x0700U</td></tr>
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<tr class="separator:ga283486dccd660fbf830e8c44b0161a63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4222e7d9ed672ea2de3a038c23f9566b" id="r_ga4222e7d9ed672ea2de3a038c23f9566b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4222e7d9ed672ea2de3a038c23f9566b">SYSCFG_EXTICR2_EXTI6_PI</a>   0x0800U</td></tr>
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<tr class="separator:ga4222e7d9ed672ea2de3a038c23f9566b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f1bfd3af524288b6ce54d7f9aef410a" id="r_ga2f1bfd3af524288b6ce54d7f9aef410a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f1bfd3af524288b6ce54d7f9aef410a">SYSCFG_EXTICR2_EXTI7_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga2f1bfd3af524288b6ce54d7f9aef410a"><td class="mdescLeft"> </td><td class="mdescRight">EXTI7 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga2f1bfd3af524288b6ce54d7f9aef410a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab18d324986b18858f901febbcc2a57b7" id="r_gab18d324986b18858f901febbcc2a57b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab18d324986b18858f901febbcc2a57b7">SYSCFG_EXTICR2_EXTI7_PB</a>   0x1000U</td></tr>
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<tr class="separator:gab18d324986b18858f901febbcc2a57b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9f53618d9cf13af2b2ecf191da8595a" id="r_gae9f53618d9cf13af2b2ecf191da8595a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9f53618d9cf13af2b2ecf191da8595a">SYSCFG_EXTICR2_EXTI7_PC</a>   0x2000U</td></tr>
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<tr class="separator:gae9f53618d9cf13af2b2ecf191da8595a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae38aa3b76227bb8e9d8cedc31c023f63" id="r_gae38aa3b76227bb8e9d8cedc31c023f63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae38aa3b76227bb8e9d8cedc31c023f63">SYSCFG_EXTICR2_EXTI7_PD</a>   0x3000U</td></tr>
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<tr class="separator:gae38aa3b76227bb8e9d8cedc31c023f63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90d097c1b5cbb62dc86327604907dcd4" id="r_ga90d097c1b5cbb62dc86327604907dcd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90d097c1b5cbb62dc86327604907dcd4">SYSCFG_EXTICR2_EXTI7_PE</a>   0x4000U</td></tr>
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<tr class="separator:ga90d097c1b5cbb62dc86327604907dcd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf2c3a661be3569fffe11515e37de1e4" id="r_gaaf2c3a661be3569fffe11515e37de1e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf2c3a661be3569fffe11515e37de1e4">SYSCFG_EXTICR2_EXTI7_PF</a>   0x5000U</td></tr>
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<tr class="separator:gaaf2c3a661be3569fffe11515e37de1e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga987bc0488e57b14b0a98e4952df2b539" id="r_ga987bc0488e57b14b0a98e4952df2b539"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga987bc0488e57b14b0a98e4952df2b539">SYSCFG_EXTICR2_EXTI7_PG</a>   0x6000U</td></tr>
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<tr class="separator:ga987bc0488e57b14b0a98e4952df2b539"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0ce56e15f4eb86a3e262deaa845cb99" id="r_gab0ce56e15f4eb86a3e262deaa845cb99"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0ce56e15f4eb86a3e262deaa845cb99">SYSCFG_EXTICR2_EXTI7_PH</a>   0x7000U</td></tr>
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<tr class="separator:gab0ce56e15f4eb86a3e262deaa845cb99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae68ca6758cf36232dd5ac63afae97cbc" id="r_gae68ca6758cf36232dd5ac63afae97cbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae68ca6758cf36232dd5ac63afae97cbc">SYSCFG_EXTICR2_EXTI7_PI</a>   0x8000U</td></tr>
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<tr class="separator:gae68ca6758cf36232dd5ac63afae97cbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e1169e4f50e721a7c6b9d9c2b722035" id="r_ga0e1169e4f50e721a7c6b9d9c2b722035"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e1169e4f50e721a7c6b9d9c2b722035">SYSCFG_EXTICR3_EXTI8_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0e1169e4f50e721a7c6b9d9c2b722035"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab693b7e686ba5646959113dd6b408673" id="r_gab693b7e686ba5646959113dd6b408673"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab693b7e686ba5646959113dd6b408673">SYSCFG_EXTICR3_EXTI8_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e1169e4f50e721a7c6b9d9c2b722035">SYSCFG_EXTICR3_EXTI8_Pos</a>)</td></tr>
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<tr class="separator:gab693b7e686ba5646959113dd6b408673"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2a656b18cc728e38acb72cf8d7e7935" id="r_gaf2a656b18cc728e38acb72cf8d7e7935"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2a656b18cc728e38acb72cf8d7e7935">SYSCFG_EXTICR3_EXTI8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab693b7e686ba5646959113dd6b408673">SYSCFG_EXTICR3_EXTI8_Msk</a></td></tr>
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<tr class="separator:gaf2a656b18cc728e38acb72cf8d7e7935"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f6d994a483df2e705db0343cb88fb53" id="r_ga6f6d994a483df2e705db0343cb88fb53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f6d994a483df2e705db0343cb88fb53">SYSCFG_EXTICR3_EXTI9_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga6f6d994a483df2e705db0343cb88fb53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ea1b3c5cb074a305ad06709a7023689" id="r_ga8ea1b3c5cb074a305ad06709a7023689"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ea1b3c5cb074a305ad06709a7023689">SYSCFG_EXTICR3_EXTI9_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f6d994a483df2e705db0343cb88fb53">SYSCFG_EXTICR3_EXTI9_Pos</a>)</td></tr>
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<tr class="separator:ga8ea1b3c5cb074a305ad06709a7023689"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga002462e4c233adc6dd502de726994575" id="r_ga002462e4c233adc6dd502de726994575"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga002462e4c233adc6dd502de726994575">SYSCFG_EXTICR3_EXTI9</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ea1b3c5cb074a305ad06709a7023689">SYSCFG_EXTICR3_EXTI9_Msk</a></td></tr>
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<tr class="separator:ga002462e4c233adc6dd502de726994575"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d6efb981e6435ae15643e438196ffba" id="r_ga8d6efb981e6435ae15643e438196ffba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d6efb981e6435ae15643e438196ffba">SYSCFG_EXTICR3_EXTI10_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga8d6efb981e6435ae15643e438196ffba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1803c2719fb53533547496e02c8b07d4" id="r_ga1803c2719fb53533547496e02c8b07d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1803c2719fb53533547496e02c8b07d4">SYSCFG_EXTICR3_EXTI10_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d6efb981e6435ae15643e438196ffba">SYSCFG_EXTICR3_EXTI10_Pos</a>)</td></tr>
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<tr class="separator:ga1803c2719fb53533547496e02c8b07d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fc06b17c3b3d393b749bf9924a43a80" id="r_ga8fc06b17c3b3d393b749bf9924a43a80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fc06b17c3b3d393b749bf9924a43a80">SYSCFG_EXTICR3_EXTI10</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1803c2719fb53533547496e02c8b07d4">SYSCFG_EXTICR3_EXTI10_Msk</a></td></tr>
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<tr class="separator:ga8fc06b17c3b3d393b749bf9924a43a80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29b9c2241040cf831bbb18391cda402c" id="r_ga29b9c2241040cf831bbb18391cda402c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29b9c2241040cf831bbb18391cda402c">SYSCFG_EXTICR3_EXTI11_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga29b9c2241040cf831bbb18391cda402c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c7d37c95e30bf30ac80d455bfa9a842" id="r_ga4c7d37c95e30bf30ac80d455bfa9a842"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c7d37c95e30bf30ac80d455bfa9a842">SYSCFG_EXTICR3_EXTI11_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga29b9c2241040cf831bbb18391cda402c">SYSCFG_EXTICR3_EXTI11_Pos</a>)</td></tr>
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<tr class="separator:ga4c7d37c95e30bf30ac80d455bfa9a842"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa66cc9a579696c8f5c41f5f138ee1e67" id="r_gaa66cc9a579696c8f5c41f5f138ee1e67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa66cc9a579696c8f5c41f5f138ee1e67">SYSCFG_EXTICR3_EXTI11</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c7d37c95e30bf30ac80d455bfa9a842">SYSCFG_EXTICR3_EXTI11_Msk</a></td></tr>
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<tr class="separator:gaa66cc9a579696c8f5c41f5f138ee1e67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1c6843a871f1a06ca25c0de50048b10" id="r_gae1c6843a871f1a06ca25c0de50048b10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1c6843a871f1a06ca25c0de50048b10">SYSCFG_EXTICR3_EXTI8_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:gae1c6843a871f1a06ca25c0de50048b10"><td class="mdescLeft"> </td><td class="mdescRight">EXTI8 configuration <br />
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<br /></td></tr>
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<tr class="separator:gae1c6843a871f1a06ca25c0de50048b10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4818dc7bffc8dfc2acc48995a62e66c5" id="r_ga4818dc7bffc8dfc2acc48995a62e66c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4818dc7bffc8dfc2acc48995a62e66c5">SYSCFG_EXTICR3_EXTI8_PB</a>   0x0001U</td></tr>
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<tr class="separator:ga4818dc7bffc8dfc2acc48995a62e66c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba0d34ff57632d7753981404cef548e2" id="r_gaba0d34ff57632d7753981404cef548e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba0d34ff57632d7753981404cef548e2">SYSCFG_EXTICR3_EXTI8_PC</a>   0x0002U</td></tr>
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<tr class="separator:gaba0d34ff57632d7753981404cef548e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa15260ba354dee354f0a71e7913009c3" id="r_gaa15260ba354dee354f0a71e7913009c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa15260ba354dee354f0a71e7913009c3">SYSCFG_EXTICR3_EXTI8_PD</a>   0x0003U</td></tr>
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<tr class="separator:gaa15260ba354dee354f0a71e7913009c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga185287204b8cead31d3760f65c5ca19d" id="r_ga185287204b8cead31d3760f65c5ca19d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga185287204b8cead31d3760f65c5ca19d">SYSCFG_EXTICR3_EXTI8_PE</a>   0x0004U</td></tr>
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<tr class="separator:ga185287204b8cead31d3760f65c5ca19d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga425e41001af4b205b8fbfba723572a81" id="r_ga425e41001af4b205b8fbfba723572a81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga425e41001af4b205b8fbfba723572a81">SYSCFG_EXTICR3_EXTI8_PF</a>   0x0005U</td></tr>
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<tr class="separator:ga425e41001af4b205b8fbfba723572a81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ecc7a12103b805da045093eb626614d" id="r_ga2ecc7a12103b805da045093eb626614d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ecc7a12103b805da045093eb626614d">SYSCFG_EXTICR3_EXTI8_PG</a>   0x0006U</td></tr>
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<tr class="separator:ga2ecc7a12103b805da045093eb626614d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0bf3fc7a2e35b7cbb9f08f2e3b06a3c4" id="r_ga0bf3fc7a2e35b7cbb9f08f2e3b06a3c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bf3fc7a2e35b7cbb9f08f2e3b06a3c4">SYSCFG_EXTICR3_EXTI8_PH</a>   0x0007U</td></tr>
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<tr class="separator:ga0bf3fc7a2e35b7cbb9f08f2e3b06a3c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0b679636c97041f5584012c78f6d7a3" id="r_gaf0b679636c97041f5584012c78f6d7a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0b679636c97041f5584012c78f6d7a3">SYSCFG_EXTICR3_EXTI8_PI</a>   0x0008U</td></tr>
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<tr class="separator:gaf0b679636c97041f5584012c78f6d7a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93e284e59c4ff887b2e79851ac0a81c4" id="r_ga93e284e59c4ff887b2e79851ac0a81c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93e284e59c4ff887b2e79851ac0a81c4">SYSCFG_EXTICR3_EXTI9_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga93e284e59c4ff887b2e79851ac0a81c4"><td class="mdescLeft"> </td><td class="mdescRight">EXTI9 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga93e284e59c4ff887b2e79851ac0a81c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9271cbc1ed09774a5fef4b379cab260" id="r_gaa9271cbc1ed09774a5fef4b379cab260"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9271cbc1ed09774a5fef4b379cab260">SYSCFG_EXTICR3_EXTI9_PB</a>   0x0010U</td></tr>
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<tr class="separator:gaa9271cbc1ed09774a5fef4b379cab260"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cc355176941881870c620c0837cab48" id="r_ga1cc355176941881870c620c0837cab48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc355176941881870c620c0837cab48">SYSCFG_EXTICR3_EXTI9_PC</a>   0x0020U</td></tr>
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<tr class="separator:ga1cc355176941881870c620c0837cab48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75af3c7a94cfc78361c94b054f9fe064" id="r_ga75af3c7a94cfc78361c94b054f9fe064"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75af3c7a94cfc78361c94b054f9fe064">SYSCFG_EXTICR3_EXTI9_PD</a>   0x0030U</td></tr>
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<tr class="separator:ga75af3c7a94cfc78361c94b054f9fe064"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafce176ef4b389251dadb98d9f59f8fe6" id="r_gafce176ef4b389251dadb98d9f59f8fe6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafce176ef4b389251dadb98d9f59f8fe6">SYSCFG_EXTICR3_EXTI9_PE</a>   0x0040U</td></tr>
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<tr class="separator:gafce176ef4b389251dadb98d9f59f8fe6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76ef2422b4d021d0cc038cb6325ed311" id="r_ga76ef2422b4d021d0cc038cb6325ed311"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76ef2422b4d021d0cc038cb6325ed311">SYSCFG_EXTICR3_EXTI9_PF</a>   0x0050U</td></tr>
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<tr class="separator:ga76ef2422b4d021d0cc038cb6325ed311"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1b37bf746ccfe0750aebd28cfa52a0c" id="r_gae1b37bf746ccfe0750aebd28cfa52a0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1b37bf746ccfe0750aebd28cfa52a0c">SYSCFG_EXTICR3_EXTI9_PG</a>   0x0060U</td></tr>
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<tr class="separator:gae1b37bf746ccfe0750aebd28cfa52a0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31fdedc4a90328881fe8817f4eef61b2" id="r_ga31fdedc4a90328881fe8817f4eef61b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31fdedc4a90328881fe8817f4eef61b2">SYSCFG_EXTICR3_EXTI9_PH</a>   0x0070U</td></tr>
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<tr class="separator:ga31fdedc4a90328881fe8817f4eef61b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cd8a0da1b9ede601094f6c651a499e4" id="r_ga8cd8a0da1b9ede601094f6c651a499e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cd8a0da1b9ede601094f6c651a499e4">SYSCFG_EXTICR3_EXTI9_PI</a>   0x0080U</td></tr>
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<tr class="separator:ga8cd8a0da1b9ede601094f6c651a499e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25acdbb9e916c440c41a060d861130ee" id="r_ga25acdbb9e916c440c41a060d861130ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25acdbb9e916c440c41a060d861130ee">SYSCFG_EXTICR3_EXTI10_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga25acdbb9e916c440c41a060d861130ee"><td class="mdescLeft"> </td><td class="mdescRight">EXTI10 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga25acdbb9e916c440c41a060d861130ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8d9aec4349bf38a4a9753b267b7de7e" id="r_gab8d9aec4349bf38a4a9753b267b7de7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8d9aec4349bf38a4a9753b267b7de7e">SYSCFG_EXTICR3_EXTI10_PB</a>   0x0100U</td></tr>
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<tr class="separator:gab8d9aec4349bf38a4a9753b267b7de7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62d2b81d49e30ab4fe96572be5da8484" id="r_ga62d2b81d49e30ab4fe96572be5da8484"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62d2b81d49e30ab4fe96572be5da8484">SYSCFG_EXTICR3_EXTI10_PC</a>   0x0200U</td></tr>
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<tr class="separator:ga62d2b81d49e30ab4fe96572be5da8484"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab3553c540cd836d465824939c2e3b79" id="r_gaab3553c540cd836d465824939c2e3b79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab3553c540cd836d465824939c2e3b79">SYSCFG_EXTICR3_EXTI10_PD</a>   0x0300U</td></tr>
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<tr class="separator:gaab3553c540cd836d465824939c2e3b79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabde568ef1c8f4bfaf18954e8ee0716a9" id="r_gabde568ef1c8f4bfaf18954e8ee0716a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabde568ef1c8f4bfaf18954e8ee0716a9">SYSCFG_EXTICR3_EXTI10_PE</a>   0x0400U</td></tr>
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<tr class="separator:gabde568ef1c8f4bfaf18954e8ee0716a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09ed841a11367cda67c7a416ed6d9b99" id="r_ga09ed841a11367cda67c7a416ed6d9b99"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09ed841a11367cda67c7a416ed6d9b99">SYSCFG_EXTICR3_EXTI10_PF</a>   0x0500U</td></tr>
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<tr class="separator:ga09ed841a11367cda67c7a416ed6d9b99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6dff840a6986b440e7633a3671ce57cc" id="r_ga6dff840a6986b440e7633a3671ce57cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6dff840a6986b440e7633a3671ce57cc">SYSCFG_EXTICR3_EXTI10_PG</a>   0x0600U</td></tr>
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<tr class="separator:ga6dff840a6986b440e7633a3671ce57cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga791e7d2bd23ae969540e5509c6718255" id="r_ga791e7d2bd23ae969540e5509c6718255"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga791e7d2bd23ae969540e5509c6718255">SYSCFG_EXTICR3_EXTI10_PH</a>   0x0700U</td></tr>
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<tr class="separator:ga791e7d2bd23ae969540e5509c6718255"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8bee76cf4bed88ff7b51145393b2cd19" id="r_ga8bee76cf4bed88ff7b51145393b2cd19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8bee76cf4bed88ff7b51145393b2cd19">SYSCFG_EXTICR3_EXTI10_PI</a>   0x0800U</td></tr>
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<tr class="separator:ga8bee76cf4bed88ff7b51145393b2cd19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ca8a85d4512677eff6ed2aac897a366" id="r_ga0ca8a85d4512677eff6ed2aac897a366"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ca8a85d4512677eff6ed2aac897a366">SYSCFG_EXTICR3_EXTI11_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga0ca8a85d4512677eff6ed2aac897a366"><td class="mdescLeft"> </td><td class="mdescRight">EXTI11 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga0ca8a85d4512677eff6ed2aac897a366"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedb3a8cc6b1763e303986553c0e4e7f8" id="r_gaedb3a8cc6b1763e303986553c0e4e7f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedb3a8cc6b1763e303986553c0e4e7f8">SYSCFG_EXTICR3_EXTI11_PB</a>   0x1000U</td></tr>
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<tr class="separator:gaedb3a8cc6b1763e303986553c0e4e7f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b01c8ba6cb27899a4f5fa494bf2b3f5" id="r_ga0b01c8ba6cb27899a4f5fa494bf2b3f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b01c8ba6cb27899a4f5fa494bf2b3f5">SYSCFG_EXTICR3_EXTI11_PC</a>   0x2000U</td></tr>
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<tr class="separator:ga0b01c8ba6cb27899a4f5fa494bf2b3f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a69d636cda0352da0982c54f582787d" id="r_ga6a69d636cda0352da0982c54f582787d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a69d636cda0352da0982c54f582787d">SYSCFG_EXTICR3_EXTI11_PD</a>   0x3000U</td></tr>
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<tr class="separator:ga6a69d636cda0352da0982c54f582787d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44affe06868a0490f8d0cbbba51ff412" id="r_ga44affe06868a0490f8d0cbbba51ff412"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44affe06868a0490f8d0cbbba51ff412">SYSCFG_EXTICR3_EXTI11_PE</a>   0x4000U</td></tr>
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<tr class="separator:ga44affe06868a0490f8d0cbbba51ff412"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66fb050835077047b576b3a510700d64" id="r_ga66fb050835077047b576b3a510700d64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66fb050835077047b576b3a510700d64">SYSCFG_EXTICR3_EXTI11_PF</a>   0x5000U</td></tr>
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<tr class="separator:ga66fb050835077047b576b3a510700d64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7b66390eeb4a8d50ebb7e87e2f281b3" id="r_gaf7b66390eeb4a8d50ebb7e87e2f281b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7b66390eeb4a8d50ebb7e87e2f281b3">SYSCFG_EXTICR3_EXTI11_PG</a>   0x6000U</td></tr>
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<tr class="separator:gaf7b66390eeb4a8d50ebb7e87e2f281b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa58cfe5d03072c259582ba8fefa322bf" id="r_gaa58cfe5d03072c259582ba8fefa322bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa58cfe5d03072c259582ba8fefa322bf">SYSCFG_EXTICR3_EXTI11_PH</a>   0x7000U</td></tr>
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<tr class="separator:gaa58cfe5d03072c259582ba8fefa322bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafadb14df8764208abeeaf6197489f1b4" id="r_gafadb14df8764208abeeaf6197489f1b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafadb14df8764208abeeaf6197489f1b4">SYSCFG_EXTICR3_EXTI11_PI</a>   0x8000U</td></tr>
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<tr class="separator:gafadb14df8764208abeeaf6197489f1b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81bcb273eca8dad24924a1402c31411e" id="r_ga81bcb273eca8dad24924a1402c31411e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81bcb273eca8dad24924a1402c31411e">SYSCFG_EXTICR4_EXTI12_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga81bcb273eca8dad24924a1402c31411e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabcd55b42c6aa84cdd8c36d7df16fcf5" id="r_gaabcd55b42c6aa84cdd8c36d7df16fcf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabcd55b42c6aa84cdd8c36d7df16fcf5">SYSCFG_EXTICR4_EXTI12_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga81bcb273eca8dad24924a1402c31411e">SYSCFG_EXTICR4_EXTI12_Pos</a>)</td></tr>
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<tr class="separator:gaabcd55b42c6aa84cdd8c36d7df16fcf5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d4b31f4a75d935b6a52afe6a16463d1" id="r_ga9d4b31f4a75d935b6a52afe6a16463d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d4b31f4a75d935b6a52afe6a16463d1">SYSCFG_EXTICR4_EXTI12</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaabcd55b42c6aa84cdd8c36d7df16fcf5">SYSCFG_EXTICR4_EXTI12_Msk</a></td></tr>
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<tr class="separator:ga9d4b31f4a75d935b6a52afe6a16463d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09cc7a3ec956c6849e56f0deb4bf94cc" id="r_ga09cc7a3ec956c6849e56f0deb4bf94cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09cc7a3ec956c6849e56f0deb4bf94cc">SYSCFG_EXTICR4_EXTI13_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga09cc7a3ec956c6849e56f0deb4bf94cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafaf1614a726586aeefae87ca1d803656" id="r_gafaf1614a726586aeefae87ca1d803656"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafaf1614a726586aeefae87ca1d803656">SYSCFG_EXTICR4_EXTI13_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga09cc7a3ec956c6849e56f0deb4bf94cc">SYSCFG_EXTICR4_EXTI13_Pos</a>)</td></tr>
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<tr class="separator:gafaf1614a726586aeefae87ca1d803656"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f04cda5bfe876431d5ad864302d7fa1" id="r_ga7f04cda5bfe876431d5ad864302d7fa1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f04cda5bfe876431d5ad864302d7fa1">SYSCFG_EXTICR4_EXTI13</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafaf1614a726586aeefae87ca1d803656">SYSCFG_EXTICR4_EXTI13_Msk</a></td></tr>
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<tr class="separator:ga7f04cda5bfe876431d5ad864302d7fa1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga525a67279d0e7f222fd770de959a96d5" id="r_ga525a67279d0e7f222fd770de959a96d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga525a67279d0e7f222fd770de959a96d5">SYSCFG_EXTICR4_EXTI14_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga525a67279d0e7f222fd770de959a96d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95bb6740c8bc08eb716e3ef71841e81a" id="r_ga95bb6740c8bc08eb716e3ef71841e81a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95bb6740c8bc08eb716e3ef71841e81a">SYSCFG_EXTICR4_EXTI14_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga525a67279d0e7f222fd770de959a96d5">SYSCFG_EXTICR4_EXTI14_Pos</a>)</td></tr>
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<tr class="separator:ga95bb6740c8bc08eb716e3ef71841e81a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabde06df3ec6e357374820a5a615991aa" id="r_gabde06df3ec6e357374820a5a615991aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabde06df3ec6e357374820a5a615991aa">SYSCFG_EXTICR4_EXTI14</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga95bb6740c8bc08eb716e3ef71841e81a">SYSCFG_EXTICR4_EXTI14_Msk</a></td></tr>
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<tr class="separator:gabde06df3ec6e357374820a5a615991aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2d829ebf74fc207970f57a960bd8b4a" id="r_gaa2d829ebf74fc207970f57a960bd8b4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2d829ebf74fc207970f57a960bd8b4a">SYSCFG_EXTICR4_EXTI15_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaa2d829ebf74fc207970f57a960bd8b4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08ef44dcc2fb1d5cb2fab3ca7eb1a45a" id="r_ga08ef44dcc2fb1d5cb2fab3ca7eb1a45a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08ef44dcc2fb1d5cb2fab3ca7eb1a45a">SYSCFG_EXTICR4_EXTI15_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2d829ebf74fc207970f57a960bd8b4a">SYSCFG_EXTICR4_EXTI15_Pos</a>)</td></tr>
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<tr class="separator:ga08ef44dcc2fb1d5cb2fab3ca7eb1a45a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd325c27cff1ae3de773d5e205a33f4e" id="r_gabd325c27cff1ae3de773d5e205a33f4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd325c27cff1ae3de773d5e205a33f4e">SYSCFG_EXTICR4_EXTI15</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga08ef44dcc2fb1d5cb2fab3ca7eb1a45a">SYSCFG_EXTICR4_EXTI15_Msk</a></td></tr>
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<tr class="separator:gabd325c27cff1ae3de773d5e205a33f4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ceaa63866465faa8145ce0c5d9a44d0" id="r_ga3ceaa63866465faa8145ce0c5d9a44d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ceaa63866465faa8145ce0c5d9a44d0">SYSCFG_EXTICR4_EXTI12_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga3ceaa63866465faa8145ce0c5d9a44d0"><td class="mdescLeft"> </td><td class="mdescRight">EXTI12 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga3ceaa63866465faa8145ce0c5d9a44d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8b00a462533a83c75c588340a2fa710" id="r_gad8b00a462533a83c75c588340a2fa710"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8b00a462533a83c75c588340a2fa710">SYSCFG_EXTICR4_EXTI12_PB</a>   0x0001U</td></tr>
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<tr class="separator:gad8b00a462533a83c75c588340a2fa710"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d27668b1fa6b1accde06aa144faa970" id="r_ga4d27668b1fa6b1accde06aa144faa970"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d27668b1fa6b1accde06aa144faa970">SYSCFG_EXTICR4_EXTI12_PC</a>   0x0002U</td></tr>
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<tr class="separator:ga4d27668b1fa6b1accde06aa144faa970"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa46ddd43a361d82abcb3cb7779ac74ff" id="r_gaa46ddd43a361d82abcb3cb7779ac74ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa46ddd43a361d82abcb3cb7779ac74ff">SYSCFG_EXTICR4_EXTI12_PD</a>   0x0003U</td></tr>
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<tr class="separator:gaa46ddd43a361d82abcb3cb7779ac74ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga102ee111e27fd67228c169836dd0849e" id="r_ga102ee111e27fd67228c169836dd0849e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga102ee111e27fd67228c169836dd0849e">SYSCFG_EXTICR4_EXTI12_PE</a>   0x0004U</td></tr>
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<tr class="separator:ga102ee111e27fd67228c169836dd0849e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9785209e7e13fcf9c4f82d57bae0837" id="r_gad9785209e7e13fcf9c4f82d57bae0837"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9785209e7e13fcf9c4f82d57bae0837">SYSCFG_EXTICR4_EXTI12_PF</a>   0x0005U</td></tr>
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<tr class="separator:gad9785209e7e13fcf9c4f82d57bae0837"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c78af5f130089bec32d6f782288765c" id="r_ga5c78af5f130089bec32d6f782288765c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c78af5f130089bec32d6f782288765c">SYSCFG_EXTICR4_EXTI12_PG</a>   0x0006U</td></tr>
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<tr class="separator:ga5c78af5f130089bec32d6f782288765c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b7baa5b844b78d3e05326607b2910a6" id="r_ga0b7baa5b844b78d3e05326607b2910a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b7baa5b844b78d3e05326607b2910a6">SYSCFG_EXTICR4_EXTI12_PH</a>   0x0007U</td></tr>
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<tr class="separator:ga0b7baa5b844b78d3e05326607b2910a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0514aaa894c9be44ba47c1346756f90b" id="r_ga0514aaa894c9be44ba47c1346756f90b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0514aaa894c9be44ba47c1346756f90b">SYSCFG_EXTICR4_EXTI13_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga0514aaa894c9be44ba47c1346756f90b"><td class="mdescLeft"> </td><td class="mdescRight">EXTI13 configuration <br />
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<tr class="separator:ga0514aaa894c9be44ba47c1346756f90b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34e6776e3ebfecc9e78c5aec77c48eff" id="r_ga34e6776e3ebfecc9e78c5aec77c48eff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34e6776e3ebfecc9e78c5aec77c48eff">SYSCFG_EXTICR4_EXTI13_PB</a>   0x0010U</td></tr>
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<tr class="separator:ga34e6776e3ebfecc9e78c5aec77c48eff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c7833d4e3c6b7f3878f62a200a6ab14" id="r_ga1c7833d4e3c6b7f3878f62a200a6ab14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c7833d4e3c6b7f3878f62a200a6ab14">SYSCFG_EXTICR4_EXTI13_PC</a>   0x0020U</td></tr>
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<tr class="separator:ga1c7833d4e3c6b7f3878f62a200a6ab14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabed530f628b3c37281f7a583af1cdb3c" id="r_gabed530f628b3c37281f7a583af1cdb3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabed530f628b3c37281f7a583af1cdb3c">SYSCFG_EXTICR4_EXTI13_PD</a>   0x0030U</td></tr>
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<tr class="separator:gabed530f628b3c37281f7a583af1cdb3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7dc5424bf39509a989464a81ec0714da" id="r_ga7dc5424bf39509a989464a81ec0714da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc5424bf39509a989464a81ec0714da">SYSCFG_EXTICR4_EXTI13_PE</a>   0x0040U</td></tr>
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<tr class="separator:ga7dc5424bf39509a989464a81ec0714da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf4c995587d7bae6436e6793b8214627" id="r_gaaf4c995587d7bae6436e6793b8214627"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf4c995587d7bae6436e6793b8214627">SYSCFG_EXTICR4_EXTI13_PF</a>   0x0050U</td></tr>
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<tr class="separator:gaaf4c995587d7bae6436e6793b8214627"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dedb6adbf49c40e5a15ad2afc471155" id="r_ga4dedb6adbf49c40e5a15ad2afc471155"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dedb6adbf49c40e5a15ad2afc471155">SYSCFG_EXTICR4_EXTI13_PG</a>   0x0060U</td></tr>
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<tr class="separator:ga4dedb6adbf49c40e5a15ad2afc471155"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61214ec3d87450f54b959aab49ea65b6" id="r_ga61214ec3d87450f54b959aab49ea65b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61214ec3d87450f54b959aab49ea65b6">SYSCFG_EXTICR4_EXTI13_PH</a>   0x0070U</td></tr>
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<tr class="separator:ga61214ec3d87450f54b959aab49ea65b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ad140a68e3e4e0406a182a504679ea9" id="r_ga7ad140a68e3e4e0406a182a504679ea9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ad140a68e3e4e0406a182a504679ea9">SYSCFG_EXTICR4_EXTI14_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:ga7ad140a68e3e4e0406a182a504679ea9"><td class="mdescLeft"> </td><td class="mdescRight">EXTI14 configuration <br />
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<br /></td></tr>
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<tr class="separator:ga7ad140a68e3e4e0406a182a504679ea9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5c1b8a0f2b4f79bd868bbb2b4eff617" id="r_gae5c1b8a0f2b4f79bd868bbb2b4eff617"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5c1b8a0f2b4f79bd868bbb2b4eff617">SYSCFG_EXTICR4_EXTI14_PB</a>   0x0100U</td></tr>
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<tr class="separator:gae5c1b8a0f2b4f79bd868bbb2b4eff617"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ca668cdd447acb1740566f46de5eb19" id="r_ga8ca668cdd447acb1740566f46de5eb19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ca668cdd447acb1740566f46de5eb19">SYSCFG_EXTICR4_EXTI14_PC</a>   0x0200U</td></tr>
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<tr class="separator:ga8ca668cdd447acb1740566f46de5eb19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f20b2bfa9dc8b57a987c127c6dfa6fe" id="r_ga2f20b2bfa9dc8b57a987c127c6dfa6fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f20b2bfa9dc8b57a987c127c6dfa6fe">SYSCFG_EXTICR4_EXTI14_PD</a>   0x0300U</td></tr>
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<tr class="separator:ga2f20b2bfa9dc8b57a987c127c6dfa6fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c13c49f6d93865ba05361cd86fddabf" id="r_ga4c13c49f6d93865ba05361cd86fddabf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c13c49f6d93865ba05361cd86fddabf">SYSCFG_EXTICR4_EXTI14_PE</a>   0x0400U</td></tr>
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<tr class="separator:ga4c13c49f6d93865ba05361cd86fddabf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9df1ee6f60db93301acaa9220a591da9" id="r_ga9df1ee6f60db93301acaa9220a591da9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9df1ee6f60db93301acaa9220a591da9">SYSCFG_EXTICR4_EXTI14_PF</a>   0x0500U</td></tr>
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<tr class="separator:ga9df1ee6f60db93301acaa9220a591da9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8ae4d091bb2c7148188ef430734020a" id="r_gae8ae4d091bb2c7148188ef430734020a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8ae4d091bb2c7148188ef430734020a">SYSCFG_EXTICR4_EXTI14_PG</a>   0x0600U</td></tr>
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<tr class="separator:gae8ae4d091bb2c7148188ef430734020a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07b38f38fa3957c6bc45ef4282b58377" id="r_ga07b38f38fa3957c6bc45ef4282b58377"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07b38f38fa3957c6bc45ef4282b58377">SYSCFG_EXTICR4_EXTI14_PH</a>   0x0700U</td></tr>
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<tr class="separator:ga07b38f38fa3957c6bc45ef4282b58377"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2f28920677dd99f9132ed28f7b1d5e2" id="r_gae2f28920677dd99f9132ed28f7b1d5e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2f28920677dd99f9132ed28f7b1d5e2">SYSCFG_EXTICR4_EXTI15_PA</a>   0x0000U</td></tr>
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<tr class="memdesc:gae2f28920677dd99f9132ed28f7b1d5e2"><td class="mdescLeft"> </td><td class="mdescRight">EXTI15 configuration <br />
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<br /></td></tr>
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<tr class="separator:gae2f28920677dd99f9132ed28f7b1d5e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga412f44d6a8f8f60420d7e7f8b5635e09" id="r_ga412f44d6a8f8f60420d7e7f8b5635e09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga412f44d6a8f8f60420d7e7f8b5635e09">SYSCFG_EXTICR4_EXTI15_PB</a>   0x1000U</td></tr>
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<tr class="separator:ga412f44d6a8f8f60420d7e7f8b5635e09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49778592caef3a176ee82c9b83e25148" id="r_ga49778592caef3a176ee82c9b83e25148"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49778592caef3a176ee82c9b83e25148">SYSCFG_EXTICR4_EXTI15_PC</a>   0x2000U</td></tr>
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<tr class="separator:ga49778592caef3a176ee82c9b83e25148"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac23e07d92a68cf7f8c3e58b479638885" id="r_gac23e07d92a68cf7f8c3e58b479638885"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac23e07d92a68cf7f8c3e58b479638885">SYSCFG_EXTICR4_EXTI15_PD</a>   0x3000U</td></tr>
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<tr class="separator:gac23e07d92a68cf7f8c3e58b479638885"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefd64bc0ea005d03068f2e9b8f425944" id="r_gaefd64bc0ea005d03068f2e9b8f425944"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefd64bc0ea005d03068f2e9b8f425944">SYSCFG_EXTICR4_EXTI15_PE</a>   0x4000U</td></tr>
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<tr class="separator:gaefd64bc0ea005d03068f2e9b8f425944"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e88d51ebabe9f70e5b7c2ad60899d54" id="r_ga5e88d51ebabe9f70e5b7c2ad60899d54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e88d51ebabe9f70e5b7c2ad60899d54">SYSCFG_EXTICR4_EXTI15_PF</a>   0x5000U</td></tr>
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<tr class="separator:ga5e88d51ebabe9f70e5b7c2ad60899d54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51d341c45e98ccbd82bf7003bfa56e6b" id="r_ga51d341c45e98ccbd82bf7003bfa56e6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51d341c45e98ccbd82bf7003bfa56e6b">SYSCFG_EXTICR4_EXTI15_PG</a>   0x6000U</td></tr>
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<tr class="separator:ga51d341c45e98ccbd82bf7003bfa56e6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga701c1065ec215a34329017bae69046c3" id="r_ga701c1065ec215a34329017bae69046c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga701c1065ec215a34329017bae69046c3">SYSCFG_EXTICR4_EXTI15_PH</a>   0x7000U</td></tr>
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<tr class="separator:ga701c1065ec215a34329017bae69046c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1747204ad5b1221e47a6610e46790e9" id="r_gad1747204ad5b1221e47a6610e46790e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1747204ad5b1221e47a6610e46790e9">SYSCFG_CMPCR_CMP_PD_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad1747204ad5b1221e47a6610e46790e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ff39240a251120eebbc18e4955be5db" id="r_ga1ff39240a251120eebbc18e4955be5db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ff39240a251120eebbc18e4955be5db">SYSCFG_CMPCR_CMP_PD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad1747204ad5b1221e47a6610e46790e9">SYSCFG_CMPCR_CMP_PD_Pos</a>)</td></tr>
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<tr class="separator:ga1ff39240a251120eebbc18e4955be5db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga261292a3a7ca1f767915b2e2ec3a7806" id="r_ga261292a3a7ca1f767915b2e2ec3a7806"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga261292a3a7ca1f767915b2e2ec3a7806">SYSCFG_CMPCR_CMP_PD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ff39240a251120eebbc18e4955be5db">SYSCFG_CMPCR_CMP_PD_Msk</a></td></tr>
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<tr class="separator:ga261292a3a7ca1f767915b2e2ec3a7806"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d5884039c7c13bdef0f45090f48e275" id="r_ga7d5884039c7c13bdef0f45090f48e275"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d5884039c7c13bdef0f45090f48e275">SYSCFG_CMPCR_READY_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga7d5884039c7c13bdef0f45090f48e275"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4d9717bd2df4c0742d09a2db4caa1ea" id="r_gaa4d9717bd2df4c0742d09a2db4caa1ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4d9717bd2df4c0742d09a2db4caa1ea">SYSCFG_CMPCR_READY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d5884039c7c13bdef0f45090f48e275">SYSCFG_CMPCR_READY_Pos</a>)</td></tr>
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<tr class="separator:gaa4d9717bd2df4c0742d09a2db4caa1ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae16bcca9b727e68f11467b6b3dad6215" id="r_gae16bcca9b727e68f11467b6b3dad6215"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae16bcca9b727e68f11467b6b3dad6215">SYSCFG_CMPCR_READY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4d9717bd2df4c0742d09a2db4caa1ea">SYSCFG_CMPCR_READY_Msk</a></td></tr>
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<tr class="separator:gae16bcca9b727e68f11467b6b3dad6215"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9cdca91d88f73215ab00bc9a84938584" id="r_ga9cdca91d88f73215ab00bc9a84938584"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cdca91d88f73215ab00bc9a84938584">TIM_CR1_CEN_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga9cdca91d88f73215ab00bc9a84938584"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab39f58b244f6d1eb12be39b714e434e5" id="r_gab39f58b244f6d1eb12be39b714e434e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab39f58b244f6d1eb12be39b714e434e5">TIM_CR1_CEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9cdca91d88f73215ab00bc9a84938584">TIM_CR1_CEN_Pos</a>)</td></tr>
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<tr class="separator:gab39f58b244f6d1eb12be39b714e434e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93d86355e5e3b399ed45e1ca83abed2a" id="r_ga93d86355e5e3b399ed45e1ca83abed2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93d86355e5e3b399ed45e1ca83abed2a">TIM_CR1_CEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab39f58b244f6d1eb12be39b714e434e5">TIM_CR1_CEN_Msk</a></td></tr>
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<tr class="separator:ga93d86355e5e3b399ed45e1ca83abed2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga014a0f9d40c6a34b7fdf70bd8908d14d" id="r_ga014a0f9d40c6a34b7fdf70bd8908d14d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga014a0f9d40c6a34b7fdf70bd8908d14d">TIM_CR1_UDIS_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga014a0f9d40c6a34b7fdf70bd8908d14d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab930af301c357d666089faef3fe38982" id="r_gab930af301c357d666089faef3fe38982"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab930af301c357d666089faef3fe38982">TIM_CR1_UDIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga014a0f9d40c6a34b7fdf70bd8908d14d">TIM_CR1_UDIS_Pos</a>)</td></tr>
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<tr class="memitem:gaa4f2a9f0cf7b60e3c623af451f141f3c" id="r_gaa4f2a9f0cf7b60e3c623af451f141f3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4f2a9f0cf7b60e3c623af451f141f3c">TIM_CR1_UDIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab930af301c357d666089faef3fe38982">TIM_CR1_UDIS_Msk</a></td></tr>
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<tr class="memitem:gaa68d9cdf8e673e01035272fa228ab239" id="r_gaa68d9cdf8e673e01035272fa228ab239"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa68d9cdf8e673e01035272fa228ab239">TIM_CR1_URS_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga86b7788d2996e1a0b729c23f6c01df18" id="r_ga86b7788d2996e1a0b729c23f6c01df18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86b7788d2996e1a0b729c23f6c01df18">TIM_CR1_URS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa68d9cdf8e673e01035272fa228ab239">TIM_CR1_URS_Pos</a>)</td></tr>
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<tr class="separator:ga86b7788d2996e1a0b729c23f6c01df18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06c997c2c23e8bef7ca07579762c113b" id="r_ga06c997c2c23e8bef7ca07579762c113b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06c997c2c23e8bef7ca07579762c113b">TIM_CR1_URS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86b7788d2996e1a0b729c23f6c01df18">TIM_CR1_URS_Msk</a></td></tr>
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<tr class="separator:ga06c997c2c23e8bef7ca07579762c113b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cae3644294078a1a12ac19f86ece98e" id="r_ga2cae3644294078a1a12ac19f86ece98e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cae3644294078a1a12ac19f86ece98e">TIM_CR1_OPM_Pos</a>   (3U)</td></tr>
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<tr class="memitem:ga6fbbf98af8ecd146d7eae1874c0f115a" id="r_ga6fbbf98af8ecd146d7eae1874c0f115a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fbbf98af8ecd146d7eae1874c0f115a">TIM_CR1_OPM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cae3644294078a1a12ac19f86ece98e">TIM_CR1_OPM_Pos</a>)</td></tr>
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<tr class="separator:ga6fbbf98af8ecd146d7eae1874c0f115a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d3d1488296350af6d36fbbf71905d29" id="r_ga6d3d1488296350af6d36fbbf71905d29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d3d1488296350af6d36fbbf71905d29">TIM_CR1_OPM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6fbbf98af8ecd146d7eae1874c0f115a">TIM_CR1_OPM_Msk</a></td></tr>
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<tr class="memitem:ga161776b682c51f69581800125bf89a48" id="r_ga161776b682c51f69581800125bf89a48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga161776b682c51f69581800125bf89a48">TIM_CR1_DIR_Pos</a>   (4U)</td></tr>
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<tr class="memitem:gad5f92c5c62905feea73880ccbf6836aa" id="r_gad5f92c5c62905feea73880ccbf6836aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5f92c5c62905feea73880ccbf6836aa">TIM_CR1_DIR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga161776b682c51f69581800125bf89a48">TIM_CR1_DIR_Pos</a>)</td></tr>
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<tr class="memitem:gacea10770904af189f3aaeb97b45722aa" id="r_gacea10770904af189f3aaeb97b45722aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacea10770904af189f3aaeb97b45722aa">TIM_CR1_DIR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad5f92c5c62905feea73880ccbf6836aa">TIM_CR1_DIR_Msk</a></td></tr>
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<tr class="separator:gacea10770904af189f3aaeb97b45722aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8f425763d1d4c1483ca41a34cda2b2a" id="r_gaa8f425763d1d4c1483ca41a34cda2b2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8f425763d1d4c1483ca41a34cda2b2a">TIM_CR1_CMS_Pos</a>   (5U)</td></tr>
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<tr class="memitem:gaee4916455eb6d08d131dd9ae5b8013ee" id="r_gaee4916455eb6d08d131dd9ae5b8013ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee4916455eb6d08d131dd9ae5b8013ee">TIM_CR1_CMS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8f425763d1d4c1483ca41a34cda2b2a">TIM_CR1_CMS_Pos</a>)</td></tr>
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<tr class="memitem:ga352b3c389bde13dd6049de0afdd874f1" id="r_ga352b3c389bde13dd6049de0afdd874f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga352b3c389bde13dd6049de0afdd874f1">TIM_CR1_CMS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaee4916455eb6d08d131dd9ae5b8013ee">TIM_CR1_CMS_Msk</a></td></tr>
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<tr class="memitem:ga83ca6f7810aba73dc8c12f22092d97a2" id="r_ga83ca6f7810aba73dc8c12f22092d97a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83ca6f7810aba73dc8c12f22092d97a2">TIM_CR1_CMS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8f425763d1d4c1483ca41a34cda2b2a">TIM_CR1_CMS_Pos</a>)</td></tr>
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<tr class="memitem:gab3ee4adcde3c001d3b97d2eae1730ea9" id="r_gab3ee4adcde3c001d3b97d2eae1730ea9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3ee4adcde3c001d3b97d2eae1730ea9">TIM_CR1_CMS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8f425763d1d4c1483ca41a34cda2b2a">TIM_CR1_CMS_Pos</a>)</td></tr>
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<tr class="separator:gab3ee4adcde3c001d3b97d2eae1730ea9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga517317561e18e823ac75a35ae05b2c29" id="r_ga517317561e18e823ac75a35ae05b2c29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga517317561e18e823ac75a35ae05b2c29">TIM_CR1_ARPE_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga517317561e18e823ac75a35ae05b2c29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e508ecc8ac453c2999b2ca7885f24a8" id="r_ga4e508ecc8ac453c2999b2ca7885f24a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e508ecc8ac453c2999b2ca7885f24a8">TIM_CR1_ARPE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga517317561e18e823ac75a35ae05b2c29">TIM_CR1_ARPE_Pos</a>)</td></tr>
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<tr class="separator:ga4e508ecc8ac453c2999b2ca7885f24a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a3ad409f6b147cdcbafbfe29102f3fd" id="r_ga4a3ad409f6b147cdcbafbfe29102f3fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a3ad409f6b147cdcbafbfe29102f3fd">TIM_CR1_ARPE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e508ecc8ac453c2999b2ca7885f24a8">TIM_CR1_ARPE_Msk</a></td></tr>
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<tr class="separator:ga4a3ad409f6b147cdcbafbfe29102f3fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee3940e6580a2f924894f6f2f80ca856" id="r_gaee3940e6580a2f924894f6f2f80ca856"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee3940e6580a2f924894f6f2f80ca856">TIM_CR1_CKD_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaee3940e6580a2f924894f6f2f80ca856"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0894ca61f67f8ce59882c5a9645f68bd" id="r_ga0894ca61f67f8ce59882c5a9645f68bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0894ca61f67f8ce59882c5a9645f68bd">TIM_CR1_CKD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee3940e6580a2f924894f6f2f80ca856">TIM_CR1_CKD_Pos</a>)</td></tr>
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<tr class="memitem:gacacc4ff7e5b75fd2e4e6b672ccd33a72" id="r_gacacc4ff7e5b75fd2e4e6b672ccd33a72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacacc4ff7e5b75fd2e4e6b672ccd33a72">TIM_CR1_CKD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0894ca61f67f8ce59882c5a9645f68bd">TIM_CR1_CKD_Msk</a></td></tr>
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<tr class="memitem:ga458d536d82aa3db7d227b0f00b36808f" id="r_ga458d536d82aa3db7d227b0f00b36808f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga458d536d82aa3db7d227b0f00b36808f">TIM_CR1_CKD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee3940e6580a2f924894f6f2f80ca856">TIM_CR1_CKD_Pos</a>)</td></tr>
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<tr class="separator:ga458d536d82aa3db7d227b0f00b36808f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ff2d6c2c350e8b719a8ad49c9a6bcbe" id="r_ga7ff2d6c2c350e8b719a8ad49c9a6bcbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ff2d6c2c350e8b719a8ad49c9a6bcbe">TIM_CR1_CKD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee3940e6580a2f924894f6f2f80ca856">TIM_CR1_CKD_Pos</a>)</td></tr>
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<tr class="separator:ga7ff2d6c2c350e8b719a8ad49c9a6bcbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86a631cdfa58f91c731b709e27ee6d0d" id="r_ga86a631cdfa58f91c731b709e27ee6d0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86a631cdfa58f91c731b709e27ee6d0d">TIM_CR2_CCPC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga86a631cdfa58f91c731b709e27ee6d0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ccf78eb52ea83a81ed28e4815860df9" id="r_ga2ccf78eb52ea83a81ed28e4815860df9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ccf78eb52ea83a81ed28e4815860df9">TIM_CR2_CCPC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga86a631cdfa58f91c731b709e27ee6d0d">TIM_CR2_CCPC_Pos</a>)</td></tr>
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<tr class="memitem:gaae22c9c1197107d6fa629f419a29541e" id="r_gaae22c9c1197107d6fa629f419a29541e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae22c9c1197107d6fa629f419a29541e">TIM_CR2_CCPC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ccf78eb52ea83a81ed28e4815860df9">TIM_CR2_CCPC_Msk</a></td></tr>
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<tr class="separator:gaae22c9c1197107d6fa629f419a29541e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga944661589a5e77ab328c5df5569d967a" id="r_ga944661589a5e77ab328c5df5569d967a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga944661589a5e77ab328c5df5569d967a">TIM_CR2_CCUS_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga944661589a5e77ab328c5df5569d967a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac9908b05b59b90ba3e42124e7ad4347" id="r_gaac9908b05b59b90ba3e42124e7ad4347"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac9908b05b59b90ba3e42124e7ad4347">TIM_CR2_CCUS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga944661589a5e77ab328c5df5569d967a">TIM_CR2_CCUS_Pos</a>)</td></tr>
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<tr class="separator:gaac9908b05b59b90ba3e42124e7ad4347"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0328c1339b2b1633ef7a8db4c02d0d5" id="r_gaf0328c1339b2b1633ef7a8db4c02d0d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0328c1339b2b1633ef7a8db4c02d0d5">TIM_CR2_CCUS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac9908b05b59b90ba3e42124e7ad4347">TIM_CR2_CCUS_Msk</a></td></tr>
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<tr class="separator:gaf0328c1339b2b1633ef7a8db4c02d0d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga159a232ac14d50dc779712b5917e2ab5" id="r_ga159a232ac14d50dc779712b5917e2ab5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga159a232ac14d50dc779712b5917e2ab5">TIM_CR2_CCDS_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga159a232ac14d50dc779712b5917e2ab5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57abe8dfa0dc138ec4c9f4b0dd72299b" id="r_ga57abe8dfa0dc138ec4c9f4b0dd72299b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57abe8dfa0dc138ec4c9f4b0dd72299b">TIM_CR2_CCDS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga159a232ac14d50dc779712b5917e2ab5">TIM_CR2_CCDS_Pos</a>)</td></tr>
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<tr class="separator:ga57abe8dfa0dc138ec4c9f4b0dd72299b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade656832d3ec303a2a7a422638dd560e" id="r_gade656832d3ec303a2a7a422638dd560e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade656832d3ec303a2a7a422638dd560e">TIM_CR2_CCDS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57abe8dfa0dc138ec4c9f4b0dd72299b">TIM_CR2_CCDS_Msk</a></td></tr>
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<tr class="separator:gade656832d3ec303a2a7a422638dd560e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e8f8be33b5a8e48b67524b93e521a91" id="r_ga7e8f8be33b5a8e48b67524b93e521a91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8f8be33b5a8e48b67524b93e521a91">TIM_CR2_MMS_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga8f6c31bf38844218cb8c8ee98aef46c4" id="r_ga8f6c31bf38844218cb8c8ee98aef46c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f6c31bf38844218cb8c8ee98aef46c4">TIM_CR2_MMS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8f8be33b5a8e48b67524b93e521a91">TIM_CR2_MMS_Pos</a>)</td></tr>
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<tr class="memitem:gaaa6987d980e5c4c71c7d0faa1eb97a45" id="r_gaaa6987d980e5c4c71c7d0faa1eb97a45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa6987d980e5c4c71c7d0faa1eb97a45">TIM_CR2_MMS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f6c31bf38844218cb8c8ee98aef46c4">TIM_CR2_MMS_Msk</a></td></tr>
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<tr class="memitem:gaf3e55308e84106d6501201e66bd46ab6" id="r_gaf3e55308e84106d6501201e66bd46ab6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3e55308e84106d6501201e66bd46ab6">TIM_CR2_MMS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8f8be33b5a8e48b67524b93e521a91">TIM_CR2_MMS_Pos</a>)</td></tr>
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<tr class="memitem:ga4b1036929b0a4ba5bd5cced9b8e0f4c3" id="r_ga4b1036929b0a4ba5bd5cced9b8e0f4c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b1036929b0a4ba5bd5cced9b8e0f4c3">TIM_CR2_MMS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8f8be33b5a8e48b67524b93e521a91">TIM_CR2_MMS_Pos</a>)</td></tr>
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<tr class="separator:ga4b1036929b0a4ba5bd5cced9b8e0f4c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb74a815afdd856d51cfcf1ddf3fce6a" id="r_gacb74a815afdd856d51cfcf1ddf3fce6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb74a815afdd856d51cfcf1ddf3fce6a">TIM_CR2_MMS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e8f8be33b5a8e48b67524b93e521a91">TIM_CR2_MMS_Pos</a>)</td></tr>
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<tr class="separator:gacb74a815afdd856d51cfcf1ddf3fce6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga493bce1bb3c1243de9e4a9069c261e54" id="r_ga493bce1bb3c1243de9e4a9069c261e54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga493bce1bb3c1243de9e4a9069c261e54">TIM_CR2_TI1S_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga493bce1bb3c1243de9e4a9069c261e54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5aef7ed878a1f55f901cfdb25d3842ed" id="r_ga5aef7ed878a1f55f901cfdb25d3842ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5aef7ed878a1f55f901cfdb25d3842ed">TIM_CR2_TI1S_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga493bce1bb3c1243de9e4a9069c261e54">TIM_CR2_TI1S_Pos</a>)</td></tr>
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<tr class="separator:ga5aef7ed878a1f55f901cfdb25d3842ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad07504497b70af628fa1aee8fe7ef63c" id="r_gad07504497b70af628fa1aee8fe7ef63c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad07504497b70af628fa1aee8fe7ef63c">TIM_CR2_TI1S</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5aef7ed878a1f55f901cfdb25d3842ed">TIM_CR2_TI1S_Msk</a></td></tr>
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<tr class="separator:gad07504497b70af628fa1aee8fe7ef63c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5a3877d7270c1ddf25da016cc40ed21" id="r_gaa5a3877d7270c1ddf25da016cc40ed21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5a3877d7270c1ddf25da016cc40ed21">TIM_CR2_OIS1_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaa5a3877d7270c1ddf25da016cc40ed21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a08d73020c32fdaa4cc403f234792b1" id="r_ga2a08d73020c32fdaa4cc403f234792b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a08d73020c32fdaa4cc403f234792b1">TIM_CR2_OIS1_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5a3877d7270c1ddf25da016cc40ed21">TIM_CR2_OIS1_Pos</a>)</td></tr>
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<tr class="separator:ga2a08d73020c32fdaa4cc403f234792b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31b26bf058f88d771c33aff85ec89358" id="r_ga31b26bf058f88d771c33aff85ec89358"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31b26bf058f88d771c33aff85ec89358">TIM_CR2_OIS1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a08d73020c32fdaa4cc403f234792b1">TIM_CR2_OIS1_Msk</a></td></tr>
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<tr class="separator:ga31b26bf058f88d771c33aff85ec89358"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga820e5a3fe5cf4265bc144c8bd697d839" id="r_ga820e5a3fe5cf4265bc144c8bd697d839"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga820e5a3fe5cf4265bc144c8bd697d839">TIM_CR2_OIS1N_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga820e5a3fe5cf4265bc144c8bd697d839"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga146f505a2802837aa5799069416206bc" id="r_ga146f505a2802837aa5799069416206bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga146f505a2802837aa5799069416206bc">TIM_CR2_OIS1N_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga820e5a3fe5cf4265bc144c8bd697d839">TIM_CR2_OIS1N_Pos</a>)</td></tr>
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<tr class="separator:ga146f505a2802837aa5799069416206bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae61f8d54923999fffb6db381e81f2b69" id="r_gae61f8d54923999fffb6db381e81f2b69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae61f8d54923999fffb6db381e81f2b69">TIM_CR2_OIS1N</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga146f505a2802837aa5799069416206bc">TIM_CR2_OIS1N_Msk</a></td></tr>
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<tr class="memitem:gae7e01ac6a03a0903067f24c11540e2f0" id="r_gae7e01ac6a03a0903067f24c11540e2f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7e01ac6a03a0903067f24c11540e2f0">TIM_CR2_OIS2_Pos</a>   (10U)</td></tr>
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<tr class="separator:gae7e01ac6a03a0903067f24c11540e2f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb2bd7f9b2666aa8205981e1c7ddb446" id="r_gaeb2bd7f9b2666aa8205981e1c7ddb446"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb2bd7f9b2666aa8205981e1c7ddb446">TIM_CR2_OIS2_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae7e01ac6a03a0903067f24c11540e2f0">TIM_CR2_OIS2_Pos</a>)</td></tr>
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<tr class="separator:gaeb2bd7f9b2666aa8205981e1c7ddb446"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61467648a433bd887683b9a4760021fa" id="r_ga61467648a433bd887683b9a4760021fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61467648a433bd887683b9a4760021fa">TIM_CR2_OIS2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb2bd7f9b2666aa8205981e1c7ddb446">TIM_CR2_OIS2_Msk</a></td></tr>
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<tr class="separator:ga61467648a433bd887683b9a4760021fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60d70395acf83574da7c53ca126bdd4d" id="r_ga60d70395acf83574da7c53ca126bdd4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60d70395acf83574da7c53ca126bdd4d">TIM_CR2_OIS2N_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga60d70395acf83574da7c53ca126bdd4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga831140b7e39cda6b158041797be1ed37" id="r_ga831140b7e39cda6b158041797be1ed37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga831140b7e39cda6b158041797be1ed37">TIM_CR2_OIS2N_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga60d70395acf83574da7c53ca126bdd4d">TIM_CR2_OIS2N_Pos</a>)</td></tr>
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<tr class="separator:ga831140b7e39cda6b158041797be1ed37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga769146db660b832f3ef26f892b567bd4" id="r_ga769146db660b832f3ef26f892b567bd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga769146db660b832f3ef26f892b567bd4">TIM_CR2_OIS2N</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga831140b7e39cda6b158041797be1ed37">TIM_CR2_OIS2N_Msk</a></td></tr>
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<tr class="separator:ga769146db660b832f3ef26f892b567bd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf56da9ea6f82692b87573a45abab7447" id="r_gaf56da9ea6f82692b87573a45abab7447"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf56da9ea6f82692b87573a45abab7447">TIM_CR2_OIS3_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaf56da9ea6f82692b87573a45abab7447"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d5376e0d45eef0125cf133db5a7189a" id="r_ga4d5376e0d45eef0125cf133db5a7189a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d5376e0d45eef0125cf133db5a7189a">TIM_CR2_OIS3_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf56da9ea6f82692b87573a45abab7447">TIM_CR2_OIS3_Pos</a>)</td></tr>
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<tr class="separator:ga4d5376e0d45eef0125cf133db5a7189a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad974d7c91edf6f1bd47e892b3b6f7565" id="r_gad974d7c91edf6f1bd47e892b3b6f7565"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad974d7c91edf6f1bd47e892b3b6f7565">TIM_CR2_OIS3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d5376e0d45eef0125cf133db5a7189a">TIM_CR2_OIS3_Msk</a></td></tr>
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<tr class="separator:gad974d7c91edf6f1bd47e892b3b6f7565"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0849600336151b9eb3a0b405913bdd96" id="r_ga0849600336151b9eb3a0b405913bdd96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0849600336151b9eb3a0b405913bdd96">TIM_CR2_OIS3N_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0849600336151b9eb3a0b405913bdd96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1c25a6a16e1d0e6e3ae26eac52d8e08" id="r_gad1c25a6a16e1d0e6e3ae26eac52d8e08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1c25a6a16e1d0e6e3ae26eac52d8e08">TIM_CR2_OIS3N_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0849600336151b9eb3a0b405913bdd96">TIM_CR2_OIS3N_Pos</a>)</td></tr>
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<tr class="separator:gad1c25a6a16e1d0e6e3ae26eac52d8e08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20fb9b62a7e8d114fbd180abd9f8ceae" id="r_ga20fb9b62a7e8d114fbd180abd9f8ceae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20fb9b62a7e8d114fbd180abd9f8ceae">TIM_CR2_OIS3N</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad1c25a6a16e1d0e6e3ae26eac52d8e08">TIM_CR2_OIS3N_Msk</a></td></tr>
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<tr class="separator:ga20fb9b62a7e8d114fbd180abd9f8ceae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab672f9b97f3346360d6d740328a780f7" id="r_gab672f9b97f3346360d6d740328a780f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab672f9b97f3346360d6d740328a780f7">TIM_CR2_OIS4_Pos</a>   (14U)</td></tr>
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<tr class="separator:gab672f9b97f3346360d6d740328a780f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8644bc052bc6251ddf877b79a2ef6f48" id="r_ga8644bc052bc6251ddf877b79a2ef6f48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8644bc052bc6251ddf877b79a2ef6f48">TIM_CR2_OIS4_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab672f9b97f3346360d6d740328a780f7">TIM_CR2_OIS4_Pos</a>)</td></tr>
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<tr class="separator:ga8644bc052bc6251ddf877b79a2ef6f48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad644f2f4b26e46587abedc8d3164e56e" id="r_gad644f2f4b26e46587abedc8d3164e56e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad644f2f4b26e46587abedc8d3164e56e">TIM_CR2_OIS4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8644bc052bc6251ddf877b79a2ef6f48">TIM_CR2_OIS4_Msk</a></td></tr>
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<tr class="separator:gad644f2f4b26e46587abedc8d3164e56e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40905e02ce0cff7e929a9e78e7f46bcb" id="r_ga40905e02ce0cff7e929a9e78e7f46bcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40905e02ce0cff7e929a9e78e7f46bcb">TIM_SMCR_SMS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga40905e02ce0cff7e929a9e78e7f46bcb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34db507d082a38eb597b9a27bb659ace" id="r_ga34db507d082a38eb597b9a27bb659ace"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34db507d082a38eb597b9a27bb659ace">TIM_SMCR_SMS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga40905e02ce0cff7e929a9e78e7f46bcb">TIM_SMCR_SMS_Pos</a>)</td></tr>
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<tr class="memitem:gae92349731a6107e0f3a251b44a67c7ea" id="r_gae92349731a6107e0f3a251b44a67c7ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae92349731a6107e0f3a251b44a67c7ea">TIM_SMCR_SMS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34db507d082a38eb597b9a27bb659ace">TIM_SMCR_SMS_Msk</a></td></tr>
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<tr class="memitem:ga7d1ebece401aeb12abd466d2eafa78b2" id="r_ga7d1ebece401aeb12abd466d2eafa78b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d1ebece401aeb12abd466d2eafa78b2">TIM_SMCR_SMS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga40905e02ce0cff7e929a9e78e7f46bcb">TIM_SMCR_SMS_Pos</a>)</td></tr>
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<tr class="memitem:gaa980a3121ab6cda5a4a42b959da8421e" id="r_gaa980a3121ab6cda5a4a42b959da8421e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa980a3121ab6cda5a4a42b959da8421e">TIM_SMCR_SMS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga40905e02ce0cff7e929a9e78e7f46bcb">TIM_SMCR_SMS_Pos</a>)</td></tr>
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<tr class="memitem:ga63847fc3c71f582403e6301b1229c3ed" id="r_ga63847fc3c71f582403e6301b1229c3ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63847fc3c71f582403e6301b1229c3ed">TIM_SMCR_SMS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga40905e02ce0cff7e929a9e78e7f46bcb">TIM_SMCR_SMS_Pos</a>)</td></tr>
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<tr class="memitem:gafcaa765c40260187fc144e9e8138cc4b" id="r_gafcaa765c40260187fc144e9e8138cc4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcaa765c40260187fc144e9e8138cc4b">TIM_SMCR_TS_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga2aa1e898f53a002c3bddaa336e8888b1" id="r_ga2aa1e898f53a002c3bddaa336e8888b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2aa1e898f53a002c3bddaa336e8888b1">TIM_SMCR_TS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcaa765c40260187fc144e9e8138cc4b">TIM_SMCR_TS_Pos</a>)</td></tr>
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<tr class="memitem:ga8680e719bca2b672d850504220ae51fc" id="r_ga8680e719bca2b672d850504220ae51fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8680e719bca2b672d850504220ae51fc">TIM_SMCR_TS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2aa1e898f53a002c3bddaa336e8888b1">TIM_SMCR_TS_Msk</a></td></tr>
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<tr class="memitem:ga8d1f040f9259acb3c2fba7b0c7eb3d96" id="r_ga8d1f040f9259acb3c2fba7b0c7eb3d96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">TIM_SMCR_TS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcaa765c40260187fc144e9e8138cc4b">TIM_SMCR_TS_Pos</a>)</td></tr>
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<tr class="memitem:gacb82212fcc89166a43ff97542da9182d" id="r_gacb82212fcc89166a43ff97542da9182d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">TIM_SMCR_TS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcaa765c40260187fc144e9e8138cc4b">TIM_SMCR_TS_Pos</a>)</td></tr>
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<tr class="memitem:gacf0dbaf4a2ec8759f283f82a958ef6a8" id="r_gacf0dbaf4a2ec8759f283f82a958ef6a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">TIM_SMCR_TS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcaa765c40260187fc144e9e8138cc4b">TIM_SMCR_TS_Pos</a>)</td></tr>
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<tr class="separator:gacf0dbaf4a2ec8759f283f82a958ef6a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga904f429175a5ab1cfb78af1487d8b187" id="r_ga904f429175a5ab1cfb78af1487d8b187"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga904f429175a5ab1cfb78af1487d8b187">TIM_SMCR_MSM_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga904f429175a5ab1cfb78af1487d8b187"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafba3fb13f79aeb124c0f496bef33e4b2" id="r_gafba3fb13f79aeb124c0f496bef33e4b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafba3fb13f79aeb124c0f496bef33e4b2">TIM_SMCR_MSM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga904f429175a5ab1cfb78af1487d8b187">TIM_SMCR_MSM_Pos</a>)</td></tr>
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<tr class="separator:gafba3fb13f79aeb124c0f496bef33e4b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52101db4ca2c7b3003f1b16a49b2032c" id="r_ga52101db4ca2c7b3003f1b16a49b2032c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52101db4ca2c7b3003f1b16a49b2032c">TIM_SMCR_MSM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafba3fb13f79aeb124c0f496bef33e4b2">TIM_SMCR_MSM_Msk</a></td></tr>
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<tr class="separator:ga52101db4ca2c7b3003f1b16a49b2032c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbb493ebc2ecb4f3759eb97f9496a1dd" id="r_gafbb493ebc2ecb4f3759eb97f9496a1dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbb493ebc2ecb4f3759eb97f9496a1dd">TIM_SMCR_ETF_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga423e64cbb40275055b1b92a6d3ab0a12" id="r_ga423e64cbb40275055b1b92a6d3ab0a12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga423e64cbb40275055b1b92a6d3ab0a12">TIM_SMCR_ETF_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafbb493ebc2ecb4f3759eb97f9496a1dd">TIM_SMCR_ETF_Pos</a>)</td></tr>
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<tr class="separator:ga423e64cbb40275055b1b92a6d3ab0a12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2ed8b32d9eb8eea251bd1dac4f34668" id="r_gae2ed8b32d9eb8eea251bd1dac4f34668"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2ed8b32d9eb8eea251bd1dac4f34668">TIM_SMCR_ETF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga423e64cbb40275055b1b92a6d3ab0a12">TIM_SMCR_ETF_Msk</a></td></tr>
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<tr class="separator:gae2ed8b32d9eb8eea251bd1dac4f34668"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43745c2894cfc1e5ee619ac85d8d5a62" id="r_ga43745c2894cfc1e5ee619ac85d8d5a62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43745c2894cfc1e5ee619ac85d8d5a62">TIM_SMCR_ETF_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafbb493ebc2ecb4f3759eb97f9496a1dd">TIM_SMCR_ETF_Pos</a>)</td></tr>
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<tr class="separator:ga43745c2894cfc1e5ee619ac85d8d5a62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga661e6cce23553cf0ad3a60d8573b9a2c" id="r_ga661e6cce23553cf0ad3a60d8573b9a2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga661e6cce23553cf0ad3a60d8573b9a2c">TIM_SMCR_ETF_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafbb493ebc2ecb4f3759eb97f9496a1dd">TIM_SMCR_ETF_Pos</a>)</td></tr>
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<tr class="separator:ga661e6cce23553cf0ad3a60d8573b9a2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb5528381fb64ffbcc719de478391ae2" id="r_gafb5528381fb64ffbcc719de478391ae2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb5528381fb64ffbcc719de478391ae2">TIM_SMCR_ETF_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafbb493ebc2ecb4f3759eb97f9496a1dd">TIM_SMCR_ETF_Pos</a>)</td></tr>
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<tr class="separator:gafb5528381fb64ffbcc719de478391ae2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6082700946fc61a6f9d6209e258fcc14" id="r_ga6082700946fc61a6f9d6209e258fcc14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6082700946fc61a6f9d6209e258fcc14">TIM_SMCR_ETF_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafbb493ebc2ecb4f3759eb97f9496a1dd">TIM_SMCR_ETF_Pos</a>)</td></tr>
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<tr class="separator:ga6082700946fc61a6f9d6209e258fcc14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac0f059d7026ed8c8b644ec62d416323b" id="r_gac0f059d7026ed8c8b644ec62d416323b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0f059d7026ed8c8b644ec62d416323b">TIM_SMCR_ETPS_Pos</a>   (12U)</td></tr>
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<tr class="separator:gac0f059d7026ed8c8b644ec62d416323b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab319df2e386dc55f421f20a7f4c8a5d4" id="r_gab319df2e386dc55f421f20a7f4c8a5d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab319df2e386dc55f421f20a7f4c8a5d4">TIM_SMCR_ETPS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac0f059d7026ed8c8b644ec62d416323b">TIM_SMCR_ETPS_Pos</a>)</td></tr>
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<tr class="separator:gab319df2e386dc55f421f20a7f4c8a5d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ebb9e631876435e276211d88e797386" id="r_ga0ebb9e631876435e276211d88e797386"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ebb9e631876435e276211d88e797386">TIM_SMCR_ETPS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab319df2e386dc55f421f20a7f4c8a5d4">TIM_SMCR_ETPS_Msk</a></td></tr>
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<tr class="separator:ga0ebb9e631876435e276211d88e797386"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00b43cd09557a69ed10471ed76b228d8" id="r_ga00b43cd09557a69ed10471ed76b228d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00b43cd09557a69ed10471ed76b228d8">TIM_SMCR_ETPS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac0f059d7026ed8c8b644ec62d416323b">TIM_SMCR_ETPS_Pos</a>)</td></tr>
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<tr class="separator:ga00b43cd09557a69ed10471ed76b228d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf12f04862dbc92ca238d1518b27b16b" id="r_gabf12f04862dbc92ca238d1518b27b16b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf12f04862dbc92ca238d1518b27b16b">TIM_SMCR_ETPS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac0f059d7026ed8c8b644ec62d416323b">TIM_SMCR_ETPS_Pos</a>)</td></tr>
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<tr class="separator:gabf12f04862dbc92ca238d1518b27b16b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaef2d4adcfd438a4d19ea54ef7031ed0" id="r_gaaef2d4adcfd438a4d19ea54ef7031ed0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaef2d4adcfd438a4d19ea54ef7031ed0">TIM_SMCR_ECE_Pos</a>   (14U)</td></tr>
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<tr class="separator:gaaef2d4adcfd438a4d19ea54ef7031ed0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7322ee5f5ebf6e9c70b7ffe4afe1fa3d" id="r_ga7322ee5f5ebf6e9c70b7ffe4afe1fa3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7322ee5f5ebf6e9c70b7ffe4afe1fa3d">TIM_SMCR_ECE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaef2d4adcfd438a4d19ea54ef7031ed0">TIM_SMCR_ECE_Pos</a>)</td></tr>
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<tr class="separator:ga7322ee5f5ebf6e9c70b7ffe4afe1fa3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga331a1d5f39d5f47b5409054e693fc651" id="r_ga331a1d5f39d5f47b5409054e693fc651"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga331a1d5f39d5f47b5409054e693fc651">TIM_SMCR_ECE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7322ee5f5ebf6e9c70b7ffe4afe1fa3d">TIM_SMCR_ECE_Msk</a></td></tr>
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<tr class="separator:ga331a1d5f39d5f47b5409054e693fc651"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada5b5864ba9fe393be0bcd168e3cf439" id="r_gada5b5864ba9fe393be0bcd168e3cf439"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada5b5864ba9fe393be0bcd168e3cf439">TIM_SMCR_ETP_Pos</a>   (15U)</td></tr>
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<tr class="separator:gada5b5864ba9fe393be0bcd168e3cf439"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77f8984e6ac3422454b0a586a2b973e3" id="r_ga77f8984e6ac3422454b0a586a2b973e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77f8984e6ac3422454b0a586a2b973e3">TIM_SMCR_ETP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada5b5864ba9fe393be0bcd168e3cf439">TIM_SMCR_ETP_Pos</a>)</td></tr>
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<tr class="separator:ga77f8984e6ac3422454b0a586a2b973e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a5f335c3d7a4f82d1e91dc1511e3322" id="r_ga2a5f335c3d7a4f82d1e91dc1511e3322"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a5f335c3d7a4f82d1e91dc1511e3322">TIM_SMCR_ETP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga77f8984e6ac3422454b0a586a2b973e3">TIM_SMCR_ETP_Msk</a></td></tr>
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<tr class="memitem:ga177019595c3a462255e7ea4a64cde2a6" id="r_ga177019595c3a462255e7ea4a64cde2a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga177019595c3a462255e7ea4a64cde2a6">TIM_DIER_UIE_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga177019595c3a462255e7ea4a64cde2a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab47c8f36981860ff345f922f6ba02662" id="r_gab47c8f36981860ff345f922f6ba02662"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab47c8f36981860ff345f922f6ba02662">TIM_DIER_UIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga177019595c3a462255e7ea4a64cde2a6">TIM_DIER_UIE_Pos</a>)</td></tr>
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<tr class="memitem:ga5c6d3e0495e6c06da4bdd0ad8995a32b" id="r_ga5c6d3e0495e6c06da4bdd0ad8995a32b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c6d3e0495e6c06da4bdd0ad8995a32b">TIM_DIER_UIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab47c8f36981860ff345f922f6ba02662">TIM_DIER_UIE_Msk</a></td></tr>
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<tr class="memitem:ga0ca1de767246ce92802bca84ae436364" id="r_ga0ca1de767246ce92802bca84ae436364"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ca1de767246ce92802bca84ae436364">TIM_DIER_CC1IE_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga9cdfb1dc6e58a5f1ba2e4379b02f8be7" id="r_ga9cdfb1dc6e58a5f1ba2e4379b02f8be7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cdfb1dc6e58a5f1ba2e4379b02f8be7">TIM_DIER_CC1IE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ca1de767246ce92802bca84ae436364">TIM_DIER_CC1IE_Pos</a>)</td></tr>
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<tr class="memitem:ga1ba7f7ca97eeaf6cc23cd6765c6bf678" id="r_ga1ba7f7ca97eeaf6cc23cd6765c6bf678"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ba7f7ca97eeaf6cc23cd6765c6bf678">TIM_DIER_CC1IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9cdfb1dc6e58a5f1ba2e4379b02f8be7">TIM_DIER_CC1IE_Msk</a></td></tr>
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<tr class="separator:ga1ba7f7ca97eeaf6cc23cd6765c6bf678"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5dcc06e124f3980a1d8a949787acc90" id="r_gab5dcc06e124f3980a1d8a949787acc90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5dcc06e124f3980a1d8a949787acc90">TIM_DIER_CC2IE_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga5db58d01a8e92e3403fb44ecc09e5e5e" id="r_ga5db58d01a8e92e3403fb44ecc09e5e5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5db58d01a8e92e3403fb44ecc09e5e5e">TIM_DIER_CC2IE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5dcc06e124f3980a1d8a949787acc90">TIM_DIER_CC2IE_Pos</a>)</td></tr>
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<tr class="separator:ga5db58d01a8e92e3403fb44ecc09e5e5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga757c59b690770adebf33e20d3d9dec15" id="r_ga757c59b690770adebf33e20d3d9dec15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga757c59b690770adebf33e20d3d9dec15">TIM_DIER_CC2IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5db58d01a8e92e3403fb44ecc09e5e5e">TIM_DIER_CC2IE_Msk</a></td></tr>
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<tr class="separator:ga757c59b690770adebf33e20d3d9dec15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3a26f9fd83be5be909cdbbf59fb138d" id="r_gae3a26f9fd83be5be909cdbbf59fb138d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3a26f9fd83be5be909cdbbf59fb138d">TIM_DIER_CC3IE_Pos</a>   (3U)</td></tr>
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<tr class="memitem:ga78bd5f90a0f2d2d34132ef5568e18779" id="r_ga78bd5f90a0f2d2d34132ef5568e18779"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78bd5f90a0f2d2d34132ef5568e18779">TIM_DIER_CC3IE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3a26f9fd83be5be909cdbbf59fb138d">TIM_DIER_CC3IE_Pos</a>)</td></tr>
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<tr class="separator:ga78bd5f90a0f2d2d34132ef5568e18779"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4edf003f04bcf250bddf5ed284201c2e" id="r_ga4edf003f04bcf250bddf5ed284201c2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4edf003f04bcf250bddf5ed284201c2e">TIM_DIER_CC3IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga78bd5f90a0f2d2d34132ef5568e18779">TIM_DIER_CC3IE_Msk</a></td></tr>
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<tr class="separator:ga4edf003f04bcf250bddf5ed284201c2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac98032297756f6e341f92fa243278e98" id="r_gac98032297756f6e341f92fa243278e98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac98032297756f6e341f92fa243278e98">TIM_DIER_CC4IE_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga66b5230621c6d2f44c44ff672a07ffaf" id="r_ga66b5230621c6d2f44c44ff672a07ffaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66b5230621c6d2f44c44ff672a07ffaf">TIM_DIER_CC4IE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac98032297756f6e341f92fa243278e98">TIM_DIER_CC4IE_Pos</a>)</td></tr>
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<tr class="memitem:ga6ad0f562a014572793b49fe87184338b" id="r_ga6ad0f562a014572793b49fe87184338b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad0f562a014572793b49fe87184338b">TIM_DIER_CC4IE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga66b5230621c6d2f44c44ff672a07ffaf">TIM_DIER_CC4IE_Msk</a></td></tr>
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<tr class="separator:ga6ad0f562a014572793b49fe87184338b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f87983f6cb8450b975286079c19ff29" id="r_ga2f87983f6cb8450b975286079c19ff29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f87983f6cb8450b975286079c19ff29">TIM_DIER_COMIE_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga2f87983f6cb8450b975286079c19ff29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe9af339214666b3251fff9598277b1f" id="r_gabe9af339214666b3251fff9598277b1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe9af339214666b3251fff9598277b1f">TIM_DIER_COMIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f87983f6cb8450b975286079c19ff29">TIM_DIER_COMIE_Pos</a>)</td></tr>
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<tr class="separator:gabe9af339214666b3251fff9598277b1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade8a374e04740aac1ece248b868522fe" id="r_gade8a374e04740aac1ece248b868522fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade8a374e04740aac1ece248b868522fe">TIM_DIER_COMIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe9af339214666b3251fff9598277b1f">TIM_DIER_COMIE_Msk</a></td></tr>
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<tr class="memitem:gaa348f21e19ac18be00577cc2844941d6" id="r_gaa348f21e19ac18be00577cc2844941d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa348f21e19ac18be00577cc2844941d6">TIM_DIER_TIE_Pos</a>   (6U)</td></tr>
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<tr class="memitem:gadf3e781c907ca4774fae5c089e445f5a" id="r_gadf3e781c907ca4774fae5c089e445f5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf3e781c907ca4774fae5c089e445f5a">TIM_DIER_TIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa348f21e19ac18be00577cc2844941d6">TIM_DIER_TIE_Pos</a>)</td></tr>
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<tr class="separator:gadf3e781c907ca4774fae5c089e445f5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa755fef2c4e96c63f2ea1cd9a32f956a" id="r_gaa755fef2c4e96c63f2ea1cd9a32f956a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa755fef2c4e96c63f2ea1cd9a32f956a">TIM_DIER_TIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadf3e781c907ca4774fae5c089e445f5a">TIM_DIER_TIE_Msk</a></td></tr>
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<tr class="separator:gaa755fef2c4e96c63f2ea1cd9a32f956a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68f1acf20b177e729494b03d389fc879" id="r_ga68f1acf20b177e729494b03d389fc879"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68f1acf20b177e729494b03d389fc879">TIM_DIER_BIE_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga68f1acf20b177e729494b03d389fc879"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad054244795a6fcd3bc1ff35e4c651982" id="r_gad054244795a6fcd3bc1ff35e4c651982"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad054244795a6fcd3bc1ff35e4c651982">TIM_DIER_BIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68f1acf20b177e729494b03d389fc879">TIM_DIER_BIE_Pos</a>)</td></tr>
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<tr class="separator:gad054244795a6fcd3bc1ff35e4c651982"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1fcb0d6d9fb7486a5901032fd81aef6a" id="r_ga1fcb0d6d9fb7486a5901032fd81aef6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fcb0d6d9fb7486a5901032fd81aef6a">TIM_DIER_BIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad054244795a6fcd3bc1ff35e4c651982">TIM_DIER_BIE_Msk</a></td></tr>
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<tr class="memitem:ga5078f4d6a9f542a502194cd1499f90a3" id="r_ga5078f4d6a9f542a502194cd1499f90a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5078f4d6a9f542a502194cd1499f90a3">TIM_DIER_UDE_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga5078f4d6a9f542a502194cd1499f90a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66544291fb58960e9f4018509a4dee09" id="r_ga66544291fb58960e9f4018509a4dee09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66544291fb58960e9f4018509a4dee09">TIM_DIER_UDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5078f4d6a9f542a502194cd1499f90a3">TIM_DIER_UDE_Pos</a>)</td></tr>
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<tr class="separator:ga66544291fb58960e9f4018509a4dee09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9f47792b1c2f123464a2955f445c811" id="r_gab9f47792b1c2f123464a2955f445c811"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9f47792b1c2f123464a2955f445c811">TIM_DIER_UDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga66544291fb58960e9f4018509a4dee09">TIM_DIER_UDE_Msk</a></td></tr>
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<tr class="memitem:ga15a2b408f82591fcffc36fb1b71e0ee4" id="r_ga15a2b408f82591fcffc36fb1b71e0ee4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15a2b408f82591fcffc36fb1b71e0ee4">TIM_DIER_CC1DE_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga15a2b408f82591fcffc36fb1b71e0ee4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40247fa7b772b644df2754b599e71e22" id="r_ga40247fa7b772b644df2754b599e71e22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40247fa7b772b644df2754b599e71e22">TIM_DIER_CC1DE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga15a2b408f82591fcffc36fb1b71e0ee4">TIM_DIER_CC1DE_Pos</a>)</td></tr>
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<tr class="separator:ga40247fa7b772b644df2754b599e71e22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae181bb16ec916aba8ba86f58f745fdfd" id="r_gae181bb16ec916aba8ba86f58f745fdfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae181bb16ec916aba8ba86f58f745fdfd">TIM_DIER_CC1DE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga40247fa7b772b644df2754b599e71e22">TIM_DIER_CC1DE_Msk</a></td></tr>
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<tr class="separator:gae181bb16ec916aba8ba86f58f745fdfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga567e807487bdcf4d7db0c50c02154420" id="r_ga567e807487bdcf4d7db0c50c02154420"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga567e807487bdcf4d7db0c50c02154420">TIM_DIER_CC2DE_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga567e807487bdcf4d7db0c50c02154420"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74a3a6d017bcc45df793e9b1d19c013d" id="r_ga74a3a6d017bcc45df793e9b1d19c013d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74a3a6d017bcc45df793e9b1d19c013d">TIM_DIER_CC2DE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga567e807487bdcf4d7db0c50c02154420">TIM_DIER_CC2DE_Pos</a>)</td></tr>
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<tr class="separator:ga74a3a6d017bcc45df793e9b1d19c013d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58f97064991095b28c91028ca3cca28e" id="r_ga58f97064991095b28c91028ca3cca28e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58f97064991095b28c91028ca3cca28e">TIM_DIER_CC2DE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga74a3a6d017bcc45df793e9b1d19c013d">TIM_DIER_CC2DE_Msk</a></td></tr>
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<tr class="separator:ga58f97064991095b28c91028ca3cca28e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e08651981fedc16b1ed9925c4f84373" id="r_ga3e08651981fedc16b1ed9925c4f84373"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e08651981fedc16b1ed9925c4f84373">TIM_DIER_CC3DE_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga3e08651981fedc16b1ed9925c4f84373"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade4d3ce6b292c28e2fd7c9e9bd8f6ab6" id="r_gade4d3ce6b292c28e2fd7c9e9bd8f6ab6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade4d3ce6b292c28e2fd7c9e9bd8f6ab6">TIM_DIER_CC3DE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e08651981fedc16b1ed9925c4f84373">TIM_DIER_CC3DE_Pos</a>)</td></tr>
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<tr class="memitem:ga1567bff5dc0564b26a8b3cff1f0fe0a4" id="r_ga1567bff5dc0564b26a8b3cff1f0fe0a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1567bff5dc0564b26a8b3cff1f0fe0a4">TIM_DIER_CC3DE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gade4d3ce6b292c28e2fd7c9e9bd8f6ab6">TIM_DIER_CC3DE_Msk</a></td></tr>
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<tr class="separator:ga1567bff5dc0564b26a8b3cff1f0fe0a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c72cedbdd1f3c2390f25bb181b76b39" id="r_ga4c72cedbdd1f3c2390f25bb181b76b39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c72cedbdd1f3c2390f25bb181b76b39">TIM_DIER_CC4DE_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga4c72cedbdd1f3c2390f25bb181b76b39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad81dbfb6c7c8907ec2debd892b48e9ba" id="r_gad81dbfb6c7c8907ec2debd892b48e9ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad81dbfb6c7c8907ec2debd892b48e9ba">TIM_DIER_CC4DE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c72cedbdd1f3c2390f25bb181b76b39">TIM_DIER_CC4DE_Pos</a>)</td></tr>
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<tr class="separator:gad81dbfb6c7c8907ec2debd892b48e9ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaba034412c54fa07024e516492748614" id="r_gaaba034412c54fa07024e516492748614"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaba034412c54fa07024e516492748614">TIM_DIER_CC4DE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad81dbfb6c7c8907ec2debd892b48e9ba">TIM_DIER_CC4DE_Msk</a></td></tr>
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<tr class="separator:gaaba034412c54fa07024e516492748614"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0311dbc32a6e1b38dd0e6a5a7ae6c4ed" id="r_ga0311dbc32a6e1b38dd0e6a5a7ae6c4ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0311dbc32a6e1b38dd0e6a5a7ae6c4ed">TIM_DIER_COMDE_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0311dbc32a6e1b38dd0e6a5a7ae6c4ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ed00410aeabe33fef5feebbaec1a0a6" id="r_ga9ed00410aeabe33fef5feebbaec1a0a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ed00410aeabe33fef5feebbaec1a0a6">TIM_DIER_COMDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0311dbc32a6e1b38dd0e6a5a7ae6c4ed">TIM_DIER_COMDE_Pos</a>)</td></tr>
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<tr class="separator:ga9ed00410aeabe33fef5feebbaec1a0a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79c3fab9d33de953a0a7f7d6516c73bc" id="r_ga79c3fab9d33de953a0a7f7d6516c73bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79c3fab9d33de953a0a7f7d6516c73bc">TIM_DIER_COMDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ed00410aeabe33fef5feebbaec1a0a6">TIM_DIER_COMDE_Msk</a></td></tr>
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<tr class="separator:ga79c3fab9d33de953a0a7f7d6516c73bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b1014527f96f63edc7dfa3b79297557" id="r_ga8b1014527f96f63edc7dfa3b79297557"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b1014527f96f63edc7dfa3b79297557">TIM_DIER_TDE_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga8b1014527f96f63edc7dfa3b79297557"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbd5aee3b64fd928be288ae86b4fa020" id="r_gadbd5aee3b64fd928be288ae86b4fa020"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbd5aee3b64fd928be288ae86b4fa020">TIM_DIER_TDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b1014527f96f63edc7dfa3b79297557">TIM_DIER_TDE_Pos</a>)</td></tr>
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<tr class="separator:gadbd5aee3b64fd928be288ae86b4fa020"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a752d4295f100708df9b8be5a7f439d" id="r_ga5a752d4295f100708df9b8be5a7f439d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a752d4295f100708df9b8be5a7f439d">TIM_DIER_TDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadbd5aee3b64fd928be288ae86b4fa020">TIM_DIER_TDE_Msk</a></td></tr>
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<tr class="separator:ga5a752d4295f100708df9b8be5a7f439d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga558df2cd4bfe780f9381149b4e0eab19" id="r_ga558df2cd4bfe780f9381149b4e0eab19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga558df2cd4bfe780f9381149b4e0eab19">TIM_SR_UIF_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga558df2cd4bfe780f9381149b4e0eab19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a713154f9408c97cd7b193f23affab2" id="r_ga7a713154f9408c97cd7b193f23affab2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a713154f9408c97cd7b193f23affab2">TIM_SR_UIF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga558df2cd4bfe780f9381149b4e0eab19">TIM_SR_UIF_Pos</a>)</td></tr>
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<tr class="separator:ga7a713154f9408c97cd7b193f23affab2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8c03fabc10654d2a3f76ea40fcdbde6" id="r_gac8c03fabc10654d2a3f76ea40fcdbde6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8c03fabc10654d2a3f76ea40fcdbde6">TIM_SR_UIF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a713154f9408c97cd7b193f23affab2">TIM_SR_UIF_Msk</a></td></tr>
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<tr class="separator:gac8c03fabc10654d2a3f76ea40fcdbde6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61c518804171ea0813d7dd5702adde4c" id="r_ga61c518804171ea0813d7dd5702adde4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61c518804171ea0813d7dd5702adde4c">TIM_SR_CC1IF_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga61c518804171ea0813d7dd5702adde4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ce1be8a563567338d87977ddc0aa2c5" id="r_ga2ce1be8a563567338d87977ddc0aa2c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ce1be8a563567338d87977ddc0aa2c5">TIM_SR_CC1IF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61c518804171ea0813d7dd5702adde4c">TIM_SR_CC1IF_Pos</a>)</td></tr>
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<tr class="separator:ga2ce1be8a563567338d87977ddc0aa2c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga449a61344a97608d85384c29f003c0e9" id="r_ga449a61344a97608d85384c29f003c0e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga449a61344a97608d85384c29f003c0e9">TIM_SR_CC1IF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ce1be8a563567338d87977ddc0aa2c5">TIM_SR_CC1IF_Msk</a></td></tr>
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<tr class="separator:ga449a61344a97608d85384c29f003c0e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef088105198e8850e542fc8e0fd362ae" id="r_gaef088105198e8850e542fc8e0fd362ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef088105198e8850e542fc8e0fd362ae">TIM_SR_CC2IF_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaef088105198e8850e542fc8e0fd362ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac970c8ac8779185ba8f313e280c40902" id="r_gac970c8ac8779185ba8f313e280c40902"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac970c8ac8779185ba8f313e280c40902">TIM_SR_CC2IF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef088105198e8850e542fc8e0fd362ae">TIM_SR_CC2IF_Pos</a>)</td></tr>
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<tr class="separator:gac970c8ac8779185ba8f313e280c40902"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25a48bf099467169aa50464fbf462bd8" id="r_ga25a48bf099467169aa50464fbf462bd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25a48bf099467169aa50464fbf462bd8">TIM_SR_CC2IF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac970c8ac8779185ba8f313e280c40902">TIM_SR_CC2IF_Msk</a></td></tr>
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<tr class="separator:ga25a48bf099467169aa50464fbf462bd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9d4e629577fc5a15dd907a0a2d6f43a" id="r_gad9d4e629577fc5a15dd907a0a2d6f43a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9d4e629577fc5a15dd907a0a2d6f43a">TIM_SR_CC3IF_Pos</a>   (3U)</td></tr>
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<tr class="separator:gad9d4e629577fc5a15dd907a0a2d6f43a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77b2e69acc55c8d12f789fc5bf9a5f54" id="r_ga77b2e69acc55c8d12f789fc5bf9a5f54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77b2e69acc55c8d12f789fc5bf9a5f54">TIM_SR_CC3IF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9d4e629577fc5a15dd907a0a2d6f43a">TIM_SR_CC3IF_Pos</a>)</td></tr>
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<tr class="separator:ga77b2e69acc55c8d12f789fc5bf9a5f54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3cf234a1059c0a04799e88382cdc0f2" id="r_gad3cf234a1059c0a04799e88382cdc0f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3cf234a1059c0a04799e88382cdc0f2">TIM_SR_CC3IF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga77b2e69acc55c8d12f789fc5bf9a5f54">TIM_SR_CC3IF_Msk</a></td></tr>
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<tr class="separator:gad3cf234a1059c0a04799e88382cdc0f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f5a114b99523c3f6766951ab28026f9" id="r_ga1f5a114b99523c3f6766951ab28026f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f5a114b99523c3f6766951ab28026f9">TIM_SR_CC4IF_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga1f5a114b99523c3f6766951ab28026f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62087fa2c5fa8166d6b4be7e32c60442" id="r_ga62087fa2c5fa8166d6b4be7e32c60442"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62087fa2c5fa8166d6b4be7e32c60442">TIM_SR_CC4IF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1f5a114b99523c3f6766951ab28026f9">TIM_SR_CC4IF_Pos</a>)</td></tr>
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<tr class="separator:ga62087fa2c5fa8166d6b4be7e32c60442"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacade8a06303bf216bfb03140c7e16cac" id="r_gacade8a06303bf216bfb03140c7e16cac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacade8a06303bf216bfb03140c7e16cac">TIM_SR_CC4IF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga62087fa2c5fa8166d6b4be7e32c60442">TIM_SR_CC4IF_Msk</a></td></tr>
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<tr class="separator:gacade8a06303bf216bfb03140c7e16cac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa44f0ec2b4134ef80ce28d7a878772af" id="r_gaa44f0ec2b4134ef80ce28d7a878772af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa44f0ec2b4134ef80ce28d7a878772af">TIM_SR_COMIF_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaa44f0ec2b4134ef80ce28d7a878772af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8af1c1f93eee747aaa7fdc3a5aeb5337" id="r_ga8af1c1f93eee747aaa7fdc3a5aeb5337"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8af1c1f93eee747aaa7fdc3a5aeb5337">TIM_SR_COMIF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa44f0ec2b4134ef80ce28d7a878772af">TIM_SR_COMIF_Pos</a>)</td></tr>
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<tr class="separator:ga8af1c1f93eee747aaa7fdc3a5aeb5337"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91775c029171c4585e9cca6ebf1cd57a" id="r_ga91775c029171c4585e9cca6ebf1cd57a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91775c029171c4585e9cca6ebf1cd57a">TIM_SR_COMIF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8af1c1f93eee747aaa7fdc3a5aeb5337">TIM_SR_COMIF_Msk</a></td></tr>
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<tr class="separator:ga91775c029171c4585e9cca6ebf1cd57a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc65e5e222f7625dda796d36e0c0d563" id="r_gabc65e5e222f7625dda796d36e0c0d563"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc65e5e222f7625dda796d36e0c0d563">TIM_SR_TIF_Pos</a>   (6U)</td></tr>
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<tr class="separator:gabc65e5e222f7625dda796d36e0c0d563"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ad9bed9cae745d41a987675821b202a" id="r_ga6ad9bed9cae745d41a987675821b202a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad9bed9cae745d41a987675821b202a">TIM_SR_TIF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc65e5e222f7625dda796d36e0c0d563">TIM_SR_TIF_Pos</a>)</td></tr>
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<tr class="separator:ga6ad9bed9cae745d41a987675821b202a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c8b16f3ced6ec03e9001276b134846e" id="r_ga7c8b16f3ced6ec03e9001276b134846e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c8b16f3ced6ec03e9001276b134846e">TIM_SR_TIF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ad9bed9cae745d41a987675821b202a">TIM_SR_TIF_Msk</a></td></tr>
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<tr class="separator:ga7c8b16f3ced6ec03e9001276b134846e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61bc5fc1383047eb82dd66cb44a52ff3" id="r_ga61bc5fc1383047eb82dd66cb44a52ff3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61bc5fc1383047eb82dd66cb44a52ff3">TIM_SR_BIF_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga61bc5fc1383047eb82dd66cb44a52ff3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga778093c3983d94f88d6da49de96c9826" id="r_ga778093c3983d94f88d6da49de96c9826"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga778093c3983d94f88d6da49de96c9826">TIM_SR_BIF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61bc5fc1383047eb82dd66cb44a52ff3">TIM_SR_BIF_Pos</a>)</td></tr>
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<tr class="separator:ga778093c3983d94f88d6da49de96c9826"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d52cd5a57c9a26b0d993c93d9875097" id="r_ga6d52cd5a57c9a26b0d993c93d9875097"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d52cd5a57c9a26b0d993c93d9875097">TIM_SR_BIF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga778093c3983d94f88d6da49de96c9826">TIM_SR_BIF_Msk</a></td></tr>
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<tr class="separator:ga6d52cd5a57c9a26b0d993c93d9875097"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d3dd0efe5e5b6c21a10091bbb61d2c6" id="r_ga6d3dd0efe5e5b6c21a10091bbb61d2c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d3dd0efe5e5b6c21a10091bbb61d2c6">TIM_SR_CC1OF_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga6d3dd0efe5e5b6c21a10091bbb61d2c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae38020b672e525cf31f3a21a01ee680f" id="r_gae38020b672e525cf31f3a21a01ee680f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae38020b672e525cf31f3a21a01ee680f">TIM_SR_CC1OF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d3dd0efe5e5b6c21a10091bbb61d2c6">TIM_SR_CC1OF_Pos</a>)</td></tr>
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<tr class="separator:gae38020b672e525cf31f3a21a01ee680f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga819c4b27f8fa99b537c4407521f9780c" id="r_ga819c4b27f8fa99b537c4407521f9780c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga819c4b27f8fa99b537c4407521f9780c">TIM_SR_CC1OF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae38020b672e525cf31f3a21a01ee680f">TIM_SR_CC1OF_Msk</a></td></tr>
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<tr class="separator:ga819c4b27f8fa99b537c4407521f9780c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a0188211bdf0406c2712d92e7d644c3" id="r_ga9a0188211bdf0406c2712d92e7d644c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a0188211bdf0406c2712d92e7d644c3">TIM_SR_CC2OF_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga9a0188211bdf0406c2712d92e7d644c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga772886dce929789865cf7053728488d4" id="r_ga772886dce929789865cf7053728488d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga772886dce929789865cf7053728488d4">TIM_SR_CC2OF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a0188211bdf0406c2712d92e7d644c3">TIM_SR_CC2OF_Pos</a>)</td></tr>
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<tr class="separator:ga772886dce929789865cf7053728488d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b7798da5863d559ea9a642af6658050" id="r_ga3b7798da5863d559ea9a642af6658050"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b7798da5863d559ea9a642af6658050">TIM_SR_CC2OF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga772886dce929789865cf7053728488d4">TIM_SR_CC2OF_Msk</a></td></tr>
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<tr class="separator:ga3b7798da5863d559ea9a642af6658050"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga131fff23ae52a9ae98267f06f35b9abb" id="r_ga131fff23ae52a9ae98267f06f35b9abb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga131fff23ae52a9ae98267f06f35b9abb">TIM_SR_CC3OF_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga131fff23ae52a9ae98267f06f35b9abb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36d466016b806136b3e0251363e7e38d" id="r_ga36d466016b806136b3e0251363e7e38d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36d466016b806136b3e0251363e7e38d">TIM_SR_CC3OF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga131fff23ae52a9ae98267f06f35b9abb">TIM_SR_CC3OF_Pos</a>)</td></tr>
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<tr class="separator:ga36d466016b806136b3e0251363e7e38d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7a2d4c831eb641ba082156e41d03358" id="r_gaf7a2d4c831eb641ba082156e41d03358"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7a2d4c831eb641ba082156e41d03358">TIM_SR_CC3OF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36d466016b806136b3e0251363e7e38d">TIM_SR_CC3OF_Msk</a></td></tr>
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<tr class="separator:gaf7a2d4c831eb641ba082156e41d03358"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa692368f903e95550c110a8cdbece996" id="r_gaa692368f903e95550c110a8cdbece996"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa692368f903e95550c110a8cdbece996">TIM_SR_CC4OF_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaa692368f903e95550c110a8cdbece996"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36421d430d4fd0d34d02444b5da804b5" id="r_ga36421d430d4fd0d34d02444b5da804b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36421d430d4fd0d34d02444b5da804b5">TIM_SR_CC4OF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa692368f903e95550c110a8cdbece996">TIM_SR_CC4OF_Pos</a>)</td></tr>
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<tr class="separator:ga36421d430d4fd0d34d02444b5da804b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81ba979e8309b66808e06e4de34bc740" id="r_ga81ba979e8309b66808e06e4de34bc740"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81ba979e8309b66808e06e4de34bc740">TIM_SR_CC4OF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36421d430d4fd0d34d02444b5da804b5">TIM_SR_CC4OF_Msk</a></td></tr>
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<tr class="separator:ga81ba979e8309b66808e06e4de34bc740"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71cd5b80d699afa003cb407a74dc0593" id="r_ga71cd5b80d699afa003cb407a74dc0593"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71cd5b80d699afa003cb407a74dc0593">TIM_EGR_UG_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga71cd5b80d699afa003cb407a74dc0593"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ff315da1492025d608eb2c71e1e4462" id="r_ga5ff315da1492025d608eb2c71e1e4462"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ff315da1492025d608eb2c71e1e4462">TIM_EGR_UG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71cd5b80d699afa003cb407a74dc0593">TIM_EGR_UG_Pos</a>)</td></tr>
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<tr class="separator:ga5ff315da1492025d608eb2c71e1e4462"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16f52a8e9aad153223405b965566ae91" id="r_ga16f52a8e9aad153223405b965566ae91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16f52a8e9aad153223405b965566ae91">TIM_EGR_UG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ff315da1492025d608eb2c71e1e4462">TIM_EGR_UG_Msk</a></td></tr>
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<tr class="separator:ga16f52a8e9aad153223405b965566ae91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee06d20dfa5d132d221a28193dedd211" id="r_gaee06d20dfa5d132d221a28193dedd211"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee06d20dfa5d132d221a28193dedd211">TIM_EGR_CC1G_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaee06d20dfa5d132d221a28193dedd211"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba7a2fa9e7341df84a32cf5d54e61ad3" id="r_gaba7a2fa9e7341df84a32cf5d54e61ad3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba7a2fa9e7341df84a32cf5d54e61ad3">TIM_EGR_CC1G_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee06d20dfa5d132d221a28193dedd211">TIM_EGR_CC1G_Pos</a>)</td></tr>
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<tr class="separator:gaba7a2fa9e7341df84a32cf5d54e61ad3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a1318609761df5de5213e9e75b5aa6a" id="r_ga0a1318609761df5de5213e9e75b5aa6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a1318609761df5de5213e9e75b5aa6a">TIM_EGR_CC1G</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba7a2fa9e7341df84a32cf5d54e61ad3">TIM_EGR_CC1G_Msk</a></td></tr>
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<tr class="separator:ga0a1318609761df5de5213e9e75b5aa6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49003c85e8c92b159faee96d1c6a8cea" id="r_ga49003c85e8c92b159faee96d1c6a8cea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49003c85e8c92b159faee96d1c6a8cea">TIM_EGR_CC2G_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga49003c85e8c92b159faee96d1c6a8cea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfa4c983163836490441a78e7bf89b67" id="r_gacfa4c983163836490441a78e7bf89b67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfa4c983163836490441a78e7bf89b67">TIM_EGR_CC2G_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga49003c85e8c92b159faee96d1c6a8cea">TIM_EGR_CC2G_Pos</a>)</td></tr>
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<tr class="separator:gacfa4c983163836490441a78e7bf89b67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5423de00e86aeb8a4657a509af485055" id="r_ga5423de00e86aeb8a4657a509af485055"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5423de00e86aeb8a4657a509af485055">TIM_EGR_CC2G</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacfa4c983163836490441a78e7bf89b67">TIM_EGR_CC2G_Msk</a></td></tr>
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<tr class="separator:ga5423de00e86aeb8a4657a509af485055"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8006ffc22a9a37d21364e8023d7eb145" id="r_ga8006ffc22a9a37d21364e8023d7eb145"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8006ffc22a9a37d21364e8023d7eb145">TIM_EGR_CC3G_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga8006ffc22a9a37d21364e8023d7eb145"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab73c2e5ea59b860e342d2ea5f99ff672" id="r_gab73c2e5ea59b860e342d2ea5f99ff672"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab73c2e5ea59b860e342d2ea5f99ff672">TIM_EGR_CC3G_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8006ffc22a9a37d21364e8023d7eb145">TIM_EGR_CC3G_Pos</a>)</td></tr>
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<tr class="separator:gab73c2e5ea59b860e342d2ea5f99ff672"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga064d2030abccc099ded418fd81d6aa07" id="r_ga064d2030abccc099ded418fd81d6aa07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga064d2030abccc099ded418fd81d6aa07">TIM_EGR_CC3G</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab73c2e5ea59b860e342d2ea5f99ff672">TIM_EGR_CC3G_Msk</a></td></tr>
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<tr class="separator:ga064d2030abccc099ded418fd81d6aa07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49b4e300af06da863900ba29d894eb26" id="r_ga49b4e300af06da863900ba29d894eb26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49b4e300af06da863900ba29d894eb26">TIM_EGR_CC4G_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga49b4e300af06da863900ba29d894eb26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ae87478438e43366db04ac05db1db0e" id="r_ga8ae87478438e43366db04ac05db1db0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ae87478438e43366db04ac05db1db0e">TIM_EGR_CC4G_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga49b4e300af06da863900ba29d894eb26">TIM_EGR_CC4G_Pos</a>)</td></tr>
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<tr class="separator:ga8ae87478438e43366db04ac05db1db0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c4e5555dd3be8ab1e631d1053f4a305" id="r_ga1c4e5555dd3be8ab1e631d1053f4a305"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c4e5555dd3be8ab1e631d1053f4a305">TIM_EGR_CC4G</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ae87478438e43366db04ac05db1db0e">TIM_EGR_CC4G_Msk</a></td></tr>
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<tr class="separator:ga1c4e5555dd3be8ab1e631d1053f4a305"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga235c6ad9b108e6640f0c3fb7b3b9e278" id="r_ga235c6ad9b108e6640f0c3fb7b3b9e278"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga235c6ad9b108e6640f0c3fb7b3b9e278">TIM_EGR_COMG_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga235c6ad9b108e6640f0c3fb7b3b9e278"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab04646da2ee78ff6e2d4c483c8050d20" id="r_gab04646da2ee78ff6e2d4c483c8050d20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab04646da2ee78ff6e2d4c483c8050d20">TIM_EGR_COMG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga235c6ad9b108e6640f0c3fb7b3b9e278">TIM_EGR_COMG_Pos</a>)</td></tr>
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<tr class="separator:gab04646da2ee78ff6e2d4c483c8050d20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb06f8bb364307695c7d6a028391de7b" id="r_gadb06f8bb364307695c7d6a028391de7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb06f8bb364307695c7d6a028391de7b">TIM_EGR_COMG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab04646da2ee78ff6e2d4c483c8050d20">TIM_EGR_COMG_Msk</a></td></tr>
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<tr class="separator:gadb06f8bb364307695c7d6a028391de7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad68094deb44a74ef649c243ec840b9a2" id="r_gad68094deb44a74ef649c243ec840b9a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad68094deb44a74ef649c243ec840b9a2">TIM_EGR_TG_Pos</a>   (6U)</td></tr>
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<tr class="separator:gad68094deb44a74ef649c243ec840b9a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedb01f674152f674c87c21b6147963d5" id="r_gaedb01f674152f674c87c21b6147963d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedb01f674152f674c87c21b6147963d5">TIM_EGR_TG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad68094deb44a74ef649c243ec840b9a2">TIM_EGR_TG_Pos</a>)</td></tr>
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<tr class="separator:gaedb01f674152f674c87c21b6147963d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2eabface433d6adaa2dee3df49852585" id="r_ga2eabface433d6adaa2dee3df49852585"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2eabface433d6adaa2dee3df49852585">TIM_EGR_TG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaedb01f674152f674c87c21b6147963d5">TIM_EGR_TG_Msk</a></td></tr>
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<tr class="separator:ga2eabface433d6adaa2dee3df49852585"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga068531a673c44015bef074e6c926ce77" id="r_ga068531a673c44015bef074e6c926ce77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga068531a673c44015bef074e6c926ce77">TIM_EGR_BG_Pos</a>   (7U)</td></tr>
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<tr class="memitem:ga3cbac05839c59f31bd13664890685941" id="r_ga3cbac05839c59f31bd13664890685941"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cbac05839c59f31bd13664890685941">TIM_EGR_BG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga068531a673c44015bef074e6c926ce77">TIM_EGR_BG_Pos</a>)</td></tr>
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<tr class="separator:ga3cbac05839c59f31bd13664890685941"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08c5635a0ac0ce5618485319a4fa0f18" id="r_ga08c5635a0ac0ce5618485319a4fa0f18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08c5635a0ac0ce5618485319a4fa0f18">TIM_EGR_BG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cbac05839c59f31bd13664890685941">TIM_EGR_BG_Msk</a></td></tr>
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<tr class="memitem:ga8824b80350897e1b65c1b98f1b7e9469" id="r_ga8824b80350897e1b65c1b98f1b7e9469"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8824b80350897e1b65c1b98f1b7e9469">TIM_CCMR1_CC1S_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8824b80350897e1b65c1b98f1b7e9469"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae45972a14def2a4e25e20a688e535b80" id="r_gae45972a14def2a4e25e20a688e535b80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae45972a14def2a4e25e20a688e535b80">TIM_CCMR1_CC1S_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8824b80350897e1b65c1b98f1b7e9469">TIM_CCMR1_CC1S_Pos</a>)</td></tr>
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<tr class="separator:gae45972a14def2a4e25e20a688e535b80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95291df1eaf532c5c996d176648938eb" id="r_ga95291df1eaf532c5c996d176648938eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">TIM_CCMR1_CC1S</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae45972a14def2a4e25e20a688e535b80">TIM_CCMR1_CC1S_Msk</a></td></tr>
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<tr class="separator:ga95291df1eaf532c5c996d176648938eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e4968b5500d58d1aebce888da31eb5d" id="r_ga1e4968b5500d58d1aebce888da31eb5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e4968b5500d58d1aebce888da31eb5d">TIM_CCMR1_CC1S_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8824b80350897e1b65c1b98f1b7e9469">TIM_CCMR1_CC1S_Pos</a>)</td></tr>
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<tr class="separator:ga1e4968b5500d58d1aebce888da31eb5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga299207b757f31c9c02471ab5f4f59dbe" id="r_ga299207b757f31c9c02471ab5f4f59dbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga299207b757f31c9c02471ab5f4f59dbe">TIM_CCMR1_CC1S_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8824b80350897e1b65c1b98f1b7e9469">TIM_CCMR1_CC1S_Pos</a>)</td></tr>
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<tr class="separator:ga299207b757f31c9c02471ab5f4f59dbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99fec0329d7dfc1ebe7d3cb9ca9b5bb1" id="r_ga99fec0329d7dfc1ebe7d3cb9ca9b5bb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99fec0329d7dfc1ebe7d3cb9ca9b5bb1">TIM_CCMR1_OC1FE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga99fec0329d7dfc1ebe7d3cb9ca9b5bb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae9383afb4e7ea68c9254f69461ec626" id="r_gaae9383afb4e7ea68c9254f69461ec626"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae9383afb4e7ea68c9254f69461ec626">TIM_CCMR1_OC1FE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga99fec0329d7dfc1ebe7d3cb9ca9b5bb1">TIM_CCMR1_OC1FE_Pos</a>)</td></tr>
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<tr class="separator:gaae9383afb4e7ea68c9254f69461ec626"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9c5878e85ce02c22d8a374deebd1b6e" id="r_gab9c5878e85ce02c22d8a374deebd1b6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9c5878e85ce02c22d8a374deebd1b6e">TIM_CCMR1_OC1FE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae9383afb4e7ea68c9254f69461ec626">TIM_CCMR1_OC1FE_Msk</a></td></tr>
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<tr class="separator:gab9c5878e85ce02c22d8a374deebd1b6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf34f1ffb1956f71bb24fb8229d76a6a7" id="r_gaf34f1ffb1956f71bb24fb8229d76a6a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf34f1ffb1956f71bb24fb8229d76a6a7">TIM_CCMR1_OC1PE_Pos</a>   (3U)</td></tr>
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<tr class="separator:gaf34f1ffb1956f71bb24fb8229d76a6a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6ad2b511f62760051b61edc1d666b02" id="r_gad6ad2b511f62760051b61edc1d666b02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6ad2b511f62760051b61edc1d666b02">TIM_CCMR1_OC1PE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf34f1ffb1956f71bb24fb8229d76a6a7">TIM_CCMR1_OC1PE_Pos</a>)</td></tr>
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<tr class="separator:gad6ad2b511f62760051b61edc1d666b02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1aa54ddf87a4b339881a8d5368ec80eb" id="r_ga1aa54ddf87a4b339881a8d5368ec80eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1aa54ddf87a4b339881a8d5368ec80eb">TIM_CCMR1_OC1PE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad6ad2b511f62760051b61edc1d666b02">TIM_CCMR1_OC1PE_Msk</a></td></tr>
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<tr class="separator:ga1aa54ddf87a4b339881a8d5368ec80eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4e6a8f6b0480f58e9632780bb393c4d" id="r_gac4e6a8f6b0480f58e9632780bb393c4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4e6a8f6b0480f58e9632780bb393c4d">TIM_CCMR1_OC1M_Pos</a>   (4U)</td></tr>
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<tr class="separator:gac4e6a8f6b0480f58e9632780bb393c4d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45e26a7685848c6cd8572038f06ceab1" id="r_ga45e26a7685848c6cd8572038f06ceab1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45e26a7685848c6cd8572038f06ceab1">TIM_CCMR1_OC1M_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4e6a8f6b0480f58e9632780bb393c4d">TIM_CCMR1_OC1M_Pos</a>)</td></tr>
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<tr class="separator:ga45e26a7685848c6cd8572038f06ceab1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ddb3dc889733e71d812baa3873cb13b" id="r_ga6ddb3dc889733e71d812baa3873cb13b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ddb3dc889733e71d812baa3873cb13b">TIM_CCMR1_OC1M</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45e26a7685848c6cd8572038f06ceab1">TIM_CCMR1_OC1M_Msk</a></td></tr>
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<tr class="separator:ga6ddb3dc889733e71d812baa3873cb13b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga410a4752a98081bad8ab3f72b28e7c5f" id="r_ga410a4752a98081bad8ab3f72b28e7c5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4e6a8f6b0480f58e9632780bb393c4d">TIM_CCMR1_OC1M_Pos</a>)</td></tr>
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<tr class="separator:ga410a4752a98081bad8ab3f72b28e7c5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b5f6ec25063483641d6dc065d96d2b5" id="r_ga8b5f6ec25063483641d6dc065d96d2b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4e6a8f6b0480f58e9632780bb393c4d">TIM_CCMR1_OC1M_Pos</a>)</td></tr>
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<tr class="separator:ga8b5f6ec25063483641d6dc065d96d2b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac024f6b9972b940925ab5786ee38701b" id="r_gac024f6b9972b940925ab5786ee38701b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4e6a8f6b0480f58e9632780bb393c4d">TIM_CCMR1_OC1M_Pos</a>)</td></tr>
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<tr class="separator:gac024f6b9972b940925ab5786ee38701b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78c5f97f5378df55d6b5bdf60219ecd2" id="r_ga78c5f97f5378df55d6b5bdf60219ecd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78c5f97f5378df55d6b5bdf60219ecd2">TIM_CCMR1_OC1CE_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga78c5f97f5378df55d6b5bdf60219ecd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga574f991bc328a80c9b44224e9a74d045" id="r_ga574f991bc328a80c9b44224e9a74d045"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga574f991bc328a80c9b44224e9a74d045">TIM_CCMR1_OC1CE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78c5f97f5378df55d6b5bdf60219ecd2">TIM_CCMR1_OC1CE_Pos</a>)</td></tr>
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<tr class="separator:ga574f991bc328a80c9b44224e9a74d045"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f44c50cf9928d2afab014e2ca29baba" id="r_ga8f44c50cf9928d2afab014e2ca29baba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f44c50cf9928d2afab014e2ca29baba">TIM_CCMR1_OC1CE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga574f991bc328a80c9b44224e9a74d045">TIM_CCMR1_OC1CE_Msk</a></td></tr>
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<tr class="separator:ga8f44c50cf9928d2afab014e2ca29baba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e06c5ff5024706a767be3454512401e" id="r_ga2e06c5ff5024706a767be3454512401e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06c5ff5024706a767be3454512401e">TIM_CCMR1_CC2S_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga2e06c5ff5024706a767be3454512401e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1df8354fa71992fddecba93c6309c7f3" id="r_ga1df8354fa71992fddecba93c6309c7f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1df8354fa71992fddecba93c6309c7f3">TIM_CCMR1_CC2S_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06c5ff5024706a767be3454512401e">TIM_CCMR1_CC2S_Pos</a>)</td></tr>
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<tr class="separator:ga1df8354fa71992fddecba93c6309c7f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdb0986b78bea5b53ea61e4ddd667cbf" id="r_gacdb0986b78bea5b53ea61e4ddd667cbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdb0986b78bea5b53ea61e4ddd667cbf">TIM_CCMR1_CC2S</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1df8354fa71992fddecba93c6309c7f3">TIM_CCMR1_CC2S_Msk</a></td></tr>
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<tr class="separator:gacdb0986b78bea5b53ea61e4ddd667cbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52bb0e50c11c35dcf42aeff7f1c22874" id="r_ga52bb0e50c11c35dcf42aeff7f1c22874"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52bb0e50c11c35dcf42aeff7f1c22874">TIM_CCMR1_CC2S_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06c5ff5024706a767be3454512401e">TIM_CCMR1_CC2S_Pos</a>)</td></tr>
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<tr class="separator:ga52bb0e50c11c35dcf42aeff7f1c22874"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78303c37fdbe0be80f5fc7d21e9eba45" id="r_ga78303c37fdbe0be80f5fc7d21e9eba45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78303c37fdbe0be80f5fc7d21e9eba45">TIM_CCMR1_CC2S_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e06c5ff5024706a767be3454512401e">TIM_CCMR1_CC2S_Pos</a>)</td></tr>
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<tr class="separator:ga78303c37fdbe0be80f5fc7d21e9eba45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7240668687c24e88a8738b3a84be511" id="r_gab7240668687c24e88a8738b3a84be511"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7240668687c24e88a8738b3a84be511">TIM_CCMR1_OC2FE_Pos</a>   (10U)</td></tr>
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<tr class="separator:gab7240668687c24e88a8738b3a84be511"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga376f7fd88a0dc62039e03bbc2fdd9569" id="r_ga376f7fd88a0dc62039e03bbc2fdd9569"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga376f7fd88a0dc62039e03bbc2fdd9569">TIM_CCMR1_OC2FE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab7240668687c24e88a8738b3a84be511">TIM_CCMR1_OC2FE_Pos</a>)</td></tr>
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<tr class="separator:ga376f7fd88a0dc62039e03bbc2fdd9569"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bf610cf77c3c6c936ce7c4f85992e6c" id="r_ga3bf610cf77c3c6c936ce7c4f85992e6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bf610cf77c3c6c936ce7c4f85992e6c">TIM_CCMR1_OC2FE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga376f7fd88a0dc62039e03bbc2fdd9569">TIM_CCMR1_OC2FE_Msk</a></td></tr>
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<tr class="separator:ga3bf610cf77c3c6c936ce7c4f85992e6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga819513a7183766b4427cddfb08413eb7" id="r_ga819513a7183766b4427cddfb08413eb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga819513a7183766b4427cddfb08413eb7">TIM_CCMR1_OC2PE_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga664936de978a62b290fe7da4c2b1c395" id="r_ga664936de978a62b290fe7da4c2b1c395"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga664936de978a62b290fe7da4c2b1c395">TIM_CCMR1_OC2PE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga819513a7183766b4427cddfb08413eb7">TIM_CCMR1_OC2PE_Pos</a>)</td></tr>
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<tr class="memitem:gabddbf508732039730125ab3e87e9d370" id="r_gabddbf508732039730125ab3e87e9d370"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabddbf508732039730125ab3e87e9d370">TIM_CCMR1_OC2PE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga664936de978a62b290fe7da4c2b1c395">TIM_CCMR1_OC2PE_Msk</a></td></tr>
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<tr class="separator:gabddbf508732039730125ab3e87e9d370"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae31265c2d3adef5873acc64f2f0045a1" id="r_gae31265c2d3adef5873acc64f2f0045a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae31265c2d3adef5873acc64f2f0045a1">TIM_CCMR1_OC2M_Pos</a>   (12U)</td></tr>
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<tr class="memitem:ga7082e88c67576a8ce483e0534b0ae8cb" id="r_ga7082e88c67576a8ce483e0534b0ae8cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7082e88c67576a8ce483e0534b0ae8cb">TIM_CCMR1_OC2M_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae31265c2d3adef5873acc64f2f0045a1">TIM_CCMR1_OC2M_Pos</a>)</td></tr>
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<tr class="separator:ga7082e88c67576a8ce483e0534b0ae8cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2326bafe64ba2ebdde908d66219eaa6f" id="r_ga2326bafe64ba2ebdde908d66219eaa6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2326bafe64ba2ebdde908d66219eaa6f">TIM_CCMR1_OC2M</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7082e88c67576a8ce483e0534b0ae8cb">TIM_CCMR1_OC2M_Msk</a></td></tr>
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<tr class="separator:ga2326bafe64ba2ebdde908d66219eaa6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbb68b91da16ffd509a6c7a2a397083c" id="r_gadbb68b91da16ffd509a6c7a2a397083c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbb68b91da16ffd509a6c7a2a397083c">TIM_CCMR1_OC2M_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae31265c2d3adef5873acc64f2f0045a1">TIM_CCMR1_OC2M_Pos</a>)</td></tr>
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<tr class="separator:gadbb68b91da16ffd509a6c7a2a397083c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedb673b7e2c016191579de704eb842e4" id="r_gaedb673b7e2c016191579de704eb842e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedb673b7e2c016191579de704eb842e4">TIM_CCMR1_OC2M_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae31265c2d3adef5873acc64f2f0045a1">TIM_CCMR1_OC2M_Pos</a>)</td></tr>
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<tr class="memitem:gad039a41e5fe97ddf904a0f9f95eb539e" id="r_gad039a41e5fe97ddf904a0f9f95eb539e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad039a41e5fe97ddf904a0f9f95eb539e">TIM_CCMR1_OC2M_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae31265c2d3adef5873acc64f2f0045a1">TIM_CCMR1_OC2M_Pos</a>)</td></tr>
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<tr class="separator:gad039a41e5fe97ddf904a0f9f95eb539e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e30d09989e2a51517b5962e63baf1dd" id="r_ga2e30d09989e2a51517b5962e63baf1dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e30d09989e2a51517b5962e63baf1dd">TIM_CCMR1_OC2CE_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga2e30d09989e2a51517b5962e63baf1dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c788cd4e4e8549585b21e050bf91de5" id="r_ga3c788cd4e4e8549585b21e050bf91de5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c788cd4e4e8549585b21e050bf91de5">TIM_CCMR1_OC2CE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e30d09989e2a51517b5962e63baf1dd">TIM_CCMR1_OC2CE_Pos</a>)</td></tr>
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<tr class="separator:ga3c788cd4e4e8549585b21e050bf91de5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19a8dd4ea04d262ec4e97b5c7a8677a5" id="r_ga19a8dd4ea04d262ec4e97b5c7a8677a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19a8dd4ea04d262ec4e97b5c7a8677a5">TIM_CCMR1_OC2CE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c788cd4e4e8549585b21e050bf91de5">TIM_CCMR1_OC2CE_Msk</a></td></tr>
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<tr class="separator:ga19a8dd4ea04d262ec4e97b5c7a8677a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84059edcc2ee8d02b8bc6757b667b47a" id="r_ga84059edcc2ee8d02b8bc6757b667b47a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84059edcc2ee8d02b8bc6757b667b47a">TIM_CCMR1_IC1PSC_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga84059edcc2ee8d02b8bc6757b667b47a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a7ca2ec3b7bc576b7883702a45823d2" id="r_ga0a7ca2ec3b7bc576b7883702a45823d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a7ca2ec3b7bc576b7883702a45823d2">TIM_CCMR1_IC1PSC_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84059edcc2ee8d02b8bc6757b667b47a">TIM_CCMR1_IC1PSC_Pos</a>)</td></tr>
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<tr class="separator:ga0a7ca2ec3b7bc576b7883702a45823d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab46b7186665f5308cd2ca52acfb63e72" id="r_gab46b7186665f5308cd2ca52acfb63e72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab46b7186665f5308cd2ca52acfb63e72">TIM_CCMR1_IC1PSC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a7ca2ec3b7bc576b7883702a45823d2">TIM_CCMR1_IC1PSC_Msk</a></td></tr>
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<tr class="separator:gab46b7186665f5308cd2ca52acfb63e72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05673358a44aeaa56daefca67341b29d" id="r_ga05673358a44aeaa56daefca67341b29d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05673358a44aeaa56daefca67341b29d">TIM_CCMR1_IC1PSC_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84059edcc2ee8d02b8bc6757b667b47a">TIM_CCMR1_IC1PSC_Pos</a>)</td></tr>
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<tr class="separator:ga05673358a44aeaa56daefca67341b29d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf42b75da9b2f127dca98b6ca616f7add" id="r_gaf42b75da9b2f127dca98b6ca616f7add"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf42b75da9b2f127dca98b6ca616f7add">TIM_CCMR1_IC1PSC_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84059edcc2ee8d02b8bc6757b667b47a">TIM_CCMR1_IC1PSC_Pos</a>)</td></tr>
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<tr class="separator:gaf42b75da9b2f127dca98b6ca616f7add"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b270ce595ea92cabc0e62576b5cbdb0" id="r_ga4b270ce595ea92cabc0e62576b5cbdb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b270ce595ea92cabc0e62576b5cbdb0">TIM_CCMR1_IC1F_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga4b270ce595ea92cabc0e62576b5cbdb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade8750e792254e281c4999de3fbf9e13" id="r_gade8750e792254e281c4999de3fbf9e13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade8750e792254e281c4999de3fbf9e13">TIM_CCMR1_IC1F_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b270ce595ea92cabc0e62576b5cbdb0">TIM_CCMR1_IC1F_Pos</a>)</td></tr>
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<tr class="separator:gade8750e792254e281c4999de3fbf9e13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0ee123675d8b8f98b5a6eeeccf37912" id="r_gab0ee123675d8b8f98b5a6eeeccf37912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0ee123675d8b8f98b5a6eeeccf37912">TIM_CCMR1_IC1F</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gade8750e792254e281c4999de3fbf9e13">TIM_CCMR1_IC1F_Msk</a></td></tr>
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<tr class="separator:gab0ee123675d8b8f98b5a6eeeccf37912"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7dde4afee556d2d8d22885f191da65a6" id="r_ga7dde4afee556d2d8d22885f191da65a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7dde4afee556d2d8d22885f191da65a6">TIM_CCMR1_IC1F_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b270ce595ea92cabc0e62576b5cbdb0">TIM_CCMR1_IC1F_Pos</a>)</td></tr>
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<tr class="separator:ga7dde4afee556d2d8d22885f191da65a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga201491465e6864088210bccb8491be84" id="r_ga201491465e6864088210bccb8491be84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga201491465e6864088210bccb8491be84">TIM_CCMR1_IC1F_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b270ce595ea92cabc0e62576b5cbdb0">TIM_CCMR1_IC1F_Pos</a>)</td></tr>
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<tr class="separator:ga201491465e6864088210bccb8491be84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabaa55ab1e0109b055cabef579c32d67b" id="r_gabaa55ab1e0109b055cabef579c32d67b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabaa55ab1e0109b055cabef579c32d67b">TIM_CCMR1_IC1F_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b270ce595ea92cabc0e62576b5cbdb0">TIM_CCMR1_IC1F_Pos</a>)</td></tr>
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<tr class="separator:gabaa55ab1e0109b055cabef579c32d67b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23da95530eb6d6451c7c9e451a580f42" id="r_ga23da95530eb6d6451c7c9e451a580f42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23da95530eb6d6451c7c9e451a580f42">TIM_CCMR1_IC1F_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b270ce595ea92cabc0e62576b5cbdb0">TIM_CCMR1_IC1F_Pos</a>)</td></tr>
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<tr class="separator:ga23da95530eb6d6451c7c9e451a580f42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5eb62126e13b62bf9ed83bcb358532b3" id="r_ga5eb62126e13b62bf9ed83bcb358532b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5eb62126e13b62bf9ed83bcb358532b3">TIM_CCMR1_IC2PSC_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga5eb62126e13b62bf9ed83bcb358532b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa7570c3a71156c52b0d95b4199f5d3e" id="r_gafa7570c3a71156c52b0d95b4199f5d3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa7570c3a71156c52b0d95b4199f5d3e">TIM_CCMR1_IC2PSC_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5eb62126e13b62bf9ed83bcb358532b3">TIM_CCMR1_IC2PSC_Pos</a>)</td></tr>
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<tr class="separator:gafa7570c3a71156c52b0d95b4199f5d3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e8e704f9ce5742f45e15e3b3126aa9d" id="r_ga5e8e704f9ce5742f45e15e3b3126aa9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e8e704f9ce5742f45e15e3b3126aa9d">TIM_CCMR1_IC2PSC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafa7570c3a71156c52b0d95b4199f5d3e">TIM_CCMR1_IC2PSC_Msk</a></td></tr>
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<tr class="separator:ga5e8e704f9ce5742f45e15e3b3126aa9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39206b27b5b1c5941b2a14ee8e2f1223" id="r_ga39206b27b5b1c5941b2a14ee8e2f1223"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39206b27b5b1c5941b2a14ee8e2f1223">TIM_CCMR1_IC2PSC_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5eb62126e13b62bf9ed83bcb358532b3">TIM_CCMR1_IC2PSC_Pos</a>)</td></tr>
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<tr class="separator:ga39206b27b5b1c5941b2a14ee8e2f1223"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae861d74943f3c045421f9fdc8b966841" id="r_gae861d74943f3c045421f9fdc8b966841"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae861d74943f3c045421f9fdc8b966841">TIM_CCMR1_IC2PSC_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5eb62126e13b62bf9ed83bcb358532b3">TIM_CCMR1_IC2PSC_Pos</a>)</td></tr>
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<tr class="separator:gae861d74943f3c045421f9fdc8b966841"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed5a16f773b95122caa60dbdd5b22964" id="r_gaed5a16f773b95122caa60dbdd5b22964"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed5a16f773b95122caa60dbdd5b22964">TIM_CCMR1_IC2F_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaed5a16f773b95122caa60dbdd5b22964"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b1456053707716ae50feded2a118887" id="r_ga4b1456053707716ae50feded2a118887"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b1456053707716ae50feded2a118887">TIM_CCMR1_IC2F_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed5a16f773b95122caa60dbdd5b22964">TIM_CCMR1_IC2F_Pos</a>)</td></tr>
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<tr class="separator:ga4b1456053707716ae50feded2a118887"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b942752d686c23323880ff576e7dffb" id="r_ga2b942752d686c23323880ff576e7dffb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b942752d686c23323880ff576e7dffb">TIM_CCMR1_IC2F</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b1456053707716ae50feded2a118887">TIM_CCMR1_IC2F_Msk</a></td></tr>
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<tr class="memitem:ga5d75acd7072f28844074702683d8493f" id="r_ga5d75acd7072f28844074702683d8493f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5d75acd7072f28844074702683d8493f">TIM_CCMR1_IC2F_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed5a16f773b95122caa60dbdd5b22964">TIM_CCMR1_IC2F_Pos</a>)</td></tr>
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<tr class="memitem:ga40e49318b54b16bda6fd7feea7c9a7dd" id="r_ga40e49318b54b16bda6fd7feea7c9a7dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40e49318b54b16bda6fd7feea7c9a7dd">TIM_CCMR1_IC2F_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed5a16f773b95122caa60dbdd5b22964">TIM_CCMR1_IC2F_Pos</a>)</td></tr>
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<tr class="memitem:ga932148c784f5cbee4dfcafcbadaf0107" id="r_ga932148c784f5cbee4dfcafcbadaf0107"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga932148c784f5cbee4dfcafcbadaf0107">TIM_CCMR1_IC2F_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed5a16f773b95122caa60dbdd5b22964">TIM_CCMR1_IC2F_Pos</a>)</td></tr>
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<tr class="memitem:gafece48b6f595ef9717d523fa23cea1e8" id="r_gafece48b6f595ef9717d523fa23cea1e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafece48b6f595ef9717d523fa23cea1e8">TIM_CCMR1_IC2F_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed5a16f773b95122caa60dbdd5b22964">TIM_CCMR1_IC2F_Pos</a>)</td></tr>
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<tr class="memitem:gaab00cf673f46bb5a112370ff94d5495b" id="r_gaab00cf673f46bb5a112370ff94d5495b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab00cf673f46bb5a112370ff94d5495b">TIM_CCMR2_CC3S_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gac236d456c1635745129611f040e50392" id="r_gac236d456c1635745129611f040e50392"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac236d456c1635745129611f040e50392">TIM_CCMR2_CC3S_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab00cf673f46bb5a112370ff94d5495b">TIM_CCMR2_CC3S_Pos</a>)</td></tr>
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<tr class="memitem:ga2eabcc7e322b02c9c406b3ff70308260" id="r_ga2eabcc7e322b02c9c406b3ff70308260"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2eabcc7e322b02c9c406b3ff70308260">TIM_CCMR2_CC3S</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac236d456c1635745129611f040e50392">TIM_CCMR2_CC3S_Msk</a></td></tr>
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<tr class="memitem:ga68c04aea2e89f1e89bd323d6d6e5e6c0" id="r_ga68c04aea2e89f1e89bd323d6d6e5e6c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68c04aea2e89f1e89bd323d6d6e5e6c0">TIM_CCMR2_CC3S_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab00cf673f46bb5a112370ff94d5495b">TIM_CCMR2_CC3S_Pos</a>)</td></tr>
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<tr class="memitem:ga4bed6648aad6e8d16196246b355452dc" id="r_ga4bed6648aad6e8d16196246b355452dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bed6648aad6e8d16196246b355452dc">TIM_CCMR2_CC3S_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab00cf673f46bb5a112370ff94d5495b">TIM_CCMR2_CC3S_Pos</a>)</td></tr>
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<tr class="memitem:ga3fada082e0cea460d9722f5dca1fe1a8" id="r_ga3fada082e0cea460d9722f5dca1fe1a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3fada082e0cea460d9722f5dca1fe1a8">TIM_CCMR2_OC3FE_Pos</a>   (2U)</td></tr>
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<tr class="memitem:gaef7fdd716098d6370d1fbef9ec6de226" id="r_gaef7fdd716098d6370d1fbef9ec6de226"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef7fdd716098d6370d1fbef9ec6de226">TIM_CCMR2_OC3FE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3fada082e0cea460d9722f5dca1fe1a8">TIM_CCMR2_OC3FE_Pos</a>)</td></tr>
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<tr class="memitem:gae6d8d2847058747ce23a648668ce4dba" id="r_gae6d8d2847058747ce23a648668ce4dba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6d8d2847058747ce23a648668ce4dba">TIM_CCMR2_OC3FE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaef7fdd716098d6370d1fbef9ec6de226">TIM_CCMR2_OC3FE_Msk</a></td></tr>
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<tr class="memitem:ga5ebdd2a0a808080fac30e5ee1514f4cf" id="r_ga5ebdd2a0a808080fac30e5ee1514f4cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ebdd2a0a808080fac30e5ee1514f4cf">TIM_CCMR2_OC3PE_Pos</a>   (3U)</td></tr>
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<tr class="memitem:ga340c7064a44bc7478982f5ef7a7655f9" id="r_ga340c7064a44bc7478982f5ef7a7655f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga340c7064a44bc7478982f5ef7a7655f9">TIM_CCMR2_OC3PE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ebdd2a0a808080fac30e5ee1514f4cf">TIM_CCMR2_OC3PE_Pos</a>)</td></tr>
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<tr class="memitem:ga276fd2250d2b085b73ef51cb4c099d24" id="r_ga276fd2250d2b085b73ef51cb4c099d24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga276fd2250d2b085b73ef51cb4c099d24">TIM_CCMR2_OC3PE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga340c7064a44bc7478982f5ef7a7655f9">TIM_CCMR2_OC3PE_Msk</a></td></tr>
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<tr class="memitem:gafc968db76163687538732d31cf4d4d91" id="r_gafc968db76163687538732d31cf4d4d91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc968db76163687538732d31cf4d4d91">TIM_CCMR2_OC3M_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga8e306d8b3f5f98f8bfb6002dc2a7ff06" id="r_ga8e306d8b3f5f98f8bfb6002dc2a7ff06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e306d8b3f5f98f8bfb6002dc2a7ff06">TIM_CCMR2_OC3M_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafc968db76163687538732d31cf4d4d91">TIM_CCMR2_OC3M_Pos</a>)</td></tr>
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<tr class="memitem:ga52095cae524adb237339bfee92e8168a" id="r_ga52095cae524adb237339bfee92e8168a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52095cae524adb237339bfee92e8168a">TIM_CCMR2_OC3M</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e306d8b3f5f98f8bfb6002dc2a7ff06">TIM_CCMR2_OC3M_Msk</a></td></tr>
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<tr class="memitem:ga899b26ffa9c5f30f143306b8598a537f" id="r_ga899b26ffa9c5f30f143306b8598a537f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga899b26ffa9c5f30f143306b8598a537f">TIM_CCMR2_OC3M_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafc968db76163687538732d31cf4d4d91">TIM_CCMR2_OC3M_Pos</a>)</td></tr>
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<tr class="memitem:ga91476ae2cc3449facafcad82569e14f8" id="r_ga91476ae2cc3449facafcad82569e14f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91476ae2cc3449facafcad82569e14f8">TIM_CCMR2_OC3M_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafc968db76163687538732d31cf4d4d91">TIM_CCMR2_OC3M_Pos</a>)</td></tr>
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<tr class="memitem:ga20394da7afcada6c3fc455b05004cff5" id="r_ga20394da7afcada6c3fc455b05004cff5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20394da7afcada6c3fc455b05004cff5">TIM_CCMR2_OC3M_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafc968db76163687538732d31cf4d4d91">TIM_CCMR2_OC3M_Pos</a>)</td></tr>
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<tr class="memitem:ga03695b16c15f57bd329b050603e11ff6" id="r_ga03695b16c15f57bd329b050603e11ff6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03695b16c15f57bd329b050603e11ff6">TIM_CCMR2_OC3CE_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga03695b16c15f57bd329b050603e11ff6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga040e81b609666fec1f0476346bb8b942" id="r_ga040e81b609666fec1f0476346bb8b942"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga040e81b609666fec1f0476346bb8b942">TIM_CCMR2_OC3CE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga03695b16c15f57bd329b050603e11ff6">TIM_CCMR2_OC3CE_Pos</a>)</td></tr>
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<tr class="memitem:ga4209d414df704ce96c54abb2ea2df66a" id="r_ga4209d414df704ce96c54abb2ea2df66a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4209d414df704ce96c54abb2ea2df66a">TIM_CCMR2_OC3CE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga040e81b609666fec1f0476346bb8b942">TIM_CCMR2_OC3CE_Msk</a></td></tr>
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<tr class="memitem:ga5774c57db57a50e9a1b7e6fa6c2833f6" id="r_ga5774c57db57a50e9a1b7e6fa6c2833f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5774c57db57a50e9a1b7e6fa6c2833f6">TIM_CCMR2_CC4S_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga5774c57db57a50e9a1b7e6fa6c2833f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66957133f2ac46cacb14834a6ad46b9b" id="r_ga66957133f2ac46cacb14834a6ad46b9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66957133f2ac46cacb14834a6ad46b9b">TIM_CCMR2_CC4S_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5774c57db57a50e9a1b7e6fa6c2833f6">TIM_CCMR2_CC4S_Pos</a>)</td></tr>
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<tr class="separator:ga66957133f2ac46cacb14834a6ad46b9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga294e216b50edd1c2f891143e1f971048" id="r_ga294e216b50edd1c2f891143e1f971048"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga294e216b50edd1c2f891143e1f971048">TIM_CCMR2_CC4S</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga66957133f2ac46cacb14834a6ad46b9b">TIM_CCMR2_CC4S_Msk</a></td></tr>
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<tr class="separator:ga294e216b50edd1c2f891143e1f971048"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabebaa6bffd90b32563bd0fc1ff4a9499" id="r_gabebaa6bffd90b32563bd0fc1ff4a9499"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabebaa6bffd90b32563bd0fc1ff4a9499">TIM_CCMR2_CC4S_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5774c57db57a50e9a1b7e6fa6c2833f6">TIM_CCMR2_CC4S_Pos</a>)</td></tr>
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<tr class="separator:gabebaa6bffd90b32563bd0fc1ff4a9499"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6386ec77a3a451954325a1512d44f893" id="r_ga6386ec77a3a451954325a1512d44f893"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6386ec77a3a451954325a1512d44f893">TIM_CCMR2_CC4S_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5774c57db57a50e9a1b7e6fa6c2833f6">TIM_CCMR2_CC4S_Pos</a>)</td></tr>
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<tr class="separator:ga6386ec77a3a451954325a1512d44f893"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69ec4d183286e02653876ead0a835a09" id="r_ga69ec4d183286e02653876ead0a835a09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69ec4d183286e02653876ead0a835a09">TIM_CCMR2_OC4FE_Pos</a>   (10U)</td></tr>
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<tr class="memitem:ga01f0c4e1d96b5dde5af64ea95b2c3880" id="r_ga01f0c4e1d96b5dde5af64ea95b2c3880"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01f0c4e1d96b5dde5af64ea95b2c3880">TIM_CCMR2_OC4FE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69ec4d183286e02653876ead0a835a09">TIM_CCMR2_OC4FE_Pos</a>)</td></tr>
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<tr class="memitem:ga70dc197250c2699d470aea1a7a42ad57" id="r_ga70dc197250c2699d470aea1a7a42ad57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70dc197250c2699d470aea1a7a42ad57">TIM_CCMR2_OC4FE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga01f0c4e1d96b5dde5af64ea95b2c3880">TIM_CCMR2_OC4FE_Msk</a></td></tr>
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<tr class="memitem:gaf1271844d8091a2494487cd082a585ca" id="r_gaf1271844d8091a2494487cd082a585ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1271844d8091a2494487cd082a585ca">TIM_CCMR2_OC4PE_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga28c07cee007c349ef4ba4a954b341ff4" id="r_ga28c07cee007c349ef4ba4a954b341ff4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28c07cee007c349ef4ba4a954b341ff4">TIM_CCMR2_OC4PE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1271844d8091a2494487cd082a585ca">TIM_CCMR2_OC4PE_Pos</a>)</td></tr>
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<tr class="memitem:ga3e951cd3f6593e321cf79b662a1deaaa" id="r_ga3e951cd3f6593e321cf79b662a1deaaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e951cd3f6593e321cf79b662a1deaaa">TIM_CCMR2_OC4PE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga28c07cee007c349ef4ba4a954b341ff4">TIM_CCMR2_OC4PE_Msk</a></td></tr>
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<tr class="memitem:ga67d4d6f1f9b93ff94a941d8c574ca400" id="r_ga67d4d6f1f9b93ff94a941d8c574ca400"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67d4d6f1f9b93ff94a941d8c574ca400">TIM_CCMR2_OC4M_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga67d4d6f1f9b93ff94a941d8c574ca400"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ffb46fed2d65aab83a895d8f791f84f" id="r_ga0ffb46fed2d65aab83a895d8f791f84f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ffb46fed2d65aab83a895d8f791f84f">TIM_CCMR2_OC4M_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67d4d6f1f9b93ff94a941d8c574ca400">TIM_CCMR2_OC4M_Pos</a>)</td></tr>
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<tr class="separator:ga0ffb46fed2d65aab83a895d8f791f84f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbed61ff3ba57c7fe6d3386ce3b7af2b" id="r_gacbed61ff3ba57c7fe6d3386ce3b7af2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbed61ff3ba57c7fe6d3386ce3b7af2b">TIM_CCMR2_OC4M</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ffb46fed2d65aab83a895d8f791f84f">TIM_CCMR2_OC4M_Msk</a></td></tr>
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<tr class="separator:gacbed61ff3ba57c7fe6d3386ce3b7af2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad866f52cce9ce32e3c0d181007b82de5" id="r_gad866f52cce9ce32e3c0d181007b82de5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad866f52cce9ce32e3c0d181007b82de5">TIM_CCMR2_OC4M_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67d4d6f1f9b93ff94a941d8c574ca400">TIM_CCMR2_OC4M_Pos</a>)</td></tr>
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<tr class="memitem:gafd97b1c86dd4953f3382fea317d165af" id="r_gafd97b1c86dd4953f3382fea317d165af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd97b1c86dd4953f3382fea317d165af">TIM_CCMR2_OC4M_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67d4d6f1f9b93ff94a941d8c574ca400">TIM_CCMR2_OC4M_Pos</a>)</td></tr>
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<tr class="memitem:ga431e5cdc0f3dc02fa5a54aa5193ddbab" id="r_ga431e5cdc0f3dc02fa5a54aa5193ddbab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga431e5cdc0f3dc02fa5a54aa5193ddbab">TIM_CCMR2_OC4M_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67d4d6f1f9b93ff94a941d8c574ca400">TIM_CCMR2_OC4M_Pos</a>)</td></tr>
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<tr class="separator:ga431e5cdc0f3dc02fa5a54aa5193ddbab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b06f4781d9ec977f5be9f010ee44b6b" id="r_ga8b06f4781d9ec977f5be9f010ee44b6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b06f4781d9ec977f5be9f010ee44b6b">TIM_CCMR2_OC4CE_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga8b06f4781d9ec977f5be9f010ee44b6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a3897ea2b9197cbc75507df645faefc" id="r_ga3a3897ea2b9197cbc75507df645faefc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a3897ea2b9197cbc75507df645faefc">TIM_CCMR2_OC4CE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b06f4781d9ec977f5be9f010ee44b6b">TIM_CCMR2_OC4CE_Pos</a>)</td></tr>
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<tr class="separator:ga3a3897ea2b9197cbc75507df645faefc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1447dfe94bdd234382bb1f43307ea5c3" id="r_ga1447dfe94bdd234382bb1f43307ea5c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1447dfe94bdd234382bb1f43307ea5c3">TIM_CCMR2_OC4CE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a3897ea2b9197cbc75507df645faefc">TIM_CCMR2_OC4CE_Msk</a></td></tr>
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<tr class="separator:ga1447dfe94bdd234382bb1f43307ea5c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae531e77cc77a9a76a0f32074ad371cf2" id="r_gae531e77cc77a9a76a0f32074ad371cf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae531e77cc77a9a76a0f32074ad371cf2">TIM_CCMR2_IC3PSC_Pos</a>   (2U)</td></tr>
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<tr class="separator:gae531e77cc77a9a76a0f32074ad371cf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabec127dfbd39286e7467a88e42b0e2a2" id="r_gabec127dfbd39286e7467a88e42b0e2a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabec127dfbd39286e7467a88e42b0e2a2">TIM_CCMR2_IC3PSC_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae531e77cc77a9a76a0f32074ad371cf2">TIM_CCMR2_IC3PSC_Pos</a>)</td></tr>
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<tr class="separator:gabec127dfbd39286e7467a88e42b0e2a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc3d11f2e968752bc9ec7131c986c3a6" id="r_gafc3d11f2e968752bc9ec7131c986c3a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc3d11f2e968752bc9ec7131c986c3a6">TIM_CCMR2_IC3PSC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabec127dfbd39286e7467a88e42b0e2a2">TIM_CCMR2_IC3PSC_Msk</a></td></tr>
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<tr class="separator:gafc3d11f2e968752bc9ec7131c986c3a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga588513395cbf8be6f4749c140fbf811c" id="r_ga588513395cbf8be6f4749c140fbf811c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga588513395cbf8be6f4749c140fbf811c">TIM_CCMR2_IC3PSC_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae531e77cc77a9a76a0f32074ad371cf2">TIM_CCMR2_IC3PSC_Pos</a>)</td></tr>
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<tr class="separator:ga588513395cbf8be6f4749c140fbf811c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd27b9bdcc161c90dc1712074a66f29d" id="r_gacd27b9bdcc161c90dc1712074a66f29d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd27b9bdcc161c90dc1712074a66f29d">TIM_CCMR2_IC3PSC_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae531e77cc77a9a76a0f32074ad371cf2">TIM_CCMR2_IC3PSC_Pos</a>)</td></tr>
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<tr class="separator:gacd27b9bdcc161c90dc1712074a66f29d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf23e70bb3dfe3c685a26e6ae00786b62" id="r_gaf23e70bb3dfe3c685a26e6ae00786b62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf23e70bb3dfe3c685a26e6ae00786b62">TIM_CCMR2_IC3F_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaf23e70bb3dfe3c685a26e6ae00786b62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac13900fc61a22d5b43f579e5854fa2c" id="r_gaac13900fc61a22d5b43f579e5854fa2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac13900fc61a22d5b43f579e5854fa2c">TIM_CCMR2_IC3F_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf23e70bb3dfe3c685a26e6ae00786b62">TIM_CCMR2_IC3F_Pos</a>)</td></tr>
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<tr class="separator:gaac13900fc61a22d5b43f579e5854fa2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad218af6bd1de72891e1b85d582b766cd" id="r_gad218af6bd1de72891e1b85d582b766cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad218af6bd1de72891e1b85d582b766cd">TIM_CCMR2_IC3F</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac13900fc61a22d5b43f579e5854fa2c">TIM_CCMR2_IC3F_Msk</a></td></tr>
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<tr class="separator:gad218af6bd1de72891e1b85d582b766cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31d5450ebc9ac6ea833a2b341ceea061" id="r_ga31d5450ebc9ac6ea833a2b341ceea061"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31d5450ebc9ac6ea833a2b341ceea061">TIM_CCMR2_IC3F_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf23e70bb3dfe3c685a26e6ae00786b62">TIM_CCMR2_IC3F_Pos</a>)</td></tr>
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<tr class="separator:ga31d5450ebc9ac6ea833a2b341ceea061"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26f92a3f831685d6df7ab69e68181849" id="r_ga26f92a3f831685d6df7ab69e68181849"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26f92a3f831685d6df7ab69e68181849">TIM_CCMR2_IC3F_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf23e70bb3dfe3c685a26e6ae00786b62">TIM_CCMR2_IC3F_Pos</a>)</td></tr>
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<tr class="separator:ga26f92a3f831685d6df7ab69e68181849"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e7d7a3c2686a6e31adc1adf2ce65df9" id="r_ga5e7d7a3c2686a6e31adc1adf2ce65df9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e7d7a3c2686a6e31adc1adf2ce65df9">TIM_CCMR2_IC3F_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf23e70bb3dfe3c685a26e6ae00786b62">TIM_CCMR2_IC3F_Pos</a>)</td></tr>
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<tr class="separator:ga5e7d7a3c2686a6e31adc1adf2ce65df9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9696c3da027f2b292d077f1ab4cdd14b" id="r_ga9696c3da027f2b292d077f1ab4cdd14b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9696c3da027f2b292d077f1ab4cdd14b">TIM_CCMR2_IC3F_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf23e70bb3dfe3c685a26e6ae00786b62">TIM_CCMR2_IC3F_Pos</a>)</td></tr>
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<tr class="separator:ga9696c3da027f2b292d077f1ab4cdd14b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1df596e58e5b71467be3d85988fb302f" id="r_ga1df596e58e5b71467be3d85988fb302f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1df596e58e5b71467be3d85988fb302f">TIM_CCMR2_IC4PSC_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga1df596e58e5b71467be3d85988fb302f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga289328a0304739b4459fa74978be5aa4" id="r_ga289328a0304739b4459fa74978be5aa4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga289328a0304739b4459fa74978be5aa4">TIM_CCMR2_IC4PSC_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1df596e58e5b71467be3d85988fb302f">TIM_CCMR2_IC4PSC_Pos</a>)</td></tr>
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<tr class="separator:ga289328a0304739b4459fa74978be5aa4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6fd7591e2de10272f7fafb08cdd1b7b0" id="r_ga6fd7591e2de10272f7fafb08cdd1b7b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fd7591e2de10272f7fafb08cdd1b7b0">TIM_CCMR2_IC4PSC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga289328a0304739b4459fa74978be5aa4">TIM_CCMR2_IC4PSC_Msk</a></td></tr>
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<tr class="separator:ga6fd7591e2de10272f7fafb08cdd1b7b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80f7d206409bc551eab06819e17451e4" id="r_ga80f7d206409bc551eab06819e17451e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80f7d206409bc551eab06819e17451e4">TIM_CCMR2_IC4PSC_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1df596e58e5b71467be3d85988fb302f">TIM_CCMR2_IC4PSC_Pos</a>)</td></tr>
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<tr class="separator:ga80f7d206409bc551eab06819e17451e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6690f5e98e02addd5e75643767c6d66" id="r_gaf6690f5e98e02addd5e75643767c6d66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6690f5e98e02addd5e75643767c6d66">TIM_CCMR2_IC4PSC_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1df596e58e5b71467be3d85988fb302f">TIM_CCMR2_IC4PSC_Pos</a>)</td></tr>
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<tr class="separator:gaf6690f5e98e02addd5e75643767c6d66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdce62241567cc540d3b7ce61084c1e2" id="r_gafdce62241567cc540d3b7ce61084c1e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdce62241567cc540d3b7ce61084c1e2">TIM_CCMR2_IC4F_Pos</a>   (12U)</td></tr>
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<tr class="separator:gafdce62241567cc540d3b7ce61084c1e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9f59cf5cc82d482d733a365cc7d887c" id="r_gaa9f59cf5cc82d482d733a365cc7d887c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9f59cf5cc82d482d733a365cc7d887c">TIM_CCMR2_IC4F_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafdce62241567cc540d3b7ce61084c1e2">TIM_CCMR2_IC4F_Pos</a>)</td></tr>
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<tr class="separator:gaa9f59cf5cc82d482d733a365cc7d887c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad51653fd06a591294d432385e794a19e" id="r_gad51653fd06a591294d432385e794a19e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad51653fd06a591294d432385e794a19e">TIM_CCMR2_IC4F</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9f59cf5cc82d482d733a365cc7d887c">TIM_CCMR2_IC4F_Msk</a></td></tr>
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<tr class="memitem:ga7d5fc8b9a6ea27582cb6c25f9654888c" id="r_ga7d5fc8b9a6ea27582cb6c25f9654888c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d5fc8b9a6ea27582cb6c25f9654888c">TIM_CCMR2_IC4F_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafdce62241567cc540d3b7ce61084c1e2">TIM_CCMR2_IC4F_Pos</a>)</td></tr>
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<tr class="separator:ga7d5fc8b9a6ea27582cb6c25f9654888c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4dcc1562c0c017493e4ee6b32354e85" id="r_gac4dcc1562c0c017493e4ee6b32354e85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4dcc1562c0c017493e4ee6b32354e85">TIM_CCMR2_IC4F_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafdce62241567cc540d3b7ce61084c1e2">TIM_CCMR2_IC4F_Pos</a>)</td></tr>
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<tr class="separator:gac4dcc1562c0c017493e4ee6b32354e85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b96de7db8b71ac7e414f247b871a53c" id="r_ga2b96de7db8b71ac7e414f247b871a53c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b96de7db8b71ac7e414f247b871a53c">TIM_CCMR2_IC4F_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafdce62241567cc540d3b7ce61084c1e2">TIM_CCMR2_IC4F_Pos</a>)</td></tr>
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<tr class="memitem:ga25d0f55e5b751f2caed6a943f5682a09" id="r_ga25d0f55e5b751f2caed6a943f5682a09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25d0f55e5b751f2caed6a943f5682a09">TIM_CCMR2_IC4F_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafdce62241567cc540d3b7ce61084c1e2">TIM_CCMR2_IC4F_Pos</a>)</td></tr>
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<tr class="separator:ga25d0f55e5b751f2caed6a943f5682a09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6da61acdf3f1662c2a522820260f0ca1" id="r_ga6da61acdf3f1662c2a522820260f0ca1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6da61acdf3f1662c2a522820260f0ca1">TIM_CCER_CC1E_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga871be5249ffb7666a32f4e2e60e50a8c" id="r_ga871be5249ffb7666a32f4e2e60e50a8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga871be5249ffb7666a32f4e2e60e50a8c">TIM_CCER_CC1E_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6da61acdf3f1662c2a522820260f0ca1">TIM_CCER_CC1E_Pos</a>)</td></tr>
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<tr class="separator:ga871be5249ffb7666a32f4e2e60e50a8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f494b9881e7b97bb2d79f7ad4e79937" id="r_ga3f494b9881e7b97bb2d79f7ad4e79937"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f494b9881e7b97bb2d79f7ad4e79937">TIM_CCER_CC1E</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga871be5249ffb7666a32f4e2e60e50a8c">TIM_CCER_CC1E_Msk</a></td></tr>
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<tr class="separator:ga3f494b9881e7b97bb2d79f7ad4e79937"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15c77329fadbcb3c84bde50fca4531fb" id="r_ga15c77329fadbcb3c84bde50fca4531fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15c77329fadbcb3c84bde50fca4531fb">TIM_CCER_CC1P_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga15c77329fadbcb3c84bde50fca4531fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3006ecce72e486321261536ae385732f" id="r_ga3006ecce72e486321261536ae385732f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3006ecce72e486321261536ae385732f">TIM_CCER_CC1P_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga15c77329fadbcb3c84bde50fca4531fb">TIM_CCER_CC1P_Pos</a>)</td></tr>
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<tr class="separator:ga3006ecce72e486321261536ae385732f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ca0aedba14241caff739afb3c3ee291" id="r_ga0ca0aedba14241caff739afb3c3ee291"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">TIM_CCER_CC1P</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3006ecce72e486321261536ae385732f">TIM_CCER_CC1P_Msk</a></td></tr>
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<tr class="separator:ga0ca0aedba14241caff739afb3c3ee291"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac27744605da2a44ce88bcd692a6dd639" id="r_gac27744605da2a44ce88bcd692a6dd639"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac27744605da2a44ce88bcd692a6dd639">TIM_CCER_CC1NE_Pos</a>   (2U)</td></tr>
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<tr class="separator:gac27744605da2a44ce88bcd692a6dd639"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f84300589fc23c7ad7c688b77adffd6" id="r_ga6f84300589fc23c7ad7c688b77adffd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f84300589fc23c7ad7c688b77adffd6">TIM_CCER_CC1NE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac27744605da2a44ce88bcd692a6dd639">TIM_CCER_CC1NE_Pos</a>)</td></tr>
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<tr class="separator:ga6f84300589fc23c7ad7c688b77adffd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga813056b3f90a13c4432aeba55f28957e" id="r_ga813056b3f90a13c4432aeba55f28957e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga813056b3f90a13c4432aeba55f28957e">TIM_CCER_CC1NE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f84300589fc23c7ad7c688b77adffd6">TIM_CCER_CC1NE_Msk</a></td></tr>
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<tr class="separator:ga813056b3f90a13c4432aeba55f28957e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17cab7ddc6363d68c881d424dc2f95b3" id="r_ga17cab7ddc6363d68c881d424dc2f95b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17cab7ddc6363d68c881d424dc2f95b3">TIM_CCER_CC1NP_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga17cab7ddc6363d68c881d424dc2f95b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22ca6b2d577776a67d48e9a7e1863700" id="r_ga22ca6b2d577776a67d48e9a7e1863700"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22ca6b2d577776a67d48e9a7e1863700">TIM_CCER_CC1NP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17cab7ddc6363d68c881d424dc2f95b3">TIM_CCER_CC1NP_Pos</a>)</td></tr>
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<tr class="separator:ga22ca6b2d577776a67d48e9a7e1863700"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga403fc501d4d8de6cabee6b07acb81a36" id="r_ga403fc501d4d8de6cabee6b07acb81a36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga403fc501d4d8de6cabee6b07acb81a36">TIM_CCER_CC1NP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga22ca6b2d577776a67d48e9a7e1863700">TIM_CCER_CC1NP_Msk</a></td></tr>
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<tr class="separator:ga403fc501d4d8de6cabee6b07acb81a36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a7e6fef34c0f02a97140620a2429b84" id="r_ga4a7e6fef34c0f02a97140620a2429b84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a7e6fef34c0f02a97140620a2429b84">TIM_CCER_CC2E_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga4a7e6fef34c0f02a97140620a2429b84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91010bed31fbd01d7013fe9be759b215" id="r_ga91010bed31fbd01d7013fe9be759b215"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91010bed31fbd01d7013fe9be759b215">TIM_CCER_CC2E_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a7e6fef34c0f02a97140620a2429b84">TIM_CCER_CC2E_Pos</a>)</td></tr>
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<tr class="separator:ga91010bed31fbd01d7013fe9be759b215"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76392a4d63674cd0db0a55762458f16c" id="r_ga76392a4d63674cd0db0a55762458f16c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76392a4d63674cd0db0a55762458f16c">TIM_CCER_CC2E</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga91010bed31fbd01d7013fe9be759b215">TIM_CCER_CC2E_Msk</a></td></tr>
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<tr class="separator:ga76392a4d63674cd0db0a55762458f16c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab6eed48ffae9d0a886c124b2993b8a9f" id="r_gab6eed48ffae9d0a886c124b2993b8a9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6eed48ffae9d0a886c124b2993b8a9f">TIM_CCER_CC2P_Pos</a>   (5U)</td></tr>
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<tr class="separator:gab6eed48ffae9d0a886c124b2993b8a9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95f10f70479dce9444a304a58dfa52e1" id="r_ga95f10f70479dce9444a304a58dfa52e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95f10f70479dce9444a304a58dfa52e1">TIM_CCER_CC2P_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab6eed48ffae9d0a886c124b2993b8a9f">TIM_CCER_CC2P_Pos</a>)</td></tr>
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<tr class="separator:ga95f10f70479dce9444a304a58dfa52e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3136c6e776c6066509d298b6a9b34912" id="r_ga3136c6e776c6066509d298b6a9b34912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3136c6e776c6066509d298b6a9b34912">TIM_CCER_CC2P</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga95f10f70479dce9444a304a58dfa52e1">TIM_CCER_CC2P_Msk</a></td></tr>
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<tr class="separator:ga3136c6e776c6066509d298b6a9b34912"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a035ed74e6d62a0fcf54bd0b31f785a" id="r_ga5a035ed74e6d62a0fcf54bd0b31f785a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a035ed74e6d62a0fcf54bd0b31f785a">TIM_CCER_CC2NE_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga5a035ed74e6d62a0fcf54bd0b31f785a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga395e49f88082d5e2144801c98047e03b" id="r_ga395e49f88082d5e2144801c98047e03b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga395e49f88082d5e2144801c98047e03b">TIM_CCER_CC2NE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a035ed74e6d62a0fcf54bd0b31f785a">TIM_CCER_CC2NE_Pos</a>)</td></tr>
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<tr class="separator:ga395e49f88082d5e2144801c98047e03b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a784649120eddec31998f34323d4156" id="r_ga6a784649120eddec31998f34323d4156"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a784649120eddec31998f34323d4156">TIM_CCER_CC2NE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga395e49f88082d5e2144801c98047e03b">TIM_CCER_CC2NE_Msk</a></td></tr>
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<tr class="separator:ga6a784649120eddec31998f34323d4156"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8de88ef55a7e82a4fe7379a0568da7ab" id="r_ga8de88ef55a7e82a4fe7379a0568da7ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8de88ef55a7e82a4fe7379a0568da7ab">TIM_CCER_CC2NP_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga8de88ef55a7e82a4fe7379a0568da7ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b294ed91060a15ee77651cd8e688e70" id="r_ga1b294ed91060a15ee77651cd8e688e70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b294ed91060a15ee77651cd8e688e70">TIM_CCER_CC2NP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8de88ef55a7e82a4fe7379a0568da7ab">TIM_CCER_CC2NP_Pos</a>)</td></tr>
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<tr class="separator:ga1b294ed91060a15ee77651cd8e688e70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga387de559d8b16b16f3934fddd2aa969f" id="r_ga387de559d8b16b16f3934fddd2aa969f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga387de559d8b16b16f3934fddd2aa969f">TIM_CCER_CC2NP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b294ed91060a15ee77651cd8e688e70">TIM_CCER_CC2NP_Msk</a></td></tr>
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<tr class="separator:ga387de559d8b16b16f3934fddd2aa969f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaee67670829d7a6333cae4b5eada7899" id="r_gaaee67670829d7a6333cae4b5eada7899"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaee67670829d7a6333cae4b5eada7899">TIM_CCER_CC3E_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaaee67670829d7a6333cae4b5eada7899"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga800a18a966d63d71dfc6cf7e3c18ca08" id="r_ga800a18a966d63d71dfc6cf7e3c18ca08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga800a18a966d63d71dfc6cf7e3c18ca08">TIM_CCER_CC3E_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaee67670829d7a6333cae4b5eada7899">TIM_CCER_CC3E_Pos</a>)</td></tr>
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<tr class="memitem:ga1da114e666b61f09cf25f50cdaa7f81f" id="r_ga1da114e666b61f09cf25f50cdaa7f81f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1da114e666b61f09cf25f50cdaa7f81f">TIM_CCER_CC3E</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga800a18a966d63d71dfc6cf7e3c18ca08">TIM_CCER_CC3E_Msk</a></td></tr>
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<tr class="separator:ga1da114e666b61f09cf25f50cdaa7f81f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab92731a4de3cb45962bfc34f3986a3bb" id="r_gab92731a4de3cb45962bfc34f3986a3bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab92731a4de3cb45962bfc34f3986a3bb">TIM_CCER_CC3P_Pos</a>   (9U)</td></tr>
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<tr class="separator:gab92731a4de3cb45962bfc34f3986a3bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga647aadf30c1f4c7850a025bce9e264a6" id="r_ga647aadf30c1f4c7850a025bce9e264a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga647aadf30c1f4c7850a025bce9e264a6">TIM_CCER_CC3P_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab92731a4de3cb45962bfc34f3986a3bb">TIM_CCER_CC3P_Pos</a>)</td></tr>
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<tr class="separator:ga647aadf30c1f4c7850a025bce9e264a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6220a5cd34c7a7a39e10c854aa00d2e5" id="r_ga6220a5cd34c7a7a39e10c854aa00d2e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6220a5cd34c7a7a39e10c854aa00d2e5">TIM_CCER_CC3P</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga647aadf30c1f4c7850a025bce9e264a6">TIM_CCER_CC3P_Msk</a></td></tr>
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<tr class="separator:ga6220a5cd34c7a7a39e10c854aa00d2e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e4ec9ec3d3f6b778c7750f4861de8dc" id="r_ga0e4ec9ec3d3f6b778c7750f4861de8dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e4ec9ec3d3f6b778c7750f4861de8dc">TIM_CCER_CC3NE_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga0e4ec9ec3d3f6b778c7750f4861de8dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34cbf30b58b4fa02ddc7c1bab93420b3" id="r_ga34cbf30b58b4fa02ddc7c1bab93420b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34cbf30b58b4fa02ddc7c1bab93420b3">TIM_CCER_CC3NE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e4ec9ec3d3f6b778c7750f4861de8dc">TIM_CCER_CC3NE_Pos</a>)</td></tr>
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<tr class="separator:ga34cbf30b58b4fa02ddc7c1bab93420b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad46cce61d3bd83b64257ba75e54ee1aa" id="r_gad46cce61d3bd83b64257ba75e54ee1aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad46cce61d3bd83b64257ba75e54ee1aa">TIM_CCER_CC3NE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34cbf30b58b4fa02ddc7c1bab93420b3">TIM_CCER_CC3NE_Msk</a></td></tr>
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<tr class="separator:gad46cce61d3bd83b64257ba75e54ee1aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc4768173a56472e6f19ca49bb229e6a" id="r_gacc4768173a56472e6f19ca49bb229e6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc4768173a56472e6f19ca49bb229e6a">TIM_CCER_CC3NP_Pos</a>   (11U)</td></tr>
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<tr class="separator:gacc4768173a56472e6f19ca49bb229e6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga013c6bc2ba905dea2713cdef67f39c6f" id="r_ga013c6bc2ba905dea2713cdef67f39c6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga013c6bc2ba905dea2713cdef67f39c6f">TIM_CCER_CC3NP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacc4768173a56472e6f19ca49bb229e6a">TIM_CCER_CC3NP_Pos</a>)</td></tr>
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<tr class="separator:ga013c6bc2ba905dea2713cdef67f39c6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4029686d3307111d3f9f4400e29e4521" id="r_ga4029686d3307111d3f9f4400e29e4521"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4029686d3307111d3f9f4400e29e4521">TIM_CCER_CC3NP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga013c6bc2ba905dea2713cdef67f39c6f">TIM_CCER_CC3NP_Msk</a></td></tr>
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<tr class="separator:ga4029686d3307111d3f9f4400e29e4521"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e4f1890df26547229ce711eed7a30c3" id="r_ga8e4f1890df26547229ce711eed7a30c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e4f1890df26547229ce711eed7a30c3">TIM_CCER_CC4E_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga8e4f1890df26547229ce711eed7a30c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8f00da3ce9a145e9c7c0ece18706d05" id="r_gae8f00da3ce9a145e9c7c0ece18706d05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8f00da3ce9a145e9c7c0ece18706d05">TIM_CCER_CC4E_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e4f1890df26547229ce711eed7a30c3">TIM_CCER_CC4E_Pos</a>)</td></tr>
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<tr class="separator:gae8f00da3ce9a145e9c7c0ece18706d05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga940b041ab5975311f42f26d314a4b621" id="r_ga940b041ab5975311f42f26d314a4b621"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga940b041ab5975311f42f26d314a4b621">TIM_CCER_CC4E</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae8f00da3ce9a145e9c7c0ece18706d05">TIM_CCER_CC4E_Msk</a></td></tr>
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<tr class="separator:ga940b041ab5975311f42f26d314a4b621"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b16bb9029a386a09ca24796a74f7fa8" id="r_ga0b16bb9029a386a09ca24796a74f7fa8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b16bb9029a386a09ca24796a74f7fa8">TIM_CCER_CC4P_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0b16bb9029a386a09ca24796a74f7fa8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22962f81c9abfc88ae30f50b5592d3a7" id="r_ga22962f81c9abfc88ae30f50b5592d3a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22962f81c9abfc88ae30f50b5592d3a7">TIM_CCER_CC4P_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b16bb9029a386a09ca24796a74f7fa8">TIM_CCER_CC4P_Pos</a>)</td></tr>
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<tr class="separator:ga22962f81c9abfc88ae30f50b5592d3a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3faf23dc47e1b0877352d7f5a00f72e1" id="r_ga3faf23dc47e1b0877352d7f5a00f72e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3faf23dc47e1b0877352d7f5a00f72e1">TIM_CCER_CC4P</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga22962f81c9abfc88ae30f50b5592d3a7">TIM_CCER_CC4P_Msk</a></td></tr>
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<tr class="separator:ga3faf23dc47e1b0877352d7f5a00f72e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga451b690ca839a363b6b911bcacafffb4" id="r_ga451b690ca839a363b6b911bcacafffb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga451b690ca839a363b6b911bcacafffb4">TIM_CCER_CC4NP_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga451b690ca839a363b6b911bcacafffb4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e263b29e870a454c029f4a825f4f50e" id="r_ga7e263b29e870a454c029f4a825f4f50e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e263b29e870a454c029f4a825f4f50e">TIM_CCER_CC4NP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga451b690ca839a363b6b911bcacafffb4">TIM_CCER_CC4NP_Pos</a>)</td></tr>
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<tr class="separator:ga7e263b29e870a454c029f4a825f4f50e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41b88bff3f38cec0617ce66fa5aef260" id="r_ga41b88bff3f38cec0617ce66fa5aef260"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41b88bff3f38cec0617ce66fa5aef260">TIM_CCER_CC4NP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e263b29e870a454c029f4a825f4f50e">TIM_CCER_CC4NP_Msk</a></td></tr>
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<tr class="separator:ga41b88bff3f38cec0617ce66fa5aef260"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf110ca46cc8cf7b55f63cafa563073b2" id="r_gaf110ca46cc8cf7b55f63cafa563073b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf110ca46cc8cf7b55f63cafa563073b2">TIM_CNT_CNT_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf110ca46cc8cf7b55f63cafa563073b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac54bb0107f222981fe8c8416af521fd0" id="r_gac54bb0107f222981fe8c8416af521fd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac54bb0107f222981fe8c8416af521fd0">TIM_CNT_CNT_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf110ca46cc8cf7b55f63cafa563073b2">TIM_CNT_CNT_Pos</a>)</td></tr>
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<tr class="separator:gac54bb0107f222981fe8c8416af521fd0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8bc45c0315de82c1c3a38a243bcd00fc" id="r_ga8bc45c0315de82c1c3a38a243bcd00fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8bc45c0315de82c1c3a38a243bcd00fc">TIM_CNT_CNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac54bb0107f222981fe8c8416af521fd0">TIM_CNT_CNT_Msk</a></td></tr>
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<tr class="separator:ga8bc45c0315de82c1c3a38a243bcd00fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac11163ae1ef14d3e7a1f047c40a501f4" id="r_gac11163ae1ef14d3e7a1f047c40a501f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac11163ae1ef14d3e7a1f047c40a501f4">TIM_PSC_PSC_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac11163ae1ef14d3e7a1f047c40a501f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacff3a421342fafac2e25421084bd85df" id="r_gacff3a421342fafac2e25421084bd85df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacff3a421342fafac2e25421084bd85df">TIM_PSC_PSC_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac11163ae1ef14d3e7a1f047c40a501f4">TIM_PSC_PSC_Pos</a>)</td></tr>
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<tr class="separator:gacff3a421342fafac2e25421084bd85df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefb85e4000ddab0ada67c5964810da35" id="r_gaefb85e4000ddab0ada67c5964810da35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefb85e4000ddab0ada67c5964810da35">TIM_PSC_PSC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacff3a421342fafac2e25421084bd85df">TIM_PSC_PSC_Msk</a></td></tr>
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<tr class="memitem:ga8430ae919aa2e98c8a4cb32049ae5c3b" id="r_ga8430ae919aa2e98c8a4cb32049ae5c3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8430ae919aa2e98c8a4cb32049ae5c3b">TIM_ARR_ARR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8430ae919aa2e98c8a4cb32049ae5c3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga166174bde137aa84aec495eef6907ed3" id="r_ga166174bde137aa84aec495eef6907ed3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga166174bde137aa84aec495eef6907ed3">TIM_ARR_ARR_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8430ae919aa2e98c8a4cb32049ae5c3b">TIM_ARR_ARR_Pos</a>)</td></tr>
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<tr class="separator:ga166174bde137aa84aec495eef6907ed3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace50256fdecc38f641050a4a3266e4d9" id="r_gace50256fdecc38f641050a4a3266e4d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace50256fdecc38f641050a4a3266e4d9">TIM_ARR_ARR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga166174bde137aa84aec495eef6907ed3">TIM_ARR_ARR_Msk</a></td></tr>
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<tr class="separator:gace50256fdecc38f641050a4a3266e4d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab062a3ee5ed93cef0fd1de937719fe5c" id="r_gab062a3ee5ed93cef0fd1de937719fe5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab062a3ee5ed93cef0fd1de937719fe5c">TIM_RCR_REP_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab062a3ee5ed93cef0fd1de937719fe5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06e8380ec8ac6138f401fa53833978fc" id="r_ga06e8380ec8ac6138f401fa53833978fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06e8380ec8ac6138f401fa53833978fc">TIM_RCR_REP_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab062a3ee5ed93cef0fd1de937719fe5c">TIM_RCR_REP_Pos</a>)</td></tr>
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<tr class="separator:ga06e8380ec8ac6138f401fa53833978fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcef8f28580e36cdfda3be1f7561afc7" id="r_gadcef8f28580e36cdfda3be1f7561afc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcef8f28580e36cdfda3be1f7561afc7">TIM_RCR_REP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06e8380ec8ac6138f401fa53833978fc">TIM_RCR_REP_Msk</a></td></tr>
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<tr class="separator:gadcef8f28580e36cdfda3be1f7561afc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga815f704b96c35f8f2b4a9160913e36f6" id="r_ga815f704b96c35f8f2b4a9160913e36f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga815f704b96c35f8f2b4a9160913e36f6">TIM_CCR1_CCR1_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga815f704b96c35f8f2b4a9160913e36f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1052d30a540b5332d39cc9e1e23587bb" id="r_ga1052d30a540b5332d39cc9e1e23587bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1052d30a540b5332d39cc9e1e23587bb">TIM_CCR1_CCR1_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga815f704b96c35f8f2b4a9160913e36f6">TIM_CCR1_CCR1_Pos</a>)</td></tr>
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<tr class="separator:ga1052d30a540b5332d39cc9e1e23587bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac927cc11eff415210dcf94657d8dfbe0" id="r_gac927cc11eff415210dcf94657d8dfbe0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac927cc11eff415210dcf94657d8dfbe0">TIM_CCR1_CCR1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1052d30a540b5332d39cc9e1e23587bb">TIM_CCR1_CCR1_Msk</a></td></tr>
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<tr class="memitem:ga22f43b4f1a39a8ff5124a31e2e37efbf" id="r_ga22f43b4f1a39a8ff5124a31e2e37efbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22f43b4f1a39a8ff5124a31e2e37efbf">TIM_CCR2_CCR2_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga22f43b4f1a39a8ff5124a31e2e37efbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4ef3300e4399d1b036c2e28061d9dd1" id="r_gab4ef3300e4399d1b036c2e28061d9dd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4ef3300e4399d1b036c2e28061d9dd1">TIM_CCR2_CCR2_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga22f43b4f1a39a8ff5124a31e2e37efbf">TIM_CCR2_CCR2_Pos</a>)</td></tr>
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<tr class="memitem:ga751e5efd90bdd1fd5f38609f3f5762ba" id="r_ga751e5efd90bdd1fd5f38609f3f5762ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga751e5efd90bdd1fd5f38609f3f5762ba">TIM_CCR2_CCR2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab4ef3300e4399d1b036c2e28061d9dd1">TIM_CCR2_CCR2_Msk</a></td></tr>
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<tr class="separator:ga751e5efd90bdd1fd5f38609f3f5762ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69a2438c905cf2e7f0c15b06090be697" id="r_ga69a2438c905cf2e7f0c15b06090be697"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69a2438c905cf2e7f0c15b06090be697">TIM_CCR3_CCR3_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga69a2438c905cf2e7f0c15b06090be697"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3983e861f1f4418bf3df69d263550024" id="r_ga3983e861f1f4418bf3df69d263550024"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3983e861f1f4418bf3df69d263550024">TIM_CCR3_CCR3_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69a2438c905cf2e7f0c15b06090be697">TIM_CCR3_CCR3_Pos</a>)</td></tr>
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<tr class="memitem:ga4e85064d37d387851e95c5c1f35315a1" id="r_ga4e85064d37d387851e95c5c1f35315a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e85064d37d387851e95c5c1f35315a1">TIM_CCR3_CCR3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3983e861f1f4418bf3df69d263550024">TIM_CCR3_CCR3_Msk</a></td></tr>
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<tr class="separator:ga4e85064d37d387851e95c5c1f35315a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga812691bb8cabc5eef6093926c6afb0fa" id="r_ga812691bb8cabc5eef6093926c6afb0fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga812691bb8cabc5eef6093926c6afb0fa">TIM_CCR4_CCR4_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga812691bb8cabc5eef6093926c6afb0fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e2e10599fa35e837f604584c742551f" id="r_ga2e2e10599fa35e837f604584c742551f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e2e10599fa35e837f604584c742551f">TIM_CCR4_CCR4_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga812691bb8cabc5eef6093926c6afb0fa">TIM_CCR4_CCR4_Pos</a>)</td></tr>
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<tr class="separator:ga2e2e10599fa35e837f604584c742551f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15c9dd67a6701b5498926ae536773eca" id="r_ga15c9dd67a6701b5498926ae536773eca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15c9dd67a6701b5498926ae536773eca">TIM_CCR4_CCR4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e2e10599fa35e837f604584c742551f">TIM_CCR4_CCR4_Msk</a></td></tr>
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<tr class="separator:ga15c9dd67a6701b5498926ae536773eca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20f8f8f7a4e2e060b4b51e0a8adc6201" id="r_ga20f8f8f7a4e2e060b4b51e0a8adc6201"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">TIM_BDTR_DTG_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga20f8f8f7a4e2e060b4b51e0a8adc6201"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c52bd0a743ce97111f4f7210f4f0875" id="r_ga2c52bd0a743ce97111f4f7210f4f0875"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c52bd0a743ce97111f4f7210f4f0875">TIM_BDTR_DTG_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">TIM_BDTR_DTG_Pos</a>)</td></tr>
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<tr class="separator:ga2c52bd0a743ce97111f4f7210f4f0875"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabcf985e9c78f15e1e44b2bc4d2bafc67" id="r_gabcf985e9c78f15e1e44b2bc4d2bafc67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabcf985e9c78f15e1e44b2bc4d2bafc67">TIM_BDTR_DTG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c52bd0a743ce97111f4f7210f4f0875">TIM_BDTR_DTG_Msk</a></td></tr>
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<tr class="separator:gabcf985e9c78f15e1e44b2bc4d2bafc67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b575cca31b0e22ef1d5b842aa162bfc" id="r_ga4b575cca31b0e22ef1d5b842aa162bfc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b575cca31b0e22ef1d5b842aa162bfc">TIM_BDTR_DTG_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">TIM_BDTR_DTG_Pos</a>)</td></tr>
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<tr class="separator:ga4b575cca31b0e22ef1d5b842aa162bfc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f33ae1e9b7847a60032a60d0cc7f81d" id="r_ga0f33ae1e9b7847a60032a60d0cc7f81d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f33ae1e9b7847a60032a60d0cc7f81d">TIM_BDTR_DTG_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">TIM_BDTR_DTG_Pos</a>)</td></tr>
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<tr class="separator:ga0f33ae1e9b7847a60032a60d0cc7f81d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f06a132eba960bd6cc972e3580d537c" id="r_ga2f06a132eba960bd6cc972e3580d537c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f06a132eba960bd6cc972e3580d537c">TIM_BDTR_DTG_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">TIM_BDTR_DTG_Pos</a>)</td></tr>
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<tr class="separator:ga2f06a132eba960bd6cc972e3580d537c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7868643a65285fc7132f040c8950f43" id="r_gae7868643a65285fc7132f040c8950f43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7868643a65285fc7132f040c8950f43">TIM_BDTR_DTG_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">TIM_BDTR_DTG_Pos</a>)</td></tr>
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<tr class="separator:gae7868643a65285fc7132f040c8950f43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga503b44e30a5fb77c34630d1faca70213" id="r_ga503b44e30a5fb77c34630d1faca70213"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga503b44e30a5fb77c34630d1faca70213">TIM_BDTR_DTG_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">TIM_BDTR_DTG_Pos</a>)</td></tr>
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<tr class="separator:ga503b44e30a5fb77c34630d1faca70213"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83a12ecb0a8dd21bc164d9a345ea564f" id="r_ga83a12ecb0a8dd21bc164d9a345ea564f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83a12ecb0a8dd21bc164d9a345ea564f">TIM_BDTR_DTG_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">TIM_BDTR_DTG_Pos</a>)</td></tr>
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<tr class="separator:ga83a12ecb0a8dd21bc164d9a345ea564f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7d418cbd0db89991522cb6be34a017e" id="r_gaf7d418cbd0db89991522cb6be34a017e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7d418cbd0db89991522cb6be34a017e">TIM_BDTR_DTG_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">TIM_BDTR_DTG_Pos</a>)</td></tr>
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<tr class="separator:gaf7d418cbd0db89991522cb6be34a017e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac945c8bcf5567912a88eb2acee53c45b" id="r_gac945c8bcf5567912a88eb2acee53c45b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac945c8bcf5567912a88eb2acee53c45b">TIM_BDTR_DTG_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">TIM_BDTR_DTG_Pos</a>)</td></tr>
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<tr class="separator:gac945c8bcf5567912a88eb2acee53c45b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71810028fd9aba73ee3b92d59017cb8d" id="r_ga71810028fd9aba73ee3b92d59017cb8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71810028fd9aba73ee3b92d59017cb8d">TIM_BDTR_LOCK_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga71810028fd9aba73ee3b92d59017cb8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31c7b82190b30d879c3c7b3a46b9ab82" id="r_ga31c7b82190b30d879c3c7b3a46b9ab82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31c7b82190b30d879c3c7b3a46b9ab82">TIM_BDTR_LOCK_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71810028fd9aba73ee3b92d59017cb8d">TIM_BDTR_LOCK_Pos</a>)</td></tr>
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<tr class="separator:ga31c7b82190b30d879c3c7b3a46b9ab82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e4215d17f0548dfcf0b15fe4d0f4651" id="r_ga7e4215d17f0548dfcf0b15fe4d0f4651"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e4215d17f0548dfcf0b15fe4d0f4651">TIM_BDTR_LOCK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31c7b82190b30d879c3c7b3a46b9ab82">TIM_BDTR_LOCK_Msk</a></td></tr>
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<tr class="separator:ga7e4215d17f0548dfcf0b15fe4d0f4651"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabbd1736c8172e7cd098bb591264b07bf" id="r_gabbd1736c8172e7cd098bb591264b07bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbd1736c8172e7cd098bb591264b07bf">TIM_BDTR_LOCK_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71810028fd9aba73ee3b92d59017cb8d">TIM_BDTR_LOCK_Pos</a>)</td></tr>
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<tr class="separator:gabbd1736c8172e7cd098bb591264b07bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga756df80ff8c34399435f52dca18e6eee" id="r_ga756df80ff8c34399435f52dca18e6eee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga756df80ff8c34399435f52dca18e6eee">TIM_BDTR_LOCK_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71810028fd9aba73ee3b92d59017cb8d">TIM_BDTR_LOCK_Pos</a>)</td></tr>
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<tr class="separator:ga756df80ff8c34399435f52dca18e6eee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga508a8d8aea6def7bd3dd689ff5f47312" id="r_ga508a8d8aea6def7bd3dd689ff5f47312"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga508a8d8aea6def7bd3dd689ff5f47312">TIM_BDTR_OSSI_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga508a8d8aea6def7bd3dd689ff5f47312"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05ff8c5f843f6587554de55163a0f420" id="r_ga05ff8c5f843f6587554de55163a0f420"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05ff8c5f843f6587554de55163a0f420">TIM_BDTR_OSSI_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga508a8d8aea6def7bd3dd689ff5f47312">TIM_BDTR_OSSI_Pos</a>)</td></tr>
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<tr class="separator:ga05ff8c5f843f6587554de55163a0f420"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1cf04e70ccf3d4aba5afcf2496a411a" id="r_gab1cf04e70ccf3d4aba5afcf2496a411a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1cf04e70ccf3d4aba5afcf2496a411a">TIM_BDTR_OSSI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga05ff8c5f843f6587554de55163a0f420">TIM_BDTR_OSSI_Msk</a></td></tr>
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<tr class="separator:gab1cf04e70ccf3d4aba5afcf2496a411a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5738bf6a27c598bc93b37db41f1a21c1" id="r_ga5738bf6a27c598bc93b37db41f1a21c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5738bf6a27c598bc93b37db41f1a21c1">TIM_BDTR_OSSR_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga5738bf6a27c598bc93b37db41f1a21c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga396c60115df4f4f217ae3b2df15d130c" id="r_ga396c60115df4f4f217ae3b2df15d130c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga396c60115df4f4f217ae3b2df15d130c">TIM_BDTR_OSSR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5738bf6a27c598bc93b37db41f1a21c1">TIM_BDTR_OSSR_Pos</a>)</td></tr>
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<tr class="separator:ga396c60115df4f4f217ae3b2df15d130c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9435f36d53c6be1107e57ab6a82c16e" id="r_gaf9435f36d53c6be1107e57ab6a82c16e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9435f36d53c6be1107e57ab6a82c16e">TIM_BDTR_OSSR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga396c60115df4f4f217ae3b2df15d130c">TIM_BDTR_OSSR_Msk</a></td></tr>
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<tr class="memitem:ga27bff46bd1b077d0a152e4600397f98d" id="r_ga27bff46bd1b077d0a152e4600397f98d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27bff46bd1b077d0a152e4600397f98d">TIM_BDTR_BKE_Pos</a>   (12U)</td></tr>
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<tr class="memitem:ga2272c6e4c575623c1f46f482cd957415" id="r_ga2272c6e4c575623c1f46f482cd957415"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2272c6e4c575623c1f46f482cd957415">TIM_BDTR_BKE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27bff46bd1b077d0a152e4600397f98d">TIM_BDTR_BKE_Pos</a>)</td></tr>
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<tr class="separator:ga2272c6e4c575623c1f46f482cd957415"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74250b040dd9fd9c09dcc54cdd6d86d8" id="r_ga74250b040dd9fd9c09dcc54cdd6d86d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74250b040dd9fd9c09dcc54cdd6d86d8">TIM_BDTR_BKE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2272c6e4c575623c1f46f482cd957415">TIM_BDTR_BKE_Msk</a></td></tr>
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<tr class="separator:ga74250b040dd9fd9c09dcc54cdd6d86d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf42525a0a24fac15595720c1ef01d57a" id="r_gaf42525a0a24fac15595720c1ef01d57a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf42525a0a24fac15595720c1ef01d57a">TIM_BDTR_BKP_Pos</a>   (13U)</td></tr>
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<tr class="memitem:ga101b7d11ccc8db986ee394ec26167130" id="r_ga101b7d11ccc8db986ee394ec26167130"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga101b7d11ccc8db986ee394ec26167130">TIM_BDTR_BKP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf42525a0a24fac15595720c1ef01d57a">TIM_BDTR_BKP_Pos</a>)</td></tr>
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<tr class="memitem:ga3247abbbf0d00260be051d176d88020e" id="r_ga3247abbbf0d00260be051d176d88020e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3247abbbf0d00260be051d176d88020e">TIM_BDTR_BKP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga101b7d11ccc8db986ee394ec26167130">TIM_BDTR_BKP_Msk</a></td></tr>
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<tr class="memitem:ga7c59af6d6570d3f4c7bff1efcde8fd5a" id="r_ga7c59af6d6570d3f4c7bff1efcde8fd5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c59af6d6570d3f4c7bff1efcde8fd5a">TIM_BDTR_AOE_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gaa9f2a293cb57e4e53908ff3968b44eda" id="r_gaa9f2a293cb57e4e53908ff3968b44eda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9f2a293cb57e4e53908ff3968b44eda">TIM_BDTR_AOE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c59af6d6570d3f4c7bff1efcde8fd5a">TIM_BDTR_AOE_Pos</a>)</td></tr>
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<tr class="memitem:ga59f15008050f91fa3ecc9eaaa971a509" id="r_ga59f15008050f91fa3ecc9eaaa971a509"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59f15008050f91fa3ecc9eaaa971a509">TIM_BDTR_AOE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9f2a293cb57e4e53908ff3968b44eda">TIM_BDTR_AOE_Msk</a></td></tr>
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<tr class="memitem:gae1874eb52559400db69885a6dee768c4" id="r_gae1874eb52559400db69885a6dee768c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1874eb52559400db69885a6dee768c4">TIM_BDTR_MOE_Pos</a>   (15U)</td></tr>
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<tr class="memitem:gaead4c63fdacf9c85e3c997275649aa8e" id="r_gaead4c63fdacf9c85e3c997275649aa8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaead4c63fdacf9c85e3c997275649aa8e">TIM_BDTR_MOE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae1874eb52559400db69885a6dee768c4">TIM_BDTR_MOE_Pos</a>)</td></tr>
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<tr class="memitem:ga277a096614829feba2d0a4fbb7d3dffc" id="r_ga277a096614829feba2d0a4fbb7d3dffc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga277a096614829feba2d0a4fbb7d3dffc">TIM_BDTR_MOE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaead4c63fdacf9c85e3c997275649aa8e">TIM_BDTR_MOE_Msk</a></td></tr>
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<tr class="memitem:ga3a306a1cb19e8538984d63e2728f18c9" id="r_ga3a306a1cb19e8538984d63e2728f18c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a306a1cb19e8538984d63e2728f18c9">TIM_DCR_DBA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3a306a1cb19e8538984d63e2728f18c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga603bd90bfdd7e08fb4c749c926ae8d0d" id="r_ga603bd90bfdd7e08fb4c749c926ae8d0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga603bd90bfdd7e08fb4c749c926ae8d0d">TIM_DCR_DBA_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a306a1cb19e8538984d63e2728f18c9">TIM_DCR_DBA_Pos</a>)</td></tr>
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<tr class="separator:ga603bd90bfdd7e08fb4c749c926ae8d0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf9051ecac123cd89f9d2a835e4cde2e" id="r_gabf9051ecac123cd89f9d2a835e4cde2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf9051ecac123cd89f9d2a835e4cde2e">TIM_DCR_DBA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga603bd90bfdd7e08fb4c749c926ae8d0d">TIM_DCR_DBA_Msk</a></td></tr>
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<tr class="separator:gabf9051ecac123cd89f9d2a835e4cde2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaaf610e5fe4bb4b10736242df3b62bba" id="r_gaaaf610e5fe4bb4b10736242df3b62bba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaaf610e5fe4bb4b10736242df3b62bba">TIM_DCR_DBA_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a306a1cb19e8538984d63e2728f18c9">TIM_DCR_DBA_Pos</a>)</td></tr>
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<tr class="separator:gaaaf610e5fe4bb4b10736242df3b62bba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a0185643c163930e30f0a1cf5fe364e" id="r_ga9a0185643c163930e30f0a1cf5fe364e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a0185643c163930e30f0a1cf5fe364e">TIM_DCR_DBA_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a306a1cb19e8538984d63e2728f18c9">TIM_DCR_DBA_Pos</a>)</td></tr>
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<tr class="separator:ga9a0185643c163930e30f0a1cf5fe364e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa5a89b93b97b0968a7d5563a18ab9d1" id="r_gaaa5a89b93b97b0968a7d5563a18ab9d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa5a89b93b97b0968a7d5563a18ab9d1">TIM_DCR_DBA_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a306a1cb19e8538984d63e2728f18c9">TIM_DCR_DBA_Pos</a>)</td></tr>
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<tr class="memitem:ga105f44ff18cbbd4ff4d60368c9184430" id="r_ga105f44ff18cbbd4ff4d60368c9184430"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga105f44ff18cbbd4ff4d60368c9184430">TIM_DCR_DBA_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a306a1cb19e8538984d63e2728f18c9">TIM_DCR_DBA_Pos</a>)</td></tr>
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<tr class="memitem:gabe1bc4b6dd7265dee2857f23d835b2dc" id="r_gabe1bc4b6dd7265dee2857f23d835b2dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe1bc4b6dd7265dee2857f23d835b2dc">TIM_DCR_DBA_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a306a1cb19e8538984d63e2728f18c9">TIM_DCR_DBA_Pos</a>)</td></tr>
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<tr class="separator:gabe1bc4b6dd7265dee2857f23d835b2dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e78721748388667766590962b29f610" id="r_ga2e78721748388667766590962b29f610"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e78721748388667766590962b29f610">TIM_DCR_DBL_Pos</a>   (8U)</td></tr>
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<tr class="memitem:ga19d5bc5ed6177c1603a35d52918e5068" id="r_ga19d5bc5ed6177c1603a35d52918e5068"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19d5bc5ed6177c1603a35d52918e5068">TIM_DCR_DBL_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e78721748388667766590962b29f610">TIM_DCR_DBL_Pos</a>)</td></tr>
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<tr class="memitem:gab9e197a78484567d4c6093c28265f3eb" id="r_gab9e197a78484567d4c6093c28265f3eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9e197a78484567d4c6093c28265f3eb">TIM_DCR_DBL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga19d5bc5ed6177c1603a35d52918e5068">TIM_DCR_DBL_Msk</a></td></tr>
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<tr class="separator:gab9e197a78484567d4c6093c28265f3eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga677195c0b4892bb6717564c0528126a9" id="r_ga677195c0b4892bb6717564c0528126a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga677195c0b4892bb6717564c0528126a9">TIM_DCR_DBL_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e78721748388667766590962b29f610">TIM_DCR_DBL_Pos</a>)</td></tr>
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<tr class="memitem:gad427ba987877e491f7a2be60e320dbea" id="r_gad427ba987877e491f7a2be60e320dbea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad427ba987877e491f7a2be60e320dbea">TIM_DCR_DBL_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e78721748388667766590962b29f610">TIM_DCR_DBL_Pos</a>)</td></tr>
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<tr class="memitem:ga369926f2a8ca5cf635ded9bb4619189c" id="r_ga369926f2a8ca5cf635ded9bb4619189c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga369926f2a8ca5cf635ded9bb4619189c">TIM_DCR_DBL_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e78721748388667766590962b29f610">TIM_DCR_DBL_Pos</a>)</td></tr>
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<tr class="memitem:ga7f1ec849c41d1abd46c528a4ac378c03" id="r_ga7f1ec849c41d1abd46c528a4ac378c03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f1ec849c41d1abd46c528a4ac378c03">TIM_DCR_DBL_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e78721748388667766590962b29f610">TIM_DCR_DBL_Pos</a>)</td></tr>
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<tr class="memitem:ga607d7b87b1b4bf167aabad36f922a8f9" id="r_ga607d7b87b1b4bf167aabad36f922a8f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga607d7b87b1b4bf167aabad36f922a8f9">TIM_DCR_DBL_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e78721748388667766590962b29f610">TIM_DCR_DBL_Pos</a>)</td></tr>
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<tr class="memitem:ga404a796ef83390218d4aed467f779ca0" id="r_ga404a796ef83390218d4aed467f779ca0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga404a796ef83390218d4aed467f779ca0">TIM_DMAR_DMAB_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga404a796ef83390218d4aed467f779ca0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5d6d71391fa416ce5c1aa65e459d92a" id="r_gaa5d6d71391fa416ce5c1aa65e459d92a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5d6d71391fa416ce5c1aa65e459d92a">TIM_DMAR_DMAB_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga404a796ef83390218d4aed467f779ca0">TIM_DMAR_DMAB_Pos</a>)</td></tr>
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<tr class="memitem:ga1afa2fc02bcd75c15122c4eb87d6cf83" id="r_ga1afa2fc02bcd75c15122c4eb87d6cf83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1afa2fc02bcd75c15122c4eb87d6cf83">TIM_DMAR_DMAB</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5d6d71391fa416ce5c1aa65e459d92a">TIM_DMAR_DMAB_Msk</a></td></tr>
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<tr class="memitem:ga3f62ec5e16705319b0d7ecdc54471788" id="r_ga3f62ec5e16705319b0d7ecdc54471788"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f62ec5e16705319b0d7ecdc54471788">TIM_OR_TI1_RMP_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga3e8ec8a0faf4bc51e04f909e3b13708e" id="r_ga3e8ec8a0faf4bc51e04f909e3b13708e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e8ec8a0faf4bc51e04f909e3b13708e">TIM_OR_TI1_RMP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f62ec5e16705319b0d7ecdc54471788">TIM_OR_TI1_RMP_Pos</a>)</td></tr>
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<tr class="separator:ga3e8ec8a0faf4bc51e04f909e3b13708e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd0ec0e64e354c9670015c91aaf54c2e" id="r_gacd0ec0e64e354c9670015c91aaf54c2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd0ec0e64e354c9670015c91aaf54c2e">TIM_OR_TI1_RMP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e8ec8a0faf4bc51e04f909e3b13708e">TIM_OR_TI1_RMP_Msk</a></td></tr>
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<tr class="separator:gacd0ec0e64e354c9670015c91aaf54c2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59fa1246d851959d5231b5b0796fd3a5" id="r_ga59fa1246d851959d5231b5b0796fd3a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59fa1246d851959d5231b5b0796fd3a5">TIM_OR_TI1_RMP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f62ec5e16705319b0d7ecdc54471788">TIM_OR_TI1_RMP_Pos</a>)</td></tr>
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<tr class="separator:ga59fa1246d851959d5231b5b0796fd3a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98d9cdc55111a548e48df0819922852b" id="r_ga98d9cdc55111a548e48df0819922852b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98d9cdc55111a548e48df0819922852b">TIM_OR_TI1_RMP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f62ec5e16705319b0d7ecdc54471788">TIM_OR_TI1_RMP_Pos</a>)</td></tr>
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<tr class="separator:ga98d9cdc55111a548e48df0819922852b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaecd8b0b125d46d02c35f990903d6fcb" id="r_gaaecd8b0b125d46d02c35f990903d6fcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaecd8b0b125d46d02c35f990903d6fcb">TIM_OR_TI4_RMP_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaaecd8b0b125d46d02c35f990903d6fcb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef046d565911337566adcc67904847ea" id="r_gaef046d565911337566adcc67904847ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef046d565911337566adcc67904847ea">TIM_OR_TI4_RMP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaecd8b0b125d46d02c35f990903d6fcb">TIM_OR_TI4_RMP_Pos</a>)</td></tr>
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<tr class="separator:gaef046d565911337566adcc67904847ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2916847c3545c06578d7ba8c381a4c20" id="r_ga2916847c3545c06578d7ba8c381a4c20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2916847c3545c06578d7ba8c381a4c20">TIM_OR_TI4_RMP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaef046d565911337566adcc67904847ea">TIM_OR_TI4_RMP_Msk</a></td></tr>
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<tr class="separator:ga2916847c3545c06578d7ba8c381a4c20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9aea4f8a0abedbf08bb1e686933c1120" id="r_ga9aea4f8a0abedbf08bb1e686933c1120"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9aea4f8a0abedbf08bb1e686933c1120">TIM_OR_TI4_RMP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaecd8b0b125d46d02c35f990903d6fcb">TIM_OR_TI4_RMP_Pos</a>)</td></tr>
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<tr class="separator:ga9aea4f8a0abedbf08bb1e686933c1120"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2a46aa18f15f2074b93233a18e85629" id="r_gaa2a46aa18f15f2074b93233a18e85629"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a46aa18f15f2074b93233a18e85629">TIM_OR_TI4_RMP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaecd8b0b125d46d02c35f990903d6fcb">TIM_OR_TI4_RMP_Pos</a>)</td></tr>
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<tr class="separator:gaa2a46aa18f15f2074b93233a18e85629"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50c5d626671e911a5d0943e6477e4aa7" id="r_ga50c5d626671e911a5d0943e6477e4aa7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50c5d626671e911a5d0943e6477e4aa7">TIM_OR_ITR1_RMP_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga50c5d626671e911a5d0943e6477e4aa7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8bc0672804e61da192e6063e0bb82ed3" id="r_ga8bc0672804e61da192e6063e0bb82ed3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8bc0672804e61da192e6063e0bb82ed3">TIM_OR_ITR1_RMP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga50c5d626671e911a5d0943e6477e4aa7">TIM_OR_ITR1_RMP_Pos</a>)</td></tr>
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<tr class="separator:ga8bc0672804e61da192e6063e0bb82ed3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f413eac7f503dfddc9a9914efa555ac" id="r_ga4f413eac7f503dfddc9a9914efa555ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f413eac7f503dfddc9a9914efa555ac">TIM_OR_ITR1_RMP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8bc0672804e61da192e6063e0bb82ed3">TIM_OR_ITR1_RMP_Msk</a></td></tr>
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<tr class="separator:ga4f413eac7f503dfddc9a9914efa555ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7141f22c81a83134d9bb35cdeca5549" id="r_gad7141f22c81a83134d9bb35cdeca5549"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7141f22c81a83134d9bb35cdeca5549">TIM_OR_ITR1_RMP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga50c5d626671e911a5d0943e6477e4aa7">TIM_OR_ITR1_RMP_Pos</a>)</td></tr>
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<tr class="separator:gad7141f22c81a83134d9bb35cdeca5549"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ba54d02d962d04d2bdf16df11c7ccd0" id="r_ga7ba54d02d962d04d2bdf16df11c7ccd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ba54d02d962d04d2bdf16df11c7ccd0">TIM_OR_ITR1_RMP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga50c5d626671e911a5d0943e6477e4aa7">TIM_OR_ITR1_RMP_Pos</a>)</td></tr>
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<tr class="separator:ga7ba54d02d962d04d2bdf16df11c7ccd0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0635e2ab8eac81f2a10164602121ccf2" id="r_ga0635e2ab8eac81f2a10164602121ccf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0635e2ab8eac81f2a10164602121ccf2">USART_SR_PE_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0635e2ab8eac81f2a10164602121ccf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83b7f81b87e70796a8cffaae0eb9ba9a" id="r_ga83b7f81b87e70796a8cffaae0eb9ba9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83b7f81b87e70796a8cffaae0eb9ba9a">USART_SR_PE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0635e2ab8eac81f2a10164602121ccf2">USART_SR_PE_Pos</a>)</td></tr>
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<tr class="separator:ga83b7f81b87e70796a8cffaae0eb9ba9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac88be3484245af8c1b271ae5c1b97a14" id="r_gac88be3484245af8c1b271ae5c1b97a14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac88be3484245af8c1b271ae5c1b97a14">USART_SR_PE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga83b7f81b87e70796a8cffaae0eb9ba9a">USART_SR_PE_Msk</a></td></tr>
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<tr class="separator:gac88be3484245af8c1b271ae5c1b97a14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga780d79584f83d2873c4026cdaa93d848" id="r_ga780d79584f83d2873c4026cdaa93d848"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga780d79584f83d2873c4026cdaa93d848">USART_SR_FE_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga780d79584f83d2873c4026cdaa93d848"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3050686c973903a8821196e0a7166f3" id="r_gad3050686c973903a8821196e0a7166f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3050686c973903a8821196e0a7166f3">USART_SR_FE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga780d79584f83d2873c4026cdaa93d848">USART_SR_FE_Pos</a>)</td></tr>
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<tr class="separator:gad3050686c973903a8821196e0a7166f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9eb6fd3f820bd12e0b5a981de1894804" id="r_ga9eb6fd3f820bd12e0b5a981de1894804"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9eb6fd3f820bd12e0b5a981de1894804">USART_SR_FE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad3050686c973903a8821196e0a7166f3">USART_SR_FE_Msk</a></td></tr>
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<tr class="separator:ga9eb6fd3f820bd12e0b5a981de1894804"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92528c798c4fa8ecfda09d6058cbb7f3" id="r_ga92528c798c4fa8ecfda09d6058cbb7f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92528c798c4fa8ecfda09d6058cbb7f3">USART_SR_NE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga92528c798c4fa8ecfda09d6058cbb7f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4150c4eff1939e0c1c474dce82ed76bf" id="r_ga4150c4eff1939e0c1c474dce82ed76bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4150c4eff1939e0c1c474dce82ed76bf">USART_SR_NE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92528c798c4fa8ecfda09d6058cbb7f3">USART_SR_NE_Pos</a>)</td></tr>
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<tr class="separator:ga4150c4eff1939e0c1c474dce82ed76bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8938468c5666a8305ade6d80d467c572" id="r_ga8938468c5666a8305ade6d80d467c572"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8938468c5666a8305ade6d80d467c572">USART_SR_NE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4150c4eff1939e0c1c474dce82ed76bf">USART_SR_NE_Msk</a></td></tr>
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<tr class="separator:ga8938468c5666a8305ade6d80d467c572"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1413d933bfe380829bd883ce5ae6f27b" id="r_ga1413d933bfe380829bd883ce5ae6f27b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1413d933bfe380829bd883ce5ae6f27b">USART_SR_ORE_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga1413d933bfe380829bd883ce5ae6f27b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga654b0cd0fb1fdf02de8f1af223eca9d5" id="r_ga654b0cd0fb1fdf02de8f1af223eca9d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga654b0cd0fb1fdf02de8f1af223eca9d5">USART_SR_ORE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1413d933bfe380829bd883ce5ae6f27b">USART_SR_ORE_Pos</a>)</td></tr>
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<tr class="separator:ga654b0cd0fb1fdf02de8f1af223eca9d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4560fc7a60df4bdf402fc7219ae7b558" id="r_ga4560fc7a60df4bdf402fc7219ae7b558"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4560fc7a60df4bdf402fc7219ae7b558">USART_SR_ORE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga654b0cd0fb1fdf02de8f1af223eca9d5">USART_SR_ORE_Msk</a></td></tr>
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<tr class="separator:ga4560fc7a60df4bdf402fc7219ae7b558"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2a7cf252454c0c27e5d4327bbd3206f" id="r_gae2a7cf252454c0c27e5d4327bbd3206f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2a7cf252454c0c27e5d4327bbd3206f">USART_SR_IDLE_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae2a7cf252454c0c27e5d4327bbd3206f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2b2420f9c84d2adbb47dce8d0e65497" id="r_gae2b2420f9c84d2adbb47dce8d0e65497"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2b2420f9c84d2adbb47dce8d0e65497">USART_SR_IDLE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae2a7cf252454c0c27e5d4327bbd3206f">USART_SR_IDLE_Pos</a>)</td></tr>
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<tr class="separator:gae2b2420f9c84d2adbb47dce8d0e65497"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga336fa8c9965ce18c10972ac80ded611f" id="r_ga336fa8c9965ce18c10972ac80ded611f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga336fa8c9965ce18c10972ac80ded611f">USART_SR_IDLE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae2b2420f9c84d2adbb47dce8d0e65497">USART_SR_IDLE_Msk</a></td></tr>
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<tr class="separator:ga336fa8c9965ce18c10972ac80ded611f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5895ff1c2d076cb10c291c873eedc55" id="r_gaf5895ff1c2d076cb10c291c873eedc55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5895ff1c2d076cb10c291c873eedc55">USART_SR_RXNE_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaf5895ff1c2d076cb10c291c873eedc55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64611f0aa4ba3dcafb6d934e831279e9" id="r_ga64611f0aa4ba3dcafb6d934e831279e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64611f0aa4ba3dcafb6d934e831279e9">USART_SR_RXNE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5895ff1c2d076cb10c291c873eedc55">USART_SR_RXNE_Pos</a>)</td></tr>
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<tr class="separator:ga64611f0aa4ba3dcafb6d934e831279e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0c99e2bb265b3d58a91aca7a93f7836" id="r_gaa0c99e2bb265b3d58a91aca7a93f7836"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0c99e2bb265b3d58a91aca7a93f7836">USART_SR_RXNE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64611f0aa4ba3dcafb6d934e831279e9">USART_SR_RXNE_Msk</a></td></tr>
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<tr class="memitem:gac8cdb6c85343e4287d5c07bcff25d58e" id="r_gac8cdb6c85343e4287d5c07bcff25d58e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8cdb6c85343e4287d5c07bcff25d58e">USART_SR_TC_Pos</a>   (6U)</td></tr>
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<tr class="separator:gac8cdb6c85343e4287d5c07bcff25d58e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga972584d838f708691ef3c153ad8233ac" id="r_ga972584d838f708691ef3c153ad8233ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga972584d838f708691ef3c153ad8233ac">USART_SR_TC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8cdb6c85343e4287d5c07bcff25d58e">USART_SR_TC_Pos</a>)</td></tr>
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<tr class="separator:ga972584d838f708691ef3c153ad8233ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76229b05ac37a5a688e6ba45851a29f1" id="r_ga76229b05ac37a5a688e6ba45851a29f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76229b05ac37a5a688e6ba45851a29f1">USART_SR_TC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga972584d838f708691ef3c153ad8233ac">USART_SR_TC_Msk</a></td></tr>
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<tr class="separator:ga76229b05ac37a5a688e6ba45851a29f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa708cd1b36e1ee1cfed89e85620a7c00" id="r_gaa708cd1b36e1ee1cfed89e85620a7c00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa708cd1b36e1ee1cfed89e85620a7c00">USART_SR_TXE_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaa708cd1b36e1ee1cfed89e85620a7c00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe75a9021a84919f6c1ea3e3c08a23e0" id="r_gabe75a9021a84919f6c1ea3e3c08a23e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe75a9021a84919f6c1ea3e3c08a23e0">USART_SR_TXE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa708cd1b36e1ee1cfed89e85620a7c00">USART_SR_TXE_Pos</a>)</td></tr>
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<tr class="separator:gabe75a9021a84919f6c1ea3e3c08a23e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65e9cddf0890113d405342f1d8b5b980" id="r_ga65e9cddf0890113d405342f1d8b5b980"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65e9cddf0890113d405342f1d8b5b980">USART_SR_TXE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabe75a9021a84919f6c1ea3e3c08a23e0">USART_SR_TXE_Msk</a></td></tr>
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<tr class="separator:ga65e9cddf0890113d405342f1d8b5b980"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae347aead943d5b4c1044a226380b3fda" id="r_gae347aead943d5b4c1044a226380b3fda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae347aead943d5b4c1044a226380b3fda">USART_SR_LBD_Pos</a>   (8U)</td></tr>
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<tr class="separator:gae347aead943d5b4c1044a226380b3fda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga233a2963e3a24a14f98865224183d93d" id="r_ga233a2963e3a24a14f98865224183d93d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga233a2963e3a24a14f98865224183d93d">USART_SR_LBD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae347aead943d5b4c1044a226380b3fda">USART_SR_LBD_Pos</a>)</td></tr>
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<tr class="separator:ga233a2963e3a24a14f98865224183d93d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b868b59576f42421226d35628c6b628" id="r_ga5b868b59576f42421226d35628c6b628"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b868b59576f42421226d35628c6b628">USART_SR_LBD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga233a2963e3a24a14f98865224183d93d">USART_SR_LBD_Msk</a></td></tr>
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<tr class="separator:ga5b868b59576f42421226d35628c6b628"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d2b04e34749fc2ef806327e991dcad8" id="r_ga8d2b04e34749fc2ef806327e991dcad8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d2b04e34749fc2ef806327e991dcad8">USART_SR_CTS_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga8d2b04e34749fc2ef806327e991dcad8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d241b440c4595aac4bdf1ffee9c22f9" id="r_ga4d241b440c4595aac4bdf1ffee9c22f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d241b440c4595aac4bdf1ffee9c22f9">USART_SR_CTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d2b04e34749fc2ef806327e991dcad8">USART_SR_CTS_Pos</a>)</td></tr>
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<tr class="separator:ga4d241b440c4595aac4bdf1ffee9c22f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9250ae2793db0541e6c4bb8837424541" id="r_ga9250ae2793db0541e6c4bb8837424541"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9250ae2793db0541e6c4bb8837424541">USART_SR_CTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d241b440c4595aac4bdf1ffee9c22f9">USART_SR_CTS_Msk</a></td></tr>
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<tr class="separator:ga9250ae2793db0541e6c4bb8837424541"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1d7d8f36a92c78b93ab1a3e4011b771" id="r_gab1d7d8f36a92c78b93ab1a3e4011b771"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1d7d8f36a92c78b93ab1a3e4011b771">USART_DR_DR_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab1d7d8f36a92c78b93ab1a3e4011b771"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga911912bd628fd1fc33a1d8819d27e81f" id="r_ga911912bd628fd1fc33a1d8819d27e81f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga911912bd628fd1fc33a1d8819d27e81f">USART_DR_DR_Msk</a>   (0x1FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab1d7d8f36a92c78b93ab1a3e4011b771">USART_DR_DR_Pos</a>)</td></tr>
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<tr class="separator:ga911912bd628fd1fc33a1d8819d27e81f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad84ad1e1d0202b41021e2d6e40486bff" id="r_gad84ad1e1d0202b41021e2d6e40486bff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad84ad1e1d0202b41021e2d6e40486bff">USART_DR_DR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga911912bd628fd1fc33a1d8819d27e81f">USART_DR_DR_Msk</a></td></tr>
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<tr class="separator:gad84ad1e1d0202b41021e2d6e40486bff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4c70e9b7c797d9a6e1e7a4e4e645ef1" id="r_gaa4c70e9b7c797d9a6e1e7a4e4e645ef1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4c70e9b7c797d9a6e1e7a4e4e645ef1">USART_BRR_DIV_Fraction_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa4c70e9b7c797d9a6e1e7a4e4e645ef1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cc35155a1120da23f3fc72cb26b4aea" id="r_ga1cc35155a1120da23f3fc72cb26b4aea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc35155a1120da23f3fc72cb26b4aea">USART_BRR_DIV_Fraction_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4c70e9b7c797d9a6e1e7a4e4e645ef1">USART_BRR_DIV_Fraction_Pos</a>)</td></tr>
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<tr class="separator:ga1cc35155a1120da23f3fc72cb26b4aea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9dfae31be4ec2c8a3b0905eff30c7046" id="r_ga9dfae31be4ec2c8a3b0905eff30c7046"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9dfae31be4ec2c8a3b0905eff30c7046">USART_BRR_DIV_Fraction</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc35155a1120da23f3fc72cb26b4aea">USART_BRR_DIV_Fraction_Msk</a></td></tr>
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<tr class="separator:ga9dfae31be4ec2c8a3b0905eff30c7046"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21895f823b1422a7af307b0656560058" id="r_ga21895f823b1422a7af307b0656560058"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21895f823b1422a7af307b0656560058">USART_BRR_DIV_Mantissa_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga21895f823b1422a7af307b0656560058"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace4259fb84cf5a9096ad62cd2453d28e" id="r_gace4259fb84cf5a9096ad62cd2453d28e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace4259fb84cf5a9096ad62cd2453d28e">USART_BRR_DIV_Mantissa_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21895f823b1422a7af307b0656560058">USART_BRR_DIV_Mantissa_Pos</a>)</td></tr>
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<tr class="separator:gace4259fb84cf5a9096ad62cd2453d28e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60cfa3802798306b86231f828ed2e71e" id="r_ga60cfa3802798306b86231f828ed2e71e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60cfa3802798306b86231f828ed2e71e">USART_BRR_DIV_Mantissa</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gace4259fb84cf5a9096ad62cd2453d28e">USART_BRR_DIV_Mantissa_Msk</a></td></tr>
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<tr class="separator:ga60cfa3802798306b86231f828ed2e71e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23eec4bbb3ac06c22aff3355f965457a" id="r_ga23eec4bbb3ac06c22aff3355f965457a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23eec4bbb3ac06c22aff3355f965457a">USART_CR1_SBK_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga23eec4bbb3ac06c22aff3355f965457a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f06150e7efb4ee5858a0863c0af36e1" id="r_ga4f06150e7efb4ee5858a0863c0af36e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f06150e7efb4ee5858a0863c0af36e1">USART_CR1_SBK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga23eec4bbb3ac06c22aff3355f965457a">USART_CR1_SBK_Pos</a>)</td></tr>
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<tr class="separator:ga4f06150e7efb4ee5858a0863c0af36e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac457c519baa28359ab7959fbe0c5cda1" id="r_gac457c519baa28359ab7959fbe0c5cda1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac457c519baa28359ab7959fbe0c5cda1">USART_CR1_SBK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f06150e7efb4ee5858a0863c0af36e1">USART_CR1_SBK_Msk</a></td></tr>
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<tr class="separator:gac457c519baa28359ab7959fbe0c5cda1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64a90f545fa1ee315c277fd0f06f2274" id="r_ga64a90f545fa1ee315c277fd0f06f2274"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64a90f545fa1ee315c277fd0f06f2274">USART_CR1_RWU_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga64a90f545fa1ee315c277fd0f06f2274"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e0cafa55c289e39145287325f9d7cf4" id="r_ga8e0cafa55c289e39145287325f9d7cf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e0cafa55c289e39145287325f9d7cf4">USART_CR1_RWU_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga64a90f545fa1ee315c277fd0f06f2274">USART_CR1_RWU_Pos</a>)</td></tr>
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<tr class="separator:ga8e0cafa55c289e39145287325f9d7cf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7d61ab5a4e2beaa3f591c56bd15a27b" id="r_gaa7d61ab5a4e2beaa3f591c56bd15a27b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7d61ab5a4e2beaa3f591c56bd15a27b">USART_CR1_RWU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e0cafa55c289e39145287325f9d7cf4">USART_CR1_RWU_Msk</a></td></tr>
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<tr class="separator:gaa7d61ab5a4e2beaa3f591c56bd15a27b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga678b98c07ad61dec17131716d1ddfa58" id="r_ga678b98c07ad61dec17131716d1ddfa58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga678b98c07ad61dec17131716d1ddfa58">USART_CR1_RE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga678b98c07ad61dec17131716d1ddfa58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga625927bbfd40ce911de7183cae92e682" id="r_ga625927bbfd40ce911de7183cae92e682"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga625927bbfd40ce911de7183cae92e682">USART_CR1_RE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga678b98c07ad61dec17131716d1ddfa58">USART_CR1_RE_Pos</a>)</td></tr>
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<tr class="separator:ga625927bbfd40ce911de7183cae92e682"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada0d5d407a22264de847bc1b40a17aeb" id="r_gada0d5d407a22264de847bc1b40a17aeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada0d5d407a22264de847bc1b40a17aeb">USART_CR1_RE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga625927bbfd40ce911de7183cae92e682">USART_CR1_RE_Msk</a></td></tr>
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<tr class="separator:gada0d5d407a22264de847bc1b40a17aeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53df187761bfed354686b47e0a691564" id="r_ga53df187761bfed354686b47e0a691564"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53df187761bfed354686b47e0a691564">USART_CR1_TE_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga53df187761bfed354686b47e0a691564"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c5e02008c2fde7c5f0070d94ee77bce" id="r_ga0c5e02008c2fde7c5f0070d94ee77bce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c5e02008c2fde7c5f0070d94ee77bce">USART_CR1_TE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga53df187761bfed354686b47e0a691564">USART_CR1_TE_Pos</a>)</td></tr>
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<tr class="separator:ga0c5e02008c2fde7c5f0070d94ee77bce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade7f090b04fd78b755b43357ecaa9622" id="r_gade7f090b04fd78b755b43357ecaa9622"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade7f090b04fd78b755b43357ecaa9622">USART_CR1_TE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c5e02008c2fde7c5f0070d94ee77bce">USART_CR1_TE_Msk</a></td></tr>
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<tr class="memitem:ga5ba3e0fc695108b77498a9fdbacc95d3" id="r_ga5ba3e0fc695108b77498a9fdbacc95d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ba3e0fc695108b77498a9fdbacc95d3">USART_CR1_IDLEIE_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga5ba3e0fc695108b77498a9fdbacc95d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ad37a38ae2c8a059a922f5b33c5c2aa" id="r_ga8ad37a38ae2c8a059a922f5b33c5c2aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ad37a38ae2c8a059a922f5b33c5c2aa">USART_CR1_IDLEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ba3e0fc695108b77498a9fdbacc95d3">USART_CR1_IDLEIE_Pos</a>)</td></tr>
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<tr class="separator:ga8ad37a38ae2c8a059a922f5b33c5c2aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5221d09eebd12445a20f221bf98066f8" id="r_ga5221d09eebd12445a20f221bf98066f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5221d09eebd12445a20f221bf98066f8">USART_CR1_IDLEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ad37a38ae2c8a059a922f5b33c5c2aa">USART_CR1_IDLEIE_Msk</a></td></tr>
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<tr class="separator:ga5221d09eebd12445a20f221bf98066f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2232ea76bad178a6e945fe573c2dc984" id="r_ga2232ea76bad178a6e945fe573c2dc984"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2232ea76bad178a6e945fe573c2dc984">USART_CR1_RXNEIE_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga2232ea76bad178a6e945fe573c2dc984"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2e4ba1ab97599cbf7f182d2cfc80543" id="r_gac2e4ba1ab97599cbf7f182d2cfc80543"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2e4ba1ab97599cbf7f182d2cfc80543">USART_CR1_RXNEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2232ea76bad178a6e945fe573c2dc984">USART_CR1_RXNEIE_Pos</a>)</td></tr>
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<tr class="separator:gac2e4ba1ab97599cbf7f182d2cfc80543"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91118f867adfdb2e805beea86666de04" id="r_ga91118f867adfdb2e805beea86666de04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91118f867adfdb2e805beea86666de04">USART_CR1_RXNEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac2e4ba1ab97599cbf7f182d2cfc80543">USART_CR1_RXNEIE_Msk</a></td></tr>
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<tr class="separator:ga91118f867adfdb2e805beea86666de04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ee92ad658865410023fc8508325024a" id="r_ga3ee92ad658865410023fc8508325024a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ee92ad658865410023fc8508325024a">USART_CR1_TCIE_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga3ee92ad658865410023fc8508325024a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3ff7666f8e81e2cf6d40bebaf0a84b7" id="r_gad3ff7666f8e81e2cf6d40bebaf0a84b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3ff7666f8e81e2cf6d40bebaf0a84b7">USART_CR1_TCIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ee92ad658865410023fc8508325024a">USART_CR1_TCIE_Pos</a>)</td></tr>
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<tr class="separator:gad3ff7666f8e81e2cf6d40bebaf0a84b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa17130690a1ca95b972429eb64d4254e" id="r_gaa17130690a1ca95b972429eb64d4254e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa17130690a1ca95b972429eb64d4254e">USART_CR1_TCIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad3ff7666f8e81e2cf6d40bebaf0a84b7">USART_CR1_TCIE_Msk</a></td></tr>
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<tr class="separator:gaa17130690a1ca95b972429eb64d4254e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6931210415f36d727f75bfc856aed9ef" id="r_ga6931210415f36d727f75bfc856aed9ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6931210415f36d727f75bfc856aed9ef">USART_CR1_TXEIE_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga6931210415f36d727f75bfc856aed9ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65436dd25155a36250ee090dd940caa5" id="r_ga65436dd25155a36250ee090dd940caa5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65436dd25155a36250ee090dd940caa5">USART_CR1_TXEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6931210415f36d727f75bfc856aed9ef">USART_CR1_TXEIE_Pos</a>)</td></tr>
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<tr class="separator:ga65436dd25155a36250ee090dd940caa5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70422871d15f974b464365e7fe1877e9" id="r_ga70422871d15f974b464365e7fe1877e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70422871d15f974b464365e7fe1877e9">USART_CR1_TXEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65436dd25155a36250ee090dd940caa5">USART_CR1_TXEIE_Msk</a></td></tr>
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<tr class="separator:ga70422871d15f974b464365e7fe1877e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46a693e8924defd8e57b0b08323afa0b" id="r_ga46a693e8924defd8e57b0b08323afa0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46a693e8924defd8e57b0b08323afa0b">USART_CR1_PEIE_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga46a693e8924defd8e57b0b08323afa0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad99fb4719a46d6d1d423d7ffe7ce06e1" id="r_gad99fb4719a46d6d1d423d7ffe7ce06e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad99fb4719a46d6d1d423d7ffe7ce06e1">USART_CR1_PEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46a693e8924defd8e57b0b08323afa0b">USART_CR1_PEIE_Pos</a>)</td></tr>
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<tr class="separator:gad99fb4719a46d6d1d423d7ffe7ce06e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27405d413b6d355ccdb076d52fef6875" id="r_ga27405d413b6d355ccdb076d52fef6875"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27405d413b6d355ccdb076d52fef6875">USART_CR1_PEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad99fb4719a46d6d1d423d7ffe7ce06e1">USART_CR1_PEIE_Msk</a></td></tr>
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<tr class="separator:ga27405d413b6d355ccdb076d52fef6875"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2e65e62ab989658fec2bdaad7892c16" id="r_gaf2e65e62ab989658fec2bdaad7892c16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2e65e62ab989658fec2bdaad7892c16">USART_CR1_PS_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaf2e65e62ab989658fec2bdaad7892c16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08638afebc30caad3337f1faac6d904e" id="r_ga08638afebc30caad3337f1faac6d904e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08638afebc30caad3337f1faac6d904e">USART_CR1_PS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2e65e62ab989658fec2bdaad7892c16">USART_CR1_PS_Pos</a>)</td></tr>
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<tr class="separator:ga08638afebc30caad3337f1faac6d904e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e159d36ab2c93a2c1942df60e9eebbe" id="r_ga2e159d36ab2c93a2c1942df60e9eebbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e159d36ab2c93a2c1942df60e9eebbe">USART_CR1_PS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga08638afebc30caad3337f1faac6d904e">USART_CR1_PS_Msk</a></td></tr>
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<tr class="separator:ga2e159d36ab2c93a2c1942df60e9eebbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1029c679b6ce540fc8343e074387fa5b" id="r_ga1029c679b6ce540fc8343e074387fa5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1029c679b6ce540fc8343e074387fa5b">USART_CR1_PCE_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga1029c679b6ce540fc8343e074387fa5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60894c2937928b5ca83fe73e60e1c9c1" id="r_ga60894c2937928b5ca83fe73e60e1c9c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60894c2937928b5ca83fe73e60e1c9c1">USART_CR1_PCE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1029c679b6ce540fc8343e074387fa5b">USART_CR1_PCE_Pos</a>)</td></tr>
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<tr class="separator:ga60894c2937928b5ca83fe73e60e1c9c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60f8fcf084f9a8514efafb617c70b074" id="r_ga60f8fcf084f9a8514efafb617c70b074"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60f8fcf084f9a8514efafb617c70b074">USART_CR1_PCE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga60894c2937928b5ca83fe73e60e1c9c1">USART_CR1_PCE_Msk</a></td></tr>
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<tr class="separator:ga60f8fcf084f9a8514efafb617c70b074"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86cc2060fef5dc3ce6820e31f0156492" id="r_ga86cc2060fef5dc3ce6820e31f0156492"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86cc2060fef5dc3ce6820e31f0156492">USART_CR1_WAKE_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga86cc2060fef5dc3ce6820e31f0156492"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0bc41f3a11fced743f19684211eacd6" id="r_gab0bc41f3a11fced743f19684211eacd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0bc41f3a11fced743f19684211eacd6">USART_CR1_WAKE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga86cc2060fef5dc3ce6820e31f0156492">USART_CR1_WAKE_Pos</a>)</td></tr>
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<tr class="separator:gab0bc41f3a11fced743f19684211eacd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad831dfc169fcf14b7284984dbecf322d" id="r_gad831dfc169fcf14b7284984dbecf322d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad831dfc169fcf14b7284984dbecf322d">USART_CR1_WAKE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab0bc41f3a11fced743f19684211eacd6">USART_CR1_WAKE_Msk</a></td></tr>
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<tr class="separator:gad831dfc169fcf14b7284984dbecf322d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b16c1bf94dba8a889397c5933322308" id="r_ga8b16c1bf94dba8a889397c5933322308"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b16c1bf94dba8a889397c5933322308">USART_CR1_M_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga8b16c1bf94dba8a889397c5933322308"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b5f5bc798207f9cc9e54ab080637634" id="r_ga3b5f5bc798207f9cc9e54ab080637634"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b5f5bc798207f9cc9e54ab080637634">USART_CR1_M_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b16c1bf94dba8a889397c5933322308">USART_CR1_M_Pos</a>)</td></tr>
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<tr class="separator:ga3b5f5bc798207f9cc9e54ab080637634"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95f0288b9c6aaeca7cb6550a2e6833e2" id="r_ga95f0288b9c6aaeca7cb6550a2e6833e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95f0288b9c6aaeca7cb6550a2e6833e2">USART_CR1_M</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b5f5bc798207f9cc9e54ab080637634">USART_CR1_M_Msk</a></td></tr>
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<tr class="separator:ga95f0288b9c6aaeca7cb6550a2e6833e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64f40c78bbc597ada96c2ec828722eeb" id="r_ga64f40c78bbc597ada96c2ec828722eeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64f40c78bbc597ada96c2ec828722eeb">USART_CR1_UE_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga64f40c78bbc597ada96c2ec828722eeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8b32c050e6d9482a819e0107ceb9f83" id="r_gab8b32c050e6d9482a819e0107ceb9f83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8b32c050e6d9482a819e0107ceb9f83">USART_CR1_UE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga64f40c78bbc597ada96c2ec828722eeb">USART_CR1_UE_Pos</a>)</td></tr>
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<tr class="separator:gab8b32c050e6d9482a819e0107ceb9f83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bb650676aaae4a5203f372d497d5947" id="r_ga2bb650676aaae4a5203f372d497d5947"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bb650676aaae4a5203f372d497d5947">USART_CR1_UE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab8b32c050e6d9482a819e0107ceb9f83">USART_CR1_UE_Msk</a></td></tr>
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<tr class="separator:ga2bb650676aaae4a5203f372d497d5947"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f51c380de00d417c76712183070ff01" id="r_ga7f51c380de00d417c76712183070ff01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f51c380de00d417c76712183070ff01">USART_CR1_OVER8_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga7f51c380de00d417c76712183070ff01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac009e53008167c20955efe87a147ea02" id="r_gac009e53008167c20955efe87a147ea02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac009e53008167c20955efe87a147ea02">USART_CR1_OVER8_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f51c380de00d417c76712183070ff01">USART_CR1_OVER8_Pos</a>)</td></tr>
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<tr class="separator:gac009e53008167c20955efe87a147ea02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed6caeb0cb48f1a7b34090f31a92a8e2" id="r_gaed6caeb0cb48f1a7b34090f31a92a8e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed6caeb0cb48f1a7b34090f31a92a8e2">USART_CR1_OVER8</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac009e53008167c20955efe87a147ea02">USART_CR1_OVER8_Msk</a></td></tr>
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<tr class="separator:gaed6caeb0cb48f1a7b34090f31a92a8e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d1320f17e2f61e21a867e538c737ac3" id="r_ga2d1320f17e2f61e21a867e538c737ac3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d1320f17e2f61e21a867e538c737ac3">USART_CR2_ADD_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2d1320f17e2f61e21a867e538c737ac3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7ee87cc9cdc865b0f5a61af0c26ec28" id="r_gad7ee87cc9cdc865b0f5a61af0c26ec28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7ee87cc9cdc865b0f5a61af0c26ec28">USART_CR2_ADD_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d1320f17e2f61e21a867e538c737ac3">USART_CR2_ADD_Pos</a>)</td></tr>
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<tr class="separator:gad7ee87cc9cdc865b0f5a61af0c26ec28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ee77fac25142271ad56d49685e518b3" id="r_ga3ee77fac25142271ad56d49685e518b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ee77fac25142271ad56d49685e518b3">USART_CR2_ADD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad7ee87cc9cdc865b0f5a61af0c26ec28">USART_CR2_ADD_Msk</a></td></tr>
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<tr class="separator:ga3ee77fac25142271ad56d49685e518b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf0b33cd8b6a3eb4a21bb6c34922a624" id="r_gadf0b33cd8b6a3eb4a21bb6c34922a624"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf0b33cd8b6a3eb4a21bb6c34922a624">USART_CR2_LBDL_Pos</a>   (5U)</td></tr>
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<tr class="separator:gadf0b33cd8b6a3eb4a21bb6c34922a624"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8d54a2e633ef8dda121c9d5670a5de5" id="r_gad8d54a2e633ef8dda121c9d5670a5de5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8d54a2e633ef8dda121c9d5670a5de5">USART_CR2_LBDL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf0b33cd8b6a3eb4a21bb6c34922a624">USART_CR2_LBDL_Pos</a>)</td></tr>
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<tr class="separator:gad8d54a2e633ef8dda121c9d5670a5de5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f9bc41700717fd93548e0e95b6072ed" id="r_ga7f9bc41700717fd93548e0e95b6072ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f9bc41700717fd93548e0e95b6072ed">USART_CR2_LBDL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad8d54a2e633ef8dda121c9d5670a5de5">USART_CR2_LBDL_Msk</a></td></tr>
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<tr class="separator:ga7f9bc41700717fd93548e0e95b6072ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9af36362bd69d0008e46a7ea7633b0f" id="r_gae9af36362bd69d0008e46a7ea7633b0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9af36362bd69d0008e46a7ea7633b0f">USART_CR2_LBDIE_Pos</a>   (6U)</td></tr>
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<tr class="separator:gae9af36362bd69d0008e46a7ea7633b0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad55383a0b8d928fd50c18c62faf44a7b" id="r_gad55383a0b8d928fd50c18c62faf44a7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad55383a0b8d928fd50c18c62faf44a7b">USART_CR2_LBDIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9af36362bd69d0008e46a7ea7633b0f">USART_CR2_LBDIE_Pos</a>)</td></tr>
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<tr class="separator:gad55383a0b8d928fd50c18c62faf44a7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa02ef5d22553f028ea48e5d9f08192b4" id="r_gaa02ef5d22553f028ea48e5d9f08192b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa02ef5d22553f028ea48e5d9f08192b4">USART_CR2_LBDIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad55383a0b8d928fd50c18c62faf44a7b">USART_CR2_LBDIE_Msk</a></td></tr>
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<tr class="separator:gaa02ef5d22553f028ea48e5d9f08192b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0262849ac25bc43d23d46945c85851b0" id="r_ga0262849ac25bc43d23d46945c85851b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0262849ac25bc43d23d46945c85851b0">USART_CR2_LBCL_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga0262849ac25bc43d23d46945c85851b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d515f33359c44365712bfbcf34c7e94" id="r_ga3d515f33359c44365712bfbcf34c7e94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d515f33359c44365712bfbcf34c7e94">USART_CR2_LBCL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0262849ac25bc43d23d46945c85851b0">USART_CR2_LBCL_Pos</a>)</td></tr>
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<tr class="separator:ga3d515f33359c44365712bfbcf34c7e94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a62e93ae7864e89622bdd92508b615e" id="r_ga4a62e93ae7864e89622bdd92508b615e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a62e93ae7864e89622bdd92508b615e">USART_CR2_LBCL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d515f33359c44365712bfbcf34c7e94">USART_CR2_LBCL_Msk</a></td></tr>
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<tr class="separator:ga4a62e93ae7864e89622bdd92508b615e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4188976dbf7f6455ba79d1afd830cf7a" id="r_ga4188976dbf7f6455ba79d1afd830cf7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4188976dbf7f6455ba79d1afd830cf7a">USART_CR2_CPHA_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga4188976dbf7f6455ba79d1afd830cf7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65c8198c5780edaa8ef67706d7d1ea34" id="r_ga65c8198c5780edaa8ef67706d7d1ea34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65c8198c5780edaa8ef67706d7d1ea34">USART_CR2_CPHA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4188976dbf7f6455ba79d1afd830cf7a">USART_CR2_CPHA_Pos</a>)</td></tr>
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<tr class="separator:ga65c8198c5780edaa8ef67706d7d1ea34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga362976ce813e58310399d113d2cf09cb" id="r_ga362976ce813e58310399d113d2cf09cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga362976ce813e58310399d113d2cf09cb">USART_CR2_CPHA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65c8198c5780edaa8ef67706d7d1ea34">USART_CR2_CPHA_Msk</a></td></tr>
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<tr class="separator:ga362976ce813e58310399d113d2cf09cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga110f164794e57c70b9d7b0b26577e86a" id="r_ga110f164794e57c70b9d7b0b26577e86a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga110f164794e57c70b9d7b0b26577e86a">USART_CR2_CPOL_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga110f164794e57c70b9d7b0b26577e86a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga182e2b837ab775c53868a37a1e4eb05a" id="r_ga182e2b837ab775c53868a37a1e4eb05a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga182e2b837ab775c53868a37a1e4eb05a">USART_CR2_CPOL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga110f164794e57c70b9d7b0b26577e86a">USART_CR2_CPOL_Pos</a>)</td></tr>
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<tr class="separator:ga182e2b837ab775c53868a37a1e4eb05a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbb4336ac93d94d4e78f9fb7b3a0dc68" id="r_gafbb4336ac93d94d4e78f9fb7b3a0dc68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbb4336ac93d94d4e78f9fb7b3a0dc68">USART_CR2_CPOL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga182e2b837ab775c53868a37a1e4eb05a">USART_CR2_CPOL_Msk</a></td></tr>
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<tr class="separator:gafbb4336ac93d94d4e78f9fb7b3a0dc68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff740ebbb84ac8db332d177cd6cc9235" id="r_gaff740ebbb84ac8db332d177cd6cc9235"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff740ebbb84ac8db332d177cd6cc9235">USART_CR2_CLKEN_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaff740ebbb84ac8db332d177cd6cc9235"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f6a20180f8b2ad531009b33ecec1ed2" id="r_ga2f6a20180f8b2ad531009b33ecec1ed2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f6a20180f8b2ad531009b33ecec1ed2">USART_CR2_CLKEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaff740ebbb84ac8db332d177cd6cc9235">USART_CR2_CLKEN_Pos</a>)</td></tr>
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<tr class="separator:ga2f6a20180f8b2ad531009b33ecec1ed2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42a396cde02ffa0c4d3fd9817b6af853" id="r_ga42a396cde02ffa0c4d3fd9817b6af853"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42a396cde02ffa0c4d3fd9817b6af853">USART_CR2_CLKEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f6a20180f8b2ad531009b33ecec1ed2">USART_CR2_CLKEN_Msk</a></td></tr>
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<tr class="separator:ga42a396cde02ffa0c4d3fd9817b6af853"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a46b8272a2fe5ae5e5ce7123db22d51" id="r_ga4a46b8272a2fe5ae5e5ce7123db22d51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a46b8272a2fe5ae5e5ce7123db22d51">USART_CR2_STOP_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga4a46b8272a2fe5ae5e5ce7123db22d51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf73b228efa85f04a6b9a42e01b7f916c" id="r_gaf73b228efa85f04a6b9a42e01b7f916c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf73b228efa85f04a6b9a42e01b7f916c">USART_CR2_STOP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a46b8272a2fe5ae5e5ce7123db22d51">USART_CR2_STOP_Pos</a>)</td></tr>
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<tr class="separator:gaf73b228efa85f04a6b9a42e01b7f916c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf993e483318ebcecffd18649de766dc6" id="r_gaf993e483318ebcecffd18649de766dc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf993e483318ebcecffd18649de766dc6">USART_CR2_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf73b228efa85f04a6b9a42e01b7f916c">USART_CR2_STOP_Msk</a></td></tr>
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<tr class="memitem:gaee6ee01c6e5325b378b2209ef20d0a61" id="r_gaee6ee01c6e5325b378b2209ef20d0a61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee6ee01c6e5325b378b2209ef20d0a61">USART_CR2_STOP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a46b8272a2fe5ae5e5ce7123db22d51">USART_CR2_STOP_Pos</a>)</td></tr>
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<tr class="separator:gaee6ee01c6e5325b378b2209ef20d0a61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b24d14f0e5d1c76c878b08aad44d02b" id="r_ga2b24d14f0e5d1c76c878b08aad44d02b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b24d14f0e5d1c76c878b08aad44d02b">USART_CR2_STOP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a46b8272a2fe5ae5e5ce7123db22d51">USART_CR2_STOP_Pos</a>)</td></tr>
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<tr class="memitem:ga4f06b1d9300507573ffbf99f9a6ee57f" id="r_ga4f06b1d9300507573ffbf99f9a6ee57f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f06b1d9300507573ffbf99f9a6ee57f">USART_CR2_LINEN_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga4f06b1d9300507573ffbf99f9a6ee57f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga500c59de0f57986002b962dc9bccfbe8" id="r_ga500c59de0f57986002b962dc9bccfbe8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga500c59de0f57986002b962dc9bccfbe8">USART_CR2_LINEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f06b1d9300507573ffbf99f9a6ee57f">USART_CR2_LINEN_Pos</a>)</td></tr>
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<tr class="separator:ga500c59de0f57986002b962dc9bccfbe8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8931efa62c29d92f5c0ec5a05f907ef" id="r_gac8931efa62c29d92f5c0ec5a05f907ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8931efa62c29d92f5c0ec5a05f907ef">USART_CR2_LINEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga500c59de0f57986002b962dc9bccfbe8">USART_CR2_LINEN_Msk</a></td></tr>
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<tr class="separator:gac8931efa62c29d92f5c0ec5a05f907ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafeb00f27cc04dab7e9bcca92d6e7ad9e" id="r_gafeb00f27cc04dab7e9bcca92d6e7ad9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafeb00f27cc04dab7e9bcca92d6e7ad9e">USART_CR3_EIE_Pos</a>   (0U)</td></tr>
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<tr class="separator:gafeb00f27cc04dab7e9bcca92d6e7ad9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac0414669386ae8dd26b993ddf96d7b0" id="r_gaac0414669386ae8dd26b993ddf96d7b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac0414669386ae8dd26b993ddf96d7b0">USART_CR3_EIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafeb00f27cc04dab7e9bcca92d6e7ad9e">USART_CR3_EIE_Pos</a>)</td></tr>
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<tr class="separator:gaac0414669386ae8dd26b993ddf96d7b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaed1a39c551b1641128f81893ff558d0" id="r_gaaed1a39c551b1641128f81893ff558d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaed1a39c551b1641128f81893ff558d0">USART_CR3_EIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac0414669386ae8dd26b993ddf96d7b0">USART_CR3_EIE_Msk</a></td></tr>
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<tr class="memitem:ga22ce6319d8acdb4a57215aeb933c7a57" id="r_ga22ce6319d8acdb4a57215aeb933c7a57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22ce6319d8acdb4a57215aeb933c7a57">USART_CR3_IREN_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga22ce6319d8acdb4a57215aeb933c7a57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3c0575491453dbd478d5a3413ac759c" id="r_gad3c0575491453dbd478d5a3413ac759c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3c0575491453dbd478d5a3413ac759c">USART_CR3_IREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga22ce6319d8acdb4a57215aeb933c7a57">USART_CR3_IREN_Pos</a>)</td></tr>
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<tr class="separator:gad3c0575491453dbd478d5a3413ac759c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31c66373bfbae7724c836ac63b8411dd" id="r_ga31c66373bfbae7724c836ac63b8411dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31c66373bfbae7724c836ac63b8411dd">USART_CR3_IREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad3c0575491453dbd478d5a3413ac759c">USART_CR3_IREN_Msk</a></td></tr>
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<tr class="separator:ga31c66373bfbae7724c836ac63b8411dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73290a1bb7594fc2016662ba4b927dd5" id="r_ga73290a1bb7594fc2016662ba4b927dd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73290a1bb7594fc2016662ba4b927dd5">USART_CR3_IRLP_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga73290a1bb7594fc2016662ba4b927dd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67262b96751aebc3a04d3a6d46213633" id="r_ga67262b96751aebc3a04d3a6d46213633"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67262b96751aebc3a04d3a6d46213633">USART_CR3_IRLP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga73290a1bb7594fc2016662ba4b927dd5">USART_CR3_IRLP_Pos</a>)</td></tr>
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<tr class="separator:ga67262b96751aebc3a04d3a6d46213633"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22af8d399f1adda62e31186f0309af80" id="r_ga22af8d399f1adda62e31186f0309af80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22af8d399f1adda62e31186f0309af80">USART_CR3_IRLP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67262b96751aebc3a04d3a6d46213633">USART_CR3_IRLP_Msk</a></td></tr>
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<tr class="separator:ga22af8d399f1adda62e31186f0309af80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7df0071641a9cc2d70e4957c28f923c9" id="r_ga7df0071641a9cc2d70e4957c28f923c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7df0071641a9cc2d70e4957c28f923c9">USART_CR3_HDSEL_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga7df0071641a9cc2d70e4957c28f923c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5553c10996ceb918244202407347848d" id="r_ga5553c10996ceb918244202407347848d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5553c10996ceb918244202407347848d">USART_CR3_HDSEL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7df0071641a9cc2d70e4957c28f923c9">USART_CR3_HDSEL_Pos</a>)</td></tr>
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<tr class="separator:ga5553c10996ceb918244202407347848d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac71129810fab0b46d91161a39e3f8d01" id="r_gac71129810fab0b46d91161a39e3f8d01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac71129810fab0b46d91161a39e3f8d01">USART_CR3_HDSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5553c10996ceb918244202407347848d">USART_CR3_HDSEL_Msk</a></td></tr>
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<tr class="separator:gac71129810fab0b46d91161a39e3f8d01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga818bd165232f86477503e8f9bc9de049" id="r_ga818bd165232f86477503e8f9bc9de049"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga818bd165232f86477503e8f9bc9de049">USART_CR3_NACK_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga818bd165232f86477503e8f9bc9de049"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga214ed21d5354e7a14f013fd4954e4d3a" id="r_ga214ed21d5354e7a14f013fd4954e4d3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga214ed21d5354e7a14f013fd4954e4d3a">USART_CR3_NACK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga818bd165232f86477503e8f9bc9de049">USART_CR3_NACK_Pos</a>)</td></tr>
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<tr class="separator:ga214ed21d5354e7a14f013fd4954e4d3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f3b70b2ee9ff0b59e952fd7ab04373c" id="r_ga3f3b70b2ee9ff0b59e952fd7ab04373c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f3b70b2ee9ff0b59e952fd7ab04373c">USART_CR3_NACK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga214ed21d5354e7a14f013fd4954e4d3a">USART_CR3_NACK_Msk</a></td></tr>
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<tr class="separator:ga3f3b70b2ee9ff0b59e952fd7ab04373c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae269fb759007c1043534a3794f7b98d" id="r_gaae269fb759007c1043534a3794f7b98d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae269fb759007c1043534a3794f7b98d">USART_CR3_SCEN_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaae269fb759007c1043534a3794f7b98d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff592b0d891ba78201de2e08cd9305b8" id="r_gaff592b0d891ba78201de2e08cd9305b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff592b0d891ba78201de2e08cd9305b8">USART_CR3_SCEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaae269fb759007c1043534a3794f7b98d">USART_CR3_SCEN_Pos</a>)</td></tr>
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<tr class="separator:gaff592b0d891ba78201de2e08cd9305b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9180b9249a26988f71d4bb2b0c3eec27" id="r_ga9180b9249a26988f71d4bb2b0c3eec27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9180b9249a26988f71d4bb2b0c3eec27">USART_CR3_SCEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaff592b0d891ba78201de2e08cd9305b8">USART_CR3_SCEN_Msk</a></td></tr>
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<tr class="separator:ga9180b9249a26988f71d4bb2b0c3eec27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga173f2f38fdb5ba3db30d3b2686bd9773" id="r_ga173f2f38fdb5ba3db30d3b2686bd9773"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga173f2f38fdb5ba3db30d3b2686bd9773">USART_CR3_DMAR_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga173f2f38fdb5ba3db30d3b2686bd9773"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dd0232a385ce9760635c92556c3eadf" id="r_ga4dd0232a385ce9760635c92556c3eadf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dd0232a385ce9760635c92556c3eadf">USART_CR3_DMAR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga173f2f38fdb5ba3db30d3b2686bd9773">USART_CR3_DMAR_Pos</a>)</td></tr>
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<tr class="separator:ga4dd0232a385ce9760635c92556c3eadf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff130f15493c765353ec2fd605667c5a" id="r_gaff130f15493c765353ec2fd605667c5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff130f15493c765353ec2fd605667c5a">USART_CR3_DMAR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4dd0232a385ce9760635c92556c3eadf">USART_CR3_DMAR_Msk</a></td></tr>
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<tr class="separator:gaff130f15493c765353ec2fd605667c5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00afc87870cbe74aabf127179dedca3f" id="r_ga00afc87870cbe74aabf127179dedca3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00afc87870cbe74aabf127179dedca3f">USART_CR3_DMAT_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga00afc87870cbe74aabf127179dedca3f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga114a52251ccd0dae87055bbd336add29" id="r_ga114a52251ccd0dae87055bbd336add29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga114a52251ccd0dae87055bbd336add29">USART_CR3_DMAT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga00afc87870cbe74aabf127179dedca3f">USART_CR3_DMAT_Pos</a>)</td></tr>
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<tr class="separator:ga114a52251ccd0dae87055bbd336add29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bb515d3814d448f84e2c98bf44f3993" id="r_ga5bb515d3814d448f84e2c98bf44f3993"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bb515d3814d448f84e2c98bf44f3993">USART_CR3_DMAT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga114a52251ccd0dae87055bbd336add29">USART_CR3_DMAT_Msk</a></td></tr>
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<tr class="separator:ga5bb515d3814d448f84e2c98bf44f3993"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga790491b1c83dd6a84a6f86945cf74563" id="r_ga790491b1c83dd6a84a6f86945cf74563"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga790491b1c83dd6a84a6f86945cf74563">USART_CR3_RTSE_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga790491b1c83dd6a84a6f86945cf74563"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae20cda51a847495ad5f32c5f5c252152" id="r_gae20cda51a847495ad5f32c5f5c252152"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae20cda51a847495ad5f32c5f5c252152">USART_CR3_RTSE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga790491b1c83dd6a84a6f86945cf74563">USART_CR3_RTSE_Pos</a>)</td></tr>
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<tr class="separator:gae20cda51a847495ad5f32c5f5c252152"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c5d6fcd84a4728cda578a0339b4cac2" id="r_ga7c5d6fcd84a4728cda578a0339b4cac2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c5d6fcd84a4728cda578a0339b4cac2">USART_CR3_RTSE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae20cda51a847495ad5f32c5f5c252152">USART_CR3_RTSE_Msk</a></td></tr>
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<tr class="separator:ga7c5d6fcd84a4728cda578a0339b4cac2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3bfa28091d9c8781aeb03fcb371dd01" id="r_gae3bfa28091d9c8781aeb03fcb371dd01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3bfa28091d9c8781aeb03fcb371dd01">USART_CR3_CTSE_Pos</a>   (9U)</td></tr>
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<tr class="separator:gae3bfa28091d9c8781aeb03fcb371dd01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97e4c254d292233d827a898bda170fa4" id="r_ga97e4c254d292233d827a898bda170fa4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97e4c254d292233d827a898bda170fa4">USART_CR3_CTSE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3bfa28091d9c8781aeb03fcb371dd01">USART_CR3_CTSE_Pos</a>)</td></tr>
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<tr class="separator:ga97e4c254d292233d827a898bda170fa4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa125f026b1ca2d76eab48b191baed265" id="r_gaa125f026b1ca2d76eab48b191baed265"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa125f026b1ca2d76eab48b191baed265">USART_CR3_CTSE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97e4c254d292233d827a898bda170fa4">USART_CR3_CTSE_Msk</a></td></tr>
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<tr class="separator:gaa125f026b1ca2d76eab48b191baed265"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga660c0090fb7c6c17bce5f15a7b07ce7d" id="r_ga660c0090fb7c6c17bce5f15a7b07ce7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga660c0090fb7c6c17bce5f15a7b07ce7d">USART_CR3_CTSIE_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga660c0090fb7c6c17bce5f15a7b07ce7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ca77aa980a93f5b35bf318c20f500cc" id="r_ga8ca77aa980a93f5b35bf318c20f500cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ca77aa980a93f5b35bf318c20f500cc">USART_CR3_CTSIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga660c0090fb7c6c17bce5f15a7b07ce7d">USART_CR3_CTSIE_Pos</a>)</td></tr>
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<tr class="separator:ga8ca77aa980a93f5b35bf318c20f500cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga636d5ec2e9556949fc68d13ad45a1e90" id="r_ga636d5ec2e9556949fc68d13ad45a1e90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga636d5ec2e9556949fc68d13ad45a1e90">USART_CR3_CTSIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ca77aa980a93f5b35bf318c20f500cc">USART_CR3_CTSIE_Msk</a></td></tr>
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<tr class="separator:ga636d5ec2e9556949fc68d13ad45a1e90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d9eb170fd3fa98254e243f588e5a068" id="r_ga8d9eb170fd3fa98254e243f588e5a068"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d9eb170fd3fa98254e243f588e5a068">USART_CR3_ONEBIT_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga8d9eb170fd3fa98254e243f588e5a068"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09e3e99ce53ca74ca3396b63a51f18ac" id="r_ga09e3e99ce53ca74ca3396b63a51f18ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09e3e99ce53ca74ca3396b63a51f18ac">USART_CR3_ONEBIT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d9eb170fd3fa98254e243f588e5a068">USART_CR3_ONEBIT_Pos</a>)</td></tr>
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<tr class="separator:ga09e3e99ce53ca74ca3396b63a51f18ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a96fb1a7beab602cbc8cb0393593826" id="r_ga9a96fb1a7beab602cbc8cb0393593826"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a96fb1a7beab602cbc8cb0393593826">USART_CR3_ONEBIT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga09e3e99ce53ca74ca3396b63a51f18ac">USART_CR3_ONEBIT_Msk</a></td></tr>
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<tr class="separator:ga9a96fb1a7beab602cbc8cb0393593826"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab09117d544d70ca803eb3831fc86b4a2" id="r_gab09117d544d70ca803eb3831fc86b4a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">USART_GTPR_PSC_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga742100366bd139204afb3402a052a588" id="r_ga742100366bd139204afb3402a052a588"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga742100366bd139204afb3402a052a588">USART_GTPR_PSC_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">USART_GTPR_PSC_Pos</a>)</td></tr>
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<tr class="memitem:gaa0b423f0f4baf7d510ea70477e5c9203" id="r_gaa0b423f0f4baf7d510ea70477e5c9203"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0b423f0f4baf7d510ea70477e5c9203">USART_GTPR_PSC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga742100366bd139204afb3402a052a588">USART_GTPR_PSC_Msk</a></td></tr>
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<tr class="memitem:ga2c49c90d83a0e3746b56b2a0a3b0ddcb" id="r_ga2c49c90d83a0e3746b56b2a0a3b0ddcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c49c90d83a0e3746b56b2a0a3b0ddcb">USART_GTPR_PSC_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">USART_GTPR_PSC_Pos</a>)</td></tr>
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<tr class="memitem:ga8eab5000ab993991d0da8ffbd386c92b" id="r_ga8eab5000ab993991d0da8ffbd386c92b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8eab5000ab993991d0da8ffbd386c92b">USART_GTPR_PSC_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">USART_GTPR_PSC_Pos</a>)</td></tr>
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<tr class="memitem:ga9d74604b6e1ab08a45ea4fe6b3f6b5cd" id="r_ga9d74604b6e1ab08a45ea4fe6b3f6b5cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d74604b6e1ab08a45ea4fe6b3f6b5cd">USART_GTPR_PSC_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">USART_GTPR_PSC_Pos</a>)</td></tr>
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<tr class="memitem:ga1b6b237fcac675f8f047c4ff64248486" id="r_ga1b6b237fcac675f8f047c4ff64248486"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b6b237fcac675f8f047c4ff64248486">USART_GTPR_PSC_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">USART_GTPR_PSC_Pos</a>)</td></tr>
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<tr class="memitem:gad1c0e92df8edb974008b3d37d12f655a" id="r_gad1c0e92df8edb974008b3d37d12f655a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1c0e92df8edb974008b3d37d12f655a">USART_GTPR_PSC_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">USART_GTPR_PSC_Pos</a>)</td></tr>
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<tr class="memitem:ga12dda4877432bc181c9684b0830b1b7b" id="r_ga12dda4877432bc181c9684b0830b1b7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga12dda4877432bc181c9684b0830b1b7b">USART_GTPR_PSC_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">USART_GTPR_PSC_Pos</a>)</td></tr>
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<tr class="memitem:ga045e834b03e7a06b2005a13923af424a" id="r_ga045e834b03e7a06b2005a13923af424a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga045e834b03e7a06b2005a13923af424a">USART_GTPR_PSC_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">USART_GTPR_PSC_Pos</a>)</td></tr>
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<tr class="memitem:gad3da67d3c9c3abf436098a86477d2dfc" id="r_gad3da67d3c9c3abf436098a86477d2dfc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3da67d3c9c3abf436098a86477d2dfc">USART_GTPR_PSC_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">USART_GTPR_PSC_Pos</a>)</td></tr>
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<tr class="memitem:ga219c2c6c797f288ff792f0b6c792070b" id="r_ga219c2c6c797f288ff792f0b6c792070b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga219c2c6c797f288ff792f0b6c792070b">USART_GTPR_GT_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga219c2c6c797f288ff792f0b6c792070b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaddc06fc01cf5031610706007672f2780" id="r_gaddc06fc01cf5031610706007672f2780"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddc06fc01cf5031610706007672f2780">USART_GTPR_GT_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga219c2c6c797f288ff792f0b6c792070b">USART_GTPR_GT_Pos</a>)</td></tr>
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<tr class="memitem:ga8e927fad0bfa430f54007e158e01f43b" id="r_ga8e927fad0bfa430f54007e158e01f43b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e927fad0bfa430f54007e158e01f43b">USART_GTPR_GT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaddc06fc01cf5031610706007672f2780">USART_GTPR_GT_Msk</a></td></tr>
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<tr class="memitem:ga1a1da6274cc0fb20e75dfbe1a20ab62e" id="r_ga1a1da6274cc0fb20e75dfbe1a20ab62e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e">WWDG_CR_T_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga1a1da6274cc0fb20e75dfbe1a20ab62e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8676c7d294b92a9ea0d0f1b088308ed" id="r_gaa8676c7d294b92a9ea0d0f1b088308ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8676c7d294b92a9ea0d0f1b088308ed">WWDG_CR_T_Msk</a>   (0x7FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e">WWDG_CR_T_Pos</a>)</td></tr>
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<tr class="separator:gaa8676c7d294b92a9ea0d0f1b088308ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga400774feb33ed7544d57d6a0a76e0f70" id="r_ga400774feb33ed7544d57d6a0a76e0f70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga400774feb33ed7544d57d6a0a76e0f70">WWDG_CR_T</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8676c7d294b92a9ea0d0f1b088308ed">WWDG_CR_T_Msk</a></td></tr>
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<tr class="separator:ga400774feb33ed7544d57d6a0a76e0f70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga305c0da4633020b9696d64a1785fa29c" id="r_ga305c0da4633020b9696d64a1785fa29c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga305c0da4633020b9696d64a1785fa29c">WWDG_CR_T_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e">WWDG_CR_T_Pos</a>)</td></tr>
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<tr class="memitem:ga44e5ea3baea1e37b0446e56e910c3409" id="r_ga44e5ea3baea1e37b0446e56e910c3409"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44e5ea3baea1e37b0446e56e910c3409">WWDG_CR_T_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e">WWDG_CR_T_Pos</a>)</td></tr>
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<tr class="separator:ga44e5ea3baea1e37b0446e56e910c3409"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67e7b9fa1867ecd6a9dd4b28381e4229" id="r_ga67e7b9fa1867ecd6a9dd4b28381e4229"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67e7b9fa1867ecd6a9dd4b28381e4229">WWDG_CR_T_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e">WWDG_CR_T_Pos</a>)</td></tr>
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<tr class="separator:ga67e7b9fa1867ecd6a9dd4b28381e4229"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64ede5bff80b5b979a44d073205f5930" id="r_ga64ede5bff80b5b979a44d073205f5930"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64ede5bff80b5b979a44d073205f5930">WWDG_CR_T_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e">WWDG_CR_T_Pos</a>)</td></tr>
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<tr class="separator:ga64ede5bff80b5b979a44d073205f5930"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabbc9c4a71473ceb1fde58a1d6054a7fe" id="r_gabbc9c4a71473ceb1fde58a1d6054a7fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbc9c4a71473ceb1fde58a1d6054a7fe">WWDG_CR_T_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e">WWDG_CR_T_Pos</a>)</td></tr>
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<tr class="separator:gabbc9c4a71473ceb1fde58a1d6054a7fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f41b8c9b91c0632521373203bcb5b64" id="r_ga9f41b8c9b91c0632521373203bcb5b64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f41b8c9b91c0632521373203bcb5b64">WWDG_CR_T_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e">WWDG_CR_T_Pos</a>)</td></tr>
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<tr class="separator:ga9f41b8c9b91c0632521373203bcb5b64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8abc0d44e390aabc2c7f787f2ed0b632" id="r_ga8abc0d44e390aabc2c7f787f2ed0b632"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8abc0d44e390aabc2c7f787f2ed0b632">WWDG_CR_T_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e">WWDG_CR_T_Pos</a>)</td></tr>
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<tr class="separator:ga8abc0d44e390aabc2c7f787f2ed0b632"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d510237467b8e10ca1001574671ad8e" id="r_ga4d510237467b8e10ca1001574671ad8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d510237467b8e10ca1001574671ad8e">WWDG_CR_T0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga305c0da4633020b9696d64a1785fa29c">WWDG_CR_T_0</a></td></tr>
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<tr class="memitem:gaed4b5d3f4d2e0540058fd2253a8feb95" id="r_gaed4b5d3f4d2e0540058fd2253a8feb95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed4b5d3f4d2e0540058fd2253a8feb95">WWDG_CR_T1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44e5ea3baea1e37b0446e56e910c3409">WWDG_CR_T_1</a></td></tr>
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<tr class="separator:gaed4b5d3f4d2e0540058fd2253a8feb95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4e9559da387f10bac2dc8ab0d4f6e6c" id="r_gaa4e9559da387f10bac2dc8ab0d4f6e6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4e9559da387f10bac2dc8ab0d4f6e6c">WWDG_CR_T2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67e7b9fa1867ecd6a9dd4b28381e4229">WWDG_CR_T_2</a></td></tr>
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<tr class="memitem:gab1e344f4a12c60e57cb643511379b261" id="r_gab1e344f4a12c60e57cb643511379b261"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1e344f4a12c60e57cb643511379b261">WWDG_CR_T3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64ede5bff80b5b979a44d073205f5930">WWDG_CR_T_3</a></td></tr>
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<tr class="memitem:gaf1f89d17eb4b3bb1b67c2b0185061e45" id="r_gaf1f89d17eb4b3bb1b67c2b0185061e45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1f89d17eb4b3bb1b67c2b0185061e45">WWDG_CR_T4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabbc9c4a71473ceb1fde58a1d6054a7fe">WWDG_CR_T_4</a></td></tr>
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<tr class="separator:gaf1f89d17eb4b3bb1b67c2b0185061e45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc9870e0e3a5c171b9c1db817afcf0ee" id="r_gadc9870e0e3a5c171b9c1db817afcf0ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc9870e0e3a5c171b9c1db817afcf0ee">WWDG_CR_T5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f41b8c9b91c0632521373203bcb5b64">WWDG_CR_T_5</a></td></tr>
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<tr class="memitem:gab3a493575c9a7c6006a3af9d13399268" id="r_gab3a493575c9a7c6006a3af9d13399268"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3a493575c9a7c6006a3af9d13399268">WWDG_CR_T6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8abc0d44e390aabc2c7f787f2ed0b632">WWDG_CR_T_6</a></td></tr>
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<tr class="memitem:ga51b9fed94bc5fdbc67446173e1b3676c" id="r_ga51b9fed94bc5fdbc67446173e1b3676c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51b9fed94bc5fdbc67446173e1b3676c">WWDG_CR_WDGA_Pos</a>   (7U)</td></tr>
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<tr class="memitem:ga06bd586be3859790f803c1275ea52390" id="r_ga06bd586be3859790f803c1275ea52390"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06bd586be3859790f803c1275ea52390">WWDG_CR_WDGA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga51b9fed94bc5fdbc67446173e1b3676c">WWDG_CR_WDGA_Pos</a>)</td></tr>
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<tr class="memitem:gab647e9997b8b8e67de72af1aaea3f52f" id="r_gab647e9997b8b8e67de72af1aaea3f52f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab647e9997b8b8e67de72af1aaea3f52f">WWDG_CR_WDGA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06bd586be3859790f803c1275ea52390">WWDG_CR_WDGA_Msk</a></td></tr>
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<tr class="memitem:gae9c98c783bea6069765360fcd6df341b" id="r_gae9c98c783bea6069765360fcd6df341b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b">WWDG_CFR_W_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga3aed21af49014ce535798f9beead136d" id="r_ga3aed21af49014ce535798f9beead136d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3aed21af49014ce535798f9beead136d">WWDG_CFR_W_Msk</a>   (0x7FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b">WWDG_CFR_W_Pos</a>)</td></tr>
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<tr class="separator:ga3aed21af49014ce535798f9beead136d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabfbb9991bd6a3699399ca569c71fe8c9" id="r_gabfbb9991bd6a3699399ca569c71fe8c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfbb9991bd6a3699399ca569c71fe8c9">WWDG_CFR_W</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3aed21af49014ce535798f9beead136d">WWDG_CFR_W_Msk</a></td></tr>
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<tr class="separator:gabfbb9991bd6a3699399ca569c71fe8c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26f4016f9990c2657acdf7521233d16d" id="r_ga26f4016f9990c2657acdf7521233d16d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26f4016f9990c2657acdf7521233d16d">WWDG_CFR_W_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b">WWDG_CFR_W_Pos</a>)</td></tr>
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<tr class="memitem:ga546410b3ec62e976c0f590cf9f216bb3" id="r_ga546410b3ec62e976c0f590cf9f216bb3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga546410b3ec62e976c0f590cf9f216bb3">WWDG_CFR_W_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b">WWDG_CFR_W_Pos</a>)</td></tr>
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<tr class="separator:ga546410b3ec62e976c0f590cf9f216bb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3de841283deaea061d977392805211d" id="r_gac3de841283deaea061d977392805211d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3de841283deaea061d977392805211d">WWDG_CFR_W_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b">WWDG_CFR_W_Pos</a>)</td></tr>
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<tr class="memitem:ga0394248f2a4e4b6ba6c28024fa961a99" id="r_ga0394248f2a4e4b6ba6c28024fa961a99"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0394248f2a4e4b6ba6c28024fa961a99">WWDG_CFR_W_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b">WWDG_CFR_W_Pos</a>)</td></tr>
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<tr class="separator:ga0394248f2a4e4b6ba6c28024fa961a99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25594b7ced3e1277b636caf02416a4e7" id="r_ga25594b7ced3e1277b636caf02416a4e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25594b7ced3e1277b636caf02416a4e7">WWDG_CFR_W_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b">WWDG_CFR_W_Pos</a>)</td></tr>
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<tr class="separator:ga25594b7ced3e1277b636caf02416a4e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e730800b000f6fe3be5ea43a6e29cf9" id="r_ga7e730800b000f6fe3be5ea43a6e29cf9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e730800b000f6fe3be5ea43a6e29cf9">WWDG_CFR_W_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b">WWDG_CFR_W_Pos</a>)</td></tr>
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<tr class="separator:ga7e730800b000f6fe3be5ea43a6e29cf9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9fc25f8d5c23a76d364c1cb5d7518a17" id="r_ga9fc25f8d5c23a76d364c1cb5d7518a17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9fc25f8d5c23a76d364c1cb5d7518a17">WWDG_CFR_W_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b">WWDG_CFR_W_Pos</a>)</td></tr>
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<tr class="separator:ga9fc25f8d5c23a76d364c1cb5d7518a17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae37e08098d003f44eb8770a9d9bd40d0" id="r_gae37e08098d003f44eb8770a9d9bd40d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae37e08098d003f44eb8770a9d9bd40d0">WWDG_CFR_W0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga26f4016f9990c2657acdf7521233d16d">WWDG_CFR_W_0</a></td></tr>
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<tr class="separator:gae37e08098d003f44eb8770a9d9bd40d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga698b68239773862647ef5f9d963b80c4" id="r_ga698b68239773862647ef5f9d963b80c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga698b68239773862647ef5f9d963b80c4">WWDG_CFR_W1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga546410b3ec62e976c0f590cf9f216bb3">WWDG_CFR_W_1</a></td></tr>
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<tr class="separator:ga698b68239773862647ef5f9d963b80c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga166845425e89d01552bac0baeec686d9" id="r_ga166845425e89d01552bac0baeec686d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga166845425e89d01552bac0baeec686d9">WWDG_CFR_W2</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac3de841283deaea061d977392805211d">WWDG_CFR_W_2</a></td></tr>
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<tr class="separator:ga166845425e89d01552bac0baeec686d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga344253edc9710aa6db6047b76cce723b" id="r_ga344253edc9710aa6db6047b76cce723b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga344253edc9710aa6db6047b76cce723b">WWDG_CFR_W3</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0394248f2a4e4b6ba6c28024fa961a99">WWDG_CFR_W_3</a></td></tr>
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<tr class="separator:ga344253edc9710aa6db6047b76cce723b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec3a0817a2dcde78414d02c0cb5d201d" id="r_gaec3a0817a2dcde78414d02c0cb5d201d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec3a0817a2dcde78414d02c0cb5d201d">WWDG_CFR_W4</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga25594b7ced3e1277b636caf02416a4e7">WWDG_CFR_W_4</a></td></tr>
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<tr class="separator:gaec3a0817a2dcde78414d02c0cb5d201d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8032c21626b10fcf5cd8ad36bc051663" id="r_ga8032c21626b10fcf5cd8ad36bc051663"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8032c21626b10fcf5cd8ad36bc051663">WWDG_CFR_W5</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e730800b000f6fe3be5ea43a6e29cf9">WWDG_CFR_W_5</a></td></tr>
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<tr class="separator:ga8032c21626b10fcf5cd8ad36bc051663"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga106cdb96da03ce192628f54cefcbec2f" id="r_ga106cdb96da03ce192628f54cefcbec2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga106cdb96da03ce192628f54cefcbec2f">WWDG_CFR_W6</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9fc25f8d5c23a76d364c1cb5d7518a17">WWDG_CFR_W_6</a></td></tr>
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<tr class="separator:ga106cdb96da03ce192628f54cefcbec2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga496363a4b305b4aa94d9ec6c80d232f1" id="r_ga496363a4b305b4aa94d9ec6c80d232f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga496363a4b305b4aa94d9ec6c80d232f1">WWDG_CFR_WDGTB_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga496363a4b305b4aa94d9ec6c80d232f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga627018d443463abccf249b1b848e2b64" id="r_ga627018d443463abccf249b1b848e2b64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga627018d443463abccf249b1b848e2b64">WWDG_CFR_WDGTB_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga496363a4b305b4aa94d9ec6c80d232f1">WWDG_CFR_WDGTB_Pos</a>)</td></tr>
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<tr class="separator:ga627018d443463abccf249b1b848e2b64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga067b1d8238f1d5613481aba71a946638" id="r_ga067b1d8238f1d5613481aba71a946638"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga067b1d8238f1d5613481aba71a946638">WWDG_CFR_WDGTB</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga627018d443463abccf249b1b848e2b64">WWDG_CFR_WDGTB_Msk</a></td></tr>
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<tr class="separator:ga067b1d8238f1d5613481aba71a946638"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab94b761166186987f91d342a5f79695" id="r_gaab94b761166186987f91d342a5f79695"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab94b761166186987f91d342a5f79695">WWDG_CFR_WDGTB_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga496363a4b305b4aa94d9ec6c80d232f1">WWDG_CFR_WDGTB_Pos</a>)</td></tr>
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<tr class="separator:gaab94b761166186987f91d342a5f79695"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9120ceb094ab327ec766a06fc66ef401" id="r_ga9120ceb094ab327ec766a06fc66ef401"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9120ceb094ab327ec766a06fc66ef401">WWDG_CFR_WDGTB_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga496363a4b305b4aa94d9ec6c80d232f1">WWDG_CFR_WDGTB_Pos</a>)</td></tr>
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<tr class="separator:ga9120ceb094ab327ec766a06fc66ef401"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4858525604534e493b8a09e0b04ace61" id="r_ga4858525604534e493b8a09e0b04ace61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4858525604534e493b8a09e0b04ace61">WWDG_CFR_WDGTB0</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaab94b761166186987f91d342a5f79695">WWDG_CFR_WDGTB_0</a></td></tr>
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<tr class="separator:ga4858525604534e493b8a09e0b04ace61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d53e6fa74c43522ebacd6dd6f450d33" id="r_ga9d53e6fa74c43522ebacd6dd6f450d33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d53e6fa74c43522ebacd6dd6f450d33">WWDG_CFR_WDGTB1</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9120ceb094ab327ec766a06fc66ef401">WWDG_CFR_WDGTB_1</a></td></tr>
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<tr class="separator:ga9d53e6fa74c43522ebacd6dd6f450d33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b4e702f6496841d60bc7ada8d68d648" id="r_ga6b4e702f6496841d60bc7ada8d68d648"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b4e702f6496841d60bc7ada8d68d648">WWDG_CFR_EWI_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga6b4e702f6496841d60bc7ada8d68d648"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca4ed7e970421b1b4b4b0f94e3296117" id="r_gaca4ed7e970421b1b4b4b0f94e3296117"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca4ed7e970421b1b4b4b0f94e3296117">WWDG_CFR_EWI_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6b4e702f6496841d60bc7ada8d68d648">WWDG_CFR_EWI_Pos</a>)</td></tr>
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<tr class="separator:gaca4ed7e970421b1b4b4b0f94e3296117"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga931941dc5d795502371ac5dd8fbac1e9" id="r_ga931941dc5d795502371ac5dd8fbac1e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga931941dc5d795502371ac5dd8fbac1e9">WWDG_CFR_EWI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaca4ed7e970421b1b4b4b0f94e3296117">WWDG_CFR_EWI_Msk</a></td></tr>
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<tr class="separator:ga931941dc5d795502371ac5dd8fbac1e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4c37d2819f82d4cec6c8c9a9250ee43" id="r_gac4c37d2819f82d4cec6c8c9a9250ee43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4c37d2819f82d4cec6c8c9a9250ee43">WWDG_SR_EWIF_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac4c37d2819f82d4cec6c8c9a9250ee43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga284cdb5e7c17598a03a9a0790dd7508c" id="r_ga284cdb5e7c17598a03a9a0790dd7508c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga284cdb5e7c17598a03a9a0790dd7508c">WWDG_SR_EWIF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4c37d2819f82d4cec6c8c9a9250ee43">WWDG_SR_EWIF_Pos</a>)</td></tr>
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<tr class="memitem:ga96cf9ddd91b6079c5aceef6f3e857b69" id="r_ga96cf9ddd91b6079c5aceef6f3e857b69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96cf9ddd91b6079c5aceef6f3e857b69">WWDG_SR_EWIF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga284cdb5e7c17598a03a9a0790dd7508c">WWDG_SR_EWIF_Msk</a></td></tr>
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<tr class="separator:ga96cf9ddd91b6079c5aceef6f3e857b69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad05a229877e557798dfbabe7188d7a54" id="r_gad05a229877e557798dfbabe7188d7a54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad05a229877e557798dfbabe7188d7a54">DBGMCU_IDCODE_DEV_ID_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gabf18661126fecb64b8c7d7d4e590fb33" id="r_gabf18661126fecb64b8c7d7d4e590fb33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf18661126fecb64b8c7d7d4e590fb33">DBGMCU_IDCODE_DEV_ID_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad05a229877e557798dfbabe7188d7a54">DBGMCU_IDCODE_DEV_ID_Pos</a>)</td></tr>
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<tr class="separator:gabf18661126fecb64b8c7d7d4e590fb33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd961fcddc40341a817a9ec85b7c80ac" id="r_gafd961fcddc40341a817a9ec85b7c80ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd961fcddc40341a817a9ec85b7c80ac">DBGMCU_IDCODE_DEV_ID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabf18661126fecb64b8c7d7d4e590fb33">DBGMCU_IDCODE_DEV_ID_Msk</a></td></tr>
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<tr class="separator:gafd961fcddc40341a817a9ec85b7c80ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e98f7579d16c36cbf6a09b04f2ee170" id="r_ga6e98f7579d16c36cbf6a09b04f2ee170"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e98f7579d16c36cbf6a09b04f2ee170">DBGMCU_IDCODE_REV_ID_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga6e98f7579d16c36cbf6a09b04f2ee170"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d92c620aed9b19c7e8d9d12f743b258" id="r_ga0d92c620aed9b19c7e8d9d12f743b258"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d92c620aed9b19c7e8d9d12f743b258">DBGMCU_IDCODE_REV_ID_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e98f7579d16c36cbf6a09b04f2ee170">DBGMCU_IDCODE_REV_ID_Pos</a>)</td></tr>
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<tr class="separator:ga0d92c620aed9b19c7e8d9d12f743b258"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga887eb26364a8693355024ca203323165" id="r_ga887eb26364a8693355024ca203323165"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga887eb26364a8693355024ca203323165">DBGMCU_IDCODE_REV_ID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d92c620aed9b19c7e8d9d12f743b258">DBGMCU_IDCODE_REV_ID_Msk</a></td></tr>
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<tr class="separator:ga887eb26364a8693355024ca203323165"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b996a2be01fbeeaa868603c7bca6044" id="r_ga3b996a2be01fbeeaa868603c7bca6044"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b996a2be01fbeeaa868603c7bca6044">DBGMCU_CR_DBG_SLEEP_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga127e0531bc305bb460fd2417106bee61" id="r_ga127e0531bc305bb460fd2417106bee61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga127e0531bc305bb460fd2417106bee61">DBGMCU_CR_DBG_SLEEP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b996a2be01fbeeaa868603c7bca6044">DBGMCU_CR_DBG_SLEEP_Pos</a>)</td></tr>
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<tr class="separator:ga127e0531bc305bb460fd2417106bee61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga037c80fe1d7308cee68245715ef6cd9a" id="r_ga037c80fe1d7308cee68245715ef6cd9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga037c80fe1d7308cee68245715ef6cd9a">DBGMCU_CR_DBG_SLEEP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga127e0531bc305bb460fd2417106bee61">DBGMCU_CR_DBG_SLEEP_Msk</a></td></tr>
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<tr class="separator:ga037c80fe1d7308cee68245715ef6cd9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga998b25ffd43297001c2f20ebb04fbcc9" id="r_ga998b25ffd43297001c2f20ebb04fbcc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga998b25ffd43297001c2f20ebb04fbcc9">DBGMCU_CR_DBG_STOP_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga998b25ffd43297001c2f20ebb04fbcc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71cd122085cdadba462f9e251ac35349" id="r_ga71cd122085cdadba462f9e251ac35349"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71cd122085cdadba462f9e251ac35349">DBGMCU_CR_DBG_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga998b25ffd43297001c2f20ebb04fbcc9">DBGMCU_CR_DBG_STOP_Pos</a>)</td></tr>
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<tr class="separator:ga71cd122085cdadba462f9e251ac35349"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf511f21a8de5b0b66c862915eee8bf75" id="r_gaf511f21a8de5b0b66c862915eee8bf75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf511f21a8de5b0b66c862915eee8bf75">DBGMCU_CR_DBG_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71cd122085cdadba462f9e251ac35349">DBGMCU_CR_DBG_STOP_Msk</a></td></tr>
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<tr class="separator:gaf511f21a8de5b0b66c862915eee8bf75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74521b2e06cd16f46ea5987d82f9ff19" id="r_ga74521b2e06cd16f46ea5987d82f9ff19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74521b2e06cd16f46ea5987d82f9ff19">DBGMCU_CR_DBG_STANDBY_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga74521b2e06cd16f46ea5987d82f9ff19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52e9a797b04f9577456af2499f5bd9ff" id="r_ga52e9a797b04f9577456af2499f5bd9ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52e9a797b04f9577456af2499f5bd9ff">DBGMCU_CR_DBG_STANDBY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga74521b2e06cd16f46ea5987d82f9ff19">DBGMCU_CR_DBG_STANDBY_Pos</a>)</td></tr>
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<tr class="separator:ga52e9a797b04f9577456af2499f5bd9ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga107a9396d63c892a8e614897c9d0b132" id="r_ga107a9396d63c892a8e614897c9d0b132"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga107a9396d63c892a8e614897c9d0b132">DBGMCU_CR_DBG_STANDBY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga52e9a797b04f9577456af2499f5bd9ff">DBGMCU_CR_DBG_STANDBY_Msk</a></td></tr>
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<tr class="separator:ga107a9396d63c892a8e614897c9d0b132"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2be1af4b18b8c9ce4001dd363e6626e7" id="r_ga2be1af4b18b8c9ce4001dd363e6626e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2be1af4b18b8c9ce4001dd363e6626e7">DBGMCU_CR_TRACE_IOEN_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga2be1af4b18b8c9ce4001dd363e6626e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18007dc2c11d41a5dc449e37cb8c0c56" id="r_ga18007dc2c11d41a5dc449e37cb8c0c56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18007dc2c11d41a5dc449e37cb8c0c56">DBGMCU_CR_TRACE_IOEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2be1af4b18b8c9ce4001dd363e6626e7">DBGMCU_CR_TRACE_IOEN_Pos</a>)</td></tr>
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<tr class="separator:ga18007dc2c11d41a5dc449e37cb8c0c56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9034b6eb9d4dceadffc6a1d1959056c9" id="r_ga9034b6eb9d4dceadffc6a1d1959056c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9034b6eb9d4dceadffc6a1d1959056c9">DBGMCU_CR_TRACE_IOEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga18007dc2c11d41a5dc449e37cb8c0c56">DBGMCU_CR_TRACE_IOEN_Msk</a></td></tr>
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<tr class="separator:ga9034b6eb9d4dceadffc6a1d1959056c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20dddffa934315ca4a5902cbf45f4d93" id="r_ga20dddffa934315ca4a5902cbf45f4d93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20dddffa934315ca4a5902cbf45f4d93">DBGMCU_CR_TRACE_MODE_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga20dddffa934315ca4a5902cbf45f4d93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad641a08b344645d47a0789ffa25d7079" id="r_gad641a08b344645d47a0789ffa25d7079"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad641a08b344645d47a0789ffa25d7079">DBGMCU_CR_TRACE_MODE_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20dddffa934315ca4a5902cbf45f4d93">DBGMCU_CR_TRACE_MODE_Pos</a>)</td></tr>
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<tr class="separator:gad641a08b344645d47a0789ffa25d7079"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1395189e10bdbc37bce9ea480e22d10" id="r_gaa1395189e10bdbc37bce9ea480e22d10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1395189e10bdbc37bce9ea480e22d10">DBGMCU_CR_TRACE_MODE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad641a08b344645d47a0789ffa25d7079">DBGMCU_CR_TRACE_MODE_Msk</a></td></tr>
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<tr class="separator:gaa1395189e10bdbc37bce9ea480e22d10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d41a4027853783633d929a43f8d6d85" id="r_ga2d41a4027853783633d929a43f8d6d85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d41a4027853783633d929a43f8d6d85">DBGMCU_CR_TRACE_MODE_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20dddffa934315ca4a5902cbf45f4d93">DBGMCU_CR_TRACE_MODE_Pos</a>)</td></tr>
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<tr class="separator:ga2d41a4027853783633d929a43f8d6d85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ba3a830051b53d43d850768242c503e" id="r_ga7ba3a830051b53d43d850768242c503e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ba3a830051b53d43d850768242c503e">DBGMCU_CR_TRACE_MODE_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20dddffa934315ca4a5902cbf45f4d93">DBGMCU_CR_TRACE_MODE_Pos</a>)</td></tr>
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<tr class="separator:ga7ba3a830051b53d43d850768242c503e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1de6489ecedec59891894a54458bef2" id="r_gad1de6489ecedec59891894a54458bef2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1de6489ecedec59891894a54458bef2">DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad1de6489ecedec59891894a54458bef2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf96a2b1fb00169f78d3c8fb050ca35be" id="r_gaf96a2b1fb00169f78d3c8fb050ca35be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf96a2b1fb00169f78d3c8fb050ca35be">DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad1de6489ecedec59891894a54458bef2">DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos</a>)</td></tr>
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<tr class="separator:gaf96a2b1fb00169f78d3c8fb050ca35be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae3c5b87084934a18748f5ec168f5aef" id="r_gaae3c5b87084934a18748f5ec168f5aef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae3c5b87084934a18748f5ec168f5aef">DBGMCU_APB1_FZ_DBG_TIM2_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf96a2b1fb00169f78d3c8fb050ca35be">DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk</a></td></tr>
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<tr class="separator:gaae3c5b87084934a18748f5ec168f5aef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bd5fd9c34fd75ddb5c77d526f8f53a1" id="r_ga3bd5fd9c34fd75ddb5c77d526f8f53a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bd5fd9c34fd75ddb5c77d526f8f53a1">DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga3bd5fd9c34fd75ddb5c77d526f8f53a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab210ab764b68711904243c0d11631b8" id="r_gaab210ab764b68711904243c0d11631b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab210ab764b68711904243c0d11631b8">DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bd5fd9c34fd75ddb5c77d526f8f53a1">DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos</a>)</td></tr>
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<tr class="separator:gaab210ab764b68711904243c0d11631b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2fea6834f4ef9fc6b403cd079a001cec" id="r_ga2fea6834f4ef9fc6b403cd079a001cec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fea6834f4ef9fc6b403cd079a001cec">DBGMCU_APB1_FZ_DBG_TIM3_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaab210ab764b68711904243c0d11631b8">DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk</a></td></tr>
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<tr class="separator:ga2fea6834f4ef9fc6b403cd079a001cec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeef66d67708ae915fbbc2ee76aeaef3e" id="r_gaeef66d67708ae915fbbc2ee76aeaef3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeef66d67708ae915fbbc2ee76aeaef3e">DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaeef66d67708ae915fbbc2ee76aeaef3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7dfb56349db84ef1ef5753e13cf2f48" id="r_gaa7dfb56349db84ef1ef5753e13cf2f48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7dfb56349db84ef1ef5753e13cf2f48">DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeef66d67708ae915fbbc2ee76aeaef3e">DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos</a>)</td></tr>
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<tr class="memitem:ga7ac65bf9342bb8acbcb25938e93abc45" id="r_ga7ac65bf9342bb8acbcb25938e93abc45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ac65bf9342bb8acbcb25938e93abc45">DBGMCU_APB1_FZ_DBG_TIM4_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7dfb56349db84ef1ef5753e13cf2f48">DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk</a></td></tr>
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<tr class="memitem:ga5218cc7d400bfb220c42a80b3a2a0603" id="r_ga5218cc7d400bfb220c42a80b3a2a0603"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5218cc7d400bfb220c42a80b3a2a0603">DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos</a>   (3U)</td></tr>
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<tr class="memitem:gac4e288f717db03126942d03a1a6fafd8" id="r_gac4e288f717db03126942d03a1a6fafd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4e288f717db03126942d03a1a6fafd8">DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5218cc7d400bfb220c42a80b3a2a0603">DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos</a>)</td></tr>
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<tr class="memitem:ga42d29d40515d36ce6ed7e5d34ed17dcf" id="r_ga42d29d40515d36ce6ed7e5d34ed17dcf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42d29d40515d36ce6ed7e5d34ed17dcf">DBGMCU_APB1_FZ_DBG_TIM5_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4e288f717db03126942d03a1a6fafd8">DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk</a></td></tr>
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<tr class="separator:ga42d29d40515d36ce6ed7e5d34ed17dcf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf603706e632bf2df878b8ba6fc0c4736" id="r_gaf603706e632bf2df878b8ba6fc0c4736"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf603706e632bf2df878b8ba6fc0c4736">DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos</a>   (4U)</td></tr>
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<tr class="memitem:gae3215a197f13b82287892283886326d1" id="r_gae3215a197f13b82287892283886326d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3215a197f13b82287892283886326d1">DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf603706e632bf2df878b8ba6fc0c4736">DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos</a>)</td></tr>
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<tr class="memitem:gadea6a1e90739bcf1d0723a0566c66de7" id="r_gadea6a1e90739bcf1d0723a0566c66de7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadea6a1e90739bcf1d0723a0566c66de7">DBGMCU_APB1_FZ_DBG_TIM6_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3215a197f13b82287892283886326d1">DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk</a></td></tr>
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<tr class="memitem:gab8568c72922b902663a7ade0e9d6cb88" id="r_gab8568c72922b902663a7ade0e9d6cb88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8568c72922b902663a7ade0e9d6cb88">DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos</a>   (5U)</td></tr>
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<tr class="separator:gab8568c72922b902663a7ade0e9d6cb88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29df0ea459e1900942f3e26141e0f9dd" id="r_ga29df0ea459e1900942f3e26141e0f9dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29df0ea459e1900942f3e26141e0f9dd">DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8568c72922b902663a7ade0e9d6cb88">DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos</a>)</td></tr>
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<tr class="memitem:gafdade78c3d28a668f9826d0b72e5844b" id="r_gafdade78c3d28a668f9826d0b72e5844b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdade78c3d28a668f9826d0b72e5844b">DBGMCU_APB1_FZ_DBG_TIM7_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga29df0ea459e1900942f3e26141e0f9dd">DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk</a></td></tr>
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<tr class="memitem:ga9db1b0c37f083a12d94bbf6beeb4516e" id="r_ga9db1b0c37f083a12d94bbf6beeb4516e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9db1b0c37f083a12d94bbf6beeb4516e">DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos</a>   (6U)</td></tr>
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<tr class="memitem:gadfcabcb2e0efbe9e76b3eae58b30943b" id="r_gadfcabcb2e0efbe9e76b3eae58b30943b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfcabcb2e0efbe9e76b3eae58b30943b">DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9db1b0c37f083a12d94bbf6beeb4516e">DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos</a>)</td></tr>
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<tr class="memitem:ga7ca0e04ad8c94e5b7fe29d8b9c20ebff" id="r_ga7ca0e04ad8c94e5b7fe29d8b9c20ebff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ca0e04ad8c94e5b7fe29d8b9c20ebff">DBGMCU_APB1_FZ_DBG_TIM12_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadfcabcb2e0efbe9e76b3eae58b30943b">DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk</a></td></tr>
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<tr class="memitem:gab27cca037c1de40bf8855316c266abd2" id="r_gab27cca037c1de40bf8855316c266abd2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab27cca037c1de40bf8855316c266abd2">DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos</a>   (7U)</td></tr>
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<tr class="memitem:ga8e25332c23efcacd48317de37e337af6" id="r_ga8e25332c23efcacd48317de37e337af6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e25332c23efcacd48317de37e337af6">DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab27cca037c1de40bf8855316c266abd2">DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos</a>)</td></tr>
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<tr class="memitem:ga68ef63b3c086ede54396596798553299" id="r_ga68ef63b3c086ede54396596798553299"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68ef63b3c086ede54396596798553299">DBGMCU_APB1_FZ_DBG_TIM13_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e25332c23efcacd48317de37e337af6">DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk</a></td></tr>
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<tr class="separator:ga68ef63b3c086ede54396596798553299"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf940f736a0f2e4531d141e53257e4e6d" id="r_gaf940f736a0f2e4531d141e53257e4e6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf940f736a0f2e4531d141e53257e4e6d">DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaf940f736a0f2e4531d141e53257e4e6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeec836ee0ced45ad06aa4b025f13987e" id="r_gaeec836ee0ced45ad06aa4b025f13987e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeec836ee0ced45ad06aa4b025f13987e">DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf940f736a0f2e4531d141e53257e4e6d">DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos</a>)</td></tr>
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<tr class="separator:gaeec836ee0ced45ad06aa4b025f13987e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd3acb3e632c74e326da7016073c7871" id="r_gafd3acb3e632c74e326da7016073c7871"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd3acb3e632c74e326da7016073c7871">DBGMCU_APB1_FZ_DBG_TIM14_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeec836ee0ced45ad06aa4b025f13987e">DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk</a></td></tr>
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<tr class="separator:gafd3acb3e632c74e326da7016073c7871"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga004684cb88ffb723509a9ca4193e78ec" id="r_ga004684cb88ffb723509a9ca4193e78ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga004684cb88ffb723509a9ca4193e78ec">DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos</a>   (10U)</td></tr>
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<tr class="memitem:gaf7fefeace05cb28675d23037f7b3966a" id="r_gaf7fefeace05cb28675d23037f7b3966a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7fefeace05cb28675d23037f7b3966a">DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga004684cb88ffb723509a9ca4193e78ec">DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos</a>)</td></tr>
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<tr class="separator:gaf7fefeace05cb28675d23037f7b3966a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e20246d389229ff46006b405bb56b1d" id="r_ga1e20246d389229ff46006b405bb56b1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e20246d389229ff46006b405bb56b1d">DBGMCU_APB1_FZ_DBG_RTC_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf7fefeace05cb28675d23037f7b3966a">DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk</a></td></tr>
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<tr class="separator:ga1e20246d389229ff46006b405bb56b1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaad459d6930c29babb7672cd26d0ea9b" id="r_gaaad459d6930c29babb7672cd26d0ea9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaad459d6930c29babb7672cd26d0ea9b">DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaaad459d6930c29babb7672cd26d0ea9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f24695b718a52f4a91297ee3c512db4" id="r_ga0f24695b718a52f4a91297ee3c512db4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f24695b718a52f4a91297ee3c512db4">DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaad459d6930c29babb7672cd26d0ea9b">DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos</a>)</td></tr>
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<tr class="separator:ga0f24695b718a52f4a91297ee3c512db4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a49d5e849185d09ee6c7594512ffe88" id="r_ga8a49d5e849185d09ee6c7594512ffe88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a49d5e849185d09ee6c7594512ffe88">DBGMCU_APB1_FZ_DBG_WWDG_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f24695b718a52f4a91297ee3c512db4">DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk</a></td></tr>
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<tr class="separator:ga8a49d5e849185d09ee6c7594512ffe88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bb0a55a4b7c9c3deeb61568b9c7e85c" id="r_ga3bb0a55a4b7c9c3deeb61568b9c7e85c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bb0a55a4b7c9c3deeb61568b9c7e85c">DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga3bb0a55a4b7c9c3deeb61568b9c7e85c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a7937e3a29764f7e80895b8fbe81baa" id="r_ga9a7937e3a29764f7e80895b8fbe81baa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a7937e3a29764f7e80895b8fbe81baa">DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bb0a55a4b7c9c3deeb61568b9c7e85c">DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos</a>)</td></tr>
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<tr class="separator:ga9a7937e3a29764f7e80895b8fbe81baa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada8989cb96dd5d6dbdaaf16e1f127c6a" id="r_gada8989cb96dd5d6dbdaaf16e1f127c6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada8989cb96dd5d6dbdaaf16e1f127c6a">DBGMCU_APB1_FZ_DBG_IWDG_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a7937e3a29764f7e80895b8fbe81baa">DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk</a></td></tr>
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<tr class="separator:gada8989cb96dd5d6dbdaaf16e1f127c6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga303e9dea0617bb3f03a8cc825005d6ce" id="r_ga303e9dea0617bb3f03a8cc825005d6ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga303e9dea0617bb3f03a8cc825005d6ce">DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga303e9dea0617bb3f03a8cc825005d6ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga202de646d5890eec98b04ad2be808604" id="r_ga202de646d5890eec98b04ad2be808604"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga202de646d5890eec98b04ad2be808604">DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga303e9dea0617bb3f03a8cc825005d6ce">DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos</a>)</td></tr>
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<tr class="memitem:gae83fb5d62c6e6fa1c2fd06084528404e" id="r_gae83fb5d62c6e6fa1c2fd06084528404e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae83fb5d62c6e6fa1c2fd06084528404e">DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga202de646d5890eec98b04ad2be808604">DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk</a></td></tr>
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<tr class="separator:gae83fb5d62c6e6fa1c2fd06084528404e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc66781299067fbbec7d1be708314c17" id="r_gabc66781299067fbbec7d1be708314c17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc66781299067fbbec7d1be708314c17">DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos</a>   (22U)</td></tr>
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<tr class="separator:gabc66781299067fbbec7d1be708314c17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae03e6603b8d1af65a2b5c026c8379908" id="r_gae03e6603b8d1af65a2b5c026c8379908"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae03e6603b8d1af65a2b5c026c8379908">DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabc66781299067fbbec7d1be708314c17">DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos</a>)</td></tr>
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<tr class="separator:gae03e6603b8d1af65a2b5c026c8379908"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f6320aba695f6c3f97608e478533e96" id="r_ga8f6320aba695f6c3f97608e478533e96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f6320aba695f6c3f97608e478533e96">DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae03e6603b8d1af65a2b5c026c8379908">DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk</a></td></tr>
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<tr class="separator:ga8f6320aba695f6c3f97608e478533e96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c17ca25c071d846eeecdc761f590bf0" id="r_ga0c17ca25c071d846eeecdc761f590bf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c17ca25c071d846eeecdc761f590bf0">DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga0c17ca25c071d846eeecdc761f590bf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ebb7cd7e57d8d9888025cfbdea082b4" id="r_ga0ebb7cd7e57d8d9888025cfbdea082b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ebb7cd7e57d8d9888025cfbdea082b4">DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c17ca25c071d846eeecdc761f590bf0">DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos</a>)</td></tr>
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<tr class="separator:ga0ebb7cd7e57d8d9888025cfbdea082b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f7e5c708387aa1ddae35b892811b4e9" id="r_ga7f7e5c708387aa1ddae35b892811b4e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f7e5c708387aa1ddae35b892811b4e9">DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ebb7cd7e57d8d9888025cfbdea082b4">DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk</a></td></tr>
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<tr class="separator:ga7f7e5c708387aa1ddae35b892811b4e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf44a606db87b49504fc17760eba9290d" id="r_gaf44a606db87b49504fc17760eba9290d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf44a606db87b49504fc17760eba9290d">DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos</a>   (25U)</td></tr>
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<tr class="separator:gaf44a606db87b49504fc17760eba9290d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72cf0d5d23a0ac36f3c4c5515082221d" id="r_ga72cf0d5d23a0ac36f3c4c5515082221d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72cf0d5d23a0ac36f3c4c5515082221d">DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf44a606db87b49504fc17760eba9290d">DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos</a>)</td></tr>
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<tr class="separator:ga72cf0d5d23a0ac36f3c4c5515082221d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b404dcea4857bccabbb03d6cce6be8c" id="r_ga1b404dcea4857bccabbb03d6cce6be8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b404dcea4857bccabbb03d6cce6be8c">DBGMCU_APB1_FZ_DBG_CAN1_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga72cf0d5d23a0ac36f3c4c5515082221d">DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk</a></td></tr>
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<tr class="separator:ga1b404dcea4857bccabbb03d6cce6be8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac38ce10efced0708fe63650e0f855c3d" id="r_gac38ce10efced0708fe63650e0f855c3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac38ce10efced0708fe63650e0f855c3d">DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos</a>   (26U)</td></tr>
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<tr class="separator:gac38ce10efced0708fe63650e0f855c3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6c0ae534d156b18cd9254ab942f88ff" id="r_gaf6c0ae534d156b18cd9254ab942f88ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6c0ae534d156b18cd9254ab942f88ff">DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac38ce10efced0708fe63650e0f855c3d">DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos</a>)</td></tr>
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<tr class="separator:gaf6c0ae534d156b18cd9254ab942f88ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadc3889d6b84d143c98ecbfd873a9a1a" id="r_gaadc3889d6b84d143c98ecbfd873a9a1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadc3889d6b84d143c98ecbfd873a9a1a">DBGMCU_APB1_FZ_DBG_CAN2_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6c0ae534d156b18cd9254ab942f88ff">DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk</a></td></tr>
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<tr class="separator:gaadc3889d6b84d143c98ecbfd873a9a1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe48f858edb831fbcb8769421df7d8e9" id="r_gabe48f858edb831fbcb8769421df7d8e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe48f858edb831fbcb8769421df7d8e9">DBGMCU_APB1_FZ_DBG_IWDEG_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada8989cb96dd5d6dbdaaf16e1f127c6a">DBGMCU_APB1_FZ_DBG_IWDG_STOP</a></td></tr>
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<tr class="separator:gabe48f858edb831fbcb8769421df7d8e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b30844d430324cfe63e4932275a6978" id="r_ga2b30844d430324cfe63e4932275a6978"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b30844d430324cfe63e4932275a6978">DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2b30844d430324cfe63e4932275a6978"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74cb9644d7d1eaf1a71254121f926169" id="r_ga74cb9644d7d1eaf1a71254121f926169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74cb9644d7d1eaf1a71254121f926169">DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b30844d430324cfe63e4932275a6978">DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos</a>)</td></tr>
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<tr class="separator:ga74cb9644d7d1eaf1a71254121f926169"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3eb7be194b6ffb258b9e9f5ed08a931e" id="r_ga3eb7be194b6ffb258b9e9f5ed08a931e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3eb7be194b6ffb258b9e9f5ed08a931e">DBGMCU_APB2_FZ_DBG_TIM1_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga74cb9644d7d1eaf1a71254121f926169">DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk</a></td></tr>
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<tr class="separator:ga3eb7be194b6ffb258b9e9f5ed08a931e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac84a0fb177332acd69c944aa00e90340" id="r_gac84a0fb177332acd69c944aa00e90340"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac84a0fb177332acd69c944aa00e90340">DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos</a>   (1U)</td></tr>
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<tr class="separator:gac84a0fb177332acd69c944aa00e90340"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98002708ee350ecf61a72911df9850b5" id="r_ga98002708ee350ecf61a72911df9850b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98002708ee350ecf61a72911df9850b5">DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac84a0fb177332acd69c944aa00e90340">DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos</a>)</td></tr>
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<tr class="separator:ga98002708ee350ecf61a72911df9850b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37128bf689254919b07f64ee41cad1cf" id="r_ga37128bf689254919b07f64ee41cad1cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37128bf689254919b07f64ee41cad1cf">DBGMCU_APB2_FZ_DBG_TIM8_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga98002708ee350ecf61a72911df9850b5">DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk</a></td></tr>
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<tr class="separator:ga37128bf689254919b07f64ee41cad1cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6fc3b8c8d5cbb8695e7cec3153bbe65" id="r_gaa6fc3b8c8d5cbb8695e7cec3153bbe65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6fc3b8c8d5cbb8695e7cec3153bbe65">DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaa6fc3b8c8d5cbb8695e7cec3153bbe65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga983432f2957617c4215fe406dd932080" id="r_ga983432f2957617c4215fe406dd932080"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga983432f2957617c4215fe406dd932080">DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6fc3b8c8d5cbb8695e7cec3153bbe65">DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos</a>)</td></tr>
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<tr class="separator:ga983432f2957617c4215fe406dd932080"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf12c17533a1e3262ee11f760e44f5127" id="r_gaf12c17533a1e3262ee11f760e44f5127"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf12c17533a1e3262ee11f760e44f5127">DBGMCU_APB2_FZ_DBG_TIM9_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga983432f2957617c4215fe406dd932080">DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk</a></td></tr>
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<tr class="separator:gaf12c17533a1e3262ee11f760e44f5127"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2eb21a02384033248b1e45030a314598" id="r_ga2eb21a02384033248b1e45030a314598"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2eb21a02384033248b1e45030a314598">DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga2eb21a02384033248b1e45030a314598"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9390f2c13a5b525bd1e7bbd6501c7a67" id="r_ga9390f2c13a5b525bd1e7bbd6501c7a67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9390f2c13a5b525bd1e7bbd6501c7a67">DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2eb21a02384033248b1e45030a314598">DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos</a>)</td></tr>
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<tr class="separator:ga9390f2c13a5b525bd1e7bbd6501c7a67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24d4bbf803a65e8202b0019ed0ce0ebb" id="r_ga24d4bbf803a65e8202b0019ed0ce0ebb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24d4bbf803a65e8202b0019ed0ce0ebb">DBGMCU_APB2_FZ_DBG_TIM10_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9390f2c13a5b525bd1e7bbd6501c7a67">DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk</a></td></tr>
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<tr class="separator:ga24d4bbf803a65e8202b0019ed0ce0ebb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0dd5b307e8d9992857942180b6f7358f" id="r_ga0dd5b307e8d9992857942180b6f7358f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dd5b307e8d9992857942180b6f7358f">DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga0dd5b307e8d9992857942180b6f7358f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea914b4c8a46cb0be4909dfd4e3199d6" id="r_gaea914b4c8a46cb0be4909dfd4e3199d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea914b4c8a46cb0be4909dfd4e3199d6">DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dd5b307e8d9992857942180b6f7358f">DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos</a>)</td></tr>
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<tr class="separator:gaea914b4c8a46cb0be4909dfd4e3199d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga354671c942db40e69820fd783ef955b4" id="r_ga354671c942db40e69820fd783ef955b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga354671c942db40e69820fd783ef955b4">DBGMCU_APB2_FZ_DBG_TIM11_STOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaea914b4c8a46cb0be4909dfd4e3199d6">DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk</a></td></tr>
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<tr class="separator:ga354671c942db40e69820fd783ef955b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae59108fa4b2f56d375f7b7b2e7d50e30" id="r_gae59108fa4b2f56d375f7b7b2e7d50e30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae59108fa4b2f56d375f7b7b2e7d50e30">ETH_MACCR_WD_Pos</a>   (23U)</td></tr>
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<tr class="separator:gae59108fa4b2f56d375f7b7b2e7d50e30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6dbb23089a2b3d19fd5deb5009a527f3" id="r_ga6dbb23089a2b3d19fd5deb5009a527f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6dbb23089a2b3d19fd5deb5009a527f3">ETH_MACCR_WD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae59108fa4b2f56d375f7b7b2e7d50e30">ETH_MACCR_WD_Pos</a>)</td></tr>
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<tr class="memitem:ga6b90fbae827b1368b83cd9b0d9c64cc8" id="r_ga6b90fbae827b1368b83cd9b0d9c64cc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b90fbae827b1368b83cd9b0d9c64cc8">ETH_MACCR_WD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6dbb23089a2b3d19fd5deb5009a527f3">ETH_MACCR_WD_Msk</a> /* Watchdog disable */</td></tr>
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<tr class="memitem:ga96003f027aa496dc4345472db3b60f10" id="r_ga96003f027aa496dc4345472db3b60f10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96003f027aa496dc4345472db3b60f10">ETH_MACCR_JD_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga96003f027aa496dc4345472db3b60f10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab36b8e9295e605680052d61f262843fc" id="r_gab36b8e9295e605680052d61f262843fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab36b8e9295e605680052d61f262843fc">ETH_MACCR_JD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96003f027aa496dc4345472db3b60f10">ETH_MACCR_JD_Pos</a>)</td></tr>
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<tr class="separator:gab36b8e9295e605680052d61f262843fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ef1243e257142caa99c086b07fa5d42" id="r_ga1ef1243e257142caa99c086b07fa5d42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ef1243e257142caa99c086b07fa5d42">ETH_MACCR_JD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab36b8e9295e605680052d61f262843fc">ETH_MACCR_JD_Msk</a> /* Jabber disable */</td></tr>
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<tr class="separator:ga1ef1243e257142caa99c086b07fa5d42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ef65cca0d90f5944aefd63db1505323" id="r_ga6ef65cca0d90f5944aefd63db1505323"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ef65cca0d90f5944aefd63db1505323">ETH_MACCR_IFG_Pos</a>   (17U)</td></tr>
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<tr class="memitem:ga0081ebdecc02644f5a0a5304478e2f9c" id="r_ga0081ebdecc02644f5a0a5304478e2f9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0081ebdecc02644f5a0a5304478e2f9c">ETH_MACCR_IFG_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ef65cca0d90f5944aefd63db1505323">ETH_MACCR_IFG_Pos</a>)</td></tr>
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<tr class="separator:ga0081ebdecc02644f5a0a5304478e2f9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga989c71f66d1361519d2b0586f30b148f" id="r_ga989c71f66d1361519d2b0586f30b148f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga989c71f66d1361519d2b0586f30b148f">ETH_MACCR_IFG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0081ebdecc02644f5a0a5304478e2f9c">ETH_MACCR_IFG_Msk</a> /* Inter-frame gap */</td></tr>
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<tr class="separator:ga989c71f66d1361519d2b0586f30b148f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga004e9dab4a5e1ed4f165facca6fd80aa" id="r_ga004e9dab4a5e1ed4f165facca6fd80aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga004e9dab4a5e1ed4f165facca6fd80aa">ETH_MACCR_IFG_96Bit</a>   0x00000000U /* Minimum IFG between frames during transmission is 96Bit */</td></tr>
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<tr class="separator:ga004e9dab4a5e1ed4f165facca6fd80aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf0f2ad0cd583f00dd2739cbb3dbdeea" id="r_gacf0f2ad0cd583f00dd2739cbb3dbdeea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf0f2ad0cd583f00dd2739cbb3dbdeea">ETH_MACCR_IFG_88Bit</a>   0x00020000U /* Minimum IFG between frames during transmission is 88Bit */</td></tr>
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<tr class="separator:gacf0f2ad0cd583f00dd2739cbb3dbdeea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56adc3166c71f29d2d30efc6ed3a4369" id="r_ga56adc3166c71f29d2d30efc6ed3a4369"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56adc3166c71f29d2d30efc6ed3a4369">ETH_MACCR_IFG_80Bit</a>   0x00040000U /* Minimum IFG between frames during transmission is 80Bit */</td></tr>
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<tr class="separator:ga56adc3166c71f29d2d30efc6ed3a4369"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2e77bc6fa5effe78706bfda4a51d1e2" id="r_gab2e77bc6fa5effe78706bfda4a51d1e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2e77bc6fa5effe78706bfda4a51d1e2">ETH_MACCR_IFG_72Bit</a>   0x00060000U /* Minimum IFG between frames during transmission is 72Bit */</td></tr>
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<tr class="separator:gab2e77bc6fa5effe78706bfda4a51d1e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga75c191358878ffd90ad6a6af336b935b" id="r_ga75c191358878ffd90ad6a6af336b935b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga75c191358878ffd90ad6a6af336b935b">ETH_MACCR_IFG_64Bit</a>   0x00080000U /* Minimum IFG between frames during transmission is 64Bit */</td></tr>
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<tr class="separator:ga75c191358878ffd90ad6a6af336b935b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebea1ff24623d7ba11f9eea98cd5466b" id="r_gaebea1ff24623d7ba11f9eea98cd5466b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebea1ff24623d7ba11f9eea98cd5466b">ETH_MACCR_IFG_56Bit</a>   0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */</td></tr>
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<tr class="separator:gaebea1ff24623d7ba11f9eea98cd5466b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8984fcb3cf6fb85c26878d9341324d77" id="r_ga8984fcb3cf6fb85c26878d9341324d77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8984fcb3cf6fb85c26878d9341324d77">ETH_MACCR_IFG_48Bit</a>   0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */</td></tr>
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<tr class="separator:ga8984fcb3cf6fb85c26878d9341324d77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bc414a4c1360538a9ccbea64009d581" id="r_ga1bc414a4c1360538a9ccbea64009d581"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bc414a4c1360538a9ccbea64009d581">ETH_MACCR_IFG_40Bit</a>   0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */</td></tr>
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<tr class="separator:ga1bc414a4c1360538a9ccbea64009d581"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga588e9336435c218354a75fc12f8bf612" id="r_ga588e9336435c218354a75fc12f8bf612"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga588e9336435c218354a75fc12f8bf612">ETH_MACCR_CSD_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gad18e8d3284ce4ec318027d9f3d8ca491" id="r_gad18e8d3284ce4ec318027d9f3d8ca491"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad18e8d3284ce4ec318027d9f3d8ca491">ETH_MACCR_CSD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga588e9336435c218354a75fc12f8bf612">ETH_MACCR_CSD_Pos</a>)</td></tr>
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<tr class="separator:gad18e8d3284ce4ec318027d9f3d8ca491"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad298d344663cc1213716b5981c61682c" id="r_gad298d344663cc1213716b5981c61682c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad298d344663cc1213716b5981c61682c">ETH_MACCR_CSD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad18e8d3284ce4ec318027d9f3d8ca491">ETH_MACCR_CSD_Msk</a> /* Carrier sense disable (during transmission) */</td></tr>
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<tr class="separator:gad298d344663cc1213716b5981c61682c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6147083b9250f2eb3364b02195fe737c" id="r_ga6147083b9250f2eb3364b02195fe737c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6147083b9250f2eb3364b02195fe737c">ETH_MACCR_FES_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga6147083b9250f2eb3364b02195fe737c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f5dd4cb0742fd13187a8c200bb1f041" id="r_ga9f5dd4cb0742fd13187a8c200bb1f041"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f5dd4cb0742fd13187a8c200bb1f041">ETH_MACCR_FES_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6147083b9250f2eb3364b02195fe737c">ETH_MACCR_FES_Pos</a>)</td></tr>
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<tr class="separator:ga9f5dd4cb0742fd13187a8c200bb1f041"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafaa2d12a706f5c166e1ed620ec53177c" id="r_gafaa2d12a706f5c166e1ed620ec53177c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafaa2d12a706f5c166e1ed620ec53177c">ETH_MACCR_FES</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f5dd4cb0742fd13187a8c200bb1f041">ETH_MACCR_FES_Msk</a> /* Fast ethernet speed */</td></tr>
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<tr class="separator:gafaa2d12a706f5c166e1ed620ec53177c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4bbbcddaca5d36eea8da9241ece9bc03" id="r_ga4bbbcddaca5d36eea8da9241ece9bc03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bbbcddaca5d36eea8da9241ece9bc03">ETH_MACCR_ROD_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga4bbbcddaca5d36eea8da9241ece9bc03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7217c59c6e0a4c0fa327e7f5b40a435b" id="r_ga7217c59c6e0a4c0fa327e7f5b40a435b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7217c59c6e0a4c0fa327e7f5b40a435b">ETH_MACCR_ROD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4bbbcddaca5d36eea8da9241ece9bc03">ETH_MACCR_ROD_Pos</a>)</td></tr>
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<tr class="separator:ga7217c59c6e0a4c0fa327e7f5b40a435b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13f0065edda127d3f1fb6e88ca6f465b" id="r_ga13f0065edda127d3f1fb6e88ca6f465b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13f0065edda127d3f1fb6e88ca6f465b">ETH_MACCR_ROD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7217c59c6e0a4c0fa327e7f5b40a435b">ETH_MACCR_ROD_Msk</a> /* Receive own disable */</td></tr>
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<tr class="separator:ga13f0065edda127d3f1fb6e88ca6f465b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59f9e595778a163299e230ac6fe01b07" id="r_ga59f9e595778a163299e230ac6fe01b07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59f9e595778a163299e230ac6fe01b07">ETH_MACCR_LM_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga59f9e595778a163299e230ac6fe01b07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8a68cc960648c12120c8b374bdd8716" id="r_gaf8a68cc960648c12120c8b374bdd8716"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8a68cc960648c12120c8b374bdd8716">ETH_MACCR_LM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga59f9e595778a163299e230ac6fe01b07">ETH_MACCR_LM_Pos</a>)</td></tr>
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<tr class="separator:gaf8a68cc960648c12120c8b374bdd8716"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38ad823b7d50c85fc620a9a93d250d54" id="r_ga38ad823b7d50c85fc620a9a93d250d54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38ad823b7d50c85fc620a9a93d250d54">ETH_MACCR_LM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8a68cc960648c12120c8b374bdd8716">ETH_MACCR_LM_Msk</a> /* loopback mode */</td></tr>
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<tr class="separator:ga38ad823b7d50c85fc620a9a93d250d54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3fb4a84c106fe35457d37c5b64c3329" id="r_gaf3fb4a84c106fe35457d37c5b64c3329"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3fb4a84c106fe35457d37c5b64c3329">ETH_MACCR_DM_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaf3fb4a84c106fe35457d37c5b64c3329"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36a3d885827efdd8dff930201dfee8cb" id="r_ga36a3d885827efdd8dff930201dfee8cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36a3d885827efdd8dff930201dfee8cb">ETH_MACCR_DM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3fb4a84c106fe35457d37c5b64c3329">ETH_MACCR_DM_Pos</a>)</td></tr>
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<tr class="separator:ga36a3d885827efdd8dff930201dfee8cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83e463b0497de6801773acd7984722b2" id="r_ga83e463b0497de6801773acd7984722b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83e463b0497de6801773acd7984722b2">ETH_MACCR_DM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36a3d885827efdd8dff930201dfee8cb">ETH_MACCR_DM_Msk</a> /* Duplex mode */</td></tr>
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<tr class="separator:ga83e463b0497de6801773acd7984722b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2debc54904a0cd2e8075c18b06b04607" id="r_ga2debc54904a0cd2e8075c18b06b04607"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2debc54904a0cd2e8075c18b06b04607">ETH_MACCR_IPCO_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga2debc54904a0cd2e8075c18b06b04607"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8366318e6b656e2f84664b29cf67d4f5" id="r_ga8366318e6b656e2f84664b29cf67d4f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8366318e6b656e2f84664b29cf67d4f5">ETH_MACCR_IPCO_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2debc54904a0cd2e8075c18b06b04607">ETH_MACCR_IPCO_Pos</a>)</td></tr>
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<tr class="separator:ga8366318e6b656e2f84664b29cf67d4f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbd6f6975a04c0ded0e1a9e98035e802" id="r_gadbd6f6975a04c0ded0e1a9e98035e802"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbd6f6975a04c0ded0e1a9e98035e802">ETH_MACCR_IPCO</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8366318e6b656e2f84664b29cf67d4f5">ETH_MACCR_IPCO_Msk</a> /* IP Checksum offload */</td></tr>
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<tr class="memitem:gab08db3705923934f19f57878b6aee621" id="r_gab08db3705923934f19f57878b6aee621"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab08db3705923934f19f57878b6aee621">ETH_MACCR_RD_Pos</a>   (9U)</td></tr>
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<tr class="separator:gab08db3705923934f19f57878b6aee621"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab35d6a69246d8b8e0df616af385338d8" id="r_gab35d6a69246d8b8e0df616af385338d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab35d6a69246d8b8e0df616af385338d8">ETH_MACCR_RD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab08db3705923934f19f57878b6aee621">ETH_MACCR_RD_Pos</a>)</td></tr>
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<tr class="separator:gab35d6a69246d8b8e0df616af385338d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2771077782e2dcac94367e54353696e" id="r_gad2771077782e2dcac94367e54353696e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2771077782e2dcac94367e54353696e">ETH_MACCR_RD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab35d6a69246d8b8e0df616af385338d8">ETH_MACCR_RD_Msk</a> /* Retry disable */</td></tr>
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<tr class="separator:gad2771077782e2dcac94367e54353696e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf11af5805335ea5bf4a581746770169" id="r_gadf11af5805335ea5bf4a581746770169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf11af5805335ea5bf4a581746770169">ETH_MACCR_APCS_Pos</a>   (7U)</td></tr>
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<tr class="separator:gadf11af5805335ea5bf4a581746770169"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64b76db821d5aacb94dd0ad98b9343b1" id="r_ga64b76db821d5aacb94dd0ad98b9343b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64b76db821d5aacb94dd0ad98b9343b1">ETH_MACCR_APCS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf11af5805335ea5bf4a581746770169">ETH_MACCR_APCS_Pos</a>)</td></tr>
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<tr class="separator:ga64b76db821d5aacb94dd0ad98b9343b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b5d2fe7260609d8186a7005f925dc28" id="r_ga0b5d2fe7260609d8186a7005f925dc28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b5d2fe7260609d8186a7005f925dc28">ETH_MACCR_APCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga64b76db821d5aacb94dd0ad98b9343b1">ETH_MACCR_APCS_Msk</a> /* Automatic Pad/<a class="el" href="group___peripheral__declaration.html#ga4381bb54c2dbc34500521165aa7b89b1">CRC</a> stripping */</td></tr>
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<tr class="separator:ga0b5d2fe7260609d8186a7005f925dc28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14f95db9a825ce4e8f6cd28c5451bad3" id="r_ga14f95db9a825ce4e8f6cd28c5451bad3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14f95db9a825ce4e8f6cd28c5451bad3">ETH_MACCR_BL_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga14f95db9a825ce4e8f6cd28c5451bad3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ec3ac5f3f2541425180e8a899d3501f" id="r_ga1ec3ac5f3f2541425180e8a899d3501f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ec3ac5f3f2541425180e8a899d3501f">ETH_MACCR_BL_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga14f95db9a825ce4e8f6cd28c5451bad3">ETH_MACCR_BL_Pos</a>)</td></tr>
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<tr class="separator:ga1ec3ac5f3f2541425180e8a899d3501f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0fab432a0d01c8c1786b3d48489c0f9" id="r_gaa0fab432a0d01c8c1786b3d48489c0f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0fab432a0d01c8c1786b3d48489c0f9">ETH_MACCR_BL</a></td></tr>
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<tr class="separator:gaa0fab432a0d01c8c1786b3d48489c0f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bc0bcf13d6a51de76a67299ba40561f" id="r_ga9bc0bcf13d6a51de76a67299ba40561f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bc0bcf13d6a51de76a67299ba40561f">ETH_MACCR_BL_10</a>   0x00000000U /* k = min (n, 10) */</td></tr>
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<tr class="separator:ga9bc0bcf13d6a51de76a67299ba40561f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga135a78ac267e35d598ed17aa776a1505" id="r_ga135a78ac267e35d598ed17aa776a1505"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga135a78ac267e35d598ed17aa776a1505">ETH_MACCR_BL_8</a>   0x00000020U /* k = min (n, 8) */</td></tr>
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<tr class="separator:ga135a78ac267e35d598ed17aa776a1505"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d5f35dc63a68792a4abfaf9d11a2feb" id="r_ga6d5f35dc63a68792a4abfaf9d11a2feb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d5f35dc63a68792a4abfaf9d11a2feb">ETH_MACCR_BL_4</a>   0x00000040U /* k = min (n, 4) */</td></tr>
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<tr class="separator:ga6d5f35dc63a68792a4abfaf9d11a2feb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf4db303c5f5822875770938f7cfb7c5" id="r_gacf4db303c5f5822875770938f7cfb7c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf4db303c5f5822875770938f7cfb7c5">ETH_MACCR_BL_1</a>   0x00000060U /* k = min (n, 1) */</td></tr>
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<tr class="separator:gacf4db303c5f5822875770938f7cfb7c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacec9ce3aee181fbc67675464bace4292" id="r_gacec9ce3aee181fbc67675464bace4292"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacec9ce3aee181fbc67675464bace4292">ETH_MACCR_DC_Pos</a>   (4U)</td></tr>
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<tr class="separator:gacec9ce3aee181fbc67675464bace4292"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga725e7bba118c5f2780295c555a3ba916" id="r_ga725e7bba118c5f2780295c555a3ba916"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga725e7bba118c5f2780295c555a3ba916">ETH_MACCR_DC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacec9ce3aee181fbc67675464bace4292">ETH_MACCR_DC_Pos</a>)</td></tr>
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<tr class="separator:ga725e7bba118c5f2780295c555a3ba916"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90347f47e9623d4714e0631b1afbccc9" id="r_ga90347f47e9623d4714e0631b1afbccc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90347f47e9623d4714e0631b1afbccc9">ETH_MACCR_DC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga725e7bba118c5f2780295c555a3ba916">ETH_MACCR_DC_Msk</a> /* Defferal check */</td></tr>
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<tr class="separator:ga90347f47e9623d4714e0631b1afbccc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad47f85fd08360f1244faff9cd913029c" id="r_gad47f85fd08360f1244faff9cd913029c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad47f85fd08360f1244faff9cd913029c">ETH_MACCR_TE_Pos</a>   (3U)</td></tr>
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<tr class="separator:gad47f85fd08360f1244faff9cd913029c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaddcad0319763dc5cdb282dda26a50634" id="r_gaddcad0319763dc5cdb282dda26a50634"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddcad0319763dc5cdb282dda26a50634">ETH_MACCR_TE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad47f85fd08360f1244faff9cd913029c">ETH_MACCR_TE_Pos</a>)</td></tr>
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<tr class="separator:gaddcad0319763dc5cdb282dda26a50634"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87c3818396ef51cad8be1f4c68fff164" id="r_ga87c3818396ef51cad8be1f4c68fff164"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87c3818396ef51cad8be1f4c68fff164">ETH_MACCR_TE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaddcad0319763dc5cdb282dda26a50634">ETH_MACCR_TE_Msk</a> /* Transmitter enable */</td></tr>
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<tr class="separator:ga87c3818396ef51cad8be1f4c68fff164"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8c13b3b7d19a9a11df6ae71c01de129" id="r_gac8c13b3b7d19a9a11df6ae71c01de129"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8c13b3b7d19a9a11df6ae71c01de129">ETH_MACCR_RE_Pos</a>   (2U)</td></tr>
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<tr class="separator:gac8c13b3b7d19a9a11df6ae71c01de129"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga074212b9bb2b4d5991e91277fdd6b18a" id="r_ga074212b9bb2b4d5991e91277fdd6b18a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga074212b9bb2b4d5991e91277fdd6b18a">ETH_MACCR_RE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac8c13b3b7d19a9a11df6ae71c01de129">ETH_MACCR_RE_Pos</a>)</td></tr>
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<tr class="separator:ga074212b9bb2b4d5991e91277fdd6b18a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77984e7a5202bdc300bccc9cc90fad3e" id="r_ga77984e7a5202bdc300bccc9cc90fad3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77984e7a5202bdc300bccc9cc90fad3e">ETH_MACCR_RE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga074212b9bb2b4d5991e91277fdd6b18a">ETH_MACCR_RE_Msk</a> /* Receiver enable */</td></tr>
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<tr class="separator:ga77984e7a5202bdc300bccc9cc90fad3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaaefa92c0f1afda53c779ae046f1bc8e" id="r_gaaaefa92c0f1afda53c779ae046f1bc8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaaefa92c0f1afda53c779ae046f1bc8e">ETH_MACFFR_RA_Pos</a>   (31U)</td></tr>
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<tr class="separator:gaaaefa92c0f1afda53c779ae046f1bc8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a98d8a880edf71d2b6fbf245adcbe4b" id="r_ga9a98d8a880edf71d2b6fbf245adcbe4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a98d8a880edf71d2b6fbf245adcbe4b">ETH_MACFFR_RA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaaefa92c0f1afda53c779ae046f1bc8e">ETH_MACFFR_RA_Pos</a>)</td></tr>
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<tr class="separator:ga9a98d8a880edf71d2b6fbf245adcbe4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7970ce2fd938029f0a58cf668a82a0fb" id="r_ga7970ce2fd938029f0a58cf668a82a0fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7970ce2fd938029f0a58cf668a82a0fb">ETH_MACFFR_RA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a98d8a880edf71d2b6fbf245adcbe4b">ETH_MACFFR_RA_Msk</a> /* Receive all */</td></tr>
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<tr class="separator:ga7970ce2fd938029f0a58cf668a82a0fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f40208cefa46427f9038e48add7d195" id="r_ga3f40208cefa46427f9038e48add7d195"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f40208cefa46427f9038e48add7d195">ETH_MACFFR_HPF_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga3f40208cefa46427f9038e48add7d195"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cb1611ef661179353862262e5685c53" id="r_ga7cb1611ef661179353862262e5685c53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cb1611ef661179353862262e5685c53">ETH_MACFFR_HPF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f40208cefa46427f9038e48add7d195">ETH_MACFFR_HPF_Pos</a>)</td></tr>
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<tr class="separator:ga7cb1611ef661179353862262e5685c53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b902b5561e392e47ce5d66275902e29" id="r_ga8b902b5561e392e47ce5d66275902e29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b902b5561e392e47ce5d66275902e29">ETH_MACFFR_HPF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cb1611ef661179353862262e5685c53">ETH_MACFFR_HPF_Msk</a> /* Hash or perfect filter */</td></tr>
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<tr class="separator:ga8b902b5561e392e47ce5d66275902e29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa74c10f8950aa00a4ecab37d9fecac9" id="r_gafa74c10f8950aa00a4ecab37d9fecac9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa74c10f8950aa00a4ecab37d9fecac9">ETH_MACFFR_SAF_Pos</a>   (9U)</td></tr>
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<tr class="separator:gafa74c10f8950aa00a4ecab37d9fecac9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3aad930295c276453e51c416902b52cc" id="r_ga3aad930295c276453e51c416902b52cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3aad930295c276453e51c416902b52cc">ETH_MACFFR_SAF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafa74c10f8950aa00a4ecab37d9fecac9">ETH_MACFFR_SAF_Pos</a>)</td></tr>
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<tr class="separator:ga3aad930295c276453e51c416902b52cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e710eda13cca42c8da46d5d37f34552" id="r_ga1e710eda13cca42c8da46d5d37f34552"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e710eda13cca42c8da46d5d37f34552">ETH_MACFFR_SAF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3aad930295c276453e51c416902b52cc">ETH_MACFFR_SAF_Msk</a> /* Source address filter enable */</td></tr>
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<tr class="separator:ga1e710eda13cca42c8da46d5d37f34552"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga848f235f8e37e0293fc51aaa8b8b642e" id="r_ga848f235f8e37e0293fc51aaa8b8b642e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga848f235f8e37e0293fc51aaa8b8b642e">ETH_MACFFR_SAIF_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga848f235f8e37e0293fc51aaa8b8b642e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabfa7482e8b8e0d949875ed2e94f3b5f7" id="r_gabfa7482e8b8e0d949875ed2e94f3b5f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfa7482e8b8e0d949875ed2e94f3b5f7">ETH_MACFFR_SAIF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga848f235f8e37e0293fc51aaa8b8b642e">ETH_MACFFR_SAIF_Pos</a>)</td></tr>
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<tr class="separator:gabfa7482e8b8e0d949875ed2e94f3b5f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa351de2818df9599ce6b3378ca31f87" id="r_gaaa351de2818df9599ce6b3378ca31f87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa351de2818df9599ce6b3378ca31f87">ETH_MACFFR_SAIF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabfa7482e8b8e0d949875ed2e94f3b5f7">ETH_MACFFR_SAIF_Msk</a> /* SA inverse filtering */</td></tr>
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<tr class="separator:gaaa351de2818df9599ce6b3378ca31f87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf59b0fd52b7f31dd5fa99ed3e0db1f24" id="r_gaf59b0fd52b7f31dd5fa99ed3e0db1f24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf59b0fd52b7f31dd5fa99ed3e0db1f24">ETH_MACFFR_PCF_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaf59b0fd52b7f31dd5fa99ed3e0db1f24"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga066564941ff14e4ee4110870be454835" id="r_ga066564941ff14e4ee4110870be454835"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga066564941ff14e4ee4110870be454835">ETH_MACFFR_PCF_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf59b0fd52b7f31dd5fa99ed3e0db1f24">ETH_MACFFR_PCF_Pos</a>)</td></tr>
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<tr class="separator:ga066564941ff14e4ee4110870be454835"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25724ed070e5948cb5541d890d2af603" id="r_ga25724ed070e5948cb5541d890d2af603"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25724ed070e5948cb5541d890d2af603">ETH_MACFFR_PCF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga066564941ff14e4ee4110870be454835">ETH_MACFFR_PCF_Msk</a> /* Pass control frames: 3 cases */</td></tr>
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<tr class="separator:ga25724ed070e5948cb5541d890d2af603"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafae24adcc21beedcf4d3668b07d9211d" id="r_gafae24adcc21beedcf4d3668b07d9211d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafae24adcc21beedcf4d3668b07d9211d">ETH_MACFFR_PCF_BlockAll_Pos</a>   (6U)</td></tr>
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<tr class="separator:gafae24adcc21beedcf4d3668b07d9211d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5382075fb7e487b0c2a1a97f0c1d0276" id="r_ga5382075fb7e487b0c2a1a97f0c1d0276"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5382075fb7e487b0c2a1a97f0c1d0276">ETH_MACFFR_PCF_BlockAll_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafae24adcc21beedcf4d3668b07d9211d">ETH_MACFFR_PCF_BlockAll_Pos</a>)</td></tr>
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<tr class="separator:ga5382075fb7e487b0c2a1a97f0c1d0276"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9bcec681af42037508574944fe68d6ff" id="r_ga9bcec681af42037508574944fe68d6ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bcec681af42037508574944fe68d6ff">ETH_MACFFR_PCF_BlockAll</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5382075fb7e487b0c2a1a97f0c1d0276">ETH_MACFFR_PCF_BlockAll_Msk</a> /* MAC filters all control frames from reaching the application */</td></tr>
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<tr class="separator:ga9bcec681af42037508574944fe68d6ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9495c05d01a26d63e6c87461d5440410" id="r_ga9495c05d01a26d63e6c87461d5440410"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9495c05d01a26d63e6c87461d5440410">ETH_MACFFR_PCF_ForwardAll_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga9495c05d01a26d63e6c87461d5440410"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga600b088ad4e2326651b1b8d066a85a0c" id="r_ga600b088ad4e2326651b1b8d066a85a0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga600b088ad4e2326651b1b8d066a85a0c">ETH_MACFFR_PCF_ForwardAll_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9495c05d01a26d63e6c87461d5440410">ETH_MACFFR_PCF_ForwardAll_Pos</a>)</td></tr>
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<tr class="separator:ga600b088ad4e2326651b1b8d066a85a0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf694466716e26c52452e21ce2a76f2fe" id="r_gaf694466716e26c52452e21ce2a76f2fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf694466716e26c52452e21ce2a76f2fe">ETH_MACFFR_PCF_ForwardAll</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga600b088ad4e2326651b1b8d066a85a0c">ETH_MACFFR_PCF_ForwardAll_Msk</a> /* MAC forwards all control frames to application even if they fail the Address Filter */</td></tr>
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<tr class="separator:gaf694466716e26c52452e21ce2a76f2fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae90264da6a4c411fc2de7ed84c21de1b" id="r_gae90264da6a4c411fc2de7ed84c21de1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae90264da6a4c411fc2de7ed84c21de1b">ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos</a>   (6U)</td></tr>
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<tr class="separator:gae90264da6a4c411fc2de7ed84c21de1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85f6303d1d492b59bb26034343e3a4df" id="r_ga85f6303d1d492b59bb26034343e3a4df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85f6303d1d492b59bb26034343e3a4df">ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae90264da6a4c411fc2de7ed84c21de1b">ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos</a>)</td></tr>
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<tr class="separator:ga85f6303d1d492b59bb26034343e3a4df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3e83e62d864be50e58455719d6df217" id="r_gaa3e83e62d864be50e58455719d6df217"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3e83e62d864be50e58455719d6df217">ETH_MACFFR_PCF_ForwardPassedAddrFilter</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga85f6303d1d492b59bb26034343e3a4df">ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk</a> /* MAC forwards control frames that pass the Address Filter. */</td></tr>
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<tr class="separator:gaa3e83e62d864be50e58455719d6df217"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac8a275e8b823431da6aa47d36271ce5" id="r_gaac8a275e8b823431da6aa47d36271ce5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac8a275e8b823431da6aa47d36271ce5">ETH_MACFFR_BFD_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaac8a275e8b823431da6aa47d36271ce5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb4108d0862a690e04665be0fc04412d" id="r_gacb4108d0862a690e04665be0fc04412d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb4108d0862a690e04665be0fc04412d">ETH_MACFFR_BFD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaac8a275e8b823431da6aa47d36271ce5">ETH_MACFFR_BFD_Pos</a>)</td></tr>
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<tr class="separator:gacb4108d0862a690e04665be0fc04412d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fea3f3e6b264e362a84675e09f33cbd" id="r_ga8fea3f3e6b264e362a84675e09f33cbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fea3f3e6b264e362a84675e09f33cbd">ETH_MACFFR_BFD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacb4108d0862a690e04665be0fc04412d">ETH_MACFFR_BFD_Msk</a> /* Broadcast frame disable */</td></tr>
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<tr class="separator:ga8fea3f3e6b264e362a84675e09f33cbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2a5d3a1ce969272150c55c2a0f66143" id="r_gaa2a5d3a1ce969272150c55c2a0f66143"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a5d3a1ce969272150c55c2a0f66143">ETH_MACFFR_PAM_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaa2a5d3a1ce969272150c55c2a0f66143"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga118b021e83c7e4ba113c17eca935e538" id="r_ga118b021e83c7e4ba113c17eca935e538"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga118b021e83c7e4ba113c17eca935e538">ETH_MACFFR_PAM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a5d3a1ce969272150c55c2a0f66143">ETH_MACFFR_PAM_Pos</a>)</td></tr>
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<tr class="separator:ga118b021e83c7e4ba113c17eca935e538"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaafaa7da9e50e9ecf39bdc614c01bc22e" id="r_gaafaa7da9e50e9ecf39bdc614c01bc22e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafaa7da9e50e9ecf39bdc614c01bc22e">ETH_MACFFR_PAM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga118b021e83c7e4ba113c17eca935e538">ETH_MACFFR_PAM_Msk</a> /* Pass all mutlicast */</td></tr>
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<tr class="separator:gaafaa7da9e50e9ecf39bdc614c01bc22e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5a60d5a987a14e474d8782af855e6f5" id="r_gab5a60d5a987a14e474d8782af855e6f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5a60d5a987a14e474d8782af855e6f5">ETH_MACFFR_DAIF_Pos</a>   (3U)</td></tr>
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<tr class="separator:gab5a60d5a987a14e474d8782af855e6f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c15d55d7f391f42bd8751d76da28480" id="r_ga3c15d55d7f391f42bd8751d76da28480"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c15d55d7f391f42bd8751d76da28480">ETH_MACFFR_DAIF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab5a60d5a987a14e474d8782af855e6f5">ETH_MACFFR_DAIF_Pos</a>)</td></tr>
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<tr class="separator:ga3c15d55d7f391f42bd8751d76da28480"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f50c885917d6df63e6250a530a9ce0c" id="r_ga7f50c885917d6df63e6250a530a9ce0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f50c885917d6df63e6250a530a9ce0c">ETH_MACFFR_DAIF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c15d55d7f391f42bd8751d76da28480">ETH_MACFFR_DAIF_Msk</a> /* DA Inverse filtering */</td></tr>
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<tr class="separator:ga7f50c885917d6df63e6250a530a9ce0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cdf71d283afa6f77ce261fe5e197b92" id="r_ga0cdf71d283afa6f77ce261fe5e197b92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cdf71d283afa6f77ce261fe5e197b92">ETH_MACFFR_HM_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga0cdf71d283afa6f77ce261fe5e197b92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3c33afcbb8d2ae59624915dc1bd2620" id="r_gab3c33afcbb8d2ae59624915dc1bd2620"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3c33afcbb8d2ae59624915dc1bd2620">ETH_MACFFR_HM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cdf71d283afa6f77ce261fe5e197b92">ETH_MACFFR_HM_Pos</a>)</td></tr>
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<tr class="separator:gab3c33afcbb8d2ae59624915dc1bd2620"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaab1e7a61949844d578d7580b9d2c143" id="r_gaaab1e7a61949844d578d7580b9d2c143"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaab1e7a61949844d578d7580b9d2c143">ETH_MACFFR_HM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab3c33afcbb8d2ae59624915dc1bd2620">ETH_MACFFR_HM_Msk</a> /* Hash multicast */</td></tr>
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<tr class="separator:gaaab1e7a61949844d578d7580b9d2c143"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4087aca0085083cb8f5ce7a5842f42dc" id="r_ga4087aca0085083cb8f5ce7a5842f42dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4087aca0085083cb8f5ce7a5842f42dc">ETH_MACFFR_HU_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga4087aca0085083cb8f5ce7a5842f42dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d738065b86ca7845927a39e9b06846a" id="r_ga9d738065b86ca7845927a39e9b06846a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d738065b86ca7845927a39e9b06846a">ETH_MACFFR_HU_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4087aca0085083cb8f5ce7a5842f42dc">ETH_MACFFR_HU_Pos</a>)</td></tr>
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<tr class="separator:ga9d738065b86ca7845927a39e9b06846a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d925e8aa55a6b07772f86abce601529" id="r_ga6d925e8aa55a6b07772f86abce601529"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d925e8aa55a6b07772f86abce601529">ETH_MACFFR_HU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d738065b86ca7845927a39e9b06846a">ETH_MACFFR_HU_Msk</a> /* Hash unicast */</td></tr>
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<tr class="separator:ga6d925e8aa55a6b07772f86abce601529"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3bf7fe779fc85379362777f881c8a2c" id="r_gab3bf7fe779fc85379362777f881c8a2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3bf7fe779fc85379362777f881c8a2c">ETH_MACFFR_PM_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab3bf7fe779fc85379362777f881c8a2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46fc57cc116b06aab750055588f841de" id="r_ga46fc57cc116b06aab750055588f841de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46fc57cc116b06aab750055588f841de">ETH_MACFFR_PM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3bf7fe779fc85379362777f881c8a2c">ETH_MACFFR_PM_Pos</a>)</td></tr>
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<tr class="separator:ga46fc57cc116b06aab750055588f841de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga168f5e4a3eb11474c65396d75c07e086" id="r_ga168f5e4a3eb11474c65396d75c07e086"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga168f5e4a3eb11474c65396d75c07e086">ETH_MACFFR_PM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga46fc57cc116b06aab750055588f841de">ETH_MACFFR_PM_Msk</a> /* Promiscuous mode */</td></tr>
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<tr class="separator:ga168f5e4a3eb11474c65396d75c07e086"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef7a817f06b2aafafe6ff3210a3c41af" id="r_gaef7a817f06b2aafafe6ff3210a3c41af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef7a817f06b2aafafe6ff3210a3c41af">ETH_MACHTHR_HTH_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaef7a817f06b2aafafe6ff3210a3c41af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18191f472ac5fce293cc159e03ecf323" id="r_ga18191f472ac5fce293cc159e03ecf323"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18191f472ac5fce293cc159e03ecf323">ETH_MACHTHR_HTH_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef7a817f06b2aafafe6ff3210a3c41af">ETH_MACHTHR_HTH_Pos</a>)</td></tr>
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<tr class="memitem:gaee61bc9033449996ae9f8f701b3bae23" id="r_gaee61bc9033449996ae9f8f701b3bae23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee61bc9033449996ae9f8f701b3bae23">ETH_MACHTHR_HTH</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga18191f472ac5fce293cc159e03ecf323">ETH_MACHTHR_HTH_Msk</a> /* Hash table high */</td></tr>
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<tr class="memitem:ga1d7f015b0b97de99d91eee7ab01e5d5f" id="r_ga1d7f015b0b97de99d91eee7ab01e5d5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d7f015b0b97de99d91eee7ab01e5d5f">ETH_MACHTLR_HTL_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga263c1c48202e6c9c8ce639ef13a8ed85" id="r_ga263c1c48202e6c9c8ce639ef13a8ed85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga263c1c48202e6c9c8ce639ef13a8ed85">ETH_MACHTLR_HTL_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d7f015b0b97de99d91eee7ab01e5d5f">ETH_MACHTLR_HTL_Pos</a>)</td></tr>
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<tr class="separator:ga263c1c48202e6c9c8ce639ef13a8ed85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac90cb3090f29ee9e5e7d935e8a3f2340" id="r_gac90cb3090f29ee9e5e7d935e8a3f2340"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac90cb3090f29ee9e5e7d935e8a3f2340">ETH_MACHTLR_HTL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga263c1c48202e6c9c8ce639ef13a8ed85">ETH_MACHTLR_HTL_Msk</a> /* Hash table low */</td></tr>
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<tr class="separator:gac90cb3090f29ee9e5e7d935e8a3f2340"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf67cfdb4230e5d14ee041303582b91d" id="r_gacf67cfdb4230e5d14ee041303582b91d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacf67cfdb4230e5d14ee041303582b91d">ETH_MACMIIAR_PA_Pos</a>   (11U)</td></tr>
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<tr class="memitem:ga036280a2fcae9747caca79a59f15dbc7" id="r_ga036280a2fcae9747caca79a59f15dbc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga036280a2fcae9747caca79a59f15dbc7">ETH_MACMIIAR_PA_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacf67cfdb4230e5d14ee041303582b91d">ETH_MACMIIAR_PA_Pos</a>)</td></tr>
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<tr class="separator:ga036280a2fcae9747caca79a59f15dbc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga712f44a77db4edfaf961e469153e34a4" id="r_ga712f44a77db4edfaf961e469153e34a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga712f44a77db4edfaf961e469153e34a4">ETH_MACMIIAR_PA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga036280a2fcae9747caca79a59f15dbc7">ETH_MACMIIAR_PA_Msk</a> /* Physical layer address */</td></tr>
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<tr class="memitem:ga50e38f04aa760a4f72b6d012cfb34f71" id="r_ga50e38f04aa760a4f72b6d012cfb34f71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50e38f04aa760a4f72b6d012cfb34f71">ETH_MACMIIAR_MR_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga50e38f04aa760a4f72b6d012cfb34f71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfed7f5d1d0cb6f84b6442a3afc24496" id="r_gacfed7f5d1d0cb6f84b6442a3afc24496"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfed7f5d1d0cb6f84b6442a3afc24496">ETH_MACMIIAR_MR_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga50e38f04aa760a4f72b6d012cfb34f71">ETH_MACMIIAR_MR_Pos</a>)</td></tr>
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<tr class="separator:gacfed7f5d1d0cb6f84b6442a3afc24496"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2ab5db007b55dca29e98ba3b31f7e66" id="r_gaa2ab5db007b55dca29e98ba3b31f7e66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2ab5db007b55dca29e98ba3b31f7e66">ETH_MACMIIAR_MR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacfed7f5d1d0cb6f84b6442a3afc24496">ETH_MACMIIAR_MR_Msk</a> /* MII register in the selected PHY */</td></tr>
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<tr class="separator:gaa2ab5db007b55dca29e98ba3b31f7e66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9498fb73edbb94c29ed6ccd963deef4e" id="r_ga9498fb73edbb94c29ed6ccd963deef4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9498fb73edbb94c29ed6ccd963deef4e">ETH_MACMIIAR_CR_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga2c7f3d710de7056d937f76f6f8329b83" id="r_ga2c7f3d710de7056d937f76f6f8329b83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c7f3d710de7056d937f76f6f8329b83">ETH_MACMIIAR_CR_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9498fb73edbb94c29ed6ccd963deef4e">ETH_MACMIIAR_CR_Pos</a>)</td></tr>
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<tr class="separator:ga2c7f3d710de7056d937f76f6f8329b83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0747e464ca8bb685ee34d28eb2677c40" id="r_ga0747e464ca8bb685ee34d28eb2677c40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0747e464ca8bb685ee34d28eb2677c40">ETH_MACMIIAR_CR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c7f3d710de7056d937f76f6f8329b83">ETH_MACMIIAR_CR_Msk</a> /* CR clock range: 6 cases */</td></tr>
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<tr class="memitem:ga1fc1c108e8e7faa35839b3f72b5570d7" id="r_ga1fc1c108e8e7faa35839b3f72b5570d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fc1c108e8e7faa35839b3f72b5570d7">ETH_MACMIIAR_CR_Div42</a>   0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */</td></tr>
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<tr class="memitem:gad42d271e9f8b028f4b77f9c6214f4b41" id="r_gad42d271e9f8b028f4b77f9c6214f4b41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad42d271e9f8b028f4b77f9c6214f4b41">ETH_MACMIIAR_CR_Div62_Pos</a>   (2U)</td></tr>
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<tr class="separator:gad42d271e9f8b028f4b77f9c6214f4b41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04311c7087462f41231e89b064c61015" id="r_ga04311c7087462f41231e89b064c61015"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04311c7087462f41231e89b064c61015">ETH_MACMIIAR_CR_Div62_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad42d271e9f8b028f4b77f9c6214f4b41">ETH_MACMIIAR_CR_Div62_Pos</a>)</td></tr>
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<tr class="separator:ga04311c7087462f41231e89b064c61015"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0002142eea07988f854915782bd691c9" id="r_ga0002142eea07988f854915782bd691c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0002142eea07988f854915782bd691c9">ETH_MACMIIAR_CR_Div62</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga04311c7087462f41231e89b064c61015">ETH_MACMIIAR_CR_Div62_Msk</a> /* HCLK:100-150 MHz; MDC clock= HCLK/62 */</td></tr>
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<tr class="memitem:gad97d20a7f5815f99bcb920d3be101deb" id="r_gad97d20a7f5815f99bcb920d3be101deb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad97d20a7f5815f99bcb920d3be101deb">ETH_MACMIIAR_CR_Div16_Pos</a>   (3U)</td></tr>
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<tr class="separator:gad97d20a7f5815f99bcb920d3be101deb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9eab0313c19320fe59b933c3bd355b15" id="r_ga9eab0313c19320fe59b933c3bd355b15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9eab0313c19320fe59b933c3bd355b15">ETH_MACMIIAR_CR_Div16_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad97d20a7f5815f99bcb920d3be101deb">ETH_MACMIIAR_CR_Div16_Pos</a>)</td></tr>
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<tr class="separator:ga9eab0313c19320fe59b933c3bd355b15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49474ccdc05637adbc870989373c6535" id="r_ga49474ccdc05637adbc870989373c6535"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49474ccdc05637adbc870989373c6535">ETH_MACMIIAR_CR_Div16</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9eab0313c19320fe59b933c3bd355b15">ETH_MACMIIAR_CR_Div16_Msk</a> /* HCLK:20-35 MHz; MDC clock= HCLK/16 */</td></tr>
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<tr class="memitem:ga1425435b4fac9a8f965e73d490d9144a" id="r_ga1425435b4fac9a8f965e73d490d9144a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1425435b4fac9a8f965e73d490d9144a">ETH_MACMIIAR_CR_Div26_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga1425435b4fac9a8f965e73d490d9144a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a42460a599738bc6fe1acfa835e61c1" id="r_ga9a42460a599738bc6fe1acfa835e61c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a42460a599738bc6fe1acfa835e61c1">ETH_MACMIIAR_CR_Div26_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1425435b4fac9a8f965e73d490d9144a">ETH_MACMIIAR_CR_Div26_Pos</a>)</td></tr>
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<tr class="separator:ga9a42460a599738bc6fe1acfa835e61c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69a9da5dbeb77d96a729afc82d4f246d" id="r_ga69a9da5dbeb77d96a729afc82d4f246d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69a9da5dbeb77d96a729afc82d4f246d">ETH_MACMIIAR_CR_Div26</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9a42460a599738bc6fe1acfa835e61c1">ETH_MACMIIAR_CR_Div26_Msk</a> /* HCLK:35-60 MHz; MDC clock= HCLK/26 */</td></tr>
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<tr class="separator:ga69a9da5dbeb77d96a729afc82d4f246d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8b402724d0798147654bb6a1193146e" id="r_gab8b402724d0798147654bb6a1193146e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8b402724d0798147654bb6a1193146e">ETH_MACMIIAR_CR_Div102_Pos</a>   (4U)</td></tr>
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<tr class="separator:gab8b402724d0798147654bb6a1193146e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56cbb5a10b42335d5355aab44552c33e" id="r_ga56cbb5a10b42335d5355aab44552c33e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56cbb5a10b42335d5355aab44552c33e">ETH_MACMIIAR_CR_Div102_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8b402724d0798147654bb6a1193146e">ETH_MACMIIAR_CR_Div102_Pos</a>)</td></tr>
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<tr class="separator:ga56cbb5a10b42335d5355aab44552c33e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga372d485677cd2e3a995dab470abe66b8" id="r_ga372d485677cd2e3a995dab470abe66b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga372d485677cd2e3a995dab470abe66b8">ETH_MACMIIAR_CR_Div102</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga56cbb5a10b42335d5355aab44552c33e">ETH_MACMIIAR_CR_Div102_Msk</a> /* HCLK:150-168 MHz; MDC clock= HCLK/102 */</td></tr>
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<tr class="memitem:gad0697f8d40c21c9b0c3ad91652ab0be4" id="r_gad0697f8d40c21c9b0c3ad91652ab0be4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0697f8d40c21c9b0c3ad91652ab0be4">ETH_MACMIIAR_MW_Pos</a>   (1U)</td></tr>
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<tr class="separator:gad0697f8d40c21c9b0c3ad91652ab0be4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a13e637f5ae98bda497300e3f65f859" id="r_ga6a13e637f5ae98bda497300e3f65f859"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a13e637f5ae98bda497300e3f65f859">ETH_MACMIIAR_MW_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad0697f8d40c21c9b0c3ad91652ab0be4">ETH_MACMIIAR_MW_Pos</a>)</td></tr>
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<tr class="separator:ga6a13e637f5ae98bda497300e3f65f859"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffdb940b35822107a5959cdd1ab06482" id="r_gaffdb940b35822107a5959cdd1ab06482"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffdb940b35822107a5959cdd1ab06482">ETH_MACMIIAR_MW</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a13e637f5ae98bda497300e3f65f859">ETH_MACMIIAR_MW_Msk</a> /* MII write */</td></tr>
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<tr class="memitem:ga0bb3ef8fa6db10f02a9c54bc8d321fdd" id="r_ga0bb3ef8fa6db10f02a9c54bc8d321fdd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0bb3ef8fa6db10f02a9c54bc8d321fdd">ETH_MACMIIAR_MB_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0bb3ef8fa6db10f02a9c54bc8d321fdd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0973869be6711854cdbd8922973cad1f" id="r_ga0973869be6711854cdbd8922973cad1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0973869be6711854cdbd8922973cad1f">ETH_MACMIIAR_MB_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0bb3ef8fa6db10f02a9c54bc8d321fdd">ETH_MACMIIAR_MB_Pos</a>)</td></tr>
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<tr class="memitem:ga4e3bd36fdbb97a3ec5b541997bf952aa" id="r_ga4e3bd36fdbb97a3ec5b541997bf952aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e3bd36fdbb97a3ec5b541997bf952aa">ETH_MACMIIAR_MB</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0973869be6711854cdbd8922973cad1f">ETH_MACMIIAR_MB_Msk</a> /* MII busy */</td></tr>
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<tr class="separator:ga4e3bd36fdbb97a3ec5b541997bf952aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ce09ce27fe279dba841d64e3da3824a" id="r_ga0ce09ce27fe279dba841d64e3da3824a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ce09ce27fe279dba841d64e3da3824a">ETH_MACMIIDR_MD_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga553476638dac48c385faf4fcfef738a5" id="r_ga553476638dac48c385faf4fcfef738a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga553476638dac48c385faf4fcfef738a5">ETH_MACMIIDR_MD_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ce09ce27fe279dba841d64e3da3824a">ETH_MACMIIDR_MD_Pos</a>)</td></tr>
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<tr class="separator:ga553476638dac48c385faf4fcfef738a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c1226bcd1fc955b69191cd84c1ffe6e" id="r_ga0c1226bcd1fc955b69191cd84c1ffe6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c1226bcd1fc955b69191cd84c1ffe6e">ETH_MACMIIDR_MD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga553476638dac48c385faf4fcfef738a5">ETH_MACMIIDR_MD_Msk</a> /* MII data: read/write data from/to PHY */</td></tr>
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<tr class="separator:ga0c1226bcd1fc955b69191cd84c1ffe6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ae35995a0ce92670739ba359d77affc" id="r_ga5ae35995a0ce92670739ba359d77affc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ae35995a0ce92670739ba359d77affc">ETH_MACFCR_PT_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga5ae35995a0ce92670739ba359d77affc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ccbe0fdabaaf7f572a77e70af27b949" id="r_ga8ccbe0fdabaaf7f572a77e70af27b949"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ccbe0fdabaaf7f572a77e70af27b949">ETH_MACFCR_PT_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ae35995a0ce92670739ba359d77affc">ETH_MACFCR_PT_Pos</a>)</td></tr>
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<tr class="separator:ga8ccbe0fdabaaf7f572a77e70af27b949"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b3bc8574eee69d1bf01d5ab91644bbc" id="r_ga2b3bc8574eee69d1bf01d5ab91644bbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b3bc8574eee69d1bf01d5ab91644bbc">ETH_MACFCR_PT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ccbe0fdabaaf7f572a77e70af27b949">ETH_MACFCR_PT_Msk</a> /* Pause time */</td></tr>
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<tr class="separator:ga2b3bc8574eee69d1bf01d5ab91644bbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab33dfecfb2d574506516b81d6098bd9f" id="r_gab33dfecfb2d574506516b81d6098bd9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab33dfecfb2d574506516b81d6098bd9f">ETH_MACFCR_ZQPD_Pos</a>   (7U)</td></tr>
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<tr class="separator:gab33dfecfb2d574506516b81d6098bd9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e17d8c6daf50d922b16cff17da9eea6" id="r_ga2e17d8c6daf50d922b16cff17da9eea6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e17d8c6daf50d922b16cff17da9eea6">ETH_MACFCR_ZQPD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab33dfecfb2d574506516b81d6098bd9f">ETH_MACFCR_ZQPD_Pos</a>)</td></tr>
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<tr class="separator:ga2e17d8c6daf50d922b16cff17da9eea6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf34f51c72bc9733694ca11993cc384e1" id="r_gaf34f51c72bc9733694ca11993cc384e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf34f51c72bc9733694ca11993cc384e1">ETH_MACFCR_ZQPD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e17d8c6daf50d922b16cff17da9eea6">ETH_MACFCR_ZQPD_Msk</a> /* Zero-quanta pause disable */</td></tr>
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<tr class="separator:gaf34f51c72bc9733694ca11993cc384e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e9b2183e3ab25eaa732bc9cff1c1179" id="r_ga0e9b2183e3ab25eaa732bc9cff1c1179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e9b2183e3ab25eaa732bc9cff1c1179">ETH_MACFCR_PLT_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga0e9b2183e3ab25eaa732bc9cff1c1179"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebd5b76da52c58fd104576b7d2ff7edb" id="r_gaebd5b76da52c58fd104576b7d2ff7edb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebd5b76da52c58fd104576b7d2ff7edb">ETH_MACFCR_PLT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e9b2183e3ab25eaa732bc9cff1c1179">ETH_MACFCR_PLT_Pos</a>)</td></tr>
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<tr class="separator:gaebd5b76da52c58fd104576b7d2ff7edb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa299b14f248991ea740c352c2e2ec1e5" id="r_gaa299b14f248991ea740c352c2e2ec1e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa299b14f248991ea740c352c2e2ec1e5">ETH_MACFCR_PLT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaebd5b76da52c58fd104576b7d2ff7edb">ETH_MACFCR_PLT_Msk</a> /* Pause low threshold: 4 cases */</td></tr>
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<tr class="separator:gaa299b14f248991ea740c352c2e2ec1e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23d3e1992eec79fe65413ab67d3a3850" id="r_ga23d3e1992eec79fe65413ab67d3a3850"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23d3e1992eec79fe65413ab67d3a3850">ETH_MACFCR_PLT_Minus4</a>   0x00000000U /* Pause time minus 4 slot times */</td></tr>
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<tr class="separator:ga23d3e1992eec79fe65413ab67d3a3850"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0a1efb0a76dd9c1cb2b0cb4534e40d3" id="r_gad0a1efb0a76dd9c1cb2b0cb4534e40d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0a1efb0a76dd9c1cb2b0cb4534e40d3">ETH_MACFCR_PLT_Minus28_Pos</a>   (4U)</td></tr>
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<tr class="separator:gad0a1efb0a76dd9c1cb2b0cb4534e40d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43d3c34bc307b8592c4576e2e1f62a78" id="r_ga43d3c34bc307b8592c4576e2e1f62a78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43d3c34bc307b8592c4576e2e1f62a78">ETH_MACFCR_PLT_Minus28_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad0a1efb0a76dd9c1cb2b0cb4534e40d3">ETH_MACFCR_PLT_Minus28_Pos</a>)</td></tr>
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<tr class="separator:ga43d3c34bc307b8592c4576e2e1f62a78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga006139afdeadd79e8ead0233a202b3aa" id="r_ga006139afdeadd79e8ead0233a202b3aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga006139afdeadd79e8ead0233a202b3aa">ETH_MACFCR_PLT_Minus28</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga43d3c34bc307b8592c4576e2e1f62a78">ETH_MACFCR_PLT_Minus28_Msk</a> /* Pause time minus 28 slot times */</td></tr>
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<tr class="separator:ga006139afdeadd79e8ead0233a202b3aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9824db95c539fb9d35eb4f0c70c78f0" id="r_gae9824db95c539fb9d35eb4f0c70c78f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9824db95c539fb9d35eb4f0c70c78f0">ETH_MACFCR_PLT_Minus144_Pos</a>   (5U)</td></tr>
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<tr class="separator:gae9824db95c539fb9d35eb4f0c70c78f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9574c5ecc97413442222dbfcda0b50c" id="r_gad9574c5ecc97413442222dbfcda0b50c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9574c5ecc97413442222dbfcda0b50c">ETH_MACFCR_PLT_Minus144_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9824db95c539fb9d35eb4f0c70c78f0">ETH_MACFCR_PLT_Minus144_Pos</a>)</td></tr>
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<tr class="separator:gad9574c5ecc97413442222dbfcda0b50c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d71124fba7219f43938d8cc25ba4fad" id="r_ga2d71124fba7219f43938d8cc25ba4fad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d71124fba7219f43938d8cc25ba4fad">ETH_MACFCR_PLT_Minus144</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad9574c5ecc97413442222dbfcda0b50c">ETH_MACFCR_PLT_Minus144_Msk</a> /* Pause time minus 144 slot times */</td></tr>
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<tr class="separator:ga2d71124fba7219f43938d8cc25ba4fad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94bf0a9fd09b9e9354a2bf9360bdcd52" id="r_ga94bf0a9fd09b9e9354a2bf9360bdcd52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94bf0a9fd09b9e9354a2bf9360bdcd52">ETH_MACFCR_PLT_Minus256_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga94bf0a9fd09b9e9354a2bf9360bdcd52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74132d764aff9d748dcf05fb9b0216ec" id="r_ga74132d764aff9d748dcf05fb9b0216ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74132d764aff9d748dcf05fb9b0216ec">ETH_MACFCR_PLT_Minus256_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga94bf0a9fd09b9e9354a2bf9360bdcd52">ETH_MACFCR_PLT_Minus256_Pos</a>)</td></tr>
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<tr class="separator:ga74132d764aff9d748dcf05fb9b0216ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf55b57c1a06e060afd934e7883a6ebca" id="r_gaf55b57c1a06e060afd934e7883a6ebca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf55b57c1a06e060afd934e7883a6ebca">ETH_MACFCR_PLT_Minus256</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga74132d764aff9d748dcf05fb9b0216ec">ETH_MACFCR_PLT_Minus256_Msk</a> /* Pause time minus 256 slot times */</td></tr>
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<tr class="separator:gaf55b57c1a06e060afd934e7883a6ebca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ff0b3e85c3bf432dd589bdab6e76cde" id="r_ga7ff0b3e85c3bf432dd589bdab6e76cde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ff0b3e85c3bf432dd589bdab6e76cde">ETH_MACFCR_UPFD_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga7ff0b3e85c3bf432dd589bdab6e76cde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80f30740b5201a4a56e2b1a6db8fe48e" id="r_ga80f30740b5201a4a56e2b1a6db8fe48e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80f30740b5201a4a56e2b1a6db8fe48e">ETH_MACFCR_UPFD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ff0b3e85c3bf432dd589bdab6e76cde">ETH_MACFCR_UPFD_Pos</a>)</td></tr>
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<tr class="separator:ga80f30740b5201a4a56e2b1a6db8fe48e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50539e6dcdc828a70c91ab0cb0c1c27c" id="r_ga50539e6dcdc828a70c91ab0cb0c1c27c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50539e6dcdc828a70c91ab0cb0c1c27c">ETH_MACFCR_UPFD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga80f30740b5201a4a56e2b1a6db8fe48e">ETH_MACFCR_UPFD_Msk</a> /* Unicast pause frame detect */</td></tr>
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<tr class="separator:ga50539e6dcdc828a70c91ab0cb0c1c27c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0612f97275b019ca840796bdd79d11e2" id="r_ga0612f97275b019ca840796bdd79d11e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0612f97275b019ca840796bdd79d11e2">ETH_MACFCR_RFCE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga0612f97275b019ca840796bdd79d11e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga433c5ff49f74755a37c1311ddc075093" id="r_ga433c5ff49f74755a37c1311ddc075093"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga433c5ff49f74755a37c1311ddc075093">ETH_MACFCR_RFCE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0612f97275b019ca840796bdd79d11e2">ETH_MACFCR_RFCE_Pos</a>)</td></tr>
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<tr class="separator:ga433c5ff49f74755a37c1311ddc075093"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2eec52cb081cdba237e1195fe8c324b" id="r_gaf2eec52cb081cdba237e1195fe8c324b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2eec52cb081cdba237e1195fe8c324b">ETH_MACFCR_RFCE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga433c5ff49f74755a37c1311ddc075093">ETH_MACFCR_RFCE_Msk</a> /* Receive flow control enable */</td></tr>
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<tr class="separator:gaf2eec52cb081cdba237e1195fe8c324b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89cab918808d77c19851211503d77e13" id="r_ga89cab918808d77c19851211503d77e13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89cab918808d77c19851211503d77e13">ETH_MACFCR_TFCE_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga89cab918808d77c19851211503d77e13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b5da2d9c9ac891b2d281bf28683ca8d" id="r_ga4b5da2d9c9ac891b2d281bf28683ca8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b5da2d9c9ac891b2d281bf28683ca8d">ETH_MACFCR_TFCE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga89cab918808d77c19851211503d77e13">ETH_MACFCR_TFCE_Pos</a>)</td></tr>
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<tr class="separator:ga4b5da2d9c9ac891b2d281bf28683ca8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5cd88b7b637bef7a8022270ee02c64a" id="r_gaa5cd88b7b637bef7a8022270ee02c64a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5cd88b7b637bef7a8022270ee02c64a">ETH_MACFCR_TFCE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b5da2d9c9ac891b2d281bf28683ca8d">ETH_MACFCR_TFCE_Msk</a> /* Transmit flow control enable */</td></tr>
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<tr class="separator:gaa5cd88b7b637bef7a8022270ee02c64a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae98c96a63ef61268f22ba4abec8d811a" id="r_gae98c96a63ef61268f22ba4abec8d811a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae98c96a63ef61268f22ba4abec8d811a">ETH_MACFCR_FCBBPA_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gabceb72e4e65bfaa290be58922efdb336" id="r_gabceb72e4e65bfaa290be58922efdb336"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabceb72e4e65bfaa290be58922efdb336">ETH_MACFCR_FCBBPA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae98c96a63ef61268f22ba4abec8d811a">ETH_MACFCR_FCBBPA_Pos</a>)</td></tr>
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<tr class="memitem:ga7dccd98a15d90caf17bcaa6ae13d60a3" id="r_ga7dccd98a15d90caf17bcaa6ae13d60a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7dccd98a15d90caf17bcaa6ae13d60a3">ETH_MACFCR_FCBBPA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabceb72e4e65bfaa290be58922efdb336">ETH_MACFCR_FCBBPA_Msk</a> /* Flow control busy/backpressure activate */</td></tr>
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<tr class="memitem:ga425510877d0af2d2dca1daba3d77e4d9" id="r_ga425510877d0af2d2dca1daba3d77e4d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga425510877d0af2d2dca1daba3d77e4d9">ETH_MACVLANTR_VLANTC_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga74a0075909956532506d7a507c059ea7" id="r_ga74a0075909956532506d7a507c059ea7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74a0075909956532506d7a507c059ea7">ETH_MACVLANTR_VLANTC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga425510877d0af2d2dca1daba3d77e4d9">ETH_MACVLANTR_VLANTC_Pos</a>)</td></tr>
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<tr class="separator:ga74a0075909956532506d7a507c059ea7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd45480752cd22efecf0d7465bf49500" id="r_gabd45480752cd22efecf0d7465bf49500"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd45480752cd22efecf0d7465bf49500">ETH_MACVLANTR_VLANTC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga74a0075909956532506d7a507c059ea7">ETH_MACVLANTR_VLANTC_Msk</a> /* 12-bit VLAN tag comparison */</td></tr>
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<tr class="memitem:gac2584a4fa262f72e82d506a3c49c00ef" id="r_gac2584a4fa262f72e82d506a3c49c00ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2584a4fa262f72e82d506a3c49c00ef">ETH_MACVLANTR_VLANTI_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac2584a4fa262f72e82d506a3c49c00ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d9e35eaf745fa9f80be9a7a722031a7" id="r_ga2d9e35eaf745fa9f80be9a7a722031a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d9e35eaf745fa9f80be9a7a722031a7">ETH_MACVLANTR_VLANTI_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2584a4fa262f72e82d506a3c49c00ef">ETH_MACVLANTR_VLANTI_Pos</a>)</td></tr>
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<tr class="separator:ga2d9e35eaf745fa9f80be9a7a722031a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50874dc921fd523d84621a337aebc53d" id="r_ga50874dc921fd523d84621a337aebc53d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50874dc921fd523d84621a337aebc53d">ETH_MACVLANTR_VLANTI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d9e35eaf745fa9f80be9a7a722031a7">ETH_MACVLANTR_VLANTI_Msk</a> /* VLAN tag identifier (for receive frames) */</td></tr>
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<tr class="memitem:ga25fbbd599df79ba574b9915e17c91990" id="r_ga25fbbd599df79ba574b9915e17c91990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25fbbd599df79ba574b9915e17c91990">ETH_MACRWUFFR_D_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga25fbbd599df79ba574b9915e17c91990"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad54a741a972e56cb46f569b953895bc5" id="r_gad54a741a972e56cb46f569b953895bc5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad54a741a972e56cb46f569b953895bc5">ETH_MACRWUFFR_D_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25fbbd599df79ba574b9915e17c91990">ETH_MACRWUFFR_D_Pos</a>)</td></tr>
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<tr class="separator:gad54a741a972e56cb46f569b953895bc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae49a607f4dc4ba71c695b3aa2fc0968" id="r_gaae49a607f4dc4ba71c695b3aa2fc0968"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae49a607f4dc4ba71c695b3aa2fc0968">ETH_MACRWUFFR_D</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad54a741a972e56cb46f569b953895bc5">ETH_MACRWUFFR_D_Msk</a> /* Wake-up frame filter register data */</td></tr>
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<tr class="separator:gaae49a607f4dc4ba71c695b3aa2fc0968"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb526c7632b5374dce52fa2beb80a038" id="r_gabb526c7632b5374dce52fa2beb80a038"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb526c7632b5374dce52fa2beb80a038">ETH_MACPMTCSR_WFFRPR_Pos</a>   (31U)</td></tr>
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<tr class="separator:gabb526c7632b5374dce52fa2beb80a038"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6fae91e3c9a395769622d32cff6427b3" id="r_ga6fae91e3c9a395769622d32cff6427b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fae91e3c9a395769622d32cff6427b3">ETH_MACPMTCSR_WFFRPR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb526c7632b5374dce52fa2beb80a038">ETH_MACPMTCSR_WFFRPR_Pos</a>)</td></tr>
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<tr class="separator:ga6fae91e3c9a395769622d32cff6427b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeaa7046c581aa1b663c819352930cdd8" id="r_gaeaa7046c581aa1b663c819352930cdd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeaa7046c581aa1b663c819352930cdd8">ETH_MACPMTCSR_WFFRPR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6fae91e3c9a395769622d32cff6427b3">ETH_MACPMTCSR_WFFRPR_Msk</a> /* Wake-Up Frame Filter Register Pointer Reset */</td></tr>
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<tr class="memitem:ga7877c7a6a9ed93454098e79a9a2a6281" id="r_ga7877c7a6a9ed93454098e79a9a2a6281"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7877c7a6a9ed93454098e79a9a2a6281">ETH_MACPMTCSR_GU_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga7877c7a6a9ed93454098e79a9a2a6281"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f845ccfd867098d3ec25775040a5c8f" id="r_ga2f845ccfd867098d3ec25775040a5c8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f845ccfd867098d3ec25775040a5c8f">ETH_MACPMTCSR_GU_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7877c7a6a9ed93454098e79a9a2a6281">ETH_MACPMTCSR_GU_Pos</a>)</td></tr>
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<tr class="separator:ga2f845ccfd867098d3ec25775040a5c8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c2d01faf67db27fb0b2cfeaf94242b4" id="r_ga3c2d01faf67db27fb0b2cfeaf94242b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c2d01faf67db27fb0b2cfeaf94242b4">ETH_MACPMTCSR_GU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f845ccfd867098d3ec25775040a5c8f">ETH_MACPMTCSR_GU_Msk</a> /* Global Unicast */</td></tr>
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<tr class="separator:ga3c2d01faf67db27fb0b2cfeaf94242b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadfbe013f1b1f93c7274e072c837709b1" id="r_gadfbe013f1b1f93c7274e072c837709b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfbe013f1b1f93c7274e072c837709b1">ETH_MACPMTCSR_WFR_Pos</a>   (6U)</td></tr>
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<tr class="separator:gadfbe013f1b1f93c7274e072c837709b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga832d4cc3d0951c965e6f515125842bc4" id="r_ga832d4cc3d0951c965e6f515125842bc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga832d4cc3d0951c965e6f515125842bc4">ETH_MACPMTCSR_WFR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadfbe013f1b1f93c7274e072c837709b1">ETH_MACPMTCSR_WFR_Pos</a>)</td></tr>
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<tr class="separator:ga832d4cc3d0951c965e6f515125842bc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga597abfcc1408cb51980fa7a594a6cf30" id="r_ga597abfcc1408cb51980fa7a594a6cf30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga597abfcc1408cb51980fa7a594a6cf30">ETH_MACPMTCSR_WFR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga832d4cc3d0951c965e6f515125842bc4">ETH_MACPMTCSR_WFR_Msk</a> /* Wake-Up Frame Received */</td></tr>
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<tr class="separator:ga597abfcc1408cb51980fa7a594a6cf30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf1514e6ea9fdddbbb6ce396bee1855a" id="r_gadf1514e6ea9fdddbbb6ce396bee1855a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf1514e6ea9fdddbbb6ce396bee1855a">ETH_MACPMTCSR_MPR_Pos</a>   (5U)</td></tr>
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<tr class="separator:gadf1514e6ea9fdddbbb6ce396bee1855a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae312b7c783a541e4dc026eef480398dd" id="r_gae312b7c783a541e4dc026eef480398dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae312b7c783a541e4dc026eef480398dd">ETH_MACPMTCSR_MPR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf1514e6ea9fdddbbb6ce396bee1855a">ETH_MACPMTCSR_MPR_Pos</a>)</td></tr>
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<tr class="separator:gae312b7c783a541e4dc026eef480398dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab855f00737fb7f828752e1353c3a1031" id="r_gab855f00737fb7f828752e1353c3a1031"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab855f00737fb7f828752e1353c3a1031">ETH_MACPMTCSR_MPR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae312b7c783a541e4dc026eef480398dd">ETH_MACPMTCSR_MPR_Msk</a> /* Magic Packet Received */</td></tr>
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<tr class="separator:gab855f00737fb7f828752e1353c3a1031"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23adb9148c3a9603d070458e5744df8a" id="r_ga23adb9148c3a9603d070458e5744df8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23adb9148c3a9603d070458e5744df8a">ETH_MACPMTCSR_WFE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga23adb9148c3a9603d070458e5744df8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4898617eb625181689fb6fbeace04705" id="r_ga4898617eb625181689fb6fbeace04705"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4898617eb625181689fb6fbeace04705">ETH_MACPMTCSR_WFE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga23adb9148c3a9603d070458e5744df8a">ETH_MACPMTCSR_WFE_Pos</a>)</td></tr>
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<tr class="separator:ga4898617eb625181689fb6fbeace04705"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga998f1f5665f94008e39dfabb489faf8e" id="r_ga998f1f5665f94008e39dfabb489faf8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga998f1f5665f94008e39dfabb489faf8e">ETH_MACPMTCSR_WFE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4898617eb625181689fb6fbeace04705">ETH_MACPMTCSR_WFE_Msk</a> /* Wake-Up Frame Enable */</td></tr>
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<tr class="separator:ga998f1f5665f94008e39dfabb489faf8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2df8ebbf70fa09790c85774e1f5e8e0" id="r_gab2df8ebbf70fa09790c85774e1f5e8e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2df8ebbf70fa09790c85774e1f5e8e0">ETH_MACPMTCSR_MPE_Pos</a>   (1U)</td></tr>
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<tr class="separator:gab2df8ebbf70fa09790c85774e1f5e8e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71fdad55986e5e2b672ea1de7feb542c" id="r_ga71fdad55986e5e2b672ea1de7feb542c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71fdad55986e5e2b672ea1de7feb542c">ETH_MACPMTCSR_MPE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab2df8ebbf70fa09790c85774e1f5e8e0">ETH_MACPMTCSR_MPE_Pos</a>)</td></tr>
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<tr class="separator:ga71fdad55986e5e2b672ea1de7feb542c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81540e67436a755a7692b32a33871f63" id="r_ga81540e67436a755a7692b32a33871f63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81540e67436a755a7692b32a33871f63">ETH_MACPMTCSR_MPE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71fdad55986e5e2b672ea1de7feb542c">ETH_MACPMTCSR_MPE_Msk</a> /* Magic Packet Enable */</td></tr>
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<tr class="separator:ga81540e67436a755a7692b32a33871f63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e7bfb3f7e9212baa158705c26c44498" id="r_ga0e7bfb3f7e9212baa158705c26c44498"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e7bfb3f7e9212baa158705c26c44498">ETH_MACPMTCSR_PD_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0e7bfb3f7e9212baa158705c26c44498"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeaa6826d4d3fd55295dadbc3c3c73873" id="r_gaeaa6826d4d3fd55295dadbc3c3c73873"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeaa6826d4d3fd55295dadbc3c3c73873">ETH_MACPMTCSR_PD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e7bfb3f7e9212baa158705c26c44498">ETH_MACPMTCSR_PD_Pos</a>)</td></tr>
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<tr class="separator:gaeaa6826d4d3fd55295dadbc3c3c73873"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab454be372dc141b6e515c4389cd18a12" id="r_gab454be372dc141b6e515c4389cd18a12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab454be372dc141b6e515c4389cd18a12">ETH_MACPMTCSR_PD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeaa6826d4d3fd55295dadbc3c3c73873">ETH_MACPMTCSR_PD_Msk</a> /* Power Down */</td></tr>
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<tr class="memitem:ga27fd32b963677065b181f32e16e04b7b" id="r_ga27fd32b963677065b181f32e16e04b7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27fd32b963677065b181f32e16e04b7b">ETH_MACDBGR_TFF_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga27fd32b963677065b181f32e16e04b7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5af5bce543dc0df3a800a2db110bbdc" id="r_gaf5af5bce543dc0df3a800a2db110bbdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5af5bce543dc0df3a800a2db110bbdc">ETH_MACDBGR_TFF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27fd32b963677065b181f32e16e04b7b">ETH_MACDBGR_TFF_Pos</a>)</td></tr>
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<tr class="separator:gaf5af5bce543dc0df3a800a2db110bbdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94103a8c53ce5eab030b42165dd6916b" id="r_ga94103a8c53ce5eab030b42165dd6916b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94103a8c53ce5eab030b42165dd6916b">ETH_MACDBGR_TFF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5af5bce543dc0df3a800a2db110bbdc">ETH_MACDBGR_TFF_Msk</a> /* Tx FIFO full */</td></tr>
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<tr class="separator:ga94103a8c53ce5eab030b42165dd6916b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67c688152c050956889165352ff65a16" id="r_ga67c688152c050956889165352ff65a16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67c688152c050956889165352ff65a16">ETH_MACDBGR_TFNE_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga67c688152c050956889165352ff65a16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga176073c87c07e195f0b2ca7868b3cde5" id="r_ga176073c87c07e195f0b2ca7868b3cde5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga176073c87c07e195f0b2ca7868b3cde5">ETH_MACDBGR_TFNE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67c688152c050956889165352ff65a16">ETH_MACDBGR_TFNE_Pos</a>)</td></tr>
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<tr class="separator:ga176073c87c07e195f0b2ca7868b3cde5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9dff0698db41111c7c99cb5973003d4" id="r_gad9dff0698db41111c7c99cb5973003d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9dff0698db41111c7c99cb5973003d4">ETH_MACDBGR_TFNE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga176073c87c07e195f0b2ca7868b3cde5">ETH_MACDBGR_TFNE_Msk</a> /* Tx FIFO not empty */</td></tr>
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<tr class="separator:gad9dff0698db41111c7c99cb5973003d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b16b33e92d14f1a2b12b8a86700fcf6" id="r_ga1b16b33e92d14f1a2b12b8a86700fcf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b16b33e92d14f1a2b12b8a86700fcf6">ETH_MACDBGR_TFWA_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga1b16b33e92d14f1a2b12b8a86700fcf6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b4ce9eaa80ad0cf60a5921737520507" id="r_ga0b4ce9eaa80ad0cf60a5921737520507"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b4ce9eaa80ad0cf60a5921737520507">ETH_MACDBGR_TFWA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b16b33e92d14f1a2b12b8a86700fcf6">ETH_MACDBGR_TFWA_Pos</a>)</td></tr>
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<tr class="separator:ga0b4ce9eaa80ad0cf60a5921737520507"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae53b57022944c49021787f52ed30117" id="r_gaae53b57022944c49021787f52ed30117"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae53b57022944c49021787f52ed30117">ETH_MACDBGR_TFWA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b4ce9eaa80ad0cf60a5921737520507">ETH_MACDBGR_TFWA_Msk</a> /* Tx FIFO write active */</td></tr>
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<tr class="separator:gaae53b57022944c49021787f52ed30117"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7473c49e7a89cbb1b0e3c9cf67980284" id="r_ga7473c49e7a89cbb1b0e3c9cf67980284"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7473c49e7a89cbb1b0e3c9cf67980284">ETH_MACDBGR_TFRS_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga7473c49e7a89cbb1b0e3c9cf67980284"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97cc364a7442339bcbed0ffde5486ef0" id="r_ga97cc364a7442339bcbed0ffde5486ef0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97cc364a7442339bcbed0ffde5486ef0">ETH_MACDBGR_TFRS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7473c49e7a89cbb1b0e3c9cf67980284">ETH_MACDBGR_TFRS_Pos</a>)</td></tr>
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<tr class="separator:ga97cc364a7442339bcbed0ffde5486ef0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga112165ea108b32a86b135583c29a2386" id="r_ga112165ea108b32a86b135583c29a2386"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga112165ea108b32a86b135583c29a2386">ETH_MACDBGR_TFRS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97cc364a7442339bcbed0ffde5486ef0">ETH_MACDBGR_TFRS_Msk</a> /* Tx FIFO read <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> mask */</td></tr>
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<tr class="separator:ga112165ea108b32a86b135583c29a2386"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa14782f524bd2b25ed567532e80f4fcf" id="r_gaa14782f524bd2b25ed567532e80f4fcf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa14782f524bd2b25ed567532e80f4fcf">ETH_MACDBGR_TFRS_WRITING_Pos</a>   (20U)</td></tr>
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<tr class="separator:gaa14782f524bd2b25ed567532e80f4fcf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6fd97c33d20badcf4ec3cbafda38ddb3" id="r_ga6fd97c33d20badcf4ec3cbafda38ddb3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6fd97c33d20badcf4ec3cbafda38ddb3">ETH_MACDBGR_TFRS_WRITING_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa14782f524bd2b25ed567532e80f4fcf">ETH_MACDBGR_TFRS_WRITING_Pos</a>)</td></tr>
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<tr class="separator:ga6fd97c33d20badcf4ec3cbafda38ddb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4902aaee652f847dd0494a87189fb275" id="r_ga4902aaee652f847dd0494a87189fb275"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4902aaee652f847dd0494a87189fb275">ETH_MACDBGR_TFRS_WRITING</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6fd97c33d20badcf4ec3cbafda38ddb3">ETH_MACDBGR_TFRS_WRITING_Msk</a> /* Writing the received TxStatus or flushing the TxFIFO */</td></tr>
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<tr class="separator:ga4902aaee652f847dd0494a87189fb275"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b3f3b4224569efda1658e0d8f0468bd" id="r_ga4b3f3b4224569efda1658e0d8f0468bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b3f3b4224569efda1658e0d8f0468bd">ETH_MACDBGR_TFRS_WAITING_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga4b3f3b4224569efda1658e0d8f0468bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga745c2d38c8863ffb583471feb51c5a91" id="r_ga745c2d38c8863ffb583471feb51c5a91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga745c2d38c8863ffb583471feb51c5a91">ETH_MACDBGR_TFRS_WAITING_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b3f3b4224569efda1658e0d8f0468bd">ETH_MACDBGR_TFRS_WAITING_Pos</a>)</td></tr>
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<tr class="separator:ga745c2d38c8863ffb583471feb51c5a91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b223d1c05a8e1503daa10e0f27f514d" id="r_ga4b223d1c05a8e1503daa10e0f27f514d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b223d1c05a8e1503daa10e0f27f514d">ETH_MACDBGR_TFRS_WAITING</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga745c2d38c8863ffb583471feb51c5a91">ETH_MACDBGR_TFRS_WAITING_Msk</a> /* Waiting for TxStatus from MAC transmitter */</td></tr>
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<tr class="separator:ga4b223d1c05a8e1503daa10e0f27f514d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9d9294176f211cb62aef1e622cf8052" id="r_gad9d9294176f211cb62aef1e622cf8052"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9d9294176f211cb62aef1e622cf8052">ETH_MACDBGR_TFRS_READ_Pos</a>   (20U)</td></tr>
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<tr class="separator:gad9d9294176f211cb62aef1e622cf8052"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21675a956d16a5aeac36b390b2bceb72" id="r_ga21675a956d16a5aeac36b390b2bceb72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21675a956d16a5aeac36b390b2bceb72">ETH_MACDBGR_TFRS_READ_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9d9294176f211cb62aef1e622cf8052">ETH_MACDBGR_TFRS_READ_Pos</a>)</td></tr>
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<tr class="separator:ga21675a956d16a5aeac36b390b2bceb72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga520c63ccb534f4fd8740e7ceb254373d" id="r_ga520c63ccb534f4fd8740e7ceb254373d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga520c63ccb534f4fd8740e7ceb254373d">ETH_MACDBGR_TFRS_READ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga21675a956d16a5aeac36b390b2bceb72">ETH_MACDBGR_TFRS_READ_Msk</a> /* Read state (transferring data to the MAC transmitter) */</td></tr>
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<tr class="separator:ga520c63ccb534f4fd8740e7ceb254373d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48bc21a580c771ed4ac9b797c0b41d25" id="r_ga48bc21a580c771ed4ac9b797c0b41d25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48bc21a580c771ed4ac9b797c0b41d25">ETH_MACDBGR_TFRS_IDLE</a>   0x00000000U /* Idle state */</td></tr>
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<tr class="separator:ga48bc21a580c771ed4ac9b797c0b41d25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0e5a13ab003041865e72fe3b22a018c" id="r_gad0e5a13ab003041865e72fe3b22a018c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0e5a13ab003041865e72fe3b22a018c">ETH_MACDBGR_MTP_Pos</a>   (19U)</td></tr>
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<tr class="separator:gad0e5a13ab003041865e72fe3b22a018c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga680e2f1a81947b367c26cc628bc10259" id="r_ga680e2f1a81947b367c26cc628bc10259"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga680e2f1a81947b367c26cc628bc10259">ETH_MACDBGR_MTP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad0e5a13ab003041865e72fe3b22a018c">ETH_MACDBGR_MTP_Pos</a>)</td></tr>
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<tr class="separator:ga680e2f1a81947b367c26cc628bc10259"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03abbf9c3ee0c6531fd85e0e83596ca8" id="r_ga03abbf9c3ee0c6531fd85e0e83596ca8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03abbf9c3ee0c6531fd85e0e83596ca8">ETH_MACDBGR_MTP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga680e2f1a81947b367c26cc628bc10259">ETH_MACDBGR_MTP_Msk</a> /* MAC transmitter in pause */</td></tr>
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<tr class="separator:ga03abbf9c3ee0c6531fd85e0e83596ca8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae311faf908813d5e2431be06b785778a" id="r_gae311faf908813d5e2431be06b785778a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae311faf908813d5e2431be06b785778a">ETH_MACDBGR_MTFCS_Pos</a>   (17U)</td></tr>
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<tr class="separator:gae311faf908813d5e2431be06b785778a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba7a88ee0e14eac0b53172fb50eb25d5" id="r_gaba7a88ee0e14eac0b53172fb50eb25d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba7a88ee0e14eac0b53172fb50eb25d5">ETH_MACDBGR_MTFCS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae311faf908813d5e2431be06b785778a">ETH_MACDBGR_MTFCS_Pos</a>)</td></tr>
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<tr class="separator:gaba7a88ee0e14eac0b53172fb50eb25d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaede9295547f715df2272833f1245482a" id="r_gaede9295547f715df2272833f1245482a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaede9295547f715df2272833f1245482a">ETH_MACDBGR_MTFCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba7a88ee0e14eac0b53172fb50eb25d5">ETH_MACDBGR_MTFCS_Msk</a> /* MAC transmit frame controller <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> mask */</td></tr>
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<tr class="separator:gaede9295547f715df2272833f1245482a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacab9c8c877f4eb62417bc729bf9a06f" id="r_gaacab9c8c877f4eb62417bc729bf9a06f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacab9c8c877f4eb62417bc729bf9a06f">ETH_MACDBGR_MTFCS_TRANSFERRING_Pos</a>   (17U)</td></tr>
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<tr class="separator:gaacab9c8c877f4eb62417bc729bf9a06f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga256a9d6a729fb24273de7934fda3382a" id="r_ga256a9d6a729fb24273de7934fda3382a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga256a9d6a729fb24273de7934fda3382a">ETH_MACDBGR_MTFCS_TRANSFERRING_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaacab9c8c877f4eb62417bc729bf9a06f">ETH_MACDBGR_MTFCS_TRANSFERRING_Pos</a>)</td></tr>
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<tr class="separator:ga256a9d6a729fb24273de7934fda3382a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga864ba1fd49a4814383f949cafe684e03" id="r_ga864ba1fd49a4814383f949cafe684e03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga864ba1fd49a4814383f949cafe684e03">ETH_MACDBGR_MTFCS_TRANSFERRING</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga256a9d6a729fb24273de7934fda3382a">ETH_MACDBGR_MTFCS_TRANSFERRING_Msk</a> /* Transferring input frame for transmission */</td></tr>
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<tr class="memitem:ga2557c4eac2221f1faab94f9b8cfe00e8" id="r_ga2557c4eac2221f1faab94f9b8cfe00e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2557c4eac2221f1faab94f9b8cfe00e8">ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga2557c4eac2221f1faab94f9b8cfe00e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad83c11088ad9488ad95df4164d87a6aa" id="r_gad83c11088ad9488ad95df4164d87a6aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad83c11088ad9488ad95df4164d87a6aa">ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2557c4eac2221f1faab94f9b8cfe00e8">ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos</a>)</td></tr>
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<tr class="separator:gad83c11088ad9488ad95df4164d87a6aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6e711aa626786701cf5a7be94022d51" id="r_gad6e711aa626786701cf5a7be94022d51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6e711aa626786701cf5a7be94022d51">ETH_MACDBGR_MTFCS_GENERATINGPCF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad83c11088ad9488ad95df4164d87a6aa">ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk</a> /* Generating and transmitting a Pause control frame (in full duplex mode) */</td></tr>
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<tr class="separator:gad6e711aa626786701cf5a7be94022d51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga924c2a45180a5d6a97c57af4472bc6da" id="r_ga924c2a45180a5d6a97c57af4472bc6da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga924c2a45180a5d6a97c57af4472bc6da">ETH_MACDBGR_MTFCS_WAITING_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga924c2a45180a5d6a97c57af4472bc6da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c76dec4e7bed65b011abe14d172b63b" id="r_ga5c76dec4e7bed65b011abe14d172b63b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c76dec4e7bed65b011abe14d172b63b">ETH_MACDBGR_MTFCS_WAITING_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga924c2a45180a5d6a97c57af4472bc6da">ETH_MACDBGR_MTFCS_WAITING_Pos</a>)</td></tr>
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<tr class="separator:ga5c76dec4e7bed65b011abe14d172b63b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b7c3b89c04bd5e78f21fbc80531d93d" id="r_ga8b7c3b89c04bd5e78f21fbc80531d93d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b7c3b89c04bd5e78f21fbc80531d93d">ETH_MACDBGR_MTFCS_WAITING</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c76dec4e7bed65b011abe14d172b63b">ETH_MACDBGR_MTFCS_WAITING_Msk</a> /* Waiting for Status of previous frame or IFG/backoff period to be over */</td></tr>
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<tr class="separator:ga8b7c3b89c04bd5e78f21fbc80531d93d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac046bac41daecef700eab3b0b56cffc8" id="r_gac046bac41daecef700eab3b0b56cffc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac046bac41daecef700eab3b0b56cffc8">ETH_MACDBGR_MTFCS_IDLE</a>   0x00000000U /* Idle */</td></tr>
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<tr class="separator:gac046bac41daecef700eab3b0b56cffc8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga255b74ece40f98dd5d09daadbaaf35a5" id="r_ga255b74ece40f98dd5d09daadbaaf35a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga255b74ece40f98dd5d09daadbaaf35a5">ETH_MACDBGR_MMTEA_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga255b74ece40f98dd5d09daadbaaf35a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaacb0318306838dab51594d9c70f1317" id="r_gaaacb0318306838dab51594d9c70f1317"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaacb0318306838dab51594d9c70f1317">ETH_MACDBGR_MMTEA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga255b74ece40f98dd5d09daadbaaf35a5">ETH_MACDBGR_MMTEA_Pos</a>)</td></tr>
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<tr class="separator:gaaacb0318306838dab51594d9c70f1317"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga351f61d0b865bf9eef1c322a63470b9b" id="r_ga351f61d0b865bf9eef1c322a63470b9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga351f61d0b865bf9eef1c322a63470b9b">ETH_MACDBGR_MMTEA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaacb0318306838dab51594d9c70f1317">ETH_MACDBGR_MMTEA_Msk</a> /* MAC MII transmit engine active */</td></tr>
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<tr class="separator:ga351f61d0b865bf9eef1c322a63470b9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga662cdc10d98ff6adaf37c06708632e18" id="r_ga662cdc10d98ff6adaf37c06708632e18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga662cdc10d98ff6adaf37c06708632e18">ETH_MACDBGR_RFFL_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga662cdc10d98ff6adaf37c06708632e18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga677c8cbf5dde19bafe80d61eeec6acdf" id="r_ga677c8cbf5dde19bafe80d61eeec6acdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga677c8cbf5dde19bafe80d61eeec6acdf">ETH_MACDBGR_RFFL_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga662cdc10d98ff6adaf37c06708632e18">ETH_MACDBGR_RFFL_Pos</a>)</td></tr>
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<tr class="separator:ga677c8cbf5dde19bafe80d61eeec6acdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeaada3f1e16d6196492ee883729b1bc5" id="r_gaeaada3f1e16d6196492ee883729b1bc5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeaada3f1e16d6196492ee883729b1bc5">ETH_MACDBGR_RFFL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga677c8cbf5dde19bafe80d61eeec6acdf">ETH_MACDBGR_RFFL_Msk</a> /* Rx FIFO fill level mask */</td></tr>
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<tr class="separator:gaeaada3f1e16d6196492ee883729b1bc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf89706d23f364ef3b84d865245142e81" id="r_gaf89706d23f364ef3b84d865245142e81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf89706d23f364ef3b84d865245142e81">ETH_MACDBGR_RFFL_FULL_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaf89706d23f364ef3b84d865245142e81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf21ee74d35ebd3ab19866e990b939cf7" id="r_gaf21ee74d35ebd3ab19866e990b939cf7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf21ee74d35ebd3ab19866e990b939cf7">ETH_MACDBGR_RFFL_FULL_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf89706d23f364ef3b84d865245142e81">ETH_MACDBGR_RFFL_FULL_Pos</a>)</td></tr>
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<tr class="separator:gaf21ee74d35ebd3ab19866e990b939cf7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe77114eff677d5aa1a9e9fdff1dd012" id="r_gafe77114eff677d5aa1a9e9fdff1dd012"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe77114eff677d5aa1a9e9fdff1dd012">ETH_MACDBGR_RFFL_FULL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf21ee74d35ebd3ab19866e990b939cf7">ETH_MACDBGR_RFFL_FULL_Msk</a> /* RxFIFO full */</td></tr>
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<tr class="separator:gafe77114eff677d5aa1a9e9fdff1dd012"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd0c643a902e127cc756b7fd2f1addc7" id="r_gadd0c643a902e127cc756b7fd2f1addc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd0c643a902e127cc756b7fd2f1addc7">ETH_MACDBGR_RFFL_ABOVEFCT_Pos</a>   (9U)</td></tr>
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<tr class="separator:gadd0c643a902e127cc756b7fd2f1addc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10c2064f3b400195c7af25036b061a7a" id="r_ga10c2064f3b400195c7af25036b061a7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10c2064f3b400195c7af25036b061a7a">ETH_MACDBGR_RFFL_ABOVEFCT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadd0c643a902e127cc756b7fd2f1addc7">ETH_MACDBGR_RFFL_ABOVEFCT_Pos</a>)</td></tr>
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<tr class="separator:ga10c2064f3b400195c7af25036b061a7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6641e0e8ac06b83bae463bc922f21d11" id="r_ga6641e0e8ac06b83bae463bc922f21d11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6641e0e8ac06b83bae463bc922f21d11">ETH_MACDBGR_RFFL_ABOVEFCT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga10c2064f3b400195c7af25036b061a7a">ETH_MACDBGR_RFFL_ABOVEFCT_Msk</a> /* RxFIFO fill-level above flow-control activate threshold */</td></tr>
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<tr class="separator:ga6641e0e8ac06b83bae463bc922f21d11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga248a8dded9a74fcbffc47420902925cf" id="r_ga248a8dded9a74fcbffc47420902925cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga248a8dded9a74fcbffc47420902925cf">ETH_MACDBGR_RFFL_BELOWFCT_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga248a8dded9a74fcbffc47420902925cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19cdea0cde9945c403c6c06813c9bf62" id="r_ga19cdea0cde9945c403c6c06813c9bf62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19cdea0cde9945c403c6c06813c9bf62">ETH_MACDBGR_RFFL_BELOWFCT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga248a8dded9a74fcbffc47420902925cf">ETH_MACDBGR_RFFL_BELOWFCT_Pos</a>)</td></tr>
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<tr class="separator:ga19cdea0cde9945c403c6c06813c9bf62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ddf7ce69f167379613a4c7cdcc1e793" id="r_ga2ddf7ce69f167379613a4c7cdcc1e793"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ddf7ce69f167379613a4c7cdcc1e793">ETH_MACDBGR_RFFL_BELOWFCT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga19cdea0cde9945c403c6c06813c9bf62">ETH_MACDBGR_RFFL_BELOWFCT_Msk</a> /* RxFIFO fill-level below flow-control de-activate threshold */</td></tr>
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<tr class="separator:ga2ddf7ce69f167379613a4c7cdcc1e793"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab858b8daec5ad2e262c045e2c356c8da" id="r_gab858b8daec5ad2e262c045e2c356c8da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab858b8daec5ad2e262c045e2c356c8da">ETH_MACDBGR_RFFL_EMPTY</a>   0x00000000U /* RxFIFO empty */</td></tr>
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<tr class="separator:gab858b8daec5ad2e262c045e2c356c8da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae559873efaadb3aeee1a88c9d57532f2" id="r_gae559873efaadb3aeee1a88c9d57532f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae559873efaadb3aeee1a88c9d57532f2">ETH_MACDBGR_RFRCS_Pos</a>   (5U)</td></tr>
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<tr class="separator:gae559873efaadb3aeee1a88c9d57532f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5bb3df9b84ce49d0cd478ad7c3c7853" id="r_gad5bb3df9b84ce49d0cd478ad7c3c7853"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5bb3df9b84ce49d0cd478ad7c3c7853">ETH_MACDBGR_RFRCS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae559873efaadb3aeee1a88c9d57532f2">ETH_MACDBGR_RFRCS_Pos</a>)</td></tr>
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<tr class="separator:gad5bb3df9b84ce49d0cd478ad7c3c7853"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71dcc3ae1256f5d497268d17da32365f" id="r_ga71dcc3ae1256f5d497268d17da32365f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71dcc3ae1256f5d497268d17da32365f">ETH_MACDBGR_RFRCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad5bb3df9b84ce49d0cd478ad7c3c7853">ETH_MACDBGR_RFRCS_Msk</a> /* Rx FIFO read controller <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> mask */</td></tr>
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<tr class="separator:ga71dcc3ae1256f5d497268d17da32365f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ad0c45c41812a126604ca20edd26ea1" id="r_ga7ad0c45c41812a126604ca20edd26ea1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ad0c45c41812a126604ca20edd26ea1">ETH_MACDBGR_RFRCS_FLUSHING_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga7ad0c45c41812a126604ca20edd26ea1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0dabbd91b31f2da515b27e58d3e4b382" id="r_ga0dabbd91b31f2da515b27e58d3e4b382"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dabbd91b31f2da515b27e58d3e4b382">ETH_MACDBGR_RFRCS_FLUSHING_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ad0c45c41812a126604ca20edd26ea1">ETH_MACDBGR_RFRCS_FLUSHING_Pos</a>)</td></tr>
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<tr class="separator:ga0dabbd91b31f2da515b27e58d3e4b382"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c6dcca9f806cc4c605e87ff6688002f" id="r_ga7c6dcca9f806cc4c605e87ff6688002f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c6dcca9f806cc4c605e87ff6688002f">ETH_MACDBGR_RFRCS_FLUSHING</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0dabbd91b31f2da515b27e58d3e4b382">ETH_MACDBGR_RFRCS_FLUSHING_Msk</a> /* Flushing the frame data and <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga7c6dcca9f806cc4c605e87ff6688002f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a03f0782ae649ffa10bf09cf6544c21" id="r_ga2a03f0782ae649ffa10bf09cf6544c21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a03f0782ae649ffa10bf09cf6544c21">ETH_MACDBGR_RFRCS_STATUSREADING_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga2a03f0782ae649ffa10bf09cf6544c21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2441dce4a78077110e952be1e34afef" id="r_gae2441dce4a78077110e952be1e34afef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2441dce4a78077110e952be1e34afef">ETH_MACDBGR_RFRCS_STATUSREADING_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a03f0782ae649ffa10bf09cf6544c21">ETH_MACDBGR_RFRCS_STATUSREADING_Pos</a>)</td></tr>
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<tr class="memitem:gae60cfc823422bbec5008b06da236861e" id="r_gae60cfc823422bbec5008b06da236861e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae60cfc823422bbec5008b06da236861e">ETH_MACDBGR_RFRCS_STATUSREADING</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae2441dce4a78077110e952be1e34afef">ETH_MACDBGR_RFRCS_STATUSREADING_Msk</a> /* Reading frame <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> (or time-stamp) */</td></tr>
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<tr class="separator:gae60cfc823422bbec5008b06da236861e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac0cf3fc9bd396cc8f571f20d977c36bd" id="r_gac0cf3fc9bd396cc8f571f20d977c36bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0cf3fc9bd396cc8f571f20d977c36bd">ETH_MACDBGR_RFRCS_DATAREADING_Pos</a>   (5U)</td></tr>
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<tr class="separator:gac0cf3fc9bd396cc8f571f20d977c36bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b84a8a7e5d71118ae3cec94160a1e95" id="r_ga7b84a8a7e5d71118ae3cec94160a1e95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b84a8a7e5d71118ae3cec94160a1e95">ETH_MACDBGR_RFRCS_DATAREADING_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac0cf3fc9bd396cc8f571f20d977c36bd">ETH_MACDBGR_RFRCS_DATAREADING_Pos</a>)</td></tr>
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<tr class="separator:ga7b84a8a7e5d71118ae3cec94160a1e95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa876e6249677eb886802d0de921586a9" id="r_gaa876e6249677eb886802d0de921586a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa876e6249677eb886802d0de921586a9">ETH_MACDBGR_RFRCS_DATAREADING</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b84a8a7e5d71118ae3cec94160a1e95">ETH_MACDBGR_RFRCS_DATAREADING_Msk</a> /* Reading frame data */</td></tr>
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<tr class="separator:gaa876e6249677eb886802d0de921586a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02670bb4130b5700cd7c8a1b83fc5ea7" id="r_ga02670bb4130b5700cd7c8a1b83fc5ea7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02670bb4130b5700cd7c8a1b83fc5ea7">ETH_MACDBGR_RFRCS_IDLE</a>   0x00000000U /* IDLE state */</td></tr>
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<tr class="separator:ga02670bb4130b5700cd7c8a1b83fc5ea7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8dd87eed0c5d5ae993d654abb251b63c" id="r_ga8dd87eed0c5d5ae993d654abb251b63c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8dd87eed0c5d5ae993d654abb251b63c">ETH_MACDBGR_RFWRA_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga8dd87eed0c5d5ae993d654abb251b63c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65529949f0603e73f75fa2a35890b5a3" id="r_ga65529949f0603e73f75fa2a35890b5a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65529949f0603e73f75fa2a35890b5a3">ETH_MACDBGR_RFWRA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8dd87eed0c5d5ae993d654abb251b63c">ETH_MACDBGR_RFWRA_Pos</a>)</td></tr>
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<tr class="separator:ga65529949f0603e73f75fa2a35890b5a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80fdd819a347bb13cbd5575fc15d914a" id="r_ga80fdd819a347bb13cbd5575fc15d914a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80fdd819a347bb13cbd5575fc15d914a">ETH_MACDBGR_RFWRA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65529949f0603e73f75fa2a35890b5a3">ETH_MACDBGR_RFWRA_Msk</a> /* Rx FIFO write controller active */</td></tr>
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<tr class="separator:ga80fdd819a347bb13cbd5575fc15d914a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga667ffe9105a73ce0bde2927cf8f3d460" id="r_ga667ffe9105a73ce0bde2927cf8f3d460"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga667ffe9105a73ce0bde2927cf8f3d460">ETH_MACDBGR_MSFRWCS_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga667ffe9105a73ce0bde2927cf8f3d460"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52fd76b8f90767f087ec1c667025c8c3" id="r_ga52fd76b8f90767f087ec1c667025c8c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52fd76b8f90767f087ec1c667025c8c3">ETH_MACDBGR_MSFRWCS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga667ffe9105a73ce0bde2927cf8f3d460">ETH_MACDBGR_MSFRWCS_Pos</a>)</td></tr>
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<tr class="separator:ga52fd76b8f90767f087ec1c667025c8c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf075cce7b6d8d49b2371c84b978d68c0" id="r_gaf075cce7b6d8d49b2371c84b978d68c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf075cce7b6d8d49b2371c84b978d68c0">ETH_MACDBGR_MSFRWCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga52fd76b8f90767f087ec1c667025c8c3">ETH_MACDBGR_MSFRWCS_Msk</a> /* MAC small FIFO read / write controllers <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> mask */</td></tr>
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<tr class="separator:gaf075cce7b6d8d49b2371c84b978d68c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c641484d2e209feeb8767877a275ded" id="r_ga4c641484d2e209feeb8767877a275ded"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c641484d2e209feeb8767877a275ded">ETH_MACDBGR_MSFRWCS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga667ffe9105a73ce0bde2927cf8f3d460">ETH_MACDBGR_MSFRWCS_Pos</a>)</td></tr>
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<tr class="separator:ga4c641484d2e209feeb8767877a275ded"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fb3798487f2a257d688ac435a608341" id="r_ga0fb3798487f2a257d688ac435a608341"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fb3798487f2a257d688ac435a608341">ETH_MACDBGR_MSFRWCS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga667ffe9105a73ce0bde2927cf8f3d460">ETH_MACDBGR_MSFRWCS_Pos</a>)</td></tr>
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<tr class="separator:ga0fb3798487f2a257d688ac435a608341"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30e18ad6efe686ce4182e2f381b136d9" id="r_ga30e18ad6efe686ce4182e2f381b136d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30e18ad6efe686ce4182e2f381b136d9">ETH_MACDBGR_MMRPEA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga30e18ad6efe686ce4182e2f381b136d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e61368122a669649e18e073d92b9523" id="r_ga8e61368122a669649e18e073d92b9523"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e61368122a669649e18e073d92b9523">ETH_MACDBGR_MMRPEA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga30e18ad6efe686ce4182e2f381b136d9">ETH_MACDBGR_MMRPEA_Pos</a>)</td></tr>
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<tr class="separator:ga8e61368122a669649e18e073d92b9523"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ea39162c87ae99fc775d7c685f4cad9" id="r_ga2ea39162c87ae99fc775d7c685f4cad9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ea39162c87ae99fc775d7c685f4cad9">ETH_MACDBGR_MMRPEA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e61368122a669649e18e073d92b9523">ETH_MACDBGR_MMRPEA_Msk</a> /* MAC MII receive protocol engine active */</td></tr>
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<tr class="separator:ga2ea39162c87ae99fc775d7c685f4cad9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga812de501f25e360962652a2a17b65e52" id="r_ga812de501f25e360962652a2a17b65e52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga812de501f25e360962652a2a17b65e52">ETH_MACSR_TSTS_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga812de501f25e360962652a2a17b65e52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7a53b96de3d0f7dc394e745bafcc899" id="r_gaa7a53b96de3d0f7dc394e745bafcc899"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7a53b96de3d0f7dc394e745bafcc899">ETH_MACSR_TSTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga812de501f25e360962652a2a17b65e52">ETH_MACSR_TSTS_Pos</a>)</td></tr>
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<tr class="separator:gaa7a53b96de3d0f7dc394e745bafcc899"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5e4af1a52a19f5b2d8f3ce74dd5c85e" id="r_gac5e4af1a52a19f5b2d8f3ce74dd5c85e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5e4af1a52a19f5b2d8f3ce74dd5c85e">ETH_MACSR_TSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7a53b96de3d0f7dc394e745bafcc899">ETH_MACSR_TSTS_Msk</a> /* Time stamp trigger <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:gac5e4af1a52a19f5b2d8f3ce74dd5c85e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf8b2cfde92f9bb04b084ea2af687689d" id="r_gaf8b2cfde92f9bb04b084ea2af687689d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf8b2cfde92f9bb04b084ea2af687689d">ETH_MACSR_MMCTS_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaf8b2cfde92f9bb04b084ea2af687689d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabce1cd290247069cb65dd4d96d0fb638" id="r_gabce1cd290247069cb65dd4d96d0fb638"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabce1cd290247069cb65dd4d96d0fb638">ETH_MACSR_MMCTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf8b2cfde92f9bb04b084ea2af687689d">ETH_MACSR_MMCTS_Pos</a>)</td></tr>
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<tr class="separator:gabce1cd290247069cb65dd4d96d0fb638"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f628abfb1f1076cd89ac76a373d48d6" id="r_ga0f628abfb1f1076cd89ac76a373d48d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f628abfb1f1076cd89ac76a373d48d6">ETH_MACSR_MMCTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabce1cd290247069cb65dd4d96d0fb638">ETH_MACSR_MMCTS_Msk</a> /* MMC transmit <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga0f628abfb1f1076cd89ac76a373d48d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e33ef451e773236892e9635f0aa7498" id="r_ga3e33ef451e773236892e9635f0aa7498"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e33ef451e773236892e9635f0aa7498">ETH_MACSR_MMMCRS_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga3e33ef451e773236892e9635f0aa7498"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06bed909940fa2ea61c81f38c0209262" id="r_ga06bed909940fa2ea61c81f38c0209262"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06bed909940fa2ea61c81f38c0209262">ETH_MACSR_MMMCRS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e33ef451e773236892e9635f0aa7498">ETH_MACSR_MMMCRS_Pos</a>)</td></tr>
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<tr class="separator:ga06bed909940fa2ea61c81f38c0209262"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9faeaa8069b56260ffc8ed2daa06fcd" id="r_gaf9faeaa8069b56260ffc8ed2daa06fcd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9faeaa8069b56260ffc8ed2daa06fcd">ETH_MACSR_MMMCRS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06bed909940fa2ea61c81f38c0209262">ETH_MACSR_MMMCRS_Msk</a> /* MMC receive <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:gaf9faeaa8069b56260ffc8ed2daa06fcd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6836cf875c27333b0358be060c931c9e" id="r_ga6836cf875c27333b0358be060c931c9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6836cf875c27333b0358be060c931c9e">ETH_MACSR_MMCS_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga6836cf875c27333b0358be060c931c9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e9a4734bc3540aa6d658c928a15634c" id="r_ga0e9a4734bc3540aa6d658c928a15634c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e9a4734bc3540aa6d658c928a15634c">ETH_MACSR_MMCS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6836cf875c27333b0358be060c931c9e">ETH_MACSR_MMCS_Pos</a>)</td></tr>
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<tr class="separator:ga0e9a4734bc3540aa6d658c928a15634c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga764dd9b736867f6c5b590c7ca49017c2" id="r_ga764dd9b736867f6c5b590c7ca49017c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga764dd9b736867f6c5b590c7ca49017c2">ETH_MACSR_MMCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e9a4734bc3540aa6d658c928a15634c">ETH_MACSR_MMCS_Msk</a> /* MMC <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga764dd9b736867f6c5b590c7ca49017c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c4e8dc8e8dad60de5b659a72ca7fe74" id="r_ga7c4e8dc8e8dad60de5b659a72ca7fe74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c4e8dc8e8dad60de5b659a72ca7fe74">ETH_MACSR_PMTS_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga7c4e8dc8e8dad60de5b659a72ca7fe74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga279ac5f84e4f33e20f11d5bdbcf21cc2" id="r_ga279ac5f84e4f33e20f11d5bdbcf21cc2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga279ac5f84e4f33e20f11d5bdbcf21cc2">ETH_MACSR_PMTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c4e8dc8e8dad60de5b659a72ca7fe74">ETH_MACSR_PMTS_Pos</a>)</td></tr>
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<tr class="separator:ga279ac5f84e4f33e20f11d5bdbcf21cc2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee99dd08ad3581436f53b7f22452dcb9" id="r_gaee99dd08ad3581436f53b7f22452dcb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee99dd08ad3581436f53b7f22452dcb9">ETH_MACSR_PMTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga279ac5f84e4f33e20f11d5bdbcf21cc2">ETH_MACSR_PMTS_Msk</a> /* PMT <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:gaee99dd08ad3581436f53b7f22452dcb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaff7e97a761e2557458f09c24e91d507" id="r_gaaff7e97a761e2557458f09c24e91d507"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaff7e97a761e2557458f09c24e91d507">ETH_MACIMR_TSTIM_Pos</a>   (9U)</td></tr>
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<tr class="memitem:ga2092019773b2c66261249da4c9eced6b" id="r_ga2092019773b2c66261249da4c9eced6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2092019773b2c66261249da4c9eced6b">ETH_MACIMR_TSTIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaff7e97a761e2557458f09c24e91d507">ETH_MACIMR_TSTIM_Pos</a>)</td></tr>
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<tr class="memitem:ga8f17c13903c30bc301c7897b93a16a24" id="r_ga8f17c13903c30bc301c7897b93a16a24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f17c13903c30bc301c7897b93a16a24">ETH_MACIMR_TSTIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2092019773b2c66261249da4c9eced6b">ETH_MACIMR_TSTIM_Msk</a> /* Time stamp trigger interrupt mask */</td></tr>
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<tr class="memitem:gadd408f2d5725c50c92eeedadc12b5b0e" id="r_gadd408f2d5725c50c92eeedadc12b5b0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd408f2d5725c50c92eeedadc12b5b0e">ETH_MACIMR_PMTIM_Pos</a>   (3U)</td></tr>
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<tr class="separator:gadd408f2d5725c50c92eeedadc12b5b0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5de068ed7fd3905c55b6e2cca8324e25" id="r_ga5de068ed7fd3905c55b6e2cca8324e25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5de068ed7fd3905c55b6e2cca8324e25">ETH_MACIMR_PMTIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadd408f2d5725c50c92eeedadc12b5b0e">ETH_MACIMR_PMTIM_Pos</a>)</td></tr>
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<tr class="separator:ga5de068ed7fd3905c55b6e2cca8324e25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2cdb4ba6c97aba3e82e8192ebddcb5f" id="r_gaf2cdb4ba6c97aba3e82e8192ebddcb5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2cdb4ba6c97aba3e82e8192ebddcb5f">ETH_MACIMR_PMTIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5de068ed7fd3905c55b6e2cca8324e25">ETH_MACIMR_PMTIM_Msk</a> /* PMT interrupt mask */</td></tr>
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<tr class="separator:gaf2cdb4ba6c97aba3e82e8192ebddcb5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21bb827892ec43224afef17af302e1a3" id="r_ga21bb827892ec43224afef17af302e1a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21bb827892ec43224afef17af302e1a3">ETH_MACA0HR_MACA0H_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga21bb827892ec43224afef17af302e1a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga867c6c9c8a1a2c5559f99673debe33a3" id="r_ga867c6c9c8a1a2c5559f99673debe33a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga867c6c9c8a1a2c5559f99673debe33a3">ETH_MACA0HR_MACA0H_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga21bb827892ec43224afef17af302e1a3">ETH_MACA0HR_MACA0H_Pos</a>)</td></tr>
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<tr class="separator:ga867c6c9c8a1a2c5559f99673debe33a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga142dbcbb7da81e8549dde3c239ed8251" id="r_ga142dbcbb7da81e8549dde3c239ed8251"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga142dbcbb7da81e8549dde3c239ed8251">ETH_MACA0HR_MACA0H</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga867c6c9c8a1a2c5559f99673debe33a3">ETH_MACA0HR_MACA0H_Msk</a> /* MAC address0 high */</td></tr>
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<tr class="separator:ga142dbcbb7da81e8549dde3c239ed8251"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72f33ca841069471da9ca73b46d40ac5" id="r_ga72f33ca841069471da9ca73b46d40ac5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72f33ca841069471da9ca73b46d40ac5">ETH_MACA0LR_MACA0L_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga72f33ca841069471da9ca73b46d40ac5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga994262dc8bd5b38a213503e3d2e6c398" id="r_ga994262dc8bd5b38a213503e3d2e6c398"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga994262dc8bd5b38a213503e3d2e6c398">ETH_MACA0LR_MACA0L_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga72f33ca841069471da9ca73b46d40ac5">ETH_MACA0LR_MACA0L_Pos</a>)</td></tr>
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<tr class="separator:ga994262dc8bd5b38a213503e3d2e6c398"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3ed9dbd9711ee9c19f40c73d8f33be3" id="r_gaf3ed9dbd9711ee9c19f40c73d8f33be3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3ed9dbd9711ee9c19f40c73d8f33be3">ETH_MACA0LR_MACA0L</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga994262dc8bd5b38a213503e3d2e6c398">ETH_MACA0LR_MACA0L_Msk</a> /* MAC address0 low */</td></tr>
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<tr class="separator:gaf3ed9dbd9711ee9c19f40c73d8f33be3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f3217cb3886e3c977a676a06b912eb2" id="r_ga2f3217cb3886e3c977a676a06b912eb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f3217cb3886e3c977a676a06b912eb2">ETH_MACA1HR_AE_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga2f3217cb3886e3c977a676a06b912eb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ab67262fcf71a730f150aed61e3e173" id="r_ga5ab67262fcf71a730f150aed61e3e173"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ab67262fcf71a730f150aed61e3e173">ETH_MACA1HR_AE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f3217cb3886e3c977a676a06b912eb2">ETH_MACA1HR_AE_Pos</a>)</td></tr>
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<tr class="separator:ga5ab67262fcf71a730f150aed61e3e173"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f88c5ead1109f1e0abac07bcb2e44ea" id="r_ga9f88c5ead1109f1e0abac07bcb2e44ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f88c5ead1109f1e0abac07bcb2e44ea">ETH_MACA1HR_AE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ab67262fcf71a730f150aed61e3e173">ETH_MACA1HR_AE_Msk</a> /* Address enable */</td></tr>
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<tr class="separator:ga9f88c5ead1109f1e0abac07bcb2e44ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaecdc77542da8b8c62da99702324479e1" id="r_gaecdc77542da8b8c62da99702324479e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaecdc77542da8b8c62da99702324479e1">ETH_MACA1HR_SA_Pos</a>   (30U)</td></tr>
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<tr class="separator:gaecdc77542da8b8c62da99702324479e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac076f91767de8a428972303da56427d5" id="r_gac076f91767de8a428972303da56427d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac076f91767de8a428972303da56427d5">ETH_MACA1HR_SA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaecdc77542da8b8c62da99702324479e1">ETH_MACA1HR_SA_Pos</a>)</td></tr>
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<tr class="separator:gac076f91767de8a428972303da56427d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3840a96465b73115d34360abf3704c5" id="r_gac3840a96465b73115d34360abf3704c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3840a96465b73115d34360abf3704c5">ETH_MACA1HR_SA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac076f91767de8a428972303da56427d5">ETH_MACA1HR_SA_Msk</a> /* Source address */</td></tr>
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<tr class="separator:gac3840a96465b73115d34360abf3704c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c4a2a38360a644181c889a97a058791" id="r_ga6c4a2a38360a644181c889a97a058791"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c4a2a38360a644181c889a97a058791">ETH_MACA1HR_MBC_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga6c4a2a38360a644181c889a97a058791"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf98e44dbd971404c80536dab4459e295" id="r_gaf98e44dbd971404c80536dab4459e295"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf98e44dbd971404c80536dab4459e295">ETH_MACA1HR_MBC_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c4a2a38360a644181c889a97a058791">ETH_MACA1HR_MBC_Pos</a>)</td></tr>
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<tr class="separator:gaf98e44dbd971404c80536dab4459e295"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7bf2fe1242cce62c3fe1cc49ce513b6a" id="r_ga7bf2fe1242cce62c3fe1cc49ce513b6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7bf2fe1242cce62c3fe1cc49ce513b6a">ETH_MACA1HR_MBC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf98e44dbd971404c80536dab4459e295">ETH_MACA1HR_MBC_Msk</a> /* Mask byte control: bits to mask for comparison of the MAC Address bytes */</td></tr>
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<tr class="separator:ga7bf2fe1242cce62c3fe1cc49ce513b6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3e731440906539ecb1c52a84df889c5" id="r_gaf3e731440906539ecb1c52a84df889c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3e731440906539ecb1c52a84df889c5">ETH_MACA1HR_MBC_HBits15_8</a>   0x20000000U /* Mask MAC Address high reg bits [15:8] */</td></tr>
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<tr class="separator:gaf3e731440906539ecb1c52a84df889c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8ebf87cc6584613fea5a49a382b2d67" id="r_gac8ebf87cc6584613fea5a49a382b2d67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8ebf87cc6584613fea5a49a382b2d67">ETH_MACA1HR_MBC_HBits7_0</a>   0x10000000U /* Mask MAC Address high reg bits [7:0] */</td></tr>
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<tr class="separator:gac8ebf87cc6584613fea5a49a382b2d67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7fa211fa742d34dd8e8d2ca2ea5e865a" id="r_ga7fa211fa742d34dd8e8d2ca2ea5e865a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fa211fa742d34dd8e8d2ca2ea5e865a">ETH_MACA1HR_MBC_LBits31_24</a>   0x08000000U /* Mask MAC Address low reg bits [31:24] */</td></tr>
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<tr class="separator:ga7fa211fa742d34dd8e8d2ca2ea5e865a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d3767ea17fd333409e63262ab5f6878" id="r_ga6d3767ea17fd333409e63262ab5f6878"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d3767ea17fd333409e63262ab5f6878">ETH_MACA1HR_MBC_LBits23_16</a>   0x04000000U /* Mask MAC Address low reg bits [23:16] */</td></tr>
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<tr class="separator:ga6d3767ea17fd333409e63262ab5f6878"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3520a54e7e68617539b51885b7bb918" id="r_gab3520a54e7e68617539b51885b7bb918"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3520a54e7e68617539b51885b7bb918">ETH_MACA1HR_MBC_LBits15_8</a>   0x02000000U /* Mask MAC Address low reg bits [15:8] */</td></tr>
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<tr class="separator:gab3520a54e7e68617539b51885b7bb918"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3894de2dc133fd5e03e4d4817852adfd" id="r_ga3894de2dc133fd5e03e4d4817852adfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3894de2dc133fd5e03e4d4817852adfd">ETH_MACA1HR_MBC_LBits7_0</a>   0x01000000U /* Mask MAC Address low reg bits [7:0] */</td></tr>
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<tr class="separator:ga3894de2dc133fd5e03e4d4817852adfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf00494291a47151e9c4ea357746f757d" id="r_gaf00494291a47151e9c4ea357746f757d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf00494291a47151e9c4ea357746f757d">ETH_MACA1HR_MACA1H_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf00494291a47151e9c4ea357746f757d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga859884136a9b5a2924fa61ecb29d28d7" id="r_ga859884136a9b5a2924fa61ecb29d28d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga859884136a9b5a2924fa61ecb29d28d7">ETH_MACA1HR_MACA1H_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf00494291a47151e9c4ea357746f757d">ETH_MACA1HR_MACA1H_Pos</a>)</td></tr>
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<tr class="separator:ga859884136a9b5a2924fa61ecb29d28d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaddd4d059d3d4734c2528ef12cadbd769" id="r_gaddd4d059d3d4734c2528ef12cadbd769"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaddd4d059d3d4734c2528ef12cadbd769">ETH_MACA1HR_MACA1H</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga859884136a9b5a2924fa61ecb29d28d7">ETH_MACA1HR_MACA1H_Msk</a> /* MAC address1 high */</td></tr>
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<tr class="separator:gaddd4d059d3d4734c2528ef12cadbd769"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa29c12e370323d466187775345ab9d1e" id="r_gaa29c12e370323d466187775345ab9d1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa29c12e370323d466187775345ab9d1e">ETH_MACA1LR_MACA1L_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa29c12e370323d466187775345ab9d1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93090bfada32ec17c3385ab72ec89ebb" id="r_ga93090bfada32ec17c3385ab72ec89ebb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93090bfada32ec17c3385ab72ec89ebb">ETH_MACA1LR_MACA1L_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa29c12e370323d466187775345ab9d1e">ETH_MACA1LR_MACA1L_Pos</a>)</td></tr>
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<tr class="separator:ga93090bfada32ec17c3385ab72ec89ebb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacce742aa0eabc2a8b23ba4f79f18409a" id="r_gacce742aa0eabc2a8b23ba4f79f18409a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacce742aa0eabc2a8b23ba4f79f18409a">ETH_MACA1LR_MACA1L</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga93090bfada32ec17c3385ab72ec89ebb">ETH_MACA1LR_MACA1L_Msk</a> /* MAC address1 low */</td></tr>
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<tr class="memitem:ga153e9d30ef5f5fd7e8107e36e4a15757" id="r_ga153e9d30ef5f5fd7e8107e36e4a15757"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga153e9d30ef5f5fd7e8107e36e4a15757">ETH_MACA2HR_AE_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga153e9d30ef5f5fd7e8107e36e4a15757"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cdb03f087e227851c3ad964da076672" id="r_ga8cdb03f087e227851c3ad964da076672"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cdb03f087e227851c3ad964da076672">ETH_MACA2HR_AE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga153e9d30ef5f5fd7e8107e36e4a15757">ETH_MACA2HR_AE_Pos</a>)</td></tr>
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<tr class="memitem:ga5713abb4f70f5514d2d44c44ea17254e" id="r_ga5713abb4f70f5514d2d44c44ea17254e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5713abb4f70f5514d2d44c44ea17254e">ETH_MACA2HR_AE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8cdb03f087e227851c3ad964da076672">ETH_MACA2HR_AE_Msk</a> /* Address enable */</td></tr>
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<tr class="separator:ga5713abb4f70f5514d2d44c44ea17254e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga303b2c351db0593d5283e7f324cb725c" id="r_ga303b2c351db0593d5283e7f324cb725c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga303b2c351db0593d5283e7f324cb725c">ETH_MACA2HR_SA_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga303b2c351db0593d5283e7f324cb725c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade8dbf6a5ba0db18a839b799b9ae951a" id="r_gade8dbf6a5ba0db18a839b799b9ae951a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade8dbf6a5ba0db18a839b799b9ae951a">ETH_MACA2HR_SA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga303b2c351db0593d5283e7f324cb725c">ETH_MACA2HR_SA_Pos</a>)</td></tr>
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<tr class="separator:gade8dbf6a5ba0db18a839b799b9ae951a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c3f0a2b08321c5441a87b385bfe0c41" id="r_ga8c3f0a2b08321c5441a87b385bfe0c41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c3f0a2b08321c5441a87b385bfe0c41">ETH_MACA2HR_SA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gade8dbf6a5ba0db18a839b799b9ae951a">ETH_MACA2HR_SA_Msk</a> /* Source address */</td></tr>
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<tr class="separator:ga8c3f0a2b08321c5441a87b385bfe0c41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b46e39d1c8da3b5d032e57f2fe9c395" id="r_ga9b46e39d1c8da3b5d032e57f2fe9c395"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b46e39d1c8da3b5d032e57f2fe9c395">ETH_MACA2HR_MBC_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga9b46e39d1c8da3b5d032e57f2fe9c395"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab90f57ac02ce2cf7223f3b0bfd0e7891" id="r_gab90f57ac02ce2cf7223f3b0bfd0e7891"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab90f57ac02ce2cf7223f3b0bfd0e7891">ETH_MACA2HR_MBC_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b46e39d1c8da3b5d032e57f2fe9c395">ETH_MACA2HR_MBC_Pos</a>)</td></tr>
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<tr class="memitem:ga270c0bb939fd71e02a8d221caada1071" id="r_ga270c0bb939fd71e02a8d221caada1071"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga270c0bb939fd71e02a8d221caada1071">ETH_MACA2HR_MBC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab90f57ac02ce2cf7223f3b0bfd0e7891">ETH_MACA2HR_MBC_Msk</a> /* Mask byte control */</td></tr>
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<tr class="separator:ga270c0bb939fd71e02a8d221caada1071"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga656070d9cc36501e927908e2f3903332" id="r_ga656070d9cc36501e927908e2f3903332"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga656070d9cc36501e927908e2f3903332">ETH_MACA2HR_MBC_HBits15_8</a>   0x20000000U /* Mask MAC Address high reg bits [15:8] */</td></tr>
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<tr class="memitem:ga322aa03bccdcb0b2e85119629e95be57" id="r_ga322aa03bccdcb0b2e85119629e95be57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga322aa03bccdcb0b2e85119629e95be57">ETH_MACA2HR_MBC_HBits7_0</a>   0x10000000U /* Mask MAC Address high reg bits [7:0] */</td></tr>
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<tr class="separator:ga322aa03bccdcb0b2e85119629e95be57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9519b002d1e0c04b1d5989bf410d24cb" id="r_ga9519b002d1e0c04b1d5989bf410d24cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9519b002d1e0c04b1d5989bf410d24cb">ETH_MACA2HR_MBC_LBits31_24</a>   0x08000000U /* Mask MAC Address low reg bits [31:24] */</td></tr>
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<tr class="separator:ga9519b002d1e0c04b1d5989bf410d24cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cc71bd0499aaa5a76247a6bd6e5e79a" id="r_ga8cc71bd0499aaa5a76247a6bd6e5e79a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cc71bd0499aaa5a76247a6bd6e5e79a">ETH_MACA2HR_MBC_LBits23_16</a>   0x04000000U /* Mask MAC Address low reg bits [23:16] */</td></tr>
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<tr class="separator:ga8cc71bd0499aaa5a76247a6bd6e5e79a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga394acdc62df68dadb1190d4f83f6dbaa" id="r_ga394acdc62df68dadb1190d4f83f6dbaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga394acdc62df68dadb1190d4f83f6dbaa">ETH_MACA2HR_MBC_LBits15_8</a>   0x02000000U /* Mask MAC Address low reg bits [15:8] */</td></tr>
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<tr class="separator:ga394acdc62df68dadb1190d4f83f6dbaa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa87b47b25381694fdcc397cc63ea8810" id="r_gaa87b47b25381694fdcc397cc63ea8810"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa87b47b25381694fdcc397cc63ea8810">ETH_MACA2HR_MBC_LBits7_0</a>   0x01000000U /* Mask MAC Address low reg bits [70] */</td></tr>
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<tr class="separator:gaa87b47b25381694fdcc397cc63ea8810"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a9cabfc6b16557ae778be5010419be9" id="r_ga0a9cabfc6b16557ae778be5010419be9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a9cabfc6b16557ae778be5010419be9">ETH_MACA2HR_MACA2H_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0a9cabfc6b16557ae778be5010419be9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a378228b4b6bd086aa8931bb2b81326" id="r_ga8a378228b4b6bd086aa8931bb2b81326"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a378228b4b6bd086aa8931bb2b81326">ETH_MACA2HR_MACA2H_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a9cabfc6b16557ae778be5010419be9">ETH_MACA2HR_MACA2H_Pos</a>)</td></tr>
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<tr class="separator:ga8a378228b4b6bd086aa8931bb2b81326"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c73a460038c40e28b27fe0cfcd17cef" id="r_ga5c73a460038c40e28b27fe0cfcd17cef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c73a460038c40e28b27fe0cfcd17cef">ETH_MACA2HR_MACA2H</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a378228b4b6bd086aa8931bb2b81326">ETH_MACA2HR_MACA2H_Msk</a> /* MAC address1 high */</td></tr>
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<tr class="separator:ga5c73a460038c40e28b27fe0cfcd17cef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84d72f061c5bd14552d066fefc0bf13c" id="r_ga84d72f061c5bd14552d066fefc0bf13c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84d72f061c5bd14552d066fefc0bf13c">ETH_MACA2LR_MACA2L_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga84d72f061c5bd14552d066fefc0bf13c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga41296fc9e2a6a59d5f7c16e94bc17736" id="r_ga41296fc9e2a6a59d5f7c16e94bc17736"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga41296fc9e2a6a59d5f7c16e94bc17736">ETH_MACA2LR_MACA2L_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84d72f061c5bd14552d066fefc0bf13c">ETH_MACA2LR_MACA2L_Pos</a>)</td></tr>
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<tr class="separator:ga41296fc9e2a6a59d5f7c16e94bc17736"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga757e0ceef1c6d529f28c7875ff3e88e7" id="r_ga757e0ceef1c6d529f28c7875ff3e88e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga757e0ceef1c6d529f28c7875ff3e88e7">ETH_MACA2LR_MACA2L</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga41296fc9e2a6a59d5f7c16e94bc17736">ETH_MACA2LR_MACA2L_Msk</a> /* MAC address2 low */</td></tr>
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<tr class="separator:ga757e0ceef1c6d529f28c7875ff3e88e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19974f597cc028a35be1daec4a1ba531" id="r_ga19974f597cc028a35be1daec4a1ba531"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19974f597cc028a35be1daec4a1ba531">ETH_MACA3HR_AE_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga19974f597cc028a35be1daec4a1ba531"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c36200e79d56aba3c56dc24c475406a" id="r_ga5c36200e79d56aba3c56dc24c475406a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c36200e79d56aba3c56dc24c475406a">ETH_MACA3HR_AE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga19974f597cc028a35be1daec4a1ba531">ETH_MACA3HR_AE_Pos</a>)</td></tr>
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<tr class="separator:ga5c36200e79d56aba3c56dc24c475406a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3bb6d5c1237b2c573f22876a62dcaa9" id="r_gaf3bb6d5c1237b2c573f22876a62dcaa9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3bb6d5c1237b2c573f22876a62dcaa9">ETH_MACA3HR_AE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c36200e79d56aba3c56dc24c475406a">ETH_MACA3HR_AE_Msk</a> /* Address enable */</td></tr>
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<tr class="separator:gaf3bb6d5c1237b2c573f22876a62dcaa9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga988fe5da295995ba022cb1a379673ad7" id="r_ga988fe5da295995ba022cb1a379673ad7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga988fe5da295995ba022cb1a379673ad7">ETH_MACA3HR_SA_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga988fe5da295995ba022cb1a379673ad7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b3ed7c73e177513e879d96e42f8fd5b" id="r_ga3b3ed7c73e177513e879d96e42f8fd5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b3ed7c73e177513e879d96e42f8fd5b">ETH_MACA3HR_SA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga988fe5da295995ba022cb1a379673ad7">ETH_MACA3HR_SA_Pos</a>)</td></tr>
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<tr class="separator:ga3b3ed7c73e177513e879d96e42f8fd5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54c41346fd61170b413812a19fcac8db" id="r_ga54c41346fd61170b413812a19fcac8db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54c41346fd61170b413812a19fcac8db">ETH_MACA3HR_SA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b3ed7c73e177513e879d96e42f8fd5b">ETH_MACA3HR_SA_Msk</a> /* Source address */</td></tr>
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<tr class="separator:ga54c41346fd61170b413812a19fcac8db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadedd5cb92d6134fd4110664083f943f9" id="r_gadedd5cb92d6134fd4110664083f943f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadedd5cb92d6134fd4110664083f943f9">ETH_MACA3HR_MBC_Pos</a>   (24U)</td></tr>
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<tr class="separator:gadedd5cb92d6134fd4110664083f943f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c9fa25a21daaf9673e50a75db9f4193" id="r_ga0c9fa25a21daaf9673e50a75db9f4193"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c9fa25a21daaf9673e50a75db9f4193">ETH_MACA3HR_MBC_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadedd5cb92d6134fd4110664083f943f9">ETH_MACA3HR_MBC_Pos</a>)</td></tr>
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<tr class="separator:ga0c9fa25a21daaf9673e50a75db9f4193"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64ec855ed04aea21b400ae947b54a353" id="r_ga64ec855ed04aea21b400ae947b54a353"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64ec855ed04aea21b400ae947b54a353">ETH_MACA3HR_MBC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c9fa25a21daaf9673e50a75db9f4193">ETH_MACA3HR_MBC_Msk</a> /* Mask byte control */</td></tr>
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<tr class="separator:ga64ec855ed04aea21b400ae947b54a353"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga019fe5bc7d94ee1ee4a605e06e777bb5" id="r_ga019fe5bc7d94ee1ee4a605e06e777bb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga019fe5bc7d94ee1ee4a605e06e777bb5">ETH_MACA3HR_MBC_HBits15_8</a>   0x20000000U /* Mask MAC Address high reg bits [15:8] */</td></tr>
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<tr class="separator:ga019fe5bc7d94ee1ee4a605e06e777bb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33587cdbe844563e853e3815b63c7c47" id="r_ga33587cdbe844563e853e3815b63c7c47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33587cdbe844563e853e3815b63c7c47">ETH_MACA3HR_MBC_HBits7_0</a>   0x10000000U /* Mask MAC Address high reg bits [7:0] */</td></tr>
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<tr class="separator:ga33587cdbe844563e853e3815b63c7c47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae147613a45eb3d13b84b66158217bb89" id="r_gae147613a45eb3d13b84b66158217bb89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae147613a45eb3d13b84b66158217bb89">ETH_MACA3HR_MBC_LBits31_24</a>   0x08000000U /* Mask MAC Address low reg bits [31:24] */</td></tr>
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<tr class="separator:gae147613a45eb3d13b84b66158217bb89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6b47f3fddf3dcd39b3af7785c1e5cced" id="r_ga6b47f3fddf3dcd39b3af7785c1e5cced"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6b47f3fddf3dcd39b3af7785c1e5cced">ETH_MACA3HR_MBC_LBits23_16</a>   0x04000000U /* Mask MAC Address low reg bits [23:16] */</td></tr>
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<tr class="separator:ga6b47f3fddf3dcd39b3af7785c1e5cced"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4744ba01934291f07b1b132b82cb1bd4" id="r_ga4744ba01934291f07b1b132b82cb1bd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4744ba01934291f07b1b132b82cb1bd4">ETH_MACA3HR_MBC_LBits15_8</a>   0x02000000U /* Mask MAC Address low reg bits [15:8] */</td></tr>
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<tr class="separator:ga4744ba01934291f07b1b132b82cb1bd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60f2f1ab81a02837ed96e5f92fe96181" id="r_ga60f2f1ab81a02837ed96e5f92fe96181"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60f2f1ab81a02837ed96e5f92fe96181">ETH_MACA3HR_MBC_LBits7_0</a>   0x01000000U /* Mask MAC Address low reg bits [70] */</td></tr>
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<tr class="separator:ga60f2f1ab81a02837ed96e5f92fe96181"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c868df20fcf4144cff7cdaecec1c892" id="r_ga8c868df20fcf4144cff7cdaecec1c892"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c868df20fcf4144cff7cdaecec1c892">ETH_MACA3HR_MACA3H_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga8c868df20fcf4144cff7cdaecec1c892"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a4c3dd7eb1ea655eb87161f5268de85" id="r_ga2a4c3dd7eb1ea655eb87161f5268de85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a4c3dd7eb1ea655eb87161f5268de85">ETH_MACA3HR_MACA3H_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c868df20fcf4144cff7cdaecec1c892">ETH_MACA3HR_MACA3H_Pos</a>)</td></tr>
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<tr class="separator:ga2a4c3dd7eb1ea655eb87161f5268de85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b5d9faa67c4cc6d1c42ec26ad99d57b" id="r_ga0b5d9faa67c4cc6d1c42ec26ad99d57b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b5d9faa67c4cc6d1c42ec26ad99d57b">ETH_MACA3HR_MACA3H</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a4c3dd7eb1ea655eb87161f5268de85">ETH_MACA3HR_MACA3H_Msk</a> /* MAC address3 high */</td></tr>
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<tr class="separator:ga0b5d9faa67c4cc6d1c42ec26ad99d57b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec6beeb51e6198352c03b91615109947" id="r_gaec6beeb51e6198352c03b91615109947"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec6beeb51e6198352c03b91615109947">ETH_MACA3LR_MACA3L_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaec6beeb51e6198352c03b91615109947"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada2b7497b892a22692e464256513c9e4" id="r_gada2b7497b892a22692e464256513c9e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada2b7497b892a22692e464256513c9e4">ETH_MACA3LR_MACA3L_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaec6beeb51e6198352c03b91615109947">ETH_MACA3LR_MACA3L_Pos</a>)</td></tr>
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<tr class="separator:gada2b7497b892a22692e464256513c9e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa08b4ccde1b7251ba6317e744b09a95f" id="r_gaa08b4ccde1b7251ba6317e744b09a95f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa08b4ccde1b7251ba6317e744b09a95f">ETH_MACA3LR_MACA3L</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada2b7497b892a22692e464256513c9e4">ETH_MACA3LR_MACA3L_Msk</a> /* MAC address3 low */</td></tr>
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<tr class="separator:gaa08b4ccde1b7251ba6317e744b09a95f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54d376c32875a39afa0492c2506b4e45" id="r_ga54d376c32875a39afa0492c2506b4e45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54d376c32875a39afa0492c2506b4e45">ETH_MMCCR_MCFHP_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga54d376c32875a39afa0492c2506b4e45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ed0579e3320b27f2fbc0c55159d7552" id="r_ga7ed0579e3320b27f2fbc0c55159d7552"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ed0579e3320b27f2fbc0c55159d7552">ETH_MMCCR_MCFHP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga54d376c32875a39afa0492c2506b4e45">ETH_MMCCR_MCFHP_Pos</a>)</td></tr>
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<tr class="separator:ga7ed0579e3320b27f2fbc0c55159d7552"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0eb309947d400951235c17953254fbf8" id="r_ga0eb309947d400951235c17953254fbf8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0eb309947d400951235c17953254fbf8">ETH_MMCCR_MCFHP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7ed0579e3320b27f2fbc0c55159d7552">ETH_MMCCR_MCFHP_Msk</a> /* MMC counter Full-Half preset */</td></tr>
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<tr class="separator:ga0eb309947d400951235c17953254fbf8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17d60ddf79fe7ab501bcf68012f7b7ec" id="r_ga17d60ddf79fe7ab501bcf68012f7b7ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17d60ddf79fe7ab501bcf68012f7b7ec">ETH_MMCCR_MCP_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga17d60ddf79fe7ab501bcf68012f7b7ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf04f6b5deb3a53b8b506162772765171" id="r_gaf04f6b5deb3a53b8b506162772765171"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf04f6b5deb3a53b8b506162772765171">ETH_MMCCR_MCP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17d60ddf79fe7ab501bcf68012f7b7ec">ETH_MMCCR_MCP_Pos</a>)</td></tr>
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<tr class="separator:gaf04f6b5deb3a53b8b506162772765171"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a6eeda6ffcafe7d8ba531ccaa3abf90" id="r_ga2a6eeda6ffcafe7d8ba531ccaa3abf90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a6eeda6ffcafe7d8ba531ccaa3abf90">ETH_MMCCR_MCP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf04f6b5deb3a53b8b506162772765171">ETH_MMCCR_MCP_Msk</a> /* MMC counter preset */</td></tr>
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<tr class="separator:ga2a6eeda6ffcafe7d8ba531ccaa3abf90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e66af70554c0813685e282d1bb9c4d5" id="r_ga1e66af70554c0813685e282d1bb9c4d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e66af70554c0813685e282d1bb9c4d5">ETH_MMCCR_MCF_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga1e66af70554c0813685e282d1bb9c4d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e4246e3804f51c0f04a91e42ee6f6b1" id="r_ga2e4246e3804f51c0f04a91e42ee6f6b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e4246e3804f51c0f04a91e42ee6f6b1">ETH_MMCCR_MCF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e66af70554c0813685e282d1bb9c4d5">ETH_MMCCR_MCF_Pos</a>)</td></tr>
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<tr class="separator:ga2e4246e3804f51c0f04a91e42ee6f6b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17ab5fbe6c5189b3f98095f9adb1eeeb" id="r_ga17ab5fbe6c5189b3f98095f9adb1eeeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17ab5fbe6c5189b3f98095f9adb1eeeb">ETH_MMCCR_MCF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e4246e3804f51c0f04a91e42ee6f6b1">ETH_MMCCR_MCF_Msk</a> /* MMC Counter Freeze */</td></tr>
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<tr class="separator:ga17ab5fbe6c5189b3f98095f9adb1eeeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ba16f3d8066423ef675d53633c3bf7f" id="r_ga0ba16f3d8066423ef675d53633c3bf7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ba16f3d8066423ef675d53633c3bf7f">ETH_MMCCR_ROR_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga0ba16f3d8066423ef675d53633c3bf7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb19c7101d5986ae5582acf37c2fa730" id="r_gaeb19c7101d5986ae5582acf37c2fa730"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb19c7101d5986ae5582acf37c2fa730">ETH_MMCCR_ROR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ba16f3d8066423ef675d53633c3bf7f">ETH_MMCCR_ROR_Pos</a>)</td></tr>
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<tr class="separator:gaeb19c7101d5986ae5582acf37c2fa730"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga243ae6b3acbbd295be6f76a84657a48d" id="r_ga243ae6b3acbbd295be6f76a84657a48d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga243ae6b3acbbd295be6f76a84657a48d">ETH_MMCCR_ROR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb19c7101d5986ae5582acf37c2fa730">ETH_MMCCR_ROR_Msk</a> /* Reset on Read */</td></tr>
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<tr class="separator:ga243ae6b3acbbd295be6f76a84657a48d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5f177ef83413fc7f8b139d2e61a195b" id="r_gad5f177ef83413fc7f8b139d2e61a195b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5f177ef83413fc7f8b139d2e61a195b">ETH_MMCCR_CSR_Pos</a>   (1U)</td></tr>
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<tr class="separator:gad5f177ef83413fc7f8b139d2e61a195b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f27d8db71e31940104b534eb8e10ca5" id="r_ga9f27d8db71e31940104b534eb8e10ca5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f27d8db71e31940104b534eb8e10ca5">ETH_MMCCR_CSR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad5f177ef83413fc7f8b139d2e61a195b">ETH_MMCCR_CSR_Pos</a>)</td></tr>
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<tr class="separator:ga9f27d8db71e31940104b534eb8e10ca5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga948b685211ced94ef5d4b8d2c94df78a" id="r_ga948b685211ced94ef5d4b8d2c94df78a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga948b685211ced94ef5d4b8d2c94df78a">ETH_MMCCR_CSR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f27d8db71e31940104b534eb8e10ca5">ETH_MMCCR_CSR_Msk</a> /* Counter Stop Rollover */</td></tr>
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<tr class="separator:ga948b685211ced94ef5d4b8d2c94df78a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43cace7bf67560967d43822c7f2fa730" id="r_ga43cace7bf67560967d43822c7f2fa730"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43cace7bf67560967d43822c7f2fa730">ETH_MMCCR_CR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga43cace7bf67560967d43822c7f2fa730"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36dc300b94cd6c761f4fb2105c306203" id="r_ga36dc300b94cd6c761f4fb2105c306203"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36dc300b94cd6c761f4fb2105c306203">ETH_MMCCR_CR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga43cace7bf67560967d43822c7f2fa730">ETH_MMCCR_CR_Pos</a>)</td></tr>
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<tr class="separator:ga36dc300b94cd6c761f4fb2105c306203"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cb520c80fc0b2f00304bb7f8f7c5d4e" id="r_ga7cb520c80fc0b2f00304bb7f8f7c5d4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cb520c80fc0b2f00304bb7f8f7c5d4e">ETH_MMCCR_CR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga36dc300b94cd6c761f4fb2105c306203">ETH_MMCCR_CR_Msk</a> /* Counters Reset */</td></tr>
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<tr class="separator:ga7cb520c80fc0b2f00304bb7f8f7c5d4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa86865c319fd4a4bdc7f612169251a25" id="r_gaa86865c319fd4a4bdc7f612169251a25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa86865c319fd4a4bdc7f612169251a25">ETH_MMCRIR_RGUFS_Pos</a>   (17U)</td></tr>
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<tr class="separator:gaa86865c319fd4a4bdc7f612169251a25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9dc1a19f41c18602c71bd10a99d70b8" id="r_gaf9dc1a19f41c18602c71bd10a99d70b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9dc1a19f41c18602c71bd10a99d70b8">ETH_MMCRIR_RGUFS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa86865c319fd4a4bdc7f612169251a25">ETH_MMCRIR_RGUFS_Pos</a>)</td></tr>
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<tr class="separator:gaf9dc1a19f41c18602c71bd10a99d70b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4b78bde6602ca062513389b8bf43e17" id="r_gaa4b78bde6602ca062513389b8bf43e17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4b78bde6602ca062513389b8bf43e17">ETH_MMCRIR_RGUFS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9dc1a19f41c18602c71bd10a99d70b8">ETH_MMCRIR_RGUFS_Msk</a> /* Set when Rx good unicast frames counter reaches half the maximum value */</td></tr>
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<tr class="separator:gaa4b78bde6602ca062513389b8bf43e17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabea46fc5d1c9b634047e5b6a56171d58" id="r_gabea46fc5d1c9b634047e5b6a56171d58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabea46fc5d1c9b634047e5b6a56171d58">ETH_MMCRIR_RFAES_Pos</a>   (6U)</td></tr>
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<tr class="separator:gabea46fc5d1c9b634047e5b6a56171d58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9456fe951f40d50ade33d8a0221d1a6c" id="r_ga9456fe951f40d50ade33d8a0221d1a6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9456fe951f40d50ade33d8a0221d1a6c">ETH_MMCRIR_RFAES_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabea46fc5d1c9b634047e5b6a56171d58">ETH_MMCRIR_RFAES_Pos</a>)</td></tr>
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<tr class="separator:ga9456fe951f40d50ade33d8a0221d1a6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d3859ff0eb6fff48fb98919fe72da15" id="r_ga7d3859ff0eb6fff48fb98919fe72da15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d3859ff0eb6fff48fb98919fe72da15">ETH_MMCRIR_RFAES</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9456fe951f40d50ade33d8a0221d1a6c">ETH_MMCRIR_RFAES_Msk</a> /* Set when Rx alignment error counter reaches half the maximum value */</td></tr>
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<tr class="separator:ga7d3859ff0eb6fff48fb98919fe72da15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d23ef057bd9e8cdb9ed25bffca057b6" id="r_ga8d23ef057bd9e8cdb9ed25bffca057b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d23ef057bd9e8cdb9ed25bffca057b6">ETH_MMCRIR_RFCES_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga8d23ef057bd9e8cdb9ed25bffca057b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga707393c1886b72fdfed379967212a36c" id="r_ga707393c1886b72fdfed379967212a36c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga707393c1886b72fdfed379967212a36c">ETH_MMCRIR_RFCES_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d23ef057bd9e8cdb9ed25bffca057b6">ETH_MMCRIR_RFCES_Pos</a>)</td></tr>
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<tr class="separator:ga707393c1886b72fdfed379967212a36c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac74e35d76820f3c2b0eb743f26023792" id="r_gac74e35d76820f3c2b0eb743f26023792"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac74e35d76820f3c2b0eb743f26023792">ETH_MMCRIR_RFCES</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga707393c1886b72fdfed379967212a36c">ETH_MMCRIR_RFCES_Msk</a> /* Set when Rx <a class="el" href="group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0be4a4f92234a92301b5dea4ef762a83">crc</a> error counter reaches half the maximum value */</td></tr>
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<tr class="separator:gac74e35d76820f3c2b0eb743f26023792"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04a0d740674b1ef700a33c222fcedef6" id="r_ga04a0d740674b1ef700a33c222fcedef6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04a0d740674b1ef700a33c222fcedef6">ETH_MMCTIR_TGFS_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga04a0d740674b1ef700a33c222fcedef6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5361ed811dd1673f55cc0ca20096022a" id="r_ga5361ed811dd1673f55cc0ca20096022a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5361ed811dd1673f55cc0ca20096022a">ETH_MMCTIR_TGFS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga04a0d740674b1ef700a33c222fcedef6">ETH_MMCTIR_TGFS_Pos</a>)</td></tr>
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<tr class="separator:ga5361ed811dd1673f55cc0ca20096022a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5d5dcc69902946befc317ea5719a34c" id="r_gab5d5dcc69902946befc317ea5719a34c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5d5dcc69902946befc317ea5719a34c">ETH_MMCTIR_TGFS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5361ed811dd1673f55cc0ca20096022a">ETH_MMCTIR_TGFS_Msk</a> /* Set when Tx good frame count counter reaches half the maximum value */</td></tr>
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<tr class="separator:gab5d5dcc69902946befc317ea5719a34c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4524f1174601c98399967db0321779f" id="r_gac4524f1174601c98399967db0321779f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4524f1174601c98399967db0321779f">ETH_MMCTIR_TGFMSCS_Pos</a>   (15U)</td></tr>
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<tr class="separator:gac4524f1174601c98399967db0321779f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd5834302f75346a6ce686d331b66cf2" id="r_gabd5834302f75346a6ce686d331b66cf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd5834302f75346a6ce686d331b66cf2">ETH_MMCTIR_TGFMSCS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac4524f1174601c98399967db0321779f">ETH_MMCTIR_TGFMSCS_Pos</a>)</td></tr>
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<tr class="separator:gabd5834302f75346a6ce686d331b66cf2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga796d834a29d0fc6fdc1908ba6db487c3" id="r_ga796d834a29d0fc6fdc1908ba6db487c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga796d834a29d0fc6fdc1908ba6db487c3">ETH_MMCTIR_TGFMSCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd5834302f75346a6ce686d331b66cf2">ETH_MMCTIR_TGFMSCS_Msk</a> /* Set when Tx good multi col counter reaches half the maximum value */</td></tr>
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<tr class="separator:ga796d834a29d0fc6fdc1908ba6db487c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7ac440ef59fd4dae474a77cff93b992" id="r_gae7ac440ef59fd4dae474a77cff93b992"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7ac440ef59fd4dae474a77cff93b992">ETH_MMCTIR_TGFSCS_Pos</a>   (14U)</td></tr>
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<tr class="separator:gae7ac440ef59fd4dae474a77cff93b992"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c0fa21e33672cbf0d9e4404aa236663" id="r_ga1c0fa21e33672cbf0d9e4404aa236663"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c0fa21e33672cbf0d9e4404aa236663">ETH_MMCTIR_TGFSCS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae7ac440ef59fd4dae474a77cff93b992">ETH_MMCTIR_TGFSCS_Pos</a>)</td></tr>
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<tr class="separator:ga1c0fa21e33672cbf0d9e4404aa236663"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe8e920b9e135d3e3ba61e0db758ff19" id="r_gabe8e920b9e135d3e3ba61e0db758ff19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe8e920b9e135d3e3ba61e0db758ff19">ETH_MMCTIR_TGFSCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c0fa21e33672cbf0d9e4404aa236663">ETH_MMCTIR_TGFSCS_Msk</a> /* Set when Tx good single col counter reaches half the maximum value */</td></tr>
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<tr class="separator:gabe8e920b9e135d3e3ba61e0db758ff19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga828d9869b1337d57b50a82873a8c8702" id="r_ga828d9869b1337d57b50a82873a8c8702"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga828d9869b1337d57b50a82873a8c8702">ETH_MMCRIMR_RGUFM_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga828d9869b1337d57b50a82873a8c8702"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga470c1e9e33a19b7da3110acd5e0d9254" id="r_ga470c1e9e33a19b7da3110acd5e0d9254"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga470c1e9e33a19b7da3110acd5e0d9254">ETH_MMCRIMR_RGUFM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga828d9869b1337d57b50a82873a8c8702">ETH_MMCRIMR_RGUFM_Pos</a>)</td></tr>
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<tr class="separator:ga470c1e9e33a19b7da3110acd5e0d9254"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga873a3b1c0a7756647be8455ea6bea8df" id="r_ga873a3b1c0a7756647be8455ea6bea8df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga873a3b1c0a7756647be8455ea6bea8df">ETH_MMCRIMR_RGUFM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga470c1e9e33a19b7da3110acd5e0d9254">ETH_MMCRIMR_RGUFM_Msk</a> /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */</td></tr>
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<tr class="separator:ga873a3b1c0a7756647be8455ea6bea8df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60b9afd54fab9bfc9df42907c63bd685" id="r_ga60b9afd54fab9bfc9df42907c63bd685"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60b9afd54fab9bfc9df42907c63bd685">ETH_MMCRIMR_RFAEM_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga60b9afd54fab9bfc9df42907c63bd685"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5a6a3b036b82adac210651815b69cb0" id="r_gae5a6a3b036b82adac210651815b69cb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5a6a3b036b82adac210651815b69cb0">ETH_MMCRIMR_RFAEM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga60b9afd54fab9bfc9df42907c63bd685">ETH_MMCRIMR_RFAEM_Pos</a>)</td></tr>
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<tr class="separator:gae5a6a3b036b82adac210651815b69cb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c763ea4da19192ab30828971579400c" id="r_ga3c763ea4da19192ab30828971579400c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c763ea4da19192ab30828971579400c">ETH_MMCRIMR_RFAEM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae5a6a3b036b82adac210651815b69cb0">ETH_MMCRIMR_RFAEM_Msk</a> /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */</td></tr>
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<tr class="separator:ga3c763ea4da19192ab30828971579400c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50fbd3537b29ce431a76f1606791183d" id="r_ga50fbd3537b29ce431a76f1606791183d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50fbd3537b29ce431a76f1606791183d">ETH_MMCRIMR_RFCEM_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga50fbd3537b29ce431a76f1606791183d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89a2ad8a6b0429d309799de95538e83f" id="r_ga89a2ad8a6b0429d309799de95538e83f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89a2ad8a6b0429d309799de95538e83f">ETH_MMCRIMR_RFCEM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga50fbd3537b29ce431a76f1606791183d">ETH_MMCRIMR_RFCEM_Pos</a>)</td></tr>
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<tr class="separator:ga89a2ad8a6b0429d309799de95538e83f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3eb72a19c5a4bd34a9ec2c624bd8a8c" id="r_gad3eb72a19c5a4bd34a9ec2c624bd8a8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3eb72a19c5a4bd34a9ec2c624bd8a8c">ETH_MMCRIMR_RFCEM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga89a2ad8a6b0429d309799de95538e83f">ETH_MMCRIMR_RFCEM_Msk</a> /* Mask the interrupt when Rx <a class="el" href="group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0be4a4f92234a92301b5dea4ef762a83">crc</a> error counter reaches half the maximum value */</td></tr>
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<tr class="separator:gad3eb72a19c5a4bd34a9ec2c624bd8a8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1600c79485a47fa57888479428b8b72" id="r_gaa1600c79485a47fa57888479428b8b72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1600c79485a47fa57888479428b8b72">ETH_MMCTIMR_TGFM_Pos</a>   (21U)</td></tr>
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<tr class="separator:gaa1600c79485a47fa57888479428b8b72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65ecd1dd64ba1588e1d83d9896f9e1f0" id="r_ga65ecd1dd64ba1588e1d83d9896f9e1f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga65ecd1dd64ba1588e1d83d9896f9e1f0">ETH_MMCTIMR_TGFM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1600c79485a47fa57888479428b8b72">ETH_MMCTIMR_TGFM_Pos</a>)</td></tr>
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<tr class="separator:ga65ecd1dd64ba1588e1d83d9896f9e1f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae67e69315d2e64d3f4c9b7e65aacf8be" id="r_gae67e69315d2e64d3f4c9b7e65aacf8be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae67e69315d2e64d3f4c9b7e65aacf8be">ETH_MMCTIMR_TGFM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga65ecd1dd64ba1588e1d83d9896f9e1f0">ETH_MMCTIMR_TGFM_Msk</a> /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */</td></tr>
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<tr class="separator:gae67e69315d2e64d3f4c9b7e65aacf8be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga383cc44ef2b8c2cb5cc9a7393a40ea6a" id="r_ga383cc44ef2b8c2cb5cc9a7393a40ea6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga383cc44ef2b8c2cb5cc9a7393a40ea6a">ETH_MMCTIMR_TGFMSCM_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga383cc44ef2b8c2cb5cc9a7393a40ea6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba449564725083891a9fc504321614cf" id="r_gaba449564725083891a9fc504321614cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba449564725083891a9fc504321614cf">ETH_MMCTIMR_TGFMSCM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga383cc44ef2b8c2cb5cc9a7393a40ea6a">ETH_MMCTIMR_TGFMSCM_Pos</a>)</td></tr>
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<tr class="separator:gaba449564725083891a9fc504321614cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20b6f12c07d34bcc014eaa31c6719486" id="r_ga20b6f12c07d34bcc014eaa31c6719486"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20b6f12c07d34bcc014eaa31c6719486">ETH_MMCTIMR_TGFMSCM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaba449564725083891a9fc504321614cf">ETH_MMCTIMR_TGFMSCM_Msk</a> /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */</td></tr>
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<tr class="separator:ga20b6f12c07d34bcc014eaa31c6719486"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcd2ae936752f3c3f6e303ecdbd6ce77" id="r_gafcd2ae936752f3c3f6e303ecdbd6ce77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcd2ae936752f3c3f6e303ecdbd6ce77">ETH_MMCTIMR_TGFSCM_Pos</a>   (14U)</td></tr>
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<tr class="separator:gafcd2ae936752f3c3f6e303ecdbd6ce77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec67763632bc2229fca4167c7db268ce" id="r_gaec67763632bc2229fca4167c7db268ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec67763632bc2229fca4167c7db268ce">ETH_MMCTIMR_TGFSCM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafcd2ae936752f3c3f6e303ecdbd6ce77">ETH_MMCTIMR_TGFSCM_Pos</a>)</td></tr>
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<tr class="separator:gaec67763632bc2229fca4167c7db268ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f41666a525c61be9c88f3d54632ce34" id="r_ga2f41666a525c61be9c88f3d54632ce34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f41666a525c61be9c88f3d54632ce34">ETH_MMCTIMR_TGFSCM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec67763632bc2229fca4167c7db268ce">ETH_MMCTIMR_TGFSCM_Msk</a> /* Mask the interrupt when Tx good single col counter reaches half the maximum value */</td></tr>
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<tr class="separator:ga2f41666a525c61be9c88f3d54632ce34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0a86aabaf7c4a86f0609e67dfc2de72" id="r_gaf0a86aabaf7c4a86f0609e67dfc2de72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0a86aabaf7c4a86f0609e67dfc2de72">ETH_MMCTGFSCCR_TGFSCC_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf0a86aabaf7c4a86f0609e67dfc2de72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac88648ccd808f151b1fc5c72083e4583" id="r_gac88648ccd808f151b1fc5c72083e4583"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac88648ccd808f151b1fc5c72083e4583">ETH_MMCTGFSCCR_TGFSCC_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf0a86aabaf7c4a86f0609e67dfc2de72">ETH_MMCTGFSCCR_TGFSCC_Pos</a>)</td></tr>
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<tr class="separator:gac88648ccd808f151b1fc5c72083e4583"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga784008b2facbc9cab1982e0382057d1c" id="r_ga784008b2facbc9cab1982e0382057d1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga784008b2facbc9cab1982e0382057d1c">ETH_MMCTGFSCCR_TGFSCC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac88648ccd808f151b1fc5c72083e4583">ETH_MMCTGFSCCR_TGFSCC_Msk</a> /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */</td></tr>
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<tr class="separator:ga784008b2facbc9cab1982e0382057d1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3b542ab35eb425c4878c828b365771d" id="r_gaf3b542ab35eb425c4878c828b365771d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3b542ab35eb425c4878c828b365771d">ETH_MMCTGFMSCCR_TGFMSCC_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf3b542ab35eb425c4878c828b365771d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedefca665609c9e6646ee60e8e91a0f9" id="r_gaedefca665609c9e6646ee60e8e91a0f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedefca665609c9e6646ee60e8e91a0f9">ETH_MMCTGFMSCCR_TGFMSCC_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3b542ab35eb425c4878c828b365771d">ETH_MMCTGFMSCCR_TGFMSCC_Pos</a>)</td></tr>
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<tr class="separator:gaedefca665609c9e6646ee60e8e91a0f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4a8b771ec947fe2b944108f72e64fbf" id="r_gad4a8b771ec947fe2b944108f72e64fbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4a8b771ec947fe2b944108f72e64fbf">ETH_MMCTGFMSCCR_TGFMSCC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaedefca665609c9e6646ee60e8e91a0f9">ETH_MMCTGFMSCCR_TGFMSCC_Msk</a> /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */</td></tr>
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<tr class="separator:gad4a8b771ec947fe2b944108f72e64fbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cd5d71ebd3cafd488e7eba99fcfaa3c" id="r_ga7cd5d71ebd3cafd488e7eba99fcfaa3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cd5d71ebd3cafd488e7eba99fcfaa3c">ETH_MMCTGFCR_TGFC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7cd5d71ebd3cafd488e7eba99fcfaa3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fdcd7783b8ea9e2c46c8b7d89a39a47" id="r_ga5fdcd7783b8ea9e2c46c8b7d89a39a47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fdcd7783b8ea9e2c46c8b7d89a39a47">ETH_MMCTGFCR_TGFC_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cd5d71ebd3cafd488e7eba99fcfaa3c">ETH_MMCTGFCR_TGFC_Pos</a>)</td></tr>
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<tr class="separator:ga5fdcd7783b8ea9e2c46c8b7d89a39a47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68b659b400b12fd5c539e24bc115dff2" id="r_ga68b659b400b12fd5c539e24bc115dff2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68b659b400b12fd5c539e24bc115dff2">ETH_MMCTGFCR_TGFC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fdcd7783b8ea9e2c46c8b7d89a39a47">ETH_MMCTGFCR_TGFC_Msk</a> /* Number of good frames transmitted. */</td></tr>
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<tr class="separator:ga68b659b400b12fd5c539e24bc115dff2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1deb0536d536852ede5d1ae0e6710164" id="r_ga1deb0536d536852ede5d1ae0e6710164"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1deb0536d536852ede5d1ae0e6710164">ETH_MMCRFCECR_RFCEC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga1deb0536d536852ede5d1ae0e6710164"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfc0fdeab6719a464423e984ee5d3f96" id="r_gacfc0fdeab6719a464423e984ee5d3f96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfc0fdeab6719a464423e984ee5d3f96">ETH_MMCRFCECR_RFCEC_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1deb0536d536852ede5d1ae0e6710164">ETH_MMCRFCECR_RFCEC_Pos</a>)</td></tr>
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<tr class="separator:gacfc0fdeab6719a464423e984ee5d3f96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ed4e2c7449a522ecbc811252ba1f12b" id="r_ga8ed4e2c7449a522ecbc811252ba1f12b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ed4e2c7449a522ecbc811252ba1f12b">ETH_MMCRFCECR_RFCEC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacfc0fdeab6719a464423e984ee5d3f96">ETH_MMCRFCECR_RFCEC_Msk</a> /* Number of frames received with <a class="el" href="group___peripheral__declaration.html#ga4381bb54c2dbc34500521165aa7b89b1">CRC</a> error. */</td></tr>
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<tr class="separator:ga8ed4e2c7449a522ecbc811252ba1f12b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e4a1a9a81806b92f26c999479b882f7" id="r_ga9e4a1a9a81806b92f26c999479b882f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e4a1a9a81806b92f26c999479b882f7">ETH_MMCRFAECR_RFAEC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga9e4a1a9a81806b92f26c999479b882f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88b5da27b7870336e6dc92e75fbaf7bc" id="r_ga88b5da27b7870336e6dc92e75fbaf7bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88b5da27b7870336e6dc92e75fbaf7bc">ETH_MMCRFAECR_RFAEC_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e4a1a9a81806b92f26c999479b882f7">ETH_MMCRFAECR_RFAEC_Pos</a>)</td></tr>
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<tr class="separator:ga88b5da27b7870336e6dc92e75fbaf7bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac52a70effea67d543da0842e323d2123" id="r_gac52a70effea67d543da0842e323d2123"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac52a70effea67d543da0842e323d2123">ETH_MMCRFAECR_RFAEC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga88b5da27b7870336e6dc92e75fbaf7bc">ETH_MMCRFAECR_RFAEC_Msk</a> /* Number of frames received with alignment (dribble) error */</td></tr>
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<tr class="separator:gac52a70effea67d543da0842e323d2123"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cc3de8b52de82433d96f3621af5e9d6" id="r_ga1cc3de8b52de82433d96f3621af5e9d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc3de8b52de82433d96f3621af5e9d6">ETH_MMCRGUFCR_RGUFC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga1cc3de8b52de82433d96f3621af5e9d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3587339b8bbd30eeff94ee495a7fdbe5" id="r_ga3587339b8bbd30eeff94ee495a7fdbe5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3587339b8bbd30eeff94ee495a7fdbe5">ETH_MMCRGUFCR_RGUFC_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1cc3de8b52de82433d96f3621af5e9d6">ETH_MMCRGUFCR_RGUFC_Pos</a>)</td></tr>
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<tr class="separator:ga3587339b8bbd30eeff94ee495a7fdbe5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2dd42857738b46f748bc6a9109ab0f9e" id="r_ga2dd42857738b46f748bc6a9109ab0f9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dd42857738b46f748bc6a9109ab0f9e">ETH_MMCRGUFCR_RGUFC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3587339b8bbd30eeff94ee495a7fdbe5">ETH_MMCRGUFCR_RGUFC_Msk</a> /* Number of good unicast frames received. */</td></tr>
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<tr class="separator:ga2dd42857738b46f748bc6a9109ab0f9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8547e484fdbe7554b28c4dbbfda55984" id="r_ga8547e484fdbe7554b28c4dbbfda55984"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8547e484fdbe7554b28c4dbbfda55984">ETH_PTPTSCR_TSPFFMAE_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga8547e484fdbe7554b28c4dbbfda55984"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07ddca2b8b3a89a0e844b12b45c0a7a1" id="r_ga07ddca2b8b3a89a0e844b12b45c0a7a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07ddca2b8b3a89a0e844b12b45c0a7a1">ETH_PTPTSCR_TSPFFMAE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8547e484fdbe7554b28c4dbbfda55984">ETH_PTPTSCR_TSPFFMAE_Pos</a>)</td></tr>
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<tr class="separator:ga07ddca2b8b3a89a0e844b12b45c0a7a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e755bd16b5f77c0e04690acf9f422a2" id="r_ga5e755bd16b5f77c0e04690acf9f422a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e755bd16b5f77c0e04690acf9f422a2">ETH_PTPTSCR_TSPFFMAE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga07ddca2b8b3a89a0e844b12b45c0a7a1">ETH_PTPTSCR_TSPFFMAE_Msk</a> /* Time stamp PTP frame filtering MAC address enable */</td></tr>
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<tr class="separator:ga5e755bd16b5f77c0e04690acf9f422a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8dee0d9d9d59df164911cfedd38f832e" id="r_ga8dee0d9d9d59df164911cfedd38f832e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8dee0d9d9d59df164911cfedd38f832e">ETH_PTPTSCR_TSCNT_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga8dee0d9d9d59df164911cfedd38f832e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6eb6cba0cbd040d7d39085c0056a7fc" id="r_gae6eb6cba0cbd040d7d39085c0056a7fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6eb6cba0cbd040d7d39085c0056a7fc">ETH_PTPTSCR_TSCNT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8dee0d9d9d59df164911cfedd38f832e">ETH_PTPTSCR_TSCNT_Pos</a>)</td></tr>
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<tr class="separator:gae6eb6cba0cbd040d7d39085c0056a7fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9d47a61f30e11b514ef0840f3a0fb91" id="r_gaf9d47a61f30e11b514ef0840f3a0fb91"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9d47a61f30e11b514ef0840f3a0fb91">ETH_PTPTSCR_TSCNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae6eb6cba0cbd040d7d39085c0056a7fc">ETH_PTPTSCR_TSCNT_Msk</a> /* Time stamp clock node type */</td></tr>
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<tr class="separator:gaf9d47a61f30e11b514ef0840f3a0fb91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c64bd7449eae554c810dceb920c8f85" id="r_ga9c64bd7449eae554c810dceb920c8f85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c64bd7449eae554c810dceb920c8f85">ETH_PTPTSCR_TSSMRME_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga9c64bd7449eae554c810dceb920c8f85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ea5dd63a69ace6876b589be79c520bc" id="r_ga2ea5dd63a69ace6876b589be79c520bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ea5dd63a69ace6876b589be79c520bc">ETH_PTPTSCR_TSSMRME_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c64bd7449eae554c810dceb920c8f85">ETH_PTPTSCR_TSSMRME_Pos</a>)</td></tr>
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<tr class="separator:ga2ea5dd63a69ace6876b589be79c520bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabfd289fdf804f8ab2240abd611fd36ee" id="r_gabfd289fdf804f8ab2240abd611fd36ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfd289fdf804f8ab2240abd611fd36ee">ETH_PTPTSCR_TSSMRME</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ea5dd63a69ace6876b589be79c520bc">ETH_PTPTSCR_TSSMRME_Msk</a> /* Time stamp snapshot for message relevant to master enable */</td></tr>
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<tr class="separator:gabfd289fdf804f8ab2240abd611fd36ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18e9717d99801dd4c06219ef74516ab9" id="r_ga18e9717d99801dd4c06219ef74516ab9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18e9717d99801dd4c06219ef74516ab9">ETH_PTPTSCR_TSSEME_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga18e9717d99801dd4c06219ef74516ab9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad299e7a85e91581bee8f41d8badd1210" id="r_gad299e7a85e91581bee8f41d8badd1210"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad299e7a85e91581bee8f41d8badd1210">ETH_PTPTSCR_TSSEME_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga18e9717d99801dd4c06219ef74516ab9">ETH_PTPTSCR_TSSEME_Pos</a>)</td></tr>
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<tr class="separator:gad299e7a85e91581bee8f41d8badd1210"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cc8829467d2678bd11d90ec20049cbd" id="r_ga6cc8829467d2678bd11d90ec20049cbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cc8829467d2678bd11d90ec20049cbd">ETH_PTPTSCR_TSSEME</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad299e7a85e91581bee8f41d8badd1210">ETH_PTPTSCR_TSSEME_Msk</a> /* Time stamp snapshot for event message enable */</td></tr>
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<tr class="separator:ga6cc8829467d2678bd11d90ec20049cbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52099e8ee00c7b8d08568e768af469d8" id="r_ga52099e8ee00c7b8d08568e768af469d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52099e8ee00c7b8d08568e768af469d8">ETH_PTPTSCR_TSSIPV4FE_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga52099e8ee00c7b8d08568e768af469d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7584fce8033ccf0a76c1d0571b1a42f7" id="r_ga7584fce8033ccf0a76c1d0571b1a42f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7584fce8033ccf0a76c1d0571b1a42f7">ETH_PTPTSCR_TSSIPV4FE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga52099e8ee00c7b8d08568e768af469d8">ETH_PTPTSCR_TSSIPV4FE_Pos</a>)</td></tr>
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<tr class="separator:ga7584fce8033ccf0a76c1d0571b1a42f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e1ed6b41f9d8c686c294846b4a2fde0" id="r_ga5e1ed6b41f9d8c686c294846b4a2fde0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e1ed6b41f9d8c686c294846b4a2fde0">ETH_PTPTSCR_TSSIPV4FE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7584fce8033ccf0a76c1d0571b1a42f7">ETH_PTPTSCR_TSSIPV4FE_Msk</a> /* Time stamp snapshot for IPv4 frames enable */</td></tr>
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<tr class="separator:ga5e1ed6b41f9d8c686c294846b4a2fde0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9861508d171c1c049ef136ab4c90f4ff" id="r_ga9861508d171c1c049ef136ab4c90f4ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9861508d171c1c049ef136ab4c90f4ff">ETH_PTPTSCR_TSSIPV6FE_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga9861508d171c1c049ef136ab4c90f4ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a1e31f374562426154d02d8e694d0cd" id="r_ga5a1e31f374562426154d02d8e694d0cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a1e31f374562426154d02d8e694d0cd">ETH_PTPTSCR_TSSIPV6FE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9861508d171c1c049ef136ab4c90f4ff">ETH_PTPTSCR_TSSIPV6FE_Pos</a>)</td></tr>
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<tr class="separator:ga5a1e31f374562426154d02d8e694d0cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc3f015ae5624edbc57fd6482c9096b6" id="r_gadc3f015ae5624edbc57fd6482c9096b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc3f015ae5624edbc57fd6482c9096b6">ETH_PTPTSCR_TSSIPV6FE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a1e31f374562426154d02d8e694d0cd">ETH_PTPTSCR_TSSIPV6FE_Msk</a> /* Time stamp snapshot for IPv6 frames enable */</td></tr>
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<tr class="separator:gadc3f015ae5624edbc57fd6482c9096b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34a9bf48d463d0bd45d5c133654c6319" id="r_ga34a9bf48d463d0bd45d5c133654c6319"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34a9bf48d463d0bd45d5c133654c6319">ETH_PTPTSCR_TSSPTPOEFE_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga34a9bf48d463d0bd45d5c133654c6319"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b84221fe479a965fcc665a05e0d2190" id="r_ga3b84221fe479a965fcc665a05e0d2190"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b84221fe479a965fcc665a05e0d2190">ETH_PTPTSCR_TSSPTPOEFE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34a9bf48d463d0bd45d5c133654c6319">ETH_PTPTSCR_TSSPTPOEFE_Pos</a>)</td></tr>
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<tr class="separator:ga3b84221fe479a965fcc665a05e0d2190"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga615bc0bc378392c6a508bb9e28826b72" id="r_ga615bc0bc378392c6a508bb9e28826b72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga615bc0bc378392c6a508bb9e28826b72">ETH_PTPTSCR_TSSPTPOEFE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b84221fe479a965fcc665a05e0d2190">ETH_PTPTSCR_TSSPTPOEFE_Msk</a> /* Time stamp snapshot for PTP over ethernet frames enable */</td></tr>
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<tr class="separator:ga615bc0bc378392c6a508bb9e28826b72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae466858afa76b1a56f3da3221352ae5e" id="r_gae466858afa76b1a56f3da3221352ae5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae466858afa76b1a56f3da3221352ae5e">ETH_PTPTSCR_TSPTPPSV2E_Pos</a>   (10U)</td></tr>
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<tr class="separator:gae466858afa76b1a56f3da3221352ae5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbc463e7a55bfd585e2f87095164ed42" id="r_gadbc463e7a55bfd585e2f87095164ed42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbc463e7a55bfd585e2f87095164ed42">ETH_PTPTSCR_TSPTPPSV2E_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae466858afa76b1a56f3da3221352ae5e">ETH_PTPTSCR_TSPTPPSV2E_Pos</a>)</td></tr>
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<tr class="separator:gadbc463e7a55bfd585e2f87095164ed42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf06151b1fa7d4437bb664964de1ee12a" id="r_gaf06151b1fa7d4437bb664964de1ee12a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf06151b1fa7d4437bb664964de1ee12a">ETH_PTPTSCR_TSPTPPSV2E</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadbc463e7a55bfd585e2f87095164ed42">ETH_PTPTSCR_TSPTPPSV2E_Msk</a> /* Time stamp PTP packet snooping for version2 format enable */</td></tr>
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<tr class="separator:gaf06151b1fa7d4437bb664964de1ee12a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7efbf85f1370fa44e7655bd0c4c6f830" id="r_ga7efbf85f1370fa44e7655bd0c4c6f830"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7efbf85f1370fa44e7655bd0c4c6f830">ETH_PTPTSCR_TSSSR_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga7efbf85f1370fa44e7655bd0c4c6f830"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0770634e7a6a880384072a2974859d6e" id="r_ga0770634e7a6a880384072a2974859d6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0770634e7a6a880384072a2974859d6e">ETH_PTPTSCR_TSSSR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7efbf85f1370fa44e7655bd0c4c6f830">ETH_PTPTSCR_TSSSR_Pos</a>)</td></tr>
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<tr class="separator:ga0770634e7a6a880384072a2974859d6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad653b859283fac4ed67f027d8af17dec" id="r_gad653b859283fac4ed67f027d8af17dec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad653b859283fac4ed67f027d8af17dec">ETH_PTPTSCR_TSSSR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0770634e7a6a880384072a2974859d6e">ETH_PTPTSCR_TSSSR_Msk</a> /* Time stamp Sub-seconds rollover */</td></tr>
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<tr class="separator:gad653b859283fac4ed67f027d8af17dec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5eaf028640c2b06b2debb0f1b16124b" id="r_gaf5eaf028640c2b06b2debb0f1b16124b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5eaf028640c2b06b2debb0f1b16124b">ETH_PTPTSCR_TSSARFE_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaf5eaf028640c2b06b2debb0f1b16124b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6e14c1d9f9e1b4882f0c4380f18a4a8" id="r_gaa6e14c1d9f9e1b4882f0c4380f18a4a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e14c1d9f9e1b4882f0c4380f18a4a8">ETH_PTPTSCR_TSSARFE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5eaf028640c2b06b2debb0f1b16124b">ETH_PTPTSCR_TSSARFE_Pos</a>)</td></tr>
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<tr class="separator:gaa6e14c1d9f9e1b4882f0c4380f18a4a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga553bc2c98222a09ce2a60fb0c098763e" id="r_ga553bc2c98222a09ce2a60fb0c098763e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga553bc2c98222a09ce2a60fb0c098763e">ETH_PTPTSCR_TSSARFE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e14c1d9f9e1b4882f0c4380f18a4a8">ETH_PTPTSCR_TSSARFE_Msk</a> /* Time stamp snapshot for all received frames enable */</td></tr>
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<tr class="separator:ga553bc2c98222a09ce2a60fb0c098763e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga764ac2859fe42ac27c1c462c9889e1f1" id="r_ga764ac2859fe42ac27c1c462c9889e1f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga764ac2859fe42ac27c1c462c9889e1f1">ETH_PTPTSCR_TSARU_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga764ac2859fe42ac27c1c462c9889e1f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae38f60d94f4dd3d08f4ef813911adf79" id="r_gae38f60d94f4dd3d08f4ef813911adf79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae38f60d94f4dd3d08f4ef813911adf79">ETH_PTPTSCR_TSARU_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga764ac2859fe42ac27c1c462c9889e1f1">ETH_PTPTSCR_TSARU_Pos</a>)</td></tr>
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<tr class="separator:gae38f60d94f4dd3d08f4ef813911adf79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19406b465c944a3e465a8077cbfbf39e" id="r_ga19406b465c944a3e465a8077cbfbf39e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19406b465c944a3e465a8077cbfbf39e">ETH_PTPTSCR_TSARU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae38f60d94f4dd3d08f4ef813911adf79">ETH_PTPTSCR_TSARU_Msk</a> /* Addend register update */</td></tr>
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<tr class="separator:ga19406b465c944a3e465a8077cbfbf39e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9464fe8bfc44323aee790eb0768f6ab" id="r_gad9464fe8bfc44323aee790eb0768f6ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad9464fe8bfc44323aee790eb0768f6ab">ETH_PTPTSCR_TSITE_Pos</a>   (4U)</td></tr>
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<tr class="separator:gad9464fe8bfc44323aee790eb0768f6ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3731fcd0a402ff13734764182b29c99a" id="r_ga3731fcd0a402ff13734764182b29c99a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3731fcd0a402ff13734764182b29c99a">ETH_PTPTSCR_TSITE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad9464fe8bfc44323aee790eb0768f6ab">ETH_PTPTSCR_TSITE_Pos</a>)</td></tr>
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<tr class="separator:ga3731fcd0a402ff13734764182b29c99a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44670d6793da45549fb7ea38c3523783" id="r_ga44670d6793da45549fb7ea38c3523783"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44670d6793da45549fb7ea38c3523783">ETH_PTPTSCR_TSITE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3731fcd0a402ff13734764182b29c99a">ETH_PTPTSCR_TSITE_Msk</a> /* Time stamp interrupt trigger enable */</td></tr>
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<tr class="separator:ga44670d6793da45549fb7ea38c3523783"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga145b98f9a8b88b60ea10329203fbb745" id="r_ga145b98f9a8b88b60ea10329203fbb745"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga145b98f9a8b88b60ea10329203fbb745">ETH_PTPTSCR_TSSTU_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga145b98f9a8b88b60ea10329203fbb745"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8573e45d80d88e5c90149584b3692421" id="r_ga8573e45d80d88e5c90149584b3692421"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8573e45d80d88e5c90149584b3692421">ETH_PTPTSCR_TSSTU_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga145b98f9a8b88b60ea10329203fbb745">ETH_PTPTSCR_TSSTU_Pos</a>)</td></tr>
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<tr class="separator:ga8573e45d80d88e5c90149584b3692421"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga589a3a200c3f68543f556432cdb98075" id="r_ga589a3a200c3f68543f556432cdb98075"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga589a3a200c3f68543f556432cdb98075">ETH_PTPTSCR_TSSTU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8573e45d80d88e5c90149584b3692421">ETH_PTPTSCR_TSSTU_Msk</a> /* Time stamp update */</td></tr>
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<tr class="separator:ga589a3a200c3f68543f556432cdb98075"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6405b2ac005034ee0ea0642f19efad4b" id="r_ga6405b2ac005034ee0ea0642f19efad4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6405b2ac005034ee0ea0642f19efad4b">ETH_PTPTSCR_TSSTI_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga6405b2ac005034ee0ea0642f19efad4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88c53dbf12851d2e912b3748de382452" id="r_ga88c53dbf12851d2e912b3748de382452"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88c53dbf12851d2e912b3748de382452">ETH_PTPTSCR_TSSTI_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6405b2ac005034ee0ea0642f19efad4b">ETH_PTPTSCR_TSSTI_Pos</a>)</td></tr>
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<tr class="separator:ga88c53dbf12851d2e912b3748de382452"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad484f7a6e6df6b3f2131d3bfb3dba856" id="r_gad484f7a6e6df6b3f2131d3bfb3dba856"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad484f7a6e6df6b3f2131d3bfb3dba856">ETH_PTPTSCR_TSSTI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga88c53dbf12851d2e912b3748de382452">ETH_PTPTSCR_TSSTI_Msk</a> /* Time stamp initialize */</td></tr>
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<tr class="separator:gad484f7a6e6df6b3f2131d3bfb3dba856"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga428f2c4ef53f655e679732f632c6f490" id="r_ga428f2c4ef53f655e679732f632c6f490"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga428f2c4ef53f655e679732f632c6f490">ETH_PTPTSCR_TSFCU_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga428f2c4ef53f655e679732f632c6f490"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29d78884eed541cedaf8b46b6914899d" id="r_ga29d78884eed541cedaf8b46b6914899d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29d78884eed541cedaf8b46b6914899d">ETH_PTPTSCR_TSFCU_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga428f2c4ef53f655e679732f632c6f490">ETH_PTPTSCR_TSFCU_Pos</a>)</td></tr>
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<tr class="separator:ga29d78884eed541cedaf8b46b6914899d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e58e22d5668ebf118f67df5eb13e834" id="r_ga9e58e22d5668ebf118f67df5eb13e834"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e58e22d5668ebf118f67df5eb13e834">ETH_PTPTSCR_TSFCU</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga29d78884eed541cedaf8b46b6914899d">ETH_PTPTSCR_TSFCU_Msk</a> /* Time stamp fine or coarse update */</td></tr>
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<tr class="separator:ga9e58e22d5668ebf118f67df5eb13e834"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga228aab4066179e8e0a8bb44d5a2205aa" id="r_ga228aab4066179e8e0a8bb44d5a2205aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga228aab4066179e8e0a8bb44d5a2205aa">ETH_PTPTSCR_TSE_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga228aab4066179e8e0a8bb44d5a2205aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa354e48ec338c1aeb40ec642b98b49e5" id="r_gaa354e48ec338c1aeb40ec642b98b49e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa354e48ec338c1aeb40ec642b98b49e5">ETH_PTPTSCR_TSE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga228aab4066179e8e0a8bb44d5a2205aa">ETH_PTPTSCR_TSE_Pos</a>)</td></tr>
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<tr class="separator:gaa354e48ec338c1aeb40ec642b98b49e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c1129b1d368bdef0c5c07d9acf8edd7" id="r_ga9c1129b1d368bdef0c5c07d9acf8edd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c1129b1d368bdef0c5c07d9acf8edd7">ETH_PTPTSCR_TSE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa354e48ec338c1aeb40ec642b98b49e5">ETH_PTPTSCR_TSE_Msk</a> /* Time stamp enable */</td></tr>
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<tr class="separator:ga9c1129b1d368bdef0c5c07d9acf8edd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3855f0e2e250856a890efb4a29b68c6" id="r_gac3855f0e2e250856a890efb4a29b68c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3855f0e2e250856a890efb4a29b68c6">ETH_PTPSSIR_STSSI_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac3855f0e2e250856a890efb4a29b68c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fef6f1da60d4682780fd1ef4cf3435f" id="r_ga0fef6f1da60d4682780fd1ef4cf3435f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fef6f1da60d4682780fd1ef4cf3435f">ETH_PTPSSIR_STSSI_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3855f0e2e250856a890efb4a29b68c6">ETH_PTPSSIR_STSSI_Pos</a>)</td></tr>
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<tr class="separator:ga0fef6f1da60d4682780fd1ef4cf3435f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab51d59cd679f65a179fe5e271b63a22c" id="r_gab51d59cd679f65a179fe5e271b63a22c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab51d59cd679f65a179fe5e271b63a22c">ETH_PTPSSIR_STSSI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0fef6f1da60d4682780fd1ef4cf3435f">ETH_PTPSSIR_STSSI_Msk</a> /* System time Sub-second increment value */</td></tr>
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<tr class="separator:gab51d59cd679f65a179fe5e271b63a22c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e50177b2fb9ba8ac977b0dec45787fc" id="r_ga0e50177b2fb9ba8ac977b0dec45787fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e50177b2fb9ba8ac977b0dec45787fc">ETH_PTPTSHR_STS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0e50177b2fb9ba8ac977b0dec45787fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac54fba4639ea8278ac2679ecf5693f11" id="r_gac54fba4639ea8278ac2679ecf5693f11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac54fba4639ea8278ac2679ecf5693f11">ETH_PTPTSHR_STS_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e50177b2fb9ba8ac977b0dec45787fc">ETH_PTPTSHR_STS_Pos</a>)</td></tr>
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<tr class="separator:gac54fba4639ea8278ac2679ecf5693f11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4e066e9342e4f16955c1506d64b26d5" id="r_gad4e066e9342e4f16955c1506d64b26d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4e066e9342e4f16955c1506d64b26d5">ETH_PTPTSHR_STS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac54fba4639ea8278ac2679ecf5693f11">ETH_PTPTSHR_STS_Msk</a> /* System Time second */</td></tr>
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<tr class="separator:gad4e066e9342e4f16955c1506d64b26d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7678974b934e9b460c8f2525a2f0ead" id="r_gac7678974b934e9b460c8f2525a2f0ead"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac7678974b934e9b460c8f2525a2f0ead">ETH_PTPTSLR_STPNS_Pos</a>   (31U)</td></tr>
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<tr class="separator:gac7678974b934e9b460c8f2525a2f0ead"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57b0d4d7480472e548d2745b71c73884" id="r_ga57b0d4d7480472e548d2745b71c73884"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57b0d4d7480472e548d2745b71c73884">ETH_PTPTSLR_STPNS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac7678974b934e9b460c8f2525a2f0ead">ETH_PTPTSLR_STPNS_Pos</a>)</td></tr>
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<tr class="separator:ga57b0d4d7480472e548d2745b71c73884"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5db7e66364e5d2022b53561fc6fcbfc6" id="r_ga5db7e66364e5d2022b53561fc6fcbfc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5db7e66364e5d2022b53561fc6fcbfc6">ETH_PTPTSLR_STPNS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57b0d4d7480472e548d2745b71c73884">ETH_PTPTSLR_STPNS_Msk</a> /* System Time Positive or negative time */</td></tr>
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<tr class="separator:ga5db7e66364e5d2022b53561fc6fcbfc6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa00f00cc105d644a374cd3ec55f191d6" id="r_gaa00f00cc105d644a374cd3ec55f191d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa00f00cc105d644a374cd3ec55f191d6">ETH_PTPTSLR_STSS_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa00f00cc105d644a374cd3ec55f191d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ea6ac5920c1f09cda85a6efe885d159" id="r_ga5ea6ac5920c1f09cda85a6efe885d159"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ea6ac5920c1f09cda85a6efe885d159">ETH_PTPTSLR_STSS_Msk</a>   (0x7FFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa00f00cc105d644a374cd3ec55f191d6">ETH_PTPTSLR_STSS_Pos</a>)</td></tr>
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<tr class="separator:ga5ea6ac5920c1f09cda85a6efe885d159"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56d984d62fb4bfdc0677734863135ade" id="r_ga56d984d62fb4bfdc0677734863135ade"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56d984d62fb4bfdc0677734863135ade">ETH_PTPTSLR_STSS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5ea6ac5920c1f09cda85a6efe885d159">ETH_PTPTSLR_STSS_Msk</a> /* System Time sub-seconds */</td></tr>
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<tr class="separator:ga56d984d62fb4bfdc0677734863135ade"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d89a6613925b5dd9ec20932d66fdb44" id="r_ga9d89a6613925b5dd9ec20932d66fdb44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d89a6613925b5dd9ec20932d66fdb44">ETH_PTPTSHUR_TSUS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga9d89a6613925b5dd9ec20932d66fdb44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b1af8c724a3bb0fbbc8d796581df651" id="r_ga5b1af8c724a3bb0fbbc8d796581df651"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b1af8c724a3bb0fbbc8d796581df651">ETH_PTPTSHUR_TSUS_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d89a6613925b5dd9ec20932d66fdb44">ETH_PTPTSHUR_TSUS_Pos</a>)</td></tr>
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<tr class="separator:ga5b1af8c724a3bb0fbbc8d796581df651"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga790cfc8e9a003b703e25d158e3490066" id="r_ga790cfc8e9a003b703e25d158e3490066"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga790cfc8e9a003b703e25d158e3490066">ETH_PTPTSHUR_TSUS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b1af8c724a3bb0fbbc8d796581df651">ETH_PTPTSHUR_TSUS_Msk</a> /* Time stamp update seconds */</td></tr>
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<tr class="separator:ga790cfc8e9a003b703e25d158e3490066"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf93e24b10684dff6d8a03817019e807c" id="r_gaf93e24b10684dff6d8a03817019e807c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf93e24b10684dff6d8a03817019e807c">ETH_PTPTSLUR_TSUPNS_Pos</a>   (31U)</td></tr>
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<tr class="separator:gaf93e24b10684dff6d8a03817019e807c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79eba1ff6e2e10261b485928bdaf9826" id="r_ga79eba1ff6e2e10261b485928bdaf9826"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79eba1ff6e2e10261b485928bdaf9826">ETH_PTPTSLUR_TSUPNS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf93e24b10684dff6d8a03817019e807c">ETH_PTPTSLUR_TSUPNS_Pos</a>)</td></tr>
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<tr class="separator:ga79eba1ff6e2e10261b485928bdaf9826"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae03c675fcd71d14198665cb8c5956086" id="r_gae03c675fcd71d14198665cb8c5956086"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae03c675fcd71d14198665cb8c5956086">ETH_PTPTSLUR_TSUPNS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga79eba1ff6e2e10261b485928bdaf9826">ETH_PTPTSLUR_TSUPNS_Msk</a> /* Time stamp update Positive or negative time */</td></tr>
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<tr class="separator:gae03c675fcd71d14198665cb8c5956086"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f59fc90e2a93ca826f9a221a0543254" id="r_ga5f59fc90e2a93ca826f9a221a0543254"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f59fc90e2a93ca826f9a221a0543254">ETH_PTPTSLUR_TSUSS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5f59fc90e2a93ca826f9a221a0543254"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40c328002f73284b6216df8d8390a040" id="r_ga40c328002f73284b6216df8d8390a040"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40c328002f73284b6216df8d8390a040">ETH_PTPTSLUR_TSUSS_Msk</a>   (0x7FFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f59fc90e2a93ca826f9a221a0543254">ETH_PTPTSLUR_TSUSS_Pos</a>)</td></tr>
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<tr class="separator:ga40c328002f73284b6216df8d8390a040"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17fdf1f11b40e68b24a27eb2c60f50b1" id="r_ga17fdf1f11b40e68b24a27eb2c60f50b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17fdf1f11b40e68b24a27eb2c60f50b1">ETH_PTPTSLUR_TSUSS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga40c328002f73284b6216df8d8390a040">ETH_PTPTSLUR_TSUSS_Msk</a> /* Time stamp update sub-seconds */</td></tr>
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<tr class="separator:ga17fdf1f11b40e68b24a27eb2c60f50b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga142199a59a370ae94ef43febe1f0e27b" id="r_ga142199a59a370ae94ef43febe1f0e27b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga142199a59a370ae94ef43febe1f0e27b">ETH_PTPTSAR_TSA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga142199a59a370ae94ef43febe1f0e27b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f67b7a220cf80fec5ea4c9cd642fef3" id="r_ga3f67b7a220cf80fec5ea4c9cd642fef3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f67b7a220cf80fec5ea4c9cd642fef3">ETH_PTPTSAR_TSA_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga142199a59a370ae94ef43febe1f0e27b">ETH_PTPTSAR_TSA_Pos</a>)</td></tr>
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<tr class="separator:ga3f67b7a220cf80fec5ea4c9cd642fef3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab944b9f1ceff57bb31beb689a19537c4" id="r_gab944b9f1ceff57bb31beb689a19537c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab944b9f1ceff57bb31beb689a19537c4">ETH_PTPTSAR_TSA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f67b7a220cf80fec5ea4c9cd642fef3">ETH_PTPTSAR_TSA_Msk</a> /* Time stamp addend */</td></tr>
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<tr class="separator:gab944b9f1ceff57bb31beb689a19537c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a1209cf78ca23936fc172c225bcd13d" id="r_ga3a1209cf78ca23936fc172c225bcd13d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a1209cf78ca23936fc172c225bcd13d">ETH_PTPTTHR_TTSH_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3a1209cf78ca23936fc172c225bcd13d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80aac932c3b5b9dc4cffb160f27431af" id="r_ga80aac932c3b5b9dc4cffb160f27431af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80aac932c3b5b9dc4cffb160f27431af">ETH_PTPTTHR_TTSH_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a1209cf78ca23936fc172c225bcd13d">ETH_PTPTTHR_TTSH_Pos</a>)</td></tr>
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<tr class="separator:ga80aac932c3b5b9dc4cffb160f27431af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21db9a6b88a17aef32ccce70f017329e" id="r_ga21db9a6b88a17aef32ccce70f017329e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21db9a6b88a17aef32ccce70f017329e">ETH_PTPTTHR_TTSH</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga80aac932c3b5b9dc4cffb160f27431af">ETH_PTPTTHR_TTSH_Msk</a> /* Target time stamp high */</td></tr>
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<tr class="separator:ga21db9a6b88a17aef32ccce70f017329e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafccab56e7239c4fc0c2c260ce3da9567" id="r_gafccab56e7239c4fc0c2c260ce3da9567"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafccab56e7239c4fc0c2c260ce3da9567">ETH_PTPTTLR_TTSL_Pos</a>   (0U)</td></tr>
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<tr class="separator:gafccab56e7239c4fc0c2c260ce3da9567"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7606deb781bd37b7ee59b6adcf9bc58f" id="r_ga7606deb781bd37b7ee59b6adcf9bc58f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7606deb781bd37b7ee59b6adcf9bc58f">ETH_PTPTTLR_TTSL_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafccab56e7239c4fc0c2c260ce3da9567">ETH_PTPTTLR_TTSL_Pos</a>)</td></tr>
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<tr class="memitem:ga61e7a9592215e36a8db010374f57d210" id="r_ga61e7a9592215e36a8db010374f57d210"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61e7a9592215e36a8db010374f57d210">ETH_PTPTTLR_TTSL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7606deb781bd37b7ee59b6adcf9bc58f">ETH_PTPTTLR_TTSL_Msk</a> /* Target time stamp low */</td></tr>
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<tr class="memitem:ga0a68e0dabcaf5d552e664091d33bf4a0" id="r_ga0a68e0dabcaf5d552e664091d33bf4a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a68e0dabcaf5d552e664091d33bf4a0">ETH_PTPTSSR_TSTTR_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga0a68e0dabcaf5d552e664091d33bf4a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6231f5b648b131af03c3eac1c3a01182" id="r_ga6231f5b648b131af03c3eac1c3a01182"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6231f5b648b131af03c3eac1c3a01182">ETH_PTPTSSR_TSTTR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0a68e0dabcaf5d552e664091d33bf4a0">ETH_PTPTSSR_TSTTR_Pos</a>)</td></tr>
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<tr class="separator:ga6231f5b648b131af03c3eac1c3a01182"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga491e96ebf2d049900f049cead51f320a" id="r_ga491e96ebf2d049900f049cead51f320a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga491e96ebf2d049900f049cead51f320a">ETH_PTPTSSR_TSTTR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6231f5b648b131af03c3eac1c3a01182">ETH_PTPTSSR_TSTTR_Msk</a> /* Time stamp target time reached */</td></tr>
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<tr class="separator:ga491e96ebf2d049900f049cead51f320a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf46c9260e7e81f588ddc44c647ea9275" id="r_gaf46c9260e7e81f588ddc44c647ea9275"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf46c9260e7e81f588ddc44c647ea9275">ETH_PTPTSSR_TSSO_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaf46c9260e7e81f588ddc44c647ea9275"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga838b3f40f55f1ec42e054e2bc13af891" id="r_ga838b3f40f55f1ec42e054e2bc13af891"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga838b3f40f55f1ec42e054e2bc13af891">ETH_PTPTSSR_TSSO_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf46c9260e7e81f588ddc44c647ea9275">ETH_PTPTSSR_TSSO_Pos</a>)</td></tr>
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<tr class="separator:ga838b3f40f55f1ec42e054e2bc13af891"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa245035f820779346591bee91d96b473" id="r_gaa245035f820779346591bee91d96b473"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa245035f820779346591bee91d96b473">ETH_PTPTSSR_TSSO</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga838b3f40f55f1ec42e054e2bc13af891">ETH_PTPTSSR_TSSO_Msk</a> /* Time stamp seconds overflow */</td></tr>
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<tr class="separator:gaa245035f820779346591bee91d96b473"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6754f2bead2bd9b49eeba732d109220e" id="r_ga6754f2bead2bd9b49eeba732d109220e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6754f2bead2bd9b49eeba732d109220e">ETH_DMABMR_MB_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga6754f2bead2bd9b49eeba732d109220e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafccc7781fcfe97b198cd1dc91959e0e9" id="r_gafccc7781fcfe97b198cd1dc91959e0e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafccc7781fcfe97b198cd1dc91959e0e9">ETH_DMABMR_MB_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6754f2bead2bd9b49eeba732d109220e">ETH_DMABMR_MB_Pos</a>)</td></tr>
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<tr class="separator:gafccc7781fcfe97b198cd1dc91959e0e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02d5b9592d4cb586352b11bc6ed179ff" id="r_ga02d5b9592d4cb586352b11bc6ed179ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02d5b9592d4cb586352b11bc6ed179ff">ETH_DMABMR_MB</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafccc7781fcfe97b198cd1dc91959e0e9">ETH_DMABMR_MB_Msk</a> /* Mixed Burst */</td></tr>
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<tr class="separator:ga02d5b9592d4cb586352b11bc6ed179ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e542f89aee68bd91d90d7546db209de" id="r_ga7e542f89aee68bd91d90d7546db209de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e542f89aee68bd91d90d7546db209de">ETH_DMABMR_AAB_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga7e542f89aee68bd91d90d7546db209de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f5eca1e6932299715114700f0015d2e" id="r_ga5f5eca1e6932299715114700f0015d2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f5eca1e6932299715114700f0015d2e">ETH_DMABMR_AAB_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e542f89aee68bd91d90d7546db209de">ETH_DMABMR_AAB_Pos</a>)</td></tr>
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<tr class="separator:ga5f5eca1e6932299715114700f0015d2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacec4fa12c34dc8fcacc2271f09ed0cbd" id="r_gacec4fa12c34dc8fcacc2271f09ed0cbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacec4fa12c34dc8fcacc2271f09ed0cbd">ETH_DMABMR_AAB</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f5eca1e6932299715114700f0015d2e">ETH_DMABMR_AAB_Msk</a> /* Address-Aligned beats */</td></tr>
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<tr class="separator:gacec4fa12c34dc8fcacc2271f09ed0cbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fabf93610f531f3f2f1f4a601fe2498" id="r_ga4fabf93610f531f3f2f1f4a601fe2498"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fabf93610f531f3f2f1f4a601fe2498">ETH_DMABMR_FPM_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga4fabf93610f531f3f2f1f4a601fe2498"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2fdb196d2e2aba0246e12581b915f783" id="r_ga2fdb196d2e2aba0246e12581b915f783"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fdb196d2e2aba0246e12581b915f783">ETH_DMABMR_FPM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4fabf93610f531f3f2f1f4a601fe2498">ETH_DMABMR_FPM_Pos</a>)</td></tr>
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<tr class="separator:ga2fdb196d2e2aba0246e12581b915f783"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcb4414b6567f8b131712e0dc5c62beb" id="r_gafcb4414b6567f8b131712e0dc5c62beb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcb4414b6567f8b131712e0dc5c62beb">ETH_DMABMR_FPM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2fdb196d2e2aba0246e12581b915f783">ETH_DMABMR_FPM_Msk</a> /* 4xPBL mode */</td></tr>
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<tr class="separator:gafcb4414b6567f8b131712e0dc5c62beb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9c6b22e49c424a0c8380a6ac0b1716a" id="r_gae9c6b22e49c424a0c8380a6ac0b1716a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9c6b22e49c424a0c8380a6ac0b1716a">ETH_DMABMR_USP_Pos</a>   (23U)</td></tr>
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<tr class="separator:gae9c6b22e49c424a0c8380a6ac0b1716a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9f99d342b5c91127b4ab8a4b34ab19f8" id="r_ga9f99d342b5c91127b4ab8a4b34ab19f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9f99d342b5c91127b4ab8a4b34ab19f8">ETH_DMABMR_USP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9c6b22e49c424a0c8380a6ac0b1716a">ETH_DMABMR_USP_Pos</a>)</td></tr>
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<tr class="separator:ga9f99d342b5c91127b4ab8a4b34ab19f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91e71c4054613222a8610bde0b191d00" id="r_ga91e71c4054613222a8610bde0b191d00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91e71c4054613222a8610bde0b191d00">ETH_DMABMR_USP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9f99d342b5c91127b4ab8a4b34ab19f8">ETH_DMABMR_USP_Msk</a> /* Use separate PBL */</td></tr>
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<tr class="separator:ga91e71c4054613222a8610bde0b191d00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e6b2716719f507d7cb5e7d140ac6fb9" id="r_ga9e6b2716719f507d7cb5e7d140ac6fb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e6b2716719f507d7cb5e7d140ac6fb9">ETH_DMABMR_RDP_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga9e6b2716719f507d7cb5e7d140ac6fb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45be619f0c8fa338658381e077b36fbb" id="r_ga45be619f0c8fa338658381e077b36fbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45be619f0c8fa338658381e077b36fbb">ETH_DMABMR_RDP_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e6b2716719f507d7cb5e7d140ac6fb9">ETH_DMABMR_RDP_Pos</a>)</td></tr>
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<tr class="separator:ga45be619f0c8fa338658381e077b36fbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f8be5fad8f704e418e3d799d4c6d3d1" id="r_ga4f8be5fad8f704e418e3d799d4c6d3d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f8be5fad8f704e418e3d799d4c6d3d1">ETH_DMABMR_RDP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45be619f0c8fa338658381e077b36fbb">ETH_DMABMR_RDP_Msk</a> /* RxDMA PBL */</td></tr>
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<tr class="separator:ga4f8be5fad8f704e418e3d799d4c6d3d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac56caa9d3b3a4300bd1aa0405131d7b9" id="r_gac56caa9d3b3a4300bd1aa0405131d7b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac56caa9d3b3a4300bd1aa0405131d7b9">ETH_DMABMR_RDP_1Beat</a>   0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */</td></tr>
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<tr class="separator:gac56caa9d3b3a4300bd1aa0405131d7b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf9bcd9870547bd6f454db6667ccdecb" id="r_gaaf9bcd9870547bd6f454db6667ccdecb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf9bcd9870547bd6f454db6667ccdecb">ETH_DMABMR_RDP_2Beat</a>   0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */</td></tr>
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<tr class="separator:gaaf9bcd9870547bd6f454db6667ccdecb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf514499cdf6581fdcff5eaad5e6ab12f" id="r_gaf514499cdf6581fdcff5eaad5e6ab12f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf514499cdf6581fdcff5eaad5e6ab12f">ETH_DMABMR_RDP_4Beat</a>   0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */</td></tr>
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<tr class="separator:gaf514499cdf6581fdcff5eaad5e6ab12f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5b0089dafe1c8c2410127e93ea40681" id="r_gad5b0089dafe1c8c2410127e93ea40681"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5b0089dafe1c8c2410127e93ea40681">ETH_DMABMR_RDP_8Beat</a>   0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */</td></tr>
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<tr class="separator:gad5b0089dafe1c8c2410127e93ea40681"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ed1d26d7d55828eadcea86f774c5dd3" id="r_ga2ed1d26d7d55828eadcea86f774c5dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ed1d26d7d55828eadcea86f774c5dd3">ETH_DMABMR_RDP_16Beat</a>   0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */</td></tr>
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<tr class="separator:ga2ed1d26d7d55828eadcea86f774c5dd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3636f50cc2841e5a945f7e908420cbd5" id="r_ga3636f50cc2841e5a945f7e908420cbd5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3636f50cc2841e5a945f7e908420cbd5">ETH_DMABMR_RDP_32Beat</a>   0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */</td></tr>
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<tr class="separator:ga3636f50cc2841e5a945f7e908420cbd5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a8ea3f877aaa74f8ea2d1a788ae3180" id="r_ga2a8ea3f877aaa74f8ea2d1a788ae3180"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a8ea3f877aaa74f8ea2d1a788ae3180">ETH_DMABMR_RDP_4xPBL_4Beat</a>   0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */</td></tr>
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<tr class="separator:ga2a8ea3f877aaa74f8ea2d1a788ae3180"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f0258c404d957601ae069a77c82d39b" id="r_ga7f0258c404d957601ae069a77c82d39b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f0258c404d957601ae069a77c82d39b">ETH_DMABMR_RDP_4xPBL_8Beat</a>   0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */</td></tr>
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<tr class="separator:ga7f0258c404d957601ae069a77c82d39b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ebf97fad14c750a087ed09210e42a1b" id="r_ga3ebf97fad14c750a087ed09210e42a1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ebf97fad14c750a087ed09210e42a1b">ETH_DMABMR_RDP_4xPBL_16Beat</a>   0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */</td></tr>
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<tr class="separator:ga3ebf97fad14c750a087ed09210e42a1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5e2d5606e920b57f303f032b0bad32b" id="r_gaf5e2d5606e920b57f303f032b0bad32b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5e2d5606e920b57f303f032b0bad32b">ETH_DMABMR_RDP_4xPBL_32Beat</a>   0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */</td></tr>
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<tr class="separator:gaf5e2d5606e920b57f303f032b0bad32b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1eab5835a2d15d943d5a8fbed274478" id="r_gad1eab5835a2d15d943d5a8fbed274478"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1eab5835a2d15d943d5a8fbed274478">ETH_DMABMR_RDP_4xPBL_64Beat</a>   0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */</td></tr>
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<tr class="memitem:ga5ea2c20d00d2428c5f6a8fe4d7ebb392" id="r_ga5ea2c20d00d2428c5f6a8fe4d7ebb392"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ea2c20d00d2428c5f6a8fe4d7ebb392">ETH_DMABMR_RDP_4xPBL_128Beat</a>   0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */</td></tr>
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<tr class="memitem:ga8c8d22bcd14946c499d9a638e7aedc25" id="r_ga8c8d22bcd14946c499d9a638e7aedc25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c8d22bcd14946c499d9a638e7aedc25">ETH_DMABMR_FB_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga062f6878427a5d9cbb00432cc046ca7d" id="r_ga062f6878427a5d9cbb00432cc046ca7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga062f6878427a5d9cbb00432cc046ca7d">ETH_DMABMR_FB_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c8d22bcd14946c499d9a638e7aedc25">ETH_DMABMR_FB_Pos</a>)</td></tr>
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<tr class="memitem:ga717f163fe72c7e1c999123160dde4143" id="r_ga717f163fe72c7e1c999123160dde4143"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga717f163fe72c7e1c999123160dde4143">ETH_DMABMR_FB</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga062f6878427a5d9cbb00432cc046ca7d">ETH_DMABMR_FB_Msk</a> /* Fixed Burst */</td></tr>
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<tr class="memitem:ga7e0752bf3c2a9ad5f6c2539dcf50a849" id="r_ga7e0752bf3c2a9ad5f6c2539dcf50a849"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e0752bf3c2a9ad5f6c2539dcf50a849">ETH_DMABMR_RTPR_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga7e0752bf3c2a9ad5f6c2539dcf50a849"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac84d16b246ae40bcd90ef3a5a000bc59" id="r_gac84d16b246ae40bcd90ef3a5a000bc59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac84d16b246ae40bcd90ef3a5a000bc59">ETH_DMABMR_RTPR_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e0752bf3c2a9ad5f6c2539dcf50a849">ETH_DMABMR_RTPR_Pos</a>)</td></tr>
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<tr class="separator:gac84d16b246ae40bcd90ef3a5a000bc59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae06b7c29931b088e66f13b055aaddcd6" id="r_gae06b7c29931b088e66f13b055aaddcd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae06b7c29931b088e66f13b055aaddcd6">ETH_DMABMR_RTPR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac84d16b246ae40bcd90ef3a5a000bc59">ETH_DMABMR_RTPR_Msk</a> /* Rx Tx priority ratio */</td></tr>
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<tr class="separator:gae06b7c29931b088e66f13b055aaddcd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga478e7d5ec02db7237be51fa5b83b9e25" id="r_ga478e7d5ec02db7237be51fa5b83b9e25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga478e7d5ec02db7237be51fa5b83b9e25">ETH_DMABMR_RTPR_1_1</a>   0x00000000U /* Rx Tx priority ratio */</td></tr>
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<tr class="separator:ga478e7d5ec02db7237be51fa5b83b9e25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d9e5dda525076cc163bdc29f18e4055" id="r_ga1d9e5dda525076cc163bdc29f18e4055"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d9e5dda525076cc163bdc29f18e4055">ETH_DMABMR_RTPR_2_1</a>   0x00004000U /* Rx Tx priority ratio */</td></tr>
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<tr class="separator:ga1d9e5dda525076cc163bdc29f18e4055"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9e4fd353c5a9ecee3feb428eb54ce2b" id="r_gaf9e4fd353c5a9ecee3feb428eb54ce2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9e4fd353c5a9ecee3feb428eb54ce2b">ETH_DMABMR_RTPR_3_1</a>   0x00008000U /* Rx Tx priority ratio */</td></tr>
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<tr class="separator:gaf9e4fd353c5a9ecee3feb428eb54ce2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad6d57a1f21bc958fa0cfab0cfed02b1" id="r_gaad6d57a1f21bc958fa0cfab0cfed02b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad6d57a1f21bc958fa0cfab0cfed02b1">ETH_DMABMR_RTPR_4_1</a>   0x0000C000U /* Rx Tx priority ratio */</td></tr>
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<tr class="separator:gaad6d57a1f21bc958fa0cfab0cfed02b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b37497a07a1d574524931c0d35f62a1" id="r_ga4b37497a07a1d574524931c0d35f62a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b37497a07a1d574524931c0d35f62a1">ETH_DMABMR_PBL_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga4b37497a07a1d574524931c0d35f62a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga640bcbad2f68125c7593018245c80db6" id="r_ga640bcbad2f68125c7593018245c80db6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga640bcbad2f68125c7593018245c80db6">ETH_DMABMR_PBL_Msk</a>   (0x3FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b37497a07a1d574524931c0d35f62a1">ETH_DMABMR_PBL_Pos</a>)</td></tr>
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<tr class="separator:ga640bcbad2f68125c7593018245c80db6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e3daa2867b6d01e8eda765e77648599" id="r_ga0e3daa2867b6d01e8eda765e77648599"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e3daa2867b6d01e8eda765e77648599">ETH_DMABMR_PBL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga640bcbad2f68125c7593018245c80db6">ETH_DMABMR_PBL_Msk</a> /* Programmable burst length */</td></tr>
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<tr class="separator:ga0e3daa2867b6d01e8eda765e77648599"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaefeb5f1c9376d0a0bc956aba567c7cb9" id="r_gaefeb5f1c9376d0a0bc956aba567c7cb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaefeb5f1c9376d0a0bc956aba567c7cb9">ETH_DMABMR_PBL_1Beat</a>   0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */</td></tr>
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<tr class="separator:gaefeb5f1c9376d0a0bc956aba567c7cb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a034f8cf671cba686e882172ad93949" id="r_ga3a034f8cf671cba686e882172ad93949"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a034f8cf671cba686e882172ad93949">ETH_DMABMR_PBL_2Beat</a>   0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */</td></tr>
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<tr class="separator:ga3a034f8cf671cba686e882172ad93949"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55ff9b7cebc3489fcaab886a065d372c" id="r_ga55ff9b7cebc3489fcaab886a065d372c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55ff9b7cebc3489fcaab886a065d372c">ETH_DMABMR_PBL_4Beat</a>   0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */</td></tr>
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<tr class="separator:ga55ff9b7cebc3489fcaab886a065d372c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae920200ec813649824a20b434c1eecb5" id="r_gae920200ec813649824a20b434c1eecb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae920200ec813649824a20b434c1eecb5">ETH_DMABMR_PBL_8Beat</a>   0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */</td></tr>
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<tr class="memitem:ga6351d1d02e94053527b8e18f393b1e82" id="r_ga6351d1d02e94053527b8e18f393b1e82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6351d1d02e94053527b8e18f393b1e82">ETH_DMABMR_PBL_16Beat</a>   0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */</td></tr>
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<tr class="separator:ga6351d1d02e94053527b8e18f393b1e82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82d8ee65c1583f4ec9092bc45563d720" id="r_ga82d8ee65c1583f4ec9092bc45563d720"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82d8ee65c1583f4ec9092bc45563d720">ETH_DMABMR_PBL_32Beat</a>   0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */</td></tr>
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<tr class="separator:ga82d8ee65c1583f4ec9092bc45563d720"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89566024f4f6772d59592f5bacc7828d" id="r_ga89566024f4f6772d59592f5bacc7828d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89566024f4f6772d59592f5bacc7828d">ETH_DMABMR_PBL_4xPBL_4Beat</a>   0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */</td></tr>
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<tr class="separator:ga89566024f4f6772d59592f5bacc7828d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33acf850c7d6f97899f69d76d87a3dd6" id="r_ga33acf850c7d6f97899f69d76d87a3dd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33acf850c7d6f97899f69d76d87a3dd6">ETH_DMABMR_PBL_4xPBL_8Beat</a>   0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */</td></tr>
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<tr class="separator:ga33acf850c7d6f97899f69d76d87a3dd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5c68f3a0a692fbd81bac47bfe2340bb" id="r_gae5c68f3a0a692fbd81bac47bfe2340bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5c68f3a0a692fbd81bac47bfe2340bb">ETH_DMABMR_PBL_4xPBL_16Beat</a>   0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */</td></tr>
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<tr class="separator:gae5c68f3a0a692fbd81bac47bfe2340bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21298fccc783e5c6d65b9d64960b4ca2" id="r_ga21298fccc783e5c6d65b9d64960b4ca2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21298fccc783e5c6d65b9d64960b4ca2">ETH_DMABMR_PBL_4xPBL_32Beat</a>   0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */</td></tr>
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<tr class="separator:ga21298fccc783e5c6d65b9d64960b4ca2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40a789fc58356a8084c5f1eeba366de2" id="r_ga40a789fc58356a8084c5f1eeba366de2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40a789fc58356a8084c5f1eeba366de2">ETH_DMABMR_PBL_4xPBL_64Beat</a>   0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */</td></tr>
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<tr class="separator:ga40a789fc58356a8084c5f1eeba366de2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c90887a852a858c630ac388bec0b392" id="r_ga4c90887a852a858c630ac388bec0b392"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c90887a852a858c630ac388bec0b392">ETH_DMABMR_PBL_4xPBL_128Beat</a>   0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */</td></tr>
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<tr class="separator:ga4c90887a852a858c630ac388bec0b392"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga772af3cfca1669d65c2eb16413483032" id="r_ga772af3cfca1669d65c2eb16413483032"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga772af3cfca1669d65c2eb16413483032">ETH_DMABMR_EDE_Pos</a>   (7U)</td></tr>
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<tr class="memitem:ga18544872c7f55ac2011ff1fe2ab6d353" id="r_ga18544872c7f55ac2011ff1fe2ab6d353"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18544872c7f55ac2011ff1fe2ab6d353">ETH_DMABMR_EDE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga772af3cfca1669d65c2eb16413483032">ETH_DMABMR_EDE_Pos</a>)</td></tr>
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<tr class="separator:ga18544872c7f55ac2011ff1fe2ab6d353"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf04f1ef51af153093743c190d25ea21b" id="r_gaf04f1ef51af153093743c190d25ea21b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf04f1ef51af153093743c190d25ea21b">ETH_DMABMR_EDE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga18544872c7f55ac2011ff1fe2ab6d353">ETH_DMABMR_EDE_Msk</a> /* Enhanced Descriptor Enable */</td></tr>
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<tr class="separator:gaf04f1ef51af153093743c190d25ea21b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff399b83a19a6a62457cd0877bea35b7" id="r_gaff399b83a19a6a62457cd0877bea35b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff399b83a19a6a62457cd0877bea35b7">ETH_DMABMR_DSL_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaff399b83a19a6a62457cd0877bea35b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c0974106bccb288a14a4f5b055f2a88" id="r_ga4c0974106bccb288a14a4f5b055f2a88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c0974106bccb288a14a4f5b055f2a88">ETH_DMABMR_DSL_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaff399b83a19a6a62457cd0877bea35b7">ETH_DMABMR_DSL_Pos</a>)</td></tr>
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<tr class="separator:ga4c0974106bccb288a14a4f5b055f2a88"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1931fd959cb78283ab0cf0bd9804387" id="r_gab1931fd959cb78283ab0cf0bd9804387"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1931fd959cb78283ab0cf0bd9804387">ETH_DMABMR_DSL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c0974106bccb288a14a4f5b055f2a88">ETH_DMABMR_DSL_Msk</a> /* Descriptor Skip Length */</td></tr>
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<tr class="memitem:gabad048a02b9fbed0c5824a6a632d0daf" id="r_gabad048a02b9fbed0c5824a6a632d0daf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabad048a02b9fbed0c5824a6a632d0daf">ETH_DMABMR_DA_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga7bd68646897581a06cbee2dacbdd0c14" id="r_ga7bd68646897581a06cbee2dacbdd0c14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7bd68646897581a06cbee2dacbdd0c14">ETH_DMABMR_DA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabad048a02b9fbed0c5824a6a632d0daf">ETH_DMABMR_DA_Pos</a>)</td></tr>
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<tr class="separator:ga7bd68646897581a06cbee2dacbdd0c14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd126734c36f2db46c51e73cef07afce" id="r_gafd126734c36f2db46c51e73cef07afce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd126734c36f2db46c51e73cef07afce">ETH_DMABMR_DA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7bd68646897581a06cbee2dacbdd0c14">ETH_DMABMR_DA_Msk</a> /* DMA arbitration scheme */</td></tr>
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<tr class="separator:gafd126734c36f2db46c51e73cef07afce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacef0ceff9d1440c18e92a28da757a8df" id="r_gacef0ceff9d1440c18e92a28da757a8df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacef0ceff9d1440c18e92a28da757a8df">ETH_DMABMR_SR_Pos</a>   (0U)</td></tr>
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<tr class="separator:gacef0ceff9d1440c18e92a28da757a8df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf0350e3541f1c466e6544db265e36a4" id="r_gadf0350e3541f1c466e6544db265e36a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf0350e3541f1c466e6544db265e36a4">ETH_DMABMR_SR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacef0ceff9d1440c18e92a28da757a8df">ETH_DMABMR_SR_Pos</a>)</td></tr>
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<tr class="separator:gadf0350e3541f1c466e6544db265e36a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e8dfe321aeaecaa87e290f4d6e710dc" id="r_ga2e8dfe321aeaecaa87e290f4d6e710dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e8dfe321aeaecaa87e290f4d6e710dc">ETH_DMABMR_SR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadf0350e3541f1c466e6544db265e36a4">ETH_DMABMR_SR_Msk</a> /* Software reset */</td></tr>
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<tr class="separator:ga2e8dfe321aeaecaa87e290f4d6e710dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37cc58720fbe96f7130a00e32023189f" id="r_ga37cc58720fbe96f7130a00e32023189f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37cc58720fbe96f7130a00e32023189f">ETH_DMATPDR_TPD_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga37cc58720fbe96f7130a00e32023189f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04187d48766f865c479d26d2c6225fa9" id="r_ga04187d48766f865c479d26d2c6225fa9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04187d48766f865c479d26d2c6225fa9">ETH_DMATPDR_TPD_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga37cc58720fbe96f7130a00e32023189f">ETH_DMATPDR_TPD_Pos</a>)</td></tr>
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<tr class="separator:ga04187d48766f865c479d26d2c6225fa9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef2d9dbefaa6940adf6422092fae2da6" id="r_gaef2d9dbefaa6940adf6422092fae2da6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef2d9dbefaa6940adf6422092fae2da6">ETH_DMATPDR_TPD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga04187d48766f865c479d26d2c6225fa9">ETH_DMATPDR_TPD_Msk</a> /* Transmit poll demand */</td></tr>
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<tr class="separator:gaef2d9dbefaa6940adf6422092fae2da6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05a0babc0d1d7b6a2ff358a8ff819fb5" id="r_ga05a0babc0d1d7b6a2ff358a8ff819fb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05a0babc0d1d7b6a2ff358a8ff819fb5">ETH_DMARPDR_RPD_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga05a0babc0d1d7b6a2ff358a8ff819fb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56d192c68de928fdbb181eb063145446" id="r_ga56d192c68de928fdbb181eb063145446"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56d192c68de928fdbb181eb063145446">ETH_DMARPDR_RPD_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05a0babc0d1d7b6a2ff358a8ff819fb5">ETH_DMARPDR_RPD_Pos</a>)</td></tr>
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<tr class="separator:ga56d192c68de928fdbb181eb063145446"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83f1c5a5628c6e7dcd853e511eac49e8" id="r_ga83f1c5a5628c6e7dcd853e511eac49e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83f1c5a5628c6e7dcd853e511eac49e8">ETH_DMARPDR_RPD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga56d192c68de928fdbb181eb063145446">ETH_DMARPDR_RPD_Msk</a> /* Receive poll demand */</td></tr>
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<tr class="separator:ga83f1c5a5628c6e7dcd853e511eac49e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b8637d2710b95d2994fb20e620c6ee5" id="r_ga3b8637d2710b95d2994fb20e620c6ee5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b8637d2710b95d2994fb20e620c6ee5">ETH_DMARDLAR_SRL_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3b8637d2710b95d2994fb20e620c6ee5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5cc8aee0138d0f2bfaf2c684376949f" id="r_gab5cc8aee0138d0f2bfaf2c684376949f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5cc8aee0138d0f2bfaf2c684376949f">ETH_DMARDLAR_SRL_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b8637d2710b95d2994fb20e620c6ee5">ETH_DMARDLAR_SRL_Pos</a>)</td></tr>
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<tr class="separator:gab5cc8aee0138d0f2bfaf2c684376949f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34e60ae1c7b80cf199c372b5e701b46e" id="r_ga34e60ae1c7b80cf199c372b5e701b46e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34e60ae1c7b80cf199c372b5e701b46e">ETH_DMARDLAR_SRL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab5cc8aee0138d0f2bfaf2c684376949f">ETH_DMARDLAR_SRL_Msk</a> /* Start of receive list */</td></tr>
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<tr class="separator:ga34e60ae1c7b80cf199c372b5e701b46e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6a7932a4408e67d5c10d5a2d18f9385" id="r_gae6a7932a4408e67d5c10d5a2d18f9385"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6a7932a4408e67d5c10d5a2d18f9385">ETH_DMATDLAR_STL_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae6a7932a4408e67d5c10d5a2d18f9385"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga001a009e3ed3f0fa5c8b8d99839d4f16" id="r_ga001a009e3ed3f0fa5c8b8d99839d4f16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga001a009e3ed3f0fa5c8b8d99839d4f16">ETH_DMATDLAR_STL_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae6a7932a4408e67d5c10d5a2d18f9385">ETH_DMATDLAR_STL_Pos</a>)</td></tr>
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<tr class="separator:ga001a009e3ed3f0fa5c8b8d99839d4f16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f9f12964bc4e019afface14df2dc87c" id="r_ga8f9f12964bc4e019afface14df2dc87c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f9f12964bc4e019afface14df2dc87c">ETH_DMATDLAR_STL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga001a009e3ed3f0fa5c8b8d99839d4f16">ETH_DMATDLAR_STL_Msk</a> /* Start of transmit list */</td></tr>
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<tr class="separator:ga8f9f12964bc4e019afface14df2dc87c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f397466df0a01f13dbc1487726a6fbc" id="r_ga3f397466df0a01f13dbc1487726a6fbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f397466df0a01f13dbc1487726a6fbc">ETH_DMASR_TSTS_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga3f397466df0a01f13dbc1487726a6fbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72e40eb362f28f7ea04d874e73e70072" id="r_ga72e40eb362f28f7ea04d874e73e70072"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72e40eb362f28f7ea04d874e73e70072">ETH_DMASR_TSTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3f397466df0a01f13dbc1487726a6fbc">ETH_DMASR_TSTS_Pos</a>)</td></tr>
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<tr class="separator:ga72e40eb362f28f7ea04d874e73e70072"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac55027d33ea49f5498f5c9a0dab629d7" id="r_gac55027d33ea49f5498f5c9a0dab629d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac55027d33ea49f5498f5c9a0dab629d7">ETH_DMASR_TSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga72e40eb362f28f7ea04d874e73e70072">ETH_DMASR_TSTS_Msk</a> /* Time-stamp trigger <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:gac55027d33ea49f5498f5c9a0dab629d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9532f43143213e838dd0ab5a24caf78" id="r_gaf9532f43143213e838dd0ab5a24caf78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9532f43143213e838dd0ab5a24caf78">ETH_DMASR_PMTS_Pos</a>   (28U)</td></tr>
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<tr class="separator:gaf9532f43143213e838dd0ab5a24caf78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92bdb1d530baa75204516d6c8045f1dc" id="r_ga92bdb1d530baa75204516d6c8045f1dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92bdb1d530baa75204516d6c8045f1dc">ETH_DMASR_PMTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf9532f43143213e838dd0ab5a24caf78">ETH_DMASR_PMTS_Pos</a>)</td></tr>
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<tr class="separator:ga92bdb1d530baa75204516d6c8045f1dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4792ff5cd86cdea1edf34ea90448b34a" id="r_ga4792ff5cd86cdea1edf34ea90448b34a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4792ff5cd86cdea1edf34ea90448b34a">ETH_DMASR_PMTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga92bdb1d530baa75204516d6c8045f1dc">ETH_DMASR_PMTS_Msk</a> /* PMT <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga4792ff5cd86cdea1edf34ea90448b34a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb58a6756ac7507049b458b398a3d6c4" id="r_gadb58a6756ac7507049b458b398a3d6c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb58a6756ac7507049b458b398a3d6c4">ETH_DMASR_MMCS_Pos</a>   (27U)</td></tr>
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<tr class="separator:gadb58a6756ac7507049b458b398a3d6c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5366f0a075f3c6821b4bade162bfc151" id="r_ga5366f0a075f3c6821b4bade162bfc151"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5366f0a075f3c6821b4bade162bfc151">ETH_DMASR_MMCS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadb58a6756ac7507049b458b398a3d6c4">ETH_DMASR_MMCS_Pos</a>)</td></tr>
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<tr class="separator:ga5366f0a075f3c6821b4bade162bfc151"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d6207fe0c8383456188e9bb1e2fb9fe" id="r_ga2d6207fe0c8383456188e9bb1e2fb9fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d6207fe0c8383456188e9bb1e2fb9fe">ETH_DMASR_MMCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5366f0a075f3c6821b4bade162bfc151">ETH_DMASR_MMCS_Msk</a> /* MMC <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga2d6207fe0c8383456188e9bb1e2fb9fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad430939a2de7c270ecb359c5d1a32670" id="r_gad430939a2de7c270ecb359c5d1a32670"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad430939a2de7c270ecb359c5d1a32670">ETH_DMASR_EBS_Pos</a>   (23U)</td></tr>
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<tr class="separator:gad430939a2de7c270ecb359c5d1a32670"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf72d998538d5fcb41440f203e916edc" id="r_gabf72d998538d5fcb41440f203e916edc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf72d998538d5fcb41440f203e916edc">ETH_DMASR_EBS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad430939a2de7c270ecb359c5d1a32670">ETH_DMASR_EBS_Pos</a>)</td></tr>
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<tr class="separator:gabf72d998538d5fcb41440f203e916edc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga098b5395babfd8474a75a5a2034c94f2" id="r_ga098b5395babfd8474a75a5a2034c94f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga098b5395babfd8474a75a5a2034c94f2">ETH_DMASR_EBS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabf72d998538d5fcb41440f203e916edc">ETH_DMASR_EBS_Msk</a> /* Error bits <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga098b5395babfd8474a75a5a2034c94f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga357bae318615787a3891c3c493b916d7" id="r_ga357bae318615787a3891c3c493b916d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga357bae318615787a3891c3c493b916d7">ETH_DMASR_EBS_DescAccess_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga357bae318615787a3891c3c493b916d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d01e1b20f21d635fd0e195148b12609" id="r_ga2d01e1b20f21d635fd0e195148b12609"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d01e1b20f21d635fd0e195148b12609">ETH_DMASR_EBS_DescAccess_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga357bae318615787a3891c3c493b916d7">ETH_DMASR_EBS_DescAccess_Pos</a>)</td></tr>
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<tr class="separator:ga2d01e1b20f21d635fd0e195148b12609"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42e1dfda0e23a1ae10c0c05c405e5c73" id="r_ga42e1dfda0e23a1ae10c0c05c405e5c73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42e1dfda0e23a1ae10c0c05c405e5c73">ETH_DMASR_EBS_DescAccess</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d01e1b20f21d635fd0e195148b12609">ETH_DMASR_EBS_DescAccess_Msk</a> /* Error bits 0-data buffer, 1-desc. access */</td></tr>
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<tr class="separator:ga42e1dfda0e23a1ae10c0c05c405e5c73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ec84cb6fb224f4511dd259a9947c6b3" id="r_ga3ec84cb6fb224f4511dd259a9947c6b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ec84cb6fb224f4511dd259a9947c6b3">ETH_DMASR_EBS_ReadTransf_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga3ec84cb6fb224f4511dd259a9947c6b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ba2f75d57b076dd6fd741eb85569ea0" id="r_ga9ba2f75d57b076dd6fd741eb85569ea0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ba2f75d57b076dd6fd741eb85569ea0">ETH_DMASR_EBS_ReadTransf_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3ec84cb6fb224f4511dd259a9947c6b3">ETH_DMASR_EBS_ReadTransf_Pos</a>)</td></tr>
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<tr class="separator:ga9ba2f75d57b076dd6fd741eb85569ea0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga315c68184fd0f0e510539dc8cd986393" id="r_ga315c68184fd0f0e510539dc8cd986393"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga315c68184fd0f0e510539dc8cd986393">ETH_DMASR_EBS_ReadTransf</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ba2f75d57b076dd6fd741eb85569ea0">ETH_DMASR_EBS_ReadTransf_Msk</a> /* Error bits 0-write trnsf, 1-read transfr */</td></tr>
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<tr class="separator:ga315c68184fd0f0e510539dc8cd986393"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad72b89b7da590a72f8e9061c96111dbf" id="r_gad72b89b7da590a72f8e9061c96111dbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad72b89b7da590a72f8e9061c96111dbf">ETH_DMASR_EBS_DataTransfTx_Pos</a>   (23U)</td></tr>
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<tr class="separator:gad72b89b7da590a72f8e9061c96111dbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb5f3f939bfb190ddd5837ecb203a7db" id="r_gabb5f3f939bfb190ddd5837ecb203a7db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb5f3f939bfb190ddd5837ecb203a7db">ETH_DMASR_EBS_DataTransfTx_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad72b89b7da590a72f8e9061c96111dbf">ETH_DMASR_EBS_DataTransfTx_Pos</a>)</td></tr>
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<tr class="separator:gabb5f3f939bfb190ddd5837ecb203a7db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd56804ed872078d962ef5f01dc295e1" id="r_gacd56804ed872078d962ef5f01dc295e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd56804ed872078d962ef5f01dc295e1">ETH_DMASR_EBS_DataTransfTx</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabb5f3f939bfb190ddd5837ecb203a7db">ETH_DMASR_EBS_DataTransfTx_Msk</a> /* Error bits 0-Rx DMA, 1-Tx DMA */</td></tr>
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<tr class="separator:gacd56804ed872078d962ef5f01dc295e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9c98699ea2df54364b5232ff3d1cd30" id="r_gae9c98699ea2df54364b5232ff3d1cd30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98699ea2df54364b5232ff3d1cd30">ETH_DMASR_TPS_Pos</a>   (20U)</td></tr>
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<tr class="separator:gae9c98699ea2df54364b5232ff3d1cd30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga706f64bbf5b12368955bc3d0fdba6a39" id="r_ga706f64bbf5b12368955bc3d0fdba6a39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga706f64bbf5b12368955bc3d0fdba6a39">ETH_DMASR_TPS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae9c98699ea2df54364b5232ff3d1cd30">ETH_DMASR_TPS_Pos</a>)</td></tr>
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<tr class="separator:ga706f64bbf5b12368955bc3d0fdba6a39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga806073adcecb9139b1c1d7ed35a4f37c" id="r_ga806073adcecb9139b1c1d7ed35a4f37c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga806073adcecb9139b1c1d7ed35a4f37c">ETH_DMASR_TPS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga706f64bbf5b12368955bc3d0fdba6a39">ETH_DMASR_TPS_Msk</a> /* Transmit process state */</td></tr>
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<tr class="separator:ga806073adcecb9139b1c1d7ed35a4f37c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c0d4830c8196127e9b26178b23b6f3e" id="r_ga0c0d4830c8196127e9b26178b23b6f3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c0d4830c8196127e9b26178b23b6f3e">ETH_DMASR_TPS_Stopped</a>   0x00000000U /* Stopped - Reset or Stop Tx Command issued */</td></tr>
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<tr class="separator:ga0c0d4830c8196127e9b26178b23b6f3e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85ca0bb143abb15cf11a7edd9d5ca974" id="r_ga85ca0bb143abb15cf11a7edd9d5ca974"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85ca0bb143abb15cf11a7edd9d5ca974">ETH_DMASR_TPS_Fetching_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga85ca0bb143abb15cf11a7edd9d5ca974"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81cc65263215ebdbae36ff6f983e5611" id="r_ga81cc65263215ebdbae36ff6f983e5611"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81cc65263215ebdbae36ff6f983e5611">ETH_DMASR_TPS_Fetching_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga85ca0bb143abb15cf11a7edd9d5ca974">ETH_DMASR_TPS_Fetching_Pos</a>)</td></tr>
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<tr class="separator:ga81cc65263215ebdbae36ff6f983e5611"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd9af883f17d4bbbdde6866ecf67afe2" id="r_gadd9af883f17d4bbbdde6866ecf67afe2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd9af883f17d4bbbdde6866ecf67afe2">ETH_DMASR_TPS_Fetching</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga81cc65263215ebdbae36ff6f983e5611">ETH_DMASR_TPS_Fetching_Msk</a> /* Running - fetching the Tx descriptor */</td></tr>
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<tr class="separator:gadd9af883f17d4bbbdde6866ecf67afe2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73cefac3fbaeed6be54b48bd24de4b8b" id="r_ga73cefac3fbaeed6be54b48bd24de4b8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73cefac3fbaeed6be54b48bd24de4b8b">ETH_DMASR_TPS_Waiting_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga73cefac3fbaeed6be54b48bd24de4b8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga372a83db64b04814ac01ef9b072bdb09" id="r_ga372a83db64b04814ac01ef9b072bdb09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga372a83db64b04814ac01ef9b072bdb09">ETH_DMASR_TPS_Waiting_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga73cefac3fbaeed6be54b48bd24de4b8b">ETH_DMASR_TPS_Waiting_Pos</a>)</td></tr>
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<tr class="separator:ga372a83db64b04814ac01ef9b072bdb09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga351ab7003c342ab1b43f9fd158fdc00d" id="r_ga351ab7003c342ab1b43f9fd158fdc00d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga351ab7003c342ab1b43f9fd158fdc00d">ETH_DMASR_TPS_Waiting</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga372a83db64b04814ac01ef9b072bdb09">ETH_DMASR_TPS_Waiting_Msk</a> /* Running - waiting for <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga351ab7003c342ab1b43f9fd158fdc00d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1f8f06d72c8a90d32f78cd39ba9abee" id="r_gae1f8f06d72c8a90d32f78cd39ba9abee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1f8f06d72c8a90d32f78cd39ba9abee">ETH_DMASR_TPS_Reading_Pos</a>   (20U)</td></tr>
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<tr class="separator:gae1f8f06d72c8a90d32f78cd39ba9abee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76229b644063a64e1939b3c9e75c2539" id="r_ga76229b644063a64e1939b3c9e75c2539"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76229b644063a64e1939b3c9e75c2539">ETH_DMASR_TPS_Reading_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae1f8f06d72c8a90d32f78cd39ba9abee">ETH_DMASR_TPS_Reading_Pos</a>)</td></tr>
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<tr class="separator:ga76229b644063a64e1939b3c9e75c2539"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72af54920faf4b54e760c3784dccaf65" id="r_ga72af54920faf4b54e760c3784dccaf65"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72af54920faf4b54e760c3784dccaf65">ETH_DMASR_TPS_Reading</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga76229b644063a64e1939b3c9e75c2539">ETH_DMASR_TPS_Reading_Msk</a> /* Running - reading the data from host memory */</td></tr>
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<tr class="separator:ga72af54920faf4b54e760c3784dccaf65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1d5230313ea8ab7b2990fac846a769b" id="r_gac1d5230313ea8ab7b2990fac846a769b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1d5230313ea8ab7b2990fac846a769b">ETH_DMASR_TPS_Suspended_Pos</a>   (21U)</td></tr>
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<tr class="separator:gac1d5230313ea8ab7b2990fac846a769b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabebe05fb2f636f75f5cd2da28d465d8d" id="r_gabebe05fb2f636f75f5cd2da28d465d8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabebe05fb2f636f75f5cd2da28d465d8d">ETH_DMASR_TPS_Suspended_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac1d5230313ea8ab7b2990fac846a769b">ETH_DMASR_TPS_Suspended_Pos</a>)</td></tr>
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<tr class="separator:gabebe05fb2f636f75f5cd2da28d465d8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80b3558db79b5903dd3966ceed7bb1e8" id="r_ga80b3558db79b5903dd3966ceed7bb1e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga80b3558db79b5903dd3966ceed7bb1e8">ETH_DMASR_TPS_Suspended</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabebe05fb2f636f75f5cd2da28d465d8d">ETH_DMASR_TPS_Suspended_Msk</a> /* Suspended - Tx Descriptor unavailable */</td></tr>
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<tr class="separator:ga80b3558db79b5903dd3966ceed7bb1e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98d18b94cc18a69e4522d1d4b4249a8e" id="r_ga98d18b94cc18a69e4522d1d4b4249a8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98d18b94cc18a69e4522d1d4b4249a8e">ETH_DMASR_TPS_Closing_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga98d18b94cc18a69e4522d1d4b4249a8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga367081b68077417f3556e514f5ca1771" id="r_ga367081b68077417f3556e514f5ca1771"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga367081b68077417f3556e514f5ca1771">ETH_DMASR_TPS_Closing_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98d18b94cc18a69e4522d1d4b4249a8e">ETH_DMASR_TPS_Closing_Pos</a>)</td></tr>
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<tr class="separator:ga367081b68077417f3556e514f5ca1771"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6e95d2a805ec4d8e50de467825c86e0" id="r_gaf6e95d2a805ec4d8e50de467825c86e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6e95d2a805ec4d8e50de467825c86e0">ETH_DMASR_TPS_Closing</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga367081b68077417f3556e514f5ca1771">ETH_DMASR_TPS_Closing_Msk</a> /* Running - closing Rx descriptor */</td></tr>
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<tr class="separator:gaf6e95d2a805ec4d8e50de467825c86e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb7b51984ea407e0d049606fcc59b665" id="r_gaeb7b51984ea407e0d049606fcc59b665"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb7b51984ea407e0d049606fcc59b665">ETH_DMASR_RPS_Pos</a>   (17U)</td></tr>
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<tr class="separator:gaeb7b51984ea407e0d049606fcc59b665"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade55bf5c8f6788537f16f5c535fca9df" id="r_gade55bf5c8f6788537f16f5c535fca9df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade55bf5c8f6788537f16f5c535fca9df">ETH_DMASR_RPS_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaeb7b51984ea407e0d049606fcc59b665">ETH_DMASR_RPS_Pos</a>)</td></tr>
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<tr class="separator:gade55bf5c8f6788537f16f5c535fca9df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae773175991a44530bcd26057a7b3819e" id="r_gae773175991a44530bcd26057a7b3819e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae773175991a44530bcd26057a7b3819e">ETH_DMASR_RPS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gade55bf5c8f6788537f16f5c535fca9df">ETH_DMASR_RPS_Msk</a> /* Receive process state */</td></tr>
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<tr class="separator:gae773175991a44530bcd26057a7b3819e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a2dfc943902722a1bce1d0a24125e45" id="r_ga6a2dfc943902722a1bce1d0a24125e45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a2dfc943902722a1bce1d0a24125e45">ETH_DMASR_RPS_Stopped</a>   0x00000000U /* Stopped - Reset or Stop Rx Command issued */</td></tr>
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<tr class="separator:ga6a2dfc943902722a1bce1d0a24125e45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a722459468b128af26661078a2e6dd3" id="r_ga4a722459468b128af26661078a2e6dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a722459468b128af26661078a2e6dd3">ETH_DMASR_RPS_Fetching_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga4a722459468b128af26661078a2e6dd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ebd16304081748a0fc85659ca005b74" id="r_ga6ebd16304081748a0fc85659ca005b74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ebd16304081748a0fc85659ca005b74">ETH_DMASR_RPS_Fetching_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a722459468b128af26661078a2e6dd3">ETH_DMASR_RPS_Fetching_Pos</a>)</td></tr>
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<tr class="separator:ga6ebd16304081748a0fc85659ca005b74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92a04f8a6f4c047967d38e4fd3f4bbb9" id="r_ga92a04f8a6f4c047967d38e4fd3f4bbb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92a04f8a6f4c047967d38e4fd3f4bbb9">ETH_DMASR_RPS_Fetching</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6ebd16304081748a0fc85659ca005b74">ETH_DMASR_RPS_Fetching_Msk</a> /* Running - fetching the Rx descriptor */</td></tr>
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<tr class="separator:ga92a04f8a6f4c047967d38e4fd3f4bbb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69b95466c40968273837da5388e29d26" id="r_ga69b95466c40968273837da5388e29d26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69b95466c40968273837da5388e29d26">ETH_DMASR_RPS_Waiting_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga69b95466c40968273837da5388e29d26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02f12914ed1c79ed445e5dbbb0e085aa" id="r_ga02f12914ed1c79ed445e5dbbb0e085aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02f12914ed1c79ed445e5dbbb0e085aa">ETH_DMASR_RPS_Waiting_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69b95466c40968273837da5388e29d26">ETH_DMASR_RPS_Waiting_Pos</a>)</td></tr>
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<tr class="separator:ga02f12914ed1c79ed445e5dbbb0e085aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5440bd06e487e3ca5d64afebc8b48bac" id="r_ga5440bd06e487e3ca5d64afebc8b48bac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5440bd06e487e3ca5d64afebc8b48bac">ETH_DMASR_RPS_Waiting</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga02f12914ed1c79ed445e5dbbb0e085aa">ETH_DMASR_RPS_Waiting_Msk</a> /* Running - waiting for packet */</td></tr>
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<tr class="separator:ga5440bd06e487e3ca5d64afebc8b48bac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga465fd4ba545bbfa3ba642e65102787de" id="r_ga465fd4ba545bbfa3ba642e65102787de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga465fd4ba545bbfa3ba642e65102787de">ETH_DMASR_RPS_Suspended_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga465fd4ba545bbfa3ba642e65102787de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1fb0ba5f7b3373caf68328175250e96" id="r_gaf1fb0ba5f7b3373caf68328175250e96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1fb0ba5f7b3373caf68328175250e96">ETH_DMASR_RPS_Suspended_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga465fd4ba545bbfa3ba642e65102787de">ETH_DMASR_RPS_Suspended_Pos</a>)</td></tr>
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<tr class="separator:gaf1fb0ba5f7b3373caf68328175250e96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5e1406af058b582a7f60f8415edde15" id="r_gad5e1406af058b582a7f60f8415edde15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5e1406af058b582a7f60f8415edde15">ETH_DMASR_RPS_Suspended</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1fb0ba5f7b3373caf68328175250e96">ETH_DMASR_RPS_Suspended_Msk</a> /* Suspended - Rx Descriptor unavailable */</td></tr>
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<tr class="separator:gad5e1406af058b582a7f60f8415edde15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d0d9e0f3ccb8bb117dc2b6b01094ff2" id="r_ga3d0d9e0f3ccb8bb117dc2b6b01094ff2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d0d9e0f3ccb8bb117dc2b6b01094ff2">ETH_DMASR_RPS_Closing_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga3d0d9e0f3ccb8bb117dc2b6b01094ff2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89428a8eb321c17f0d6319d5f8409d6e" id="r_ga89428a8eb321c17f0d6319d5f8409d6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89428a8eb321c17f0d6319d5f8409d6e">ETH_DMASR_RPS_Closing_Msk</a>   (0x5UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d0d9e0f3ccb8bb117dc2b6b01094ff2">ETH_DMASR_RPS_Closing_Pos</a>)</td></tr>
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<tr class="separator:ga89428a8eb321c17f0d6319d5f8409d6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0976a4ba0b8dcbe42fdef38a8589fda8" id="r_ga0976a4ba0b8dcbe42fdef38a8589fda8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0976a4ba0b8dcbe42fdef38a8589fda8">ETH_DMASR_RPS_Closing</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga89428a8eb321c17f0d6319d5f8409d6e">ETH_DMASR_RPS_Closing_Msk</a> /* Running - closing descriptor */</td></tr>
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<tr class="separator:ga0976a4ba0b8dcbe42fdef38a8589fda8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38c80ba33689333b6f1a08318ebb31b2" id="r_ga38c80ba33689333b6f1a08318ebb31b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38c80ba33689333b6f1a08318ebb31b2">ETH_DMASR_RPS_Queuing_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga38c80ba33689333b6f1a08318ebb31b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga276f57d8860566be667d03e6f38f9840" id="r_ga276f57d8860566be667d03e6f38f9840"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga276f57d8860566be667d03e6f38f9840">ETH_DMASR_RPS_Queuing_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga38c80ba33689333b6f1a08318ebb31b2">ETH_DMASR_RPS_Queuing_Pos</a>)</td></tr>
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<tr class="separator:ga276f57d8860566be667d03e6f38f9840"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6aaf0193e4f15e2937cb18586567e43" id="r_gae6aaf0193e4f15e2937cb18586567e43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6aaf0193e4f15e2937cb18586567e43">ETH_DMASR_RPS_Queuing</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga276f57d8860566be667d03e6f38f9840">ETH_DMASR_RPS_Queuing_Msk</a> /* Running - queuing the receive frame into host memory */</td></tr>
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<tr class="separator:gae6aaf0193e4f15e2937cb18586567e43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c5b7e682ca590e3a6069be7111c04eb" id="r_ga3c5b7e682ca590e3a6069be7111c04eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c5b7e682ca590e3a6069be7111c04eb">ETH_DMASR_NIS_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga3c5b7e682ca590e3a6069be7111c04eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a4beec3bd9093993f5b2434b1b1e09d" id="r_ga8a4beec3bd9093993f5b2434b1b1e09d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a4beec3bd9093993f5b2434b1b1e09d">ETH_DMASR_NIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c5b7e682ca590e3a6069be7111c04eb">ETH_DMASR_NIS_Pos</a>)</td></tr>
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<tr class="separator:ga8a4beec3bd9093993f5b2434b1b1e09d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8585a6af3197e49831882373410d94c" id="r_gad8585a6af3197e49831882373410d94c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8585a6af3197e49831882373410d94c">ETH_DMASR_NIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a4beec3bd9093993f5b2434b1b1e09d">ETH_DMASR_NIS_Msk</a> /* Normal interrupt summary */</td></tr>
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<tr class="separator:gad8585a6af3197e49831882373410d94c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf97acf90b407e4b509779b5af53d230b" id="r_gaf97acf90b407e4b509779b5af53d230b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf97acf90b407e4b509779b5af53d230b">ETH_DMASR_AIS_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaf97acf90b407e4b509779b5af53d230b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa257027c6436c5549724db8df50284db" id="r_gaa257027c6436c5549724db8df50284db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa257027c6436c5549724db8df50284db">ETH_DMASR_AIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf97acf90b407e4b509779b5af53d230b">ETH_DMASR_AIS_Pos</a>)</td></tr>
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<tr class="separator:gaa257027c6436c5549724db8df50284db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cb15b33a997bec75b9c8750231ee411" id="r_ga1cb15b33a997bec75b9c8750231ee411"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cb15b33a997bec75b9c8750231ee411">ETH_DMASR_AIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa257027c6436c5549724db8df50284db">ETH_DMASR_AIS_Msk</a> /* Abnormal interrupt summary */</td></tr>
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<tr class="separator:ga1cb15b33a997bec75b9c8750231ee411"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08262d444227cc81a46fa9e3b1dff314" id="r_ga08262d444227cc81a46fa9e3b1dff314"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08262d444227cc81a46fa9e3b1dff314">ETH_DMASR_ERS_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga08262d444227cc81a46fa9e3b1dff314"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1038a467b90b609a7b709b179334c33" id="r_gab1038a467b90b609a7b709b179334c33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1038a467b90b609a7b709b179334c33">ETH_DMASR_ERS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga08262d444227cc81a46fa9e3b1dff314">ETH_DMASR_ERS_Pos</a>)</td></tr>
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<tr class="separator:gab1038a467b90b609a7b709b179334c33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga899d94d62f011fc56aa5814e528055f7" id="r_ga899d94d62f011fc56aa5814e528055f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga899d94d62f011fc56aa5814e528055f7">ETH_DMASR_ERS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab1038a467b90b609a7b709b179334c33">ETH_DMASR_ERS_Msk</a> /* Early receive <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga899d94d62f011fc56aa5814e528055f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga491afda68d7906be911a8be5e16966ae" id="r_ga491afda68d7906be911a8be5e16966ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga491afda68d7906be911a8be5e16966ae">ETH_DMASR_FBES_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga491afda68d7906be911a8be5e16966ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga616a1ac8f4d7a70430585b6461fc0ce3" id="r_ga616a1ac8f4d7a70430585b6461fc0ce3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga616a1ac8f4d7a70430585b6461fc0ce3">ETH_DMASR_FBES_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga491afda68d7906be911a8be5e16966ae">ETH_DMASR_FBES_Pos</a>)</td></tr>
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<tr class="separator:ga616a1ac8f4d7a70430585b6461fc0ce3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab28c0a99d8d2ff948096d06b6dfdab9c" id="r_gab28c0a99d8d2ff948096d06b6dfdab9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab28c0a99d8d2ff948096d06b6dfdab9c">ETH_DMASR_FBES</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga616a1ac8f4d7a70430585b6461fc0ce3">ETH_DMASR_FBES_Msk</a> /* Fatal bus error <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:gab28c0a99d8d2ff948096d06b6dfdab9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacea84ae95fd863044bfb89895ce0edc6" id="r_gacea84ae95fd863044bfb89895ce0edc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacea84ae95fd863044bfb89895ce0edc6">ETH_DMASR_ETS_Pos</a>   (10U)</td></tr>
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<tr class="separator:gacea84ae95fd863044bfb89895ce0edc6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86649ab55b955dee747af1266d117270" id="r_ga86649ab55b955dee747af1266d117270"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86649ab55b955dee747af1266d117270">ETH_DMASR_ETS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacea84ae95fd863044bfb89895ce0edc6">ETH_DMASR_ETS_Pos</a>)</td></tr>
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<tr class="separator:ga86649ab55b955dee747af1266d117270"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb828d827c627f704a53dc486cec821c" id="r_gacb828d827c627f704a53dc486cec821c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb828d827c627f704a53dc486cec821c">ETH_DMASR_ETS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86649ab55b955dee747af1266d117270">ETH_DMASR_ETS_Msk</a> /* Early transmit <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:gacb828d827c627f704a53dc486cec821c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54e86ee5eaafdcced3a4d545fa49525a" id="r_ga54e86ee5eaafdcced3a4d545fa49525a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54e86ee5eaafdcced3a4d545fa49525a">ETH_DMASR_RWTS_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga54e86ee5eaafdcced3a4d545fa49525a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a3f72a3dc3b046d2771cdcbf514b175" id="r_ga1a3f72a3dc3b046d2771cdcbf514b175"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a3f72a3dc3b046d2771cdcbf514b175">ETH_DMASR_RWTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga54e86ee5eaafdcced3a4d545fa49525a">ETH_DMASR_RWTS_Pos</a>)</td></tr>
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<tr class="separator:ga1a3f72a3dc3b046d2771cdcbf514b175"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ce8d0c087f96b2b5c3e1db45cd1ecf5" id="r_ga3ce8d0c087f96b2b5c3e1db45cd1ecf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3ce8d0c087f96b2b5c3e1db45cd1ecf5">ETH_DMASR_RWTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a3f72a3dc3b046d2771cdcbf514b175">ETH_DMASR_RWTS_Msk</a> /* Receive watchdog timeout <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga3ce8d0c087f96b2b5c3e1db45cd1ecf5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67f272abdf029d7a2f9d8f111df46102" id="r_ga67f272abdf029d7a2f9d8f111df46102"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67f272abdf029d7a2f9d8f111df46102">ETH_DMASR_RPSS_Pos</a>   (8U)</td></tr>
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<tr class="memitem:gad2630d1d889e82544e5f3eaaa0c73efb" id="r_gad2630d1d889e82544e5f3eaaa0c73efb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2630d1d889e82544e5f3eaaa0c73efb">ETH_DMASR_RPSS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67f272abdf029d7a2f9d8f111df46102">ETH_DMASR_RPSS_Pos</a>)</td></tr>
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<tr class="memitem:ga70de31c814e36b7bb2b752e7b62bf840" id="r_ga70de31c814e36b7bb2b752e7b62bf840"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70de31c814e36b7bb2b752e7b62bf840">ETH_DMASR_RPSS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad2630d1d889e82544e5f3eaaa0c73efb">ETH_DMASR_RPSS_Msk</a> /* Receive process stopped <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga70de31c814e36b7bb2b752e7b62bf840"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaafcf0fea72f556ad86e10f1f4261fdfe" id="r_gaafcf0fea72f556ad86e10f1f4261fdfe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafcf0fea72f556ad86e10f1f4261fdfe">ETH_DMASR_RBUS_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaafcf0fea72f556ad86e10f1f4261fdfe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03519d5ceec7c307530cd4d84ab77a86" id="r_ga03519d5ceec7c307530cd4d84ab77a86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03519d5ceec7c307530cd4d84ab77a86">ETH_DMASR_RBUS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaafcf0fea72f556ad86e10f1f4261fdfe">ETH_DMASR_RBUS_Pos</a>)</td></tr>
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<tr class="separator:ga03519d5ceec7c307530cd4d84ab77a86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5569311c70d6ededf186d9a8af19d884" id="r_ga5569311c70d6ededf186d9a8af19d884"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5569311c70d6ededf186d9a8af19d884">ETH_DMASR_RBUS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga03519d5ceec7c307530cd4d84ab77a86">ETH_DMASR_RBUS_Msk</a> /* Receive buffer unavailable <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga5569311c70d6ededf186d9a8af19d884"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6121b0165acc877d7927a4c4c4cde2d0" id="r_ga6121b0165acc877d7927a4c4c4cde2d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6121b0165acc877d7927a4c4c4cde2d0">ETH_DMASR_RS_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga6121b0165acc877d7927a4c4c4cde2d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad460f6aaea486c070dec64bbe36e7fa8" id="r_gad460f6aaea486c070dec64bbe36e7fa8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad460f6aaea486c070dec64bbe36e7fa8">ETH_DMASR_RS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6121b0165acc877d7927a4c4c4cde2d0">ETH_DMASR_RS_Pos</a>)</td></tr>
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<tr class="separator:gad460f6aaea486c070dec64bbe36e7fa8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40f33df77007eab0110e1ffef365a2df" id="r_ga40f33df77007eab0110e1ffef365a2df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40f33df77007eab0110e1ffef365a2df">ETH_DMASR_RS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad460f6aaea486c070dec64bbe36e7fa8">ETH_DMASR_RS_Msk</a> /* Receive <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga40f33df77007eab0110e1ffef365a2df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea24133f548e4e4cfc21d0074a61a2e6" id="r_gaea24133f548e4e4cfc21d0074a61a2e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea24133f548e4e4cfc21d0074a61a2e6">ETH_DMASR_TUS_Pos</a>   (5U)</td></tr>
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<tr class="separator:gaea24133f548e4e4cfc21d0074a61a2e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3a7203a5fb55c1d6a69e6daab2e961b" id="r_gab3a7203a5fb55c1d6a69e6daab2e961b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3a7203a5fb55c1d6a69e6daab2e961b">ETH_DMASR_TUS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea24133f548e4e4cfc21d0074a61a2e6">ETH_DMASR_TUS_Pos</a>)</td></tr>
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<tr class="separator:gab3a7203a5fb55c1d6a69e6daab2e961b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2597865c464586829cec4f8d26fb1f1" id="r_gaf2597865c464586829cec4f8d26fb1f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2597865c464586829cec4f8d26fb1f1">ETH_DMASR_TUS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab3a7203a5fb55c1d6a69e6daab2e961b">ETH_DMASR_TUS_Msk</a> /* Transmit underflow <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:gaf2597865c464586829cec4f8d26fb1f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73b5f22a117c3ef116e9506999b5a3a0" id="r_ga73b5f22a117c3ef116e9506999b5a3a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73b5f22a117c3ef116e9506999b5a3a0">ETH_DMASR_ROS_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga73b5f22a117c3ef116e9506999b5a3a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89c38680c790e1e1717c0a0c76c4f9ef" id="r_ga89c38680c790e1e1717c0a0c76c4f9ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89c38680c790e1e1717c0a0c76c4f9ef">ETH_DMASR_ROS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga73b5f22a117c3ef116e9506999b5a3a0">ETH_DMASR_ROS_Pos</a>)</td></tr>
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<tr class="separator:ga89c38680c790e1e1717c0a0c76c4f9ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c2f1e3cb729230b1099026b6a53b867" id="r_ga0c2f1e3cb729230b1099026b6a53b867"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c2f1e3cb729230b1099026b6a53b867">ETH_DMASR_ROS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga89c38680c790e1e1717c0a0c76c4f9ef">ETH_DMASR_ROS_Msk</a> /* Receive overflow <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga0c2f1e3cb729230b1099026b6a53b867"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1736d46500149b490b990061e0e6504a" id="r_ga1736d46500149b490b990061e0e6504a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1736d46500149b490b990061e0e6504a">ETH_DMASR_TJTS_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga1736d46500149b490b990061e0e6504a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43884645887bb7d31bf18e4e5709d7dc" id="r_ga43884645887bb7d31bf18e4e5709d7dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43884645887bb7d31bf18e4e5709d7dc">ETH_DMASR_TJTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1736d46500149b490b990061e0e6504a">ETH_DMASR_TJTS_Pos</a>)</td></tr>
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<tr class="separator:ga43884645887bb7d31bf18e4e5709d7dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c543637a7e9669b8bdb12265b5ff448" id="r_ga8c543637a7e9669b8bdb12265b5ff448"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c543637a7e9669b8bdb12265b5ff448">ETH_DMASR_TJTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga43884645887bb7d31bf18e4e5709d7dc">ETH_DMASR_TJTS_Msk</a> /* Transmit jabber timeout <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga8c543637a7e9669b8bdb12265b5ff448"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadae620d299f7887143c10c6b67953637" id="r_gadae620d299f7887143c10c6b67953637"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadae620d299f7887143c10c6b67953637">ETH_DMASR_TBUS_Pos</a>   (2U)</td></tr>
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<tr class="separator:gadae620d299f7887143c10c6b67953637"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca6dd2813fb9e0bdf4bccedba156e4c7" id="r_gaca6dd2813fb9e0bdf4bccedba156e4c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca6dd2813fb9e0bdf4bccedba156e4c7">ETH_DMASR_TBUS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadae620d299f7887143c10c6b67953637">ETH_DMASR_TBUS_Pos</a>)</td></tr>
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<tr class="separator:gaca6dd2813fb9e0bdf4bccedba156e4c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26668ea80a2d794d72c0a441aa73d0d7" id="r_ga26668ea80a2d794d72c0a441aa73d0d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26668ea80a2d794d72c0a441aa73d0d7">ETH_DMASR_TBUS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaca6dd2813fb9e0bdf4bccedba156e4c7">ETH_DMASR_TBUS_Msk</a> /* Transmit buffer unavailable <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga26668ea80a2d794d72c0a441aa73d0d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98138bcfbccf33bbfe3e5556ebf5d394" id="r_ga98138bcfbccf33bbfe3e5556ebf5d394"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98138bcfbccf33bbfe3e5556ebf5d394">ETH_DMASR_TPSS_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga98138bcfbccf33bbfe3e5556ebf5d394"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga531f361a12151e7c1335f9133526edb5" id="r_ga531f361a12151e7c1335f9133526edb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga531f361a12151e7c1335f9133526edb5">ETH_DMASR_TPSS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga98138bcfbccf33bbfe3e5556ebf5d394">ETH_DMASR_TPSS_Pos</a>)</td></tr>
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<tr class="separator:ga531f361a12151e7c1335f9133526edb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad48c871e98a7794ce6cd8294baee114a" id="r_gad48c871e98a7794ce6cd8294baee114a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad48c871e98a7794ce6cd8294baee114a">ETH_DMASR_TPSS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga531f361a12151e7c1335f9133526edb5">ETH_DMASR_TPSS_Msk</a> /* Transmit process stopped <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:gad48c871e98a7794ce6cd8294baee114a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab853a917a2d74fa41e630058426b301d" id="r_gab853a917a2d74fa41e630058426b301d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab853a917a2d74fa41e630058426b301d">ETH_DMASR_TS_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab853a917a2d74fa41e630058426b301d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabfe8fdf02110a1d44c6f28f1d641d92f" id="r_gabfe8fdf02110a1d44c6f28f1d641d92f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfe8fdf02110a1d44c6f28f1d641d92f">ETH_DMASR_TS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab853a917a2d74fa41e630058426b301d">ETH_DMASR_TS_Pos</a>)</td></tr>
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<tr class="separator:gabfe8fdf02110a1d44c6f28f1d641d92f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9aa47191609cba66df647cb7e8e10974" id="r_ga9aa47191609cba66df647cb7e8e10974"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9aa47191609cba66df647cb7e8e10974">ETH_DMASR_TS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabfe8fdf02110a1d44c6f28f1d641d92f">ETH_DMASR_TS_Msk</a> /* Transmit <a class="el" href="mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6">status</a> */</td></tr>
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<tr class="separator:ga9aa47191609cba66df647cb7e8e10974"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60ee4d9125ea52f825f501b8fb3a5023" id="r_ga60ee4d9125ea52f825f501b8fb3a5023"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60ee4d9125ea52f825f501b8fb3a5023">ETH_DMAOMR_DTCEFD_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga60ee4d9125ea52f825f501b8fb3a5023"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57a12e235193d9a8db8d635b59287bdc" id="r_ga57a12e235193d9a8db8d635b59287bdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57a12e235193d9a8db8d635b59287bdc">ETH_DMAOMR_DTCEFD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga60ee4d9125ea52f825f501b8fb3a5023">ETH_DMAOMR_DTCEFD_Pos</a>)</td></tr>
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<tr class="separator:ga57a12e235193d9a8db8d635b59287bdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade93bfc37c0b1fc371b2fa1278ee7dfd" id="r_gade93bfc37c0b1fc371b2fa1278ee7dfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade93bfc37c0b1fc371b2fa1278ee7dfd">ETH_DMAOMR_DTCEFD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57a12e235193d9a8db8d635b59287bdc">ETH_DMAOMR_DTCEFD_Msk</a> /* Disable Dropping of TCP/IP checksum error frames */</td></tr>
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<tr class="separator:gade93bfc37c0b1fc371b2fa1278ee7dfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac568f4c7cfdae0a997fae6d41b397772" id="r_gac568f4c7cfdae0a997fae6d41b397772"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac568f4c7cfdae0a997fae6d41b397772">ETH_DMAOMR_RSF_Pos</a>   (25U)</td></tr>
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<tr class="separator:gac568f4c7cfdae0a997fae6d41b397772"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac86b0ef8cd7b378ad33471bf63fabf28" id="r_gac86b0ef8cd7b378ad33471bf63fabf28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac86b0ef8cd7b378ad33471bf63fabf28">ETH_DMAOMR_RSF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac568f4c7cfdae0a997fae6d41b397772">ETH_DMAOMR_RSF_Pos</a>)</td></tr>
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<tr class="memitem:ga7132ff722841d431f9c6d3fc7e0c8912" id="r_ga7132ff722841d431f9c6d3fc7e0c8912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7132ff722841d431f9c6d3fc7e0c8912">ETH_DMAOMR_RSF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac86b0ef8cd7b378ad33471bf63fabf28">ETH_DMAOMR_RSF_Msk</a> /* Receive store and forward */</td></tr>
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<tr class="separator:ga7132ff722841d431f9c6d3fc7e0c8912"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2b6e2a9d1a9466c95e92fe1a095158f" id="r_gab2b6e2a9d1a9466c95e92fe1a095158f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2b6e2a9d1a9466c95e92fe1a095158f">ETH_DMAOMR_DFRF_Pos</a>   (24U)</td></tr>
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<tr class="memitem:ga58b42f95e34f9fd0fd26a720830cef43" id="r_ga58b42f95e34f9fd0fd26a720830cef43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58b42f95e34f9fd0fd26a720830cef43">ETH_DMAOMR_DFRF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab2b6e2a9d1a9466c95e92fe1a095158f">ETH_DMAOMR_DFRF_Pos</a>)</td></tr>
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<tr class="separator:ga58b42f95e34f9fd0fd26a720830cef43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61cfaa51bb7973e7e3c4fd6d549c88b2" id="r_ga61cfaa51bb7973e7e3c4fd6d549c88b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61cfaa51bb7973e7e3c4fd6d549c88b2">ETH_DMAOMR_DFRF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga58b42f95e34f9fd0fd26a720830cef43">ETH_DMAOMR_DFRF_Msk</a> /* Disable flushing of received frames */</td></tr>
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<tr class="separator:ga61cfaa51bb7973e7e3c4fd6d549c88b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c6ccd5e3a792ff5bb20751121db1ad4" id="r_ga3c6ccd5e3a792ff5bb20751121db1ad4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c6ccd5e3a792ff5bb20751121db1ad4">ETH_DMAOMR_TSF_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga3c6ccd5e3a792ff5bb20751121db1ad4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga627c0721df614ee7895be0c8603965ab" id="r_ga627c0721df614ee7895be0c8603965ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga627c0721df614ee7895be0c8603965ab">ETH_DMAOMR_TSF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c6ccd5e3a792ff5bb20751121db1ad4">ETH_DMAOMR_TSF_Pos</a>)</td></tr>
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<tr class="memitem:ga600b35b875335358746524e5f6760613" id="r_ga600b35b875335358746524e5f6760613"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga600b35b875335358746524e5f6760613">ETH_DMAOMR_TSF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga627c0721df614ee7895be0c8603965ab">ETH_DMAOMR_TSF_Msk</a> /* Transmit store and forward */</td></tr>
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<tr class="memitem:gae8d8c2e989f7e596b73202f7c41361c7" id="r_gae8d8c2e989f7e596b73202f7c41361c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8d8c2e989f7e596b73202f7c41361c7">ETH_DMAOMR_FTF_Pos</a>   (20U)</td></tr>
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<tr class="separator:gae8d8c2e989f7e596b73202f7c41361c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ef2167aa40e49e8f8d49b0283a8f832" id="r_ga2ef2167aa40e49e8f8d49b0283a8f832"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ef2167aa40e49e8f8d49b0283a8f832">ETH_DMAOMR_FTF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae8d8c2e989f7e596b73202f7c41361c7">ETH_DMAOMR_FTF_Pos</a>)</td></tr>
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<tr class="separator:ga2ef2167aa40e49e8f8d49b0283a8f832"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ba6031456a00e99638005b7af823a49" id="r_ga6ba6031456a00e99638005b7af823a49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6ba6031456a00e99638005b7af823a49">ETH_DMAOMR_FTF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ef2167aa40e49e8f8d49b0283a8f832">ETH_DMAOMR_FTF_Msk</a> /* Flush transmit FIFO */</td></tr>
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<tr class="separator:ga6ba6031456a00e99638005b7af823a49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b3ede16f6855eec35690336a66089e3" id="r_ga9b3ede16f6855eec35690336a66089e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b3ede16f6855eec35690336a66089e3">ETH_DMAOMR_TTC_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga9b3ede16f6855eec35690336a66089e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3c316b48c8c3a4e683b6e56cefa844d" id="r_gab3c316b48c8c3a4e683b6e56cefa844d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3c316b48c8c3a4e683b6e56cefa844d">ETH_DMAOMR_TTC_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9b3ede16f6855eec35690336a66089e3">ETH_DMAOMR_TTC_Pos</a>)</td></tr>
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<tr class="separator:gab3c316b48c8c3a4e683b6e56cefa844d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8af2f55493df254efed28cad7fb72651" id="r_ga8af2f55493df254efed28cad7fb72651"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8af2f55493df254efed28cad7fb72651">ETH_DMAOMR_TTC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab3c316b48c8c3a4e683b6e56cefa844d">ETH_DMAOMR_TTC_Msk</a> /* Transmit threshold control */</td></tr>
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<tr class="separator:ga8af2f55493df254efed28cad7fb72651"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca0372554b5b8c2b816071ced929b30f" id="r_gaca0372554b5b8c2b816071ced929b30f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca0372554b5b8c2b816071ced929b30f">ETH_DMAOMR_TTC_64Bytes</a>   0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */</td></tr>
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<tr class="separator:gaca0372554b5b8c2b816071ced929b30f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a0af7e5f2074a30e33e4845b1c72155" id="r_ga0a0af7e5f2074a30e33e4845b1c72155"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a0af7e5f2074a30e33e4845b1c72155">ETH_DMAOMR_TTC_128Bytes</a>   0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */</td></tr>
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<tr class="separator:ga0a0af7e5f2074a30e33e4845b1c72155"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a29aa54f61418b0086bef0d8c9a4868" id="r_ga4a29aa54f61418b0086bef0d8c9a4868"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a29aa54f61418b0086bef0d8c9a4868">ETH_DMAOMR_TTC_192Bytes</a>   0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */</td></tr>
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<tr class="separator:ga4a29aa54f61418b0086bef0d8c9a4868"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9d703eb56388097660839c0dbb2dcf4" id="r_gae9d703eb56388097660839c0dbb2dcf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9d703eb56388097660839c0dbb2dcf4">ETH_DMAOMR_TTC_256Bytes</a>   0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */</td></tr>
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<tr class="separator:gae9d703eb56388097660839c0dbb2dcf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6c6cd2f59e4f784ef22ca7873bcafe6" id="r_gac6c6cd2f59e4f784ef22ca7873bcafe6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6c6cd2f59e4f784ef22ca7873bcafe6">ETH_DMAOMR_TTC_40Bytes</a>   0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */</td></tr>
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<tr class="separator:gac6c6cd2f59e4f784ef22ca7873bcafe6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e74522b40a38dbc62dca1cc87f7b13f" id="r_ga3e74522b40a38dbc62dca1cc87f7b13f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e74522b40a38dbc62dca1cc87f7b13f">ETH_DMAOMR_TTC_32Bytes</a>   0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */</td></tr>
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<tr class="separator:ga3e74522b40a38dbc62dca1cc87f7b13f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2e990a61fd2ca6d1f5d9e0fddfc1a76" id="r_gac2e990a61fd2ca6d1f5d9e0fddfc1a76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2e990a61fd2ca6d1f5d9e0fddfc1a76">ETH_DMAOMR_TTC_24Bytes</a>   0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */</td></tr>
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<tr class="separator:gac2e990a61fd2ca6d1f5d9e0fddfc1a76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c21df36ca8ecb3c2d016cd4c683aded" id="r_ga6c21df36ca8ecb3c2d016cd4c683aded"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c21df36ca8ecb3c2d016cd4c683aded">ETH_DMAOMR_TTC_16Bytes</a>   0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */</td></tr>
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<tr class="separator:ga6c21df36ca8ecb3c2d016cd4c683aded"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e013ae0230f9b0c4f9598bb38c93b1e" id="r_ga9e013ae0230f9b0c4f9598bb38c93b1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e013ae0230f9b0c4f9598bb38c93b1e">ETH_DMAOMR_ST_Pos</a>   (13U)</td></tr>
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<tr class="memitem:gabd2cf0246f5b06eac0b6534c9802ac29" id="r_gabd2cf0246f5b06eac0b6534c9802ac29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd2cf0246f5b06eac0b6534c9802ac29">ETH_DMAOMR_ST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e013ae0230f9b0c4f9598bb38c93b1e">ETH_DMAOMR_ST_Pos</a>)</td></tr>
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<tr class="separator:gabd2cf0246f5b06eac0b6534c9802ac29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f15d70215b151c4c151b7b8475939ce" id="r_ga5f15d70215b151c4c151b7b8475939ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f15d70215b151c4c151b7b8475939ce">ETH_DMAOMR_ST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabd2cf0246f5b06eac0b6534c9802ac29">ETH_DMAOMR_ST_Msk</a> /* Start/stop transmission command */</td></tr>
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<tr class="separator:ga5f15d70215b151c4c151b7b8475939ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4562507352bcedf8243532c8f3509cd1" id="r_ga4562507352bcedf8243532c8f3509cd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4562507352bcedf8243532c8f3509cd1">ETH_DMAOMR_FEF_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga4562507352bcedf8243532c8f3509cd1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46da3dc9006268330b091ea369040c7e" id="r_ga46da3dc9006268330b091ea369040c7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46da3dc9006268330b091ea369040c7e">ETH_DMAOMR_FEF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4562507352bcedf8243532c8f3509cd1">ETH_DMAOMR_FEF_Pos</a>)</td></tr>
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<tr class="separator:ga46da3dc9006268330b091ea369040c7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ff2d7be55ac4e29a18d8490012d8d8f" id="r_ga9ff2d7be55ac4e29a18d8490012d8d8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ff2d7be55ac4e29a18d8490012d8d8f">ETH_DMAOMR_FEF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga46da3dc9006268330b091ea369040c7e">ETH_DMAOMR_FEF_Msk</a> /* Forward error frames */</td></tr>
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<tr class="separator:ga9ff2d7be55ac4e29a18d8490012d8d8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad86ef8a3fdd31501c9ad670c6e0ee358" id="r_gad86ef8a3fdd31501c9ad670c6e0ee358"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad86ef8a3fdd31501c9ad670c6e0ee358">ETH_DMAOMR_FUGF_Pos</a>   (6U)</td></tr>
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<tr class="separator:gad86ef8a3fdd31501c9ad670c6e0ee358"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb00925901abe34858a008f599a3949d" id="r_gafb00925901abe34858a008f599a3949d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb00925901abe34858a008f599a3949d">ETH_DMAOMR_FUGF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad86ef8a3fdd31501c9ad670c6e0ee358">ETH_DMAOMR_FUGF_Pos</a>)</td></tr>
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<tr class="separator:gafb00925901abe34858a008f599a3949d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7fb0b48ffa17fb3c37e730e63790b95" id="r_gad7fb0b48ffa17fb3c37e730e63790b95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7fb0b48ffa17fb3c37e730e63790b95">ETH_DMAOMR_FUGF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb00925901abe34858a008f599a3949d">ETH_DMAOMR_FUGF_Msk</a> /* Forward undersized good frames */</td></tr>
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<tr class="separator:gad7fb0b48ffa17fb3c37e730e63790b95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67e6a96f920fd6dbe951e83bab2fcbc8" id="r_ga67e6a96f920fd6dbe951e83bab2fcbc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67e6a96f920fd6dbe951e83bab2fcbc8">ETH_DMAOMR_RTC_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga67e6a96f920fd6dbe951e83bab2fcbc8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a10ffb355ad5a39fcee6c591a74c4f1" id="r_ga6a10ffb355ad5a39fcee6c591a74c4f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a10ffb355ad5a39fcee6c591a74c4f1">ETH_DMAOMR_RTC_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67e6a96f920fd6dbe951e83bab2fcbc8">ETH_DMAOMR_RTC_Pos</a>)</td></tr>
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<tr class="memitem:ga00653932f863ff8c73752e4dea63283d" id="r_ga00653932f863ff8c73752e4dea63283d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00653932f863ff8c73752e4dea63283d">ETH_DMAOMR_RTC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a10ffb355ad5a39fcee6c591a74c4f1">ETH_DMAOMR_RTC_Msk</a> /* receive threshold control */</td></tr>
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<tr class="memitem:ga29ec3c609bf796437bb50879be53974e" id="r_ga29ec3c609bf796437bb50879be53974e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29ec3c609bf796437bb50879be53974e">ETH_DMAOMR_RTC_64Bytes</a>   0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */</td></tr>
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<tr class="memitem:ga6f4f5e1950abb65d6ed23e30994b7a26" id="r_ga6f4f5e1950abb65d6ed23e30994b7a26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f4f5e1950abb65d6ed23e30994b7a26">ETH_DMAOMR_RTC_32Bytes</a>   0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */</td></tr>
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<tr class="separator:ga6f4f5e1950abb65d6ed23e30994b7a26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf73706fb0cf9a03909a55e3bcd19c75c" id="r_gaf73706fb0cf9a03909a55e3bcd19c75c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf73706fb0cf9a03909a55e3bcd19c75c">ETH_DMAOMR_RTC_96Bytes</a>   0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */</td></tr>
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<tr class="memitem:gab7099f07f7c61fdc118cebe38db796e9" id="r_gab7099f07f7c61fdc118cebe38db796e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7099f07f7c61fdc118cebe38db796e9">ETH_DMAOMR_RTC_128Bytes</a>   0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */</td></tr>
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<tr class="memitem:gae0704646af78b6cf53b47640835429ae" id="r_gae0704646af78b6cf53b47640835429ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0704646af78b6cf53b47640835429ae">ETH_DMAOMR_OSF_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga3643718f1c533d40fd4f9868544cdb66" id="r_ga3643718f1c533d40fd4f9868544cdb66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3643718f1c533d40fd4f9868544cdb66">ETH_DMAOMR_OSF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae0704646af78b6cf53b47640835429ae">ETH_DMAOMR_OSF_Pos</a>)</td></tr>
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<tr class="memitem:ga6a9e1270eefa558420deba526b7cd2c2" id="r_ga6a9e1270eefa558420deba526b7cd2c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a9e1270eefa558420deba526b7cd2c2">ETH_DMAOMR_OSF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3643718f1c533d40fd4f9868544cdb66">ETH_DMAOMR_OSF_Msk</a> /* operate on second frame */</td></tr>
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<tr class="memitem:gaac945eacab78cad8b2f6149ad6ab3570" id="r_gaac945eacab78cad8b2f6149ad6ab3570"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac945eacab78cad8b2f6149ad6ab3570">ETH_DMAOMR_SR_Pos</a>   (1U)</td></tr>
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<tr class="memitem:ga16eb92e4f7b229407dcf6e7e836f3504" id="r_ga16eb92e4f7b229407dcf6e7e836f3504"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16eb92e4f7b229407dcf6e7e836f3504">ETH_DMAOMR_SR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaac945eacab78cad8b2f6149ad6ab3570">ETH_DMAOMR_SR_Pos</a>)</td></tr>
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<tr class="memitem:gaf08aaa0c916bb56d2e4e71fdf0f034da" id="r_gaf08aaa0c916bb56d2e4e71fdf0f034da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf08aaa0c916bb56d2e4e71fdf0f034da">ETH_DMAOMR_SR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga16eb92e4f7b229407dcf6e7e836f3504">ETH_DMAOMR_SR_Msk</a> /* Start/stop receive */</td></tr>
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<tr class="memitem:ga6c2bf9775f1b2daae49c199875633b31" id="r_ga6c2bf9775f1b2daae49c199875633b31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c2bf9775f1b2daae49c199875633b31">ETH_DMAIER_NISE_Pos</a>   (16U)</td></tr>
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<tr class="memitem:ga1c8386338d800b390b1a94a7bf353b0b" id="r_ga1c8386338d800b390b1a94a7bf353b0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c8386338d800b390b1a94a7bf353b0b">ETH_DMAIER_NISE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c2bf9775f1b2daae49c199875633b31">ETH_DMAIER_NISE_Pos</a>)</td></tr>
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<tr class="memitem:ga3c12b833cb206d8bafa7d60faebea805" id="r_ga3c12b833cb206d8bafa7d60faebea805"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c12b833cb206d8bafa7d60faebea805">ETH_DMAIER_NISE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c8386338d800b390b1a94a7bf353b0b">ETH_DMAIER_NISE_Msk</a> /* Normal interrupt summary enable */</td></tr>
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<tr class="separator:ga3c12b833cb206d8bafa7d60faebea805"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea77db4415f16fb34552c4f2e4672ec2" id="r_gaea77db4415f16fb34552c4f2e4672ec2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea77db4415f16fb34552c4f2e4672ec2">ETH_DMAIER_AISE_Pos</a>   (15U)</td></tr>
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<tr class="memitem:gabde04568b44b661a4ae2938663c0af68" id="r_gabde04568b44b661a4ae2938663c0af68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabde04568b44b661a4ae2938663c0af68">ETH_DMAIER_AISE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea77db4415f16fb34552c4f2e4672ec2">ETH_DMAIER_AISE_Pos</a>)</td></tr>
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<tr class="memitem:ga7ae9340fa928abb4664efbb5c8478756" id="r_ga7ae9340fa928abb4664efbb5c8478756"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ae9340fa928abb4664efbb5c8478756">ETH_DMAIER_AISE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabde04568b44b661a4ae2938663c0af68">ETH_DMAIER_AISE_Msk</a> /* Abnormal interrupt summary enable */</td></tr>
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<tr class="memitem:gabf996fdcd5fe7a43c250aee861d96cf8" id="r_gabf996fdcd5fe7a43c250aee861d96cf8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabf996fdcd5fe7a43c250aee861d96cf8">ETH_DMAIER_ERIE_Pos</a>   (14U)</td></tr>
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<tr class="memitem:gac2fbc6e64e1d5c1bf78ada2bf0bef741" id="r_gac2fbc6e64e1d5c1bf78ada2bf0bef741"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2fbc6e64e1d5c1bf78ada2bf0bef741">ETH_DMAIER_ERIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabf996fdcd5fe7a43c250aee861d96cf8">ETH_DMAIER_ERIE_Pos</a>)</td></tr>
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<tr class="separator:gac2fbc6e64e1d5c1bf78ada2bf0bef741"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fe43c4432e0505a5509424665692807" id="r_ga4fe43c4432e0505a5509424665692807"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fe43c4432e0505a5509424665692807">ETH_DMAIER_ERIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac2fbc6e64e1d5c1bf78ada2bf0bef741">ETH_DMAIER_ERIE_Msk</a> /* Early receive interrupt enable */</td></tr>
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<tr class="memitem:ga0e17cb26491d68d522f4aec00288a171" id="r_ga0e17cb26491d68d522f4aec00288a171"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e17cb26491d68d522f4aec00288a171">ETH_DMAIER_FBEIE_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0e17cb26491d68d522f4aec00288a171"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1d818d82852308c7dc3884e4ab6bd0d" id="r_gab1d818d82852308c7dc3884e4ab6bd0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1d818d82852308c7dc3884e4ab6bd0d">ETH_DMAIER_FBEIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e17cb26491d68d522f4aec00288a171">ETH_DMAIER_FBEIE_Pos</a>)</td></tr>
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<tr class="separator:gab1d818d82852308c7dc3884e4ab6bd0d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92e94d1d37660b7cca9306ac020b4110" id="r_ga92e94d1d37660b7cca9306ac020b4110"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92e94d1d37660b7cca9306ac020b4110">ETH_DMAIER_FBEIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab1d818d82852308c7dc3884e4ab6bd0d">ETH_DMAIER_FBEIE_Msk</a> /* Fatal bus error interrupt enable */</td></tr>
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<tr class="memitem:ga369f3ea6bca9aebeceaf6b6d4d51b485" id="r_ga369f3ea6bca9aebeceaf6b6d4d51b485"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga369f3ea6bca9aebeceaf6b6d4d51b485">ETH_DMAIER_ETIE_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga369f3ea6bca9aebeceaf6b6d4d51b485"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac753c8cb27122c6d9bb32ab8cfc2ae64" id="r_gac753c8cb27122c6d9bb32ab8cfc2ae64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac753c8cb27122c6d9bb32ab8cfc2ae64">ETH_DMAIER_ETIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga369f3ea6bca9aebeceaf6b6d4d51b485">ETH_DMAIER_ETIE_Pos</a>)</td></tr>
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<tr class="separator:gac753c8cb27122c6d9bb32ab8cfc2ae64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b1c57b5102ca78372420b45a707b43e" id="r_ga5b1c57b5102ca78372420b45a707b43e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b1c57b5102ca78372420b45a707b43e">ETH_DMAIER_ETIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac753c8cb27122c6d9bb32ab8cfc2ae64">ETH_DMAIER_ETIE_Msk</a> /* Early transmit interrupt enable */</td></tr>
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<tr class="separator:ga5b1c57b5102ca78372420b45a707b43e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89d02c397b29b9a25d117baef252c11d" id="r_ga89d02c397b29b9a25d117baef252c11d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89d02c397b29b9a25d117baef252c11d">ETH_DMAIER_RWTIE_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga89d02c397b29b9a25d117baef252c11d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a773793e51e25028b71f7bc22127a84" id="r_ga6a773793e51e25028b71f7bc22127a84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a773793e51e25028b71f7bc22127a84">ETH_DMAIER_RWTIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga89d02c397b29b9a25d117baef252c11d">ETH_DMAIER_RWTIE_Pos</a>)</td></tr>
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<tr class="separator:ga6a773793e51e25028b71f7bc22127a84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa28e115ada97b2e6d793f9d542f93e35" id="r_gaa28e115ada97b2e6d793f9d542f93e35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa28e115ada97b2e6d793f9d542f93e35">ETH_DMAIER_RWTIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a773793e51e25028b71f7bc22127a84">ETH_DMAIER_RWTIE_Msk</a> /* Receive watchdog timeout interrupt enable */</td></tr>
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<tr class="separator:gaa28e115ada97b2e6d793f9d542f93e35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83ecac2aa610bfebcf7ae2d63d8afbb2" id="r_ga83ecac2aa610bfebcf7ae2d63d8afbb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83ecac2aa610bfebcf7ae2d63d8afbb2">ETH_DMAIER_RPSIE_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga83ecac2aa610bfebcf7ae2d63d8afbb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97d3ac01bc13ea08b25b59e5e200aaf4" id="r_ga97d3ac01bc13ea08b25b59e5e200aaf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97d3ac01bc13ea08b25b59e5e200aaf4">ETH_DMAIER_RPSIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga83ecac2aa610bfebcf7ae2d63d8afbb2">ETH_DMAIER_RPSIE_Pos</a>)</td></tr>
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<tr class="separator:ga97d3ac01bc13ea08b25b59e5e200aaf4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcfba49acf14e8a0194e1fef8b1837f7" id="r_gafcfba49acf14e8a0194e1fef8b1837f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcfba49acf14e8a0194e1fef8b1837f7">ETH_DMAIER_RPSIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga97d3ac01bc13ea08b25b59e5e200aaf4">ETH_DMAIER_RPSIE_Msk</a> /* Receive process stopped interrupt enable */</td></tr>
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<tr class="memitem:gac599bb486eff43714e2340c066df6d22" id="r_gac599bb486eff43714e2340c066df6d22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac599bb486eff43714e2340c066df6d22">ETH_DMAIER_RBUIE_Pos</a>   (7U)</td></tr>
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<tr class="memitem:gada6ce4050a22be8bf8ecd9f32a62cb51" id="r_gada6ce4050a22be8bf8ecd9f32a62cb51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada6ce4050a22be8bf8ecd9f32a62cb51">ETH_DMAIER_RBUIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac599bb486eff43714e2340c066df6d22">ETH_DMAIER_RBUIE_Pos</a>)</td></tr>
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<tr class="memitem:ga0c349d0b4aa329d39fcfd10d59de7b26" id="r_ga0c349d0b4aa329d39fcfd10d59de7b26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c349d0b4aa329d39fcfd10d59de7b26">ETH_DMAIER_RBUIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada6ce4050a22be8bf8ecd9f32a62cb51">ETH_DMAIER_RBUIE_Msk</a> /* Receive buffer unavailable interrupt enable */</td></tr>
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<tr class="memitem:gaba03ad718ced9224bb8b34762994818e" id="r_gaba03ad718ced9224bb8b34762994818e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba03ad718ced9224bb8b34762994818e">ETH_DMAIER_RIE_Pos</a>   (6U)</td></tr>
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<tr class="memitem:gab5bd8f0165aaa498cdafe884dd1343d9" id="r_gab5bd8f0165aaa498cdafe884dd1343d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5bd8f0165aaa498cdafe884dd1343d9">ETH_DMAIER_RIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaba03ad718ced9224bb8b34762994818e">ETH_DMAIER_RIE_Pos</a>)</td></tr>
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<tr class="memitem:ga4bce67fd8ee3363c1ab95b9f5324f745" id="r_ga4bce67fd8ee3363c1ab95b9f5324f745"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4bce67fd8ee3363c1ab95b9f5324f745">ETH_DMAIER_RIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab5bd8f0165aaa498cdafe884dd1343d9">ETH_DMAIER_RIE_Msk</a> /* Receive interrupt enable */</td></tr>
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<tr class="memitem:gafe6b97c4e2981f246308d884fb2acd78" id="r_gafe6b97c4e2981f246308d884fb2acd78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe6b97c4e2981f246308d884fb2acd78">ETH_DMAIER_TUIE_Pos</a>   (5U)</td></tr>
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<tr class="memitem:ga3479e12a504721ace0d9c1f2e9deae52" id="r_ga3479e12a504721ace0d9c1f2e9deae52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3479e12a504721ace0d9c1f2e9deae52">ETH_DMAIER_TUIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafe6b97c4e2981f246308d884fb2acd78">ETH_DMAIER_TUIE_Pos</a>)</td></tr>
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<tr class="memitem:ga91a59aa3adff595051bdda2da948ec71" id="r_ga91a59aa3adff595051bdda2da948ec71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91a59aa3adff595051bdda2da948ec71">ETH_DMAIER_TUIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3479e12a504721ace0d9c1f2e9deae52">ETH_DMAIER_TUIE_Msk</a> /* Transmit Underflow interrupt enable */</td></tr>
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<tr class="memitem:ga2e9037ad879e5483c5c2bb1989a09b89" id="r_ga2e9037ad879e5483c5c2bb1989a09b89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e9037ad879e5483c5c2bb1989a09b89">ETH_DMAIER_ROIE_Pos</a>   (4U)</td></tr>
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<tr class="memitem:gaf567f33d5a3d85984e52c65705f2c334" id="r_gaf567f33d5a3d85984e52c65705f2c334"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf567f33d5a3d85984e52c65705f2c334">ETH_DMAIER_ROIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e9037ad879e5483c5c2bb1989a09b89">ETH_DMAIER_ROIE_Pos</a>)</td></tr>
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<tr class="memitem:gab3cdf8611ab9a0a7f4fc0e0090a33ba6" id="r_gab3cdf8611ab9a0a7f4fc0e0090a33ba6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3cdf8611ab9a0a7f4fc0e0090a33ba6">ETH_DMAIER_ROIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf567f33d5a3d85984e52c65705f2c334">ETH_DMAIER_ROIE_Msk</a> /* Receive Overflow interrupt enable */</td></tr>
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<tr class="memitem:gad439769a7926aaf62c3053133fe87beb" id="r_gad439769a7926aaf62c3053133fe87beb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad439769a7926aaf62c3053133fe87beb">ETH_DMAIER_TJTIE_Pos</a>   (3U)</td></tr>
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<tr class="memitem:gaf14e7f30233722f892e6af1d6428f7b8" id="r_gaf14e7f30233722f892e6af1d6428f7b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf14e7f30233722f892e6af1d6428f7b8">ETH_DMAIER_TJTIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad439769a7926aaf62c3053133fe87beb">ETH_DMAIER_TJTIE_Pos</a>)</td></tr>
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<tr class="memitem:ga7a9cd48115f0b32941ee3087e9c60ec9" id="r_ga7a9cd48115f0b32941ee3087e9c60ec9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a9cd48115f0b32941ee3087e9c60ec9">ETH_DMAIER_TJTIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf14e7f30233722f892e6af1d6428f7b8">ETH_DMAIER_TJTIE_Msk</a> /* Transmit jabber timeout interrupt enable */</td></tr>
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<tr class="memitem:ga436fa7c9599495a1a1a55eb40ec00d63" id="r_ga436fa7c9599495a1a1a55eb40ec00d63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga436fa7c9599495a1a1a55eb40ec00d63">ETH_DMAIER_TBUIE_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga436fa7c9599495a1a1a55eb40ec00d63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38bf7b752b9e72761ab2bd11400e7730" id="r_ga38bf7b752b9e72761ab2bd11400e7730"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38bf7b752b9e72761ab2bd11400e7730">ETH_DMAIER_TBUIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga436fa7c9599495a1a1a55eb40ec00d63">ETH_DMAIER_TBUIE_Pos</a>)</td></tr>
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<tr class="memitem:ga37fc5c9c473407d77a379d7032147b59" id="r_ga37fc5c9c473407d77a379d7032147b59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37fc5c9c473407d77a379d7032147b59">ETH_DMAIER_TBUIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga38bf7b752b9e72761ab2bd11400e7730">ETH_DMAIER_TBUIE_Msk</a> /* Transmit buffer unavailable interrupt enable */</td></tr>
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<tr class="separator:ga37fc5c9c473407d77a379d7032147b59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08ab269c60b0052ee58983d0fd7ceff0" id="r_ga08ab269c60b0052ee58983d0fd7ceff0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08ab269c60b0052ee58983d0fd7ceff0">ETH_DMAIER_TPSIE_Pos</a>   (1U)</td></tr>
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<tr class="memitem:gaa8db6095575b73d506673d78d355fdcb" id="r_gaa8db6095575b73d506673d78d355fdcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8db6095575b73d506673d78d355fdcb">ETH_DMAIER_TPSIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga08ab269c60b0052ee58983d0fd7ceff0">ETH_DMAIER_TPSIE_Pos</a>)</td></tr>
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<tr class="memitem:ga3d4b2c3e0d50326adf0e8b3955aa9972" id="r_ga3d4b2c3e0d50326adf0e8b3955aa9972"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d4b2c3e0d50326adf0e8b3955aa9972">ETH_DMAIER_TPSIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8db6095575b73d506673d78d355fdcb">ETH_DMAIER_TPSIE_Msk</a> /* Transmit process stopped interrupt enable */</td></tr>
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<tr class="memitem:gab7498e400e393f90604c092ce9bd5e74" id="r_gab7498e400e393f90604c092ce9bd5e74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7498e400e393f90604c092ce9bd5e74">ETH_DMAIER_TIE_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab7498e400e393f90604c092ce9bd5e74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a48f7292330cdb3c61e4e499357eb8b" id="r_ga6a48f7292330cdb3c61e4e499357eb8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a48f7292330cdb3c61e4e499357eb8b">ETH_DMAIER_TIE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab7498e400e393f90604c092ce9bd5e74">ETH_DMAIER_TIE_Pos</a>)</td></tr>
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<tr class="separator:ga6a48f7292330cdb3c61e4e499357eb8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a19f069ddf349de788130cefdbc4149" id="r_ga1a19f069ddf349de788130cefdbc4149"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a19f069ddf349de788130cefdbc4149">ETH_DMAIER_TIE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a48f7292330cdb3c61e4e499357eb8b">ETH_DMAIER_TIE_Msk</a> /* Transmit interrupt enable */</td></tr>
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<tr class="memitem:ga8b868e9111c52d02c0df2319e41e40b2" id="r_ga8b868e9111c52d02c0df2319e41e40b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b868e9111c52d02c0df2319e41e40b2">ETH_DMAMFBOCR_OFOC_Pos</a>   (28U)</td></tr>
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<tr class="memitem:gaff5db91b32eee3facb9523b1e8c7f836" id="r_gaff5db91b32eee3facb9523b1e8c7f836"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff5db91b32eee3facb9523b1e8c7f836">ETH_DMAMFBOCR_OFOC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b868e9111c52d02c0df2319e41e40b2">ETH_DMAMFBOCR_OFOC_Pos</a>)</td></tr>
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<tr class="separator:gaff5db91b32eee3facb9523b1e8c7f836"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3793f0a194ff3a19a1559824a821fe61" id="r_ga3793f0a194ff3a19a1559824a821fe61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3793f0a194ff3a19a1559824a821fe61">ETH_DMAMFBOCR_OFOC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaff5db91b32eee3facb9523b1e8c7f836">ETH_DMAMFBOCR_OFOC_Msk</a> /* Overflow bit for FIFO overflow counter */</td></tr>
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<tr class="memitem:gadf9e76a42bbf3d3b6de19402dc3c9cfa" id="r_gadf9e76a42bbf3d3b6de19402dc3c9cfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf9e76a42bbf3d3b6de19402dc3c9cfa">ETH_DMAMFBOCR_MFA_Pos</a>   (17U)</td></tr>
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<tr class="separator:gadf9e76a42bbf3d3b6de19402dc3c9cfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga265274e3d4f38a6e39a08b112fef1b63" id="r_ga265274e3d4f38a6e39a08b112fef1b63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga265274e3d4f38a6e39a08b112fef1b63">ETH_DMAMFBOCR_MFA_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gadf9e76a42bbf3d3b6de19402dc3c9cfa">ETH_DMAMFBOCR_MFA_Pos</a>)</td></tr>
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<tr class="separator:ga265274e3d4f38a6e39a08b112fef1b63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9595307f4b9d38f6e0991fa54c4bae8f" id="r_ga9595307f4b9d38f6e0991fa54c4bae8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9595307f4b9d38f6e0991fa54c4bae8f">ETH_DMAMFBOCR_MFA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga265274e3d4f38a6e39a08b112fef1b63">ETH_DMAMFBOCR_MFA_Msk</a> /* Number of frames missed by the application */</td></tr>
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<tr class="separator:ga9595307f4b9d38f6e0991fa54c4bae8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d8683626bc1e997264dc41e58d7b1e9" id="r_ga0d8683626bc1e997264dc41e58d7b1e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d8683626bc1e997264dc41e58d7b1e9">ETH_DMAMFBOCR_OMFC_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga0d8683626bc1e997264dc41e58d7b1e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga948b0af4c7ca43ee7b22e4db7318c6fd" id="r_ga948b0af4c7ca43ee7b22e4db7318c6fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga948b0af4c7ca43ee7b22e4db7318c6fd">ETH_DMAMFBOCR_OMFC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d8683626bc1e997264dc41e58d7b1e9">ETH_DMAMFBOCR_OMFC_Pos</a>)</td></tr>
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<tr class="separator:ga948b0af4c7ca43ee7b22e4db7318c6fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ffc962868d2b5ed265e7bffd6881aab" id="r_ga9ffc962868d2b5ed265e7bffd6881aab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ffc962868d2b5ed265e7bffd6881aab">ETH_DMAMFBOCR_OMFC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga948b0af4c7ca43ee7b22e4db7318c6fd">ETH_DMAMFBOCR_OMFC_Msk</a> /* Overflow bit for missed frame counter */</td></tr>
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<tr class="memitem:gac9fd0920c44a894d3e2984214df300b3" id="r_gac9fd0920c44a894d3e2984214df300b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9fd0920c44a894d3e2984214df300b3">ETH_DMAMFBOCR_MFC_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gac16af00ecd2def9c483943a7b60bb6ff" id="r_gac16af00ecd2def9c483943a7b60bb6ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac16af00ecd2def9c483943a7b60bb6ff">ETH_DMAMFBOCR_MFC_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9fd0920c44a894d3e2984214df300b3">ETH_DMAMFBOCR_MFC_Pos</a>)</td></tr>
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<tr class="memitem:ga81aa193a52d5b3757a008b84eb0c6182" id="r_ga81aa193a52d5b3757a008b84eb0c6182"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga81aa193a52d5b3757a008b84eb0c6182">ETH_DMAMFBOCR_MFC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac16af00ecd2def9c483943a7b60bb6ff">ETH_DMAMFBOCR_MFC_Msk</a> /* Number of frames missed by the controller */</td></tr>
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<tr class="memitem:gac66c32e504b7893aab68fb675b30686f" id="r_gac66c32e504b7893aab68fb675b30686f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac66c32e504b7893aab68fb675b30686f">ETH_DMACHTDR_HTDAP_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga9e0d1eda1d389b3f99bbe46f26a25959" id="r_ga9e0d1eda1d389b3f99bbe46f26a25959"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e0d1eda1d389b3f99bbe46f26a25959">ETH_DMACHTDR_HTDAP_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac66c32e504b7893aab68fb675b30686f">ETH_DMACHTDR_HTDAP_Pos</a>)</td></tr>
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<tr class="separator:ga9e0d1eda1d389b3f99bbe46f26a25959"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae013d158ee1e13f61069722eff4d52ac" id="r_gae013d158ee1e13f61069722eff4d52ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae013d158ee1e13f61069722eff4d52ac">ETH_DMACHTDR_HTDAP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e0d1eda1d389b3f99bbe46f26a25959">ETH_DMACHTDR_HTDAP_Msk</a> /* Host transmit descriptor address pointer */</td></tr>
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<tr class="memitem:ga28f70ba69e471a3c4142c22529f41057" id="r_ga28f70ba69e471a3c4142c22529f41057"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga28f70ba69e471a3c4142c22529f41057">ETH_DMACHRDR_HRDAP_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga28f70ba69e471a3c4142c22529f41057"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga385d61115e00ef2711fb128ba0bc58a8" id="r_ga385d61115e00ef2711fb128ba0bc58a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga385d61115e00ef2711fb128ba0bc58a8">ETH_DMACHRDR_HRDAP_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga28f70ba69e471a3c4142c22529f41057">ETH_DMACHRDR_HRDAP_Pos</a>)</td></tr>
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<tr class="memitem:gacb91f0f377b2bb0bfffe7df0ad46c7d3" id="r_gacb91f0f377b2bb0bfffe7df0ad46c7d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb91f0f377b2bb0bfffe7df0ad46c7d3">ETH_DMACHRDR_HRDAP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga385d61115e00ef2711fb128ba0bc58a8">ETH_DMACHRDR_HRDAP_Msk</a> /* Host receive descriptor address pointer */</td></tr>
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<tr class="separator:gacb91f0f377b2bb0bfffe7df0ad46c7d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac708faf2f587cf1d4b48a9d9d864dad8" id="r_gac708faf2f587cf1d4b48a9d9d864dad8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac708faf2f587cf1d4b48a9d9d864dad8">ETH_DMACHTBAR_HTBAP_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac708faf2f587cf1d4b48a9d9d864dad8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacc327724f91b8ddb36f526ec8d78dfa" id="r_gaacc327724f91b8ddb36f526ec8d78dfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacc327724f91b8ddb36f526ec8d78dfa">ETH_DMACHTBAR_HTBAP_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac708faf2f587cf1d4b48a9d9d864dad8">ETH_DMACHTBAR_HTBAP_Pos</a>)</td></tr>
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<tr class="separator:gaacc327724f91b8ddb36f526ec8d78dfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3524cdddc8525fe50c6754029011e12" id="r_gad3524cdddc8525fe50c6754029011e12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3524cdddc8525fe50c6754029011e12">ETH_DMACHTBAR_HTBAP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaacc327724f91b8ddb36f526ec8d78dfa">ETH_DMACHTBAR_HTBAP_Msk</a> /* Host transmit buffer address pointer */</td></tr>
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<tr class="memitem:ga7efa5638b78f19fc5df0386817347add" id="r_ga7efa5638b78f19fc5df0386817347add"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7efa5638b78f19fc5df0386817347add">ETH_DMACHRBAR_HRBAP_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7efa5638b78f19fc5df0386817347add"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6260b879f63938dfecd17e8d98f0a6dc" id="r_ga6260b879f63938dfecd17e8d98f0a6dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6260b879f63938dfecd17e8d98f0a6dc">ETH_DMACHRBAR_HRBAP_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7efa5638b78f19fc5df0386817347add">ETH_DMACHRBAR_HRBAP_Pos</a>)</td></tr>
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<tr class="separator:ga6260b879f63938dfecd17e8d98f0a6dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cf1a9ed443f3498b67c658d26468212" id="r_ga1cf1a9ed443f3498b67c658d26468212"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cf1a9ed443f3498b67c658d26468212">ETH_DMACHRBAR_HRBAP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6260b879f63938dfecd17e8d98f0a6dc">ETH_DMACHRBAR_HRBAP_Msk</a> /* Host receive buffer address pointer */</td></tr>
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<tr class="separator:ga1cf1a9ed443f3498b67c658d26468212"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8ebcd754d775e8f9c405194f2b2258d" id="r_gab8ebcd754d775e8f9c405194f2b2258d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8ebcd754d775e8f9c405194f2b2258d">USB_OTG_GOTGCTL_SRQSCS_Pos</a>   (0U)</td></tr>
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<tr class="separator:gab8ebcd754d775e8f9c405194f2b2258d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27144da12fabf5f20058022b7a060375" id="r_ga27144da12fabf5f20058022b7a060375"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27144da12fabf5f20058022b7a060375">USB_OTG_GOTGCTL_SRQSCS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8ebcd754d775e8f9c405194f2b2258d">USB_OTG_GOTGCTL_SRQSCS_Pos</a>)</td></tr>
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<tr class="separator:ga27144da12fabf5f20058022b7a060375"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae09ab672e632dfd87bfb97e10563dfac" id="r_gae09ab672e632dfd87bfb97e10563dfac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae09ab672e632dfd87bfb97e10563dfac">USB_OTG_GOTGCTL_SRQSCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga27144da12fabf5f20058022b7a060375">USB_OTG_GOTGCTL_SRQSCS_Msk</a></td></tr>
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<tr class="memitem:ga46b2b4067f78896b9de20b00d78beae7" id="r_ga46b2b4067f78896b9de20b00d78beae7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46b2b4067f78896b9de20b00d78beae7">USB_OTG_GOTGCTL_SRQ_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga46b2b4067f78896b9de20b00d78beae7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga911bbd5c9dff39b1539db5afda218133" id="r_ga911bbd5c9dff39b1539db5afda218133"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga911bbd5c9dff39b1539db5afda218133">USB_OTG_GOTGCTL_SRQ_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga46b2b4067f78896b9de20b00d78beae7">USB_OTG_GOTGCTL_SRQ_Pos</a>)</td></tr>
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<tr class="separator:ga911bbd5c9dff39b1539db5afda218133"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade39c1039ab30f1ca7ff7c33dd3e1c1b" id="r_gade39c1039ab30f1ca7ff7c33dd3e1c1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gade39c1039ab30f1ca7ff7c33dd3e1c1b">USB_OTG_GOTGCTL_SRQ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga911bbd5c9dff39b1539db5afda218133">USB_OTG_GOTGCTL_SRQ_Msk</a></td></tr>
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<tr class="separator:gade39c1039ab30f1ca7ff7c33dd3e1c1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa11f463747ce5e1444256f11fd57e3bc" id="r_gaa11f463747ce5e1444256f11fd57e3bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa11f463747ce5e1444256f11fd57e3bc">USB_OTG_GOTGCTL_HNGSCS_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaa11f463747ce5e1444256f11fd57e3bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf1172acd99753812214a91f822770fad" id="r_gaf1172acd99753812214a91f822770fad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf1172acd99753812214a91f822770fad">USB_OTG_GOTGCTL_HNGSCS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa11f463747ce5e1444256f11fd57e3bc">USB_OTG_GOTGCTL_HNGSCS_Pos</a>)</td></tr>
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<tr class="separator:gaf1172acd99753812214a91f822770fad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0325825760f66d4792be59cde2a6fb36" id="r_ga0325825760f66d4792be59cde2a6fb36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0325825760f66d4792be59cde2a6fb36">USB_OTG_GOTGCTL_HNGSCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf1172acd99753812214a91f822770fad">USB_OTG_GOTGCTL_HNGSCS_Msk</a></td></tr>
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<tr class="separator:ga0325825760f66d4792be59cde2a6fb36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga500945c12339a4e1350eaa5ca75c2767" id="r_ga500945c12339a4e1350eaa5ca75c2767"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga500945c12339a4e1350eaa5ca75c2767">USB_OTG_GOTGCTL_HNPRQ_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga500945c12339a4e1350eaa5ca75c2767"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga00ce59b4eac11aed163f9b0a40ebd830" id="r_ga00ce59b4eac11aed163f9b0a40ebd830"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga00ce59b4eac11aed163f9b0a40ebd830">USB_OTG_GOTGCTL_HNPRQ_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga500945c12339a4e1350eaa5ca75c2767">USB_OTG_GOTGCTL_HNPRQ_Pos</a>)</td></tr>
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<tr class="separator:ga00ce59b4eac11aed163f9b0a40ebd830"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5db1466d8363575ab2cc8e61855b6d9" id="r_gab5db1466d8363575ab2cc8e61855b6d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5db1466d8363575ab2cc8e61855b6d9">USB_OTG_GOTGCTL_HNPRQ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga00ce59b4eac11aed163f9b0a40ebd830">USB_OTG_GOTGCTL_HNPRQ_Msk</a></td></tr>
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<tr class="separator:gab5db1466d8363575ab2cc8e61855b6d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49a2918e796f1451a374f53af914d19e" id="r_ga49a2918e796f1451a374f53af914d19e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49a2918e796f1451a374f53af914d19e">USB_OTG_GOTGCTL_HSHNPEN_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga49a2918e796f1451a374f53af914d19e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac02604ee9f359f998fac804332d8e82e" id="r_gac02604ee9f359f998fac804332d8e82e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac02604ee9f359f998fac804332d8e82e">USB_OTG_GOTGCTL_HSHNPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga49a2918e796f1451a374f53af914d19e">USB_OTG_GOTGCTL_HSHNPEN_Pos</a>)</td></tr>
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<tr class="separator:gac02604ee9f359f998fac804332d8e82e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62b67d7ea4c4a3d92b031b1dc4e2d014" id="r_ga62b67d7ea4c4a3d92b031b1dc4e2d014"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62b67d7ea4c4a3d92b031b1dc4e2d014">USB_OTG_GOTGCTL_HSHNPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac02604ee9f359f998fac804332d8e82e">USB_OTG_GOTGCTL_HSHNPEN_Msk</a></td></tr>
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<tr class="separator:ga62b67d7ea4c4a3d92b031b1dc4e2d014"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa13365d4746a4b49753d9f4852995063" id="r_gaa13365d4746a4b49753d9f4852995063"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa13365d4746a4b49753d9f4852995063">USB_OTG_GOTGCTL_DHNPEN_Pos</a>   (11U)</td></tr>
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<tr class="separator:gaa13365d4746a4b49753d9f4852995063"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa5c847c2f7db2b4f25a4b807847cf5fd" id="r_gaa5c847c2f7db2b4f25a4b807847cf5fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa5c847c2f7db2b4f25a4b807847cf5fd">USB_OTG_GOTGCTL_DHNPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa13365d4746a4b49753d9f4852995063">USB_OTG_GOTGCTL_DHNPEN_Pos</a>)</td></tr>
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<tr class="separator:gaa5c847c2f7db2b4f25a4b807847cf5fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad29b2224940ad3324855355f4fb52c51" id="r_gad29b2224940ad3324855355f4fb52c51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad29b2224940ad3324855355f4fb52c51">USB_OTG_GOTGCTL_DHNPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa5c847c2f7db2b4f25a4b807847cf5fd">USB_OTG_GOTGCTL_DHNPEN_Msk</a></td></tr>
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<tr class="memitem:ga61f4a444a7765ed3acc31d88e20a145b" id="r_ga61f4a444a7765ed3acc31d88e20a145b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61f4a444a7765ed3acc31d88e20a145b">USB_OTG_GOTGCTL_CIDSTS_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gadcbeabffac3327cd545d469b58baf2f2" id="r_gadcbeabffac3327cd545d469b58baf2f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcbeabffac3327cd545d469b58baf2f2">USB_OTG_GOTGCTL_CIDSTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61f4a444a7765ed3acc31d88e20a145b">USB_OTG_GOTGCTL_CIDSTS_Pos</a>)</td></tr>
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<tr class="separator:gadcbeabffac3327cd545d469b58baf2f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2ab7a1464a20fd128370a41c6b2c5db" id="r_gad2ab7a1464a20fd128370a41c6b2c5db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2ab7a1464a20fd128370a41c6b2c5db">USB_OTG_GOTGCTL_CIDSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadcbeabffac3327cd545d469b58baf2f2">USB_OTG_GOTGCTL_CIDSTS_Msk</a></td></tr>
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<tr class="separator:gad2ab7a1464a20fd128370a41c6b2c5db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada74ca38296ae390167d8d6ef705b79c" id="r_gada74ca38296ae390167d8d6ef705b79c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada74ca38296ae390167d8d6ef705b79c">USB_OTG_GOTGCTL_DBCT_Pos</a>   (17U)</td></tr>
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<tr class="separator:gada74ca38296ae390167d8d6ef705b79c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4cb7bd418b6f7625dd90c36be4a20008" id="r_ga4cb7bd418b6f7625dd90c36be4a20008"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4cb7bd418b6f7625dd90c36be4a20008">USB_OTG_GOTGCTL_DBCT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gada74ca38296ae390167d8d6ef705b79c">USB_OTG_GOTGCTL_DBCT_Pos</a>)</td></tr>
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<tr class="separator:ga4cb7bd418b6f7625dd90c36be4a20008"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac28cd7384fa1d08b1aa518d5d8ed622d" id="r_gac28cd7384fa1d08b1aa518d5d8ed622d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac28cd7384fa1d08b1aa518d5d8ed622d">USB_OTG_GOTGCTL_DBCT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4cb7bd418b6f7625dd90c36be4a20008">USB_OTG_GOTGCTL_DBCT_Msk</a></td></tr>
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<tr class="separator:gac28cd7384fa1d08b1aa518d5d8ed622d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61b0ea0a085b2f7608a51fdb0a842b14" id="r_ga61b0ea0a085b2f7608a51fdb0a842b14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61b0ea0a085b2f7608a51fdb0a842b14">USB_OTG_GOTGCTL_ASVLD_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga61b0ea0a085b2f7608a51fdb0a842b14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga845bbc4c94240d4de22010b542f47ba8" id="r_ga845bbc4c94240d4de22010b542f47ba8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga845bbc4c94240d4de22010b542f47ba8">USB_OTG_GOTGCTL_ASVLD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga61b0ea0a085b2f7608a51fdb0a842b14">USB_OTG_GOTGCTL_ASVLD_Pos</a>)</td></tr>
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<tr class="separator:ga845bbc4c94240d4de22010b542f47ba8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd37f8bf64b304c6e4d053849f56748c" id="r_gafd37f8bf64b304c6e4d053849f56748c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd37f8bf64b304c6e4d053849f56748c">USB_OTG_GOTGCTL_ASVLD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga845bbc4c94240d4de22010b542f47ba8">USB_OTG_GOTGCTL_ASVLD_Msk</a></td></tr>
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<tr class="separator:gafd37f8bf64b304c6e4d053849f56748c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf05b62615285fd77bc354c072b7ba0cd" id="r_gaf05b62615285fd77bc354c072b7ba0cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf05b62615285fd77bc354c072b7ba0cd">USB_OTG_GOTGCTL_BSVLD_Pos</a>   (19U)</td></tr>
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<tr class="memitem:ga4110e90ebb7c55aeb8b429fb5171e378" id="r_ga4110e90ebb7c55aeb8b429fb5171e378"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4110e90ebb7c55aeb8b429fb5171e378">USB_OTG_GOTGCTL_BSVLD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf05b62615285fd77bc354c072b7ba0cd">USB_OTG_GOTGCTL_BSVLD_Pos</a>)</td></tr>
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<tr class="separator:ga4110e90ebb7c55aeb8b429fb5171e378"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacc2ae24138663e92bdca36c8017b6c13" id="r_gacc2ae24138663e92bdca36c8017b6c13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacc2ae24138663e92bdca36c8017b6c13">USB_OTG_GOTGCTL_BSVLD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4110e90ebb7c55aeb8b429fb5171e378">USB_OTG_GOTGCTL_BSVLD_Msk</a></td></tr>
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<tr class="memitem:ga473714ba284e49803fdf522f88151914" id="r_ga473714ba284e49803fdf522f88151914"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga473714ba284e49803fdf522f88151914">USB_OTG_HCFG_FSLSPCS_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga473714ba284e49803fdf522f88151914"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad2eed76dce0ee687f52e08f16bc4c1b" id="r_gaad2eed76dce0ee687f52e08f16bc4c1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad2eed76dce0ee687f52e08f16bc4c1b">USB_OTG_HCFG_FSLSPCS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga473714ba284e49803fdf522f88151914">USB_OTG_HCFG_FSLSPCS_Pos</a>)</td></tr>
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<tr class="separator:gaad2eed76dce0ee687f52e08f16bc4c1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a881de3c707878018490b8b3db282f7" id="r_ga8a881de3c707878018490b8b3db282f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a881de3c707878018490b8b3db282f7">USB_OTG_HCFG_FSLSPCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaad2eed76dce0ee687f52e08f16bc4c1b">USB_OTG_HCFG_FSLSPCS_Msk</a></td></tr>
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<tr class="separator:ga8a881de3c707878018490b8b3db282f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad229aff8e0584e5b5abbf80629e141cc" id="r_gad229aff8e0584e5b5abbf80629e141cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad229aff8e0584e5b5abbf80629e141cc">USB_OTG_HCFG_FSLSPCS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga473714ba284e49803fdf522f88151914">USB_OTG_HCFG_FSLSPCS_Pos</a>)</td></tr>
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<tr class="separator:gad229aff8e0584e5b5abbf80629e141cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga981001cbade2d922b72e1b06d6069da0" id="r_ga981001cbade2d922b72e1b06d6069da0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga981001cbade2d922b72e1b06d6069da0">USB_OTG_HCFG_FSLSPCS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga473714ba284e49803fdf522f88151914">USB_OTG_HCFG_FSLSPCS_Pos</a>)</td></tr>
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<tr class="separator:ga981001cbade2d922b72e1b06d6069da0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab662285d2cc3bfd61c664e572fb69f5e" id="r_gab662285d2cc3bfd61c664e572fb69f5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab662285d2cc3bfd61c664e572fb69f5e">USB_OTG_HCFG_FSLSS_Pos</a>   (2U)</td></tr>
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<tr class="separator:gab662285d2cc3bfd61c664e572fb69f5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebb27b8d77f15f8100c1d27149fb7186" id="r_gaebb27b8d77f15f8100c1d27149fb7186"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebb27b8d77f15f8100c1d27149fb7186">USB_OTG_HCFG_FSLSS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab662285d2cc3bfd61c664e572fb69f5e">USB_OTG_HCFG_FSLSS_Pos</a>)</td></tr>
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<tr class="separator:gaebb27b8d77f15f8100c1d27149fb7186"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98190493ea5b039322c77341e3cf61f8" id="r_ga98190493ea5b039322c77341e3cf61f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98190493ea5b039322c77341e3cf61f8">USB_OTG_HCFG_FSLSS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaebb27b8d77f15f8100c1d27149fb7186">USB_OTG_HCFG_FSLSS_Msk</a></td></tr>
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<tr class="memitem:ga0f814fca4fbed44bc00dc4fd248cba7f" id="r_ga0f814fca4fbed44bc00dc4fd248cba7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f814fca4fbed44bc00dc4fd248cba7f">USB_OTG_DCFG_DSPD_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0f814fca4fbed44bc00dc4fd248cba7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b6bf36ee06f07105efb0568bfb3c06d" id="r_ga0b6bf36ee06f07105efb0568bfb3c06d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b6bf36ee06f07105efb0568bfb3c06d">USB_OTG_DCFG_DSPD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f814fca4fbed44bc00dc4fd248cba7f">USB_OTG_DCFG_DSPD_Pos</a>)</td></tr>
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<tr class="separator:ga0b6bf36ee06f07105efb0568bfb3c06d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f008e2b969946597b56824fef3cc7ef" id="r_ga6f008e2b969946597b56824fef3cc7ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f008e2b969946597b56824fef3cc7ef">USB_OTG_DCFG_DSPD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b6bf36ee06f07105efb0568bfb3c06d">USB_OTG_DCFG_DSPD_Msk</a></td></tr>
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<tr class="separator:ga6f008e2b969946597b56824fef3cc7ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f73c1cb1213fd6e28ce7409fc3c63d1" id="r_ga5f73c1cb1213fd6e28ce7409fc3c63d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f73c1cb1213fd6e28ce7409fc3c63d1">USB_OTG_DCFG_DSPD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f814fca4fbed44bc00dc4fd248cba7f">USB_OTG_DCFG_DSPD_Pos</a>)</td></tr>
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<tr class="separator:ga5f73c1cb1213fd6e28ce7409fc3c63d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7d4f6f3e5002c73be03457ab3ac4023" id="r_gab7d4f6f3e5002c73be03457ab3ac4023"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7d4f6f3e5002c73be03457ab3ac4023">USB_OTG_DCFG_DSPD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f814fca4fbed44bc00dc4fd248cba7f">USB_OTG_DCFG_DSPD_Pos</a>)</td></tr>
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<tr class="separator:gab7d4f6f3e5002c73be03457ab3ac4023"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e34cb67fa67ee5ea04ca8ade51d10e5" id="r_ga7e34cb67fa67ee5ea04ca8ade51d10e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e34cb67fa67ee5ea04ca8ade51d10e5">USB_OTG_DCFG_NZLSOHSK_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga7e34cb67fa67ee5ea04ca8ade51d10e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa785273cbe79b53e609ed2715cfbf98" id="r_gaaa785273cbe79b53e609ed2715cfbf98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa785273cbe79b53e609ed2715cfbf98">USB_OTG_DCFG_NZLSOHSK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e34cb67fa67ee5ea04ca8ade51d10e5">USB_OTG_DCFG_NZLSOHSK_Pos</a>)</td></tr>
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<tr class="separator:gaaa785273cbe79b53e609ed2715cfbf98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c492b6fc8389b58b1879aa7d822137f" id="r_ga7c492b6fc8389b58b1879aa7d822137f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c492b6fc8389b58b1879aa7d822137f">USB_OTG_DCFG_NZLSOHSK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa785273cbe79b53e609ed2715cfbf98">USB_OTG_DCFG_NZLSOHSK_Msk</a></td></tr>
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<tr class="separator:ga7c492b6fc8389b58b1879aa7d822137f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae76878ba65b726eb3baca6db5a9c4397" id="r_gae76878ba65b726eb3baca6db5a9c4397"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae76878ba65b726eb3baca6db5a9c4397">USB_OTG_DCFG_DAD_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae76878ba65b726eb3baca6db5a9c4397"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67fabe86ac6ef650b9ad01a026b67a5d" id="r_ga67fabe86ac6ef650b9ad01a026b67a5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67fabe86ac6ef650b9ad01a026b67a5d">USB_OTG_DCFG_DAD_Msk</a>   (0x7FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae76878ba65b726eb3baca6db5a9c4397">USB_OTG_DCFG_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga67fabe86ac6ef650b9ad01a026b67a5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9fd5819883e2d18cad4c19af8146e1d" id="r_gaf9fd5819883e2d18cad4c19af8146e1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf9fd5819883e2d18cad4c19af8146e1d">USB_OTG_DCFG_DAD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67fabe86ac6ef650b9ad01a026b67a5d">USB_OTG_DCFG_DAD_Msk</a></td></tr>
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<tr class="separator:gaf9fd5819883e2d18cad4c19af8146e1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34aa0076cdeff59113e9880458ae79ba" id="r_ga34aa0076cdeff59113e9880458ae79ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34aa0076cdeff59113e9880458ae79ba">USB_OTG_DCFG_DAD_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae76878ba65b726eb3baca6db5a9c4397">USB_OTG_DCFG_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga34aa0076cdeff59113e9880458ae79ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga646ba21ce25f42e2fbf706295a5ad031" id="r_ga646ba21ce25f42e2fbf706295a5ad031"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga646ba21ce25f42e2fbf706295a5ad031">USB_OTG_DCFG_DAD_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae76878ba65b726eb3baca6db5a9c4397">USB_OTG_DCFG_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga646ba21ce25f42e2fbf706295a5ad031"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d495202852341acc620ce02043281a6" id="r_ga2d495202852341acc620ce02043281a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d495202852341acc620ce02043281a6">USB_OTG_DCFG_DAD_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae76878ba65b726eb3baca6db5a9c4397">USB_OTG_DCFG_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga2d495202852341acc620ce02043281a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1fa407810d17c7f3795fe268bd01120b" id="r_ga1fa407810d17c7f3795fe268bd01120b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fa407810d17c7f3795fe268bd01120b">USB_OTG_DCFG_DAD_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae76878ba65b726eb3baca6db5a9c4397">USB_OTG_DCFG_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga1fa407810d17c7f3795fe268bd01120b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72351ad7cdbbd7992f70892b49a2a669" id="r_ga72351ad7cdbbd7992f70892b49a2a669"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72351ad7cdbbd7992f70892b49a2a669">USB_OTG_DCFG_DAD_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae76878ba65b726eb3baca6db5a9c4397">USB_OTG_DCFG_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga72351ad7cdbbd7992f70892b49a2a669"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61f0d5b909af5196782bbe6e03855f06" id="r_ga61f0d5b909af5196782bbe6e03855f06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61f0d5b909af5196782bbe6e03855f06">USB_OTG_DCFG_DAD_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae76878ba65b726eb3baca6db5a9c4397">USB_OTG_DCFG_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga61f0d5b909af5196782bbe6e03855f06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae949fe90d15c793eb011958a4f600ac" id="r_gaae949fe90d15c793eb011958a4f600ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae949fe90d15c793eb011958a4f600ac">USB_OTG_DCFG_DAD_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae76878ba65b726eb3baca6db5a9c4397">USB_OTG_DCFG_DAD_Pos</a>)</td></tr>
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<tr class="separator:gaae949fe90d15c793eb011958a4f600ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27759af8c6692f16b6fd717fba4c7fd1" id="r_ga27759af8c6692f16b6fd717fba4c7fd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27759af8c6692f16b6fd717fba4c7fd1">USB_OTG_DCFG_PFIVL_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga27759af8c6692f16b6fd717fba4c7fd1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga273b5f0a16f8276d0f0e76f216caa03f" id="r_ga273b5f0a16f8276d0f0e76f216caa03f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga273b5f0a16f8276d0f0e76f216caa03f">USB_OTG_DCFG_PFIVL_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27759af8c6692f16b6fd717fba4c7fd1">USB_OTG_DCFG_PFIVL_Pos</a>)</td></tr>
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<tr class="separator:ga273b5f0a16f8276d0f0e76f216caa03f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08ae423d6325aa35bb037304ba8f8235" id="r_ga08ae423d6325aa35bb037304ba8f8235"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08ae423d6325aa35bb037304ba8f8235">USB_OTG_DCFG_PFIVL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga273b5f0a16f8276d0f0e76f216caa03f">USB_OTG_DCFG_PFIVL_Msk</a></td></tr>
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<tr class="separator:ga08ae423d6325aa35bb037304ba8f8235"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4e78c573f8cd0548bce86ce8593353d" id="r_gaf4e78c573f8cd0548bce86ce8593353d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4e78c573f8cd0548bce86ce8593353d">USB_OTG_DCFG_PFIVL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27759af8c6692f16b6fd717fba4c7fd1">USB_OTG_DCFG_PFIVL_Pos</a>)</td></tr>
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<tr class="separator:gaf4e78c573f8cd0548bce86ce8593353d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9cc973db831fb86b1e122443a58aa7c" id="r_gab9cc973db831fb86b1e122443a58aa7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9cc973db831fb86b1e122443a58aa7c">USB_OTG_DCFG_PFIVL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27759af8c6692f16b6fd717fba4c7fd1">USB_OTG_DCFG_PFIVL_Pos</a>)</td></tr>
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<tr class="separator:gab9cc973db831fb86b1e122443a58aa7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad13016a80c9fcb7f2219d7d6c5a15420" id="r_gad13016a80c9fcb7f2219d7d6c5a15420"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad13016a80c9fcb7f2219d7d6c5a15420">USB_OTG_DCFG_XCVRDLY_Pos</a>   (14U)</td></tr>
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<tr class="separator:gad13016a80c9fcb7f2219d7d6c5a15420"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9a4c6ac40e44ccfe90a65c583c202b2" id="r_gac9a4c6ac40e44ccfe90a65c583c202b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9a4c6ac40e44ccfe90a65c583c202b2">USB_OTG_DCFG_XCVRDLY_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad13016a80c9fcb7f2219d7d6c5a15420">USB_OTG_DCFG_XCVRDLY_Pos</a>)</td></tr>
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<tr class="separator:gac9a4c6ac40e44ccfe90a65c583c202b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fbc004fabda6fa9cda2977d45755e42" id="r_ga0fbc004fabda6fa9cda2977d45755e42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fbc004fabda6fa9cda2977d45755e42">USB_OTG_DCFG_XCVRDLY</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac9a4c6ac40e44ccfe90a65c583c202b2">USB_OTG_DCFG_XCVRDLY_Msk</a></td></tr>
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<tr class="separator:ga0fbc004fabda6fa9cda2977d45755e42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6e3c2d9632a9ab98fae27f4e1de639c" id="r_gaa6e3c2d9632a9ab98fae27f4e1de639c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e3c2d9632a9ab98fae27f4e1de639c">USB_OTG_DCFG_ERRATIM_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaa6e3c2d9632a9ab98fae27f4e1de639c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd12755447b5773fd5db5b71b5ea292a" id="r_gacd12755447b5773fd5db5b71b5ea292a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd12755447b5773fd5db5b71b5ea292a">USB_OTG_DCFG_ERRATIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6e3c2d9632a9ab98fae27f4e1de639c">USB_OTG_DCFG_ERRATIM_Pos</a>)</td></tr>
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<tr class="separator:gacd12755447b5773fd5db5b71b5ea292a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36b7cce75bb4e60fe38760c78167b2ac" id="r_ga36b7cce75bb4e60fe38760c78167b2ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36b7cce75bb4e60fe38760c78167b2ac">USB_OTG_DCFG_ERRATIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacd12755447b5773fd5db5b71b5ea292a">USB_OTG_DCFG_ERRATIM_Msk</a></td></tr>
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<tr class="separator:ga36b7cce75bb4e60fe38760c78167b2ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad22746397a7c2cfeba819d38a172c212" id="r_gad22746397a7c2cfeba819d38a172c212"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad22746397a7c2cfeba819d38a172c212">USB_OTG_DCFG_PERSCHIVL_Pos</a>   (24U)</td></tr>
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<tr class="separator:gad22746397a7c2cfeba819d38a172c212"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4407194cfda70b7408523c537ba03060" id="r_ga4407194cfda70b7408523c537ba03060"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4407194cfda70b7408523c537ba03060">USB_OTG_DCFG_PERSCHIVL_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad22746397a7c2cfeba819d38a172c212">USB_OTG_DCFG_PERSCHIVL_Pos</a>)</td></tr>
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<tr class="separator:ga4407194cfda70b7408523c537ba03060"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fb78d02bad573871d6b9d92100561a4" id="r_ga8fb78d02bad573871d6b9d92100561a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fb78d02bad573871d6b9d92100561a4">USB_OTG_DCFG_PERSCHIVL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4407194cfda70b7408523c537ba03060">USB_OTG_DCFG_PERSCHIVL_Msk</a></td></tr>
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<tr class="separator:ga8fb78d02bad573871d6b9d92100561a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4eef8bf8e73d8b94b0caf98caa978c11" id="r_ga4eef8bf8e73d8b94b0caf98caa978c11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4eef8bf8e73d8b94b0caf98caa978c11">USB_OTG_DCFG_PERSCHIVL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad22746397a7c2cfeba819d38a172c212">USB_OTG_DCFG_PERSCHIVL_Pos</a>)</td></tr>
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<tr class="separator:ga4eef8bf8e73d8b94b0caf98caa978c11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e47455432a6c8c7c7400024427c25d8" id="r_ga4e47455432a6c8c7c7400024427c25d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e47455432a6c8c7c7400024427c25d8">USB_OTG_DCFG_PERSCHIVL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad22746397a7c2cfeba819d38a172c212">USB_OTG_DCFG_PERSCHIVL_Pos</a>)</td></tr>
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<tr class="separator:ga4e47455432a6c8c7c7400024427c25d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b40c8b9e9f41a6d908e918591093dea" id="r_ga3b40c8b9e9f41a6d908e918591093dea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b40c8b9e9f41a6d908e918591093dea">USB_OTG_PCGCR_STPPCLK_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3b40c8b9e9f41a6d908e918591093dea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f118ddd4551c474f8edc23058876fdf" id="r_ga7f118ddd4551c474f8edc23058876fdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f118ddd4551c474f8edc23058876fdf">USB_OTG_PCGCR_STPPCLK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b40c8b9e9f41a6d908e918591093dea">USB_OTG_PCGCR_STPPCLK_Pos</a>)</td></tr>
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<tr class="separator:ga7f118ddd4551c474f8edc23058876fdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac696153ff9f165deadff3fe0225849e8" id="r_gac696153ff9f165deadff3fe0225849e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac696153ff9f165deadff3fe0225849e8">USB_OTG_PCGCR_STPPCLK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f118ddd4551c474f8edc23058876fdf">USB_OTG_PCGCR_STPPCLK_Msk</a></td></tr>
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<tr class="separator:gac696153ff9f165deadff3fe0225849e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf87ca67c6646747e2fbea26cda8890b5" id="r_gaf87ca67c6646747e2fbea26cda8890b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf87ca67c6646747e2fbea26cda8890b5">USB_OTG_PCGCR_GATEHCLK_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaf87ca67c6646747e2fbea26cda8890b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14c302139df9ab546ce190277ecbc090" id="r_ga14c302139df9ab546ce190277ecbc090"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14c302139df9ab546ce190277ecbc090">USB_OTG_PCGCR_GATEHCLK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf87ca67c6646747e2fbea26cda8890b5">USB_OTG_PCGCR_GATEHCLK_Pos</a>)</td></tr>
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<tr class="separator:ga14c302139df9ab546ce190277ecbc090"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d6bcb65b4cb112d17466cf24c42e37f" id="r_ga6d6bcb65b4cb112d17466cf24c42e37f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d6bcb65b4cb112d17466cf24c42e37f">USB_OTG_PCGCR_GATEHCLK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga14c302139df9ab546ce190277ecbc090">USB_OTG_PCGCR_GATEHCLK_Msk</a></td></tr>
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<tr class="separator:ga6d6bcb65b4cb112d17466cf24c42e37f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d0ac8d8fabee0eea8a1711ea7fafe02" id="r_ga0d0ac8d8fabee0eea8a1711ea7fafe02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d0ac8d8fabee0eea8a1711ea7fafe02">USB_OTG_PCGCR_PHYSUSP_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga0d0ac8d8fabee0eea8a1711ea7fafe02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bd9eee61333c5bd9565e74be8daacb2" id="r_ga6bd9eee61333c5bd9565e74be8daacb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6bd9eee61333c5bd9565e74be8daacb2">USB_OTG_PCGCR_PHYSUSP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d0ac8d8fabee0eea8a1711ea7fafe02">USB_OTG_PCGCR_PHYSUSP_Pos</a>)</td></tr>
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<tr class="separator:ga6bd9eee61333c5bd9565e74be8daacb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b8c8a29c623fc354c03942a6a414c06" id="r_ga0b8c8a29c623fc354c03942a6a414c06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b8c8a29c623fc354c03942a6a414c06">USB_OTG_PCGCR_PHYSUSP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6bd9eee61333c5bd9565e74be8daacb2">USB_OTG_PCGCR_PHYSUSP_Msk</a></td></tr>
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<tr class="separator:ga0b8c8a29c623fc354c03942a6a414c06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7880e1cd896eb997da0931d7ec2382bd" id="r_ga7880e1cd896eb997da0931d7ec2382bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7880e1cd896eb997da0931d7ec2382bd">USB_OTG_GOTGINT_SEDET_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga7880e1cd896eb997da0931d7ec2382bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa244dfb48bb953763802745e978649b2" id="r_gaa244dfb48bb953763802745e978649b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa244dfb48bb953763802745e978649b2">USB_OTG_GOTGINT_SEDET_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7880e1cd896eb997da0931d7ec2382bd">USB_OTG_GOTGINT_SEDET_Pos</a>)</td></tr>
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<tr class="separator:gaa244dfb48bb953763802745e978649b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46e79a60810179da2479104fbf514a70" id="r_ga46e79a60810179da2479104fbf514a70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46e79a60810179da2479104fbf514a70">USB_OTG_GOTGINT_SEDET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa244dfb48bb953763802745e978649b2">USB_OTG_GOTGINT_SEDET_Msk</a></td></tr>
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<tr class="separator:ga46e79a60810179da2479104fbf514a70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9485401fa0f22f9eece9f372d8189343" id="r_ga9485401fa0f22f9eece9f372d8189343"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9485401fa0f22f9eece9f372d8189343">USB_OTG_GOTGINT_SRSSCHG_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga9485401fa0f22f9eece9f372d8189343"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga750e5c8cbb573197c89318c8b99771e0" id="r_ga750e5c8cbb573197c89318c8b99771e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga750e5c8cbb573197c89318c8b99771e0">USB_OTG_GOTGINT_SRSSCHG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9485401fa0f22f9eece9f372d8189343">USB_OTG_GOTGINT_SRSSCHG_Pos</a>)</td></tr>
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<tr class="separator:ga750e5c8cbb573197c89318c8b99771e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7c5094462de3569f89fdcc641ead7d47" id="r_ga7c5094462de3569f89fdcc641ead7d47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c5094462de3569f89fdcc641ead7d47">USB_OTG_GOTGINT_SRSSCHG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga750e5c8cbb573197c89318c8b99771e0">USB_OTG_GOTGINT_SRSSCHG_Msk</a></td></tr>
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<tr class="separator:ga7c5094462de3569f89fdcc641ead7d47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga747d0bf0c6cd7caaaa24b7263689b6f7" id="r_ga747d0bf0c6cd7caaaa24b7263689b6f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga747d0bf0c6cd7caaaa24b7263689b6f7">USB_OTG_GOTGINT_HNSSCHG_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga747d0bf0c6cd7caaaa24b7263689b6f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83eeecbc4aa4d8bc1c1c6cac82695577" id="r_ga83eeecbc4aa4d8bc1c1c6cac82695577"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83eeecbc4aa4d8bc1c1c6cac82695577">USB_OTG_GOTGINT_HNSSCHG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga747d0bf0c6cd7caaaa24b7263689b6f7">USB_OTG_GOTGINT_HNSSCHG_Pos</a>)</td></tr>
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<tr class="separator:ga83eeecbc4aa4d8bc1c1c6cac82695577"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50fcdec0f5ff7e594b726dc63175a1f3" id="r_ga50fcdec0f5ff7e594b726dc63175a1f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50fcdec0f5ff7e594b726dc63175a1f3">USB_OTG_GOTGINT_HNSSCHG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga83eeecbc4aa4d8bc1c1c6cac82695577">USB_OTG_GOTGINT_HNSSCHG_Msk</a></td></tr>
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<tr class="separator:ga50fcdec0f5ff7e594b726dc63175a1f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad417dfa3c157c52bd339c8a832017bcd" id="r_gad417dfa3c157c52bd339c8a832017bcd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad417dfa3c157c52bd339c8a832017bcd">USB_OTG_GOTGINT_HNGDET_Pos</a>   (17U)</td></tr>
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<tr class="separator:gad417dfa3c157c52bd339c8a832017bcd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c87ba48d57c205ce011dfa8b6888a9f" id="r_ga1c87ba48d57c205ce011dfa8b6888a9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c87ba48d57c205ce011dfa8b6888a9f">USB_OTG_GOTGINT_HNGDET_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad417dfa3c157c52bd339c8a832017bcd">USB_OTG_GOTGINT_HNGDET_Pos</a>)</td></tr>
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<tr class="separator:ga1c87ba48d57c205ce011dfa8b6888a9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab16a656720e4914c0935ef597f9719ef" id="r_gab16a656720e4914c0935ef597f9719ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab16a656720e4914c0935ef597f9719ef">USB_OTG_GOTGINT_HNGDET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1c87ba48d57c205ce011dfa8b6888a9f">USB_OTG_GOTGINT_HNGDET_Msk</a></td></tr>
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<tr class="separator:gab16a656720e4914c0935ef597f9719ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae10eaf27601d24b1501f70242905fee9" id="r_gae10eaf27601d24b1501f70242905fee9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae10eaf27601d24b1501f70242905fee9">USB_OTG_GOTGINT_ADTOCHG_Pos</a>   (18U)</td></tr>
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<tr class="separator:gae10eaf27601d24b1501f70242905fee9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e2f3eeb46b9addf20afbc0f4e0c3196" id="r_ga6e2f3eeb46b9addf20afbc0f4e0c3196"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e2f3eeb46b9addf20afbc0f4e0c3196">USB_OTG_GOTGINT_ADTOCHG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae10eaf27601d24b1501f70242905fee9">USB_OTG_GOTGINT_ADTOCHG_Pos</a>)</td></tr>
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<tr class="separator:ga6e2f3eeb46b9addf20afbc0f4e0c3196"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac73e4e50f0fbe8376e87b833872f4b40" id="r_gac73e4e50f0fbe8376e87b833872f4b40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac73e4e50f0fbe8376e87b833872f4b40">USB_OTG_GOTGINT_ADTOCHG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e2f3eeb46b9addf20afbc0f4e0c3196">USB_OTG_GOTGINT_ADTOCHG_Msk</a></td></tr>
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<tr class="separator:gac73e4e50f0fbe8376e87b833872f4b40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d9e656b9e43f0959f16a86b21aef45e" id="r_ga1d9e656b9e43f0959f16a86b21aef45e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d9e656b9e43f0959f16a86b21aef45e">USB_OTG_GOTGINT_DBCDNE_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga1d9e656b9e43f0959f16a86b21aef45e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e2ad3f6e96de9fbe88f1e5f6d3be7d4" id="r_ga9e2ad3f6e96de9fbe88f1e5f6d3be7d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e2ad3f6e96de9fbe88f1e5f6d3be7d4">USB_OTG_GOTGINT_DBCDNE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d9e656b9e43f0959f16a86b21aef45e">USB_OTG_GOTGINT_DBCDNE_Pos</a>)</td></tr>
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<tr class="separator:ga9e2ad3f6e96de9fbe88f1e5f6d3be7d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa17e41c826fded604c1837cacae0b66" id="r_gafa17e41c826fded604c1837cacae0b66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa17e41c826fded604c1837cacae0b66">USB_OTG_GOTGINT_DBCDNE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9e2ad3f6e96de9fbe88f1e5f6d3be7d4">USB_OTG_GOTGINT_DBCDNE_Msk</a></td></tr>
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<tr class="separator:gafa17e41c826fded604c1837cacae0b66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c2fa606dfe64d8839dbfd7cb059eb1f" id="r_ga4c2fa606dfe64d8839dbfd7cb059eb1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c2fa606dfe64d8839dbfd7cb059eb1f">USB_OTG_DCTL_RWUSIG_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4c2fa606dfe64d8839dbfd7cb059eb1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6caa072b60a7c1c580d47f5ac1d4a63d" id="r_ga6caa072b60a7c1c580d47f5ac1d4a63d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6caa072b60a7c1c580d47f5ac1d4a63d">USB_OTG_DCTL_RWUSIG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c2fa606dfe64d8839dbfd7cb059eb1f">USB_OTG_DCTL_RWUSIG_Pos</a>)</td></tr>
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<tr class="separator:ga6caa072b60a7c1c580d47f5ac1d4a63d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e87febbcda52c3b0b4679ce4fc10aae" id="r_ga8e87febbcda52c3b0b4679ce4fc10aae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e87febbcda52c3b0b4679ce4fc10aae">USB_OTG_DCTL_RWUSIG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6caa072b60a7c1c580d47f5ac1d4a63d">USB_OTG_DCTL_RWUSIG_Msk</a></td></tr>
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<tr class="separator:ga8e87febbcda52c3b0b4679ce4fc10aae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebac09e13aa5eb753c567253f7a7be17" id="r_gaebac09e13aa5eb753c567253f7a7be17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebac09e13aa5eb753c567253f7a7be17">USB_OTG_DCTL_SDIS_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaebac09e13aa5eb753c567253f7a7be17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34f43895b41cdf03141fd07278679e9c" id="r_ga34f43895b41cdf03141fd07278679e9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34f43895b41cdf03141fd07278679e9c">USB_OTG_DCTL_SDIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaebac09e13aa5eb753c567253f7a7be17">USB_OTG_DCTL_SDIS_Pos</a>)</td></tr>
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<tr class="separator:ga34f43895b41cdf03141fd07278679e9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga148c9f1be1abbca2c8568a079894c9d0" id="r_ga148c9f1be1abbca2c8568a079894c9d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga148c9f1be1abbca2c8568a079894c9d0">USB_OTG_DCTL_SDIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34f43895b41cdf03141fd07278679e9c">USB_OTG_DCTL_SDIS_Msk</a></td></tr>
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<tr class="separator:ga148c9f1be1abbca2c8568a079894c9d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b3fab019e98600e57b4416eff4b0c6c" id="r_ga5b3fab019e98600e57b4416eff4b0c6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b3fab019e98600e57b4416eff4b0c6c">USB_OTG_DCTL_GINSTS_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga5b3fab019e98600e57b4416eff4b0c6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf928315cb36f5a39a14f58cb15468ec8" id="r_gaf928315cb36f5a39a14f58cb15468ec8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf928315cb36f5a39a14f58cb15468ec8">USB_OTG_DCTL_GINSTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b3fab019e98600e57b4416eff4b0c6c">USB_OTG_DCTL_GINSTS_Pos</a>)</td></tr>
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<tr class="separator:gaf928315cb36f5a39a14f58cb15468ec8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d3d6c5c6827fad61f6f8fa5553935fa" id="r_ga6d3d6c5c6827fad61f6f8fa5553935fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d3d6c5c6827fad61f6f8fa5553935fa">USB_OTG_DCTL_GINSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf928315cb36f5a39a14f58cb15468ec8">USB_OTG_DCTL_GINSTS_Msk</a></td></tr>
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<tr class="separator:ga6d3d6c5c6827fad61f6f8fa5553935fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62e7c5f4b5a7e317f9691805596a54cb" id="r_ga62e7c5f4b5a7e317f9691805596a54cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62e7c5f4b5a7e317f9691805596a54cb">USB_OTG_DCTL_GONSTS_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga62e7c5f4b5a7e317f9691805596a54cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa880c9c7c5ee16534e0156380cf04d28" id="r_gaa880c9c7c5ee16534e0156380cf04d28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa880c9c7c5ee16534e0156380cf04d28">USB_OTG_DCTL_GONSTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga62e7c5f4b5a7e317f9691805596a54cb">USB_OTG_DCTL_GONSTS_Pos</a>)</td></tr>
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<tr class="memitem:ga199625403480a432df8f653b9bee0bd4" id="r_ga199625403480a432df8f653b9bee0bd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga199625403480a432df8f653b9bee0bd4">USB_OTG_DCTL_GONSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa880c9c7c5ee16534e0156380cf04d28">USB_OTG_DCTL_GONSTS_Msk</a></td></tr>
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<tr class="separator:ga199625403480a432df8f653b9bee0bd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2949c49bf972e4db35cd85649ccb3c6" id="r_gaf2949c49bf972e4db35cd85649ccb3c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2949c49bf972e4db35cd85649ccb3c6">USB_OTG_DCTL_TCTL_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaf2949c49bf972e4db35cd85649ccb3c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad771cd9b6f19e1f335016426d41dec48" id="r_gad771cd9b6f19e1f335016426d41dec48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad771cd9b6f19e1f335016426d41dec48">USB_OTG_DCTL_TCTL_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2949c49bf972e4db35cd85649ccb3c6">USB_OTG_DCTL_TCTL_Pos</a>)</td></tr>
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<tr class="separator:gad771cd9b6f19e1f335016426d41dec48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaebcf7c6c98c93f075f635cf0969c16f4" id="r_gaebcf7c6c98c93f075f635cf0969c16f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaebcf7c6c98c93f075f635cf0969c16f4">USB_OTG_DCTL_TCTL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad771cd9b6f19e1f335016426d41dec48">USB_OTG_DCTL_TCTL_Msk</a></td></tr>
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<tr class="separator:gaebcf7c6c98c93f075f635cf0969c16f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48750394a0e7d020b3b1e4c4b73b981f" id="r_ga48750394a0e7d020b3b1e4c4b73b981f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48750394a0e7d020b3b1e4c4b73b981f">USB_OTG_DCTL_TCTL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2949c49bf972e4db35cd85649ccb3c6">USB_OTG_DCTL_TCTL_Pos</a>)</td></tr>
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<tr class="separator:ga48750394a0e7d020b3b1e4c4b73b981f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27636cb092fce5a35e0dd25debc50294" id="r_ga27636cb092fce5a35e0dd25debc50294"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27636cb092fce5a35e0dd25debc50294">USB_OTG_DCTL_TCTL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2949c49bf972e4db35cd85649ccb3c6">USB_OTG_DCTL_TCTL_Pos</a>)</td></tr>
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<tr class="separator:ga27636cb092fce5a35e0dd25debc50294"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82ad49a50f4cb5a7c310e94d92daa889" id="r_ga82ad49a50f4cb5a7c310e94d92daa889"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82ad49a50f4cb5a7c310e94d92daa889">USB_OTG_DCTL_TCTL_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2949c49bf972e4db35cd85649ccb3c6">USB_OTG_DCTL_TCTL_Pos</a>)</td></tr>
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<tr class="separator:ga82ad49a50f4cb5a7c310e94d92daa889"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a6d0efe73a56eb7e63594717cd3784e" id="r_ga3a6d0efe73a56eb7e63594717cd3784e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a6d0efe73a56eb7e63594717cd3784e">USB_OTG_DCTL_SGINAK_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga3a6d0efe73a56eb7e63594717cd3784e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa822717fd13eed433f8496f8c0b81482" id="r_gaa822717fd13eed433f8496f8c0b81482"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa822717fd13eed433f8496f8c0b81482">USB_OTG_DCTL_SGINAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a6d0efe73a56eb7e63594717cd3784e">USB_OTG_DCTL_SGINAK_Pos</a>)</td></tr>
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<tr class="separator:gaa822717fd13eed433f8496f8c0b81482"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafde278c400411575329026a0a8a67fa0" id="r_gafde278c400411575329026a0a8a67fa0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafde278c400411575329026a0a8a67fa0">USB_OTG_DCTL_SGINAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa822717fd13eed433f8496f8c0b81482">USB_OTG_DCTL_SGINAK_Msk</a></td></tr>
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<tr class="separator:gafde278c400411575329026a0a8a67fa0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2110acce46d292ea06baa8816332b516" id="r_ga2110acce46d292ea06baa8816332b516"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2110acce46d292ea06baa8816332b516">USB_OTG_DCTL_CGINAK_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga2110acce46d292ea06baa8816332b516"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45fb8854f9cb1d9e5aa9b55e4392af8b" id="r_ga45fb8854f9cb1d9e5aa9b55e4392af8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45fb8854f9cb1d9e5aa9b55e4392af8b">USB_OTG_DCTL_CGINAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2110acce46d292ea06baa8816332b516">USB_OTG_DCTL_CGINAK_Pos</a>)</td></tr>
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<tr class="separator:ga45fb8854f9cb1d9e5aa9b55e4392af8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga200f87e323c35612737fbaeb7b1c52f2" id="r_ga200f87e323c35612737fbaeb7b1c52f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga200f87e323c35612737fbaeb7b1c52f2">USB_OTG_DCTL_CGINAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga45fb8854f9cb1d9e5aa9b55e4392af8b">USB_OTG_DCTL_CGINAK_Msk</a></td></tr>
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<tr class="separator:ga200f87e323c35612737fbaeb7b1c52f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7701014b6f5ba7a52bd48e8c8a1d1821" id="r_ga7701014b6f5ba7a52bd48e8c8a1d1821"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7701014b6f5ba7a52bd48e8c8a1d1821">USB_OTG_DCTL_SGONAK_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga7701014b6f5ba7a52bd48e8c8a1d1821"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga54678325db99694db585d8ec50f46ae6" id="r_ga54678325db99694db585d8ec50f46ae6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga54678325db99694db585d8ec50f46ae6">USB_OTG_DCTL_SGONAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7701014b6f5ba7a52bd48e8c8a1d1821">USB_OTG_DCTL_SGONAK_Pos</a>)</td></tr>
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<tr class="separator:ga54678325db99694db585d8ec50f46ae6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga717ea6d52263b0b9938ebf1f3ef4b409" id="r_ga717ea6d52263b0b9938ebf1f3ef4b409"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga717ea6d52263b0b9938ebf1f3ef4b409">USB_OTG_DCTL_SGONAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga54678325db99694db585d8ec50f46ae6">USB_OTG_DCTL_SGONAK_Msk</a></td></tr>
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<tr class="separator:ga717ea6d52263b0b9938ebf1f3ef4b409"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57d32c2416c40902c1095f2e3e84c2c1" id="r_ga57d32c2416c40902c1095f2e3e84c2c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57d32c2416c40902c1095f2e3e84c2c1">USB_OTG_DCTL_CGONAK_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga57d32c2416c40902c1095f2e3e84c2c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07b9fd237b82bf4b3556a7a344a0058c" id="r_ga07b9fd237b82bf4b3556a7a344a0058c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07b9fd237b82bf4b3556a7a344a0058c">USB_OTG_DCTL_CGONAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga57d32c2416c40902c1095f2e3e84c2c1">USB_OTG_DCTL_CGONAK_Pos</a>)</td></tr>
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<tr class="separator:ga07b9fd237b82bf4b3556a7a344a0058c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga232f28bae3c9cd354b2fca1be518d043" id="r_ga232f28bae3c9cd354b2fca1be518d043"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga232f28bae3c9cd354b2fca1be518d043">USB_OTG_DCTL_CGONAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga07b9fd237b82bf4b3556a7a344a0058c">USB_OTG_DCTL_CGONAK_Msk</a></td></tr>
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<tr class="separator:ga232f28bae3c9cd354b2fca1be518d043"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga607c004ead13d867f5712fc7c46d335d" id="r_ga607c004ead13d867f5712fc7c46d335d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga607c004ead13d867f5712fc7c46d335d">USB_OTG_DCTL_POPRGDNE_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga607c004ead13d867f5712fc7c46d335d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2daaa82f3b3ea2bbfb3c0677c46b93b" id="r_gac2daaa82f3b3ea2bbfb3c0677c46b93b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2daaa82f3b3ea2bbfb3c0677c46b93b">USB_OTG_DCTL_POPRGDNE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga607c004ead13d867f5712fc7c46d335d">USB_OTG_DCTL_POPRGDNE_Pos</a>)</td></tr>
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<tr class="separator:gac2daaa82f3b3ea2bbfb3c0677c46b93b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace837326945cc056aef6969fc24e1a09" id="r_gace837326945cc056aef6969fc24e1a09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace837326945cc056aef6969fc24e1a09">USB_OTG_DCTL_POPRGDNE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac2daaa82f3b3ea2bbfb3c0677c46b93b">USB_OTG_DCTL_POPRGDNE_Msk</a></td></tr>
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<tr class="separator:gace837326945cc056aef6969fc24e1a09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97444625f6ff4b49606dc6f571bc66ff" id="r_ga97444625f6ff4b49606dc6f571bc66ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga97444625f6ff4b49606dc6f571bc66ff">USB_OTG_HFIR_FRIVL_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga97444625f6ff4b49606dc6f571bc66ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadcdb6f745b118b51a607d89bbf864a0" id="r_gaadcdb6f745b118b51a607d89bbf864a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadcdb6f745b118b51a607d89bbf864a0">USB_OTG_HFIR_FRIVL_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga97444625f6ff4b49606dc6f571bc66ff">USB_OTG_HFIR_FRIVL_Pos</a>)</td></tr>
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<tr class="separator:gaadcdb6f745b118b51a607d89bbf864a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8345933ec4180c4ea9013291ce085a2d" id="r_ga8345933ec4180c4ea9013291ce085a2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8345933ec4180c4ea9013291ce085a2d">USB_OTG_HFIR_FRIVL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaadcdb6f745b118b51a607d89bbf864a0">USB_OTG_HFIR_FRIVL_Msk</a></td></tr>
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<tr class="separator:ga8345933ec4180c4ea9013291ce085a2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d39ecc57d3e50e398dcca940eaf4a17" id="r_ga0d39ecc57d3e50e398dcca940eaf4a17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d39ecc57d3e50e398dcca940eaf4a17">USB_OTG_HFNUM_FRNUM_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0d39ecc57d3e50e398dcca940eaf4a17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34a555bd57d9e8f2a41d5b9499ad7c44" id="r_ga34a555bd57d9e8f2a41d5b9499ad7c44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34a555bd57d9e8f2a41d5b9499ad7c44">USB_OTG_HFNUM_FRNUM_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d39ecc57d3e50e398dcca940eaf4a17">USB_OTG_HFNUM_FRNUM_Pos</a>)</td></tr>
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<tr class="separator:ga34a555bd57d9e8f2a41d5b9499ad7c44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab240bcea196fe42725639b82a3ceac75" id="r_gab240bcea196fe42725639b82a3ceac75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab240bcea196fe42725639b82a3ceac75">USB_OTG_HFNUM_FRNUM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34a555bd57d9e8f2a41d5b9499ad7c44">USB_OTG_HFNUM_FRNUM_Msk</a></td></tr>
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<tr class="separator:gab240bcea196fe42725639b82a3ceac75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3bc7db92586a96e7a4c3cebb97644a5" id="r_gae3bc7db92586a96e7a4c3cebb97644a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3bc7db92586a96e7a4c3cebb97644a5">USB_OTG_HFNUM_FTREM_Pos</a>   (16U)</td></tr>
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<tr class="separator:gae3bc7db92586a96e7a4c3cebb97644a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad58aef8796a09f03191b07f54244b67f" id="r_gad58aef8796a09f03191b07f54244b67f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad58aef8796a09f03191b07f54244b67f">USB_OTG_HFNUM_FTREM_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3bc7db92586a96e7a4c3cebb97644a5">USB_OTG_HFNUM_FTREM_Pos</a>)</td></tr>
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<tr class="separator:gad58aef8796a09f03191b07f54244b67f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51a24f44589040844690a0d6d2f23c13" id="r_ga51a24f44589040844690a0d6d2f23c13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51a24f44589040844690a0d6d2f23c13">USB_OTG_HFNUM_FTREM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad58aef8796a09f03191b07f54244b67f">USB_OTG_HFNUM_FTREM_Msk</a></td></tr>
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<tr class="separator:ga51a24f44589040844690a0d6d2f23c13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2c34163004ae2c55ba72739f5accd8d" id="r_gac2c34163004ae2c55ba72739f5accd8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2c34163004ae2c55ba72739f5accd8d">USB_OTG_DSTS_SUSPSTS_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac2c34163004ae2c55ba72739f5accd8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga474e845231f3f8f1de1d4be1e99167ca" id="r_ga474e845231f3f8f1de1d4be1e99167ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga474e845231f3f8f1de1d4be1e99167ca">USB_OTG_DSTS_SUSPSTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac2c34163004ae2c55ba72739f5accd8d">USB_OTG_DSTS_SUSPSTS_Pos</a>)</td></tr>
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<tr class="separator:ga474e845231f3f8f1de1d4be1e99167ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8faf1dcd3fb686cc4acf23ca6f4b71ec" id="r_ga8faf1dcd3fb686cc4acf23ca6f4b71ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8faf1dcd3fb686cc4acf23ca6f4b71ec">USB_OTG_DSTS_SUSPSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga474e845231f3f8f1de1d4be1e99167ca">USB_OTG_DSTS_SUSPSTS_Msk</a></td></tr>
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<tr class="separator:ga8faf1dcd3fb686cc4acf23ca6f4b71ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86eea0eb8d965de29d5e33c0996001eb" id="r_ga86eea0eb8d965de29d5e33c0996001eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86eea0eb8d965de29d5e33c0996001eb">USB_OTG_DSTS_ENUMSPD_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga86eea0eb8d965de29d5e33c0996001eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga270bfa6f7139f8a15af6a55c4b48c167" id="r_ga270bfa6f7139f8a15af6a55c4b48c167"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga270bfa6f7139f8a15af6a55c4b48c167">USB_OTG_DSTS_ENUMSPD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga86eea0eb8d965de29d5e33c0996001eb">USB_OTG_DSTS_ENUMSPD_Pos</a>)</td></tr>
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<tr class="separator:ga270bfa6f7139f8a15af6a55c4b48c167"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf68e749d3365b8b6aba2002718a16e94" id="r_gaf68e749d3365b8b6aba2002718a16e94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf68e749d3365b8b6aba2002718a16e94">USB_OTG_DSTS_ENUMSPD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga270bfa6f7139f8a15af6a55c4b48c167">USB_OTG_DSTS_ENUMSPD_Msk</a></td></tr>
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<tr class="separator:gaf68e749d3365b8b6aba2002718a16e94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b85a30093b2120bd2f0dca9a2fabd46" id="r_ga4b85a30093b2120bd2f0dca9a2fabd46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b85a30093b2120bd2f0dca9a2fabd46">USB_OTG_DSTS_ENUMSPD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga86eea0eb8d965de29d5e33c0996001eb">USB_OTG_DSTS_ENUMSPD_Pos</a>)</td></tr>
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<tr class="separator:ga4b85a30093b2120bd2f0dca9a2fabd46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38dcfba81d842a0514d24f42fbea815c" id="r_ga38dcfba81d842a0514d24f42fbea815c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga38dcfba81d842a0514d24f42fbea815c">USB_OTG_DSTS_ENUMSPD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga86eea0eb8d965de29d5e33c0996001eb">USB_OTG_DSTS_ENUMSPD_Pos</a>)</td></tr>
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<tr class="separator:ga38dcfba81d842a0514d24f42fbea815c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f6d51148141137f5b622379f7966cca" id="r_ga7f6d51148141137f5b622379f7966cca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f6d51148141137f5b622379f7966cca">USB_OTG_DSTS_EERR_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga7f6d51148141137f5b622379f7966cca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3125d311d52b88b33109ffd3b1c2b194" id="r_ga3125d311d52b88b33109ffd3b1c2b194"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3125d311d52b88b33109ffd3b1c2b194">USB_OTG_DSTS_EERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f6d51148141137f5b622379f7966cca">USB_OTG_DSTS_EERR_Pos</a>)</td></tr>
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<tr class="separator:ga3125d311d52b88b33109ffd3b1c2b194"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9787add94a212edfffa82dd2fe47863" id="r_gab9787add94a212edfffa82dd2fe47863"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9787add94a212edfffa82dd2fe47863">USB_OTG_DSTS_EERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3125d311d52b88b33109ffd3b1c2b194">USB_OTG_DSTS_EERR_Msk</a></td></tr>
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<tr class="separator:gab9787add94a212edfffa82dd2fe47863"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27e73ebdbb3e3c257187546cda07466a" id="r_ga27e73ebdbb3e3c257187546cda07466a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27e73ebdbb3e3c257187546cda07466a">USB_OTG_DSTS_FNSOF_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga27e73ebdbb3e3c257187546cda07466a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9aa7bb17de01b147c98b6c23e4f146cd" id="r_ga9aa7bb17de01b147c98b6c23e4f146cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9aa7bb17de01b147c98b6c23e4f146cd">USB_OTG_DSTS_FNSOF_Msk</a>   (0x3FFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27e73ebdbb3e3c257187546cda07466a">USB_OTG_DSTS_FNSOF_Pos</a>)</td></tr>
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<tr class="separator:ga9aa7bb17de01b147c98b6c23e4f146cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga047ff56c1d9fbd02b738f2a5bf768a45" id="r_ga047ff56c1d9fbd02b738f2a5bf768a45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga047ff56c1d9fbd02b738f2a5bf768a45">USB_OTG_DSTS_FNSOF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9aa7bb17de01b147c98b6c23e4f146cd">USB_OTG_DSTS_FNSOF_Msk</a></td></tr>
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<tr class="separator:ga047ff56c1d9fbd02b738f2a5bf768a45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga02c768ed073f3aaa6a43cf514e44a1d5" id="r_ga02c768ed073f3aaa6a43cf514e44a1d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02c768ed073f3aaa6a43cf514e44a1d5">USB_OTG_GAHBCFG_GINT_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga02c768ed073f3aaa6a43cf514e44a1d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadfab3e804f69049a10d08b30d986ecf0" id="r_gadfab3e804f69049a10d08b30d986ecf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadfab3e804f69049a10d08b30d986ecf0">USB_OTG_GAHBCFG_GINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga02c768ed073f3aaa6a43cf514e44a1d5">USB_OTG_GAHBCFG_GINT_Pos</a>)</td></tr>
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<tr class="separator:gadfab3e804f69049a10d08b30d986ecf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd1bbe9e90d56d2aa225ff5532e15c6e" id="r_gafd1bbe9e90d56d2aa225ff5532e15c6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd1bbe9e90d56d2aa225ff5532e15c6e">USB_OTG_GAHBCFG_GINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadfab3e804f69049a10d08b30d986ecf0">USB_OTG_GAHBCFG_GINT_Msk</a></td></tr>
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<tr class="separator:gafd1bbe9e90d56d2aa225ff5532e15c6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabaef2f23bb565f244cae0c2fed8655bf" id="r_gabaef2f23bb565f244cae0c2fed8655bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabaef2f23bb565f244cae0c2fed8655bf">USB_OTG_GAHBCFG_HBSTLEN_Pos</a>   (1U)</td></tr>
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<tr class="separator:gabaef2f23bb565f244cae0c2fed8655bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f129cc1f698c1a272851d848541397c" id="r_ga0f129cc1f698c1a272851d848541397c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f129cc1f698c1a272851d848541397c">USB_OTG_GAHBCFG_HBSTLEN_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaef2f23bb565f244cae0c2fed8655bf">USB_OTG_GAHBCFG_HBSTLEN_Pos</a>)</td></tr>
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<tr class="separator:ga0f129cc1f698c1a272851d848541397c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ffbca11bd10b4d94843a5084078fdd4" id="r_ga2ffbca11bd10b4d94843a5084078fdd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ffbca11bd10b4d94843a5084078fdd4">USB_OTG_GAHBCFG_HBSTLEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0f129cc1f698c1a272851d848541397c">USB_OTG_GAHBCFG_HBSTLEN_Msk</a></td></tr>
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<tr class="separator:ga2ffbca11bd10b4d94843a5084078fdd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacccaf834ac65b3859e6f0519d2c4d75d" id="r_gacccaf834ac65b3859e6f0519d2c4d75d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacccaf834ac65b3859e6f0519d2c4d75d">USB_OTG_GAHBCFG_HBSTLEN_0</a>   (0x0UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaef2f23bb565f244cae0c2fed8655bf">USB_OTG_GAHBCFG_HBSTLEN_Pos</a>)</td></tr>
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<tr class="separator:gacccaf834ac65b3859e6f0519d2c4d75d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga944e91046cd27e0bea8954bd56a45a94" id="r_ga944e91046cd27e0bea8954bd56a45a94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga944e91046cd27e0bea8954bd56a45a94">USB_OTG_GAHBCFG_HBSTLEN_1</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaef2f23bb565f244cae0c2fed8655bf">USB_OTG_GAHBCFG_HBSTLEN_Pos</a>)</td></tr>
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<tr class="separator:ga944e91046cd27e0bea8954bd56a45a94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b9994176dc5115431b0a537ad26900c" id="r_ga3b9994176dc5115431b0a537ad26900c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b9994176dc5115431b0a537ad26900c">USB_OTG_GAHBCFG_HBSTLEN_2</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaef2f23bb565f244cae0c2fed8655bf">USB_OTG_GAHBCFG_HBSTLEN_Pos</a>)</td></tr>
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<tr class="separator:ga3b9994176dc5115431b0a537ad26900c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ac6781cf82fd4c21a342b4e8c8f25f8" id="r_ga1ac6781cf82fd4c21a342b4e8c8f25f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ac6781cf82fd4c21a342b4e8c8f25f8">USB_OTG_GAHBCFG_HBSTLEN_3</a>   (0x5UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaef2f23bb565f244cae0c2fed8655bf">USB_OTG_GAHBCFG_HBSTLEN_Pos</a>)</td></tr>
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<tr class="separator:ga1ac6781cf82fd4c21a342b4e8c8f25f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae60a1aed37523932d2cbfa6e78963e28" id="r_gae60a1aed37523932d2cbfa6e78963e28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae60a1aed37523932d2cbfa6e78963e28">USB_OTG_GAHBCFG_HBSTLEN_4</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaef2f23bb565f244cae0c2fed8655bf">USB_OTG_GAHBCFG_HBSTLEN_Pos</a>)</td></tr>
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<tr class="separator:gae60a1aed37523932d2cbfa6e78963e28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4dbb305ea29c5269f275bb2f727fc0a" id="r_gad4dbb305ea29c5269f275bb2f727fc0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4dbb305ea29c5269f275bb2f727fc0a">USB_OTG_GAHBCFG_DMAEN_Pos</a>   (5U)</td></tr>
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<tr class="separator:gad4dbb305ea29c5269f275bb2f727fc0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67d9f42ed7111f4a498e213ceae2d357" id="r_ga67d9f42ed7111f4a498e213ceae2d357"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67d9f42ed7111f4a498e213ceae2d357">USB_OTG_GAHBCFG_DMAEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad4dbb305ea29c5269f275bb2f727fc0a">USB_OTG_GAHBCFG_DMAEN_Pos</a>)</td></tr>
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<tr class="separator:ga67d9f42ed7111f4a498e213ceae2d357"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46b9ace9572bb6ec977594c8b4b0825f" id="r_ga46b9ace9572bb6ec977594c8b4b0825f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46b9ace9572bb6ec977594c8b4b0825f">USB_OTG_GAHBCFG_DMAEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67d9f42ed7111f4a498e213ceae2d357">USB_OTG_GAHBCFG_DMAEN_Msk</a></td></tr>
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<tr class="separator:ga46b9ace9572bb6ec977594c8b4b0825f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59620c8a8f85f5f5986b0382152e2564" id="r_ga59620c8a8f85f5f5986b0382152e2564"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59620c8a8f85f5f5986b0382152e2564">USB_OTG_GAHBCFG_TXFELVL_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga59620c8a8f85f5f5986b0382152e2564"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadbed93fcc3e44debab0f9a6b8f56a4e4" id="r_gadbed93fcc3e44debab0f9a6b8f56a4e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadbed93fcc3e44debab0f9a6b8f56a4e4">USB_OTG_GAHBCFG_TXFELVL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga59620c8a8f85f5f5986b0382152e2564">USB_OTG_GAHBCFG_TXFELVL_Pos</a>)</td></tr>
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<tr class="separator:gadbed93fcc3e44debab0f9a6b8f56a4e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a8af9d1d89b731426db773905ae4450" id="r_ga6a8af9d1d89b731426db773905ae4450"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a8af9d1d89b731426db773905ae4450">USB_OTG_GAHBCFG_TXFELVL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadbed93fcc3e44debab0f9a6b8f56a4e4">USB_OTG_GAHBCFG_TXFELVL_Msk</a></td></tr>
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<tr class="separator:ga6a8af9d1d89b731426db773905ae4450"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf86fe83bcec3b4ce6a21c18bb0996af8" id="r_gaf86fe83bcec3b4ce6a21c18bb0996af8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf86fe83bcec3b4ce6a21c18bb0996af8">USB_OTG_GAHBCFG_PTXFELVL_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaf86fe83bcec3b4ce6a21c18bb0996af8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ce05358bc5a54302af1f296bd1338c4" id="r_ga1ce05358bc5a54302af1f296bd1338c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ce05358bc5a54302af1f296bd1338c4">USB_OTG_GAHBCFG_PTXFELVL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf86fe83bcec3b4ce6a21c18bb0996af8">USB_OTG_GAHBCFG_PTXFELVL_Pos</a>)</td></tr>
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<tr class="separator:ga1ce05358bc5a54302af1f296bd1338c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7443f8ddb5b67b506637b282923a0c57" id="r_ga7443f8ddb5b67b506637b282923a0c57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7443f8ddb5b67b506637b282923a0c57">USB_OTG_GAHBCFG_PTXFELVL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ce05358bc5a54302af1f296bd1338c4">USB_OTG_GAHBCFG_PTXFELVL_Msk</a></td></tr>
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<tr class="separator:ga7443f8ddb5b67b506637b282923a0c57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga652452baf3a68648d58eda39f8b95b17" id="r_ga652452baf3a68648d58eda39f8b95b17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga652452baf3a68648d58eda39f8b95b17">USB_OTG_GUSBCFG_TOCAL_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga652452baf3a68648d58eda39f8b95b17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa03324441e7f1d314a3d553097a97d98" id="r_gaa03324441e7f1d314a3d553097a97d98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa03324441e7f1d314a3d553097a97d98">USB_OTG_GUSBCFG_TOCAL_Msk</a>   (0x7UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga652452baf3a68648d58eda39f8b95b17">USB_OTG_GUSBCFG_TOCAL_Pos</a>)</td></tr>
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<tr class="separator:gaa03324441e7f1d314a3d553097a97d98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb035573c48f1055126d94a3c15dd5f3" id="r_gadb035573c48f1055126d94a3c15dd5f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb035573c48f1055126d94a3c15dd5f3">USB_OTG_GUSBCFG_TOCAL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa03324441e7f1d314a3d553097a97d98">USB_OTG_GUSBCFG_TOCAL_Msk</a></td></tr>
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<tr class="separator:gadb035573c48f1055126d94a3c15dd5f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9afeebc0fdfffa134586228627d0994" id="r_gaa9afeebc0fdfffa134586228627d0994"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9afeebc0fdfffa134586228627d0994">USB_OTG_GUSBCFG_TOCAL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga652452baf3a68648d58eda39f8b95b17">USB_OTG_GUSBCFG_TOCAL_Pos</a>)</td></tr>
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<tr class="separator:gaa9afeebc0fdfffa134586228627d0994"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad406f5ebd83521f075d973f1afae39f8" id="r_gad406f5ebd83521f075d973f1afae39f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad406f5ebd83521f075d973f1afae39f8">USB_OTG_GUSBCFG_TOCAL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga652452baf3a68648d58eda39f8b95b17">USB_OTG_GUSBCFG_TOCAL_Pos</a>)</td></tr>
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<tr class="separator:gad406f5ebd83521f075d973f1afae39f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c336a75d6e5035c376667f9794d9aae" id="r_ga5c336a75d6e5035c376667f9794d9aae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c336a75d6e5035c376667f9794d9aae">USB_OTG_GUSBCFG_TOCAL_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga652452baf3a68648d58eda39f8b95b17">USB_OTG_GUSBCFG_TOCAL_Pos</a>)</td></tr>
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<tr class="separator:ga5c336a75d6e5035c376667f9794d9aae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55cc06db9db1914662fbcf8ad9de06b8" id="r_ga55cc06db9db1914662fbcf8ad9de06b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55cc06db9db1914662fbcf8ad9de06b8">USB_OTG_GUSBCFG_PHYSEL_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga55cc06db9db1914662fbcf8ad9de06b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3373712099429d9b7186af1f2bf1e662" id="r_ga3373712099429d9b7186af1f2bf1e662"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3373712099429d9b7186af1f2bf1e662">USB_OTG_GUSBCFG_PHYSEL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55cc06db9db1914662fbcf8ad9de06b8">USB_OTG_GUSBCFG_PHYSEL_Pos</a>)</td></tr>
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<tr class="separator:ga3373712099429d9b7186af1f2bf1e662"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2148059ec3e6a804d102ed9964c9a005" id="r_ga2148059ec3e6a804d102ed9964c9a005"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2148059ec3e6a804d102ed9964c9a005">USB_OTG_GUSBCFG_PHYSEL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3373712099429d9b7186af1f2bf1e662">USB_OTG_GUSBCFG_PHYSEL_Msk</a></td></tr>
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<tr class="separator:ga2148059ec3e6a804d102ed9964c9a005"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24275f2398ac98c01acd951a7a03d3dc" id="r_ga24275f2398ac98c01acd951a7a03d3dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24275f2398ac98c01acd951a7a03d3dc">USB_OTG_GUSBCFG_SRPCAP_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga24275f2398ac98c01acd951a7a03d3dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffdc662f62192d4b3b04c2967dc17499" id="r_gaffdc662f62192d4b3b04c2967dc17499"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffdc662f62192d4b3b04c2967dc17499">USB_OTG_GUSBCFG_SRPCAP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24275f2398ac98c01acd951a7a03d3dc">USB_OTG_GUSBCFG_SRPCAP_Pos</a>)</td></tr>
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<tr class="separator:gaffdc662f62192d4b3b04c2967dc17499"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26cadf8d7d278615a2681c308d69a1f4" id="r_ga26cadf8d7d278615a2681c308d69a1f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26cadf8d7d278615a2681c308d69a1f4">USB_OTG_GUSBCFG_SRPCAP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaffdc662f62192d4b3b04c2967dc17499">USB_OTG_GUSBCFG_SRPCAP_Msk</a></td></tr>
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<tr class="separator:ga26cadf8d7d278615a2681c308d69a1f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f1e032b4bf712c5f02f8fcbf6493f9c" id="r_ga6f1e032b4bf712c5f02f8fcbf6493f9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f1e032b4bf712c5f02f8fcbf6493f9c">USB_OTG_GUSBCFG_HNPCAP_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga6f1e032b4bf712c5f02f8fcbf6493f9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga014d25d1f767f3db5ad0c60e7c752607" id="r_ga014d25d1f767f3db5ad0c60e7c752607"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga014d25d1f767f3db5ad0c60e7c752607">USB_OTG_GUSBCFG_HNPCAP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f1e032b4bf712c5f02f8fcbf6493f9c">USB_OTG_GUSBCFG_HNPCAP_Pos</a>)</td></tr>
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<tr class="separator:ga014d25d1f767f3db5ad0c60e7c752607"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e220d23f5739e07442461204a70a2c7" id="r_ga6e220d23f5739e07442461204a70a2c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e220d23f5739e07442461204a70a2c7">USB_OTG_GUSBCFG_HNPCAP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga014d25d1f767f3db5ad0c60e7c752607">USB_OTG_GUSBCFG_HNPCAP_Msk</a></td></tr>
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<tr class="separator:ga6e220d23f5739e07442461204a70a2c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bb11f994508c0f3582a561c67784df2" id="r_ga5bb11f994508c0f3582a561c67784df2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bb11f994508c0f3582a561c67784df2">USB_OTG_GUSBCFG_TRDT_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga5bb11f994508c0f3582a561c67784df2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec02000199e190ce726adc091bd9fc18" id="r_gaec02000199e190ce726adc091bd9fc18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec02000199e190ce726adc091bd9fc18">USB_OTG_GUSBCFG_TRDT_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bb11f994508c0f3582a561c67784df2">USB_OTG_GUSBCFG_TRDT_Pos</a>)</td></tr>
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<tr class="separator:gaec02000199e190ce726adc091bd9fc18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedf4c990f79714f2747232ccb7470d4c" id="r_gaedf4c990f79714f2747232ccb7470d4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedf4c990f79714f2747232ccb7470d4c">USB_OTG_GUSBCFG_TRDT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec02000199e190ce726adc091bd9fc18">USB_OTG_GUSBCFG_TRDT_Msk</a></td></tr>
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<tr class="separator:gaedf4c990f79714f2747232ccb7470d4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09f21fcd7d2ba96955088e33afa034e5" id="r_ga09f21fcd7d2ba96955088e33afa034e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09f21fcd7d2ba96955088e33afa034e5">USB_OTG_GUSBCFG_TRDT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bb11f994508c0f3582a561c67784df2">USB_OTG_GUSBCFG_TRDT_Pos</a>)</td></tr>
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<tr class="separator:ga09f21fcd7d2ba96955088e33afa034e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad316e69d3679d7fa0a73caf577e1d2b8" id="r_gad316e69d3679d7fa0a73caf577e1d2b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad316e69d3679d7fa0a73caf577e1d2b8">USB_OTG_GUSBCFG_TRDT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bb11f994508c0f3582a561c67784df2">USB_OTG_GUSBCFG_TRDT_Pos</a>)</td></tr>
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<tr class="separator:gad316e69d3679d7fa0a73caf577e1d2b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8ecdc45ec0654c353bee6da6d17a9a6" id="r_gad8ecdc45ec0654c353bee6da6d17a9a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8ecdc45ec0654c353bee6da6d17a9a6">USB_OTG_GUSBCFG_TRDT_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bb11f994508c0f3582a561c67784df2">USB_OTG_GUSBCFG_TRDT_Pos</a>)</td></tr>
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<tr class="separator:gad8ecdc45ec0654c353bee6da6d17a9a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga019e347f4b9b5a2bf980b90e921c23f0" id="r_ga019e347f4b9b5a2bf980b90e921c23f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga019e347f4b9b5a2bf980b90e921c23f0">USB_OTG_GUSBCFG_TRDT_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bb11f994508c0f3582a561c67784df2">USB_OTG_GUSBCFG_TRDT_Pos</a>)</td></tr>
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<tr class="separator:ga019e347f4b9b5a2bf980b90e921c23f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9374168e3afcc350fa7645900bec121" id="r_gac9374168e3afcc350fa7645900bec121"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9374168e3afcc350fa7645900bec121">USB_OTG_GUSBCFG_PHYLPCS_Pos</a>   (15U)</td></tr>
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<tr class="separator:gac9374168e3afcc350fa7645900bec121"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga754ace191e8556620eec7c93ba53a914" id="r_ga754ace191e8556620eec7c93ba53a914"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga754ace191e8556620eec7c93ba53a914">USB_OTG_GUSBCFG_PHYLPCS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9374168e3afcc350fa7645900bec121">USB_OTG_GUSBCFG_PHYLPCS_Pos</a>)</td></tr>
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<tr class="separator:ga754ace191e8556620eec7c93ba53a914"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga87e134cc67f7b77efcb1506f7ca57b64" id="r_ga87e134cc67f7b77efcb1506f7ca57b64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga87e134cc67f7b77efcb1506f7ca57b64">USB_OTG_GUSBCFG_PHYLPCS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga754ace191e8556620eec7c93ba53a914">USB_OTG_GUSBCFG_PHYLPCS_Msk</a></td></tr>
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<tr class="separator:ga87e134cc67f7b77efcb1506f7ca57b64"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cf18014a20add68d69f8cceb62e012e" id="r_ga1cf18014a20add68d69f8cceb62e012e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cf18014a20add68d69f8cceb62e012e">USB_OTG_GUSBCFG_ULPIFSLS_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga1cf18014a20add68d69f8cceb62e012e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff2a24486b52bc1e86707e5e4f9ebbd9" id="r_gaff2a24486b52bc1e86707e5e4f9ebbd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff2a24486b52bc1e86707e5e4f9ebbd9">USB_OTG_GUSBCFG_ULPIFSLS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1cf18014a20add68d69f8cceb62e012e">USB_OTG_GUSBCFG_ULPIFSLS_Pos</a>)</td></tr>
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<tr class="separator:gaff2a24486b52bc1e86707e5e4f9ebbd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ad0a14d1e0b69f72209ac0de8290862" id="r_ga9ad0a14d1e0b69f72209ac0de8290862"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ad0a14d1e0b69f72209ac0de8290862">USB_OTG_GUSBCFG_ULPIFSLS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaff2a24486b52bc1e86707e5e4f9ebbd9">USB_OTG_GUSBCFG_ULPIFSLS_Msk</a></td></tr>
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<tr class="separator:ga9ad0a14d1e0b69f72209ac0de8290862"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d99b3198a804e57d5b103de896cbae1" id="r_ga3d99b3198a804e57d5b103de896cbae1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d99b3198a804e57d5b103de896cbae1">USB_OTG_GUSBCFG_ULPIAR_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga3d99b3198a804e57d5b103de896cbae1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2787eb50165fdc318425a15808e195d7" id="r_ga2787eb50165fdc318425a15808e195d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2787eb50165fdc318425a15808e195d7">USB_OTG_GUSBCFG_ULPIAR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d99b3198a804e57d5b103de896cbae1">USB_OTG_GUSBCFG_ULPIAR_Pos</a>)</td></tr>
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<tr class="separator:ga2787eb50165fdc318425a15808e195d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9996da3f96fd45ce80d12a1db533b89d" id="r_ga9996da3f96fd45ce80d12a1db533b89d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9996da3f96fd45ce80d12a1db533b89d">USB_OTG_GUSBCFG_ULPIAR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2787eb50165fdc318425a15808e195d7">USB_OTG_GUSBCFG_ULPIAR_Msk</a></td></tr>
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<tr class="separator:ga9996da3f96fd45ce80d12a1db533b89d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c0898ecb1e370e25eda1e7b4296f497" id="r_ga8c0898ecb1e370e25eda1e7b4296f497"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c0898ecb1e370e25eda1e7b4296f497">USB_OTG_GUSBCFG_ULPICSM_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga8c0898ecb1e370e25eda1e7b4296f497"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb75fefda7133445f8372502ee6dc415" id="r_gacb75fefda7133445f8372502ee6dc415"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb75fefda7133445f8372502ee6dc415">USB_OTG_GUSBCFG_ULPICSM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c0898ecb1e370e25eda1e7b4296f497">USB_OTG_GUSBCFG_ULPICSM_Pos</a>)</td></tr>
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<tr class="separator:gacb75fefda7133445f8372502ee6dc415"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7f25e19a542791bcb97956262637e9b" id="r_gae7f25e19a542791bcb97956262637e9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7f25e19a542791bcb97956262637e9b">USB_OTG_GUSBCFG_ULPICSM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacb75fefda7133445f8372502ee6dc415">USB_OTG_GUSBCFG_ULPICSM_Msk</a></td></tr>
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<tr class="separator:gae7f25e19a542791bcb97956262637e9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga971bd3927ed8382dc26b7031f44140ab" id="r_ga971bd3927ed8382dc26b7031f44140ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga971bd3927ed8382dc26b7031f44140ab">USB_OTG_GUSBCFG_ULPIEVBUSD_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga971bd3927ed8382dc26b7031f44140ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51f99055d4e1309feeba94e88c767f03" id="r_ga51f99055d4e1309feeba94e88c767f03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51f99055d4e1309feeba94e88c767f03">USB_OTG_GUSBCFG_ULPIEVBUSD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga971bd3927ed8382dc26b7031f44140ab">USB_OTG_GUSBCFG_ULPIEVBUSD_Pos</a>)</td></tr>
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<tr class="separator:ga51f99055d4e1309feeba94e88c767f03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafad0b734f8f4511d7839385a01f105b6" id="r_gafad0b734f8f4511d7839385a01f105b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafad0b734f8f4511d7839385a01f105b6">USB_OTG_GUSBCFG_ULPIEVBUSD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga51f99055d4e1309feeba94e88c767f03">USB_OTG_GUSBCFG_ULPIEVBUSD_Msk</a></td></tr>
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<tr class="separator:gafad0b734f8f4511d7839385a01f105b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3c02da8d9118f5fb97e6ba78fd4d04f" id="r_gad3c02da8d9118f5fb97e6ba78fd4d04f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3c02da8d9118f5fb97e6ba78fd4d04f">USB_OTG_GUSBCFG_ULPIEVBUSI_Pos</a>   (21U)</td></tr>
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<tr class="separator:gad3c02da8d9118f5fb97e6ba78fd4d04f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04c1b32f50469cd6f5b5728b85af1ad0" id="r_ga04c1b32f50469cd6f5b5728b85af1ad0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04c1b32f50469cd6f5b5728b85af1ad0">USB_OTG_GUSBCFG_ULPIEVBUSI_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad3c02da8d9118f5fb97e6ba78fd4d04f">USB_OTG_GUSBCFG_ULPIEVBUSI_Pos</a>)</td></tr>
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<tr class="separator:ga04c1b32f50469cd6f5b5728b85af1ad0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a57c032717ceeeef110b7fd33cddd79" id="r_ga3a57c032717ceeeef110b7fd33cddd79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a57c032717ceeeef110b7fd33cddd79">USB_OTG_GUSBCFG_ULPIEVBUSI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga04c1b32f50469cd6f5b5728b85af1ad0">USB_OTG_GUSBCFG_ULPIEVBUSI_Msk</a></td></tr>
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<tr class="separator:ga3a57c032717ceeeef110b7fd33cddd79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72a8efdaa2432c74a2e7e81a79ee96b0" id="r_ga72a8efdaa2432c74a2e7e81a79ee96b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72a8efdaa2432c74a2e7e81a79ee96b0">USB_OTG_GUSBCFG_TSDPS_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga72a8efdaa2432c74a2e7e81a79ee96b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4f3f8f8230c13d226cfc088d2ef2f5b" id="r_gac4f3f8f8230c13d226cfc088d2ef2f5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4f3f8f8230c13d226cfc088d2ef2f5b">USB_OTG_GUSBCFG_TSDPS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga72a8efdaa2432c74a2e7e81a79ee96b0">USB_OTG_GUSBCFG_TSDPS_Pos</a>)</td></tr>
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<tr class="separator:gac4f3f8f8230c13d226cfc088d2ef2f5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe1cdbe63bf7a5b2212e602f88a16796" id="r_gabe1cdbe63bf7a5b2212e602f88a16796"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe1cdbe63bf7a5b2212e602f88a16796">USB_OTG_GUSBCFG_TSDPS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4f3f8f8230c13d226cfc088d2ef2f5b">USB_OTG_GUSBCFG_TSDPS_Msk</a></td></tr>
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<tr class="separator:gabe1cdbe63bf7a5b2212e602f88a16796"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68a28d51da909433ba4244ba2a5e42d8" id="r_ga68a28d51da909433ba4244ba2a5e42d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68a28d51da909433ba4244ba2a5e42d8">USB_OTG_GUSBCFG_PCCI_Pos</a>   (23U)</td></tr>
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<tr class="separator:ga68a28d51da909433ba4244ba2a5e42d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga013f30e987d548455287896e9f5600a6" id="r_ga013f30e987d548455287896e9f5600a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga013f30e987d548455287896e9f5600a6">USB_OTG_GUSBCFG_PCCI_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68a28d51da909433ba4244ba2a5e42d8">USB_OTG_GUSBCFG_PCCI_Pos</a>)</td></tr>
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<tr class="separator:ga013f30e987d548455287896e9f5600a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae325703f616d90c6c22198c288fa4f28" id="r_gae325703f616d90c6c22198c288fa4f28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae325703f616d90c6c22198c288fa4f28">USB_OTG_GUSBCFG_PCCI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga013f30e987d548455287896e9f5600a6">USB_OTG_GUSBCFG_PCCI_Msk</a></td></tr>
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<tr class="separator:gae325703f616d90c6c22198c288fa4f28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa08ed9b2e729e9b8ff29283ed8fadb84" id="r_gaa08ed9b2e729e9b8ff29283ed8fadb84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa08ed9b2e729e9b8ff29283ed8fadb84">USB_OTG_GUSBCFG_PTCI_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaa08ed9b2e729e9b8ff29283ed8fadb84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab89a6d18ebdbf9a78551b167eedf7c2f" id="r_gab89a6d18ebdbf9a78551b167eedf7c2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab89a6d18ebdbf9a78551b167eedf7c2f">USB_OTG_GUSBCFG_PTCI_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa08ed9b2e729e9b8ff29283ed8fadb84">USB_OTG_GUSBCFG_PTCI_Pos</a>)</td></tr>
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<tr class="separator:gab89a6d18ebdbf9a78551b167eedf7c2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55174040ef4566af2326b0a424bff30a" id="r_ga55174040ef4566af2326b0a424bff30a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55174040ef4566af2326b0a424bff30a">USB_OTG_GUSBCFG_PTCI</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab89a6d18ebdbf9a78551b167eedf7c2f">USB_OTG_GUSBCFG_PTCI_Msk</a></td></tr>
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<tr class="separator:ga55174040ef4566af2326b0a424bff30a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a20078b3fc4f5aad413fe73b96c7ed3" id="r_ga8a20078b3fc4f5aad413fe73b96c7ed3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8a20078b3fc4f5aad413fe73b96c7ed3">USB_OTG_GUSBCFG_ULPIIPD_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga8a20078b3fc4f5aad413fe73b96c7ed3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c2349edc84b6a82c2e350ae60c3c49b" id="r_ga3c2349edc84b6a82c2e350ae60c3c49b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c2349edc84b6a82c2e350ae60c3c49b">USB_OTG_GUSBCFG_ULPIIPD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8a20078b3fc4f5aad413fe73b96c7ed3">USB_OTG_GUSBCFG_ULPIIPD_Pos</a>)</td></tr>
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<tr class="separator:ga3c2349edc84b6a82c2e350ae60c3c49b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga240a106dc942384f0c0dae11a7efc018" id="r_ga240a106dc942384f0c0dae11a7efc018"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga240a106dc942384f0c0dae11a7efc018">USB_OTG_GUSBCFG_ULPIIPD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c2349edc84b6a82c2e350ae60c3c49b">USB_OTG_GUSBCFG_ULPIIPD_Msk</a></td></tr>
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<tr class="separator:ga240a106dc942384f0c0dae11a7efc018"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78d129fd19d35e210ec7dcf9e50dfd07" id="r_ga78d129fd19d35e210ec7dcf9e50dfd07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78d129fd19d35e210ec7dcf9e50dfd07">USB_OTG_GUSBCFG_FHMOD_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga78d129fd19d35e210ec7dcf9e50dfd07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b9aae8e1a49ed8a7d8b3d8a779581a3" id="r_ga8b9aae8e1a49ed8a7d8b3d8a779581a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b9aae8e1a49ed8a7d8b3d8a779581a3">USB_OTG_GUSBCFG_FHMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78d129fd19d35e210ec7dcf9e50dfd07">USB_OTG_GUSBCFG_FHMOD_Pos</a>)</td></tr>
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<tr class="separator:ga8b9aae8e1a49ed8a7d8b3d8a779581a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2bafa204b663017c8c08dcd42c1c031" id="r_gac2bafa204b663017c8c08dcd42c1c031"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2bafa204b663017c8c08dcd42c1c031">USB_OTG_GUSBCFG_FHMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b9aae8e1a49ed8a7d8b3d8a779581a3">USB_OTG_GUSBCFG_FHMOD_Msk</a></td></tr>
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<tr class="separator:gac2bafa204b663017c8c08dcd42c1c031"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa1338a2855521cf8b23de215e0a24d4" id="r_gaaa1338a2855521cf8b23de215e0a24d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa1338a2855521cf8b23de215e0a24d4">USB_OTG_GUSBCFG_FDMOD_Pos</a>   (30U)</td></tr>
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<tr class="separator:gaaa1338a2855521cf8b23de215e0a24d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93cc2f6447eb4b2e36588e604b66d2b8" id="r_ga93cc2f6447eb4b2e36588e604b66d2b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93cc2f6447eb4b2e36588e604b66d2b8">USB_OTG_GUSBCFG_FDMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa1338a2855521cf8b23de215e0a24d4">USB_OTG_GUSBCFG_FDMOD_Pos</a>)</td></tr>
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<tr class="separator:ga93cc2f6447eb4b2e36588e604b66d2b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga012379ec9a2c86e7d28f5dc882fed0c5" id="r_ga012379ec9a2c86e7d28f5dc882fed0c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga012379ec9a2c86e7d28f5dc882fed0c5">USB_OTG_GUSBCFG_FDMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga93cc2f6447eb4b2e36588e604b66d2b8">USB_OTG_GUSBCFG_FDMOD_Msk</a></td></tr>
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<tr class="separator:ga012379ec9a2c86e7d28f5dc882fed0c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58fa0446165b4a2d5dbb3998ca3c8030" id="r_ga58fa0446165b4a2d5dbb3998ca3c8030"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58fa0446165b4a2d5dbb3998ca3c8030">USB_OTG_GUSBCFG_CTXPKT_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga58fa0446165b4a2d5dbb3998ca3c8030"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90ac2f68e29f0584ba980f3d396eb1e2" id="r_ga90ac2f68e29f0584ba980f3d396eb1e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90ac2f68e29f0584ba980f3d396eb1e2">USB_OTG_GUSBCFG_CTXPKT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58fa0446165b4a2d5dbb3998ca3c8030">USB_OTG_GUSBCFG_CTXPKT_Pos</a>)</td></tr>
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<tr class="separator:ga90ac2f68e29f0584ba980f3d396eb1e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0efb62f80533abcf9cecd96815200380" id="r_ga0efb62f80533abcf9cecd96815200380"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0efb62f80533abcf9cecd96815200380">USB_OTG_GUSBCFG_CTXPKT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga90ac2f68e29f0584ba980f3d396eb1e2">USB_OTG_GUSBCFG_CTXPKT_Msk</a></td></tr>
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<tr class="memitem:gae5123d9d21428692a45e351595b14954" id="r_gae5123d9d21428692a45e351595b14954"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5123d9d21428692a45e351595b14954">USB_OTG_GRSTCTL_CSRST_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga1ff29d2fa7bd837e8130717b43e71a04" id="r_ga1ff29d2fa7bd837e8130717b43e71a04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ff29d2fa7bd837e8130717b43e71a04">USB_OTG_GRSTCTL_CSRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae5123d9d21428692a45e351595b14954">USB_OTG_GRSTCTL_CSRST_Pos</a>)</td></tr>
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<tr class="separator:ga1ff29d2fa7bd837e8130717b43e71a04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2e85306ee6705e7120877dee47d50b0" id="r_gad2e85306ee6705e7120877dee47d50b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2e85306ee6705e7120877dee47d50b0">USB_OTG_GRSTCTL_CSRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ff29d2fa7bd837e8130717b43e71a04">USB_OTG_GRSTCTL_CSRST_Msk</a></td></tr>
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<tr class="separator:gad2e85306ee6705e7120877dee47d50b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2d70beddcb07affa73404fb00c02e9d" id="r_gab2d70beddcb07affa73404fb00c02e9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2d70beddcb07affa73404fb00c02e9d">USB_OTG_GRSTCTL_HSRST_Pos</a>   (1U)</td></tr>
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<tr class="separator:gab2d70beddcb07affa73404fb00c02e9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff92f8742438f99c8e81d37c63e8fbf0" id="r_gaff92f8742438f99c8e81d37c63e8fbf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff92f8742438f99c8e81d37c63e8fbf0">USB_OTG_GRSTCTL_HSRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab2d70beddcb07affa73404fb00c02e9d">USB_OTG_GRSTCTL_HSRST_Pos</a>)</td></tr>
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<tr class="separator:gaff92f8742438f99c8e81d37c63e8fbf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88a5f9be64498b49d12a3dc7b5bb4d0c" id="r_ga88a5f9be64498b49d12a3dc7b5bb4d0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88a5f9be64498b49d12a3dc7b5bb4d0c">USB_OTG_GRSTCTL_HSRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaff92f8742438f99c8e81d37c63e8fbf0">USB_OTG_GRSTCTL_HSRST_Msk</a></td></tr>
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<tr class="separator:ga88a5f9be64498b49d12a3dc7b5bb4d0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace5718ced264cecb7108c689b6cf3d66" id="r_gace5718ced264cecb7108c689b6cf3d66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace5718ced264cecb7108c689b6cf3d66">USB_OTG_GRSTCTL_FCRST_Pos</a>   (2U)</td></tr>
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<tr class="separator:gace5718ced264cecb7108c689b6cf3d66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e8b8125ce36876edcb9041304fb0d81" id="r_ga0e8b8125ce36876edcb9041304fb0d81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e8b8125ce36876edcb9041304fb0d81">USB_OTG_GRSTCTL_FCRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gace5718ced264cecb7108c689b6cf3d66">USB_OTG_GRSTCTL_FCRST_Pos</a>)</td></tr>
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<tr class="separator:ga0e8b8125ce36876edcb9041304fb0d81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6417d13d2568b05676800c9eda4bdfb" id="r_gae6417d13d2568b05676800c9eda4bdfb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae6417d13d2568b05676800c9eda4bdfb">USB_OTG_GRSTCTL_FCRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e8b8125ce36876edcb9041304fb0d81">USB_OTG_GRSTCTL_FCRST_Msk</a></td></tr>
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<tr class="separator:gae6417d13d2568b05676800c9eda4bdfb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4801088b836b002fe4b2c7525cf8a4a" id="r_gae4801088b836b002fe4b2c7525cf8a4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4801088b836b002fe4b2c7525cf8a4a">USB_OTG_GRSTCTL_RXFFLSH_Pos</a>   (4U)</td></tr>
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<tr class="separator:gae4801088b836b002fe4b2c7525cf8a4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e6d47098a622dd1002f38438db5db6d" id="r_ga6e6d47098a622dd1002f38438db5db6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e6d47098a622dd1002f38438db5db6d">USB_OTG_GRSTCTL_RXFFLSH_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4801088b836b002fe4b2c7525cf8a4a">USB_OTG_GRSTCTL_RXFFLSH_Pos</a>)</td></tr>
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<tr class="separator:ga6e6d47098a622dd1002f38438db5db6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbe28fdd671e34e48f5d96119fd91cab" id="r_gacbe28fdd671e34e48f5d96119fd91cab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacbe28fdd671e34e48f5d96119fd91cab">USB_OTG_GRSTCTL_RXFFLSH</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e6d47098a622dd1002f38438db5db6d">USB_OTG_GRSTCTL_RXFFLSH_Msk</a></td></tr>
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<tr class="separator:gacbe28fdd671e34e48f5d96119fd91cab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a3cc0fc41e913807924741e7f197cbf" id="r_ga4a3cc0fc41e913807924741e7f197cbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a3cc0fc41e913807924741e7f197cbf">USB_OTG_GRSTCTL_TXFFLSH_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga4a3cc0fc41e913807924741e7f197cbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a3ea77b9f0bdd2cb5e6c104d28278de" id="r_ga7a3ea77b9f0bdd2cb5e6c104d28278de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7a3ea77b9f0bdd2cb5e6c104d28278de">USB_OTG_GRSTCTL_TXFFLSH_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a3cc0fc41e913807924741e7f197cbf">USB_OTG_GRSTCTL_TXFFLSH_Pos</a>)</td></tr>
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<tr class="separator:ga7a3ea77b9f0bdd2cb5e6c104d28278de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac92d0ccd406f33733199edbee13eeb7b" id="r_gac92d0ccd406f33733199edbee13eeb7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac92d0ccd406f33733199edbee13eeb7b">USB_OTG_GRSTCTL_TXFFLSH</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7a3ea77b9f0bdd2cb5e6c104d28278de">USB_OTG_GRSTCTL_TXFFLSH_Msk</a></td></tr>
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<tr class="separator:gac92d0ccd406f33733199edbee13eeb7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabaa3cd465651e6d08fa0507cffaeb1ce" id="r_gabaa3cd465651e6d08fa0507cffaeb1ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabaa3cd465651e6d08fa0507cffaeb1ce">USB_OTG_GRSTCTL_TXFNUM_Pos</a>   (6U)</td></tr>
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<tr class="separator:gabaa3cd465651e6d08fa0507cffaeb1ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15516a0193e467d3a42dfe24a7a20b09" id="r_ga15516a0193e467d3a42dfe24a7a20b09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15516a0193e467d3a42dfe24a7a20b09">USB_OTG_GRSTCTL_TXFNUM_Msk</a>   (0x1FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaa3cd465651e6d08fa0507cffaeb1ce">USB_OTG_GRSTCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:ga15516a0193e467d3a42dfe24a7a20b09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d15f7c8d94dbf1b67b6d7fda680a5ad" id="r_ga1d15f7c8d94dbf1b67b6d7fda680a5ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d15f7c8d94dbf1b67b6d7fda680a5ad">USB_OTG_GRSTCTL_TXFNUM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga15516a0193e467d3a42dfe24a7a20b09">USB_OTG_GRSTCTL_TXFNUM_Msk</a></td></tr>
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<tr class="separator:ga1d15f7c8d94dbf1b67b6d7fda680a5ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30d4785ae9db0a59b8e945be32582fa3" id="r_ga30d4785ae9db0a59b8e945be32582fa3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga30d4785ae9db0a59b8e945be32582fa3">USB_OTG_GRSTCTL_TXFNUM_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaa3cd465651e6d08fa0507cffaeb1ce">USB_OTG_GRSTCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:ga30d4785ae9db0a59b8e945be32582fa3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga260a76595ceb569e47b30fc946ce7f84" id="r_ga260a76595ceb569e47b30fc946ce7f84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga260a76595ceb569e47b30fc946ce7f84">USB_OTG_GRSTCTL_TXFNUM_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaa3cd465651e6d08fa0507cffaeb1ce">USB_OTG_GRSTCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:ga260a76595ceb569e47b30fc946ce7f84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82fc2f146c00833e94244fdb640fcbd4" id="r_ga82fc2f146c00833e94244fdb640fcbd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82fc2f146c00833e94244fdb640fcbd4">USB_OTG_GRSTCTL_TXFNUM_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaa3cd465651e6d08fa0507cffaeb1ce">USB_OTG_GRSTCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:ga82fc2f146c00833e94244fdb640fcbd4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga625608800e950e7540f7888a281ab91e" id="r_ga625608800e950e7540f7888a281ab91e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga625608800e950e7540f7888a281ab91e">USB_OTG_GRSTCTL_TXFNUM_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaa3cd465651e6d08fa0507cffaeb1ce">USB_OTG_GRSTCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:ga625608800e950e7540f7888a281ab91e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafacdf091f563680eafdd5500809c912f" id="r_gafacdf091f563680eafdd5500809c912f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafacdf091f563680eafdd5500809c912f">USB_OTG_GRSTCTL_TXFNUM_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabaa3cd465651e6d08fa0507cffaeb1ce">USB_OTG_GRSTCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:gafacdf091f563680eafdd5500809c912f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e0e58f272fdcbb69d964319b0cf58db" id="r_ga8e0e58f272fdcbb69d964319b0cf58db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e0e58f272fdcbb69d964319b0cf58db">USB_OTG_GRSTCTL_DMAREQ_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga8e0e58f272fdcbb69d964319b0cf58db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac32cd68230279be0476ab2bafd5f8e1d" id="r_gac32cd68230279be0476ab2bafd5f8e1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac32cd68230279be0476ab2bafd5f8e1d">USB_OTG_GRSTCTL_DMAREQ_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e0e58f272fdcbb69d964319b0cf58db">USB_OTG_GRSTCTL_DMAREQ_Pos</a>)</td></tr>
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<tr class="separator:gac32cd68230279be0476ab2bafd5f8e1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf152b268977d411b34bf47e674a8239a" id="r_gaf152b268977d411b34bf47e674a8239a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf152b268977d411b34bf47e674a8239a">USB_OTG_GRSTCTL_DMAREQ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac32cd68230279be0476ab2bafd5f8e1d">USB_OTG_GRSTCTL_DMAREQ_Msk</a></td></tr>
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<tr class="separator:gaf152b268977d411b34bf47e674a8239a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25e845d8586bdcf102f99fde5ba85f40" id="r_ga25e845d8586bdcf102f99fde5ba85f40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25e845d8586bdcf102f99fde5ba85f40">USB_OTG_GRSTCTL_AHBIDL_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga25e845d8586bdcf102f99fde5ba85f40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dd9f38aa1f6dcc20c4eeb13a6547a46" id="r_ga4dd9f38aa1f6dcc20c4eeb13a6547a46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dd9f38aa1f6dcc20c4eeb13a6547a46">USB_OTG_GRSTCTL_AHBIDL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25e845d8586bdcf102f99fde5ba85f40">USB_OTG_GRSTCTL_AHBIDL_Pos</a>)</td></tr>
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<tr class="separator:ga4dd9f38aa1f6dcc20c4eeb13a6547a46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabfc525ece665c5448d652166bf962b7a" id="r_gabfc525ece665c5448d652166bf962b7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfc525ece665c5448d652166bf962b7a">USB_OTG_GRSTCTL_AHBIDL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4dd9f38aa1f6dcc20c4eeb13a6547a46">USB_OTG_GRSTCTL_AHBIDL_Msk</a></td></tr>
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<tr class="separator:gabfc525ece665c5448d652166bf962b7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77a95aac6875bc11ee78ffec7381ec24" id="r_ga77a95aac6875bc11ee78ffec7381ec24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77a95aac6875bc11ee78ffec7381ec24">USB_OTG_DIEPMSK_XFRCM_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga4d4f31482f2ac26051500e0c8f3a0869" id="r_ga4d4f31482f2ac26051500e0c8f3a0869"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d4f31482f2ac26051500e0c8f3a0869">USB_OTG_DIEPMSK_XFRCM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga77a95aac6875bc11ee78ffec7381ec24">USB_OTG_DIEPMSK_XFRCM_Pos</a>)</td></tr>
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<tr class="separator:ga4d4f31482f2ac26051500e0c8f3a0869"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f5c0badd33dc95fa7897bd4bb558ad6" id="r_ga6f5c0badd33dc95fa7897bd4bb558ad6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f5c0badd33dc95fa7897bd4bb558ad6">USB_OTG_DIEPMSK_XFRCM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d4f31482f2ac26051500e0c8f3a0869">USB_OTG_DIEPMSK_XFRCM_Msk</a></td></tr>
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<tr class="separator:ga6f5c0badd33dc95fa7897bd4bb558ad6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf33e7f717470ec3ffbaf5655caeb5042" id="r_gaf33e7f717470ec3ffbaf5655caeb5042"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf33e7f717470ec3ffbaf5655caeb5042">USB_OTG_DIEPMSK_EPDM_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaf33e7f717470ec3ffbaf5655caeb5042"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f93bf9a17e71b2f6d82c485ec81c464" id="r_ga5f93bf9a17e71b2f6d82c485ec81c464"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f93bf9a17e71b2f6d82c485ec81c464">USB_OTG_DIEPMSK_EPDM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf33e7f717470ec3ffbaf5655caeb5042">USB_OTG_DIEPMSK_EPDM_Pos</a>)</td></tr>
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<tr class="separator:ga5f93bf9a17e71b2f6d82c485ec81c464"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd42de5994316c7c765e349aceaf1718" id="r_gafd42de5994316c7c765e349aceaf1718"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd42de5994316c7c765e349aceaf1718">USB_OTG_DIEPMSK_EPDM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f93bf9a17e71b2f6d82c485ec81c464">USB_OTG_DIEPMSK_EPDM_Msk</a></td></tr>
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<tr class="separator:gafd42de5994316c7c765e349aceaf1718"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23c48c84904e681f9f973b9e102dd45b" id="r_ga23c48c84904e681f9f973b9e102dd45b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23c48c84904e681f9f973b9e102dd45b">USB_OTG_DIEPMSK_TOM_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga23c48c84904e681f9f973b9e102dd45b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3ef8fc38aa3179714c5ac82ac381e94" id="r_gae3ef8fc38aa3179714c5ac82ac381e94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3ef8fc38aa3179714c5ac82ac381e94">USB_OTG_DIEPMSK_TOM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga23c48c84904e681f9f973b9e102dd45b">USB_OTG_DIEPMSK_TOM_Pos</a>)</td></tr>
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<tr class="separator:gae3ef8fc38aa3179714c5ac82ac381e94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7329fbd5f4d78564704e80cbdcfb6a8f" id="r_ga7329fbd5f4d78564704e80cbdcfb6a8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7329fbd5f4d78564704e80cbdcfb6a8f">USB_OTG_DIEPMSK_TOM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae3ef8fc38aa3179714c5ac82ac381e94">USB_OTG_DIEPMSK_TOM_Msk</a></td></tr>
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<tr class="separator:ga7329fbd5f4d78564704e80cbdcfb6a8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8b2199466036aae72f41437ca8d12305" id="r_ga8b2199466036aae72f41437ca8d12305"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8b2199466036aae72f41437ca8d12305">USB_OTG_DIEPMSK_ITTXFEMSK_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga8b2199466036aae72f41437ca8d12305"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa7c9ebfa6013f1aed7b853573298a0a" id="r_gafa7c9ebfa6013f1aed7b853573298a0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa7c9ebfa6013f1aed7b853573298a0a">USB_OTG_DIEPMSK_ITTXFEMSK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b2199466036aae72f41437ca8d12305">USB_OTG_DIEPMSK_ITTXFEMSK_Pos</a>)</td></tr>
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<tr class="separator:gafa7c9ebfa6013f1aed7b853573298a0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52a6c7819bcf9554d7f20c9ba4ad99dd" id="r_ga52a6c7819bcf9554d7f20c9ba4ad99dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52a6c7819bcf9554d7f20c9ba4ad99dd">USB_OTG_DIEPMSK_ITTXFEMSK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafa7c9ebfa6013f1aed7b853573298a0a">USB_OTG_DIEPMSK_ITTXFEMSK_Msk</a></td></tr>
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<tr class="separator:ga52a6c7819bcf9554d7f20c9ba4ad99dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e89f316e156b4d99a97be6c55c697ef" id="r_ga4e89f316e156b4d99a97be6c55c697ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e89f316e156b4d99a97be6c55c697ef">USB_OTG_DIEPMSK_INEPNMM_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga4e89f316e156b4d99a97be6c55c697ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9558bbbb276b63f32baf0dc2c9e37a87" id="r_ga9558bbbb276b63f32baf0dc2c9e37a87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9558bbbb276b63f32baf0dc2c9e37a87">USB_OTG_DIEPMSK_INEPNMM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e89f316e156b4d99a97be6c55c697ef">USB_OTG_DIEPMSK_INEPNMM_Pos</a>)</td></tr>
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<tr class="separator:ga9558bbbb276b63f32baf0dc2c9e37a87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34f85531f0e6f963d30dbc284c23fb92" id="r_ga34f85531f0e6f963d30dbc284c23fb92"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34f85531f0e6f963d30dbc284c23fb92">USB_OTG_DIEPMSK_INEPNMM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9558bbbb276b63f32baf0dc2c9e37a87">USB_OTG_DIEPMSK_INEPNMM_Msk</a></td></tr>
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<tr class="separator:ga34f85531f0e6f963d30dbc284c23fb92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62f0c997d4ec1a2a00c07963d66f4a19" id="r_ga62f0c997d4ec1a2a00c07963d66f4a19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62f0c997d4ec1a2a00c07963d66f4a19">USB_OTG_DIEPMSK_INEPNEM_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga62f0c997d4ec1a2a00c07963d66f4a19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4413974123f59fa698d3f79b8218016" id="r_gac4413974123f59fa698d3f79b8218016"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4413974123f59fa698d3f79b8218016">USB_OTG_DIEPMSK_INEPNEM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga62f0c997d4ec1a2a00c07963d66f4a19">USB_OTG_DIEPMSK_INEPNEM_Pos</a>)</td></tr>
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<tr class="separator:gac4413974123f59fa698d3f79b8218016"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26a366ee28afa322e37670c3eb5d0722" id="r_ga26a366ee28afa322e37670c3eb5d0722"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26a366ee28afa322e37670c3eb5d0722">USB_OTG_DIEPMSK_INEPNEM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac4413974123f59fa698d3f79b8218016">USB_OTG_DIEPMSK_INEPNEM_Msk</a></td></tr>
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<tr class="separator:ga26a366ee28afa322e37670c3eb5d0722"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a917fb1c83934de74f903f2d5fb68ae" id="r_ga1a917fb1c83934de74f903f2d5fb68ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a917fb1c83934de74f903f2d5fb68ae">USB_OTG_DIEPMSK_TXFURM_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga1a917fb1c83934de74f903f2d5fb68ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e7e1dc554fdd79e23762aac9e2338b0" id="r_ga3e7e1dc554fdd79e23762aac9e2338b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e7e1dc554fdd79e23762aac9e2338b0">USB_OTG_DIEPMSK_TXFURM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1a917fb1c83934de74f903f2d5fb68ae">USB_OTG_DIEPMSK_TXFURM_Pos</a>)</td></tr>
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<tr class="separator:ga3e7e1dc554fdd79e23762aac9e2338b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d10ab688d3bf47aaf8180daf0624e9d" id="r_ga8d10ab688d3bf47aaf8180daf0624e9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d10ab688d3bf47aaf8180daf0624e9d">USB_OTG_DIEPMSK_TXFURM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e7e1dc554fdd79e23762aac9e2338b0">USB_OTG_DIEPMSK_TXFURM_Msk</a></td></tr>
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<tr class="separator:ga8d10ab688d3bf47aaf8180daf0624e9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16c9b6bfc32bc4fe2109567cc99efc3d" id="r_ga16c9b6bfc32bc4fe2109567cc99efc3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16c9b6bfc32bc4fe2109567cc99efc3d">USB_OTG_DIEPMSK_BIM_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga16c9b6bfc32bc4fe2109567cc99efc3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf510f548548201cdaef6370c77bd644" id="r_gaaf510f548548201cdaef6370c77bd644"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf510f548548201cdaef6370c77bd644">USB_OTG_DIEPMSK_BIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga16c9b6bfc32bc4fe2109567cc99efc3d">USB_OTG_DIEPMSK_BIM_Pos</a>)</td></tr>
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<tr class="separator:gaaf510f548548201cdaef6370c77bd644"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2dd5dbb2c67a3dd71a8fe6563441d243" id="r_ga2dd5dbb2c67a3dd71a8fe6563441d243"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dd5dbb2c67a3dd71a8fe6563441d243">USB_OTG_DIEPMSK_BIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf510f548548201cdaef6370c77bd644">USB_OTG_DIEPMSK_BIM_Msk</a></td></tr>
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<tr class="separator:ga2dd5dbb2c67a3dd71a8fe6563441d243"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a6aedb1b39e4e5adaacbc690e30515a" id="r_ga4a6aedb1b39e4e5adaacbc690e30515a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a6aedb1b39e4e5adaacbc690e30515a">USB_OTG_HPTXSTS_PTXFSAVL_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4a6aedb1b39e4e5adaacbc690e30515a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab49ec3e222a628b813a802f9ebb28448" id="r_gab49ec3e222a628b813a802f9ebb28448"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab49ec3e222a628b813a802f9ebb28448">USB_OTG_HPTXSTS_PTXFSAVL_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4a6aedb1b39e4e5adaacbc690e30515a">USB_OTG_HPTXSTS_PTXFSAVL_Pos</a>)</td></tr>
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<tr class="separator:gab49ec3e222a628b813a802f9ebb28448"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab37734d4115211633d584e59cbeabe19" id="r_gab37734d4115211633d584e59cbeabe19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab37734d4115211633d584e59cbeabe19">USB_OTG_HPTXSTS_PTXFSAVL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab49ec3e222a628b813a802f9ebb28448">USB_OTG_HPTXSTS_PTXFSAVL_Msk</a></td></tr>
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<tr class="separator:gab37734d4115211633d584e59cbeabe19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad838ab2d271e69a85003600c33fa636e" id="r_gad838ab2d271e69a85003600c33fa636e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">USB_OTG_HPTXSTS_PTXQSAV_Pos</a>   (16U)</td></tr>
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<tr class="separator:gad838ab2d271e69a85003600c33fa636e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57a34e5dc4826091ab53667fa1d0d6d7" id="r_ga57a34e5dc4826091ab53667fa1d0d6d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga57a34e5dc4826091ab53667fa1d0d6d7">USB_OTG_HPTXSTS_PTXQSAV_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">USB_OTG_HPTXSTS_PTXQSAV_Pos</a>)</td></tr>
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<tr class="separator:ga57a34e5dc4826091ab53667fa1d0d6d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga338e5e7a3613da0d1dbca7bcdced15ca" id="r_ga338e5e7a3613da0d1dbca7bcdced15ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga338e5e7a3613da0d1dbca7bcdced15ca">USB_OTG_HPTXSTS_PTXQSAV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga57a34e5dc4826091ab53667fa1d0d6d7">USB_OTG_HPTXSTS_PTXQSAV_Msk</a></td></tr>
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<tr class="separator:ga338e5e7a3613da0d1dbca7bcdced15ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0029668daec1137fa7373e7b151099ac" id="r_ga0029668daec1137fa7373e7b151099ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0029668daec1137fa7373e7b151099ac">USB_OTG_HPTXSTS_PTXQSAV_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">USB_OTG_HPTXSTS_PTXQSAV_Pos</a>)</td></tr>
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<tr class="separator:ga0029668daec1137fa7373e7b151099ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96badb4855acc006656a4045db4170f2" id="r_ga96badb4855acc006656a4045db4170f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96badb4855acc006656a4045db4170f2">USB_OTG_HPTXSTS_PTXQSAV_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">USB_OTG_HPTXSTS_PTXQSAV_Pos</a>)</td></tr>
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<tr class="memitem:ga51e29269f12dd3a01bdccd31b5fefcdf" id="r_ga51e29269f12dd3a01bdccd31b5fefcdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51e29269f12dd3a01bdccd31b5fefcdf">USB_OTG_HPTXSTS_PTXQSAV_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">USB_OTG_HPTXSTS_PTXQSAV_Pos</a>)</td></tr>
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<tr class="separator:ga51e29269f12dd3a01bdccd31b5fefcdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac36241d1f9e6a781b55952f6ae8ca4ea" id="r_gac36241d1f9e6a781b55952f6ae8ca4ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac36241d1f9e6a781b55952f6ae8ca4ea">USB_OTG_HPTXSTS_PTXQSAV_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">USB_OTG_HPTXSTS_PTXQSAV_Pos</a>)</td></tr>
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<tr class="separator:gac36241d1f9e6a781b55952f6ae8ca4ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccf8f748b5a048fd46fc3c710daddf2a" id="r_gaccf8f748b5a048fd46fc3c710daddf2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccf8f748b5a048fd46fc3c710daddf2a">USB_OTG_HPTXSTS_PTXQSAV_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">USB_OTG_HPTXSTS_PTXQSAV_Pos</a>)</td></tr>
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<tr class="separator:gaccf8f748b5a048fd46fc3c710daddf2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac0ab79df9fad1b945edb6384dbc8e3d" id="r_gaac0ab79df9fad1b945edb6384dbc8e3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac0ab79df9fad1b945edb6384dbc8e3d">USB_OTG_HPTXSTS_PTXQSAV_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">USB_OTG_HPTXSTS_PTXQSAV_Pos</a>)</td></tr>
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<tr class="separator:gaac0ab79df9fad1b945edb6384dbc8e3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba458280e9d6532dd12837a90742f408" id="r_gaba458280e9d6532dd12837a90742f408"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba458280e9d6532dd12837a90742f408">USB_OTG_HPTXSTS_PTXQSAV_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">USB_OTG_HPTXSTS_PTXQSAV_Pos</a>)</td></tr>
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<tr class="separator:gaba458280e9d6532dd12837a90742f408"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga873ee2b3f86e357de46cd936a899ed31" id="r_ga873ee2b3f86e357de46cd936a899ed31"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga873ee2b3f86e357de46cd936a899ed31">USB_OTG_HPTXSTS_PTXQSAV_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">USB_OTG_HPTXSTS_PTXQSAV_Pos</a>)</td></tr>
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<tr class="separator:ga873ee2b3f86e357de46cd936a899ed31"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a19e1bb99e39af155bffbdaed9f001d" id="r_ga6a19e1bb99e39af155bffbdaed9f001d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d">USB_OTG_HPTXSTS_PTXQTOP_Pos</a>   (24U)</td></tr>
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<tr class="separator:ga6a19e1bb99e39af155bffbdaed9f001d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4378a888dfbf5185446cdf184521471b" id="r_ga4378a888dfbf5185446cdf184521471b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4378a888dfbf5185446cdf184521471b">USB_OTG_HPTXSTS_PTXQTOP_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d">USB_OTG_HPTXSTS_PTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:ga4378a888dfbf5185446cdf184521471b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c9381ee78a71b8c91e76a974fd633f1" id="r_ga4c9381ee78a71b8c91e76a974fd633f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c9381ee78a71b8c91e76a974fd633f1">USB_OTG_HPTXSTS_PTXQTOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4378a888dfbf5185446cdf184521471b">USB_OTG_HPTXSTS_PTXQTOP_Msk</a></td></tr>
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<tr class="separator:ga4c9381ee78a71b8c91e76a974fd633f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc4f9d82388f22aedd70ffc2074f8526" id="r_gadc4f9d82388f22aedd70ffc2074f8526"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc4f9d82388f22aedd70ffc2074f8526">USB_OTG_HPTXSTS_PTXQTOP_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d">USB_OTG_HPTXSTS_PTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:gadc4f9d82388f22aedd70ffc2074f8526"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b75ae59aa46eb3f366e0c0eb18a953e" id="r_ga4b75ae59aa46eb3f366e0c0eb18a953e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b75ae59aa46eb3f366e0c0eb18a953e">USB_OTG_HPTXSTS_PTXQTOP_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d">USB_OTG_HPTXSTS_PTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:ga4b75ae59aa46eb3f366e0c0eb18a953e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49c079a1cad8c676ff57e997fddcc939" id="r_ga49c079a1cad8c676ff57e997fddcc939"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49c079a1cad8c676ff57e997fddcc939">USB_OTG_HPTXSTS_PTXQTOP_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d">USB_OTG_HPTXSTS_PTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:ga49c079a1cad8c676ff57e997fddcc939"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37f71961a65f5c88a0bcfea71c88bfab" id="r_ga37f71961a65f5c88a0bcfea71c88bfab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37f71961a65f5c88a0bcfea71c88bfab">USB_OTG_HPTXSTS_PTXQTOP_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d">USB_OTG_HPTXSTS_PTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:ga37f71961a65f5c88a0bcfea71c88bfab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10291d16c7f539b1fb2d6e0b22fd7cbf" id="r_ga10291d16c7f539b1fb2d6e0b22fd7cbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga10291d16c7f539b1fb2d6e0b22fd7cbf">USB_OTG_HPTXSTS_PTXQTOP_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d">USB_OTG_HPTXSTS_PTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:ga10291d16c7f539b1fb2d6e0b22fd7cbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8bac7d58ce0353c4570601a5a8c04090" id="r_ga8bac7d58ce0353c4570601a5a8c04090"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8bac7d58ce0353c4570601a5a8c04090">USB_OTG_HPTXSTS_PTXQTOP_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d">USB_OTG_HPTXSTS_PTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:ga8bac7d58ce0353c4570601a5a8c04090"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga164af5e3ff7a7c104028840b5ccb8447" id="r_ga164af5e3ff7a7c104028840b5ccb8447"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga164af5e3ff7a7c104028840b5ccb8447">USB_OTG_HPTXSTS_PTXQTOP_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d">USB_OTG_HPTXSTS_PTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:ga164af5e3ff7a7c104028840b5ccb8447"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad66e43fdfea8df808ae46b41537c5b0a" id="r_gad66e43fdfea8df808ae46b41537c5b0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad66e43fdfea8df808ae46b41537c5b0a">USB_OTG_HPTXSTS_PTXQTOP_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d">USB_OTG_HPTXSTS_PTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:gad66e43fdfea8df808ae46b41537c5b0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb914e0dfd6e2f21aa41ce6e2ac289bf" id="r_gabb914e0dfd6e2f21aa41ce6e2ac289bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb914e0dfd6e2f21aa41ce6e2ac289bf">USB_OTG_HAINT_HAINT_Pos</a>   (0U)</td></tr>
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<tr class="separator:gabb914e0dfd6e2f21aa41ce6e2ac289bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d40f68bf4ce28cec78ad449152f16e2" id="r_ga6d40f68bf4ce28cec78ad449152f16e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d40f68bf4ce28cec78ad449152f16e2">USB_OTG_HAINT_HAINT_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb914e0dfd6e2f21aa41ce6e2ac289bf">USB_OTG_HAINT_HAINT_Pos</a>)</td></tr>
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<tr class="separator:ga6d40f68bf4ce28cec78ad449152f16e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13f6ce630f54df1a49314012a612d98d" id="r_ga13f6ce630f54df1a49314012a612d98d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13f6ce630f54df1a49314012a612d98d">USB_OTG_HAINT_HAINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d40f68bf4ce28cec78ad449152f16e2">USB_OTG_HAINT_HAINT_Msk</a></td></tr>
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<tr class="separator:ga13f6ce630f54df1a49314012a612d98d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6f7cf9e1a76b015dd90de4a3d5b3c2c" id="r_gaf6f7cf9e1a76b015dd90de4a3d5b3c2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf6f7cf9e1a76b015dd90de4a3d5b3c2c">USB_OTG_DOEPMSK_XFRCM_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaf6f7cf9e1a76b015dd90de4a3d5b3c2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga722790431dd642e348bcded588d7e824" id="r_ga722790431dd642e348bcded588d7e824"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga722790431dd642e348bcded588d7e824">USB_OTG_DOEPMSK_XFRCM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf6f7cf9e1a76b015dd90de4a3d5b3c2c">USB_OTG_DOEPMSK_XFRCM_Pos</a>)</td></tr>
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<tr class="separator:ga722790431dd642e348bcded588d7e824"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9e4371d47a5b0cfcc1235fbb9fbd7931" id="r_ga9e4371d47a5b0cfcc1235fbb9fbd7931"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9e4371d47a5b0cfcc1235fbb9fbd7931">USB_OTG_DOEPMSK_XFRCM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga722790431dd642e348bcded588d7e824">USB_OTG_DOEPMSK_XFRCM_Msk</a></td></tr>
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<tr class="separator:ga9e4371d47a5b0cfcc1235fbb9fbd7931"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b5c2c8efd16702ac54250eef9e71f5f" id="r_ga7b5c2c8efd16702ac54250eef9e71f5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7b5c2c8efd16702ac54250eef9e71f5f">USB_OTG_DOEPMSK_EPDM_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga7b5c2c8efd16702ac54250eef9e71f5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3b3d4b03a79afdb9c3a5b9e40d07158" id="r_gab3b3d4b03a79afdb9c3a5b9e40d07158"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3b3d4b03a79afdb9c3a5b9e40d07158">USB_OTG_DOEPMSK_EPDM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7b5c2c8efd16702ac54250eef9e71f5f">USB_OTG_DOEPMSK_EPDM_Pos</a>)</td></tr>
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<tr class="separator:gab3b3d4b03a79afdb9c3a5b9e40d07158"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6078d0855016e26c85d0a5b935e6f6ba" id="r_ga6078d0855016e26c85d0a5b935e6f6ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6078d0855016e26c85d0a5b935e6f6ba">USB_OTG_DOEPMSK_EPDM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab3b3d4b03a79afdb9c3a5b9e40d07158">USB_OTG_DOEPMSK_EPDM_Msk</a></td></tr>
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<tr class="separator:ga6078d0855016e26c85d0a5b935e6f6ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cee72a98e75f37cc4e9c71002ed9e74" id="r_ga3cee72a98e75f37cc4e9c71002ed9e74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3cee72a98e75f37cc4e9c71002ed9e74">USB_OTG_DOEPMSK_AHBERRM_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga3cee72a98e75f37cc4e9c71002ed9e74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaec4375fe9d10b890e84c603398653dbd" id="r_gaec4375fe9d10b890e84c603398653dbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaec4375fe9d10b890e84c603398653dbd">USB_OTG_DOEPMSK_AHBERRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3cee72a98e75f37cc4e9c71002ed9e74">USB_OTG_DOEPMSK_AHBERRM_Pos</a>)</td></tr>
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<tr class="separator:gaec4375fe9d10b890e84c603398653dbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafc5eeb0500ce7832cf607829de07dc06" id="r_gafc5eeb0500ce7832cf607829de07dc06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafc5eeb0500ce7832cf607829de07dc06">USB_OTG_DOEPMSK_AHBERRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaec4375fe9d10b890e84c603398653dbd">USB_OTG_DOEPMSK_AHBERRM_Msk</a></td></tr>
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<tr class="separator:gafc5eeb0500ce7832cf607829de07dc06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cc448d81a686805e6929bfa1b0733a0" id="r_ga7cc448d81a686805e6929bfa1b0733a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cc448d81a686805e6929bfa1b0733a0">USB_OTG_DOEPMSK_STUPM_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga7cc448d81a686805e6929bfa1b0733a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafccb9d1a7a0af8c8ed2be97eff94a8d1" id="r_gafccb9d1a7a0af8c8ed2be97eff94a8d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafccb9d1a7a0af8c8ed2be97eff94a8d1">USB_OTG_DOEPMSK_STUPM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cc448d81a686805e6929bfa1b0733a0">USB_OTG_DOEPMSK_STUPM_Pos</a>)</td></tr>
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<tr class="separator:gafccb9d1a7a0af8c8ed2be97eff94a8d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb61e805f1e512b80a7b33efcca6182e" id="r_gabb61e805f1e512b80a7b33efcca6182e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb61e805f1e512b80a7b33efcca6182e">USB_OTG_DOEPMSK_STUPM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafccb9d1a7a0af8c8ed2be97eff94a8d1">USB_OTG_DOEPMSK_STUPM_Msk</a></td></tr>
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<tr class="memitem:ga71b98d5a957803fef609dcc8ce29e5e7" id="r_ga71b98d5a957803fef609dcc8ce29e5e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71b98d5a957803fef609dcc8ce29e5e7">USB_OTG_DOEPMSK_OTEPDM_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga71b98d5a957803fef609dcc8ce29e5e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7df1cf9a2583c2a2c079c2743db0c0a" id="r_gae7df1cf9a2583c2a2c079c2743db0c0a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7df1cf9a2583c2a2c079c2743db0c0a">USB_OTG_DOEPMSK_OTEPDM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga71b98d5a957803fef609dcc8ce29e5e7">USB_OTG_DOEPMSK_OTEPDM_Pos</a>)</td></tr>
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<tr class="separator:gae7df1cf9a2583c2a2c079c2743db0c0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad472667f09c79f0ca122586ae032e9df" id="r_gad472667f09c79f0ca122586ae032e9df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad472667f09c79f0ca122586ae032e9df">USB_OTG_DOEPMSK_OTEPDM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae7df1cf9a2583c2a2c079c2743db0c0a">USB_OTG_DOEPMSK_OTEPDM_Msk</a></td></tr>
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<tr class="separator:gad472667f09c79f0ca122586ae032e9df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae44f78310897990a88aaef41fb7e0ec3" id="r_gae44f78310897990a88aaef41fb7e0ec3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae44f78310897990a88aaef41fb7e0ec3">USB_OTG_DOEPMSK_OTEPSPRM_Pos</a>   (5U)</td></tr>
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<tr class="separator:gae44f78310897990a88aaef41fb7e0ec3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2715f06a8df58db51a00016f761d6b0" id="r_gaf2715f06a8df58db51a00016f761d6b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2715f06a8df58db51a00016f761d6b0">USB_OTG_DOEPMSK_OTEPSPRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae44f78310897990a88aaef41fb7e0ec3">USB_OTG_DOEPMSK_OTEPSPRM_Pos</a>)</td></tr>
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<tr class="separator:gaf2715f06a8df58db51a00016f761d6b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22b959b8d57d5bace18e35d95de09a77" id="r_ga22b959b8d57d5bace18e35d95de09a77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22b959b8d57d5bace18e35d95de09a77">USB_OTG_DOEPMSK_OTEPSPRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2715f06a8df58db51a00016f761d6b0">USB_OTG_DOEPMSK_OTEPSPRM_Msk</a></td></tr>
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<tr class="separator:ga22b959b8d57d5bace18e35d95de09a77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab4e6b15ce4e8b36a49a8e46d6354ab2" id="r_gaab4e6b15ce4e8b36a49a8e46d6354ab2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab4e6b15ce4e8b36a49a8e46d6354ab2">USB_OTG_DOEPMSK_B2BSTUP_Pos</a>   (6U)</td></tr>
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<tr class="separator:gaab4e6b15ce4e8b36a49a8e46d6354ab2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga990e43476d2858b9b8b0a1e10ddd3ca1" id="r_ga990e43476d2858b9b8b0a1e10ddd3ca1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga990e43476d2858b9b8b0a1e10ddd3ca1">USB_OTG_DOEPMSK_B2BSTUP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab4e6b15ce4e8b36a49a8e46d6354ab2">USB_OTG_DOEPMSK_B2BSTUP_Pos</a>)</td></tr>
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<tr class="separator:ga990e43476d2858b9b8b0a1e10ddd3ca1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59ef878371c32d6157a619ec42144c09" id="r_ga59ef878371c32d6157a619ec42144c09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga59ef878371c32d6157a619ec42144c09">USB_OTG_DOEPMSK_B2BSTUP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga990e43476d2858b9b8b0a1e10ddd3ca1">USB_OTG_DOEPMSK_B2BSTUP_Msk</a></td></tr>
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<tr class="separator:ga59ef878371c32d6157a619ec42144c09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5e214436522dcf78ba7057e0cd9e463" id="r_gaf5e214436522dcf78ba7057e0cd9e463"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5e214436522dcf78ba7057e0cd9e463">USB_OTG_DOEPMSK_OPEM_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaf5e214436522dcf78ba7057e0cd9e463"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf413b92fd7377313378c481fbf28c6f0" id="r_gaf413b92fd7377313378c481fbf28c6f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf413b92fd7377313378c481fbf28c6f0">USB_OTG_DOEPMSK_OPEM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5e214436522dcf78ba7057e0cd9e463">USB_OTG_DOEPMSK_OPEM_Pos</a>)</td></tr>
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<tr class="separator:gaf413b92fd7377313378c481fbf28c6f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26bf486957377a746a55ae6203ea697c" id="r_ga26bf486957377a746a55ae6203ea697c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26bf486957377a746a55ae6203ea697c">USB_OTG_DOEPMSK_OPEM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf413b92fd7377313378c481fbf28c6f0">USB_OTG_DOEPMSK_OPEM_Msk</a></td></tr>
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<tr class="separator:ga26bf486957377a746a55ae6203ea697c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf13c76bdd8af0056459a0ec9e8b38a50" id="r_gaf13c76bdd8af0056459a0ec9e8b38a50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf13c76bdd8af0056459a0ec9e8b38a50">USB_OTG_DOEPMSK_BOIM_Pos</a>   (9U)</td></tr>
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<tr class="separator:gaf13c76bdd8af0056459a0ec9e8b38a50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa93f1e928648830df23013e8868ed53a" id="r_gaa93f1e928648830df23013e8868ed53a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa93f1e928648830df23013e8868ed53a">USB_OTG_DOEPMSK_BOIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf13c76bdd8af0056459a0ec9e8b38a50">USB_OTG_DOEPMSK_BOIM_Pos</a>)</td></tr>
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<tr class="separator:gaa93f1e928648830df23013e8868ed53a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga980f37cfb000d12f7752530986d5069c" id="r_ga980f37cfb000d12f7752530986d5069c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga980f37cfb000d12f7752530986d5069c">USB_OTG_DOEPMSK_BOIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa93f1e928648830df23013e8868ed53a">USB_OTG_DOEPMSK_BOIM_Msk</a></td></tr>
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<tr class="separator:ga980f37cfb000d12f7752530986d5069c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f60404d296c1b736ed763904914bbc4" id="r_ga4f60404d296c1b736ed763904914bbc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f60404d296c1b736ed763904914bbc4">USB_OTG_DOEPMSK_BERRM_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga4f60404d296c1b736ed763904914bbc4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad22af854eb20c0c8f6c718703aa06cc" id="r_gaad22af854eb20c0c8f6c718703aa06cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaad22af854eb20c0c8f6c718703aa06cc">USB_OTG_DOEPMSK_BERRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f60404d296c1b736ed763904914bbc4">USB_OTG_DOEPMSK_BERRM_Pos</a>)</td></tr>
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<tr class="separator:gaad22af854eb20c0c8f6c718703aa06cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaac35f8747cd753d8534cfd8d6f4e6f2" id="r_gaaac35f8747cd753d8534cfd8d6f4e6f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaac35f8747cd753d8534cfd8d6f4e6f2">USB_OTG_DOEPMSK_BERRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaad22af854eb20c0c8f6c718703aa06cc">USB_OTG_DOEPMSK_BERRM_Msk</a></td></tr>
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<tr class="separator:gaaac35f8747cd753d8534cfd8d6f4e6f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga849d7e79fa347faa484a293e99337c37" id="r_ga849d7e79fa347faa484a293e99337c37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga849d7e79fa347faa484a293e99337c37">USB_OTG_DOEPMSK_NAKM_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga849d7e79fa347faa484a293e99337c37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4282f15a3f24294c3de271447aa0b53a" id="r_ga4282f15a3f24294c3de271447aa0b53a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4282f15a3f24294c3de271447aa0b53a">USB_OTG_DOEPMSK_NAKM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga849d7e79fa347faa484a293e99337c37">USB_OTG_DOEPMSK_NAKM_Pos</a>)</td></tr>
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<tr class="separator:ga4282f15a3f24294c3de271447aa0b53a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga377812e187288777184fec2d96929ac3" id="r_ga377812e187288777184fec2d96929ac3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga377812e187288777184fec2d96929ac3">USB_OTG_DOEPMSK_NAKM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4282f15a3f24294c3de271447aa0b53a">USB_OTG_DOEPMSK_NAKM_Msk</a></td></tr>
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<tr class="separator:ga377812e187288777184fec2d96929ac3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60d3e6971b726ef17a4f7518838813b5" id="r_ga60d3e6971b726ef17a4f7518838813b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60d3e6971b726ef17a4f7518838813b5">USB_OTG_DOEPMSK_NYETM_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga60d3e6971b726ef17a4f7518838813b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7d2f79cc4d6c27cc7d24cc63b2103d0" id="r_gaa7d2f79cc4d6c27cc7d24cc63b2103d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7d2f79cc4d6c27cc7d24cc63b2103d0">USB_OTG_DOEPMSK_NYETM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga60d3e6971b726ef17a4f7518838813b5">USB_OTG_DOEPMSK_NYETM_Pos</a>)</td></tr>
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<tr class="separator:gaa7d2f79cc4d6c27cc7d24cc63b2103d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a60db81ca4a7ab4ce864d70c5235498" id="r_ga1a60db81ca4a7ab4ce864d70c5235498"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a60db81ca4a7ab4ce864d70c5235498">USB_OTG_DOEPMSK_NYETM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7d2f79cc4d6c27cc7d24cc63b2103d0">USB_OTG_DOEPMSK_NYETM_Msk</a></td></tr>
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<tr class="separator:ga1a60db81ca4a7ab4ce864d70c5235498"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd85c4ebf2f92718d17fe2d03542046a" id="r_gacd85c4ebf2f92718d17fe2d03542046a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd85c4ebf2f92718d17fe2d03542046a">USB_OTG_GINTSTS_CMOD_Pos</a>   (0U)</td></tr>
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<tr class="separator:gacd85c4ebf2f92718d17fe2d03542046a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac38b6e32c779099c6cdba55e857f33e0" id="r_gac38b6e32c779099c6cdba55e857f33e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac38b6e32c779099c6cdba55e857f33e0">USB_OTG_GINTSTS_CMOD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacd85c4ebf2f92718d17fe2d03542046a">USB_OTG_GINTSTS_CMOD_Pos</a>)</td></tr>
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<tr class="separator:gac38b6e32c779099c6cdba55e857f33e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga357496f2734867ddaf5a00cc61ff0191" id="r_ga357496f2734867ddaf5a00cc61ff0191"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga357496f2734867ddaf5a00cc61ff0191">USB_OTG_GINTSTS_CMOD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac38b6e32c779099c6cdba55e857f33e0">USB_OTG_GINTSTS_CMOD_Msk</a></td></tr>
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<tr class="separator:ga357496f2734867ddaf5a00cc61ff0191"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabeb493e86d2c0348c72313101d37d35" id="r_gaabeb493e86d2c0348c72313101d37d35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabeb493e86d2c0348c72313101d37d35">USB_OTG_GINTSTS_MMIS_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaabeb493e86d2c0348c72313101d37d35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6421c9e8b57f5343e197c85008ae82d5" id="r_ga6421c9e8b57f5343e197c85008ae82d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6421c9e8b57f5343e197c85008ae82d5">USB_OTG_GINTSTS_MMIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaabeb493e86d2c0348c72313101d37d35">USB_OTG_GINTSTS_MMIS_Pos</a>)</td></tr>
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<tr class="separator:ga6421c9e8b57f5343e197c85008ae82d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0c1ac0fa6a6a1b95d1dfc2b90383a39" id="r_gab0c1ac0fa6a6a1b95d1dfc2b90383a39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab0c1ac0fa6a6a1b95d1dfc2b90383a39">USB_OTG_GINTSTS_MMIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6421c9e8b57f5343e197c85008ae82d5">USB_OTG_GINTSTS_MMIS_Msk</a></td></tr>
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<tr class="separator:gab0c1ac0fa6a6a1b95d1dfc2b90383a39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaea398db5607b71a1f2502cf2070114b3" id="r_gaea398db5607b71a1f2502cf2070114b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaea398db5607b71a1f2502cf2070114b3">USB_OTG_GINTSTS_OTGINT_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaea398db5607b71a1f2502cf2070114b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7154d80c30c1c71720c35ce47aed996b" id="r_ga7154d80c30c1c71720c35ce47aed996b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7154d80c30c1c71720c35ce47aed996b">USB_OTG_GINTSTS_OTGINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaea398db5607b71a1f2502cf2070114b3">USB_OTG_GINTSTS_OTGINT_Pos</a>)</td></tr>
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<tr class="separator:ga7154d80c30c1c71720c35ce47aed996b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a7ff1e46bfa5481522003726a1b6304" id="r_ga4a7ff1e46bfa5481522003726a1b6304"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4a7ff1e46bfa5481522003726a1b6304">USB_OTG_GINTSTS_OTGINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7154d80c30c1c71720c35ce47aed996b">USB_OTG_GINTSTS_OTGINT_Msk</a></td></tr>
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<tr class="separator:ga4a7ff1e46bfa5481522003726a1b6304"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga241c59b3b0a4716cdfeae02bee7ee6f7" id="r_ga241c59b3b0a4716cdfeae02bee7ee6f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga241c59b3b0a4716cdfeae02bee7ee6f7">USB_OTG_GINTSTS_SOF_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga241c59b3b0a4716cdfeae02bee7ee6f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga574b32ff2365c138b8454bec261a44e5" id="r_ga574b32ff2365c138b8454bec261a44e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga574b32ff2365c138b8454bec261a44e5">USB_OTG_GINTSTS_SOF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga241c59b3b0a4716cdfeae02bee7ee6f7">USB_OTG_GINTSTS_SOF_Pos</a>)</td></tr>
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<tr class="separator:ga574b32ff2365c138b8454bec261a44e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga478373e0aea76bfad1c9d8e93c33a2f8" id="r_ga478373e0aea76bfad1c9d8e93c33a2f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga478373e0aea76bfad1c9d8e93c33a2f8">USB_OTG_GINTSTS_SOF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga574b32ff2365c138b8454bec261a44e5">USB_OTG_GINTSTS_SOF_Msk</a></td></tr>
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<tr class="separator:ga478373e0aea76bfad1c9d8e93c33a2f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b883fbb67ff958f65920e91e1bef891" id="r_ga0b883fbb67ff958f65920e91e1bef891"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b883fbb67ff958f65920e91e1bef891">USB_OTG_GINTSTS_RXFLVL_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga0b883fbb67ff958f65920e91e1bef891"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7fb089db587ace41b14385dda34247e5" id="r_ga7fb089db587ace41b14385dda34247e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fb089db587ace41b14385dda34247e5">USB_OTG_GINTSTS_RXFLVL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b883fbb67ff958f65920e91e1bef891">USB_OTG_GINTSTS_RXFLVL_Pos</a>)</td></tr>
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<tr class="separator:ga7fb089db587ace41b14385dda34247e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd7c264becfe7a116ae20933173b1e5b" id="r_gabd7c264becfe7a116ae20933173b1e5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd7c264becfe7a116ae20933173b1e5b">USB_OTG_GINTSTS_RXFLVL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7fb089db587ace41b14385dda34247e5">USB_OTG_GINTSTS_RXFLVL_Msk</a></td></tr>
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<tr class="separator:gabd7c264becfe7a116ae20933173b1e5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga445da8fb063099b3ad27f761ccbb5717" id="r_ga445da8fb063099b3ad27f761ccbb5717"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga445da8fb063099b3ad27f761ccbb5717">USB_OTG_GINTSTS_NPTXFE_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga445da8fb063099b3ad27f761ccbb5717"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga750ef2111fed4186378990d5b4604911" id="r_ga750ef2111fed4186378990d5b4604911"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga750ef2111fed4186378990d5b4604911">USB_OTG_GINTSTS_NPTXFE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga445da8fb063099b3ad27f761ccbb5717">USB_OTG_GINTSTS_NPTXFE_Pos</a>)</td></tr>
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<tr class="separator:ga750ef2111fed4186378990d5b4604911"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa84f417f4c311418505bcd04e6b9cbdf" id="r_gaa84f417f4c311418505bcd04e6b9cbdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa84f417f4c311418505bcd04e6b9cbdf">USB_OTG_GINTSTS_NPTXFE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga750ef2111fed4186378990d5b4604911">USB_OTG_GINTSTS_NPTXFE_Msk</a></td></tr>
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<tr class="separator:gaa84f417f4c311418505bcd04e6b9cbdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99b72bc7ac0386f0db4fe4525c29e29a" id="r_ga99b72bc7ac0386f0db4fe4525c29e29a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99b72bc7ac0386f0db4fe4525c29e29a">USB_OTG_GINTSTS_GINAKEFF_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga99b72bc7ac0386f0db4fe4525c29e29a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac8bce3f4c26db797f4d5bc1fbbf56a3" id="r_gaac8bce3f4c26db797f4d5bc1fbbf56a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac8bce3f4c26db797f4d5bc1fbbf56a3">USB_OTG_GINTSTS_GINAKEFF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga99b72bc7ac0386f0db4fe4525c29e29a">USB_OTG_GINTSTS_GINAKEFF_Pos</a>)</td></tr>
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<tr class="separator:gaac8bce3f4c26db797f4d5bc1fbbf56a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcf16d8b480c90018eaf6a717c989100" id="r_gafcf16d8b480c90018eaf6a717c989100"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcf16d8b480c90018eaf6a717c989100">USB_OTG_GINTSTS_GINAKEFF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaac8bce3f4c26db797f4d5bc1fbbf56a3">USB_OTG_GINTSTS_GINAKEFF_Msk</a></td></tr>
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<tr class="separator:gafcf16d8b480c90018eaf6a717c989100"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga317bd1c94486fbce8c5fad17a0c1a888" id="r_ga317bd1c94486fbce8c5fad17a0c1a888"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga317bd1c94486fbce8c5fad17a0c1a888">USB_OTG_GINTSTS_BOUTNAKEFF_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga317bd1c94486fbce8c5fad17a0c1a888"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2197d4cc945121d9c75d7d9701e64c5" id="r_gad2197d4cc945121d9c75d7d9701e64c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2197d4cc945121d9c75d7d9701e64c5">USB_OTG_GINTSTS_BOUTNAKEFF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga317bd1c94486fbce8c5fad17a0c1a888">USB_OTG_GINTSTS_BOUTNAKEFF_Pos</a>)</td></tr>
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<tr class="separator:gad2197d4cc945121d9c75d7d9701e64c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2966f09bafa5de7b1ee2bbddfc2628fc" id="r_ga2966f09bafa5de7b1ee2bbddfc2628fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2966f09bafa5de7b1ee2bbddfc2628fc">USB_OTG_GINTSTS_BOUTNAKEFF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad2197d4cc945121d9c75d7d9701e64c5">USB_OTG_GINTSTS_BOUTNAKEFF_Msk</a></td></tr>
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<tr class="separator:ga2966f09bafa5de7b1ee2bbddfc2628fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cad1cf9f3eb790549029467955ec3ca" id="r_ga7cad1cf9f3eb790549029467955ec3ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cad1cf9f3eb790549029467955ec3ca">USB_OTG_GINTSTS_ESUSP_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga7cad1cf9f3eb790549029467955ec3ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d506f6959a079205ed975944e8e1189" id="r_ga6d506f6959a079205ed975944e8e1189"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d506f6959a079205ed975944e8e1189">USB_OTG_GINTSTS_ESUSP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cad1cf9f3eb790549029467955ec3ca">USB_OTG_GINTSTS_ESUSP_Pos</a>)</td></tr>
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<tr class="separator:ga6d506f6959a079205ed975944e8e1189"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99d72bb12c0c5bf1d17290c49b392027" id="r_ga99d72bb12c0c5bf1d17290c49b392027"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99d72bb12c0c5bf1d17290c49b392027">USB_OTG_GINTSTS_ESUSP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d506f6959a079205ed975944e8e1189">USB_OTG_GINTSTS_ESUSP_Msk</a></td></tr>
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<tr class="separator:ga99d72bb12c0c5bf1d17290c49b392027"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae44254e287488e465ba70a9a19d1b95a" id="r_gae44254e287488e465ba70a9a19d1b95a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae44254e287488e465ba70a9a19d1b95a">USB_OTG_GINTSTS_USBSUSP_Pos</a>   (11U)</td></tr>
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<tr class="separator:gae44254e287488e465ba70a9a19d1b95a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e012bb063b871af8f27698f652d757d" id="r_ga4e012bb063b871af8f27698f652d757d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e012bb063b871af8f27698f652d757d">USB_OTG_GINTSTS_USBSUSP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae44254e287488e465ba70a9a19d1b95a">USB_OTG_GINTSTS_USBSUSP_Pos</a>)</td></tr>
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<tr class="separator:ga4e012bb063b871af8f27698f652d757d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd16c90192e1c43d95c16265f86cdd5d" id="r_gadd16c90192e1c43d95c16265f86cdd5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd16c90192e1c43d95c16265f86cdd5d">USB_OTG_GINTSTS_USBSUSP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e012bb063b871af8f27698f652d757d">USB_OTG_GINTSTS_USBSUSP_Msk</a></td></tr>
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<tr class="separator:gadd16c90192e1c43d95c16265f86cdd5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf52cb564c30e26f503da97e15c1404cd" id="r_gaf52cb564c30e26f503da97e15c1404cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf52cb564c30e26f503da97e15c1404cd">USB_OTG_GINTSTS_USBRST_Pos</a>   (12U)</td></tr>
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<tr class="separator:gaf52cb564c30e26f503da97e15c1404cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2cc0c061635f5ac73557643af51a1441" id="r_ga2cc0c061635f5ac73557643af51a1441"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2cc0c061635f5ac73557643af51a1441">USB_OTG_GINTSTS_USBRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf52cb564c30e26f503da97e15c1404cd">USB_OTG_GINTSTS_USBRST_Pos</a>)</td></tr>
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<tr class="separator:ga2cc0c061635f5ac73557643af51a1441"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga446f240725aaa8a702b70763cef41661" id="r_ga446f240725aaa8a702b70763cef41661"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga446f240725aaa8a702b70763cef41661">USB_OTG_GINTSTS_USBRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2cc0c061635f5ac73557643af51a1441">USB_OTG_GINTSTS_USBRST_Msk</a></td></tr>
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<tr class="separator:ga446f240725aaa8a702b70763cef41661"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0fd05b6cfa6b54ec8258ccd9c4957859" id="r_ga0fd05b6cfa6b54ec8258ccd9c4957859"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0fd05b6cfa6b54ec8258ccd9c4957859">USB_OTG_GINTSTS_ENUMDNE_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga0fd05b6cfa6b54ec8258ccd9c4957859"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4300a8cbfa6b81490d1747b67966f63b" id="r_ga4300a8cbfa6b81490d1747b67966f63b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4300a8cbfa6b81490d1747b67966f63b">USB_OTG_GINTSTS_ENUMDNE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0fd05b6cfa6b54ec8258ccd9c4957859">USB_OTG_GINTSTS_ENUMDNE_Pos</a>)</td></tr>
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<tr class="separator:ga4300a8cbfa6b81490d1747b67966f63b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88d4e3bdfdfc08a0cc2db20a34cbd598" id="r_ga88d4e3bdfdfc08a0cc2db20a34cbd598"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88d4e3bdfdfc08a0cc2db20a34cbd598">USB_OTG_GINTSTS_ENUMDNE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4300a8cbfa6b81490d1747b67966f63b">USB_OTG_GINTSTS_ENUMDNE_Msk</a></td></tr>
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<tr class="separator:ga88d4e3bdfdfc08a0cc2db20a34cbd598"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga23417bce86919951f9fa8b03d99d9017" id="r_ga23417bce86919951f9fa8b03d99d9017"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga23417bce86919951f9fa8b03d99d9017">USB_OTG_GINTSTS_ISOODRP_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga23417bce86919951f9fa8b03d99d9017"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ca4fde1933a925bf08275f0dc66fab3" id="r_ga1ca4fde1933a925bf08275f0dc66fab3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ca4fde1933a925bf08275f0dc66fab3">USB_OTG_GINTSTS_ISOODRP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga23417bce86919951f9fa8b03d99d9017">USB_OTG_GINTSTS_ISOODRP_Pos</a>)</td></tr>
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<tr class="separator:ga1ca4fde1933a925bf08275f0dc66fab3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad550fd1c59868de214b47c06ef72af16" id="r_gad550fd1c59868de214b47c06ef72af16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad550fd1c59868de214b47c06ef72af16">USB_OTG_GINTSTS_ISOODRP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ca4fde1933a925bf08275f0dc66fab3">USB_OTG_GINTSTS_ISOODRP_Msk</a></td></tr>
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<tr class="memitem:ga3812f09bf415a4f1ee087e527f2f8ff2" id="r_ga3812f09bf415a4f1ee087e527f2f8ff2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3812f09bf415a4f1ee087e527f2f8ff2">USB_OTG_GINTSTS_EOPF_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga3812f09bf415a4f1ee087e527f2f8ff2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1c09e625f1d9bc1b803c5930d0e0298" id="r_gab1c09e625f1d9bc1b803c5930d0e0298"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab1c09e625f1d9bc1b803c5930d0e0298">USB_OTG_GINTSTS_EOPF_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3812f09bf415a4f1ee087e527f2f8ff2">USB_OTG_GINTSTS_EOPF_Pos</a>)</td></tr>
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<tr class="separator:gab1c09e625f1d9bc1b803c5930d0e0298"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e72bb03e22a40500af8f0cf4a34d4a8" id="r_ga3e72bb03e22a40500af8f0cf4a34d4a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e72bb03e22a40500af8f0cf4a34d4a8">USB_OTG_GINTSTS_EOPF</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab1c09e625f1d9bc1b803c5930d0e0298">USB_OTG_GINTSTS_EOPF_Msk</a></td></tr>
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<tr class="separator:ga3e72bb03e22a40500af8f0cf4a34d4a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac190f90afc7a7800ce530536635c84db" id="r_gac190f90afc7a7800ce530536635c84db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac190f90afc7a7800ce530536635c84db">USB_OTG_GINTSTS_IEPINT_Pos</a>   (18U)</td></tr>
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<tr class="separator:gac190f90afc7a7800ce530536635c84db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa17b5ac65578ca653e41479144a6f1fc" id="r_gaa17b5ac65578ca653e41479144a6f1fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa17b5ac65578ca653e41479144a6f1fc">USB_OTG_GINTSTS_IEPINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac190f90afc7a7800ce530536635c84db">USB_OTG_GINTSTS_IEPINT_Pos</a>)</td></tr>
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<tr class="separator:gaa17b5ac65578ca653e41479144a6f1fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba3464cca97f65b232975c7ede5f3928" id="r_gaba3464cca97f65b232975c7ede5f3928"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba3464cca97f65b232975c7ede5f3928">USB_OTG_GINTSTS_IEPINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa17b5ac65578ca653e41479144a6f1fc">USB_OTG_GINTSTS_IEPINT_Msk</a></td></tr>
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<tr class="separator:gaba3464cca97f65b232975c7ede5f3928"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8df58b4dcba0c0e787cd6b5943342c52" id="r_ga8df58b4dcba0c0e787cd6b5943342c52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8df58b4dcba0c0e787cd6b5943342c52">USB_OTG_GINTSTS_OEPINT_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga8df58b4dcba0c0e787cd6b5943342c52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga005e49f60424a85b2abd5315691093dd" id="r_ga005e49f60424a85b2abd5315691093dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga005e49f60424a85b2abd5315691093dd">USB_OTG_GINTSTS_OEPINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8df58b4dcba0c0e787cd6b5943342c52">USB_OTG_GINTSTS_OEPINT_Pos</a>)</td></tr>
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<tr class="separator:ga005e49f60424a85b2abd5315691093dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7191a4ff25e5834f2ebdf0b61103294b" id="r_ga7191a4ff25e5834f2ebdf0b61103294b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7191a4ff25e5834f2ebdf0b61103294b">USB_OTG_GINTSTS_OEPINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga005e49f60424a85b2abd5315691093dd">USB_OTG_GINTSTS_OEPINT_Msk</a></td></tr>
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<tr class="separator:ga7191a4ff25e5834f2ebdf0b61103294b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac5e42d68b484721ee831b67ded60c83" id="r_gaac5e42d68b484721ee831b67ded60c83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac5e42d68b484721ee831b67ded60c83">USB_OTG_GINTSTS_IISOIXFR_Pos</a>   (20U)</td></tr>
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<tr class="separator:gaac5e42d68b484721ee831b67ded60c83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf380deb48e6ff5e99ab18c74684dd51e" id="r_gaf380deb48e6ff5e99ab18c74684dd51e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf380deb48e6ff5e99ab18c74684dd51e">USB_OTG_GINTSTS_IISOIXFR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaac5e42d68b484721ee831b67ded60c83">USB_OTG_GINTSTS_IISOIXFR_Pos</a>)</td></tr>
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<tr class="separator:gaf380deb48e6ff5e99ab18c74684dd51e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga64d9ad7356460a81cfb01e4a39d9fe14" id="r_ga64d9ad7356460a81cfb01e4a39d9fe14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga64d9ad7356460a81cfb01e4a39d9fe14">USB_OTG_GINTSTS_IISOIXFR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf380deb48e6ff5e99ab18c74684dd51e">USB_OTG_GINTSTS_IISOIXFR_Msk</a></td></tr>
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<tr class="separator:ga64d9ad7356460a81cfb01e4a39d9fe14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga58cee872eb24af9fbf28c6e5d736f6ea" id="r_ga58cee872eb24af9fbf28c6e5d736f6ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58cee872eb24af9fbf28c6e5d736f6ea">USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga58cee872eb24af9fbf28c6e5d736f6ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga038bf029239a7327a134697d89adf4d2" id="r_ga038bf029239a7327a134697d89adf4d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga038bf029239a7327a134697d89adf4d2">USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58cee872eb24af9fbf28c6e5d736f6ea">USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos</a>)</td></tr>
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<tr class="separator:ga038bf029239a7327a134697d89adf4d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga590d7ef0d41e8499b968429da4bbe289" id="r_ga590d7ef0d41e8499b968429da4bbe289"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga590d7ef0d41e8499b968429da4bbe289">USB_OTG_GINTSTS_PXFR_INCOMPISOOUT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga038bf029239a7327a134697d89adf4d2">USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk</a></td></tr>
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<tr class="separator:ga590d7ef0d41e8499b968429da4bbe289"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf89d028cf11771da190cb02568a7c711" id="r_gaf89d028cf11771da190cb02568a7c711"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf89d028cf11771da190cb02568a7c711">USB_OTG_GINTSTS_DATAFSUSP_Pos</a>   (22U)</td></tr>
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<tr class="separator:gaf89d028cf11771da190cb02568a7c711"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7b0f4c8c2bbc97f303685f3d236bb0b" id="r_gaa7b0f4c8c2bbc97f303685f3d236bb0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7b0f4c8c2bbc97f303685f3d236bb0b">USB_OTG_GINTSTS_DATAFSUSP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf89d028cf11771da190cb02568a7c711">USB_OTG_GINTSTS_DATAFSUSP_Pos</a>)</td></tr>
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<tr class="separator:gaa7b0f4c8c2bbc97f303685f3d236bb0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e3ca6a1a8087c2c60a6980fa365776d" id="r_ga3e3ca6a1a8087c2c60a6980fa365776d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e3ca6a1a8087c2c60a6980fa365776d">USB_OTG_GINTSTS_DATAFSUSP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa7b0f4c8c2bbc97f303685f3d236bb0b">USB_OTG_GINTSTS_DATAFSUSP_Msk</a></td></tr>
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<tr class="separator:ga3e3ca6a1a8087c2c60a6980fa365776d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae42486a050eb3f8d9b546a06c955f831" id="r_gae42486a050eb3f8d9b546a06c955f831"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae42486a050eb3f8d9b546a06c955f831">USB_OTG_GINTSTS_HPRTINT_Pos</a>   (24U)</td></tr>
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<tr class="separator:gae42486a050eb3f8d9b546a06c955f831"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d8553b58efc1196c9390088c8c28cac" id="r_ga6d8553b58efc1196c9390088c8c28cac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d8553b58efc1196c9390088c8c28cac">USB_OTG_GINTSTS_HPRTINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae42486a050eb3f8d9b546a06c955f831">USB_OTG_GINTSTS_HPRTINT_Pos</a>)</td></tr>
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<tr class="separator:ga6d8553b58efc1196c9390088c8c28cac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaea3470d78914a470f9aba4367f7609d" id="r_gaaea3470d78914a470f9aba4367f7609d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaea3470d78914a470f9aba4367f7609d">USB_OTG_GINTSTS_HPRTINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6d8553b58efc1196c9390088c8c28cac">USB_OTG_GINTSTS_HPRTINT_Msk</a></td></tr>
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<tr class="separator:gaaea3470d78914a470f9aba4367f7609d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ee336f2248571aab4d92adab169cff9" id="r_ga2ee336f2248571aab4d92adab169cff9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ee336f2248571aab4d92adab169cff9">USB_OTG_GINTSTS_HCINT_Pos</a>   (25U)</td></tr>
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<tr class="separator:ga2ee336f2248571aab4d92adab169cff9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga367de65d703dfe6cb6db52c76f996f85" id="r_ga367de65d703dfe6cb6db52c76f996f85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga367de65d703dfe6cb6db52c76f996f85">USB_OTG_GINTSTS_HCINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ee336f2248571aab4d92adab169cff9">USB_OTG_GINTSTS_HCINT_Pos</a>)</td></tr>
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<tr class="separator:ga367de65d703dfe6cb6db52c76f996f85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaedc1e52a9576a68e762d473c74225d2a" id="r_gaedc1e52a9576a68e762d473c74225d2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaedc1e52a9576a68e762d473c74225d2a">USB_OTG_GINTSTS_HCINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga367de65d703dfe6cb6db52c76f996f85">USB_OTG_GINTSTS_HCINT_Msk</a></td></tr>
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<tr class="separator:gaedc1e52a9576a68e762d473c74225d2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f8c0100f49bf442ec3aedc4b4d24d1c" id="r_ga5f8c0100f49bf442ec3aedc4b4d24d1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f8c0100f49bf442ec3aedc4b4d24d1c">USB_OTG_GINTSTS_PTXFE_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga5f8c0100f49bf442ec3aedc4b4d24d1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16028501b6619df3019f71876b649884" id="r_ga16028501b6619df3019f71876b649884"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16028501b6619df3019f71876b649884">USB_OTG_GINTSTS_PTXFE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f8c0100f49bf442ec3aedc4b4d24d1c">USB_OTG_GINTSTS_PTXFE_Pos</a>)</td></tr>
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<tr class="separator:ga16028501b6619df3019f71876b649884"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ce397157106fc508c7f067d8efb7396" id="r_ga2ce397157106fc508c7f067d8efb7396"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ce397157106fc508c7f067d8efb7396">USB_OTG_GINTSTS_PTXFE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga16028501b6619df3019f71876b649884">USB_OTG_GINTSTS_PTXFE_Msk</a></td></tr>
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<tr class="separator:ga2ce397157106fc508c7f067d8efb7396"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2695d008efbfc9c58c739542f8b5a3da" id="r_ga2695d008efbfc9c58c739542f8b5a3da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2695d008efbfc9c58c739542f8b5a3da">USB_OTG_GINTSTS_CIDSCHG_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga2695d008efbfc9c58c739542f8b5a3da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga99288d13e884a0c4c554d3219bf56f51" id="r_ga99288d13e884a0c4c554d3219bf56f51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99288d13e884a0c4c554d3219bf56f51">USB_OTG_GINTSTS_CIDSCHG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2695d008efbfc9c58c739542f8b5a3da">USB_OTG_GINTSTS_CIDSCHG_Pos</a>)</td></tr>
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<tr class="separator:ga99288d13e884a0c4c554d3219bf56f51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga931ec3cde136bc655953191000a16855" id="r_ga931ec3cde136bc655953191000a16855"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga931ec3cde136bc655953191000a16855">USB_OTG_GINTSTS_CIDSCHG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga99288d13e884a0c4c554d3219bf56f51">USB_OTG_GINTSTS_CIDSCHG_Msk</a></td></tr>
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<tr class="memitem:ga2f782ddcb6d950f66177624dd4945906" id="r_ga2f782ddcb6d950f66177624dd4945906"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f782ddcb6d950f66177624dd4945906">USB_OTG_GINTSTS_DISCINT_Pos</a>   (29U)</td></tr>
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<tr class="memitem:ga9bf091e3d68accaeb0237700d77c9fc3" id="r_ga9bf091e3d68accaeb0237700d77c9fc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9bf091e3d68accaeb0237700d77c9fc3">USB_OTG_GINTSTS_DISCINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f782ddcb6d950f66177624dd4945906">USB_OTG_GINTSTS_DISCINT_Pos</a>)</td></tr>
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<tr class="separator:ga9bf091e3d68accaeb0237700d77c9fc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7ef887fec0170857c82ad7a142cce98" id="r_gaa7ef887fec0170857c82ad7a142cce98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7ef887fec0170857c82ad7a142cce98">USB_OTG_GINTSTS_DISCINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9bf091e3d68accaeb0237700d77c9fc3">USB_OTG_GINTSTS_DISCINT_Msk</a></td></tr>
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<tr class="memitem:ga5f3e7b8b9ed0fbb3398b29a092e775bb" id="r_ga5f3e7b8b9ed0fbb3398b29a092e775bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5f3e7b8b9ed0fbb3398b29a092e775bb">USB_OTG_GINTSTS_SRQINT_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga5f3e7b8b9ed0fbb3398b29a092e775bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga37cf1033876ca51d197c2652b87bd084" id="r_ga37cf1033876ca51d197c2652b87bd084"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga37cf1033876ca51d197c2652b87bd084">USB_OTG_GINTSTS_SRQINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5f3e7b8b9ed0fbb3398b29a092e775bb">USB_OTG_GINTSTS_SRQINT_Pos</a>)</td></tr>
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<tr class="separator:ga37cf1033876ca51d197c2652b87bd084"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6f152a76e8a4457cf7f2cd93a95d3fd" id="r_gad6f152a76e8a4457cf7f2cd93a95d3fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6f152a76e8a4457cf7f2cd93a95d3fd">USB_OTG_GINTSTS_SRQINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga37cf1033876ca51d197c2652b87bd084">USB_OTG_GINTSTS_SRQINT_Msk</a></td></tr>
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<tr class="separator:gad6f152a76e8a4457cf7f2cd93a95d3fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3a4034786904e2e3e8d6125d0e8c43d" id="r_gae3a4034786904e2e3e8d6125d0e8c43d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3a4034786904e2e3e8d6125d0e8c43d">USB_OTG_GINTSTS_WKUINT_Pos</a>   (31U)</td></tr>
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<tr class="separator:gae3a4034786904e2e3e8d6125d0e8c43d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0607db8d81e1637d4f91fbddb26bc25" id="r_gaa0607db8d81e1637d4f91fbddb26bc25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0607db8d81e1637d4f91fbddb26bc25">USB_OTG_GINTSTS_WKUINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae3a4034786904e2e3e8d6125d0e8c43d">USB_OTG_GINTSTS_WKUINT_Pos</a>)</td></tr>
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<tr class="separator:gaa0607db8d81e1637d4f91fbddb26bc25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60bc942876444a039c20070d3a91055e" id="r_ga60bc942876444a039c20070d3a91055e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60bc942876444a039c20070d3a91055e">USB_OTG_GINTSTS_WKUINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0607db8d81e1637d4f91fbddb26bc25">USB_OTG_GINTSTS_WKUINT_Msk</a></td></tr>
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<tr class="memitem:ga2c01134b517eb3df18e9f5ef8468aa00" id="r_ga2c01134b517eb3df18e9f5ef8468aa00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c01134b517eb3df18e9f5ef8468aa00">USB_OTG_GINTMSK_MMISM_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga2c01134b517eb3df18e9f5ef8468aa00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf5ccb0f8c7955022c74175b060f1a5e4" id="r_gaf5ccb0f8c7955022c74175b060f1a5e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf5ccb0f8c7955022c74175b060f1a5e4">USB_OTG_GINTMSK_MMISM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c01134b517eb3df18e9f5ef8468aa00">USB_OTG_GINTMSK_MMISM_Pos</a>)</td></tr>
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<tr class="separator:gaf5ccb0f8c7955022c74175b060f1a5e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49ccdddf721bcdb2d44915f210b3e2e2" id="r_ga49ccdddf721bcdb2d44915f210b3e2e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49ccdddf721bcdb2d44915f210b3e2e2">USB_OTG_GINTMSK_MMISM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf5ccb0f8c7955022c74175b060f1a5e4">USB_OTG_GINTMSK_MMISM_Msk</a></td></tr>
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<tr class="separator:ga49ccdddf721bcdb2d44915f210b3e2e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6855459d5f63d37ac78e68e3b4e1c6c" id="r_gaa6855459d5f63d37ac78e68e3b4e1c6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6855459d5f63d37ac78e68e3b4e1c6c">USB_OTG_GINTMSK_OTGINT_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaa6855459d5f63d37ac78e68e3b4e1c6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaff43c3b891b1e76c1e0242a2bab658c" id="r_gaaff43c3b891b1e76c1e0242a2bab658c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaff43c3b891b1e76c1e0242a2bab658c">USB_OTG_GINTMSK_OTGINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6855459d5f63d37ac78e68e3b4e1c6c">USB_OTG_GINTMSK_OTGINT_Pos</a>)</td></tr>
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<tr class="separator:gaaff43c3b891b1e76c1e0242a2bab658c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1138fd4386ac29900b5c46ec7754b4ff" id="r_ga1138fd4386ac29900b5c46ec7754b4ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1138fd4386ac29900b5c46ec7754b4ff">USB_OTG_GINTMSK_OTGINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaff43c3b891b1e76c1e0242a2bab658c">USB_OTG_GINTMSK_OTGINT_Msk</a></td></tr>
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<tr class="separator:ga1138fd4386ac29900b5c46ec7754b4ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d66ca67546aa82347d6c35b525d514e" id="r_ga9d66ca67546aa82347d6c35b525d514e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d66ca67546aa82347d6c35b525d514e">USB_OTG_GINTMSK_SOFM_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga9d66ca67546aa82347d6c35b525d514e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga03618e5abf25fbd2f495b47e6121402a" id="r_ga03618e5abf25fbd2f495b47e6121402a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga03618e5abf25fbd2f495b47e6121402a">USB_OTG_GINTMSK_SOFM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9d66ca67546aa82347d6c35b525d514e">USB_OTG_GINTMSK_SOFM_Pos</a>)</td></tr>
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<tr class="separator:ga03618e5abf25fbd2f495b47e6121402a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabbd83cf86e077c35fdc47e2a2666b391" id="r_gabbd83cf86e077c35fdc47e2a2666b391"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabbd83cf86e077c35fdc47e2a2666b391">USB_OTG_GINTMSK_SOFM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga03618e5abf25fbd2f495b47e6121402a">USB_OTG_GINTMSK_SOFM_Msk</a></td></tr>
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<tr class="separator:gabbd83cf86e077c35fdc47e2a2666b391"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18b2b2a3983a115a57c5a8187568b1f5" id="r_ga18b2b2a3983a115a57c5a8187568b1f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18b2b2a3983a115a57c5a8187568b1f5">USB_OTG_GINTMSK_RXFLVLM_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga18b2b2a3983a115a57c5a8187568b1f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2e0f9299eaf0a9987bb07d6d4ba05228" id="r_ga2e0f9299eaf0a9987bb07d6d4ba05228"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2e0f9299eaf0a9987bb07d6d4ba05228">USB_OTG_GINTMSK_RXFLVLM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga18b2b2a3983a115a57c5a8187568b1f5">USB_OTG_GINTMSK_RXFLVLM_Pos</a>)</td></tr>
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<tr class="separator:ga2e0f9299eaf0a9987bb07d6d4ba05228"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacca853066f092884b6c6af005eee77ed" id="r_gacca853066f092884b6c6af005eee77ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacca853066f092884b6c6af005eee77ed">USB_OTG_GINTMSK_RXFLVLM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2e0f9299eaf0a9987bb07d6d4ba05228">USB_OTG_GINTMSK_RXFLVLM_Msk</a></td></tr>
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<tr class="separator:gacca853066f092884b6c6af005eee77ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga980f36264fcd2e20e5d0f53fbde196f1" id="r_ga980f36264fcd2e20e5d0f53fbde196f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga980f36264fcd2e20e5d0f53fbde196f1">USB_OTG_GINTMSK_NPTXFEM_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga980f36264fcd2e20e5d0f53fbde196f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67278c309dddbbaa4cc520416c60d9be" id="r_ga67278c309dddbbaa4cc520416c60d9be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67278c309dddbbaa4cc520416c60d9be">USB_OTG_GINTMSK_NPTXFEM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga980f36264fcd2e20e5d0f53fbde196f1">USB_OTG_GINTMSK_NPTXFEM_Pos</a>)</td></tr>
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<tr class="separator:ga67278c309dddbbaa4cc520416c60d9be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40b7860f3dc90a9f46e46e2dc133f2e4" id="r_ga40b7860f3dc90a9f46e46e2dc133f2e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40b7860f3dc90a9f46e46e2dc133f2e4">USB_OTG_GINTMSK_NPTXFEM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga67278c309dddbbaa4cc520416c60d9be">USB_OTG_GINTMSK_NPTXFEM_Msk</a></td></tr>
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<tr class="separator:ga40b7860f3dc90a9f46e46e2dc133f2e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bc09652469952607ef86af53e1faa20" id="r_ga2bc09652469952607ef86af53e1faa20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bc09652469952607ef86af53e1faa20">USB_OTG_GINTMSK_GINAKEFFM_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga2bc09652469952607ef86af53e1faa20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53aed86becf8549f65f3038d0d5da115" id="r_ga53aed86becf8549f65f3038d0d5da115"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53aed86becf8549f65f3038d0d5da115">USB_OTG_GINTMSK_GINAKEFFM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2bc09652469952607ef86af53e1faa20">USB_OTG_GINTMSK_GINAKEFFM_Pos</a>)</td></tr>
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<tr class="separator:ga53aed86becf8549f65f3038d0d5da115"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3eb2bbcd11ddee87630472eb01897d3d" id="r_ga3eb2bbcd11ddee87630472eb01897d3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3eb2bbcd11ddee87630472eb01897d3d">USB_OTG_GINTMSK_GINAKEFFM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga53aed86becf8549f65f3038d0d5da115">USB_OTG_GINTMSK_GINAKEFFM_Msk</a></td></tr>
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<tr class="separator:ga3eb2bbcd11ddee87630472eb01897d3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cd00e95e293a7cf81e2912b02a7cf58" id="r_ga8cd00e95e293a7cf81e2912b02a7cf58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cd00e95e293a7cf81e2912b02a7cf58">USB_OTG_GINTMSK_GONAKEFFM_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga8cd00e95e293a7cf81e2912b02a7cf58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga360c770dba2809d002ba1cf317179988" id="r_ga360c770dba2809d002ba1cf317179988"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga360c770dba2809d002ba1cf317179988">USB_OTG_GINTMSK_GONAKEFFM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8cd00e95e293a7cf81e2912b02a7cf58">USB_OTG_GINTMSK_GONAKEFFM_Pos</a>)</td></tr>
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<tr class="separator:ga360c770dba2809d002ba1cf317179988"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba9de7677f70e7fcb4dab90228bdb484" id="r_gaba9de7677f70e7fcb4dab90228bdb484"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba9de7677f70e7fcb4dab90228bdb484">USB_OTG_GINTMSK_GONAKEFFM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga360c770dba2809d002ba1cf317179988">USB_OTG_GINTMSK_GONAKEFFM_Msk</a></td></tr>
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<tr class="separator:gaba9de7677f70e7fcb4dab90228bdb484"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7751043116b431d9ad344b0a58d57a9b" id="r_ga7751043116b431d9ad344b0a58d57a9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7751043116b431d9ad344b0a58d57a9b">USB_OTG_GINTMSK_ESUSPM_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga7751043116b431d9ad344b0a58d57a9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabed33a7a408afafbce8c6243e2345433" id="r_gabed33a7a408afafbce8c6243e2345433"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabed33a7a408afafbce8c6243e2345433">USB_OTG_GINTMSK_ESUSPM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7751043116b431d9ad344b0a58d57a9b">USB_OTG_GINTMSK_ESUSPM_Pos</a>)</td></tr>
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<tr class="separator:gabed33a7a408afafbce8c6243e2345433"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa0fc70a7e7198d7d6f179d9cae29394" id="r_gafa0fc70a7e7198d7d6f179d9cae29394"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa0fc70a7e7198d7d6f179d9cae29394">USB_OTG_GINTMSK_ESUSPM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabed33a7a408afafbce8c6243e2345433">USB_OTG_GINTMSK_ESUSPM_Msk</a></td></tr>
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<tr class="separator:gafa0fc70a7e7198d7d6f179d9cae29394"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7dc3bfe1c4f58eee80c49b1382df3a9" id="r_gae7dc3bfe1c4f58eee80c49b1382df3a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7dc3bfe1c4f58eee80c49b1382df3a9">USB_OTG_GINTMSK_USBSUSPM_Pos</a>   (11U)</td></tr>
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<tr class="separator:gae7dc3bfe1c4f58eee80c49b1382df3a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga44cee5301fb072bbea3e3b095d12e08d" id="r_ga44cee5301fb072bbea3e3b095d12e08d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga44cee5301fb072bbea3e3b095d12e08d">USB_OTG_GINTMSK_USBSUSPM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae7dc3bfe1c4f58eee80c49b1382df3a9">USB_OTG_GINTMSK_USBSUSPM_Pos</a>)</td></tr>
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<tr class="separator:ga44cee5301fb072bbea3e3b095d12e08d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7afb2b0396964430aeb1c7650012fe6" id="r_gaa7afb2b0396964430aeb1c7650012fe6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7afb2b0396964430aeb1c7650012fe6">USB_OTG_GINTMSK_USBSUSPM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga44cee5301fb072bbea3e3b095d12e08d">USB_OTG_GINTMSK_USBSUSPM_Msk</a></td></tr>
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<tr class="memitem:ga4e9ba2c03e49bbe6da21b73e57e73c26" id="r_ga4e9ba2c03e49bbe6da21b73e57e73c26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e9ba2c03e49bbe6da21b73e57e73c26">USB_OTG_GINTMSK_USBRST_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga4e9ba2c03e49bbe6da21b73e57e73c26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9356341b405c61209433fd206e5edc4" id="r_gaa9356341b405c61209433fd206e5edc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9356341b405c61209433fd206e5edc4">USB_OTG_GINTMSK_USBRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4e9ba2c03e49bbe6da21b73e57e73c26">USB_OTG_GINTMSK_USBRST_Pos</a>)</td></tr>
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<tr class="memitem:ga0935f9f5fb77fee0755ceaaa787bb7f6" id="r_ga0935f9f5fb77fee0755ceaaa787bb7f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0935f9f5fb77fee0755ceaaa787bb7f6">USB_OTG_GINTMSK_USBRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa9356341b405c61209433fd206e5edc4">USB_OTG_GINTMSK_USBRST_Msk</a></td></tr>
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<tr class="memitem:ga7bafbc1ce354519f9b0d53d8d8f4187f" id="r_ga7bafbc1ce354519f9b0d53d8d8f4187f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7bafbc1ce354519f9b0d53d8d8f4187f">USB_OTG_GINTMSK_ENUMDNEM_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga7bafbc1ce354519f9b0d53d8d8f4187f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc647118b4e7ef089e014a6da2e42f9e" id="r_gabc647118b4e7ef089e014a6da2e42f9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc647118b4e7ef089e014a6da2e42f9e">USB_OTG_GINTMSK_ENUMDNEM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7bafbc1ce354519f9b0d53d8d8f4187f">USB_OTG_GINTMSK_ENUMDNEM_Pos</a>)</td></tr>
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<tr class="separator:gabc647118b4e7ef089e014a6da2e42f9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6066078d17a4216093855cc210ab6764" id="r_ga6066078d17a4216093855cc210ab6764"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6066078d17a4216093855cc210ab6764">USB_OTG_GINTMSK_ENUMDNEM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gabc647118b4e7ef089e014a6da2e42f9e">USB_OTG_GINTMSK_ENUMDNEM_Msk</a></td></tr>
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<tr class="separator:ga6066078d17a4216093855cc210ab6764"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga594d179afd1c73ca5c341fe09a67cbe7" id="r_ga594d179afd1c73ca5c341fe09a67cbe7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga594d179afd1c73ca5c341fe09a67cbe7">USB_OTG_GINTMSK_ISOODRPM_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga594d179afd1c73ca5c341fe09a67cbe7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga442bbb88091efa2c2f707909e51477f3" id="r_ga442bbb88091efa2c2f707909e51477f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga442bbb88091efa2c2f707909e51477f3">USB_OTG_GINTMSK_ISOODRPM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga594d179afd1c73ca5c341fe09a67cbe7">USB_OTG_GINTMSK_ISOODRPM_Pos</a>)</td></tr>
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<tr class="separator:ga442bbb88091efa2c2f707909e51477f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e01710480bf4d5edf5c344798c88624" id="r_ga1e01710480bf4d5edf5c344798c88624"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e01710480bf4d5edf5c344798c88624">USB_OTG_GINTMSK_ISOODRPM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga442bbb88091efa2c2f707909e51477f3">USB_OTG_GINTMSK_ISOODRPM_Msk</a></td></tr>
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<tr class="separator:ga1e01710480bf4d5edf5c344798c88624"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac9dc782a42d4b724d28494d0030b9a71" id="r_gac9dc782a42d4b724d28494d0030b9a71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac9dc782a42d4b724d28494d0030b9a71">USB_OTG_GINTMSK_EOPFM_Pos</a>   (15U)</td></tr>
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<tr class="separator:gac9dc782a42d4b724d28494d0030b9a71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53404953b235600349f7f631caff940b" id="r_ga53404953b235600349f7f631caff940b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga53404953b235600349f7f631caff940b">USB_OTG_GINTMSK_EOPFM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac9dc782a42d4b724d28494d0030b9a71">USB_OTG_GINTMSK_EOPFM_Pos</a>)</td></tr>
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<tr class="separator:ga53404953b235600349f7f631caff940b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd06eee1627ac5ba7212a728f19e4fe8" id="r_gabd06eee1627ac5ba7212a728f19e4fe8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd06eee1627ac5ba7212a728f19e4fe8">USB_OTG_GINTMSK_EOPFM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga53404953b235600349f7f631caff940b">USB_OTG_GINTMSK_EOPFM_Msk</a></td></tr>
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<tr class="separator:gabd06eee1627ac5ba7212a728f19e4fe8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2c92fa81e0b29cbf873ac24bdcbc1ac" id="r_gad2c92fa81e0b29cbf873ac24bdcbc1ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2c92fa81e0b29cbf873ac24bdcbc1ac">USB_OTG_GINTMSK_EPMISM_Pos</a>   (17U)</td></tr>
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<tr class="separator:gad2c92fa81e0b29cbf873ac24bdcbc1ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf538166d934b884ae39bdfe98cbd16b6" id="r_gaf538166d934b884ae39bdfe98cbd16b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf538166d934b884ae39bdfe98cbd16b6">USB_OTG_GINTMSK_EPMISM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2c92fa81e0b29cbf873ac24bdcbc1ac">USB_OTG_GINTMSK_EPMISM_Pos</a>)</td></tr>
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<tr class="memitem:ga35ecb8ef940b0ace19712f5fefa1193c" id="r_ga35ecb8ef940b0ace19712f5fefa1193c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga35ecb8ef940b0ace19712f5fefa1193c">USB_OTG_GINTMSK_EPMISM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf538166d934b884ae39bdfe98cbd16b6">USB_OTG_GINTMSK_EPMISM_Msk</a></td></tr>
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<tr class="memitem:ga6cf4b99bff0d732dfc46a83947266fce" id="r_ga6cf4b99bff0d732dfc46a83947266fce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cf4b99bff0d732dfc46a83947266fce">USB_OTG_GINTMSK_IEPINT_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga6cf4b99bff0d732dfc46a83947266fce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae283ace2a396c147245a581322b25761" id="r_gae283ace2a396c147245a581322b25761"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae283ace2a396c147245a581322b25761">USB_OTG_GINTMSK_IEPINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cf4b99bff0d732dfc46a83947266fce">USB_OTG_GINTMSK_IEPINT_Pos</a>)</td></tr>
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<tr class="separator:gae283ace2a396c147245a581322b25761"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7b0d0879e3d57e3a21610ab590da6ae" id="r_gaa7b0d0879e3d57e3a21610ab590da6ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7b0d0879e3d57e3a21610ab590da6ae">USB_OTG_GINTMSK_IEPINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae283ace2a396c147245a581322b25761">USB_OTG_GINTMSK_IEPINT_Msk</a></td></tr>
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<tr class="separator:gaa7b0d0879e3d57e3a21610ab590da6ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e646bf0709fd1662301a3e81e167e8f" id="r_ga7e646bf0709fd1662301a3e81e167e8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e646bf0709fd1662301a3e81e167e8f">USB_OTG_GINTMSK_OEPINT_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga7e646bf0709fd1662301a3e81e167e8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcdffda36a1a980f7d77038e2e5acb29" id="r_gafcdffda36a1a980f7d77038e2e5acb29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcdffda36a1a980f7d77038e2e5acb29">USB_OTG_GINTMSK_OEPINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7e646bf0709fd1662301a3e81e167e8f">USB_OTG_GINTMSK_OEPINT_Pos</a>)</td></tr>
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<tr class="separator:gafcdffda36a1a980f7d77038e2e5acb29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff1341cabf6155e197f657b12237dbb8" id="r_gaff1341cabf6155e197f657b12237dbb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaff1341cabf6155e197f657b12237dbb8">USB_OTG_GINTMSK_OEPINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafcdffda36a1a980f7d77038e2e5acb29">USB_OTG_GINTMSK_OEPINT_Msk</a></td></tr>
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<tr class="separator:gaff1341cabf6155e197f657b12237dbb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f677a85809f7741c7bce7d6486f4f0b" id="r_ga7f677a85809f7741c7bce7d6486f4f0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f677a85809f7741c7bce7d6486f4f0b">USB_OTG_GINTMSK_IISOIXFRM_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga7f677a85809f7741c7bce7d6486f4f0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga932753540aef5f14f8801ea26789cef4" id="r_ga932753540aef5f14f8801ea26789cef4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga932753540aef5f14f8801ea26789cef4">USB_OTG_GINTMSK_IISOIXFRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f677a85809f7741c7bce7d6486f4f0b">USB_OTG_GINTMSK_IISOIXFRM_Pos</a>)</td></tr>
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<tr class="separator:ga932753540aef5f14f8801ea26789cef4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a505c6af38c507dfe84028d6194e08e" id="r_ga9a505c6af38c507dfe84028d6194e08e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9a505c6af38c507dfe84028d6194e08e">USB_OTG_GINTMSK_IISOIXFRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga932753540aef5f14f8801ea26789cef4">USB_OTG_GINTMSK_IISOIXFRM_Msk</a></td></tr>
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<tr class="separator:ga9a505c6af38c507dfe84028d6194e08e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6a04d965084d298bd9902072771750f" id="r_gad6a04d965084d298bd9902072771750f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6a04d965084d298bd9902072771750f">USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos</a>   (21U)</td></tr>
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<tr class="separator:gad6a04d965084d298bd9902072771750f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7fc2d5326991ca1857dcc4825688d21" id="r_gae7fc2d5326991ca1857dcc4825688d21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7fc2d5326991ca1857dcc4825688d21">USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad6a04d965084d298bd9902072771750f">USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos</a>)</td></tr>
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<tr class="memitem:ga7fb0cdc2b7f0d8de8bbd8beaf3d69ae1" id="r_ga7fb0cdc2b7f0d8de8bbd8beaf3d69ae1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7fb0cdc2b7f0d8de8bbd8beaf3d69ae1">USB_OTG_GINTMSK_PXFRM_IISOOXFRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae7fc2d5326991ca1857dcc4825688d21">USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk</a></td></tr>
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<tr class="separator:ga7fb0cdc2b7f0d8de8bbd8beaf3d69ae1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2fc5d32a7e8a6828c986edb99360bb61" id="r_ga2fc5d32a7e8a6828c986edb99360bb61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fc5d32a7e8a6828c986edb99360bb61">USB_OTG_GINTMSK_FSUSPM_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga2fc5d32a7e8a6828c986edb99360bb61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga941f4e537d06501247b906cbd37410c7" id="r_ga941f4e537d06501247b906cbd37410c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga941f4e537d06501247b906cbd37410c7">USB_OTG_GINTMSK_FSUSPM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2fc5d32a7e8a6828c986edb99360bb61">USB_OTG_GINTMSK_FSUSPM_Pos</a>)</td></tr>
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<tr class="separator:ga941f4e537d06501247b906cbd37410c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae29d6ecd5e6c802a6214b814f6466b58" id="r_gae29d6ecd5e6c802a6214b814f6466b58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae29d6ecd5e6c802a6214b814f6466b58">USB_OTG_GINTMSK_FSUSPM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga941f4e537d06501247b906cbd37410c7">USB_OTG_GINTMSK_FSUSPM_Msk</a></td></tr>
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<tr class="separator:gae29d6ecd5e6c802a6214b814f6466b58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2401d68c3c2a2d7229572c214377615" id="r_gaa2401d68c3c2a2d7229572c214377615"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa2401d68c3c2a2d7229572c214377615">USB_OTG_GINTMSK_PRTIM_Pos</a>   (24U)</td></tr>
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<tr class="separator:gaa2401d68c3c2a2d7229572c214377615"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2f3349ecf1e586219b22452f93d3725" id="r_gaf2f3349ecf1e586219b22452f93d3725"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2f3349ecf1e586219b22452f93d3725">USB_OTG_GINTMSK_PRTIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa2401d68c3c2a2d7229572c214377615">USB_OTG_GINTMSK_PRTIM_Pos</a>)</td></tr>
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<tr class="separator:gaf2f3349ecf1e586219b22452f93d3725"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8b1d4a903966e3ad62a8c299875a082" id="r_gab8b1d4a903966e3ad62a8c299875a082"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8b1d4a903966e3ad62a8c299875a082">USB_OTG_GINTMSK_PRTIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2f3349ecf1e586219b22452f93d3725">USB_OTG_GINTMSK_PRTIM_Msk</a></td></tr>
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<tr class="separator:gab8b1d4a903966e3ad62a8c299875a082"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad83cad33689d2b786e2ea01faece0f6a" id="r_gad83cad33689d2b786e2ea01faece0f6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad83cad33689d2b786e2ea01faece0f6a">USB_OTG_GINTMSK_HCIM_Pos</a>   (25U)</td></tr>
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<tr class="separator:gad83cad33689d2b786e2ea01faece0f6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91482bd34447d0e44c2bf4ad9b9e3aa0" id="r_ga91482bd34447d0e44c2bf4ad9b9e3aa0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91482bd34447d0e44c2bf4ad9b9e3aa0">USB_OTG_GINTMSK_HCIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad83cad33689d2b786e2ea01faece0f6a">USB_OTG_GINTMSK_HCIM_Pos</a>)</td></tr>
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<tr class="separator:ga91482bd34447d0e44c2bf4ad9b9e3aa0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ff8e84db67f2f7c46998c2236f9c6cc" id="r_ga1ff8e84db67f2f7c46998c2236f9c6cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ff8e84db67f2f7c46998c2236f9c6cc">USB_OTG_GINTMSK_HCIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga91482bd34447d0e44c2bf4ad9b9e3aa0">USB_OTG_GINTMSK_HCIM_Msk</a></td></tr>
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<tr class="separator:ga1ff8e84db67f2f7c46998c2236f9c6cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafe3c9998d70dd959dfa2afa021984bf6" id="r_gafe3c9998d70dd959dfa2afa021984bf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafe3c9998d70dd959dfa2afa021984bf6">USB_OTG_GINTMSK_PTXFEM_Pos</a>   (26U)</td></tr>
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<tr class="separator:gafe3c9998d70dd959dfa2afa021984bf6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7146797fddc3a6bae1b081568810f35e" id="r_ga7146797fddc3a6bae1b081568810f35e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7146797fddc3a6bae1b081568810f35e">USB_OTG_GINTMSK_PTXFEM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafe3c9998d70dd959dfa2afa021984bf6">USB_OTG_GINTMSK_PTXFEM_Pos</a>)</td></tr>
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<tr class="separator:ga7146797fddc3a6bae1b081568810f35e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2744ae4d8e4c018a9a541af8ce68d01d" id="r_ga2744ae4d8e4c018a9a541af8ce68d01d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2744ae4d8e4c018a9a541af8ce68d01d">USB_OTG_GINTMSK_PTXFEM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7146797fddc3a6bae1b081568810f35e">USB_OTG_GINTMSK_PTXFEM_Msk</a></td></tr>
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<tr class="separator:ga2744ae4d8e4c018a9a541af8ce68d01d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17256c345931101867a6244fffd296e5" id="r_ga17256c345931101867a6244fffd296e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17256c345931101867a6244fffd296e5">USB_OTG_GINTMSK_CIDSCHGM_Pos</a>   (28U)</td></tr>
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<tr class="separator:ga17256c345931101867a6244fffd296e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae4b71ca238b78977cad1c0362044065" id="r_gaae4b71ca238b78977cad1c0362044065"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae4b71ca238b78977cad1c0362044065">USB_OTG_GINTMSK_CIDSCHGM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga17256c345931101867a6244fffd296e5">USB_OTG_GINTMSK_CIDSCHGM_Pos</a>)</td></tr>
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<tr class="separator:gaae4b71ca238b78977cad1c0362044065"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe390b69b7379dc93f9c25b6b35a71f2" id="r_gabe390b69b7379dc93f9c25b6b35a71f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe390b69b7379dc93f9c25b6b35a71f2">USB_OTG_GINTMSK_CIDSCHGM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae4b71ca238b78977cad1c0362044065">USB_OTG_GINTMSK_CIDSCHGM_Msk</a></td></tr>
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<tr class="separator:gabe390b69b7379dc93f9c25b6b35a71f2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9413f2f7748902aa9b9e6997fdb2e59c" id="r_ga9413f2f7748902aa9b9e6997fdb2e59c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9413f2f7748902aa9b9e6997fdb2e59c">USB_OTG_GINTMSK_DISCINT_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga9413f2f7748902aa9b9e6997fdb2e59c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34f387040509ac1ea94b3dbc95302e54" id="r_ga34f387040509ac1ea94b3dbc95302e54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34f387040509ac1ea94b3dbc95302e54">USB_OTG_GINTMSK_DISCINT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9413f2f7748902aa9b9e6997fdb2e59c">USB_OTG_GINTMSK_DISCINT_Pos</a>)</td></tr>
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<tr class="separator:ga34f387040509ac1ea94b3dbc95302e54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6de24048cab1948503c26d09ee5a4397" id="r_ga6de24048cab1948503c26d09ee5a4397"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6de24048cab1948503c26d09ee5a4397">USB_OTG_GINTMSK_DISCINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34f387040509ac1ea94b3dbc95302e54">USB_OTG_GINTMSK_DISCINT_Msk</a></td></tr>
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<tr class="separator:ga6de24048cab1948503c26d09ee5a4397"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b7fa3ef7a96e9fc563a90bdd46348e9" id="r_ga2b7fa3ef7a96e9fc563a90bdd46348e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b7fa3ef7a96e9fc563a90bdd46348e9">USB_OTG_GINTMSK_SRQIM_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga2b7fa3ef7a96e9fc563a90bdd46348e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga075abd906877496518197feccbd33643" id="r_ga075abd906877496518197feccbd33643"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga075abd906877496518197feccbd33643">USB_OTG_GINTMSK_SRQIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b7fa3ef7a96e9fc563a90bdd46348e9">USB_OTG_GINTMSK_SRQIM_Pos</a>)</td></tr>
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<tr class="separator:ga075abd906877496518197feccbd33643"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga896592b90dc012f3c4d004cd2280fb8f" id="r_ga896592b90dc012f3c4d004cd2280fb8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga896592b90dc012f3c4d004cd2280fb8f">USB_OTG_GINTMSK_SRQIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga075abd906877496518197feccbd33643">USB_OTG_GINTMSK_SRQIM_Msk</a></td></tr>
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<tr class="separator:ga896592b90dc012f3c4d004cd2280fb8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cfe069353fb275d12afa3e0a55e7e11" id="r_ga5cfe069353fb275d12afa3e0a55e7e11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5cfe069353fb275d12afa3e0a55e7e11">USB_OTG_GINTMSK_WUIM_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga5cfe069353fb275d12afa3e0a55e7e11"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaf042e8854e22eacdba2faa356fe1b58" id="r_gaaf042e8854e22eacdba2faa356fe1b58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaf042e8854e22eacdba2faa356fe1b58">USB_OTG_GINTMSK_WUIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cfe069353fb275d12afa3e0a55e7e11">USB_OTG_GINTMSK_WUIM_Pos</a>)</td></tr>
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<tr class="separator:gaaf042e8854e22eacdba2faa356fe1b58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab641d285c79ab1b54c1d0c615afe87f5" id="r_gab641d285c79ab1b54c1d0c615afe87f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab641d285c79ab1b54c1d0c615afe87f5">USB_OTG_GINTMSK_WUIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaf042e8854e22eacdba2faa356fe1b58">USB_OTG_GINTMSK_WUIM_Msk</a></td></tr>
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<tr class="separator:gab641d285c79ab1b54c1d0c615afe87f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae63137414d813c9639e678ce3f59d214" id="r_gae63137414d813c9639e678ce3f59d214"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae63137414d813c9639e678ce3f59d214">USB_OTG_DAINT_IEPINT_Pos</a>   (0U)</td></tr>
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<tr class="separator:gae63137414d813c9639e678ce3f59d214"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0458c7203562b2f88f6301ee5914b5be" id="r_ga0458c7203562b2f88f6301ee5914b5be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0458c7203562b2f88f6301ee5914b5be">USB_OTG_DAINT_IEPINT_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae63137414d813c9639e678ce3f59d214">USB_OTG_DAINT_IEPINT_Pos</a>)</td></tr>
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<tr class="separator:ga0458c7203562b2f88f6301ee5914b5be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac640d7686606412f8b3593fc3bc76976" id="r_gac640d7686606412f8b3593fc3bc76976"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac640d7686606412f8b3593fc3bc76976">USB_OTG_DAINT_IEPINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0458c7203562b2f88f6301ee5914b5be">USB_OTG_DAINT_IEPINT_Msk</a></td></tr>
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<tr class="separator:gac640d7686606412f8b3593fc3bc76976"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga25afe9767c710d1e25db2f40719e2d1e" id="r_ga25afe9767c710d1e25db2f40719e2d1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga25afe9767c710d1e25db2f40719e2d1e">USB_OTG_DAINT_OEPINT_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga25afe9767c710d1e25db2f40719e2d1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae1224c9e9728d40025d9326e31a0c6b" id="r_gaae1224c9e9728d40025d9326e31a0c6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae1224c9e9728d40025d9326e31a0c6b">USB_OTG_DAINT_OEPINT_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga25afe9767c710d1e25db2f40719e2d1e">USB_OTG_DAINT_OEPINT_Pos</a>)</td></tr>
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<tr class="separator:gaae1224c9e9728d40025d9326e31a0c6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1da6e6b0cb689727710c7c23162fb5d" id="r_gad1da6e6b0cb689727710c7c23162fb5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1da6e6b0cb689727710c7c23162fb5d">USB_OTG_DAINT_OEPINT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae1224c9e9728d40025d9326e31a0c6b">USB_OTG_DAINT_OEPINT_Msk</a></td></tr>
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<tr class="separator:gad1da6e6b0cb689727710c7c23162fb5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa567788f5117a97c9ac2f72065e49365" id="r_gaa567788f5117a97c9ac2f72065e49365"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa567788f5117a97c9ac2f72065e49365">USB_OTG_HAINTMSK_HAINTM_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga326da6d7c5280028f57cf69bc5958b4a" id="r_ga326da6d7c5280028f57cf69bc5958b4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga326da6d7c5280028f57cf69bc5958b4a">USB_OTG_HAINTMSK_HAINTM_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa567788f5117a97c9ac2f72065e49365">USB_OTG_HAINTMSK_HAINTM_Pos</a>)</td></tr>
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<tr class="memitem:gac1f2419baf94819340bd759b09004121" id="r_gac1f2419baf94819340bd759b09004121"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1f2419baf94819340bd759b09004121">USB_OTG_HAINTMSK_HAINTM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga326da6d7c5280028f57cf69bc5958b4a">USB_OTG_HAINTMSK_HAINTM_Msk</a></td></tr>
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<tr class="memitem:ga7c7c5fd797eed7457c60a0edfa2578e5" id="r_ga7c7c5fd797eed7457c60a0edfa2578e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c7c5fd797eed7457c60a0edfa2578e5">USB_OTG_GRXSTSP_EPNUM_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7c7c5fd797eed7457c60a0edfa2578e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34de745d37102b0c8d8bc0daac0437a4" id="r_ga34de745d37102b0c8d8bc0daac0437a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34de745d37102b0c8d8bc0daac0437a4">USB_OTG_GRXSTSP_EPNUM_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c7c5fd797eed7457c60a0edfa2578e5">USB_OTG_GRXSTSP_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:ga34de745d37102b0c8d8bc0daac0437a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09b6ae9c0db0348ae11d171912651bf2" id="r_ga09b6ae9c0db0348ae11d171912651bf2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09b6ae9c0db0348ae11d171912651bf2">USB_OTG_GRXSTSP_EPNUM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga34de745d37102b0c8d8bc0daac0437a4">USB_OTG_GRXSTSP_EPNUM_Msk</a></td></tr>
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<tr class="memitem:gac000307f9a9c2cd3f342ea9bb1d5c53f" id="r_gac000307f9a9c2cd3f342ea9bb1d5c53f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac000307f9a9c2cd3f342ea9bb1d5c53f">USB_OTG_GRXSTSP_BCNT_Pos</a>   (4U)</td></tr>
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<tr class="separator:gac000307f9a9c2cd3f342ea9bb1d5c53f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffd3da88ae4fb7c15b79e072e2230441" id="r_gaffd3da88ae4fb7c15b79e072e2230441"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffd3da88ae4fb7c15b79e072e2230441">USB_OTG_GRXSTSP_BCNT_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac000307f9a9c2cd3f342ea9bb1d5c53f">USB_OTG_GRXSTSP_BCNT_Pos</a>)</td></tr>
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<tr class="separator:gaffd3da88ae4fb7c15b79e072e2230441"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7cc28354cac4479286e02df84b82eaa" id="r_gaa7cc28354cac4479286e02df84b82eaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa7cc28354cac4479286e02df84b82eaa">USB_OTG_GRXSTSP_BCNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaffd3da88ae4fb7c15b79e072e2230441">USB_OTG_GRXSTSP_BCNT_Msk</a></td></tr>
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<tr class="memitem:ga13cf2cc9c798b4048a80c993020c4306" id="r_ga13cf2cc9c798b4048a80c993020c4306"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13cf2cc9c798b4048a80c993020c4306">USB_OTG_GRXSTSP_DPID_Pos</a>   (15U)</td></tr>
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<tr class="memitem:ga76f9198db9bcb93fc1823fe6278c06ad" id="r_ga76f9198db9bcb93fc1823fe6278c06ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76f9198db9bcb93fc1823fe6278c06ad">USB_OTG_GRXSTSP_DPID_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga13cf2cc9c798b4048a80c993020c4306">USB_OTG_GRXSTSP_DPID_Pos</a>)</td></tr>
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<tr class="separator:ga76f9198db9bcb93fc1823fe6278c06ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89a85cea9c8ee8cea016f80c1354b0e2" id="r_ga89a85cea9c8ee8cea016f80c1354b0e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89a85cea9c8ee8cea016f80c1354b0e2">USB_OTG_GRXSTSP_DPID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga76f9198db9bcb93fc1823fe6278c06ad">USB_OTG_GRXSTSP_DPID_Msk</a></td></tr>
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<tr class="separator:ga89a85cea9c8ee8cea016f80c1354b0e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga27644858023a064bac6755fcdff30ab9" id="r_ga27644858023a064bac6755fcdff30ab9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga27644858023a064bac6755fcdff30ab9">USB_OTG_GRXSTSP_PKTSTS_Pos</a>   (17U)</td></tr>
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<tr class="memitem:ga02d6c9af341038ba6622a9ac14e0aeda" id="r_ga02d6c9af341038ba6622a9ac14e0aeda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga02d6c9af341038ba6622a9ac14e0aeda">USB_OTG_GRXSTSP_PKTSTS_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga27644858023a064bac6755fcdff30ab9">USB_OTG_GRXSTSP_PKTSTS_Pos</a>)</td></tr>
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<tr class="separator:ga02d6c9af341038ba6622a9ac14e0aeda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga968cdd119ee75647a2ab2a6beecd54fc" id="r_ga968cdd119ee75647a2ab2a6beecd54fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga968cdd119ee75647a2ab2a6beecd54fc">USB_OTG_GRXSTSP_PKTSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga02d6c9af341038ba6622a9ac14e0aeda">USB_OTG_GRXSTSP_PKTSTS_Msk</a></td></tr>
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<tr class="memitem:ga7c30ee057efc639e21534e6d8cff9a1f" id="r_ga7c30ee057efc639e21534e6d8cff9a1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7c30ee057efc639e21534e6d8cff9a1f">USB_OTG_DAINTMSK_IEPM_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7c30ee057efc639e21534e6d8cff9a1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafff61f58b2d93be3d36f44794981e80c" id="r_gafff61f58b2d93be3d36f44794981e80c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafff61f58b2d93be3d36f44794981e80c">USB_OTG_DAINTMSK_IEPM_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7c30ee057efc639e21534e6d8cff9a1f">USB_OTG_DAINTMSK_IEPM_Pos</a>)</td></tr>
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<tr class="separator:gafff61f58b2d93be3d36f44794981e80c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa9eaacec55a1e6d5ea06babfacf6a77c" id="r_gaa9eaacec55a1e6d5ea06babfacf6a77c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa9eaacec55a1e6d5ea06babfacf6a77c">USB_OTG_DAINTMSK_IEPM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafff61f58b2d93be3d36f44794981e80c">USB_OTG_DAINTMSK_IEPM_Msk</a></td></tr>
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<tr class="separator:gaa9eaacec55a1e6d5ea06babfacf6a77c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24fb9df620319cb9d09fb93822cf9673" id="r_ga24fb9df620319cb9d09fb93822cf9673"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24fb9df620319cb9d09fb93822cf9673">USB_OTG_DAINTMSK_OEPM_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga24fb9df620319cb9d09fb93822cf9673"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86dad56d8d5e8ced81ff1486b8f8b82c" id="r_ga86dad56d8d5e8ced81ff1486b8f8b82c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86dad56d8d5e8ced81ff1486b8f8b82c">USB_OTG_DAINTMSK_OEPM_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24fb9df620319cb9d09fb93822cf9673">USB_OTG_DAINTMSK_OEPM_Pos</a>)</td></tr>
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<tr class="separator:ga86dad56d8d5e8ced81ff1486b8f8b82c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1e90f8633158170a810a7b739d280aa" id="r_gad1e90f8633158170a810a7b739d280aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1e90f8633158170a810a7b739d280aa">USB_OTG_DAINTMSK_OEPM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86dad56d8d5e8ced81ff1486b8f8b82c">USB_OTG_DAINTMSK_OEPM_Msk</a></td></tr>
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<tr class="memitem:gac57cf2cc40ef0ecb3f7162af3bde8417" id="r_gac57cf2cc40ef0ecb3f7162af3bde8417"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac57cf2cc40ef0ecb3f7162af3bde8417">USB_OTG_GRXFSIZ_RXFD_Pos</a>   (0U)</td></tr>
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<tr class="separator:gac57cf2cc40ef0ecb3f7162af3bde8417"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19912b7862dbda078a7c986251282051" id="r_ga19912b7862dbda078a7c986251282051"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga19912b7862dbda078a7c986251282051">USB_OTG_GRXFSIZ_RXFD_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac57cf2cc40ef0ecb3f7162af3bde8417">USB_OTG_GRXFSIZ_RXFD_Pos</a>)</td></tr>
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<tr class="memitem:ga645e153273d36f18999be31a5f9c152b" id="r_ga645e153273d36f18999be31a5f9c152b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga645e153273d36f18999be31a5f9c152b">USB_OTG_GRXFSIZ_RXFD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga19912b7862dbda078a7c986251282051">USB_OTG_GRXFSIZ_RXFD_Msk</a></td></tr>
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<tr class="separator:ga645e153273d36f18999be31a5f9c152b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga068bb85a1956e5ef91ed2556a68814da" id="r_ga068bb85a1956e5ef91ed2556a68814da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga068bb85a1956e5ef91ed2556a68814da">USB_OTG_DVBUSDIS_VBUSDT_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga068bb85a1956e5ef91ed2556a68814da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05d481daeec0e3867bc14ddbf33c668b" id="r_ga05d481daeec0e3867bc14ddbf33c668b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05d481daeec0e3867bc14ddbf33c668b">USB_OTG_DVBUSDIS_VBUSDT_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga068bb85a1956e5ef91ed2556a68814da">USB_OTG_DVBUSDIS_VBUSDT_Pos</a>)</td></tr>
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<tr class="separator:ga05d481daeec0e3867bc14ddbf33c668b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga749c7152aea411faaaeec1b43afb43e5" id="r_ga749c7152aea411faaaeec1b43afb43e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga749c7152aea411faaaeec1b43afb43e5">USB_OTG_DVBUSDIS_VBUSDT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga05d481daeec0e3867bc14ddbf33c668b">USB_OTG_DVBUSDIS_VBUSDT_Msk</a></td></tr>
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<tr class="separator:ga749c7152aea411faaaeec1b43afb43e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad33e0dcd0891b3d9175d22596f37335e" id="r_gad33e0dcd0891b3d9175d22596f37335e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad33e0dcd0891b3d9175d22596f37335e">USB_OTG_NPTXFSA_Pos</a>   (0U)</td></tr>
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<tr class="separator:gad33e0dcd0891b3d9175d22596f37335e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8d574718d661d828fdbd50dd9de84f79" id="r_ga8d574718d661d828fdbd50dd9de84f79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8d574718d661d828fdbd50dd9de84f79">USB_OTG_NPTXFSA_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad33e0dcd0891b3d9175d22596f37335e">USB_OTG_NPTXFSA_Pos</a>)</td></tr>
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<tr class="separator:ga8d574718d661d828fdbd50dd9de84f79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7288bc9a03bd0068584bfbf7a00de132" id="r_ga7288bc9a03bd0068584bfbf7a00de132"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7288bc9a03bd0068584bfbf7a00de132">USB_OTG_NPTXFSA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8d574718d661d828fdbd50dd9de84f79">USB_OTG_NPTXFSA_Msk</a></td></tr>
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<tr class="separator:ga7288bc9a03bd0068584bfbf7a00de132"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga954d5cbcea939dfff88dcbf8be48fcb8" id="r_ga954d5cbcea939dfff88dcbf8be48fcb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga954d5cbcea939dfff88dcbf8be48fcb8">USB_OTG_NPTXFD_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga954d5cbcea939dfff88dcbf8be48fcb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga925ee7600d2f4c33f4ada106ad2da436" id="r_ga925ee7600d2f4c33f4ada106ad2da436"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga925ee7600d2f4c33f4ada106ad2da436">USB_OTG_NPTXFD_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga954d5cbcea939dfff88dcbf8be48fcb8">USB_OTG_NPTXFD_Pos</a>)</td></tr>
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<tr class="separator:ga925ee7600d2f4c33f4ada106ad2da436"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa42909f04dfa46977d5d95ba84a81f7a" id="r_gaa42909f04dfa46977d5d95ba84a81f7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa42909f04dfa46977d5d95ba84a81f7a">USB_OTG_NPTXFD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga925ee7600d2f4c33f4ada106ad2da436">USB_OTG_NPTXFD_Msk</a></td></tr>
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<tr class="memitem:ga09477e07dbd7bb519ed546c5a609f9e2" id="r_ga09477e07dbd7bb519ed546c5a609f9e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga09477e07dbd7bb519ed546c5a609f9e2">USB_OTG_TX0FSA_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga1135e855d8d6bd816ab72978a82217d5" id="r_ga1135e855d8d6bd816ab72978a82217d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1135e855d8d6bd816ab72978a82217d5">USB_OTG_TX0FSA_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga09477e07dbd7bb519ed546c5a609f9e2">USB_OTG_TX0FSA_Pos</a>)</td></tr>
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<tr class="separator:ga1135e855d8d6bd816ab72978a82217d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga878564768aedb86dd987f933edd56ded" id="r_ga878564768aedb86dd987f933edd56ded"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga878564768aedb86dd987f933edd56ded">USB_OTG_TX0FSA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1135e855d8d6bd816ab72978a82217d5">USB_OTG_TX0FSA_Msk</a></td></tr>
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<tr class="separator:ga878564768aedb86dd987f933edd56ded"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1230d9e57244b6175d180f4055043add" id="r_ga1230d9e57244b6175d180f4055043add"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1230d9e57244b6175d180f4055043add">USB_OTG_TX0FD_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga1230d9e57244b6175d180f4055043add"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae9db88da5ed817b0e836a7fe631b8a3c" id="r_gae9db88da5ed817b0e836a7fe631b8a3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae9db88da5ed817b0e836a7fe631b8a3c">USB_OTG_TX0FD_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1230d9e57244b6175d180f4055043add">USB_OTG_TX0FD_Pos</a>)</td></tr>
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<tr class="separator:gae9db88da5ed817b0e836a7fe631b8a3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd6ed0dba3c92506928f19a8dae4a4cd" id="r_gabd6ed0dba3c92506928f19a8dae4a4cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd6ed0dba3c92506928f19a8dae4a4cd">USB_OTG_TX0FD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae9db88da5ed817b0e836a7fe631b8a3c">USB_OTG_TX0FD_Msk</a></td></tr>
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<tr class="separator:gabd6ed0dba3c92506928f19a8dae4a4cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1debd748822446b78fd35dd4e5bffb2" id="r_gaa1debd748822446b78fd35dd4e5bffb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1debd748822446b78fd35dd4e5bffb2">USB_OTG_DVBUSPULSE_DVBUSP_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa1debd748822446b78fd35dd4e5bffb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0f53728ef57cfd0c9099458e5ede08b" id="r_gaa0f53728ef57cfd0c9099458e5ede08b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0f53728ef57cfd0c9099458e5ede08b">USB_OTG_DVBUSPULSE_DVBUSP_Msk</a>   (0xFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1debd748822446b78fd35dd4e5bffb2">USB_OTG_DVBUSPULSE_DVBUSP_Pos</a>)</td></tr>
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<tr class="separator:gaa0f53728ef57cfd0c9099458e5ede08b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4dc9a44df3a6bf09319feb0ade70219b" id="r_ga4dc9a44df3a6bf09319feb0ade70219b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4dc9a44df3a6bf09319feb0ade70219b">USB_OTG_DVBUSPULSE_DVBUSP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0f53728ef57cfd0c9099458e5ede08b">USB_OTG_DVBUSPULSE_DVBUSP_Msk</a></td></tr>
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<tr class="separator:ga4dc9a44df3a6bf09319feb0ade70219b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39a026cf1344c10820c26d7b2c6e6d05" id="r_ga39a026cf1344c10820c26d7b2c6e6d05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39a026cf1344c10820c26d7b2c6e6d05">USB_OTG_GNPTXSTS_NPTXFSAV_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga39a026cf1344c10820c26d7b2c6e6d05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f2d1e26e3ce0e261b8fbe6fe2797edc" id="r_ga8f2d1e26e3ce0e261b8fbe6fe2797edc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f2d1e26e3ce0e261b8fbe6fe2797edc">USB_OTG_GNPTXSTS_NPTXFSAV_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga39a026cf1344c10820c26d7b2c6e6d05">USB_OTG_GNPTXSTS_NPTXFSAV_Pos</a>)</td></tr>
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<tr class="memitem:ga8e0f0efb60ff9965a1ef407bb36b0c9b" id="r_ga8e0f0efb60ff9965a1ef407bb36b0c9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e0f0efb60ff9965a1ef407bb36b0c9b">USB_OTG_GNPTXSTS_NPTXFSAV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8f2d1e26e3ce0e261b8fbe6fe2797edc">USB_OTG_GNPTXSTS_NPTXFSAV_Msk</a></td></tr>
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<tr class="separator:ga8e0f0efb60ff9965a1ef407bb36b0c9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cc6b3fe2c33634188cb47dd7c4c79be" id="r_ga5cc6b3fe2c33634188cb47dd7c4c79be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be">USB_OTG_GNPTXSTS_NPTQXSAV_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga5cc6b3fe2c33634188cb47dd7c4c79be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca3b71a13949ca23c81dfd7901d5078e" id="r_gaca3b71a13949ca23c81dfd7901d5078e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca3b71a13949ca23c81dfd7901d5078e">USB_OTG_GNPTXSTS_NPTQXSAV_Msk</a>   (0xFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be">USB_OTG_GNPTXSTS_NPTQXSAV_Pos</a>)</td></tr>
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<tr class="separator:gaca3b71a13949ca23c81dfd7901d5078e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0dbb974d940609afd19b073574c40019" id="r_ga0dbb974d940609afd19b073574c40019"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0dbb974d940609afd19b073574c40019">USB_OTG_GNPTXSTS_NPTQXSAV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaca3b71a13949ca23c81dfd7901d5078e">USB_OTG_GNPTXSTS_NPTQXSAV_Msk</a></td></tr>
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<tr class="separator:ga0dbb974d940609afd19b073574c40019"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7731a3940c52add8741a9102d1d921b4" id="r_ga7731a3940c52add8741a9102d1d921b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7731a3940c52add8741a9102d1d921b4">USB_OTG_GNPTXSTS_NPTQXSAV_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be">USB_OTG_GNPTXSTS_NPTQXSAV_Pos</a>)</td></tr>
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<tr class="separator:ga7731a3940c52add8741a9102d1d921b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaead027a78b6c561c4ab16a7b138373c" id="r_gaaead027a78b6c561c4ab16a7b138373c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaead027a78b6c561c4ab16a7b138373c">USB_OTG_GNPTXSTS_NPTQXSAV_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be">USB_OTG_GNPTXSTS_NPTQXSAV_Pos</a>)</td></tr>
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<tr class="separator:gaaead027a78b6c561c4ab16a7b138373c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0af12c08cce383a26e0eef3c6a6fa72" id="r_gae0af12c08cce383a26e0eef3c6a6fa72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0af12c08cce383a26e0eef3c6a6fa72">USB_OTG_GNPTXSTS_NPTQXSAV_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be">USB_OTG_GNPTXSTS_NPTQXSAV_Pos</a>)</td></tr>
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<tr class="separator:gae0af12c08cce383a26e0eef3c6a6fa72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga896f6671b046ebcba5dde1f267508c2f" id="r_ga896f6671b046ebcba5dde1f267508c2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga896f6671b046ebcba5dde1f267508c2f">USB_OTG_GNPTXSTS_NPTQXSAV_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be">USB_OTG_GNPTXSTS_NPTQXSAV_Pos</a>)</td></tr>
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<tr class="separator:ga896f6671b046ebcba5dde1f267508c2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga207fc30605e39e471f9790f69e3fac74" id="r_ga207fc30605e39e471f9790f69e3fac74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga207fc30605e39e471f9790f69e3fac74">USB_OTG_GNPTXSTS_NPTQXSAV_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be">USB_OTG_GNPTXSTS_NPTQXSAV_Pos</a>)</td></tr>
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<tr class="separator:ga207fc30605e39e471f9790f69e3fac74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d2c61ea0a8811b95ea5880adf869e0b" id="r_ga0d2c61ea0a8811b95ea5880adf869e0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d2c61ea0a8811b95ea5880adf869e0b">USB_OTG_GNPTXSTS_NPTQXSAV_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be">USB_OTG_GNPTXSTS_NPTQXSAV_Pos</a>)</td></tr>
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<tr class="separator:ga0d2c61ea0a8811b95ea5880adf869e0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga787291b79ab2b19dcd87a188a8ad0c7b" id="r_ga787291b79ab2b19dcd87a188a8ad0c7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga787291b79ab2b19dcd87a188a8ad0c7b">USB_OTG_GNPTXSTS_NPTQXSAV_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be">USB_OTG_GNPTXSTS_NPTQXSAV_Pos</a>)</td></tr>
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<tr class="separator:ga787291b79ab2b19dcd87a188a8ad0c7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1212da7f367d7ccc3bb3db806c0293c" id="r_gac1212da7f367d7ccc3bb3db806c0293c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1212da7f367d7ccc3bb3db806c0293c">USB_OTG_GNPTXSTS_NPTQXSAV_7</a>   (0x80UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be">USB_OTG_GNPTXSTS_NPTQXSAV_Pos</a>)</td></tr>
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<tr class="separator:gac1212da7f367d7ccc3bb3db806c0293c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3fecb494258b9c4565f90696e76a599" id="r_gac3fecb494258b9c4565f90696e76a599"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3fecb494258b9c4565f90696e76a599">USB_OTG_GNPTXSTS_NPTXQTOP_Pos</a>   (24U)</td></tr>
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<tr class="separator:gac3fecb494258b9c4565f90696e76a599"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga730120d7b71007fb05f5e74b8d3e6264" id="r_ga730120d7b71007fb05f5e74b8d3e6264"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga730120d7b71007fb05f5e74b8d3e6264">USB_OTG_GNPTXSTS_NPTXQTOP_Msk</a>   (0x7FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3fecb494258b9c4565f90696e76a599">USB_OTG_GNPTXSTS_NPTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:ga730120d7b71007fb05f5e74b8d3e6264"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga111271d7bfdc7155f029c2402d2bac41" id="r_ga111271d7bfdc7155f029c2402d2bac41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga111271d7bfdc7155f029c2402d2bac41">USB_OTG_GNPTXSTS_NPTXQTOP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga730120d7b71007fb05f5e74b8d3e6264">USB_OTG_GNPTXSTS_NPTXQTOP_Msk</a></td></tr>
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<tr class="separator:ga111271d7bfdc7155f029c2402d2bac41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e940aac39f5922c0b7c6ffa797ce691" id="r_ga6e940aac39f5922c0b7c6ffa797ce691"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e940aac39f5922c0b7c6ffa797ce691">USB_OTG_GNPTXSTS_NPTXQTOP_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3fecb494258b9c4565f90696e76a599">USB_OTG_GNPTXSTS_NPTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:ga6e940aac39f5922c0b7c6ffa797ce691"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4ff80fe229f3a0ca31450cf037ad3117" id="r_ga4ff80fe229f3a0ca31450cf037ad3117"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4ff80fe229f3a0ca31450cf037ad3117">USB_OTG_GNPTXSTS_NPTXQTOP_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3fecb494258b9c4565f90696e76a599">USB_OTG_GNPTXSTS_NPTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:ga4ff80fe229f3a0ca31450cf037ad3117"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb3f5554d1d052c25cba115f406d6f07" id="r_gacb3f5554d1d052c25cba115f406d6f07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacb3f5554d1d052c25cba115f406d6f07">USB_OTG_GNPTXSTS_NPTXQTOP_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3fecb494258b9c4565f90696e76a599">USB_OTG_GNPTXSTS_NPTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:gacb3f5554d1d052c25cba115f406d6f07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9fd208770d7a63c0c031fed2b650d19" id="r_gab9fd208770d7a63c0c031fed2b650d19"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab9fd208770d7a63c0c031fed2b650d19">USB_OTG_GNPTXSTS_NPTXQTOP_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3fecb494258b9c4565f90696e76a599">USB_OTG_GNPTXSTS_NPTXQTOP_Pos</a>)</td></tr>
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<tr class="separator:gab9fd208770d7a63c0c031fed2b650d19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga963a180ae1705b5161555d23fc8f9a1e" id="r_ga963a180ae1705b5161555d23fc8f9a1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga963a180ae1705b5161555d23fc8f9a1e">USB_OTG_GNPTXSTS_NPTXQTOP_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3fecb494258b9c4565f90696e76a599">USB_OTG_GNPTXSTS_NPTXQTOP_Pos</a>)</td></tr>
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<tr class="memitem:gad681db11aef73b8b65b2528f31fa9668" id="r_gad681db11aef73b8b65b2528f31fa9668"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad681db11aef73b8b65b2528f31fa9668">USB_OTG_GNPTXSTS_NPTXQTOP_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3fecb494258b9c4565f90696e76a599">USB_OTG_GNPTXSTS_NPTXQTOP_Pos</a>)</td></tr>
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<tr class="memitem:gaba22a705c0bd9f3c18a22afcddd3edc4" id="r_gaba22a705c0bd9f3c18a22afcddd3edc4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba22a705c0bd9f3c18a22afcddd3edc4">USB_OTG_GNPTXSTS_NPTXQTOP_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac3fecb494258b9c4565f90696e76a599">USB_OTG_GNPTXSTS_NPTXQTOP_Pos</a>)</td></tr>
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<tr class="memitem:gaa27b3b7a9c8d5bd43eeed11c120b6b94" id="r_gaa27b3b7a9c8d5bd43eeed11c120b6b94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa27b3b7a9c8d5bd43eeed11c120b6b94">USB_OTG_DTHRCTL_NONISOTHREN_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gafb5a75e2c30cc44403d12a7fa3f3bbd6" id="r_gafb5a75e2c30cc44403d12a7fa3f3bbd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb5a75e2c30cc44403d12a7fa3f3bbd6">USB_OTG_DTHRCTL_NONISOTHREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa27b3b7a9c8d5bd43eeed11c120b6b94">USB_OTG_DTHRCTL_NONISOTHREN_Pos</a>)</td></tr>
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<tr class="memitem:ga90deedb84e953f01c80f382926cc07f7" id="r_ga90deedb84e953f01c80f382926cc07f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90deedb84e953f01c80f382926cc07f7">USB_OTG_DTHRCTL_NONISOTHREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafb5a75e2c30cc44403d12a7fa3f3bbd6">USB_OTG_DTHRCTL_NONISOTHREN_Msk</a></td></tr>
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<tr class="memitem:gacad27878401eaeb8cbf31bcca1aec333" id="r_gacad27878401eaeb8cbf31bcca1aec333"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacad27878401eaeb8cbf31bcca1aec333">USB_OTG_DTHRCTL_ISOTHREN_Pos</a>   (1U)</td></tr>
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<tr class="memitem:gace1a2aa524f45130efc83e053acb865b" id="r_gace1a2aa524f45130efc83e053acb865b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace1a2aa524f45130efc83e053acb865b">USB_OTG_DTHRCTL_ISOTHREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacad27878401eaeb8cbf31bcca1aec333">USB_OTG_DTHRCTL_ISOTHREN_Pos</a>)</td></tr>
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<tr class="separator:gace1a2aa524f45130efc83e053acb865b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04e741a79f38ab24adc52bd7143af049" id="r_ga04e741a79f38ab24adc52bd7143af049"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04e741a79f38ab24adc52bd7143af049">USB_OTG_DTHRCTL_ISOTHREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gace1a2aa524f45130efc83e053acb865b">USB_OTG_DTHRCTL_ISOTHREN_Msk</a></td></tr>
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<tr class="memitem:gab8369129264871f2a808694ae56b143a" id="r_gab8369129264871f2a808694ae56b143a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>   (2U)</td></tr>
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<tr class="memitem:ga43e14dc940b6baf117c256d9c60aa2e0" id="r_ga43e14dc940b6baf117c256d9c60aa2e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga43e14dc940b6baf117c256d9c60aa2e0">USB_OTG_DTHRCTL_TXTHRLEN_Msk</a>   (0x1FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:ga43e14dc940b6baf117c256d9c60aa2e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89abc875678e55dd6f0404d06fd71ac4" id="r_ga89abc875678e55dd6f0404d06fd71ac4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89abc875678e55dd6f0404d06fd71ac4">USB_OTG_DTHRCTL_TXTHRLEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga43e14dc940b6baf117c256d9c60aa2e0">USB_OTG_DTHRCTL_TXTHRLEN_Msk</a></td></tr>
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<tr class="separator:ga89abc875678e55dd6f0404d06fd71ac4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6dc7e5363efa0a295aa92980b6cc04fa" id="r_ga6dc7e5363efa0a295aa92980b6cc04fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6dc7e5363efa0a295aa92980b6cc04fa">USB_OTG_DTHRCTL_TXTHRLEN_0</a>   (0x001UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:ga6dc7e5363efa0a295aa92980b6cc04fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77e5b0ffa7872b1a86a5c1b595e1010e" id="r_ga77e5b0ffa7872b1a86a5c1b595e1010e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77e5b0ffa7872b1a86a5c1b595e1010e">USB_OTG_DTHRCTL_TXTHRLEN_1</a>   (0x002UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:ga77e5b0ffa7872b1a86a5c1b595e1010e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05f69f648818f4c055d939afc66946ae" id="r_ga05f69f648818f4c055d939afc66946ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05f69f648818f4c055d939afc66946ae">USB_OTG_DTHRCTL_TXTHRLEN_2</a>   (0x004UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:ga05f69f648818f4c055d939afc66946ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf30c1d04c0cdd9d55beae15953ec7693" id="r_gaf30c1d04c0cdd9d55beae15953ec7693"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf30c1d04c0cdd9d55beae15953ec7693">USB_OTG_DTHRCTL_TXTHRLEN_3</a>   (0x008UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:gaf30c1d04c0cdd9d55beae15953ec7693"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49b7ac9081652b86cba455dd0241ec67" id="r_ga49b7ac9081652b86cba455dd0241ec67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49b7ac9081652b86cba455dd0241ec67">USB_OTG_DTHRCTL_TXTHRLEN_4</a>   (0x010UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>)</td></tr>
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<tr class="memitem:ga5adde0e7e9543650a413afa08241a990" id="r_ga5adde0e7e9543650a413afa08241a990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5adde0e7e9543650a413afa08241a990">USB_OTG_DTHRCTL_TXTHRLEN_5</a>   (0x020UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>)</td></tr>
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<tr class="memitem:ga13d34b0ad2fc0bb5c9fef41cf8d139a2" id="r_ga13d34b0ad2fc0bb5c9fef41cf8d139a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13d34b0ad2fc0bb5c9fef41cf8d139a2">USB_OTG_DTHRCTL_TXTHRLEN_6</a>   (0x040UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:ga13d34b0ad2fc0bb5c9fef41cf8d139a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga86ac850ea713f1545dcd207e2e5bd104" id="r_ga86ac850ea713f1545dcd207e2e5bd104"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86ac850ea713f1545dcd207e2e5bd104">USB_OTG_DTHRCTL_TXTHRLEN_7</a>   (0x080UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>)</td></tr>
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<tr class="memitem:ga4eafc52de58d4605d63ba125ceb08e93" id="r_ga4eafc52de58d4605d63ba125ceb08e93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4eafc52de58d4605d63ba125ceb08e93">USB_OTG_DTHRCTL_TXTHRLEN_8</a>   (0x100UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a">USB_OTG_DTHRCTL_TXTHRLEN_Pos</a>)</td></tr>
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<tr class="memitem:ga18423f010a887869d9240587099fb245" id="r_ga18423f010a887869d9240587099fb245"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18423f010a887869d9240587099fb245">USB_OTG_DTHRCTL_RXTHREN_Pos</a>   (16U)</td></tr>
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<tr class="memitem:gad7ea756a244f4f1c30f3d1feab40f90d" id="r_gad7ea756a244f4f1c30f3d1feab40f90d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7ea756a244f4f1c30f3d1feab40f90d">USB_OTG_DTHRCTL_RXTHREN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga18423f010a887869d9240587099fb245">USB_OTG_DTHRCTL_RXTHREN_Pos</a>)</td></tr>
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<tr class="separator:gad7ea756a244f4f1c30f3d1feab40f90d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccd6ccdda30038743b8857ec89c897d0" id="r_gaccd6ccdda30038743b8857ec89c897d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaccd6ccdda30038743b8857ec89c897d0">USB_OTG_DTHRCTL_RXTHREN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad7ea756a244f4f1c30f3d1feab40f90d">USB_OTG_DTHRCTL_RXTHREN_Msk</a></td></tr>
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<tr class="memitem:ga989aba6821e2352c5690961510aad20c" id="r_ga989aba6821e2352c5690961510aad20c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>   (17U)</td></tr>
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<tr class="memitem:ga86e3d673a7dffea2edb0212199ca55d8" id="r_ga86e3d673a7dffea2edb0212199ca55d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86e3d673a7dffea2edb0212199ca55d8">USB_OTG_DTHRCTL_RXTHRLEN_Msk</a>   (0x1FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:ga86e3d673a7dffea2edb0212199ca55d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33dd5d34180983c398a1944eafd47fac" id="r_ga33dd5d34180983c398a1944eafd47fac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33dd5d34180983c398a1944eafd47fac">USB_OTG_DTHRCTL_RXTHRLEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga86e3d673a7dffea2edb0212199ca55d8">USB_OTG_DTHRCTL_RXTHRLEN_Msk</a></td></tr>
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<tr class="memitem:gabfb6edd2de6ee8c4680a604711920b83" id="r_gabfb6edd2de6ee8c4680a604711920b83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabfb6edd2de6ee8c4680a604711920b83">USB_OTG_DTHRCTL_RXTHRLEN_0</a>   (0x001UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:gabfb6edd2de6ee8c4680a604711920b83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga933148ffeb4784606b66a3229d77b921" id="r_ga933148ffeb4784606b66a3229d77b921"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga933148ffeb4784606b66a3229d77b921">USB_OTG_DTHRCTL_RXTHRLEN_1</a>   (0x002UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>)</td></tr>
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<tr class="memitem:ga4208cac73e194db119277ed12a69eedd" id="r_ga4208cac73e194db119277ed12a69eedd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4208cac73e194db119277ed12a69eedd">USB_OTG_DTHRCTL_RXTHRLEN_2</a>   (0x004UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>)</td></tr>
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<tr class="memitem:ga1c499a8120b848257819105790c44aef" id="r_ga1c499a8120b848257819105790c44aef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1c499a8120b848257819105790c44aef">USB_OTG_DTHRCTL_RXTHRLEN_3</a>   (0x008UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:ga1c499a8120b848257819105790c44aef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b8e7493d15184845243110b44ef4e45" id="r_ga5b8e7493d15184845243110b44ef4e45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b8e7493d15184845243110b44ef4e45">USB_OTG_DTHRCTL_RXTHRLEN_4</a>   (0x010UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:ga5b8e7493d15184845243110b44ef4e45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1a10cc9b79775c3c0067a1b005862f0" id="r_gac1a10cc9b79775c3c0067a1b005862f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1a10cc9b79775c3c0067a1b005862f0">USB_OTG_DTHRCTL_RXTHRLEN_5</a>   (0x020UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:gac1a10cc9b79775c3c0067a1b005862f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee1447a1041c5a2b2a88fd2edacb9cdf" id="r_gaee1447a1041c5a2b2a88fd2edacb9cdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee1447a1041c5a2b2a88fd2edacb9cdf">USB_OTG_DTHRCTL_RXTHRLEN_6</a>   (0x040UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:gaee1447a1041c5a2b2a88fd2edacb9cdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f753e4d8650b04a44a092c7581cda36" id="r_ga2f753e4d8650b04a44a092c7581cda36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f753e4d8650b04a44a092c7581cda36">USB_OTG_DTHRCTL_RXTHRLEN_7</a>   (0x080UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:ga2f753e4d8650b04a44a092c7581cda36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb2dbf9b5e747cff136273b67258c36e" id="r_gabb2dbf9b5e747cff136273b67258c36e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb2dbf9b5e747cff136273b67258c36e">USB_OTG_DTHRCTL_RXTHRLEN_8</a>   (0x100UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c">USB_OTG_DTHRCTL_RXTHRLEN_Pos</a>)</td></tr>
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<tr class="separator:gabb2dbf9b5e747cff136273b67258c36e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1905c98a839664f140afc08295b0e5a2" id="r_ga1905c98a839664f140afc08295b0e5a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1905c98a839664f140afc08295b0e5a2">USB_OTG_DTHRCTL_ARPEN_Pos</a>   (27U)</td></tr>
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<tr class="separator:ga1905c98a839664f140afc08295b0e5a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac23e9fc77b37f86b49a3e6f9bb4f711b" id="r_gac23e9fc77b37f86b49a3e6f9bb4f711b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac23e9fc77b37f86b49a3e6f9bb4f711b">USB_OTG_DTHRCTL_ARPEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1905c98a839664f140afc08295b0e5a2">USB_OTG_DTHRCTL_ARPEN_Pos</a>)</td></tr>
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<tr class="separator:gac23e9fc77b37f86b49a3e6f9bb4f711b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gababbacdcc33bdd2be91513fd31c4efbc" id="r_gababbacdcc33bdd2be91513fd31c4efbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gababbacdcc33bdd2be91513fd31c4efbc">USB_OTG_DTHRCTL_ARPEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac23e9fc77b37f86b49a3e6f9bb4f711b">USB_OTG_DTHRCTL_ARPEN_Msk</a></td></tr>
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<tr class="separator:gababbacdcc33bdd2be91513fd31c4efbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga417e459f4724862c9832ec1a3762774c" id="r_ga417e459f4724862c9832ec1a3762774c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga417e459f4724862c9832ec1a3762774c">USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga417e459f4724862c9832ec1a3762774c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e5d9742bbb59530bdf7648a369aa31a" id="r_ga8e5d9742bbb59530bdf7648a369aa31a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8e5d9742bbb59530bdf7648a369aa31a">USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga417e459f4724862c9832ec1a3762774c">USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos</a>)</td></tr>
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<tr class="separator:ga8e5d9742bbb59530bdf7648a369aa31a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8129b6a9f51c5131fb60ae0b92887af" id="r_gac8129b6a9f51c5131fb60ae0b92887af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8129b6a9f51c5131fb60ae0b92887af">USB_OTG_DIEPEMPMSK_INEPTXFEM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8e5d9742bbb59530bdf7648a369aa31a">USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk</a></td></tr>
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<tr class="separator:gac8129b6a9f51c5131fb60ae0b92887af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga199c8da83c26360084406b7ead8f5d3b" id="r_ga199c8da83c26360084406b7ead8f5d3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga199c8da83c26360084406b7ead8f5d3b">USB_OTG_DEACHINT_IEP1INT_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga199c8da83c26360084406b7ead8f5d3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad029d48387a2d3e0e29661bab1848c41" id="r_gad029d48387a2d3e0e29661bab1848c41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad029d48387a2d3e0e29661bab1848c41">USB_OTG_DEACHINT_IEP1INT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga199c8da83c26360084406b7ead8f5d3b">USB_OTG_DEACHINT_IEP1INT_Pos</a>)</td></tr>
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<tr class="separator:gad029d48387a2d3e0e29661bab1848c41"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc58bf6e4389a56f5482f3c3b9f0afae" id="r_gadc58bf6e4389a56f5482f3c3b9f0afae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadc58bf6e4389a56f5482f3c3b9f0afae">USB_OTG_DEACHINT_IEP1INT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad029d48387a2d3e0e29661bab1848c41">USB_OTG_DEACHINT_IEP1INT_Msk</a></td></tr>
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<tr class="separator:gadc58bf6e4389a56f5482f3c3b9f0afae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68088b39445739349ceaf47186f57b80" id="r_ga68088b39445739349ceaf47186f57b80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68088b39445739349ceaf47186f57b80">USB_OTG_DEACHINT_OEP1INT_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga68088b39445739349ceaf47186f57b80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15176fb77b4e56480776944239113e2d" id="r_ga15176fb77b4e56480776944239113e2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga15176fb77b4e56480776944239113e2d">USB_OTG_DEACHINT_OEP1INT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68088b39445739349ceaf47186f57b80">USB_OTG_DEACHINT_OEP1INT_Pos</a>)</td></tr>
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<tr class="separator:ga15176fb77b4e56480776944239113e2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga303cb170236d7f710cc125fb1af37179" id="r_ga303cb170236d7f710cc125fb1af37179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga303cb170236d7f710cc125fb1af37179">USB_OTG_DEACHINT_OEP1INT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga15176fb77b4e56480776944239113e2d">USB_OTG_DEACHINT_OEP1INT_Msk</a></td></tr>
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<tr class="separator:ga303cb170236d7f710cc125fb1af37179"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa044953a65f22022f0b54cf1f35216cc" id="r_gaa044953a65f22022f0b54cf1f35216cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa044953a65f22022f0b54cf1f35216cc">USB_OTG_GCCFG_PWRDWN_Pos</a>   (16U)</td></tr>
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<tr class="separator:gaa044953a65f22022f0b54cf1f35216cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga29705f28087b457d2e6d6ade469b8da8" id="r_ga29705f28087b457d2e6d6ade469b8da8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga29705f28087b457d2e6d6ade469b8da8">USB_OTG_GCCFG_PWRDWN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa044953a65f22022f0b54cf1f35216cc">USB_OTG_GCCFG_PWRDWN_Pos</a>)</td></tr>
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<tr class="separator:ga29705f28087b457d2e6d6ade469b8da8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c298cedbc73302fae613084ad098b22" id="r_ga4c298cedbc73302fae613084ad098b22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c298cedbc73302fae613084ad098b22">USB_OTG_GCCFG_PWRDWN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga29705f28087b457d2e6d6ade469b8da8">USB_OTG_GCCFG_PWRDWN_Msk</a></td></tr>
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<tr class="separator:ga4c298cedbc73302fae613084ad098b22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bd96a2a753042888490b2d8b5cdae0f" id="r_ga5bd96a2a753042888490b2d8b5cdae0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bd96a2a753042888490b2d8b5cdae0f">USB_OTG_GCCFG_I2CPADEN_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga5bd96a2a753042888490b2d8b5cdae0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4d5a74bbfa9c61ca56b7b1f5a511dd3" id="r_gaa4d5a74bbfa9c61ca56b7b1f5a511dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4d5a74bbfa9c61ca56b7b1f5a511dd3">USB_OTG_GCCFG_I2CPADEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bd96a2a753042888490b2d8b5cdae0f">USB_OTG_GCCFG_I2CPADEN_Pos</a>)</td></tr>
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<tr class="separator:gaa4d5a74bbfa9c61ca56b7b1f5a511dd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga048469450e7d634cafa2e5677e5182b3" id="r_ga048469450e7d634cafa2e5677e5182b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga048469450e7d634cafa2e5677e5182b3">USB_OTG_GCCFG_I2CPADEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa4d5a74bbfa9c61ca56b7b1f5a511dd3">USB_OTG_GCCFG_I2CPADEN_Msk</a></td></tr>
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<tr class="separator:ga048469450e7d634cafa2e5677e5182b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa59fa04d9f6d8e352b2a880b2cdd6163" id="r_gaa59fa04d9f6d8e352b2a880b2cdd6163"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa59fa04d9f6d8e352b2a880b2cdd6163">USB_OTG_GCCFG_VBUSASEN_Pos</a>   (18U)</td></tr>
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<tr class="separator:gaa59fa04d9f6d8e352b2a880b2cdd6163"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa234c38562741de2c25aa2d87a53b2b9" id="r_gaa234c38562741de2c25aa2d87a53b2b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa234c38562741de2c25aa2d87a53b2b9">USB_OTG_GCCFG_VBUSASEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa59fa04d9f6d8e352b2a880b2cdd6163">USB_OTG_GCCFG_VBUSASEN_Pos</a>)</td></tr>
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<tr class="separator:gaa234c38562741de2c25aa2d87a53b2b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga83a0db31f98476dc46d77a77475c2991" id="r_ga83a0db31f98476dc46d77a77475c2991"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga83a0db31f98476dc46d77a77475c2991">USB_OTG_GCCFG_VBUSASEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa234c38562741de2c25aa2d87a53b2b9">USB_OTG_GCCFG_VBUSASEN_Msk</a></td></tr>
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<tr class="separator:ga83a0db31f98476dc46d77a77475c2991"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90a2fb91409323a578610f09cac80a12" id="r_ga90a2fb91409323a578610f09cac80a12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90a2fb91409323a578610f09cac80a12">USB_OTG_GCCFG_VBUSBSEN_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga90a2fb91409323a578610f09cac80a12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11b625bb997a725e1965d4a678f0bea4" id="r_ga11b625bb997a725e1965d4a678f0bea4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga11b625bb997a725e1965d4a678f0bea4">USB_OTG_GCCFG_VBUSBSEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga90a2fb91409323a578610f09cac80a12">USB_OTG_GCCFG_VBUSBSEN_Pos</a>)</td></tr>
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<tr class="separator:ga11b625bb997a725e1965d4a678f0bea4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1aa57c29a5c04621f54b2125536d11b2" id="r_ga1aa57c29a5c04621f54b2125536d11b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1aa57c29a5c04621f54b2125536d11b2">USB_OTG_GCCFG_VBUSBSEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga11b625bb997a725e1965d4a678f0bea4">USB_OTG_GCCFG_VBUSBSEN_Msk</a></td></tr>
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<tr class="separator:ga1aa57c29a5c04621f54b2125536d11b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36422f7842d3381290b5c7f1e1d920c8" id="r_ga36422f7842d3381290b5c7f1e1d920c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga36422f7842d3381290b5c7f1e1d920c8">USB_OTG_GCCFG_SOFOUTEN_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga36422f7842d3381290b5c7f1e1d920c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e05968150501b4f565898b43d33aed8" id="r_ga3e05968150501b4f565898b43d33aed8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e05968150501b4f565898b43d33aed8">USB_OTG_GCCFG_SOFOUTEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga36422f7842d3381290b5c7f1e1d920c8">USB_OTG_GCCFG_SOFOUTEN_Pos</a>)</td></tr>
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<tr class="separator:ga3e05968150501b4f565898b43d33aed8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3caba9befa711f3bdeb99e0ed33d608" id="r_gac3caba9befa711f3bdeb99e0ed33d608"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3caba9befa711f3bdeb99e0ed33d608">USB_OTG_GCCFG_SOFOUTEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e05968150501b4f565898b43d33aed8">USB_OTG_GCCFG_SOFOUTEN_Msk</a></td></tr>
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<tr class="separator:gac3caba9befa711f3bdeb99e0ed33d608"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga198d2b56aa36042fd5874d004d8a71f5" id="r_ga198d2b56aa36042fd5874d004d8a71f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga198d2b56aa36042fd5874d004d8a71f5">USB_OTG_GCCFG_NOVBUSSENS_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga198d2b56aa36042fd5874d004d8a71f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84a118dc6bff7012b8a6d944b15089b8" id="r_ga84a118dc6bff7012b8a6d944b15089b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84a118dc6bff7012b8a6d944b15089b8">USB_OTG_GCCFG_NOVBUSSENS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga198d2b56aa36042fd5874d004d8a71f5">USB_OTG_GCCFG_NOVBUSSENS_Pos</a>)</td></tr>
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<tr class="separator:ga84a118dc6bff7012b8a6d944b15089b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b38845c9338d0637983b3d81fc0c95d" id="r_ga4b38845c9338d0637983b3d81fc0c95d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b38845c9338d0637983b3d81fc0c95d">USB_OTG_GCCFG_NOVBUSSENS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga84a118dc6bff7012b8a6d944b15089b8">USB_OTG_GCCFG_NOVBUSSENS_Msk</a></td></tr>
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<tr class="separator:ga4b38845c9338d0637983b3d81fc0c95d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ee42186200d9099506cd4c8f877eba3" id="r_ga2ee42186200d9099506cd4c8f877eba3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ee42186200d9099506cd4c8f877eba3">USB_OTG_DEACHINTMSK_IEP1INTM_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga2ee42186200d9099506cd4c8f877eba3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8771cbb994263301333d9847621094e" id="r_gaa8771cbb994263301333d9847621094e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8771cbb994263301333d9847621094e">USB_OTG_DEACHINTMSK_IEP1INTM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ee42186200d9099506cd4c8f877eba3">USB_OTG_DEACHINTMSK_IEP1INTM_Pos</a>)</td></tr>
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<tr class="separator:gaa8771cbb994263301333d9847621094e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga258a2e60f2796217e28607252d4c57bf" id="r_ga258a2e60f2796217e28607252d4c57bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga258a2e60f2796217e28607252d4c57bf">USB_OTG_DEACHINTMSK_IEP1INTM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8771cbb994263301333d9847621094e">USB_OTG_DEACHINTMSK_IEP1INTM_Msk</a></td></tr>
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<tr class="separator:ga258a2e60f2796217e28607252d4c57bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2ddea2717e85931ae3085ef697f30311" id="r_ga2ddea2717e85931ae3085ef697f30311"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2ddea2717e85931ae3085ef697f30311">USB_OTG_DEACHINTMSK_OEP1INTM_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga2ddea2717e85931ae3085ef697f30311"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga429749723f28d5ac2c69768ec5340d17" id="r_ga429749723f28d5ac2c69768ec5340d17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga429749723f28d5ac2c69768ec5340d17">USB_OTG_DEACHINTMSK_OEP1INTM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2ddea2717e85931ae3085ef697f30311">USB_OTG_DEACHINTMSK_OEP1INTM_Pos</a>)</td></tr>
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<tr class="separator:ga429749723f28d5ac2c69768ec5340d17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1fc88b5e76ded044e77ec4bebbe91ec5" id="r_ga1fc88b5e76ded044e77ec4bebbe91ec5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1fc88b5e76ded044e77ec4bebbe91ec5">USB_OTG_DEACHINTMSK_OEP1INTM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga429749723f28d5ac2c69768ec5340d17">USB_OTG_DEACHINTMSK_OEP1INTM_Msk</a></td></tr>
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<tr class="separator:ga1fc88b5e76ded044e77ec4bebbe91ec5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga812e14aa406ecfa45f30df73aacbd611" id="r_ga812e14aa406ecfa45f30df73aacbd611"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga812e14aa406ecfa45f30df73aacbd611">USB_OTG_CID_PRODUCT_ID_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga812e14aa406ecfa45f30df73aacbd611"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c0749f0863635f439e2d8b760eeee17" id="r_ga2c0749f0863635f439e2d8b760eeee17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c0749f0863635f439e2d8b760eeee17">USB_OTG_CID_PRODUCT_ID_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga812e14aa406ecfa45f30df73aacbd611">USB_OTG_CID_PRODUCT_ID_Pos</a>)</td></tr>
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<tr class="separator:ga2c0749f0863635f439e2d8b760eeee17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bad40ec1b2cb101eaa49a5605f7a097" id="r_ga2bad40ec1b2cb101eaa49a5605f7a097"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bad40ec1b2cb101eaa49a5605f7a097">USB_OTG_CID_PRODUCT_ID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c0749f0863635f439e2d8b760eeee17">USB_OTG_CID_PRODUCT_ID_Msk</a></td></tr>
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<tr class="separator:ga2bad40ec1b2cb101eaa49a5605f7a097"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5be6178b3fbce4257db1b3272e5108b1" id="r_ga5be6178b3fbce4257db1b3272e5108b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5be6178b3fbce4257db1b3272e5108b1">USB_OTG_DIEPEACHMSK1_XFRCM_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5be6178b3fbce4257db1b3272e5108b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e1c74dcd04816e72d4dcb0cb87407bb" id="r_ga3e1c74dcd04816e72d4dcb0cb87407bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e1c74dcd04816e72d4dcb0cb87407bb">USB_OTG_DIEPEACHMSK1_XFRCM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5be6178b3fbce4257db1b3272e5108b1">USB_OTG_DIEPEACHMSK1_XFRCM_Pos</a>)</td></tr>
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<tr class="separator:ga3e1c74dcd04816e72d4dcb0cb87407bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3720d0a07deae3c6ff0c6c30c03543c" id="r_gaf3720d0a07deae3c6ff0c6c30c03543c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3720d0a07deae3c6ff0c6c30c03543c">USB_OTG_DIEPEACHMSK1_XFRCM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3e1c74dcd04816e72d4dcb0cb87407bb">USB_OTG_DIEPEACHMSK1_XFRCM_Msk</a></td></tr>
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<tr class="separator:gaf3720d0a07deae3c6ff0c6c30c03543c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae21af2079e378d491e4fb43a5048b422" id="r_gae21af2079e378d491e4fb43a5048b422"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae21af2079e378d491e4fb43a5048b422">USB_OTG_DIEPEACHMSK1_EPDM_Pos</a>   (1U)</td></tr>
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<tr class="separator:gae21af2079e378d491e4fb43a5048b422"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8cd0e0b574eba98114663d2eafcd3efd" id="r_ga8cd0e0b574eba98114663d2eafcd3efd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8cd0e0b574eba98114663d2eafcd3efd">USB_OTG_DIEPEACHMSK1_EPDM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae21af2079e378d491e4fb43a5048b422">USB_OTG_DIEPEACHMSK1_EPDM_Pos</a>)</td></tr>
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<tr class="separator:ga8cd0e0b574eba98114663d2eafcd3efd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62e4b8c28bb41136e5d6d3de217e5afd" id="r_ga62e4b8c28bb41136e5d6d3de217e5afd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62e4b8c28bb41136e5d6d3de217e5afd">USB_OTG_DIEPEACHMSK1_EPDM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8cd0e0b574eba98114663d2eafcd3efd">USB_OTG_DIEPEACHMSK1_EPDM_Msk</a></td></tr>
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<tr class="separator:ga62e4b8c28bb41136e5d6d3de217e5afd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7759259bb9b0d42d020b79d0fe3a8d1a" id="r_ga7759259bb9b0d42d020b79d0fe3a8d1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7759259bb9b0d42d020b79d0fe3a8d1a">USB_OTG_DIEPEACHMSK1_TOM_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga7759259bb9b0d42d020b79d0fe3a8d1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga460e8e6ba9daf019aa81f13d097a19fc" id="r_ga460e8e6ba9daf019aa81f13d097a19fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga460e8e6ba9daf019aa81f13d097a19fc">USB_OTG_DIEPEACHMSK1_TOM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7759259bb9b0d42d020b79d0fe3a8d1a">USB_OTG_DIEPEACHMSK1_TOM_Pos</a>)</td></tr>
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<tr class="separator:ga460e8e6ba9daf019aa81f13d097a19fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae910eb3d34714653d43579dcface4ead" id="r_gae910eb3d34714653d43579dcface4ead"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae910eb3d34714653d43579dcface4ead">USB_OTG_DIEPEACHMSK1_TOM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga460e8e6ba9daf019aa81f13d097a19fc">USB_OTG_DIEPEACHMSK1_TOM_Msk</a></td></tr>
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<tr class="separator:gae910eb3d34714653d43579dcface4ead"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8f0a7616486631d230baade93ed84d8" id="r_gad8f0a7616486631d230baade93ed84d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8f0a7616486631d230baade93ed84d8">USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos</a>   (4U)</td></tr>
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<tr class="separator:gad8f0a7616486631d230baade93ed84d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f86ddcb79c7f4467cdcd206e95dec7e" id="r_ga6f86ddcb79c7f4467cdcd206e95dec7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f86ddcb79c7f4467cdcd206e95dec7e">USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad8f0a7616486631d230baade93ed84d8">USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos</a>)</td></tr>
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<tr class="separator:ga6f86ddcb79c7f4467cdcd206e95dec7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96b7b0c15d5b36f6f3925e51d56990ac" id="r_ga96b7b0c15d5b36f6f3925e51d56990ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96b7b0c15d5b36f6f3925e51d56990ac">USB_OTG_DIEPEACHMSK1_ITTXFEMSK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f86ddcb79c7f4467cdcd206e95dec7e">USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk</a></td></tr>
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<tr class="separator:ga96b7b0c15d5b36f6f3925e51d56990ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabffd6dd8a5069f4eb0ceacde6f8b1c81" id="r_gabffd6dd8a5069f4eb0ceacde6f8b1c81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabffd6dd8a5069f4eb0ceacde6f8b1c81">USB_OTG_DIEPEACHMSK1_INEPNMM_Pos</a>   (5U)</td></tr>
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<tr class="separator:gabffd6dd8a5069f4eb0ceacde6f8b1c81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafdc16990fc5f01933112bbba2fa079a9" id="r_gafdc16990fc5f01933112bbba2fa079a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafdc16990fc5f01933112bbba2fa079a9">USB_OTG_DIEPEACHMSK1_INEPNMM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabffd6dd8a5069f4eb0ceacde6f8b1c81">USB_OTG_DIEPEACHMSK1_INEPNMM_Pos</a>)</td></tr>
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<tr class="separator:gafdc16990fc5f01933112bbba2fa079a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcc0f1fab9aac10d6edff07dde25d5bc" id="r_gafcc0f1fab9aac10d6edff07dde25d5bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafcc0f1fab9aac10d6edff07dde25d5bc">USB_OTG_DIEPEACHMSK1_INEPNMM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafdc16990fc5f01933112bbba2fa079a9">USB_OTG_DIEPEACHMSK1_INEPNMM_Msk</a></td></tr>
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<tr class="separator:gafcc0f1fab9aac10d6edff07dde25d5bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae45a7ceb9a2a0fe26a60b723e80d7f4b" id="r_gae45a7ceb9a2a0fe26a60b723e80d7f4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae45a7ceb9a2a0fe26a60b723e80d7f4b">USB_OTG_DIEPEACHMSK1_INEPNEM_Pos</a>   (6U)</td></tr>
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<tr class="separator:gae45a7ceb9a2a0fe26a60b723e80d7f4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga720ea28b3588862d6054ca5b13a7a883" id="r_ga720ea28b3588862d6054ca5b13a7a883"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga720ea28b3588862d6054ca5b13a7a883">USB_OTG_DIEPEACHMSK1_INEPNEM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae45a7ceb9a2a0fe26a60b723e80d7f4b">USB_OTG_DIEPEACHMSK1_INEPNEM_Pos</a>)</td></tr>
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<tr class="separator:ga720ea28b3588862d6054ca5b13a7a883"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8ee1bc04de47f522a90619d57086b06" id="r_gae8ee1bc04de47f522a90619d57086b06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8ee1bc04de47f522a90619d57086b06">USB_OTG_DIEPEACHMSK1_INEPNEM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga720ea28b3588862d6054ca5b13a7a883">USB_OTG_DIEPEACHMSK1_INEPNEM_Msk</a></td></tr>
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<tr class="separator:gae8ee1bc04de47f522a90619d57086b06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e8c4451b16845ea560b21c80640b4d6" id="r_ga0e8c4451b16845ea560b21c80640b4d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e8c4451b16845ea560b21c80640b4d6">USB_OTG_DIEPEACHMSK1_TXFURM_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga0e8c4451b16845ea560b21c80640b4d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga227ade985d4eb585dc25efe080981d66" id="r_ga227ade985d4eb585dc25efe080981d66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga227ade985d4eb585dc25efe080981d66">USB_OTG_DIEPEACHMSK1_TXFURM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e8c4451b16845ea560b21c80640b4d6">USB_OTG_DIEPEACHMSK1_TXFURM_Pos</a>)</td></tr>
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<tr class="separator:ga227ade985d4eb585dc25efe080981d66"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6c8f64ad39f7ca4fe195b0b03067866" id="r_gaa6c8f64ad39f7ca4fe195b0b03067866"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6c8f64ad39f7ca4fe195b0b03067866">USB_OTG_DIEPEACHMSK1_TXFURM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga227ade985d4eb585dc25efe080981d66">USB_OTG_DIEPEACHMSK1_TXFURM_Msk</a></td></tr>
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<tr class="separator:gaa6c8f64ad39f7ca4fe195b0b03067866"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c87f9f2c5c5eeedc735b455a1921afd" id="r_ga2c87f9f2c5c5eeedc735b455a1921afd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c87f9f2c5c5eeedc735b455a1921afd">USB_OTG_DIEPEACHMSK1_BIM_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga2c87f9f2c5c5eeedc735b455a1921afd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga942df01e1be13f057f2e7ecc286d1621" id="r_ga942df01e1be13f057f2e7ecc286d1621"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga942df01e1be13f057f2e7ecc286d1621">USB_OTG_DIEPEACHMSK1_BIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c87f9f2c5c5eeedc735b455a1921afd">USB_OTG_DIEPEACHMSK1_BIM_Pos</a>)</td></tr>
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<tr class="separator:ga942df01e1be13f057f2e7ecc286d1621"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac4445e5439cad7796d3fc5de74a2ed8" id="r_gaac4445e5439cad7796d3fc5de74a2ed8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac4445e5439cad7796d3fc5de74a2ed8">USB_OTG_DIEPEACHMSK1_BIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga942df01e1be13f057f2e7ecc286d1621">USB_OTG_DIEPEACHMSK1_BIM_Msk</a></td></tr>
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<tr class="separator:gaac4445e5439cad7796d3fc5de74a2ed8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe57f29d04c457e07e50a6cbcd273505" id="r_gabe57f29d04c457e07e50a6cbcd273505"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe57f29d04c457e07e50a6cbcd273505">USB_OTG_DIEPEACHMSK1_NAKM_Pos</a>   (13U)</td></tr>
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<tr class="separator:gabe57f29d04c457e07e50a6cbcd273505"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63e3d316ebc4d1b530ac5da37be23e6e" id="r_ga63e3d316ebc4d1b530ac5da37be23e6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63e3d316ebc4d1b530ac5da37be23e6e">USB_OTG_DIEPEACHMSK1_NAKM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabe57f29d04c457e07e50a6cbcd273505">USB_OTG_DIEPEACHMSK1_NAKM_Pos</a>)</td></tr>
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<tr class="separator:ga63e3d316ebc4d1b530ac5da37be23e6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa4089e9aeb641963584d76c932f78e06" id="r_gaa4089e9aeb641963584d76c932f78e06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa4089e9aeb641963584d76c932f78e06">USB_OTG_DIEPEACHMSK1_NAKM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63e3d316ebc4d1b530ac5da37be23e6e">USB_OTG_DIEPEACHMSK1_NAKM_Msk</a></td></tr>
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<tr class="separator:gaa4089e9aeb641963584d76c932f78e06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacd91baead77bc3be91bf92566210fca2" id="r_gacd91baead77bc3be91bf92566210fca2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacd91baead77bc3be91bf92566210fca2">USB_OTG_HPRT_PCSTS_Pos</a>   (0U)</td></tr>
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<tr class="separator:gacd91baead77bc3be91bf92566210fca2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6277ab1fc490e322b3da7f1ebab56dce" id="r_ga6277ab1fc490e322b3da7f1ebab56dce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6277ab1fc490e322b3da7f1ebab56dce">USB_OTG_HPRT_PCSTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacd91baead77bc3be91bf92566210fca2">USB_OTG_HPRT_PCSTS_Pos</a>)</td></tr>
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<tr class="separator:ga6277ab1fc490e322b3da7f1ebab56dce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01b303083e66f3018e57dbb275b6f4b5" id="r_ga01b303083e66f3018e57dbb275b6f4b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01b303083e66f3018e57dbb275b6f4b5">USB_OTG_HPRT_PCSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6277ab1fc490e322b3da7f1ebab56dce">USB_OTG_HPRT_PCSTS_Msk</a></td></tr>
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<tr class="separator:ga01b303083e66f3018e57dbb275b6f4b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20a5c1b6c67d02966503ed2867676c03" id="r_ga20a5c1b6c67d02966503ed2867676c03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20a5c1b6c67d02966503ed2867676c03">USB_OTG_HPRT_PCDET_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga20a5c1b6c67d02966503ed2867676c03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd445d6f75df03444eb8b978d39f1e6f" id="r_gafd445d6f75df03444eb8b978d39f1e6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafd445d6f75df03444eb8b978d39f1e6f">USB_OTG_HPRT_PCDET_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20a5c1b6c67d02966503ed2867676c03">USB_OTG_HPRT_PCDET_Pos</a>)</td></tr>
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<tr class="separator:gafd445d6f75df03444eb8b978d39f1e6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bd9f8a9da09f9d52f19b8e68551c285" id="r_ga1bd9f8a9da09f9d52f19b8e68551c285"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bd9f8a9da09f9d52f19b8e68551c285">USB_OTG_HPRT_PCDET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafd445d6f75df03444eb8b978d39f1e6f">USB_OTG_HPRT_PCDET_Msk</a></td></tr>
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<tr class="separator:ga1bd9f8a9da09f9d52f19b8e68551c285"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa45a500ec95308387eebdfb881c0fcfc" id="r_gaa45a500ec95308387eebdfb881c0fcfc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa45a500ec95308387eebdfb881c0fcfc">USB_OTG_HPRT_PENA_Pos</a>   (2U)</td></tr>
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<tr class="separator:gaa45a500ec95308387eebdfb881c0fcfc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8068309917d8be1de7bc9a2d9dea22e6" id="r_ga8068309917d8be1de7bc9a2d9dea22e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8068309917d8be1de7bc9a2d9dea22e6">USB_OTG_HPRT_PENA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa45a500ec95308387eebdfb881c0fcfc">USB_OTG_HPRT_PENA_Pos</a>)</td></tr>
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<tr class="separator:ga8068309917d8be1de7bc9a2d9dea22e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga95ad10f10631095aeb7a27e0475242f0" id="r_ga95ad10f10631095aeb7a27e0475242f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga95ad10f10631095aeb7a27e0475242f0">USB_OTG_HPRT_PENA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8068309917d8be1de7bc9a2d9dea22e6">USB_OTG_HPRT_PENA_Msk</a></td></tr>
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<tr class="separator:ga95ad10f10631095aeb7a27e0475242f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga47e25510c52062775f4155eb233a4bca" id="r_ga47e25510c52062775f4155eb233a4bca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga47e25510c52062775f4155eb233a4bca">USB_OTG_HPRT_PENCHNG_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga47e25510c52062775f4155eb233a4bca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2e7655490c7bdff631166769d46838d" id="r_gae2e7655490c7bdff631166769d46838d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2e7655490c7bdff631166769d46838d">USB_OTG_HPRT_PENCHNG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga47e25510c52062775f4155eb233a4bca">USB_OTG_HPRT_PENCHNG_Pos</a>)</td></tr>
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<tr class="separator:gae2e7655490c7bdff631166769d46838d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d84be9a2f9c7f8750ee448c99164821" id="r_ga7d84be9a2f9c7f8750ee448c99164821"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d84be9a2f9c7f8750ee448c99164821">USB_OTG_HPRT_PENCHNG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae2e7655490c7bdff631166769d46838d">USB_OTG_HPRT_PENCHNG_Msk</a></td></tr>
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<tr class="separator:ga7d84be9a2f9c7f8750ee448c99164821"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3602a595b6dd2c43483e6df37567ebc" id="r_gab3602a595b6dd2c43483e6df37567ebc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3602a595b6dd2c43483e6df37567ebc">USB_OTG_HPRT_POCA_Pos</a>   (4U)</td></tr>
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<tr class="separator:gab3602a595b6dd2c43483e6df37567ebc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf14c79e04bc40d676bb24be0b41145ca" id="r_gaf14c79e04bc40d676bb24be0b41145ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf14c79e04bc40d676bb24be0b41145ca">USB_OTG_HPRT_POCA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab3602a595b6dd2c43483e6df37567ebc">USB_OTG_HPRT_POCA_Pos</a>)</td></tr>
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<tr class="separator:gaf14c79e04bc40d676bb24be0b41145ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4d510d6215d72faac65ad3109f009af" id="r_gac4d510d6215d72faac65ad3109f009af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac4d510d6215d72faac65ad3109f009af">USB_OTG_HPRT_POCA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf14c79e04bc40d676bb24be0b41145ca">USB_OTG_HPRT_POCA_Msk</a></td></tr>
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<tr class="memitem:gac12d375e01d04a960d38b26dd2e8685f" id="r_gac12d375e01d04a960d38b26dd2e8685f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac12d375e01d04a960d38b26dd2e8685f">USB_OTG_HPRT_POCCHNG_Pos</a>   (5U)</td></tr>
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<tr class="separator:gac12d375e01d04a960d38b26dd2e8685f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63a4749bf5614ee8388364463ef039d6" id="r_ga63a4749bf5614ee8388364463ef039d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63a4749bf5614ee8388364463ef039d6">USB_OTG_HPRT_POCCHNG_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac12d375e01d04a960d38b26dd2e8685f">USB_OTG_HPRT_POCCHNG_Pos</a>)</td></tr>
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<tr class="separator:ga63a4749bf5614ee8388364463ef039d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabc46d2c0e7f2525ad2d1dcb41c5e3814" id="r_gabc46d2c0e7f2525ad2d1dcb41c5e3814"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabc46d2c0e7f2525ad2d1dcb41c5e3814">USB_OTG_HPRT_POCCHNG</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63a4749bf5614ee8388364463ef039d6">USB_OTG_HPRT_POCCHNG_Msk</a></td></tr>
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<tr class="separator:gabc46d2c0e7f2525ad2d1dcb41c5e3814"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33aaef70a252270021a2aaef1c33b726" id="r_ga33aaef70a252270021a2aaef1c33b726"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga33aaef70a252270021a2aaef1c33b726">USB_OTG_HPRT_PRES_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga33aaef70a252270021a2aaef1c33b726"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3cf39420fbe05f13da97b9d4f54c753" id="r_gad3cf39420fbe05f13da97b9d4f54c753"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3cf39420fbe05f13da97b9d4f54c753">USB_OTG_HPRT_PRES_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga33aaef70a252270021a2aaef1c33b726">USB_OTG_HPRT_PRES_Pos</a>)</td></tr>
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<tr class="separator:gad3cf39420fbe05f13da97b9d4f54c753"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga643fdc3285aa718952214857d15dadfb" id="r_ga643fdc3285aa718952214857d15dadfb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga643fdc3285aa718952214857d15dadfb">USB_OTG_HPRT_PRES</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad3cf39420fbe05f13da97b9d4f54c753">USB_OTG_HPRT_PRES_Msk</a></td></tr>
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<tr class="separator:ga643fdc3285aa718952214857d15dadfb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga017663af01aba7f6745732a92f731668" id="r_ga017663af01aba7f6745732a92f731668"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga017663af01aba7f6745732a92f731668">USB_OTG_HPRT_PSUSP_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga017663af01aba7f6745732a92f731668"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5b1f55077b63ba7fda82f1d5d06de23" id="r_gad5b1f55077b63ba7fda82f1d5d06de23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5b1f55077b63ba7fda82f1d5d06de23">USB_OTG_HPRT_PSUSP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga017663af01aba7f6745732a92f731668">USB_OTG_HPRT_PSUSP_Pos</a>)</td></tr>
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<tr class="separator:gad5b1f55077b63ba7fda82f1d5d06de23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98db6454c00ab942c1ca969ebb192f67" id="r_ga98db6454c00ab942c1ca969ebb192f67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98db6454c00ab942c1ca969ebb192f67">USB_OTG_HPRT_PSUSP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad5b1f55077b63ba7fda82f1d5d06de23">USB_OTG_HPRT_PSUSP_Msk</a></td></tr>
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<tr class="separator:ga98db6454c00ab942c1ca969ebb192f67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac3ce670bb14739add1077513f30a91e" id="r_gaac3ce670bb14739add1077513f30a91e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaac3ce670bb14739add1077513f30a91e">USB_OTG_HPRT_PRST_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaac3ce670bb14739add1077513f30a91e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26c4eb727f6b37a90e1b9a2aaa64414d" id="r_ga26c4eb727f6b37a90e1b9a2aaa64414d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga26c4eb727f6b37a90e1b9a2aaa64414d">USB_OTG_HPRT_PRST_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaac3ce670bb14739add1077513f30a91e">USB_OTG_HPRT_PRST_Pos</a>)</td></tr>
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<tr class="separator:ga26c4eb727f6b37a90e1b9a2aaa64414d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5741bb0728c8ccf320ef609699c3425a" id="r_ga5741bb0728c8ccf320ef609699c3425a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5741bb0728c8ccf320ef609699c3425a">USB_OTG_HPRT_PRST</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga26c4eb727f6b37a90e1b9a2aaa64414d">USB_OTG_HPRT_PRST_Msk</a></td></tr>
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<tr class="separator:ga5741bb0728c8ccf320ef609699c3425a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4b46c779a0b842af9f269ad488a9ed58" id="r_ga4b46c779a0b842af9f269ad488a9ed58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4b46c779a0b842af9f269ad488a9ed58">USB_OTG_HPRT_PLSTS_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga4b46c779a0b842af9f269ad488a9ed58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b757dac879fce7dae5214b192863ea2" id="r_ga2b757dac879fce7dae5214b192863ea2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b757dac879fce7dae5214b192863ea2">USB_OTG_HPRT_PLSTS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b46c779a0b842af9f269ad488a9ed58">USB_OTG_HPRT_PLSTS_Pos</a>)</td></tr>
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<tr class="separator:ga2b757dac879fce7dae5214b192863ea2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0a3c8eb0d6b7eea1f4aaf60bb27b15c" id="r_gad0a3c8eb0d6b7eea1f4aaf60bb27b15c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0a3c8eb0d6b7eea1f4aaf60bb27b15c">USB_OTG_HPRT_PLSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b757dac879fce7dae5214b192863ea2">USB_OTG_HPRT_PLSTS_Msk</a></td></tr>
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<tr class="separator:gad0a3c8eb0d6b7eea1f4aaf60bb27b15c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bbb5a9719331ba00d44ff01b267bf7d" id="r_ga2bbb5a9719331ba00d44ff01b267bf7d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bbb5a9719331ba00d44ff01b267bf7d">USB_OTG_HPRT_PLSTS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b46c779a0b842af9f269ad488a9ed58">USB_OTG_HPRT_PLSTS_Pos</a>)</td></tr>
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<tr class="separator:ga2bbb5a9719331ba00d44ff01b267bf7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae87cecc544d0c1d8e778c3a598da9276" id="r_gae87cecc544d0c1d8e778c3a598da9276"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae87cecc544d0c1d8e778c3a598da9276">USB_OTG_HPRT_PLSTS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4b46c779a0b842af9f269ad488a9ed58">USB_OTG_HPRT_PLSTS_Pos</a>)</td></tr>
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<tr class="separator:gae87cecc544d0c1d8e778c3a598da9276"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88c07618a453428a840a89100f6dab38" id="r_ga88c07618a453428a840a89100f6dab38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88c07618a453428a840a89100f6dab38">USB_OTG_HPRT_PPWR_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga88c07618a453428a840a89100f6dab38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cd2ac835835be4a80bc43659d300ebe" id="r_ga6cd2ac835835be4a80bc43659d300ebe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6cd2ac835835be4a80bc43659d300ebe">USB_OTG_HPRT_PPWR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga88c07618a453428a840a89100f6dab38">USB_OTG_HPRT_PPWR_Pos</a>)</td></tr>
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<tr class="separator:ga6cd2ac835835be4a80bc43659d300ebe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20965e6de30c19d8b0f355f62680c180" id="r_ga20965e6de30c19d8b0f355f62680c180"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20965e6de30c19d8b0f355f62680c180">USB_OTG_HPRT_PPWR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6cd2ac835835be4a80bc43659d300ebe">USB_OTG_HPRT_PPWR_Msk</a></td></tr>
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<tr class="separator:ga20965e6de30c19d8b0f355f62680c180"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga07ff20317b07fd8655f12cdc0e4dba61" id="r_ga07ff20317b07fd8655f12cdc0e4dba61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga07ff20317b07fd8655f12cdc0e4dba61">USB_OTG_HPRT_PTCTL_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga07ff20317b07fd8655f12cdc0e4dba61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a02e11d6a1f700ee19fcc08117ebe16" id="r_ga3a02e11d6a1f700ee19fcc08117ebe16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3a02e11d6a1f700ee19fcc08117ebe16">USB_OTG_HPRT_PTCTL_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07ff20317b07fd8655f12cdc0e4dba61">USB_OTG_HPRT_PTCTL_Pos</a>)</td></tr>
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<tr class="separator:ga3a02e11d6a1f700ee19fcc08117ebe16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01677a7e4ccb6c54d7bce0cba3899bfb" id="r_ga01677a7e4ccb6c54d7bce0cba3899bfb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01677a7e4ccb6c54d7bce0cba3899bfb">USB_OTG_HPRT_PTCTL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3a02e11d6a1f700ee19fcc08117ebe16">USB_OTG_HPRT_PTCTL_Msk</a></td></tr>
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<tr class="separator:ga01677a7e4ccb6c54d7bce0cba3899bfb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f4faf063b47c7bc83c090e6000e9162" id="r_ga3f4faf063b47c7bc83c090e6000e9162"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f4faf063b47c7bc83c090e6000e9162">USB_OTG_HPRT_PTCTL_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07ff20317b07fd8655f12cdc0e4dba61">USB_OTG_HPRT_PTCTL_Pos</a>)</td></tr>
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<tr class="separator:ga3f4faf063b47c7bc83c090e6000e9162"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga791b063b5e86ffbbfd6980f447408e83" id="r_ga791b063b5e86ffbbfd6980f447408e83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga791b063b5e86ffbbfd6980f447408e83">USB_OTG_HPRT_PTCTL_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07ff20317b07fd8655f12cdc0e4dba61">USB_OTG_HPRT_PTCTL_Pos</a>)</td></tr>
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<tr class="separator:ga791b063b5e86ffbbfd6980f447408e83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6491b21dbe177ecb91628169d02b8c76" id="r_ga6491b21dbe177ecb91628169d02b8c76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6491b21dbe177ecb91628169d02b8c76">USB_OTG_HPRT_PTCTL_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07ff20317b07fd8655f12cdc0e4dba61">USB_OTG_HPRT_PTCTL_Pos</a>)</td></tr>
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<tr class="separator:ga6491b21dbe177ecb91628169d02b8c76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga087d26522b46212d380ca5a1e1c16fed" id="r_ga087d26522b46212d380ca5a1e1c16fed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga087d26522b46212d380ca5a1e1c16fed">USB_OTG_HPRT_PTCTL_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga07ff20317b07fd8655f12cdc0e4dba61">USB_OTG_HPRT_PTCTL_Pos</a>)</td></tr>
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<tr class="separator:ga087d26522b46212d380ca5a1e1c16fed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55160c4571f2bcfb4a77c907b0b7c07c" id="r_ga55160c4571f2bcfb4a77c907b0b7c07c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga55160c4571f2bcfb4a77c907b0b7c07c">USB_OTG_HPRT_PSPD_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga55160c4571f2bcfb4a77c907b0b7c07c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66c65cc05ea21eebd9013f9f84880385" id="r_ga66c65cc05ea21eebd9013f9f84880385"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66c65cc05ea21eebd9013f9f84880385">USB_OTG_HPRT_PSPD_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55160c4571f2bcfb4a77c907b0b7c07c">USB_OTG_HPRT_PSPD_Pos</a>)</td></tr>
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<tr class="separator:ga66c65cc05ea21eebd9013f9f84880385"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a28ddd62304e263536ff9b5cd855ff5" id="r_ga5a28ddd62304e263536ff9b5cd855ff5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a28ddd62304e263536ff9b5cd855ff5">USB_OTG_HPRT_PSPD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga66c65cc05ea21eebd9013f9f84880385">USB_OTG_HPRT_PSPD_Msk</a></td></tr>
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<tr class="separator:ga5a28ddd62304e263536ff9b5cd855ff5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac47d8caa24e4f5e6b66e4d70d549d5fa" id="r_gac47d8caa24e4f5e6b66e4d70d549d5fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac47d8caa24e4f5e6b66e4d70d549d5fa">USB_OTG_HPRT_PSPD_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55160c4571f2bcfb4a77c907b0b7c07c">USB_OTG_HPRT_PSPD_Pos</a>)</td></tr>
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<tr class="separator:gac47d8caa24e4f5e6b66e4d70d549d5fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b8f7977f0d956d6955efd2640530f73" id="r_ga1b8f7977f0d956d6955efd2640530f73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b8f7977f0d956d6955efd2640530f73">USB_OTG_HPRT_PSPD_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga55160c4571f2bcfb4a77c907b0b7c07c">USB_OTG_HPRT_PSPD_Pos</a>)</td></tr>
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<tr class="separator:ga1b8f7977f0d956d6955efd2640530f73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga50c80b485139155fd7ede8a5b78af293" id="r_ga50c80b485139155fd7ede8a5b78af293"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga50c80b485139155fd7ede8a5b78af293">USB_OTG_DOEPEACHMSK1_XFRCM_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga50c80b485139155fd7ede8a5b78af293"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1124b10adb855eb49ab052fd8f7adf5" id="r_gaa1124b10adb855eb49ab052fd8f7adf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1124b10adb855eb49ab052fd8f7adf5">USB_OTG_DOEPEACHMSK1_XFRCM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga50c80b485139155fd7ede8a5b78af293">USB_OTG_DOEPEACHMSK1_XFRCM_Pos</a>)</td></tr>
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<tr class="separator:gaa1124b10adb855eb49ab052fd8f7adf5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f709b5af2c771d66d240adef5d8be21" id="r_ga4f709b5af2c771d66d240adef5d8be21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f709b5af2c771d66d240adef5d8be21">USB_OTG_DOEPEACHMSK1_XFRCM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa1124b10adb855eb49ab052fd8f7adf5">USB_OTG_DOEPEACHMSK1_XFRCM_Msk</a></td></tr>
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<tr class="separator:ga4f709b5af2c771d66d240adef5d8be21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac39a208617e70f246d83e7ca33f2d63a" id="r_gac39a208617e70f246d83e7ca33f2d63a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac39a208617e70f246d83e7ca33f2d63a">USB_OTG_DOEPEACHMSK1_EPDM_Pos</a>   (1U)</td></tr>
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<tr class="separator:gac39a208617e70f246d83e7ca33f2d63a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c0d1dc807789f08756d5eebc35065e5" id="r_ga6c0d1dc807789f08756d5eebc35065e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c0d1dc807789f08756d5eebc35065e5">USB_OTG_DOEPEACHMSK1_EPDM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac39a208617e70f246d83e7ca33f2d63a">USB_OTG_DOEPEACHMSK1_EPDM_Pos</a>)</td></tr>
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<tr class="separator:ga6c0d1dc807789f08756d5eebc35065e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga866580df1a60ef8b3347d63b1369f76e" id="r_ga866580df1a60ef8b3347d63b1369f76e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga866580df1a60ef8b3347d63b1369f76e">USB_OTG_DOEPEACHMSK1_EPDM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c0d1dc807789f08756d5eebc35065e5">USB_OTG_DOEPEACHMSK1_EPDM_Msk</a></td></tr>
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<tr class="separator:ga866580df1a60ef8b3347d63b1369f76e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2a3e66bdba3af962f77a2643a8dfe38" id="r_gae2a3e66bdba3af962f77a2643a8dfe38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2a3e66bdba3af962f77a2643a8dfe38">USB_OTG_DOEPEACHMSK1_TOM_Pos</a>   (3U)</td></tr>
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<tr class="separator:gae2a3e66bdba3af962f77a2643a8dfe38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaae427974c1d2cd44962a72e5ad4d9e68" id="r_gaae427974c1d2cd44962a72e5ad4d9e68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaae427974c1d2cd44962a72e5ad4d9e68">USB_OTG_DOEPEACHMSK1_TOM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae2a3e66bdba3af962f77a2643a8dfe38">USB_OTG_DOEPEACHMSK1_TOM_Pos</a>)</td></tr>
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<tr class="separator:gaae427974c1d2cd44962a72e5ad4d9e68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga038706cd615636fe5bf10e6636b3c035" id="r_ga038706cd615636fe5bf10e6636b3c035"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga038706cd615636fe5bf10e6636b3c035">USB_OTG_DOEPEACHMSK1_TOM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaae427974c1d2cd44962a72e5ad4d9e68">USB_OTG_DOEPEACHMSK1_TOM_Msk</a></td></tr>
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<tr class="separator:ga038706cd615636fe5bf10e6636b3c035"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20102cf4a07490f60bd525bce51de6b6" id="r_ga20102cf4a07490f60bd525bce51de6b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20102cf4a07490f60bd525bce51de6b6">USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga20102cf4a07490f60bd525bce51de6b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga958f2820ea10558695b00400bfed9927" id="r_ga958f2820ea10558695b00400bfed9927"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga958f2820ea10558695b00400bfed9927">USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20102cf4a07490f60bd525bce51de6b6">USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos</a>)</td></tr>
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<tr class="separator:ga958f2820ea10558695b00400bfed9927"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace8821806fb4cb204d97dbb965e5067d" id="r_gace8821806fb4cb204d97dbb965e5067d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace8821806fb4cb204d97dbb965e5067d">USB_OTG_DOEPEACHMSK1_ITTXFEMSK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga958f2820ea10558695b00400bfed9927">USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk</a></td></tr>
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<tr class="separator:gace8821806fb4cb204d97dbb965e5067d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe0a86e9dbdf4a15922a6503e78c2f67" id="r_gabe0a86e9dbdf4a15922a6503e78c2f67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe0a86e9dbdf4a15922a6503e78c2f67">USB_OTG_DOEPEACHMSK1_INEPNMM_Pos</a>   (5U)</td></tr>
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<tr class="separator:gabe0a86e9dbdf4a15922a6503e78c2f67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa0193a714c31b0cf57e25588071cc637" id="r_gaa0193a714c31b0cf57e25588071cc637"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa0193a714c31b0cf57e25588071cc637">USB_OTG_DOEPEACHMSK1_INEPNMM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabe0a86e9dbdf4a15922a6503e78c2f67">USB_OTG_DOEPEACHMSK1_INEPNMM_Pos</a>)</td></tr>
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<tr class="separator:gaa0193a714c31b0cf57e25588071cc637"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20d91d742e89a430937207cca6dd0a1a" id="r_ga20d91d742e89a430937207cca6dd0a1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20d91d742e89a430937207cca6dd0a1a">USB_OTG_DOEPEACHMSK1_INEPNMM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa0193a714c31b0cf57e25588071cc637">USB_OTG_DOEPEACHMSK1_INEPNMM_Msk</a></td></tr>
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<tr class="separator:ga20d91d742e89a430937207cca6dd0a1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga773825312f8b0edbb607a5fea843c882" id="r_ga773825312f8b0edbb607a5fea843c882"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga773825312f8b0edbb607a5fea843c882">USB_OTG_DOEPEACHMSK1_INEPNEM_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga773825312f8b0edbb607a5fea843c882"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6b4fd478ae41b36f08356f9c98840d5" id="r_gaa6b4fd478ae41b36f08356f9c98840d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6b4fd478ae41b36f08356f9c98840d5">USB_OTG_DOEPEACHMSK1_INEPNEM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga773825312f8b0edbb607a5fea843c882">USB_OTG_DOEPEACHMSK1_INEPNEM_Pos</a>)</td></tr>
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<tr class="separator:gaa6b4fd478ae41b36f08356f9c98840d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73a879622564efeb3244262bf9419818" id="r_ga73a879622564efeb3244262bf9419818"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga73a879622564efeb3244262bf9419818">USB_OTG_DOEPEACHMSK1_INEPNEM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6b4fd478ae41b36f08356f9c98840d5">USB_OTG_DOEPEACHMSK1_INEPNEM_Msk</a></td></tr>
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<tr class="separator:ga73a879622564efeb3244262bf9419818"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae23cef3a94a622721e9f36176b8ee292" id="r_gae23cef3a94a622721e9f36176b8ee292"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae23cef3a94a622721e9f36176b8ee292">USB_OTG_DOEPEACHMSK1_TXFURM_Pos</a>   (8U)</td></tr>
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<tr class="separator:gae23cef3a94a622721e9f36176b8ee292"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3bd6db454cff3d758f6d9d36f8bac8c1" id="r_ga3bd6db454cff3d758f6d9d36f8bac8c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3bd6db454cff3d758f6d9d36f8bac8c1">USB_OTG_DOEPEACHMSK1_TXFURM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae23cef3a94a622721e9f36176b8ee292">USB_OTG_DOEPEACHMSK1_TXFURM_Pos</a>)</td></tr>
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<tr class="separator:ga3bd6db454cff3d758f6d9d36f8bac8c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3ca9111b1b74380566ce72b6c985560" id="r_gaa3ca9111b1b74380566ce72b6c985560"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3ca9111b1b74380566ce72b6c985560">USB_OTG_DOEPEACHMSK1_TXFURM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3bd6db454cff3d758f6d9d36f8bac8c1">USB_OTG_DOEPEACHMSK1_TXFURM_Msk</a></td></tr>
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<tr class="separator:gaa3ca9111b1b74380566ce72b6c985560"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85a209e39fa583a74b58fa30ccc01496" id="r_ga85a209e39fa583a74b58fa30ccc01496"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85a209e39fa583a74b58fa30ccc01496">USB_OTG_DOEPEACHMSK1_BIM_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga85a209e39fa583a74b58fa30ccc01496"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4b101ae377598650c667420a8465cef" id="r_gad4b101ae377598650c667420a8465cef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4b101ae377598650c667420a8465cef">USB_OTG_DOEPEACHMSK1_BIM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga85a209e39fa583a74b58fa30ccc01496">USB_OTG_DOEPEACHMSK1_BIM_Pos</a>)</td></tr>
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<tr class="separator:gad4b101ae377598650c667420a8465cef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa99f230d086cf41692cfab0c1aad0f26" id="r_gaa99f230d086cf41692cfab0c1aad0f26"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa99f230d086cf41692cfab0c1aad0f26">USB_OTG_DOEPEACHMSK1_BIM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad4b101ae377598650c667420a8465cef">USB_OTG_DOEPEACHMSK1_BIM_Msk</a></td></tr>
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<tr class="separator:gaa99f230d086cf41692cfab0c1aad0f26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d940b15d335a584cb074297e330804c" id="r_ga7d940b15d335a584cb074297e330804c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7d940b15d335a584cb074297e330804c">USB_OTG_DOEPEACHMSK1_BERRM_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga7d940b15d335a584cb074297e330804c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadb8873ed6ca0091147855a58b22054ed" id="r_gadb8873ed6ca0091147855a58b22054ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadb8873ed6ca0091147855a58b22054ed">USB_OTG_DOEPEACHMSK1_BERRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7d940b15d335a584cb074297e330804c">USB_OTG_DOEPEACHMSK1_BERRM_Pos</a>)</td></tr>
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<tr class="separator:gadb8873ed6ca0091147855a58b22054ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3eecdae7aa0c9b1b40f219e8b0c18879" id="r_ga3eecdae7aa0c9b1b40f219e8b0c18879"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3eecdae7aa0c9b1b40f219e8b0c18879">USB_OTG_DOEPEACHMSK1_BERRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadb8873ed6ca0091147855a58b22054ed">USB_OTG_DOEPEACHMSK1_BERRM_Msk</a></td></tr>
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<tr class="separator:ga3eecdae7aa0c9b1b40f219e8b0c18879"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6935021f39b8b2ba43e5e963c441c0bf" id="r_ga6935021f39b8b2ba43e5e963c441c0bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6935021f39b8b2ba43e5e963c441c0bf">USB_OTG_DOEPEACHMSK1_NAKM_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga6935021f39b8b2ba43e5e963c441c0bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94cf1998cd40af00f7295c221fd4850b" id="r_ga94cf1998cd40af00f7295c221fd4850b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga94cf1998cd40af00f7295c221fd4850b">USB_OTG_DOEPEACHMSK1_NAKM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6935021f39b8b2ba43e5e963c441c0bf">USB_OTG_DOEPEACHMSK1_NAKM_Pos</a>)</td></tr>
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<tr class="separator:ga94cf1998cd40af00f7295c221fd4850b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98fa7db10f7b8e4998d30646a9e8e266" id="r_ga98fa7db10f7b8e4998d30646a9e8e266"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98fa7db10f7b8e4998d30646a9e8e266">USB_OTG_DOEPEACHMSK1_NAKM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga94cf1998cd40af00f7295c221fd4850b">USB_OTG_DOEPEACHMSK1_NAKM_Msk</a></td></tr>
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<tr class="separator:ga98fa7db10f7b8e4998d30646a9e8e266"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9738465ddedbad09f63f86d8932235ca" id="r_ga9738465ddedbad09f63f86d8932235ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9738465ddedbad09f63f86d8932235ca">USB_OTG_DOEPEACHMSK1_NYETM_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga9738465ddedbad09f63f86d8932235ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cfdf8dc17970f375d544ff23c3369fc" id="r_ga5cfdf8dc17970f375d544ff23c3369fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5cfdf8dc17970f375d544ff23c3369fc">USB_OTG_DOEPEACHMSK1_NYETM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9738465ddedbad09f63f86d8932235ca">USB_OTG_DOEPEACHMSK1_NYETM_Pos</a>)</td></tr>
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<tr class="separator:ga5cfdf8dc17970f375d544ff23c3369fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bcea3bd49b83367b4f62c554815770e" id="r_ga5bcea3bd49b83367b4f62c554815770e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bcea3bd49b83367b4f62c554815770e">USB_OTG_DOEPEACHMSK1_NYETM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5cfdf8dc17970f375d544ff23c3369fc">USB_OTG_DOEPEACHMSK1_NYETM_Msk</a></td></tr>
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<tr class="separator:ga5bcea3bd49b83367b4f62c554815770e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga249c1794df3b2690031184ae330118e7" id="r_ga249c1794df3b2690031184ae330118e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga249c1794df3b2690031184ae330118e7">USB_OTG_HPTXFSIZ_PTXSA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga249c1794df3b2690031184ae330118e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9be1af071c308f74cf353d2ce3d691b9" id="r_ga9be1af071c308f74cf353d2ce3d691b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9be1af071c308f74cf353d2ce3d691b9">USB_OTG_HPTXFSIZ_PTXSA_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga249c1794df3b2690031184ae330118e7">USB_OTG_HPTXFSIZ_PTXSA_Pos</a>)</td></tr>
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<tr class="separator:ga9be1af071c308f74cf353d2ce3d691b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62a28fc8c8ab16a52858febfbb0382ef" id="r_ga62a28fc8c8ab16a52858febfbb0382ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62a28fc8c8ab16a52858febfbb0382ef">USB_OTG_HPTXFSIZ_PTXSA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9be1af071c308f74cf353d2ce3d691b9">USB_OTG_HPTXFSIZ_PTXSA_Msk</a></td></tr>
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<tr class="separator:ga62a28fc8c8ab16a52858febfbb0382ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab930c4f0f50e3f18256064a8f2bdb2b4" id="r_gab930c4f0f50e3f18256064a8f2bdb2b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab930c4f0f50e3f18256064a8f2bdb2b4">USB_OTG_HPTXFSIZ_PTXFD_Pos</a>   (16U)</td></tr>
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<tr class="separator:gab930c4f0f50e3f18256064a8f2bdb2b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b5b79b979f2e9443324066faaa92245" id="r_ga1b5b79b979f2e9443324066faaa92245"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b5b79b979f2e9443324066faaa92245">USB_OTG_HPTXFSIZ_PTXFD_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab930c4f0f50e3f18256064a8f2bdb2b4">USB_OTG_HPTXFSIZ_PTXFD_Pos</a>)</td></tr>
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<tr class="separator:ga1b5b79b979f2e9443324066faaa92245"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85a628f9094f55c620b2846635803781" id="r_ga85a628f9094f55c620b2846635803781"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85a628f9094f55c620b2846635803781">USB_OTG_HPTXFSIZ_PTXFD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b5b79b979f2e9443324066faaa92245">USB_OTG_HPTXFSIZ_PTXFD_Msk</a></td></tr>
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<tr class="separator:ga85a628f9094f55c620b2846635803781"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f340944f765c7e6ed22c40b337d8fc1" id="r_ga6f340944f765c7e6ed22c40b337d8fc1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6f340944f765c7e6ed22c40b337d8fc1">USB_OTG_DIEPCTL_MPSIZ_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga6f340944f765c7e6ed22c40b337d8fc1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ea4a7999fe1ba166d761a56a5f045aa" id="r_ga9ea4a7999fe1ba166d761a56a5f045aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ea4a7999fe1ba166d761a56a5f045aa">USB_OTG_DIEPCTL_MPSIZ_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga6f340944f765c7e6ed22c40b337d8fc1">USB_OTG_DIEPCTL_MPSIZ_Pos</a>)</td></tr>
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<tr class="separator:ga9ea4a7999fe1ba166d761a56a5f045aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabda35dcaaa3faa8443bec36b9edc438e" id="r_gabda35dcaaa3faa8443bec36b9edc438e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabda35dcaaa3faa8443bec36b9edc438e">USB_OTG_DIEPCTL_MPSIZ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ea4a7999fe1ba166d761a56a5f045aa">USB_OTG_DIEPCTL_MPSIZ_Msk</a></td></tr>
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<tr class="separator:gabda35dcaaa3faa8443bec36b9edc438e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3259dc5bb86cce573ba8469dc82573f" id="r_gad3259dc5bb86cce573ba8469dc82573f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3259dc5bb86cce573ba8469dc82573f">USB_OTG_DIEPCTL_USBAEP_Pos</a>   (15U)</td></tr>
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<tr class="separator:gad3259dc5bb86cce573ba8469dc82573f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf2847317d82bfe14ae48839902c177dd" id="r_gaf2847317d82bfe14ae48839902c177dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf2847317d82bfe14ae48839902c177dd">USB_OTG_DIEPCTL_USBAEP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad3259dc5bb86cce573ba8469dc82573f">USB_OTG_DIEPCTL_USBAEP_Pos</a>)</td></tr>
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<tr class="separator:gaf2847317d82bfe14ae48839902c177dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52604d4a0d7b24ad619a2860003e8fe3" id="r_ga52604d4a0d7b24ad619a2860003e8fe3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga52604d4a0d7b24ad619a2860003e8fe3">USB_OTG_DIEPCTL_USBAEP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf2847317d82bfe14ae48839902c177dd">USB_OTG_DIEPCTL_USBAEP_Msk</a></td></tr>
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<tr class="separator:ga52604d4a0d7b24ad619a2860003e8fe3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4ea8a7d612c65303a2d6e6c89a6e99c" id="r_gae4ea8a7d612c65303a2d6e6c89a6e99c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4ea8a7d612c65303a2d6e6c89a6e99c">USB_OTG_DIEPCTL_EONUM_DPID_Pos</a>   (16U)</td></tr>
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<tr class="separator:gae4ea8a7d612c65303a2d6e6c89a6e99c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4d849a015e877f7b9e4a82291a9997b" id="r_gab4d849a015e877f7b9e4a82291a9997b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab4d849a015e877f7b9e4a82291a9997b">USB_OTG_DIEPCTL_EONUM_DPID_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae4ea8a7d612c65303a2d6e6c89a6e99c">USB_OTG_DIEPCTL_EONUM_DPID_Pos</a>)</td></tr>
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<tr class="separator:gab4d849a015e877f7b9e4a82291a9997b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1f908cbb98598542f631c746bc3a85a1" id="r_ga1f908cbb98598542f631c746bc3a85a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1f908cbb98598542f631c746bc3a85a1">USB_OTG_DIEPCTL_EONUM_DPID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab4d849a015e877f7b9e4a82291a9997b">USB_OTG_DIEPCTL_EONUM_DPID_Msk</a></td></tr>
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<tr class="separator:ga1f908cbb98598542f631c746bc3a85a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga78ccc71651a434402bef238206f3cd32" id="r_ga78ccc71651a434402bef238206f3cd32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78ccc71651a434402bef238206f3cd32">USB_OTG_DIEPCTL_NAKSTS_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga78ccc71651a434402bef238206f3cd32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48e2e960476f1b5e1e205bef19c30b5b" id="r_ga48e2e960476f1b5e1e205bef19c30b5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48e2e960476f1b5e1e205bef19c30b5b">USB_OTG_DIEPCTL_NAKSTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78ccc71651a434402bef238206f3cd32">USB_OTG_DIEPCTL_NAKSTS_Pos</a>)</td></tr>
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<tr class="separator:ga48e2e960476f1b5e1e205bef19c30b5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3aa35782f7d920f0c6520db137bce768" id="r_ga3aa35782f7d920f0c6520db137bce768"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3aa35782f7d920f0c6520db137bce768">USB_OTG_DIEPCTL_NAKSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga48e2e960476f1b5e1e205bef19c30b5b">USB_OTG_DIEPCTL_NAKSTS_Msk</a></td></tr>
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<tr class="separator:ga3aa35782f7d920f0c6520db137bce768"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadfa549c62330bf01de4ddb187ce5e96" id="r_gaadfa549c62330bf01de4ddb187ce5e96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaadfa549c62330bf01de4ddb187ce5e96">USB_OTG_DIEPCTL_EPTYP_Pos</a>   (18U)</td></tr>
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<tr class="separator:gaadfa549c62330bf01de4ddb187ce5e96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf416ce016be26169bcb25b1eea153f08" id="r_gaf416ce016be26169bcb25b1eea153f08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf416ce016be26169bcb25b1eea153f08">USB_OTG_DIEPCTL_EPTYP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaadfa549c62330bf01de4ddb187ce5e96">USB_OTG_DIEPCTL_EPTYP_Pos</a>)</td></tr>
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<tr class="separator:gaf416ce016be26169bcb25b1eea153f08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2fc1b4e978ef3a22450da75f2608dff2" id="r_ga2fc1b4e978ef3a22450da75f2608dff2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2fc1b4e978ef3a22450da75f2608dff2">USB_OTG_DIEPCTL_EPTYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf416ce016be26169bcb25b1eea153f08">USB_OTG_DIEPCTL_EPTYP_Msk</a></td></tr>
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<tr class="separator:ga2fc1b4e978ef3a22450da75f2608dff2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4da4d418faa4245347a4ad3c1b8334d9" id="r_ga4da4d418faa4245347a4ad3c1b8334d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4da4d418faa4245347a4ad3c1b8334d9">USB_OTG_DIEPCTL_EPTYP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaadfa549c62330bf01de4ddb187ce5e96">USB_OTG_DIEPCTL_EPTYP_Pos</a>)</td></tr>
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<tr class="separator:ga4da4d418faa4245347a4ad3c1b8334d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae2ca76cb985239ed613062b1087075ab" id="r_gae2ca76cb985239ed613062b1087075ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae2ca76cb985239ed613062b1087075ab">USB_OTG_DIEPCTL_EPTYP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaadfa549c62330bf01de4ddb187ce5e96">USB_OTG_DIEPCTL_EPTYP_Pos</a>)</td></tr>
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<tr class="separator:gae2ca76cb985239ed613062b1087075ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga740abf97e28d1670808797448f75d062" id="r_ga740abf97e28d1670808797448f75d062"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga740abf97e28d1670808797448f75d062">USB_OTG_DIEPCTL_STALL_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga740abf97e28d1670808797448f75d062"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga72b289fbf1a810cefd61091e9affcf62" id="r_ga72b289fbf1a810cefd61091e9affcf62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72b289fbf1a810cefd61091e9affcf62">USB_OTG_DIEPCTL_STALL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga740abf97e28d1670808797448f75d062">USB_OTG_DIEPCTL_STALL_Pos</a>)</td></tr>
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<tr class="separator:ga72b289fbf1a810cefd61091e9affcf62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab313ac4b4a0d85f45af3733d574cb9a9" id="r_gab313ac4b4a0d85f45af3733d574cb9a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab313ac4b4a0d85f45af3733d574cb9a9">USB_OTG_DIEPCTL_STALL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga72b289fbf1a810cefd61091e9affcf62">USB_OTG_DIEPCTL_STALL_Msk</a></td></tr>
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<tr class="separator:gab313ac4b4a0d85f45af3733d574cb9a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84597138dd8b05b14b586fd8d51013ff" id="r_ga84597138dd8b05b14b586fd8d51013ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga84597138dd8b05b14b586fd8d51013ff">USB_OTG_DIEPCTL_TXFNUM_Pos</a>   (22U)</td></tr>
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<tr class="separator:ga84597138dd8b05b14b586fd8d51013ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e8e627baaad5f7ed0176d106ec0f43a" id="r_ga6e8e627baaad5f7ed0176d106ec0f43a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e8e627baaad5f7ed0176d106ec0f43a">USB_OTG_DIEPCTL_TXFNUM_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84597138dd8b05b14b586fd8d51013ff">USB_OTG_DIEPCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:ga6e8e627baaad5f7ed0176d106ec0f43a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2a4ce33e0e644c9439c9cce59b2edfa" id="r_gad2a4ce33e0e644c9439c9cce59b2edfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2a4ce33e0e644c9439c9cce59b2edfa">USB_OTG_DIEPCTL_TXFNUM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e8e627baaad5f7ed0176d106ec0f43a">USB_OTG_DIEPCTL_TXFNUM_Msk</a></td></tr>
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<tr class="separator:gad2a4ce33e0e644c9439c9cce59b2edfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0cd18c0071ac8c9676fbc010a07ef49" id="r_gaf0cd18c0071ac8c9676fbc010a07ef49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf0cd18c0071ac8c9676fbc010a07ef49">USB_OTG_DIEPCTL_TXFNUM_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84597138dd8b05b14b586fd8d51013ff">USB_OTG_DIEPCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:gaf0cd18c0071ac8c9676fbc010a07ef49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e710b13ec4621897335fe9e18c7398c" id="r_ga3e710b13ec4621897335fe9e18c7398c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3e710b13ec4621897335fe9e18c7398c">USB_OTG_DIEPCTL_TXFNUM_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84597138dd8b05b14b586fd8d51013ff">USB_OTG_DIEPCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:ga3e710b13ec4621897335fe9e18c7398c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bf5811bde53bd29c3c91ab07fdc2a5b" id="r_ga1bf5811bde53bd29c3c91ab07fdc2a5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1bf5811bde53bd29c3c91ab07fdc2a5b">USB_OTG_DIEPCTL_TXFNUM_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84597138dd8b05b14b586fd8d51013ff">USB_OTG_DIEPCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:ga1bf5811bde53bd29c3c91ab07fdc2a5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae67a96234e062d1304a4af3afc938164" id="r_gae67a96234e062d1304a4af3afc938164"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae67a96234e062d1304a4af3afc938164">USB_OTG_DIEPCTL_TXFNUM_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga84597138dd8b05b14b586fd8d51013ff">USB_OTG_DIEPCTL_TXFNUM_Pos</a>)</td></tr>
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<tr class="separator:gae67a96234e062d1304a4af3afc938164"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga34262b1369356b472f2f5fd07ab00329" id="r_ga34262b1369356b472f2f5fd07ab00329"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga34262b1369356b472f2f5fd07ab00329">USB_OTG_DIEPCTL_CNAK_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga34262b1369356b472f2f5fd07ab00329"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4398c0cf3ff27735935e0ec567d28dcc" id="r_ga4398c0cf3ff27735935e0ec567d28dcc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4398c0cf3ff27735935e0ec567d28dcc">USB_OTG_DIEPCTL_CNAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga34262b1369356b472f2f5fd07ab00329">USB_OTG_DIEPCTL_CNAK_Pos</a>)</td></tr>
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<tr class="separator:ga4398c0cf3ff27735935e0ec567d28dcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7aa93621e2379266fd2901742f9d652" id="r_gab7aa93621e2379266fd2901742f9d652"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7aa93621e2379266fd2901742f9d652">USB_OTG_DIEPCTL_CNAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4398c0cf3ff27735935e0ec567d28dcc">USB_OTG_DIEPCTL_CNAK_Msk</a></td></tr>
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<tr class="separator:gab7aa93621e2379266fd2901742f9d652"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae02f66b28850f4cde25bc3c4d844d7f5" id="r_gae02f66b28850f4cde25bc3c4d844d7f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae02f66b28850f4cde25bc3c4d844d7f5">USB_OTG_DIEPCTL_SNAK_Pos</a>   (27U)</td></tr>
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<tr class="separator:gae02f66b28850f4cde25bc3c4d844d7f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79c45bf1dcfa6b08ee039f3dde83926a" id="r_ga79c45bf1dcfa6b08ee039f3dde83926a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79c45bf1dcfa6b08ee039f3dde83926a">USB_OTG_DIEPCTL_SNAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae02f66b28850f4cde25bc3c4d844d7f5">USB_OTG_DIEPCTL_SNAK_Pos</a>)</td></tr>
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<tr class="separator:ga79c45bf1dcfa6b08ee039f3dde83926a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04939f2cc7cab01a34b516197883c542" id="r_ga04939f2cc7cab01a34b516197883c542"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04939f2cc7cab01a34b516197883c542">USB_OTG_DIEPCTL_SNAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga79c45bf1dcfa6b08ee039f3dde83926a">USB_OTG_DIEPCTL_SNAK_Msk</a></td></tr>
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<tr class="separator:ga04939f2cc7cab01a34b516197883c542"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa2ed3b1957b14db8a12ba9553356607" id="r_gaaa2ed3b1957b14db8a12ba9553356607"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa2ed3b1957b14db8a12ba9553356607">USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos</a>   (28U)</td></tr>
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<tr class="separator:gaaa2ed3b1957b14db8a12ba9553356607"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cabb03e5a98b0496a9f019d337362dc" id="r_ga7cabb03e5a98b0496a9f019d337362dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cabb03e5a98b0496a9f019d337362dc">USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa2ed3b1957b14db8a12ba9553356607">USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos</a>)</td></tr>
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<tr class="separator:ga7cabb03e5a98b0496a9f019d337362dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5ea132b2710076fcc0ef9ebaffe7e1e" id="r_gac5ea132b2710076fcc0ef9ebaffe7e1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5ea132b2710076fcc0ef9ebaffe7e1e">USB_OTG_DIEPCTL_SD0PID_SEVNFRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cabb03e5a98b0496a9f019d337362dc">USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk</a></td></tr>
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<tr class="separator:gac5ea132b2710076fcc0ef9ebaffe7e1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2f39c24ed8d37c04b07b7decd807af2" id="r_gad2f39c24ed8d37c04b07b7decd807af2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2f39c24ed8d37c04b07b7decd807af2">USB_OTG_DIEPCTL_SODDFRM_Pos</a>   (29U)</td></tr>
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<tr class="separator:gad2f39c24ed8d37c04b07b7decd807af2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06e1743fc6505d240ba8929c579a807a" id="r_ga06e1743fc6505d240ba8929c579a807a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06e1743fc6505d240ba8929c579a807a">USB_OTG_DIEPCTL_SODDFRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad2f39c24ed8d37c04b07b7decd807af2">USB_OTG_DIEPCTL_SODDFRM_Pos</a>)</td></tr>
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<tr class="separator:ga06e1743fc6505d240ba8929c579a807a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae874b1d1b15b4ada193bab411634a37a" id="r_gae874b1d1b15b4ada193bab411634a37a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae874b1d1b15b4ada193bab411634a37a">USB_OTG_DIEPCTL_SODDFRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga06e1743fc6505d240ba8929c579a807a">USB_OTG_DIEPCTL_SODDFRM_Msk</a></td></tr>
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<tr class="separator:gae874b1d1b15b4ada193bab411634a37a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2daf3ac53bfdfdbb7835126c245b34c2" id="r_ga2daf3ac53bfdfdbb7835126c245b34c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2daf3ac53bfdfdbb7835126c245b34c2">USB_OTG_DIEPCTL_EPDIS_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga2daf3ac53bfdfdbb7835126c245b34c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c56726a11ab538f4108a37ffd15f254" id="r_ga6c56726a11ab538f4108a37ffd15f254"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c56726a11ab538f4108a37ffd15f254">USB_OTG_DIEPCTL_EPDIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2daf3ac53bfdfdbb7835126c245b34c2">USB_OTG_DIEPCTL_EPDIS_Pos</a>)</td></tr>
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<tr class="separator:ga6c56726a11ab538f4108a37ffd15f254"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9cc396ddf6cd0c0781acec4e278aa815" id="r_ga9cc396ddf6cd0c0781acec4e278aa815"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9cc396ddf6cd0c0781acec4e278aa815">USB_OTG_DIEPCTL_EPDIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c56726a11ab538f4108a37ffd15f254">USB_OTG_DIEPCTL_EPDIS_Msk</a></td></tr>
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<tr class="separator:ga9cc396ddf6cd0c0781acec4e278aa815"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga465665c0a5926a0b27ec5288e46d2394" id="r_ga465665c0a5926a0b27ec5288e46d2394"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga465665c0a5926a0b27ec5288e46d2394">USB_OTG_DIEPCTL_EPENA_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga465665c0a5926a0b27ec5288e46d2394"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5eb8f53ab834ffe44f784baab031791" id="r_gab5eb8f53ab834ffe44f784baab031791"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5eb8f53ab834ffe44f784baab031791">USB_OTG_DIEPCTL_EPENA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga465665c0a5926a0b27ec5288e46d2394">USB_OTG_DIEPCTL_EPENA_Pos</a>)</td></tr>
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<tr class="separator:gab5eb8f53ab834ffe44f784baab031791"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6951a1febc2510628114a0297170bce" id="r_gad6951a1febc2510628114a0297170bce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad6951a1febc2510628114a0297170bce">USB_OTG_DIEPCTL_EPENA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab5eb8f53ab834ffe44f784baab031791">USB_OTG_DIEPCTL_EPENA_Msk</a></td></tr>
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<tr class="separator:gad6951a1febc2510628114a0297170bce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca874060952d9d5d5a31d3ce095d0358" id="r_gaca874060952d9d5d5a31d3ce095d0358"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaca874060952d9d5d5a31d3ce095d0358">USB_OTG_HCCHAR_MPSIZ_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaca874060952d9d5d5a31d3ce095d0358"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaacaf54f4394f57b2eea234e1aeb4bb43" id="r_gaacaf54f4394f57b2eea234e1aeb4bb43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaacaf54f4394f57b2eea234e1aeb4bb43">USB_OTG_HCCHAR_MPSIZ_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaca874060952d9d5d5a31d3ce095d0358">USB_OTG_HCCHAR_MPSIZ_Pos</a>)</td></tr>
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<tr class="separator:gaacaf54f4394f57b2eea234e1aeb4bb43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7d25c42363f797cf4c2c308006de784" id="r_gaf7d25c42363f797cf4c2c308006de784"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf7d25c42363f797cf4c2c308006de784">USB_OTG_HCCHAR_MPSIZ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaacaf54f4394f57b2eea234e1aeb4bb43">USB_OTG_HCCHAR_MPSIZ_Msk</a></td></tr>
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<tr class="separator:gaf7d25c42363f797cf4c2c308006de784"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb71f23c0ec214d2ffc8d8bc81aa2ab2" id="r_gabb71f23c0ec214d2ffc8d8bc81aa2ab2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabb71f23c0ec214d2ffc8d8bc81aa2ab2">USB_OTG_HCCHAR_EPNUM_Pos</a>   (11U)</td></tr>
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<tr class="separator:gabb71f23c0ec214d2ffc8d8bc81aa2ab2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7341e59397aba116872d63a3606d0cb6" id="r_ga7341e59397aba116872d63a3606d0cb6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7341e59397aba116872d63a3606d0cb6">USB_OTG_HCCHAR_EPNUM_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb71f23c0ec214d2ffc8d8bc81aa2ab2">USB_OTG_HCCHAR_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:ga7341e59397aba116872d63a3606d0cb6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0ac25b2f10b80c3f529c97f225be728" id="r_gae0ac25b2f10b80c3f529c97f225be728"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0ac25b2f10b80c3f529c97f225be728">USB_OTG_HCCHAR_EPNUM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7341e59397aba116872d63a3606d0cb6">USB_OTG_HCCHAR_EPNUM_Msk</a></td></tr>
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<tr class="separator:gae0ac25b2f10b80c3f529c97f225be728"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fa97e03ed82c3f48b7b8ceb38db62bf" id="r_ga8fa97e03ed82c3f48b7b8ceb38db62bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8fa97e03ed82c3f48b7b8ceb38db62bf">USB_OTG_HCCHAR_EPNUM_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb71f23c0ec214d2ffc8d8bc81aa2ab2">USB_OTG_HCCHAR_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:ga8fa97e03ed82c3f48b7b8ceb38db62bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3898f15c5f3db168ab867f1dbfc8d3b" id="r_gac3898f15c5f3db168ab867f1dbfc8d3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac3898f15c5f3db168ab867f1dbfc8d3b">USB_OTG_HCCHAR_EPNUM_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb71f23c0ec214d2ffc8d8bc81aa2ab2">USB_OTG_HCCHAR_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:gac3898f15c5f3db168ab867f1dbfc8d3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb6e82877f06b262cc0ec2143821ebf3" id="r_gaeb6e82877f06b262cc0ec2143821ebf3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb6e82877f06b262cc0ec2143821ebf3">USB_OTG_HCCHAR_EPNUM_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb71f23c0ec214d2ffc8d8bc81aa2ab2">USB_OTG_HCCHAR_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:gaeb6e82877f06b262cc0ec2143821ebf3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3977b57bb81f942fcdde8f4d5e9fe24" id="r_gab3977b57bb81f942fcdde8f4d5e9fe24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3977b57bb81f942fcdde8f4d5e9fe24">USB_OTG_HCCHAR_EPNUM_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabb71f23c0ec214d2ffc8d8bc81aa2ab2">USB_OTG_HCCHAR_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:gab3977b57bb81f942fcdde8f4d5e9fe24"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdd23192fd35d666bd97f831304d45d2" id="r_gacdd23192fd35d666bd97f831304d45d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacdd23192fd35d666bd97f831304d45d2">USB_OTG_HCCHAR_EPDIR_Pos</a>   (15U)</td></tr>
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<tr class="separator:gacdd23192fd35d666bd97f831304d45d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga93cab809dbd5a48454d9370b5cc83571" id="r_ga93cab809dbd5a48454d9370b5cc83571"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga93cab809dbd5a48454d9370b5cc83571">USB_OTG_HCCHAR_EPDIR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gacdd23192fd35d666bd97f831304d45d2">USB_OTG_HCCHAR_EPDIR_Pos</a>)</td></tr>
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<tr class="separator:ga93cab809dbd5a48454d9370b5cc83571"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga303898c1943aede8d1ed6b9f259b9d0c" id="r_ga303898c1943aede8d1ed6b9f259b9d0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga303898c1943aede8d1ed6b9f259b9d0c">USB_OTG_HCCHAR_EPDIR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga93cab809dbd5a48454d9370b5cc83571">USB_OTG_HCCHAR_EPDIR_Msk</a></td></tr>
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<tr class="separator:ga303898c1943aede8d1ed6b9f259b9d0c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20cb6423ef24ca58ed85c86a008849fc" id="r_ga20cb6423ef24ca58ed85c86a008849fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20cb6423ef24ca58ed85c86a008849fc">USB_OTG_HCCHAR_LSDEV_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga20cb6423ef24ca58ed85c86a008849fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3a41d259407f924e05803713ee882b5" id="r_gaf3a41d259407f924e05803713ee882b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3a41d259407f924e05803713ee882b5">USB_OTG_HCCHAR_LSDEV_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga20cb6423ef24ca58ed85c86a008849fc">USB_OTG_HCCHAR_LSDEV_Pos</a>)</td></tr>
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<tr class="separator:gaf3a41d259407f924e05803713ee882b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20e48f56546fe73be76efe518c239114" id="r_ga20e48f56546fe73be76efe518c239114"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga20e48f56546fe73be76efe518c239114">USB_OTG_HCCHAR_LSDEV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3a41d259407f924e05803713ee882b5">USB_OTG_HCCHAR_LSDEV_Msk</a></td></tr>
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<tr class="memitem:ga13ea0363e5157b965e6a96756bc1068d" id="r_ga13ea0363e5157b965e6a96756bc1068d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga13ea0363e5157b965e6a96756bc1068d">USB_OTG_HCCHAR_EPTYP_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga13ea0363e5157b965e6a96756bc1068d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga108a8e59d323596cb35aae675e3422eb" id="r_ga108a8e59d323596cb35aae675e3422eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga108a8e59d323596cb35aae675e3422eb">USB_OTG_HCCHAR_EPTYP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga13ea0363e5157b965e6a96756bc1068d">USB_OTG_HCCHAR_EPTYP_Pos</a>)</td></tr>
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<tr class="separator:ga108a8e59d323596cb35aae675e3422eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1dcca7cc02f8f9f2adf14fdd36b36055" id="r_ga1dcca7cc02f8f9f2adf14fdd36b36055"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1dcca7cc02f8f9f2adf14fdd36b36055">USB_OTG_HCCHAR_EPTYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga108a8e59d323596cb35aae675e3422eb">USB_OTG_HCCHAR_EPTYP_Msk</a></td></tr>
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<tr class="separator:ga1dcca7cc02f8f9f2adf14fdd36b36055"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1a360a7769f0c9ec5a44bdf11b0787b5" id="r_ga1a360a7769f0c9ec5a44bdf11b0787b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1a360a7769f0c9ec5a44bdf11b0787b5">USB_OTG_HCCHAR_EPTYP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga13ea0363e5157b965e6a96756bc1068d">USB_OTG_HCCHAR_EPTYP_Pos</a>)</td></tr>
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<tr class="separator:ga1a360a7769f0c9ec5a44bdf11b0787b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga88b483febece6e61c20347d02dd98b8e" id="r_ga88b483febece6e61c20347d02dd98b8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga88b483febece6e61c20347d02dd98b8e">USB_OTG_HCCHAR_EPTYP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga13ea0363e5157b965e6a96756bc1068d">USB_OTG_HCCHAR_EPTYP_Pos</a>)</td></tr>
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<tr class="separator:ga88b483febece6e61c20347d02dd98b8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga18e4b603f645b249c583dfe4f04f2518" id="r_ga18e4b603f645b249c583dfe4f04f2518"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga18e4b603f645b249c583dfe4f04f2518">USB_OTG_HCCHAR_MC_Pos</a>   (20U)</td></tr>
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<tr class="separator:ga18e4b603f645b249c583dfe4f04f2518"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab76a960e55c3396d2d3ef9b790ff9d44" id="r_gab76a960e55c3396d2d3ef9b790ff9d44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab76a960e55c3396d2d3ef9b790ff9d44">USB_OTG_HCCHAR_MC_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga18e4b603f645b249c583dfe4f04f2518">USB_OTG_HCCHAR_MC_Pos</a>)</td></tr>
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<tr class="separator:gab76a960e55c3396d2d3ef9b790ff9d44"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga373dce758b81f5555b484092be97f4f7" id="r_ga373dce758b81f5555b484092be97f4f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga373dce758b81f5555b484092be97f4f7">USB_OTG_HCCHAR_MC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab76a960e55c3396d2d3ef9b790ff9d44">USB_OTG_HCCHAR_MC_Msk</a></td></tr>
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<tr class="memitem:ga0f3c212ab7781f5f354c8081d4ef1a60" id="r_ga0f3c212ab7781f5f354c8081d4ef1a60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f3c212ab7781f5f354c8081d4ef1a60">USB_OTG_HCCHAR_MC_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga18e4b603f645b249c583dfe4f04f2518">USB_OTG_HCCHAR_MC_Pos</a>)</td></tr>
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<tr class="separator:ga0f3c212ab7781f5f354c8081d4ef1a60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5ecb48ef55ed2a5c7cf5f4ab6f0fac9" id="r_gad5ecb48ef55ed2a5c7cf5f4ab6f0fac9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad5ecb48ef55ed2a5c7cf5f4ab6f0fac9">USB_OTG_HCCHAR_MC_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga18e4b603f645b249c583dfe4f04f2518">USB_OTG_HCCHAR_MC_Pos</a>)</td></tr>
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<tr class="separator:gad5ecb48ef55ed2a5c7cf5f4ab6f0fac9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafeea28ea8c54145ee049e740da932291" id="r_gafeea28ea8c54145ee049e740da932291"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafeea28ea8c54145ee049e740da932291">USB_OTG_HCCHAR_DAD_Pos</a>   (22U)</td></tr>
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<tr class="separator:gafeea28ea8c54145ee049e740da932291"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08d35b165b6c8ca666c72993bee4a098" id="r_ga08d35b165b6c8ca666c72993bee4a098"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga08d35b165b6c8ca666c72993bee4a098">USB_OTG_HCCHAR_DAD_Msk</a>   (0x7FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafeea28ea8c54145ee049e740da932291">USB_OTG_HCCHAR_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga08d35b165b6c8ca666c72993bee4a098"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad1ef60bbb223f7605a2b58d99b0c1734" id="r_gad1ef60bbb223f7605a2b58d99b0c1734"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad1ef60bbb223f7605a2b58d99b0c1734">USB_OTG_HCCHAR_DAD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga08d35b165b6c8ca666c72993bee4a098">USB_OTG_HCCHAR_DAD_Msk</a></td></tr>
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<tr class="separator:gad1ef60bbb223f7605a2b58d99b0c1734"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3fd299a559b62badc881da2a5372ebc" id="r_gae3fd299a559b62badc881da2a5372ebc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae3fd299a559b62badc881da2a5372ebc">USB_OTG_HCCHAR_DAD_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafeea28ea8c54145ee049e740da932291">USB_OTG_HCCHAR_DAD_Pos</a>)</td></tr>
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<tr class="separator:gae3fd299a559b62badc881da2a5372ebc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga172f14d42d36a6782891fc2bb8069258" id="r_ga172f14d42d36a6782891fc2bb8069258"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga172f14d42d36a6782891fc2bb8069258">USB_OTG_HCCHAR_DAD_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafeea28ea8c54145ee049e740da932291">USB_OTG_HCCHAR_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga172f14d42d36a6782891fc2bb8069258"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6dc7e9e1a9dee8376aaa948b7caf6f8e" id="r_ga6dc7e9e1a9dee8376aaa948b7caf6f8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6dc7e9e1a9dee8376aaa948b7caf6f8e">USB_OTG_HCCHAR_DAD_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafeea28ea8c54145ee049e740da932291">USB_OTG_HCCHAR_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga6dc7e9e1a9dee8376aaa948b7caf6f8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9209069e0fc607042c54ef7394aa6b61" id="r_ga9209069e0fc607042c54ef7394aa6b61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9209069e0fc607042c54ef7394aa6b61">USB_OTG_HCCHAR_DAD_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafeea28ea8c54145ee049e740da932291">USB_OTG_HCCHAR_DAD_Pos</a>)</td></tr>
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<tr class="memitem:ga835ff39312f6b7b6b8610cdf0dcd3b99" id="r_ga835ff39312f6b7b6b8610cdf0dcd3b99"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga835ff39312f6b7b6b8610cdf0dcd3b99">USB_OTG_HCCHAR_DAD_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafeea28ea8c54145ee049e740da932291">USB_OTG_HCCHAR_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga835ff39312f6b7b6b8610cdf0dcd3b99"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga79ad8aecc4f86e9d3446691c747a48da" id="r_ga79ad8aecc4f86e9d3446691c747a48da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga79ad8aecc4f86e9d3446691c747a48da">USB_OTG_HCCHAR_DAD_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafeea28ea8c54145ee049e740da932291">USB_OTG_HCCHAR_DAD_Pos</a>)</td></tr>
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<tr class="separator:ga79ad8aecc4f86e9d3446691c747a48da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0063e054d76ae8962838b7bf9d14ef2" id="r_gad0063e054d76ae8962838b7bf9d14ef2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0063e054d76ae8962838b7bf9d14ef2">USB_OTG_HCCHAR_DAD_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafeea28ea8c54145ee049e740da932291">USB_OTG_HCCHAR_DAD_Pos</a>)</td></tr>
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<tr class="separator:gad0063e054d76ae8962838b7bf9d14ef2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2b18ec4af69c872fde54266c33774b51" id="r_ga2b18ec4af69c872fde54266c33774b51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b18ec4af69c872fde54266c33774b51">USB_OTG_HCCHAR_ODDFRM_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga2b18ec4af69c872fde54266c33774b51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf3b86db5b44b232005a73d7c660ee326" id="r_gaf3b86db5b44b232005a73d7c660ee326"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf3b86db5b44b232005a73d7c660ee326">USB_OTG_HCCHAR_ODDFRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b18ec4af69c872fde54266c33774b51">USB_OTG_HCCHAR_ODDFRM_Pos</a>)</td></tr>
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<tr class="separator:gaf3b86db5b44b232005a73d7c660ee326"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad866d817dedea4edb9514815ab3f5ae6" id="r_gad866d817dedea4edb9514815ab3f5ae6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad866d817dedea4edb9514815ab3f5ae6">USB_OTG_HCCHAR_ODDFRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaf3b86db5b44b232005a73d7c660ee326">USB_OTG_HCCHAR_ODDFRM_Msk</a></td></tr>
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<tr class="separator:gad866d817dedea4edb9514815ab3f5ae6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74f85c58e9d1ba64d4bdb8f049cd11e2" id="r_ga74f85c58e9d1ba64d4bdb8f049cd11e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74f85c58e9d1ba64d4bdb8f049cd11e2">USB_OTG_HCCHAR_CHDIS_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga74f85c58e9d1ba64d4bdb8f049cd11e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga917118333ba8be9747a356d0a27e71ae" id="r_ga917118333ba8be9747a356d0a27e71ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga917118333ba8be9747a356d0a27e71ae">USB_OTG_HCCHAR_CHDIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga74f85c58e9d1ba64d4bdb8f049cd11e2">USB_OTG_HCCHAR_CHDIS_Pos</a>)</td></tr>
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<tr class="separator:ga917118333ba8be9747a356d0a27e71ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga39de05e23016253698aa5348fffdf8a2" id="r_ga39de05e23016253698aa5348fffdf8a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga39de05e23016253698aa5348fffdf8a2">USB_OTG_HCCHAR_CHDIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga917118333ba8be9747a356d0a27e71ae">USB_OTG_HCCHAR_CHDIS_Msk</a></td></tr>
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<tr class="memitem:gaee61eaf9a8783c6a440b7835074818e5" id="r_gaee61eaf9a8783c6a440b7835074818e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaee61eaf9a8783c6a440b7835074818e5">USB_OTG_HCCHAR_CHENA_Pos</a>   (31U)</td></tr>
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<tr class="separator:gaee61eaf9a8783c6a440b7835074818e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfdd5a74cad64a4655be2486fce7230b" id="r_gacfdd5a74cad64a4655be2486fce7230b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacfdd5a74cad64a4655be2486fce7230b">USB_OTG_HCCHAR_CHENA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaee61eaf9a8783c6a440b7835074818e5">USB_OTG_HCCHAR_CHENA_Pos</a>)</td></tr>
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<tr class="separator:gacfdd5a74cad64a4655be2486fce7230b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e7dc29241b644b8bcce53440658c93f" id="r_ga1e7dc29241b644b8bcce53440658c93f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1e7dc29241b644b8bcce53440658c93f">USB_OTG_HCCHAR_CHENA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacfdd5a74cad64a4655be2486fce7230b">USB_OTG_HCCHAR_CHENA_Msk</a></td></tr>
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<tr class="memitem:ga58473c053e85bca6cd888f694dfc054a" id="r_ga58473c053e85bca6cd888f694dfc054a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a">USB_OTG_HCSPLT_PRTADDR_Pos</a>   (0U)</td></tr>
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<tr class="memitem:ga2bf43d5ac1fcccf90a4a257da69fe9b9" id="r_ga2bf43d5ac1fcccf90a4a257da69fe9b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf43d5ac1fcccf90a4a257da69fe9b9">USB_OTG_HCSPLT_PRTADDR_Msk</a>   (0x7FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a">USB_OTG_HCSPLT_PRTADDR_Pos</a>)</td></tr>
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<tr class="separator:ga2bf43d5ac1fcccf90a4a257da69fe9b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4fdaef6145025430a8d9d3742b11bf06" id="r_ga4fdaef6145025430a8d9d3742b11bf06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4fdaef6145025430a8d9d3742b11bf06">USB_OTG_HCSPLT_PRTADDR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2bf43d5ac1fcccf90a4a257da69fe9b9">USB_OTG_HCSPLT_PRTADDR_Msk</a></td></tr>
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<tr class="separator:ga4fdaef6145025430a8d9d3742b11bf06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga212d74a7af2379f1b7065bb46fbb9d2a" id="r_ga212d74a7af2379f1b7065bb46fbb9d2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga212d74a7af2379f1b7065bb46fbb9d2a">USB_OTG_HCSPLT_PRTADDR_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a">USB_OTG_HCSPLT_PRTADDR_Pos</a>)</td></tr>
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<tr class="separator:ga212d74a7af2379f1b7065bb46fbb9d2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0704e2d889ef64707ab85a66962e1004" id="r_ga0704e2d889ef64707ab85a66962e1004"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0704e2d889ef64707ab85a66962e1004">USB_OTG_HCSPLT_PRTADDR_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a">USB_OTG_HCSPLT_PRTADDR_Pos</a>)</td></tr>
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<tr class="separator:ga0704e2d889ef64707ab85a66962e1004"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab33fa67bd58f2fa736d8f64bfbea4e5c" id="r_gab33fa67bd58f2fa736d8f64bfbea4e5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab33fa67bd58f2fa736d8f64bfbea4e5c">USB_OTG_HCSPLT_PRTADDR_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a">USB_OTG_HCSPLT_PRTADDR_Pos</a>)</td></tr>
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<tr class="separator:gab33fa67bd58f2fa736d8f64bfbea4e5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac813f65324490b9885be03ff12328185" id="r_gac813f65324490b9885be03ff12328185"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac813f65324490b9885be03ff12328185">USB_OTG_HCSPLT_PRTADDR_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a">USB_OTG_HCSPLT_PRTADDR_Pos</a>)</td></tr>
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<tr class="separator:gac813f65324490b9885be03ff12328185"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab6201a61e92821955efb64d3ccffb0da" id="r_gab6201a61e92821955efb64d3ccffb0da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab6201a61e92821955efb64d3ccffb0da">USB_OTG_HCSPLT_PRTADDR_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a">USB_OTG_HCSPLT_PRTADDR_Pos</a>)</td></tr>
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<tr class="separator:gab6201a61e92821955efb64d3ccffb0da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2617f8146fa1656b415f31e9717fd875" id="r_ga2617f8146fa1656b415f31e9717fd875"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2617f8146fa1656b415f31e9717fd875">USB_OTG_HCSPLT_PRTADDR_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a">USB_OTG_HCSPLT_PRTADDR_Pos</a>)</td></tr>
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<tr class="separator:ga2617f8146fa1656b415f31e9717fd875"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c80e6a85b5960c708594433db74b713" id="r_ga6c80e6a85b5960c708594433db74b713"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c80e6a85b5960c708594433db74b713">USB_OTG_HCSPLT_PRTADDR_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a">USB_OTG_HCSPLT_PRTADDR_Pos</a>)</td></tr>
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<tr class="separator:ga6c80e6a85b5960c708594433db74b713"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9664e8f0ddccc220bf3e13df322de47c" id="r_ga9664e8f0ddccc220bf3e13df322de47c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9664e8f0ddccc220bf3e13df322de47c">USB_OTG_HCSPLT_HUBADDR_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga9664e8f0ddccc220bf3e13df322de47c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga16a3d74ca420462ff6493c0a299b49f8" id="r_ga16a3d74ca420462ff6493c0a299b49f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga16a3d74ca420462ff6493c0a299b49f8">USB_OTG_HCSPLT_HUBADDR_Msk</a>   (0x7FUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9664e8f0ddccc220bf3e13df322de47c">USB_OTG_HCSPLT_HUBADDR_Pos</a>)</td></tr>
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<tr class="separator:ga16a3d74ca420462ff6493c0a299b49f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga01754e9ee191528767bb4e9c4acb92d8" id="r_ga01754e9ee191528767bb4e9c4acb92d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga01754e9ee191528767bb4e9c4acb92d8">USB_OTG_HCSPLT_HUBADDR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga16a3d74ca420462ff6493c0a299b49f8">USB_OTG_HCSPLT_HUBADDR_Msk</a></td></tr>
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<tr class="separator:ga01754e9ee191528767bb4e9c4acb92d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6181cfe518eacf85a1fac93dd66327ec" id="r_ga6181cfe518eacf85a1fac93dd66327ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6181cfe518eacf85a1fac93dd66327ec">USB_OTG_HCSPLT_HUBADDR_0</a>   (0x01UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9664e8f0ddccc220bf3e13df322de47c">USB_OTG_HCSPLT_HUBADDR_Pos</a>)</td></tr>
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<tr class="separator:ga6181cfe518eacf85a1fac93dd66327ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb05271f1a273bc14380c9ad00288701" id="r_gaeb05271f1a273bc14380c9ad00288701"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeb05271f1a273bc14380c9ad00288701">USB_OTG_HCSPLT_HUBADDR_1</a>   (0x02UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9664e8f0ddccc220bf3e13df322de47c">USB_OTG_HCSPLT_HUBADDR_Pos</a>)</td></tr>
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<tr class="separator:gaeb05271f1a273bc14380c9ad00288701"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6d1c70b3d92a311b13635ff67f491ec0" id="r_ga6d1c70b3d92a311b13635ff67f491ec0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6d1c70b3d92a311b13635ff67f491ec0">USB_OTG_HCSPLT_HUBADDR_2</a>   (0x04UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9664e8f0ddccc220bf3e13df322de47c">USB_OTG_HCSPLT_HUBADDR_Pos</a>)</td></tr>
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<tr class="separator:ga6d1c70b3d92a311b13635ff67f491ec0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbb8d9ca0465a572fa7be1afcfa430a8" id="r_gafbb8d9ca0465a572fa7be1afcfa430a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafbb8d9ca0465a572fa7be1afcfa430a8">USB_OTG_HCSPLT_HUBADDR_3</a>   (0x08UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9664e8f0ddccc220bf3e13df322de47c">USB_OTG_HCSPLT_HUBADDR_Pos</a>)</td></tr>
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<tr class="separator:gafbb8d9ca0465a572fa7be1afcfa430a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad738cccdb8cd3c9db582d8f4aebc3e25" id="r_gad738cccdb8cd3c9db582d8f4aebc3e25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad738cccdb8cd3c9db582d8f4aebc3e25">USB_OTG_HCSPLT_HUBADDR_4</a>   (0x10UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9664e8f0ddccc220bf3e13df322de47c">USB_OTG_HCSPLT_HUBADDR_Pos</a>)</td></tr>
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<tr class="separator:gad738cccdb8cd3c9db582d8f4aebc3e25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeaa7e01257224ccaedb6ac4b34b962cf" id="r_gaeaa7e01257224ccaedb6ac4b34b962cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaeaa7e01257224ccaedb6ac4b34b962cf">USB_OTG_HCSPLT_HUBADDR_5</a>   (0x20UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9664e8f0ddccc220bf3e13df322de47c">USB_OTG_HCSPLT_HUBADDR_Pos</a>)</td></tr>
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<tr class="separator:gaeaa7e01257224ccaedb6ac4b34b962cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32808c2fdb053958a30c5ca464534557" id="r_ga32808c2fdb053958a30c5ca464534557"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32808c2fdb053958a30c5ca464534557">USB_OTG_HCSPLT_HUBADDR_6</a>   (0x40UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga9664e8f0ddccc220bf3e13df322de47c">USB_OTG_HCSPLT_HUBADDR_Pos</a>)</td></tr>
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<tr class="separator:ga32808c2fdb053958a30c5ca464534557"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga96c57d899d1d4e67d86d4f8d34712a7c" id="r_ga96c57d899d1d4e67d86d4f8d34712a7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga96c57d899d1d4e67d86d4f8d34712a7c">USB_OTG_HCSPLT_XACTPOS_Pos</a>   (14U)</td></tr>
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<tr class="separator:ga96c57d899d1d4e67d86d4f8d34712a7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6229c6f4ebd9ee5ca4cc7feeda5d3e15" id="r_ga6229c6f4ebd9ee5ca4cc7feeda5d3e15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6229c6f4ebd9ee5ca4cc7feeda5d3e15">USB_OTG_HCSPLT_XACTPOS_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96c57d899d1d4e67d86d4f8d34712a7c">USB_OTG_HCSPLT_XACTPOS_Pos</a>)</td></tr>
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<tr class="separator:ga6229c6f4ebd9ee5ca4cc7feeda5d3e15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac8a144d40531b5f7565d81ca90012f2f" id="r_gac8a144d40531b5f7565d81ca90012f2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac8a144d40531b5f7565d81ca90012f2f">USB_OTG_HCSPLT_XACTPOS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6229c6f4ebd9ee5ca4cc7feeda5d3e15">USB_OTG_HCSPLT_XACTPOS_Msk</a></td></tr>
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<tr class="separator:gac8a144d40531b5f7565d81ca90012f2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae22d65d33e06b57429f285a7ae7e655e" id="r_gae22d65d33e06b57429f285a7ae7e655e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae22d65d33e06b57429f285a7ae7e655e">USB_OTG_HCSPLT_XACTPOS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96c57d899d1d4e67d86d4f8d34712a7c">USB_OTG_HCSPLT_XACTPOS_Pos</a>)</td></tr>
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<tr class="separator:gae22d65d33e06b57429f285a7ae7e655e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d1c8241b689b9771dce804274470e08" id="r_ga0d1c8241b689b9771dce804274470e08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d1c8241b689b9771dce804274470e08">USB_OTG_HCSPLT_XACTPOS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga96c57d899d1d4e67d86d4f8d34712a7c">USB_OTG_HCSPLT_XACTPOS_Pos</a>)</td></tr>
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<tr class="separator:ga0d1c8241b689b9771dce804274470e08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d085f79d265bd2588856d35fa1c83d1" id="r_ga2d085f79d265bd2588856d35fa1c83d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2d085f79d265bd2588856d35fa1c83d1">USB_OTG_HCSPLT_COMPLSPLT_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga2d085f79d265bd2588856d35fa1c83d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74893ad7550eb4c2d08e5568f1c75c6b" id="r_ga74893ad7550eb4c2d08e5568f1c75c6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74893ad7550eb4c2d08e5568f1c75c6b">USB_OTG_HCSPLT_COMPLSPLT_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2d085f79d265bd2588856d35fa1c83d1">USB_OTG_HCSPLT_COMPLSPLT_Pos</a>)</td></tr>
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<tr class="separator:ga74893ad7550eb4c2d08e5568f1c75c6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3f351343c90321b0a43d3a86902bff1" id="r_gab3f351343c90321b0a43d3a86902bff1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3f351343c90321b0a43d3a86902bff1">USB_OTG_HCSPLT_COMPLSPLT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga74893ad7550eb4c2d08e5568f1c75c6b">USB_OTG_HCSPLT_COMPLSPLT_Msk</a></td></tr>
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<tr class="separator:gab3f351343c90321b0a43d3a86902bff1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga166c9d0c9c88d3331c2ad15ce365d8d0" id="r_ga166c9d0c9c88d3331c2ad15ce365d8d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga166c9d0c9c88d3331c2ad15ce365d8d0">USB_OTG_HCSPLT_SPLITEN_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga166c9d0c9c88d3331c2ad15ce365d8d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa1a7031a99e4d180e1510827a84f09a" id="r_gafa1a7031a99e4d180e1510827a84f09a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa1a7031a99e4d180e1510827a84f09a">USB_OTG_HCSPLT_SPLITEN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga166c9d0c9c88d3331c2ad15ce365d8d0">USB_OTG_HCSPLT_SPLITEN_Pos</a>)</td></tr>
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<tr class="separator:gafa1a7031a99e4d180e1510827a84f09a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa189a5468eabc8d2e05b2c94660060e4" id="r_gaa189a5468eabc8d2e05b2c94660060e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa189a5468eabc8d2e05b2c94660060e4">USB_OTG_HCSPLT_SPLITEN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafa1a7031a99e4d180e1510827a84f09a">USB_OTG_HCSPLT_SPLITEN_Msk</a></td></tr>
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<tr class="separator:gaa189a5468eabc8d2e05b2c94660060e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56016189953a9cbb4085baf96bb4d6c8" id="r_ga56016189953a9cbb4085baf96bb4d6c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga56016189953a9cbb4085baf96bb4d6c8">USB_OTG_HCINT_XFRC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga56016189953a9cbb4085baf96bb4d6c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae073b77821aa500ba31c336cc510a2dd" id="r_gae073b77821aa500ba31c336cc510a2dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae073b77821aa500ba31c336cc510a2dd">USB_OTG_HCINT_XFRC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga56016189953a9cbb4085baf96bb4d6c8">USB_OTG_HCINT_XFRC_Pos</a>)</td></tr>
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<tr class="separator:gae073b77821aa500ba31c336cc510a2dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga332b761dd88ddfacac9ebff6fced8846" id="r_ga332b761dd88ddfacac9ebff6fced8846"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga332b761dd88ddfacac9ebff6fced8846">USB_OTG_HCINT_XFRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae073b77821aa500ba31c336cc510a2dd">USB_OTG_HCINT_XFRC_Msk</a></td></tr>
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<tr class="separator:ga332b761dd88ddfacac9ebff6fced8846"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga356d30f2a7cbe9b63ac9dd149c872bd7" id="r_ga356d30f2a7cbe9b63ac9dd149c872bd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga356d30f2a7cbe9b63ac9dd149c872bd7">USB_OTG_HCINT_CHH_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga356d30f2a7cbe9b63ac9dd149c872bd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga177761d89d797f8d6194e6618792be8d" id="r_ga177761d89d797f8d6194e6618792be8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga177761d89d797f8d6194e6618792be8d">USB_OTG_HCINT_CHH_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga356d30f2a7cbe9b63ac9dd149c872bd7">USB_OTG_HCINT_CHH_Pos</a>)</td></tr>
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<tr class="separator:ga177761d89d797f8d6194e6618792be8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf4ecd695c1cc06335445a49780888bb1" id="r_gaf4ecd695c1cc06335445a49780888bb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf4ecd695c1cc06335445a49780888bb1">USB_OTG_HCINT_CHH</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga177761d89d797f8d6194e6618792be8d">USB_OTG_HCINT_CHH_Msk</a></td></tr>
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<tr class="separator:gaf4ecd695c1cc06335445a49780888bb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a20fc8de6dd01708697f76f73b9844b" id="r_ga2a20fc8de6dd01708697f76f73b9844b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a20fc8de6dd01708697f76f73b9844b">USB_OTG_HCINT_AHBERR_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga2a20fc8de6dd01708697f76f73b9844b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab7250908e6d8ad8ab40adccafdae4f9" id="r_gaab7250908e6d8ad8ab40adccafdae4f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab7250908e6d8ad8ab40adccafdae4f9">USB_OTG_HCINT_AHBERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a20fc8de6dd01708697f76f73b9844b">USB_OTG_HCINT_AHBERR_Pos</a>)</td></tr>
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<tr class="separator:gaab7250908e6d8ad8ab40adccafdae4f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae8b909ca659271857d9f3fcc817d8a4a" id="r_gae8b909ca659271857d9f3fcc817d8a4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae8b909ca659271857d9f3fcc817d8a4a">USB_OTG_HCINT_AHBERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaab7250908e6d8ad8ab40adccafdae4f9">USB_OTG_HCINT_AHBERR_Msk</a></td></tr>
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<tr class="separator:gae8b909ca659271857d9f3fcc817d8a4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d9beff066b9b48480c25194af3004aa" id="r_ga4d9beff066b9b48480c25194af3004aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d9beff066b9b48480c25194af3004aa">USB_OTG_HCINT_STALL_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga4d9beff066b9b48480c25194af3004aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadd9b71968e54876f10fca2af973a95fb" id="r_gadd9b71968e54876f10fca2af973a95fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadd9b71968e54876f10fca2af973a95fb">USB_OTG_HCINT_STALL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4d9beff066b9b48480c25194af3004aa">USB_OTG_HCINT_STALL_Pos</a>)</td></tr>
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<tr class="separator:gadd9b71968e54876f10fca2af973a95fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe1d65156f846dcecac479a451b5109e" id="r_gabe1d65156f846dcecac479a451b5109e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabe1d65156f846dcecac479a451b5109e">USB_OTG_HCINT_STALL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadd9b71968e54876f10fca2af973a95fb">USB_OTG_HCINT_STALL_Msk</a></td></tr>
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<tr class="separator:gabe1d65156f846dcecac479a451b5109e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad31cbff32e8f912b9dd70fa421465fab" id="r_gad31cbff32e8f912b9dd70fa421465fab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad31cbff32e8f912b9dd70fa421465fab">USB_OTG_HCINT_NAK_Pos</a>   (4U)</td></tr>
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<tr class="separator:gad31cbff32e8f912b9dd70fa421465fab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62c4fd21ba532f275b90104da9c69825" id="r_ga62c4fd21ba532f275b90104da9c69825"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga62c4fd21ba532f275b90104da9c69825">USB_OTG_HCINT_NAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad31cbff32e8f912b9dd70fa421465fab">USB_OTG_HCINT_NAK_Pos</a>)</td></tr>
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<tr class="separator:ga62c4fd21ba532f275b90104da9c69825"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga069dfb657cf84125520ec5e4f20b8da0" id="r_ga069dfb657cf84125520ec5e4f20b8da0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga069dfb657cf84125520ec5e4f20b8da0">USB_OTG_HCINT_NAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga62c4fd21ba532f275b90104da9c69825">USB_OTG_HCINT_NAK_Msk</a></td></tr>
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<tr class="separator:ga069dfb657cf84125520ec5e4f20b8da0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24055327fbeb5884d6df6de0657ae195" id="r_ga24055327fbeb5884d6df6de0657ae195"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga24055327fbeb5884d6df6de0657ae195">USB_OTG_HCINT_ACK_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga24055327fbeb5884d6df6de0657ae195"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ab325ca96f65ccaea0b7abb66b33702" id="r_ga9ab325ca96f65ccaea0b7abb66b33702"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ab325ca96f65ccaea0b7abb66b33702">USB_OTG_HCINT_ACK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga24055327fbeb5884d6df6de0657ae195">USB_OTG_HCINT_ACK_Pos</a>)</td></tr>
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<tr class="separator:ga9ab325ca96f65ccaea0b7abb66b33702"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7bdbdb2fe8526b144ca06b537c5acdd0" id="r_ga7bdbdb2fe8526b144ca06b537c5acdd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7bdbdb2fe8526b144ca06b537c5acdd0">USB_OTG_HCINT_ACK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9ab325ca96f65ccaea0b7abb66b33702">USB_OTG_HCINT_ACK_Msk</a></td></tr>
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<tr class="separator:ga7bdbdb2fe8526b144ca06b537c5acdd0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c596c2aae4b88e04a122a9af560730e" id="r_ga4c596c2aae4b88e04a122a9af560730e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4c596c2aae4b88e04a122a9af560730e">USB_OTG_HCINT_NYET_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga4c596c2aae4b88e04a122a9af560730e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga516eea514a6024132cc66218882582dd" id="r_ga516eea514a6024132cc66218882582dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga516eea514a6024132cc66218882582dd">USB_OTG_HCINT_NYET_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4c596c2aae4b88e04a122a9af560730e">USB_OTG_HCINT_NYET_Pos</a>)</td></tr>
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<tr class="separator:ga516eea514a6024132cc66218882582dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f54751dc8abdbd65c786d2736cc2038" id="r_ga0f54751dc8abdbd65c786d2736cc2038"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0f54751dc8abdbd65c786d2736cc2038">USB_OTG_HCINT_NYET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga516eea514a6024132cc66218882582dd">USB_OTG_HCINT_NYET_Msk</a></td></tr>
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<tr class="separator:ga0f54751dc8abdbd65c786d2736cc2038"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cf2523fa4c59105d01a17d4caac3cbf" id="r_ga7cf2523fa4c59105d01a17d4caac3cbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cf2523fa4c59105d01a17d4caac3cbf">USB_OTG_HCINT_TXERR_Pos</a>   (7U)</td></tr>
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<tr class="separator:ga7cf2523fa4c59105d01a17d4caac3cbf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga158802078f5364292b4b93103aef6b1f" id="r_ga158802078f5364292b4b93103aef6b1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga158802078f5364292b4b93103aef6b1f">USB_OTG_HCINT_TXERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cf2523fa4c59105d01a17d4caac3cbf">USB_OTG_HCINT_TXERR_Pos</a>)</td></tr>
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<tr class="separator:ga158802078f5364292b4b93103aef6b1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e34974081aceef1865b83e47d48d158" id="r_ga7e34974081aceef1865b83e47d48d158"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7e34974081aceef1865b83e47d48d158">USB_OTG_HCINT_TXERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga158802078f5364292b4b93103aef6b1f">USB_OTG_HCINT_TXERR_Msk</a></td></tr>
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<tr class="separator:ga7e34974081aceef1865b83e47d48d158"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaace090462b379413a409acffad4d33ca" id="r_gaace090462b379413a409acffad4d33ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaace090462b379413a409acffad4d33ca">USB_OTG_HCINT_BBERR_Pos</a>   (8U)</td></tr>
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<tr class="separator:gaace090462b379413a409acffad4d33ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71fa9e120a3bfed31484cfd157f11fbc" id="r_ga71fa9e120a3bfed31484cfd157f11fbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71fa9e120a3bfed31484cfd157f11fbc">USB_OTG_HCINT_BBERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaace090462b379413a409acffad4d33ca">USB_OTG_HCINT_BBERR_Pos</a>)</td></tr>
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<tr class="separator:ga71fa9e120a3bfed31484cfd157f11fbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3b7e21abc4b3e5ea1eff06eb0850441" id="r_gaa3b7e21abc4b3e5ea1eff06eb0850441"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3b7e21abc4b3e5ea1eff06eb0850441">USB_OTG_HCINT_BBERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71fa9e120a3bfed31484cfd157f11fbc">USB_OTG_HCINT_BBERR_Msk</a></td></tr>
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<tr class="separator:gaa3b7e21abc4b3e5ea1eff06eb0850441"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab72d52c361d7fc77fcca26897e5a1bd9" id="r_gab72d52c361d7fc77fcca26897e5a1bd9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab72d52c361d7fc77fcca26897e5a1bd9">USB_OTG_HCINT_FRMOR_Pos</a>   (9U)</td></tr>
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<tr class="separator:gab72d52c361d7fc77fcca26897e5a1bd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa98c0c3233732702f627741e818b08ae" id="r_gaa98c0c3233732702f627741e818b08ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa98c0c3233732702f627741e818b08ae">USB_OTG_HCINT_FRMOR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab72d52c361d7fc77fcca26897e5a1bd9">USB_OTG_HCINT_FRMOR_Pos</a>)</td></tr>
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<tr class="separator:gaa98c0c3233732702f627741e818b08ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7805a112e2897572bffee4c25042cc9" id="r_gad7805a112e2897572bffee4c25042cc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7805a112e2897572bffee4c25042cc9">USB_OTG_HCINT_FRMOR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa98c0c3233732702f627741e818b08ae">USB_OTG_HCINT_FRMOR_Msk</a></td></tr>
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<tr class="separator:gad7805a112e2897572bffee4c25042cc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69cbb7f274c4d4f82666599af8dd5428" id="r_ga69cbb7f274c4d4f82666599af8dd5428"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69cbb7f274c4d4f82666599af8dd5428">USB_OTG_HCINT_DTERR_Pos</a>   (10U)</td></tr>
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<tr class="separator:ga69cbb7f274c4d4f82666599af8dd5428"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac35a8a3f2a57b8881cb825c07f263570" id="r_gac35a8a3f2a57b8881cb825c07f263570"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac35a8a3f2a57b8881cb825c07f263570">USB_OTG_HCINT_DTERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga69cbb7f274c4d4f82666599af8dd5428">USB_OTG_HCINT_DTERR_Pos</a>)</td></tr>
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<tr class="separator:gac35a8a3f2a57b8881cb825c07f263570"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0089841c8301b5e572e29da28ef95467" id="r_ga0089841c8301b5e572e29da28ef95467"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0089841c8301b5e572e29da28ef95467">USB_OTG_HCINT_DTERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac35a8a3f2a57b8881cb825c07f263570">USB_OTG_HCINT_DTERR_Msk</a></td></tr>
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<tr class="memitem:ga48ad51eeb41d7d5a2708467685dc81b3" id="r_ga48ad51eeb41d7d5a2708467685dc81b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48ad51eeb41d7d5a2708467685dc81b3">USB_OTG_DIEPINT_XFRC_Pos</a>   (0U)</td></tr>
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<tr class="memitem:gac2947aa5667ae63ee9bcb747ae955a0b" id="r_gac2947aa5667ae63ee9bcb747ae955a0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2947aa5667ae63ee9bcb747ae955a0b">USB_OTG_DIEPINT_XFRC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga48ad51eeb41d7d5a2708467685dc81b3">USB_OTG_DIEPINT_XFRC_Pos</a>)</td></tr>
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<tr class="separator:gac2947aa5667ae63ee9bcb747ae955a0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab01f771d126cb58a8cb83841e08bec9b" id="r_gab01f771d126cb58a8cb83841e08bec9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab01f771d126cb58a8cb83841e08bec9b">USB_OTG_DIEPINT_XFRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac2947aa5667ae63ee9bcb747ae955a0b">USB_OTG_DIEPINT_XFRC_Msk</a></td></tr>
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<tr class="memitem:gaa8e3323ea3b0713a2308da446c5d627b" id="r_gaa8e3323ea3b0713a2308da446c5d627b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8e3323ea3b0713a2308da446c5d627b">USB_OTG_DIEPINT_EPDISD_Pos</a>   (1U)</td></tr>
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<tr class="separator:gaa8e3323ea3b0713a2308da446c5d627b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa8a90367a919959f753ed93ac388259d" id="r_gaa8a90367a919959f753ed93ac388259d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa8a90367a919959f753ed93ac388259d">USB_OTG_DIEPINT_EPDISD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8e3323ea3b0713a2308da446c5d627b">USB_OTG_DIEPINT_EPDISD_Pos</a>)</td></tr>
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<tr class="memitem:ga657c139dc16514808c516bff6e523531" id="r_ga657c139dc16514808c516bff6e523531"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga657c139dc16514808c516bff6e523531">USB_OTG_DIEPINT_EPDISD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa8a90367a919959f753ed93ac388259d">USB_OTG_DIEPINT_EPDISD_Msk</a></td></tr>
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<tr class="memitem:ga928709eec43877b93798c748fdb8fe6e" id="r_ga928709eec43877b93798c748fdb8fe6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga928709eec43877b93798c748fdb8fe6e">USB_OTG_DIEPINT_AHBERR_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga928709eec43877b93798c748fdb8fe6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3854f2057e03eb6e282a34d4d26f5093" id="r_ga3854f2057e03eb6e282a34d4d26f5093"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3854f2057e03eb6e282a34d4d26f5093">USB_OTG_DIEPINT_AHBERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga928709eec43877b93798c748fdb8fe6e">USB_OTG_DIEPINT_AHBERR_Pos</a>)</td></tr>
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<tr class="separator:ga3854f2057e03eb6e282a34d4d26f5093"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga630e92ca04288a83f7f515cedbf01ca9" id="r_ga630e92ca04288a83f7f515cedbf01ca9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga630e92ca04288a83f7f515cedbf01ca9">USB_OTG_DIEPINT_AHBERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3854f2057e03eb6e282a34d4d26f5093">USB_OTG_DIEPINT_AHBERR_Msk</a></td></tr>
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<tr class="memitem:ga86a45c7c6fc7a421171a0d6179646f85" id="r_ga86a45c7c6fc7a421171a0d6179646f85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga86a45c7c6fc7a421171a0d6179646f85">USB_OTG_DIEPINT_TOC_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga86a45c7c6fc7a421171a0d6179646f85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ca3db2648c05083065675eda6aaef0e" id="r_ga1ca3db2648c05083065675eda6aaef0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1ca3db2648c05083065675eda6aaef0e">USB_OTG_DIEPINT_TOC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga86a45c7c6fc7a421171a0d6179646f85">USB_OTG_DIEPINT_TOC_Pos</a>)</td></tr>
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<tr class="memitem:ga253fce8bc78be1504c85d684f232dc43" id="r_ga253fce8bc78be1504c85d684f232dc43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga253fce8bc78be1504c85d684f232dc43">USB_OTG_DIEPINT_TOC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1ca3db2648c05083065675eda6aaef0e">USB_OTG_DIEPINT_TOC_Msk</a></td></tr>
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<tr class="memitem:ga72bfd0fc0d049c2b27634300aba27e28" id="r_ga72bfd0fc0d049c2b27634300aba27e28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga72bfd0fc0d049c2b27634300aba27e28">USB_OTG_DIEPINT_ITTXFE_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga72bfd0fc0d049c2b27634300aba27e28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad15ffda9000245db34322f4a75b31780" id="r_gad15ffda9000245db34322f4a75b31780"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad15ffda9000245db34322f4a75b31780">USB_OTG_DIEPINT_ITTXFE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga72bfd0fc0d049c2b27634300aba27e28">USB_OTG_DIEPINT_ITTXFE_Pos</a>)</td></tr>
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<tr class="separator:gad15ffda9000245db34322f4a75b31780"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0f91471274c3411579a7ede5a7d80f8" id="r_gad0f91471274c3411579a7ede5a7d80f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad0f91471274c3411579a7ede5a7d80f8">USB_OTG_DIEPINT_ITTXFE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad15ffda9000245db34322f4a75b31780">USB_OTG_DIEPINT_ITTXFE_Msk</a></td></tr>
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<tr class="separator:gad0f91471274c3411579a7ede5a7d80f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c1240b1526225892f7518ed1e6ad3f8" id="r_ga8c1240b1526225892f7518ed1e6ad3f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c1240b1526225892f7518ed1e6ad3f8">USB_OTG_DIEPINT_INEPNM_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga8c1240b1526225892f7518ed1e6ad3f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c72659090e081560681486217bc9e21" id="r_ga6c72659090e081560681486217bc9e21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6c72659090e081560681486217bc9e21">USB_OTG_DIEPINT_INEPNM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c1240b1526225892f7518ed1e6ad3f8">USB_OTG_DIEPINT_INEPNM_Pos</a>)</td></tr>
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<tr class="separator:ga6c72659090e081560681486217bc9e21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb8ac53eab340e711478e5509be40e13" id="r_gafb8ac53eab340e711478e5509be40e13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb8ac53eab340e711478e5509be40e13">USB_OTG_DIEPINT_INEPNM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6c72659090e081560681486217bc9e21">USB_OTG_DIEPINT_INEPNM_Msk</a></td></tr>
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<tr class="memitem:ga99e5d6f548490c1a8e3c3b8f8332a6d0" id="r_ga99e5d6f548490c1a8e3c3b8f8332a6d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga99e5d6f548490c1a8e3c3b8f8332a6d0">USB_OTG_DIEPINT_INEPNE_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga99e5d6f548490c1a8e3c3b8f8332a6d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98ecb4c61f48a1fc073cda01f1599ad6" id="r_ga98ecb4c61f48a1fc073cda01f1599ad6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga98ecb4c61f48a1fc073cda01f1599ad6">USB_OTG_DIEPINT_INEPNE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga99e5d6f548490c1a8e3c3b8f8332a6d0">USB_OTG_DIEPINT_INEPNE_Pos</a>)</td></tr>
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<tr class="separator:ga98ecb4c61f48a1fc073cda01f1599ad6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40fbe18a5838e768b9afca5c1695dbb3" id="r_ga40fbe18a5838e768b9afca5c1695dbb3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga40fbe18a5838e768b9afca5c1695dbb3">USB_OTG_DIEPINT_INEPNE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga98ecb4c61f48a1fc073cda01f1599ad6">USB_OTG_DIEPINT_INEPNE_Msk</a></td></tr>
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<tr class="separator:ga40fbe18a5838e768b9afca5c1695dbb3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab28f246cb52201b01baa4f85be3c196" id="r_gaab28f246cb52201b01baa4f85be3c196"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab28f246cb52201b01baa4f85be3c196">USB_OTG_DIEPINT_TXFE_Pos</a>   (7U)</td></tr>
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<tr class="separator:gaab28f246cb52201b01baa4f85be3c196"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadea85fa99c59be521a394f7cfeeadf25" id="r_gadea85fa99c59be521a394f7cfeeadf25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadea85fa99c59be521a394f7cfeeadf25">USB_OTG_DIEPINT_TXFE_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaab28f246cb52201b01baa4f85be3c196">USB_OTG_DIEPINT_TXFE_Pos</a>)</td></tr>
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<tr class="separator:gadea85fa99c59be521a394f7cfeeadf25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae4770cce2b4f601e88fb512f6db688ec" id="r_gae4770cce2b4f601e88fb512f6db688ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae4770cce2b4f601e88fb512f6db688ec">USB_OTG_DIEPINT_TXFE</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadea85fa99c59be521a394f7cfeeadf25">USB_OTG_DIEPINT_TXFE_Msk</a></td></tr>
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<tr class="separator:gae4770cce2b4f601e88fb512f6db688ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga795f1914ee10b65cd745129afc32b51f" id="r_ga795f1914ee10b65cd745129afc32b51f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga795f1914ee10b65cd745129afc32b51f">USB_OTG_DIEPINT_TXFIFOUDRN_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga795f1914ee10b65cd745129afc32b51f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaffc8a052f72319f433728b6571098ba0" id="r_gaffc8a052f72319f433728b6571098ba0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaffc8a052f72319f433728b6571098ba0">USB_OTG_DIEPINT_TXFIFOUDRN_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga795f1914ee10b65cd745129afc32b51f">USB_OTG_DIEPINT_TXFIFOUDRN_Pos</a>)</td></tr>
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<tr class="separator:gaffc8a052f72319f433728b6571098ba0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga934d166eae0af7663585c903567ebe2b" id="r_ga934d166eae0af7663585c903567ebe2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga934d166eae0af7663585c903567ebe2b">USB_OTG_DIEPINT_TXFIFOUDRN</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaffc8a052f72319f433728b6571098ba0">USB_OTG_DIEPINT_TXFIFOUDRN_Msk</a></td></tr>
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<tr class="separator:ga934d166eae0af7663585c903567ebe2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c35d8a426e47ad0a81add3adb9adbad" id="r_ga5c35d8a426e47ad0a81add3adb9adbad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5c35d8a426e47ad0a81add3adb9adbad">USB_OTG_DIEPINT_BNA_Pos</a>   (9U)</td></tr>
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<tr class="separator:ga5c35d8a426e47ad0a81add3adb9adbad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92124e1fe13558df5464e356658e67b2" id="r_ga92124e1fe13558df5464e356658e67b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92124e1fe13558df5464e356658e67b2">USB_OTG_DIEPINT_BNA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5c35d8a426e47ad0a81add3adb9adbad">USB_OTG_DIEPINT_BNA_Pos</a>)</td></tr>
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<tr class="separator:ga92124e1fe13558df5464e356658e67b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22983c7c561dedc17e8688d313a50fb0" id="r_ga22983c7c561dedc17e8688d313a50fb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22983c7c561dedc17e8688d313a50fb0">USB_OTG_DIEPINT_BNA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga92124e1fe13558df5464e356658e67b2">USB_OTG_DIEPINT_BNA_Msk</a></td></tr>
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<tr class="separator:ga22983c7c561dedc17e8688d313a50fb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45fcaff3092226af9b6df98e6f4e3c5f" id="r_ga45fcaff3092226af9b6df98e6f4e3c5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45fcaff3092226af9b6df98e6f4e3c5f">USB_OTG_DIEPINT_PKTDRPSTS_Pos</a>   (11U)</td></tr>
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<tr class="separator:ga45fcaff3092226af9b6df98e6f4e3c5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bbb4304aaa31dceb651eb6ebea21ca4" id="r_ga5bbb4304aaa31dceb651eb6ebea21ca4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bbb4304aaa31dceb651eb6ebea21ca4">USB_OTG_DIEPINT_PKTDRPSTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga45fcaff3092226af9b6df98e6f4e3c5f">USB_OTG_DIEPINT_PKTDRPSTS_Pos</a>)</td></tr>
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<tr class="memitem:ga5bf74048c663e9dcc21c282a8c7be576" id="r_ga5bf74048c663e9dcc21c282a8c7be576"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bf74048c663e9dcc21c282a8c7be576">USB_OTG_DIEPINT_PKTDRPSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bbb4304aaa31dceb651eb6ebea21ca4">USB_OTG_DIEPINT_PKTDRPSTS_Msk</a></td></tr>
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<tr class="memitem:ga2b3a9433ebbf032f80b3a26b2b10e4c9" id="r_ga2b3a9433ebbf032f80b3a26b2b10e4c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2b3a9433ebbf032f80b3a26b2b10e4c9">USB_OTG_DIEPINT_BERR_Pos</a>   (12U)</td></tr>
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<tr class="separator:ga2b3a9433ebbf032f80b3a26b2b10e4c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7902d1f040d0669ad22a9cb4a1e88bdd" id="r_ga7902d1f040d0669ad22a9cb4a1e88bdd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7902d1f040d0669ad22a9cb4a1e88bdd">USB_OTG_DIEPINT_BERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2b3a9433ebbf032f80b3a26b2b10e4c9">USB_OTG_DIEPINT_BERR_Pos</a>)</td></tr>
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<tr class="separator:ga7902d1f040d0669ad22a9cb4a1e88bdd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga496c09a9096346e6141acc2464742b4c" id="r_ga496c09a9096346e6141acc2464742b4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga496c09a9096346e6141acc2464742b4c">USB_OTG_DIEPINT_BERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7902d1f040d0669ad22a9cb4a1e88bdd">USB_OTG_DIEPINT_BERR_Msk</a></td></tr>
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<tr class="memitem:ga78a4751b6393d56bdd1d4e1c837c217e" id="r_ga78a4751b6393d56bdd1d4e1c837c217e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga78a4751b6393d56bdd1d4e1c837c217e">USB_OTG_DIEPINT_NAK_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga78a4751b6393d56bdd1d4e1c837c217e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaafb6909297147bb09786d5e20715656c" id="r_gaafb6909297147bb09786d5e20715656c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaafb6909297147bb09786d5e20715656c">USB_OTG_DIEPINT_NAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga78a4751b6393d56bdd1d4e1c837c217e">USB_OTG_DIEPINT_NAK_Pos</a>)</td></tr>
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<tr class="separator:gaafb6909297147bb09786d5e20715656c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d91e68b693b9c8ff6fb2236093975cf" id="r_ga9d91e68b693b9c8ff6fb2236093975cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9d91e68b693b9c8ff6fb2236093975cf">USB_OTG_DIEPINT_NAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaafb6909297147bb09786d5e20715656c">USB_OTG_DIEPINT_NAK_Msk</a></td></tr>
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<tr class="separator:ga9d91e68b693b9c8ff6fb2236093975cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3a724642ee5e5c4fb980d2091e5f1b4" id="r_gaa3a724642ee5e5c4fb980d2091e5f1b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3a724642ee5e5c4fb980d2091e5f1b4">USB_OTG_HCINTMSK_XFRCM_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa3a724642ee5e5c4fb980d2091e5f1b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e1633eb41c92d2a0716e893d10ea404" id="r_ga6e1633eb41c92d2a0716e893d10ea404"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6e1633eb41c92d2a0716e893d10ea404">USB_OTG_HCINTMSK_XFRCM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3a724642ee5e5c4fb980d2091e5f1b4">USB_OTG_HCINTMSK_XFRCM_Pos</a>)</td></tr>
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<tr class="separator:ga6e1633eb41c92d2a0716e893d10ea404"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3647bba98a8f2c2234aadb2f9441874" id="r_gaa3647bba98a8f2c2234aadb2f9441874"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3647bba98a8f2c2234aadb2f9441874">USB_OTG_HCINTMSK_XFRCM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6e1633eb41c92d2a0716e893d10ea404">USB_OTG_HCINTMSK_XFRCM_Msk</a></td></tr>
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<tr class="separator:gaa3647bba98a8f2c2234aadb2f9441874"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a9e51a34d9b5145d7c4d92a342ffb9c" id="r_ga5a9e51a34d9b5145d7c4d92a342ffb9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a9e51a34d9b5145d7c4d92a342ffb9c">USB_OTG_HCINTMSK_CHHM_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga5a9e51a34d9b5145d7c4d92a342ffb9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa6cb390f8f0cf8a561f41a88a8339d7e" id="r_gaa6cb390f8f0cf8a561f41a88a8339d7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa6cb390f8f0cf8a561f41a88a8339d7e">USB_OTG_HCINTMSK_CHHM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5a9e51a34d9b5145d7c4d92a342ffb9c">USB_OTG_HCINTMSK_CHHM_Pos</a>)</td></tr>
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<tr class="separator:gaa6cb390f8f0cf8a561f41a88a8339d7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f359b89c79fba4414e0838645f13a6b" id="r_ga8f359b89c79fba4414e0838645f13a6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f359b89c79fba4414e0838645f13a6b">USB_OTG_HCINTMSK_CHHM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa6cb390f8f0cf8a561f41a88a8339d7e">USB_OTG_HCINTMSK_CHHM_Msk</a></td></tr>
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<tr class="separator:ga8f359b89c79fba4414e0838645f13a6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d753e4c1acd73bd24b7e4d07405d94a" id="r_ga0d753e4c1acd73bd24b7e4d07405d94a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0d753e4c1acd73bd24b7e4d07405d94a">USB_OTG_HCINTMSK_AHBERR_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga0d753e4c1acd73bd24b7e4d07405d94a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70c101e1a4e376d61f77fcf4f5f32bf6" id="r_ga70c101e1a4e376d61f77fcf4f5f32bf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga70c101e1a4e376d61f77fcf4f5f32bf6">USB_OTG_HCINTMSK_AHBERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0d753e4c1acd73bd24b7e4d07405d94a">USB_OTG_HCINTMSK_AHBERR_Pos</a>)</td></tr>
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<tr class="separator:ga70c101e1a4e376d61f77fcf4f5f32bf6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf281bb6b61c559e8b068ab32114572af" id="r_gaf281bb6b61c559e8b068ab32114572af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf281bb6b61c559e8b068ab32114572af">USB_OTG_HCINTMSK_AHBERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga70c101e1a4e376d61f77fcf4f5f32bf6">USB_OTG_HCINTMSK_AHBERR_Msk</a></td></tr>
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<tr class="separator:gaf281bb6b61c559e8b068ab32114572af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafafbf0f454f7c9f2ca81e29897782cd7" id="r_gafafbf0f454f7c9f2ca81e29897782cd7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafafbf0f454f7c9f2ca81e29897782cd7">USB_OTG_HCINTMSK_STALLM_Pos</a>   (3U)</td></tr>
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<tr class="separator:gafafbf0f454f7c9f2ca81e29897782cd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga60f5b08f1a892221f86f3cb370260ef6" id="r_ga60f5b08f1a892221f86f3cb370260ef6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga60f5b08f1a892221f86f3cb370260ef6">USB_OTG_HCINTMSK_STALLM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafafbf0f454f7c9f2ca81e29897782cd7">USB_OTG_HCINTMSK_STALLM_Pos</a>)</td></tr>
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<tr class="separator:ga60f5b08f1a892221f86f3cb370260ef6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga001d17d4511b40850fd7c338be250f08" id="r_ga001d17d4511b40850fd7c338be250f08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga001d17d4511b40850fd7c338be250f08">USB_OTG_HCINTMSK_STALLM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga60f5b08f1a892221f86f3cb370260ef6">USB_OTG_HCINTMSK_STALLM_Msk</a></td></tr>
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<tr class="separator:ga001d17d4511b40850fd7c338be250f08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5163e183955b5eca93ec5dcaf1915a5f" id="r_ga5163e183955b5eca93ec5dcaf1915a5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5163e183955b5eca93ec5dcaf1915a5f">USB_OTG_HCINTMSK_NAKM_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga5163e183955b5eca93ec5dcaf1915a5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51cc9dd53764be5f1d2ff3d5c7241fd3" id="r_ga51cc9dd53764be5f1d2ff3d5c7241fd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51cc9dd53764be5f1d2ff3d5c7241fd3">USB_OTG_HCINTMSK_NAKM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5163e183955b5eca93ec5dcaf1915a5f">USB_OTG_HCINTMSK_NAKM_Pos</a>)</td></tr>
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<tr class="separator:ga51cc9dd53764be5f1d2ff3d5c7241fd3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51b9246da6c3a45ab697edc1cac74651" id="r_ga51b9246da6c3a45ab697edc1cac74651"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga51b9246da6c3a45ab697edc1cac74651">USB_OTG_HCINTMSK_NAKM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga51cc9dd53764be5f1d2ff3d5c7241fd3">USB_OTG_HCINTMSK_NAKM_Msk</a></td></tr>
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<tr class="separator:ga51b9246da6c3a45ab697edc1cac74651"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67b66f3e3480ac1542b1a1f4ce8d0970" id="r_ga67b66f3e3480ac1542b1a1f4ce8d0970"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67b66f3e3480ac1542b1a1f4ce8d0970">USB_OTG_HCINTMSK_ACKM_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga67b66f3e3480ac1542b1a1f4ce8d0970"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga372e5e68431087f0fb3b25408ce9eec9" id="r_ga372e5e68431087f0fb3b25408ce9eec9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga372e5e68431087f0fb3b25408ce9eec9">USB_OTG_HCINTMSK_ACKM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67b66f3e3480ac1542b1a1f4ce8d0970">USB_OTG_HCINTMSK_ACKM_Pos</a>)</td></tr>
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<tr class="separator:ga372e5e68431087f0fb3b25408ce9eec9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga21eb5c0fa8aafa12a725ab52f85023d1" id="r_ga21eb5c0fa8aafa12a725ab52f85023d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga21eb5c0fa8aafa12a725ab52f85023d1">USB_OTG_HCINTMSK_ACKM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga372e5e68431087f0fb3b25408ce9eec9">USB_OTG_HCINTMSK_ACKM_Msk</a></td></tr>
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<tr class="separator:ga21eb5c0fa8aafa12a725ab52f85023d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49e120401dd9574089323f30a21ce886" id="r_ga49e120401dd9574089323f30a21ce886"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga49e120401dd9574089323f30a21ce886">USB_OTG_HCINTMSK_NYET_Pos</a>   (6U)</td></tr>
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<tr class="separator:ga49e120401dd9574089323f30a21ce886"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac6b099d2da095f8d31fe49ad9b9ecc90" id="r_gac6b099d2da095f8d31fe49ad9b9ecc90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac6b099d2da095f8d31fe49ad9b9ecc90">USB_OTG_HCINTMSK_NYET_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga49e120401dd9574089323f30a21ce886">USB_OTG_HCINTMSK_NYET_Pos</a>)</td></tr>
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<tr class="separator:gac6b099d2da095f8d31fe49ad9b9ecc90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga059e35d45f848183cf19399ac1e21ff5" id="r_ga059e35d45f848183cf19399ac1e21ff5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga059e35d45f848183cf19399ac1e21ff5">USB_OTG_HCINTMSK_NYET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac6b099d2da095f8d31fe49ad9b9ecc90">USB_OTG_HCINTMSK_NYET_Msk</a></td></tr>
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<tr class="separator:ga059e35d45f848183cf19399ac1e21ff5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7091461a6aef6b084ca11343b1fcb8a" id="r_gad7091461a6aef6b084ca11343b1fcb8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad7091461a6aef6b084ca11343b1fcb8a">USB_OTG_HCINTMSK_TXERRM_Pos</a>   (7U)</td></tr>
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<tr class="separator:gad7091461a6aef6b084ca11343b1fcb8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5bbe2d77401d28701eb827ac3d4cd149" id="r_ga5bbe2d77401d28701eb827ac3d4cd149"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5bbe2d77401d28701eb827ac3d4cd149">USB_OTG_HCINTMSK_TXERRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad7091461a6aef6b084ca11343b1fcb8a">USB_OTG_HCINTMSK_TXERRM_Pos</a>)</td></tr>
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<tr class="memitem:ga5322b79193b042004614b21c391d4880" id="r_ga5322b79193b042004614b21c391d4880"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5322b79193b042004614b21c391d4880">USB_OTG_HCINTMSK_TXERRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5bbe2d77401d28701eb827ac3d4cd149">USB_OTG_HCINTMSK_TXERRM_Msk</a></td></tr>
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<tr class="memitem:gabadb45319c35046abce6475a1105a3d6" id="r_gabadb45319c35046abce6475a1105a3d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabadb45319c35046abce6475a1105a3d6">USB_OTG_HCINTMSK_BBERRM_Pos</a>   (8U)</td></tr>
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<tr class="separator:gabadb45319c35046abce6475a1105a3d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f9165c1fbf87679bb83efa46571b96c" id="r_ga2f9165c1fbf87679bb83efa46571b96c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f9165c1fbf87679bb83efa46571b96c">USB_OTG_HCINTMSK_BBERRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabadb45319c35046abce6475a1105a3d6">USB_OTG_HCINTMSK_BBERRM_Pos</a>)</td></tr>
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<tr class="separator:ga2f9165c1fbf87679bb83efa46571b96c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9ae263bd38eec1c423b0a70904b5099a" id="r_ga9ae263bd38eec1c423b0a70904b5099a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9ae263bd38eec1c423b0a70904b5099a">USB_OTG_HCINTMSK_BBERRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f9165c1fbf87679bb83efa46571b96c">USB_OTG_HCINTMSK_BBERRM_Msk</a></td></tr>
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<tr class="separator:ga9ae263bd38eec1c423b0a70904b5099a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac75612d12f30f20d62f93d75bfe2d93a" id="r_gac75612d12f30f20d62f93d75bfe2d93a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac75612d12f30f20d62f93d75bfe2d93a">USB_OTG_HCINTMSK_FRMORM_Pos</a>   (9U)</td></tr>
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<tr class="separator:gac75612d12f30f20d62f93d75bfe2d93a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gada017fb34e00a15702d759ff174d33ff" id="r_gada017fb34e00a15702d759ff174d33ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gada017fb34e00a15702d759ff174d33ff">USB_OTG_HCINTMSK_FRMORM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gac75612d12f30f20d62f93d75bfe2d93a">USB_OTG_HCINTMSK_FRMORM_Pos</a>)</td></tr>
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<tr class="separator:gada017fb34e00a15702d759ff174d33ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2178eb0791f9ea69122edfbd567ba48" id="r_gad2178eb0791f9ea69122edfbd567ba48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2178eb0791f9ea69122edfbd567ba48">USB_OTG_HCINTMSK_FRMORM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gada017fb34e00a15702d759ff174d33ff">USB_OTG_HCINTMSK_FRMORM_Msk</a></td></tr>
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<tr class="separator:gad2178eb0791f9ea69122edfbd567ba48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab10e5fcf2df7005211ca7b39160ee4a3" id="r_gab10e5fcf2df7005211ca7b39160ee4a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab10e5fcf2df7005211ca7b39160ee4a3">USB_OTG_HCINTMSK_DTERRM_Pos</a>   (10U)</td></tr>
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<tr class="separator:gab10e5fcf2df7005211ca7b39160ee4a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1cbd167749a70c575efd955503111f5c" id="r_ga1cbd167749a70c575efd955503111f5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1cbd167749a70c575efd955503111f5c">USB_OTG_HCINTMSK_DTERRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab10e5fcf2df7005211ca7b39160ee4a3">USB_OTG_HCINTMSK_DTERRM_Pos</a>)</td></tr>
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<tr class="separator:ga1cbd167749a70c575efd955503111f5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7ab7105e77ce288988037b1df3406ab3" id="r_ga7ab7105e77ce288988037b1df3406ab3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7ab7105e77ce288988037b1df3406ab3">USB_OTG_HCINTMSK_DTERRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1cbd167749a70c575efd955503111f5c">USB_OTG_HCINTMSK_DTERRM_Msk</a></td></tr>
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<tr class="separator:ga7ab7105e77ce288988037b1df3406ab3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa981fab712cf94125aa509221dc26720" id="r_gaa981fab712cf94125aa509221dc26720"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa981fab712cf94125aa509221dc26720">USB_OTG_DIEPTSIZ_XFRSIZ_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaa981fab712cf94125aa509221dc26720"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b953496e53318844d2444b0d3982d2d" id="r_ga3b953496e53318844d2444b0d3982d2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b953496e53318844d2444b0d3982d2d">USB_OTG_DIEPTSIZ_XFRSIZ_Msk</a>   (0x7FFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa981fab712cf94125aa509221dc26720">USB_OTG_DIEPTSIZ_XFRSIZ_Pos</a>)</td></tr>
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<tr class="separator:ga3b953496e53318844d2444b0d3982d2d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5497667d259391162884390afd456f62" id="r_ga5497667d259391162884390afd456f62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5497667d259391162884390afd456f62">USB_OTG_DIEPTSIZ_XFRSIZ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b953496e53318844d2444b0d3982d2d">USB_OTG_DIEPTSIZ_XFRSIZ_Msk</a></td></tr>
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<tr class="separator:ga5497667d259391162884390afd456f62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga623bbf2a88cfc42a0e43ede442a58eca" id="r_ga623bbf2a88cfc42a0e43ede442a58eca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga623bbf2a88cfc42a0e43ede442a58eca">USB_OTG_DIEPTSIZ_PKTCNT_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga623bbf2a88cfc42a0e43ede442a58eca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4032f4b698ca8efd7417e13471d834e0" id="r_ga4032f4b698ca8efd7417e13471d834e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4032f4b698ca8efd7417e13471d834e0">USB_OTG_DIEPTSIZ_PKTCNT_Msk</a>   (0x3FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga623bbf2a88cfc42a0e43ede442a58eca">USB_OTG_DIEPTSIZ_PKTCNT_Pos</a>)</td></tr>
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<tr class="separator:ga4032f4b698ca8efd7417e13471d834e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga664b39d163f9f2e400aa9fe2577ffc06" id="r_ga664b39d163f9f2e400aa9fe2577ffc06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga664b39d163f9f2e400aa9fe2577ffc06">USB_OTG_DIEPTSIZ_PKTCNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4032f4b698ca8efd7417e13471d834e0">USB_OTG_DIEPTSIZ_PKTCNT_Msk</a></td></tr>
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<tr class="separator:ga664b39d163f9f2e400aa9fe2577ffc06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d027496fed28964c3a0ec36bfe5c03c" id="r_ga1d027496fed28964c3a0ec36bfe5c03c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d027496fed28964c3a0ec36bfe5c03c">USB_OTG_DIEPTSIZ_MULCNT_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga1d027496fed28964c3a0ec36bfe5c03c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5b2138444cba4a94fea9ab112d212e1c" id="r_ga5b2138444cba4a94fea9ab112d212e1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5b2138444cba4a94fea9ab112d212e1c">USB_OTG_DIEPTSIZ_MULCNT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d027496fed28964c3a0ec36bfe5c03c">USB_OTG_DIEPTSIZ_MULCNT_Pos</a>)</td></tr>
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<tr class="separator:ga5b2138444cba4a94fea9ab112d212e1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga428da482bfd499096cff02a3d8aa6738" id="r_ga428da482bfd499096cff02a3d8aa6738"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga428da482bfd499096cff02a3d8aa6738">USB_OTG_DIEPTSIZ_MULCNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga5b2138444cba4a94fea9ab112d212e1c">USB_OTG_DIEPTSIZ_MULCNT_Msk</a></td></tr>
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<tr class="separator:ga428da482bfd499096cff02a3d8aa6738"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4879da0413028804a012612d7459804f" id="r_ga4879da0413028804a012612d7459804f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4879da0413028804a012612d7459804f">USB_OTG_HCTSIZ_XFRSIZ_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga4879da0413028804a012612d7459804f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d0ecc462bdb146edeb44b1e1bf3ae08" id="r_ga3d0ecc462bdb146edeb44b1e1bf3ae08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3d0ecc462bdb146edeb44b1e1bf3ae08">USB_OTG_HCTSIZ_XFRSIZ_Msk</a>   (0x7FFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga4879da0413028804a012612d7459804f">USB_OTG_HCTSIZ_XFRSIZ_Pos</a>)</td></tr>
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<tr class="separator:ga3d0ecc462bdb146edeb44b1e1bf3ae08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga983ec8ca0ffac66eea9219acb008fe9c" id="r_ga983ec8ca0ffac66eea9219acb008fe9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga983ec8ca0ffac66eea9219acb008fe9c">USB_OTG_HCTSIZ_XFRSIZ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga3d0ecc462bdb146edeb44b1e1bf3ae08">USB_OTG_HCTSIZ_XFRSIZ_Msk</a></td></tr>
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<tr class="separator:ga983ec8ca0ffac66eea9219acb008fe9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga386ed2405e9608d8846b344d4061eff0" id="r_ga386ed2405e9608d8846b344d4061eff0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga386ed2405e9608d8846b344d4061eff0">USB_OTG_HCTSIZ_PKTCNT_Pos</a>   (19U)</td></tr>
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<tr class="separator:ga386ed2405e9608d8846b344d4061eff0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae242d5b51bdad2968cc7f59f2356195b" id="r_gae242d5b51bdad2968cc7f59f2356195b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae242d5b51bdad2968cc7f59f2356195b">USB_OTG_HCTSIZ_PKTCNT_Msk</a>   (0x3FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga386ed2405e9608d8846b344d4061eff0">USB_OTG_HCTSIZ_PKTCNT_Pos</a>)</td></tr>
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<tr class="separator:gae242d5b51bdad2968cc7f59f2356195b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2177151366a5539b446104cb87d3059" id="r_gab2177151366a5539b446104cb87d3059"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2177151366a5539b446104cb87d3059">USB_OTG_HCTSIZ_PKTCNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gae242d5b51bdad2968cc7f59f2356195b">USB_OTG_HCTSIZ_PKTCNT_Msk</a></td></tr>
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<tr class="separator:gab2177151366a5539b446104cb87d3059"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaabd15ce174827e22c8ebd38fd41d4dcd" id="r_gaabd15ce174827e22c8ebd38fd41d4dcd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaabd15ce174827e22c8ebd38fd41d4dcd">USB_OTG_HCTSIZ_DOPING_Pos</a>   (31U)</td></tr>
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<tr class="separator:gaabd15ce174827e22c8ebd38fd41d4dcd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga63444676f787b5850bcd74a3dac24c06" id="r_ga63444676f787b5850bcd74a3dac24c06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga63444676f787b5850bcd74a3dac24c06">USB_OTG_HCTSIZ_DOPING_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaabd15ce174827e22c8ebd38fd41d4dcd">USB_OTG_HCTSIZ_DOPING_Pos</a>)</td></tr>
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<tr class="separator:ga63444676f787b5850bcd74a3dac24c06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2dcc4677244eb50d430a62870b90c30c" id="r_ga2dcc4677244eb50d430a62870b90c30c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2dcc4677244eb50d430a62870b90c30c">USB_OTG_HCTSIZ_DOPING</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga63444676f787b5850bcd74a3dac24c06">USB_OTG_HCTSIZ_DOPING_Msk</a></td></tr>
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<tr class="separator:ga2dcc4677244eb50d430a62870b90c30c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga015e511e5d6f38252ca6006e8b984bb7" id="r_ga015e511e5d6f38252ca6006e8b984bb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga015e511e5d6f38252ca6006e8b984bb7">USB_OTG_HCTSIZ_DPID_Pos</a>   (29U)</td></tr>
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<tr class="separator:ga015e511e5d6f38252ca6006e8b984bb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga66d5133c860991521246501b6e1c055d" id="r_ga66d5133c860991521246501b6e1c055d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga66d5133c860991521246501b6e1c055d">USB_OTG_HCTSIZ_DPID_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga015e511e5d6f38252ca6006e8b984bb7">USB_OTG_HCTSIZ_DPID_Pos</a>)</td></tr>
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<tr class="separator:ga66d5133c860991521246501b6e1c055d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7037fb804f6e2a4a3e0c08bd3e345f18" id="r_ga7037fb804f6e2a4a3e0c08bd3e345f18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7037fb804f6e2a4a3e0c08bd3e345f18">USB_OTG_HCTSIZ_DPID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga66d5133c860991521246501b6e1c055d">USB_OTG_HCTSIZ_DPID_Msk</a></td></tr>
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<tr class="separator:ga7037fb804f6e2a4a3e0c08bd3e345f18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae5509a0f869a4c7ba34f45be4b733b23" id="r_gae5509a0f869a4c7ba34f45be4b733b23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae5509a0f869a4c7ba34f45be4b733b23">USB_OTG_HCTSIZ_DPID_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga015e511e5d6f38252ca6006e8b984bb7">USB_OTG_HCTSIZ_DPID_Pos</a>)</td></tr>
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<tr class="separator:gae5509a0f869a4c7ba34f45be4b733b23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5ae95b441c770521507da1d1d4c51d18" id="r_ga5ae95b441c770521507da1d1d4c51d18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5ae95b441c770521507da1d1d4c51d18">USB_OTG_HCTSIZ_DPID_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga015e511e5d6f38252ca6006e8b984bb7">USB_OTG_HCTSIZ_DPID_Pos</a>)</td></tr>
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<tr class="separator:ga5ae95b441c770521507da1d1d4c51d18"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f8a6b9128f9e824a0ae68346fb8fe73" id="r_ga2f8a6b9128f9e824a0ae68346fb8fe73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2f8a6b9128f9e824a0ae68346fb8fe73">USB_OTG_DIEPDMA_DMAADDR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga2f8a6b9128f9e824a0ae68346fb8fe73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17d3f62d2f03495bb28e7b65f00dbafa" id="r_ga17d3f62d2f03495bb28e7b65f00dbafa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga17d3f62d2f03495bb28e7b65f00dbafa">USB_OTG_DIEPDMA_DMAADDR_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga2f8a6b9128f9e824a0ae68346fb8fe73">USB_OTG_DIEPDMA_DMAADDR_Pos</a>)</td></tr>
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<tr class="separator:ga17d3f62d2f03495bb28e7b65f00dbafa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab177fc20463978ff09c399cb56e904bb" id="r_gab177fc20463978ff09c399cb56e904bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab177fc20463978ff09c399cb56e904bb">USB_OTG_DIEPDMA_DMAADDR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga17d3f62d2f03495bb28e7b65f00dbafa">USB_OTG_DIEPDMA_DMAADDR_Msk</a></td></tr>
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<tr class="separator:gab177fc20463978ff09c399cb56e904bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3c69fd9913335fdca15a7dc32d1193cc" id="r_ga3c69fd9913335fdca15a7dc32d1193cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3c69fd9913335fdca15a7dc32d1193cc">USB_OTG_HCDMA_DMAADDR_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga3c69fd9913335fdca15a7dc32d1193cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a98df839cd4108ef0b1b814d0f7020b" id="r_ga2a98df839cd4108ef0b1b814d0f7020b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a98df839cd4108ef0b1b814d0f7020b">USB_OTG_HCDMA_DMAADDR_Msk</a>   (0xFFFFFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3c69fd9913335fdca15a7dc32d1193cc">USB_OTG_HCDMA_DMAADDR_Pos</a>)</td></tr>
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<tr class="separator:ga2a98df839cd4108ef0b1b814d0f7020b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2980c7f7c60bf5ff4842dc9e363ea7b" id="r_gab2980c7f7c60bf5ff4842dc9e363ea7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab2980c7f7c60bf5ff4842dc9e363ea7b">USB_OTG_HCDMA_DMAADDR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a98df839cd4108ef0b1b814d0f7020b">USB_OTG_HCDMA_DMAADDR_Msk</a></td></tr>
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<tr class="separator:gab2980c7f7c60bf5ff4842dc9e363ea7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7bd1cf28f02f4bd52c71afee6f718e27" id="r_ga7bd1cf28f02f4bd52c71afee6f718e27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7bd1cf28f02f4bd52c71afee6f718e27">USB_OTG_DTXFSTS_INEPTFSAV_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7bd1cf28f02f4bd52c71afee6f718e27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9c1a0115d517ac979a61c81763f4ce8f" id="r_ga9c1a0115d517ac979a61c81763f4ce8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9c1a0115d517ac979a61c81763f4ce8f">USB_OTG_DTXFSTS_INEPTFSAV_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7bd1cf28f02f4bd52c71afee6f718e27">USB_OTG_DTXFSTS_INEPTFSAV_Pos</a>)</td></tr>
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<tr class="separator:ga9c1a0115d517ac979a61c81763f4ce8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae1789e8c79b7a271a58f56cbff4bd03a" id="r_gae1789e8c79b7a271a58f56cbff4bd03a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae1789e8c79b7a271a58f56cbff4bd03a">USB_OTG_DTXFSTS_INEPTFSAV</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga9c1a0115d517ac979a61c81763f4ce8f">USB_OTG_DTXFSTS_INEPTFSAV_Msk</a></td></tr>
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<tr class="separator:gae1789e8c79b7a271a58f56cbff4bd03a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga129f8f89a1a613ce6f86fdb826238e16" id="r_ga129f8f89a1a613ce6f86fdb826238e16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga129f8f89a1a613ce6f86fdb826238e16">USB_OTG_DIEPTXF_INEPTXSA_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga129f8f89a1a613ce6f86fdb826238e16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5b86ac57a1176451f435dda801dbddb" id="r_gac5b86ac57a1176451f435dda801dbddb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac5b86ac57a1176451f435dda801dbddb">USB_OTG_DIEPTXF_INEPTXSA_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga129f8f89a1a613ce6f86fdb826238e16">USB_OTG_DIEPTXF_INEPTXSA_Pos</a>)</td></tr>
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<tr class="separator:gac5b86ac57a1176451f435dda801dbddb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga731c1eaaf15ec1b7f24e055172f7e0cf" id="r_ga731c1eaaf15ec1b7f24e055172f7e0cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga731c1eaaf15ec1b7f24e055172f7e0cf">USB_OTG_DIEPTXF_INEPTXSA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac5b86ac57a1176451f435dda801dbddb">USB_OTG_DIEPTXF_INEPTXSA_Msk</a></td></tr>
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<tr class="separator:ga731c1eaaf15ec1b7f24e055172f7e0cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8c94d7d7bd4526bc8cef42790a10af14" id="r_ga8c94d7d7bd4526bc8cef42790a10af14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8c94d7d7bd4526bc8cef42790a10af14">USB_OTG_DIEPTXF_INEPTXFD_Pos</a>   (16U)</td></tr>
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<tr class="separator:ga8c94d7d7bd4526bc8cef42790a10af14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafccb927bfa114a368eea25db7d46c85f" id="r_gafccb927bfa114a368eea25db7d46c85f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafccb927bfa114a368eea25db7d46c85f">USB_OTG_DIEPTXF_INEPTXFD_Msk</a>   (0xFFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8c94d7d7bd4526bc8cef42790a10af14">USB_OTG_DIEPTXF_INEPTXFD_Pos</a>)</td></tr>
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<tr class="separator:gafccb927bfa114a368eea25db7d46c85f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga015ec5caee27272afa335fa9d5892a40" id="r_ga015ec5caee27272afa335fa9d5892a40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga015ec5caee27272afa335fa9d5892a40">USB_OTG_DIEPTXF_INEPTXFD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gafccb927bfa114a368eea25db7d46c85f">USB_OTG_DIEPTXF_INEPTXFD_Msk</a></td></tr>
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<tr class="separator:ga015ec5caee27272afa335fa9d5892a40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef51a2cbd7e13a734ffdfded5b1e772d" id="r_gaef51a2cbd7e13a734ffdfded5b1e772d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaef51a2cbd7e13a734ffdfded5b1e772d">USB_OTG_DOEPCTL_MPSIZ_Pos</a>   (0U)</td></tr>
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<tr class="separator:gaef51a2cbd7e13a734ffdfded5b1e772d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga103ef4c7123cb64007a1eb050d96c4b7" id="r_ga103ef4c7123cb64007a1eb050d96c4b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga103ef4c7123cb64007a1eb050d96c4b7">USB_OTG_DOEPCTL_MPSIZ_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaef51a2cbd7e13a734ffdfded5b1e772d">USB_OTG_DOEPCTL_MPSIZ_Pos</a>)</td></tr>
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<tr class="separator:ga103ef4c7123cb64007a1eb050d96c4b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ebce086e91feb566f223ae07d01ff57" id="r_ga0ebce086e91feb566f223ae07d01ff57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0ebce086e91feb566f223ae07d01ff57">USB_OTG_DOEPCTL_MPSIZ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga103ef4c7123cb64007a1eb050d96c4b7">USB_OTG_DOEPCTL_MPSIZ_Msk</a> /*!< Maximum packet size */</td></tr>
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<tr class="separator:ga0ebce086e91feb566f223ae07d01ff57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf003bdf82be8bff3e23452c7a83a9ed2" id="r_gaf003bdf82be8bff3e23452c7a83a9ed2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf003bdf82be8bff3e23452c7a83a9ed2">USB_OTG_DOEPCTL_USBAEP_Pos</a>   (15U)</td></tr>
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<tr class="separator:gaf003bdf82be8bff3e23452c7a83a9ed2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga31ba8e0d0b5bf08b034ba5cf27eaef4c" id="r_ga31ba8e0d0b5bf08b034ba5cf27eaef4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga31ba8e0d0b5bf08b034ba5cf27eaef4c">USB_OTG_DOEPCTL_USBAEP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaf003bdf82be8bff3e23452c7a83a9ed2">USB_OTG_DOEPCTL_USBAEP_Pos</a>)</td></tr>
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<tr class="separator:ga31ba8e0d0b5bf08b034ba5cf27eaef4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabed242624f140356cc793039988d89df" id="r_gabed242624f140356cc793039988d89df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabed242624f140356cc793039988d89df">USB_OTG_DOEPCTL_USBAEP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga31ba8e0d0b5bf08b034ba5cf27eaef4c">USB_OTG_DOEPCTL_USBAEP_Msk</a></td></tr>
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<tr class="separator:gabed242624f140356cc793039988d89df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab721aee46a6d9aaabb0c1449155777c9" id="r_gab721aee46a6d9aaabb0c1449155777c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab721aee46a6d9aaabb0c1449155777c9">USB_OTG_DOEPCTL_NAKSTS_Pos</a>   (17U)</td></tr>
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<tr class="separator:gab721aee46a6d9aaabb0c1449155777c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacca51b95d03a684417745d2870bc02aa" id="r_gacca51b95d03a684417745d2870bc02aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gacca51b95d03a684417745d2870bc02aa">USB_OTG_DOEPCTL_NAKSTS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab721aee46a6d9aaabb0c1449155777c9">USB_OTG_DOEPCTL_NAKSTS_Pos</a>)</td></tr>
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<tr class="separator:gacca51b95d03a684417745d2870bc02aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa1735002d3abf233ca0cbe473da2d8fb" id="r_gaa1735002d3abf233ca0cbe473da2d8fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa1735002d3abf233ca0cbe473da2d8fb">USB_OTG_DOEPCTL_NAKSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gacca51b95d03a684417745d2870bc02aa">USB_OTG_DOEPCTL_NAKSTS_Msk</a></td></tr>
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<tr class="separator:gaa1735002d3abf233ca0cbe473da2d8fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0a8dc23aee4dc031e4f2e85b8a09dbb" id="r_gae0a8dc23aee4dc031e4f2e85b8a09dbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae0a8dc23aee4dc031e4f2e85b8a09dbb">USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos</a>   (28U)</td></tr>
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<tr class="separator:gae0a8dc23aee4dc031e4f2e85b8a09dbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac1b8b770cb957bf0f4148311ddfef503" id="r_gac1b8b770cb957bf0f4148311ddfef503"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac1b8b770cb957bf0f4148311ddfef503">USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gae0a8dc23aee4dc031e4f2e85b8a09dbb">USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos</a>)</td></tr>
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<tr class="separator:gac1b8b770cb957bf0f4148311ddfef503"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0a06b55e9caa25873e734fb15cafbc51" id="r_ga0a06b55e9caa25873e734fb15cafbc51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0a06b55e9caa25873e734fb15cafbc51">USB_OTG_DOEPCTL_SD0PID_SEVNFRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac1b8b770cb957bf0f4148311ddfef503">USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk</a></td></tr>
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<tr class="separator:ga0a06b55e9caa25873e734fb15cafbc51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab617807c602f3dd930adca64b0c5fed1" id="r_gab617807c602f3dd930adca64b0c5fed1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab617807c602f3dd930adca64b0c5fed1">USB_OTG_DOEPCTL_SODDFRM_Pos</a>   (29U)</td></tr>
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<tr class="separator:gab617807c602f3dd930adca64b0c5fed1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4f4b73b3f5f6813412b392b8b619a1ae" id="r_ga4f4b73b3f5f6813412b392b8b619a1ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4f4b73b3f5f6813412b392b8b619a1ae">USB_OTG_DOEPCTL_SODDFRM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gab617807c602f3dd930adca64b0c5fed1">USB_OTG_DOEPCTL_SODDFRM_Pos</a>)</td></tr>
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<tr class="separator:ga4f4b73b3f5f6813412b392b8b619a1ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77ddb336230fa5a497dbb2393a180ae6" id="r_ga77ddb336230fa5a497dbb2393a180ae6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77ddb336230fa5a497dbb2393a180ae6">USB_OTG_DOEPCTL_SODDFRM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga4f4b73b3f5f6813412b392b8b619a1ae">USB_OTG_DOEPCTL_SODDFRM_Msk</a></td></tr>
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<tr class="separator:ga77ddb336230fa5a497dbb2393a180ae6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3dd2ea9b1c00daf741f7ac74f32bebc3" id="r_ga3dd2ea9b1c00daf741f7ac74f32bebc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3dd2ea9b1c00daf741f7ac74f32bebc3">USB_OTG_DOEPCTL_EPTYP_Pos</a>   (18U)</td></tr>
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<tr class="separator:ga3dd2ea9b1c00daf741f7ac74f32bebc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5fea8cfdb01a643000019dc830fc30f" id="r_gab5fea8cfdb01a643000019dc830fc30f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab5fea8cfdb01a643000019dc830fc30f">USB_OTG_DOEPCTL_EPTYP_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3dd2ea9b1c00daf741f7ac74f32bebc3">USB_OTG_DOEPCTL_EPTYP_Pos</a>)</td></tr>
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<tr class="memitem:ga4e347921b96b8435ec2ef6cc9b3470d8" id="r_ga4e347921b96b8435ec2ef6cc9b3470d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4e347921b96b8435ec2ef6cc9b3470d8">USB_OTG_DOEPCTL_EPTYP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab5fea8cfdb01a643000019dc830fc30f">USB_OTG_DOEPCTL_EPTYP_Msk</a></td></tr>
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<tr class="separator:ga4e347921b96b8435ec2ef6cc9b3470d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga48b0660b499862424b72cd59bca9226e" id="r_ga48b0660b499862424b72cd59bca9226e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga48b0660b499862424b72cd59bca9226e">USB_OTG_DOEPCTL_EPTYP_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3dd2ea9b1c00daf741f7ac74f32bebc3">USB_OTG_DOEPCTL_EPTYP_Pos</a>)</td></tr>
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<tr class="separator:ga48b0660b499862424b72cd59bca9226e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga89595201dd98cc05712d046e98c142fd" id="r_ga89595201dd98cc05712d046e98c142fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga89595201dd98cc05712d046e98c142fd">USB_OTG_DOEPCTL_EPTYP_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3dd2ea9b1c00daf741f7ac74f32bebc3">USB_OTG_DOEPCTL_EPTYP_Pos</a>)</td></tr>
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<tr class="separator:ga89595201dd98cc05712d046e98c142fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed30bbeec479174dbaeb4ec6342e7acc" id="r_gaed30bbeec479174dbaeb4ec6342e7acc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaed30bbeec479174dbaeb4ec6342e7acc">USB_OTG_DOEPCTL_SNPM_Pos</a>   (20U)</td></tr>
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<tr class="separator:gaed30bbeec479174dbaeb4ec6342e7acc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga592d0d387403b49dd841153e1c8ef922" id="r_ga592d0d387403b49dd841153e1c8ef922"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga592d0d387403b49dd841153e1c8ef922">USB_OTG_DOEPCTL_SNPM_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaed30bbeec479174dbaeb4ec6342e7acc">USB_OTG_DOEPCTL_SNPM_Pos</a>)</td></tr>
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<tr class="separator:ga592d0d387403b49dd841153e1c8ef922"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14ef1fba78e67a55f665495ae7f8732e" id="r_ga14ef1fba78e67a55f665495ae7f8732e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga14ef1fba78e67a55f665495ae7f8732e">USB_OTG_DOEPCTL_SNPM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga592d0d387403b49dd841153e1c8ef922">USB_OTG_DOEPCTL_SNPM_Msk</a></td></tr>
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<tr class="separator:ga14ef1fba78e67a55f665495ae7f8732e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga713faf56d7526c1671e9920f96207902" id="r_ga713faf56d7526c1671e9920f96207902"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga713faf56d7526c1671e9920f96207902">USB_OTG_DOEPCTL_STALL_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga713faf56d7526c1671e9920f96207902"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga600dc33e80274fdf8ec793bce5df9ad4" id="r_ga600dc33e80274fdf8ec793bce5df9ad4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga600dc33e80274fdf8ec793bce5df9ad4">USB_OTG_DOEPCTL_STALL_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga713faf56d7526c1671e9920f96207902">USB_OTG_DOEPCTL_STALL_Pos</a>)</td></tr>
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<tr class="separator:ga600dc33e80274fdf8ec793bce5df9ad4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e6aea29335780171f8ce42aba031699" id="r_ga5e6aea29335780171f8ce42aba031699"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e6aea29335780171f8ce42aba031699">USB_OTG_DOEPCTL_STALL</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga600dc33e80274fdf8ec793bce5df9ad4">USB_OTG_DOEPCTL_STALL_Msk</a></td></tr>
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<tr class="separator:ga5e6aea29335780171f8ce42aba031699"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ce77ba5437dc8c547c7fe2b2851af15" id="r_ga8ce77ba5437dc8c547c7fe2b2851af15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ce77ba5437dc8c547c7fe2b2851af15">USB_OTG_DOEPCTL_CNAK_Pos</a>   (26U)</td></tr>
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<tr class="separator:ga8ce77ba5437dc8c547c7fe2b2851af15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92c45d7d3e789caf1b5a8967592939ae" id="r_ga92c45d7d3e789caf1b5a8967592939ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92c45d7d3e789caf1b5a8967592939ae">USB_OTG_DOEPCTL_CNAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ce77ba5437dc8c547c7fe2b2851af15">USB_OTG_DOEPCTL_CNAK_Pos</a>)</td></tr>
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<tr class="separator:ga92c45d7d3e789caf1b5a8967592939ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd05c0aa7833e7467e0ff66cfa1f20cb" id="r_gabd05c0aa7833e7467e0ff66cfa1f20cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd05c0aa7833e7467e0ff66cfa1f20cb">USB_OTG_DOEPCTL_CNAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga92c45d7d3e789caf1b5a8967592939ae">USB_OTG_DOEPCTL_CNAK_Msk</a></td></tr>
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<tr class="separator:gabd05c0aa7833e7467e0ff66cfa1f20cb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3f8d51a7d585bca9ab215fd90fcba33" id="r_gaa3f8d51a7d585bca9ab215fd90fcba33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3f8d51a7d585bca9ab215fd90fcba33">USB_OTG_DOEPCTL_SNAK_Pos</a>   (27U)</td></tr>
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<tr class="separator:gaa3f8d51a7d585bca9ab215fd90fcba33"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6be0f6d6ed75219981fc07465ba09298" id="r_ga6be0f6d6ed75219981fc07465ba09298"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6be0f6d6ed75219981fc07465ba09298">USB_OTG_DOEPCTL_SNAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3f8d51a7d585bca9ab215fd90fcba33">USB_OTG_DOEPCTL_SNAK_Pos</a>)</td></tr>
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<tr class="separator:ga6be0f6d6ed75219981fc07465ba09298"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05a3e120b2c56a13ff622b0a507f48ee" id="r_ga05a3e120b2c56a13ff622b0a507f48ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05a3e120b2c56a13ff622b0a507f48ee">USB_OTG_DOEPCTL_SNAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga6be0f6d6ed75219981fc07465ba09298">USB_OTG_DOEPCTL_SNAK_Msk</a></td></tr>
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<tr class="separator:ga05a3e120b2c56a13ff622b0a507f48ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06d18faa6f215148241b0aa16a2708dc" id="r_ga06d18faa6f215148241b0aa16a2708dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga06d18faa6f215148241b0aa16a2708dc">USB_OTG_DOEPCTL_EPDIS_Pos</a>   (30U)</td></tr>
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<tr class="separator:ga06d18faa6f215148241b0aa16a2708dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46881c1a50c0a2b48f4d107a9cdc540f" id="r_ga46881c1a50c0a2b48f4d107a9cdc540f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46881c1a50c0a2b48f4d107a9cdc540f">USB_OTG_DOEPCTL_EPDIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga06d18faa6f215148241b0aa16a2708dc">USB_OTG_DOEPCTL_EPDIS_Pos</a>)</td></tr>
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<tr class="separator:ga46881c1a50c0a2b48f4d107a9cdc540f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf170f97217b0a2e3f66a33a67257674e" id="r_gaf170f97217b0a2e3f66a33a67257674e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf170f97217b0a2e3f66a33a67257674e">USB_OTG_DOEPCTL_EPDIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga46881c1a50c0a2b48f4d107a9cdc540f">USB_OTG_DOEPCTL_EPDIS_Msk</a></td></tr>
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<tr class="separator:gaf170f97217b0a2e3f66a33a67257674e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga67d45681d84c4e5a4a1050291a2f1c4c" id="r_ga67d45681d84c4e5a4a1050291a2f1c4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga67d45681d84c4e5a4a1050291a2f1c4c">USB_OTG_DOEPCTL_EPENA_Pos</a>   (31U)</td></tr>
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<tr class="separator:ga67d45681d84c4e5a4a1050291a2f1c4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga891f80e6cdbf19579db62d0214bc09b5" id="r_ga891f80e6cdbf19579db62d0214bc09b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga891f80e6cdbf19579db62d0214bc09b5">USB_OTG_DOEPCTL_EPENA_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga67d45681d84c4e5a4a1050291a2f1c4c">USB_OTG_DOEPCTL_EPENA_Pos</a>)</td></tr>
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<tr class="separator:ga891f80e6cdbf19579db62d0214bc09b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8875f7311dfde66125b78dd715fd2d7c" id="r_ga8875f7311dfde66125b78dd715fd2d7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8875f7311dfde66125b78dd715fd2d7c">USB_OTG_DOEPCTL_EPENA</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga891f80e6cdbf19579db62d0214bc09b5">USB_OTG_DOEPCTL_EPENA_Msk</a></td></tr>
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<tr class="separator:ga8875f7311dfde66125b78dd715fd2d7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga22c42c63b15338fb0f80bc252ab8a1f9" id="r_ga22c42c63b15338fb0f80bc252ab8a1f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga22c42c63b15338fb0f80bc252ab8a1f9">USB_OTG_DOEPINT_XFRC_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga22c42c63b15338fb0f80bc252ab8a1f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71bec204f2c5886251295d5ea7739331" id="r_ga71bec204f2c5886251295d5ea7739331"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga71bec204f2c5886251295d5ea7739331">USB_OTG_DOEPINT_XFRC_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga22c42c63b15338fb0f80bc252ab8a1f9">USB_OTG_DOEPINT_XFRC_Pos</a>)</td></tr>
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<tr class="separator:ga71bec204f2c5886251295d5ea7739331"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e51a7b1cc412e304246176c207cbcb8" id="r_ga0e51a7b1cc412e304246176c207cbcb8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e51a7b1cc412e304246176c207cbcb8">USB_OTG_DOEPINT_XFRC</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga71bec204f2c5886251295d5ea7739331">USB_OTG_DOEPINT_XFRC_Msk</a></td></tr>
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<tr class="separator:ga0e51a7b1cc412e304246176c207cbcb8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd8ea7d7381b81fc6ace42213c39c909" id="r_gabd8ea7d7381b81fc6ace42213c39c909"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabd8ea7d7381b81fc6ace42213c39c909">USB_OTG_DOEPINT_EPDISD_Pos</a>   (1U)</td></tr>
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<tr class="separator:gabd8ea7d7381b81fc6ace42213c39c909"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad2bee78f4eead58dd6e9d772d77c843d" id="r_gad2bee78f4eead58dd6e9d772d77c843d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad2bee78f4eead58dd6e9d772d77c843d">USB_OTG_DOEPINT_EPDISD_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gabd8ea7d7381b81fc6ace42213c39c909">USB_OTG_DOEPINT_EPDISD_Pos</a>)</td></tr>
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<tr class="separator:gad2bee78f4eead58dd6e9d772d77c843d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga32e18140ad2c7902fe788947cea557d2" id="r_ga32e18140ad2c7902fe788947cea557d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga32e18140ad2c7902fe788947cea557d2">USB_OTG_DOEPINT_EPDISD</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gad2bee78f4eead58dd6e9d772d77c843d">USB_OTG_DOEPINT_EPDISD_Msk</a></td></tr>
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<tr class="separator:ga32e18140ad2c7902fe788947cea557d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e071c9b55a563d90d1ab1c0577390a4" id="r_ga0e071c9b55a563d90d1ab1c0577390a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e071c9b55a563d90d1ab1c0577390a4">USB_OTG_DOEPINT_AHBERR_Pos</a>   (2U)</td></tr>
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<tr class="separator:ga0e071c9b55a563d90d1ab1c0577390a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7dfe74336fa143f3b5a536a74ff77dcb" id="r_ga7dfe74336fa143f3b5a536a74ff77dcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7dfe74336fa143f3b5a536a74ff77dcb">USB_OTG_DOEPINT_AHBERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0e071c9b55a563d90d1ab1c0577390a4">USB_OTG_DOEPINT_AHBERR_Pos</a>)</td></tr>
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<tr class="separator:ga7dfe74336fa143f3b5a536a74ff77dcb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8957520b45ebd1ed0000d8a0c0cc9ef6" id="r_ga8957520b45ebd1ed0000d8a0c0cc9ef6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8957520b45ebd1ed0000d8a0c0cc9ef6">USB_OTG_DOEPINT_AHBERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7dfe74336fa143f3b5a536a74ff77dcb">USB_OTG_DOEPINT_AHBERR_Msk</a></td></tr>
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<tr class="separator:ga8957520b45ebd1ed0000d8a0c0cc9ef6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga74a9a1fec27e8dd4a5a603a0d63fc104" id="r_ga74a9a1fec27e8dd4a5a603a0d63fc104"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga74a9a1fec27e8dd4a5a603a0d63fc104">USB_OTG_DOEPINT_STUP_Pos</a>   (3U)</td></tr>
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<tr class="separator:ga74a9a1fec27e8dd4a5a603a0d63fc104"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42dda03dc0034c884c0a51c1f749edfb" id="r_ga42dda03dc0034c884c0a51c1f749edfb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42dda03dc0034c884c0a51c1f749edfb">USB_OTG_DOEPINT_STUP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga74a9a1fec27e8dd4a5a603a0d63fc104">USB_OTG_DOEPINT_STUP_Pos</a>)</td></tr>
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<tr class="separator:ga42dda03dc0034c884c0a51c1f749edfb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga76444bdecd4d6def6c718ed1bb8e8b8c" id="r_ga76444bdecd4d6def6c718ed1bb8e8b8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga76444bdecd4d6def6c718ed1bb8e8b8c">USB_OTG_DOEPINT_STUP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga42dda03dc0034c884c0a51c1f749edfb">USB_OTG_DOEPINT_STUP_Msk</a></td></tr>
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<tr class="separator:ga76444bdecd4d6def6c718ed1bb8e8b8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa3e353ea229f93246f7fb4ef0efc90a9" id="r_gaa3e353ea229f93246f7fb4ef0efc90a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa3e353ea229f93246f7fb4ef0efc90a9">USB_OTG_DOEPINT_OTEPDIS_Pos</a>   (4U)</td></tr>
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<tr class="separator:gaa3e353ea229f93246f7fb4ef0efc90a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab8a3dd1c173d5cd66abf1d5aff97f894" id="r_gab8a3dd1c173d5cd66abf1d5aff97f894"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab8a3dd1c173d5cd66abf1d5aff97f894">USB_OTG_DOEPINT_OTEPDIS_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaa3e353ea229f93246f7fb4ef0efc90a9">USB_OTG_DOEPINT_OTEPDIS_Pos</a>)</td></tr>
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<tr class="separator:gab8a3dd1c173d5cd66abf1d5aff97f894"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f4c92b08606cf934de16b353053dd78" id="r_ga3f4c92b08606cf934de16b353053dd78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3f4c92b08606cf934de16b353053dd78">USB_OTG_DOEPINT_OTEPDIS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab8a3dd1c173d5cd66abf1d5aff97f894">USB_OTG_DOEPINT_OTEPDIS_Msk</a></td></tr>
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<tr class="separator:ga3f4c92b08606cf934de16b353053dd78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cd4ee8b333b45244a950aec7b6d1756" id="r_ga0cd4ee8b333b45244a950aec7b6d1756"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cd4ee8b333b45244a950aec7b6d1756">USB_OTG_DOEPINT_OTEPSPR_Pos</a>   (5U)</td></tr>
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<tr class="separator:ga0cd4ee8b333b45244a950aec7b6d1756"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c064a7156878cca72817277cce28cef" id="r_ga0c064a7156878cca72817277cce28cef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0c064a7156878cca72817277cce28cef">USB_OTG_DOEPINT_OTEPSPR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0cd4ee8b333b45244a950aec7b6d1756">USB_OTG_DOEPINT_OTEPSPR_Pos</a>)</td></tr>
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<tr class="separator:ga0c064a7156878cca72817277cce28cef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2451732dfee15831f09e28041dabf9ce" id="r_ga2451732dfee15831f09e28041dabf9ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2451732dfee15831f09e28041dabf9ce">USB_OTG_DOEPINT_OTEPSPR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga0c064a7156878cca72817277cce28cef">USB_OTG_DOEPINT_OTEPSPR_Msk</a></td></tr>
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<tr class="separator:ga2451732dfee15831f09e28041dabf9ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb2f0d32861f239d7cf694ce1f34d019" id="r_gafb2f0d32861f239d7cf694ce1f34d019"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafb2f0d32861f239d7cf694ce1f34d019">USB_OTG_DOEPINT_B2BSTUP_Pos</a>   (6U)</td></tr>
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<tr class="separator:gafb2f0d32861f239d7cf694ce1f34d019"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab7623d1db984217c12acc54117994337" id="r_gab7623d1db984217c12acc54117994337"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab7623d1db984217c12acc54117994337">USB_OTG_DOEPINT_B2BSTUP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gafb2f0d32861f239d7cf694ce1f34d019">USB_OTG_DOEPINT_B2BSTUP_Pos</a>)</td></tr>
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<tr class="separator:gab7623d1db984217c12acc54117994337"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82261faaf818baade125d4de42f78fa5" id="r_ga82261faaf818baade125d4de42f78fa5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga82261faaf818baade125d4de42f78fa5">USB_OTG_DOEPINT_B2BSTUP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab7623d1db984217c12acc54117994337">USB_OTG_DOEPINT_B2BSTUP_Msk</a></td></tr>
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<tr class="separator:ga82261faaf818baade125d4de42f78fa5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga92efd02af8d099a47efd3e038bada011" id="r_ga92efd02af8d099a47efd3e038bada011"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga92efd02af8d099a47efd3e038bada011">USB_OTG_DOEPINT_OUTPKTERR_Pos</a>   (8U)</td></tr>
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<tr class="separator:ga92efd02af8d099a47efd3e038bada011"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f5870176a1b59ee2048b23087b677ae" id="r_ga7f5870176a1b59ee2048b23087b677ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7f5870176a1b59ee2048b23087b677ae">USB_OTG_DOEPINT_OUTPKTERR_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga92efd02af8d099a47efd3e038bada011">USB_OTG_DOEPINT_OUTPKTERR_Pos</a>)</td></tr>
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<tr class="separator:ga7f5870176a1b59ee2048b23087b677ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadf82df64a03b0a9f6915a36a750488ac" id="r_gadf82df64a03b0a9f6915a36a750488ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadf82df64a03b0a9f6915a36a750488ac">USB_OTG_DOEPINT_OUTPKTERR</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga7f5870176a1b59ee2048b23087b677ae">USB_OTG_DOEPINT_OUTPKTERR_Msk</a></td></tr>
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<tr class="separator:gadf82df64a03b0a9f6915a36a750488ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b77b085273952d4999950d52cd674c7" id="r_ga3b77b085273952d4999950d52cd674c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b77b085273952d4999950d52cd674c7">USB_OTG_DOEPINT_NAK_Pos</a>   (13U)</td></tr>
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<tr class="separator:ga3b77b085273952d4999950d52cd674c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaaa6114d1a7f5860c94bc9eb1ef1207c" id="r_gaaaa6114d1a7f5860c94bc9eb1ef1207c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaaa6114d1a7f5860c94bc9eb1ef1207c">USB_OTG_DOEPINT_NAK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga3b77b085273952d4999950d52cd674c7">USB_OTG_DOEPINT_NAK_Pos</a>)</td></tr>
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<tr class="separator:gaaaa6114d1a7f5860c94bc9eb1ef1207c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d1b7add4ca4362bb47501b456d3bb8b" id="r_ga1d1b7add4ca4362bb47501b456d3bb8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d1b7add4ca4362bb47501b456d3bb8b">USB_OTG_DOEPINT_NAK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaaaa6114d1a7f5860c94bc9eb1ef1207c">USB_OTG_DOEPINT_NAK_Msk</a></td></tr>
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<tr class="separator:ga1d1b7add4ca4362bb47501b456d3bb8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3e46923e595b9049270b43fece30784" id="r_gad3e46923e595b9049270b43fece30784"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad3e46923e595b9049270b43fece30784">USB_OTG_DOEPINT_NYET_Pos</a>   (14U)</td></tr>
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<tr class="separator:gad3e46923e595b9049270b43fece30784"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8ea8387720c1dd29d7c4689f4b83792f" id="r_ga8ea8387720c1dd29d7c4689f4b83792f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8ea8387720c1dd29d7c4689f4b83792f">USB_OTG_DOEPINT_NYET_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad3e46923e595b9049270b43fece30784">USB_OTG_DOEPINT_NYET_Pos</a>)</td></tr>
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<tr class="separator:ga8ea8387720c1dd29d7c4689f4b83792f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf63ba909dd472b7ce95b05e8ed984ac3" id="r_gaf63ba909dd472b7ce95b05e8ed984ac3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaf63ba909dd472b7ce95b05e8ed984ac3">USB_OTG_DOEPINT_NYET</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8ea8387720c1dd29d7c4689f4b83792f">USB_OTG_DOEPINT_NYET_Msk</a></td></tr>
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<tr class="separator:gaf63ba909dd472b7ce95b05e8ed984ac3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga05052a0dcef08b6e6acaf900e3f4b39d" id="r_ga05052a0dcef08b6e6acaf900e3f4b39d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga05052a0dcef08b6e6acaf900e3f4b39d">USB_OTG_DOEPINT_STPKTRX_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga05052a0dcef08b6e6acaf900e3f4b39d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c90fbb29ef97f0974e4040889d12e34" id="r_ga2c90fbb29ef97f0974e4040889d12e34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2c90fbb29ef97f0974e4040889d12e34">USB_OTG_DOEPINT_STPKTRX_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga05052a0dcef08b6e6acaf900e3f4b39d">USB_OTG_DOEPINT_STPKTRX_Pos</a>)</td></tr>
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<tr class="separator:ga2c90fbb29ef97f0974e4040889d12e34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga90d44e256af7596e109c61925dbdb6fd" id="r_ga90d44e256af7596e109c61925dbdb6fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga90d44e256af7596e109c61925dbdb6fd">USB_OTG_DOEPINT_STPKTRX</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2c90fbb29ef97f0974e4040889d12e34">USB_OTG_DOEPINT_STPKTRX_Msk</a></td></tr>
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<tr class="separator:ga90d44e256af7596e109c61925dbdb6fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5fe13401b6bd1b7d884f5250ac4863bc" id="r_ga5fe13401b6bd1b7d884f5250ac4863bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe13401b6bd1b7d884f5250ac4863bc">USB_OTG_DOEPTSIZ_XFRSIZ_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga5fe13401b6bd1b7d884f5250ac4863bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab5ef41f398424f0a7e6a4c7cd6010c2" id="r_gaab5ef41f398424f0a7e6a4c7cd6010c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaab5ef41f398424f0a7e6a4c7cd6010c2">USB_OTG_DOEPTSIZ_XFRSIZ_Msk</a>   (0x7FFFFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga5fe13401b6bd1b7d884f5250ac4863bc">USB_OTG_DOEPTSIZ_XFRSIZ_Pos</a>)</td></tr>
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<tr class="separator:gaab5ef41f398424f0a7e6a4c7cd6010c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab954bdd4334a2643622e3d33fee16ad5" id="r_gab954bdd4334a2643622e3d33fee16ad5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab954bdd4334a2643622e3d33fee16ad5">USB_OTG_DOEPTSIZ_XFRSIZ</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaab5ef41f398424f0a7e6a4c7cd6010c2">USB_OTG_DOEPTSIZ_XFRSIZ_Msk</a></td></tr>
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<tr class="separator:gab954bdd4334a2643622e3d33fee16ad5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad4b9ba7c05cf5f15d1d68d5f01097daf" id="r_gad4b9ba7c05cf5f15d1d68d5f01097daf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad4b9ba7c05cf5f15d1d68d5f01097daf">USB_OTG_DOEPTSIZ_PKTCNT_Pos</a>   (19U)</td></tr>
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<tr class="separator:gad4b9ba7c05cf5f15d1d68d5f01097daf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga285281ff18968724fb73d8dc292b930b" id="r_ga285281ff18968724fb73d8dc292b930b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga285281ff18968724fb73d8dc292b930b">USB_OTG_DOEPTSIZ_PKTCNT_Msk</a>   (0x3FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gad4b9ba7c05cf5f15d1d68d5f01097daf">USB_OTG_DOEPTSIZ_PKTCNT_Pos</a>)</td></tr>
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<tr class="separator:ga285281ff18968724fb73d8dc292b930b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae7bc1fb16d2d5b7a8d92fce5a61a038f" id="r_gae7bc1fb16d2d5b7a8d92fce5a61a038f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gae7bc1fb16d2d5b7a8d92fce5a61a038f">USB_OTG_DOEPTSIZ_PKTCNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga285281ff18968724fb73d8dc292b930b">USB_OTG_DOEPTSIZ_PKTCNT_Msk</a></td></tr>
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<tr class="separator:gae7bc1fb16d2d5b7a8d92fce5a61a038f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaa3ab3c0bc7a7e35ff98521b58230188" id="r_gaaa3ab3c0bc7a7e35ff98521b58230188"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaaa3ab3c0bc7a7e35ff98521b58230188">USB_OTG_DOEPTSIZ_STUPCNT_Pos</a>   (29U)</td></tr>
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<tr class="separator:gaaa3ab3c0bc7a7e35ff98521b58230188"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadcb0c6895cd600227f3a037dfbddbbc5" id="r_gadcb0c6895cd600227f3a037dfbddbbc5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gadcb0c6895cd600227f3a037dfbddbbc5">USB_OTG_DOEPTSIZ_STUPCNT_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa3ab3c0bc7a7e35ff98521b58230188">USB_OTG_DOEPTSIZ_STUPCNT_Pos</a>)</td></tr>
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<tr class="separator:gadcb0c6895cd600227f3a037dfbddbbc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5a99a82646ef5a7a7785bec2d07334b5" id="r_ga5a99a82646ef5a7a7785bec2d07334b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5a99a82646ef5a7a7785bec2d07334b5">USB_OTG_DOEPTSIZ_STUPCNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gadcb0c6895cd600227f3a037dfbddbbc5">USB_OTG_DOEPTSIZ_STUPCNT_Msk</a></td></tr>
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<tr class="separator:ga5a99a82646ef5a7a7785bec2d07334b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cabae65ef4f05c5314de57beed11000" id="r_ga0cabae65ef4f05c5314de57beed11000"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cabae65ef4f05c5314de57beed11000">USB_OTG_DOEPTSIZ_STUPCNT_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa3ab3c0bc7a7e35ff98521b58230188">USB_OTG_DOEPTSIZ_STUPCNT_Pos</a>)</td></tr>
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<tr class="memitem:ga3b109418cfad831c4f292eb86d132f0e" id="r_ga3b109418cfad831c4f292eb86d132f0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga3b109418cfad831c4f292eb86d132f0e">USB_OTG_DOEPTSIZ_STUPCNT_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#gaaa3ab3c0bc7a7e35ff98521b58230188">USB_OTG_DOEPTSIZ_STUPCNT_Pos</a>)</td></tr>
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<tr class="separator:ga3b109418cfad831c4f292eb86d132f0e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7cf33736f41c6c0098df1ac2cb9dcb00" id="r_ga7cf33736f41c6c0098df1ac2cb9dcb00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga7cf33736f41c6c0098df1ac2cb9dcb00">USB_OTG_PCGCCTL_STOPCLK_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga7cf33736f41c6c0098df1ac2cb9dcb00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d4f9a974fab851fcfb0803ba5380b8d" id="r_ga1d4f9a974fab851fcfb0803ba5380b8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1d4f9a974fab851fcfb0803ba5380b8d">USB_OTG_PCGCCTL_STOPCLK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga7cf33736f41c6c0098df1ac2cb9dcb00">USB_OTG_PCGCCTL_STOPCLK_Pos</a>)</td></tr>
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<tr class="separator:ga1d4f9a974fab851fcfb0803ba5380b8d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77cb2d7ab53783663a7a6dd457d3ba25" id="r_ga77cb2d7ab53783663a7a6dd457d3ba25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77cb2d7ab53783663a7a6dd457d3ba25">USB_OTG_PCGCCTL_STOPCLK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga1d4f9a974fab851fcfb0803ba5380b8d">USB_OTG_PCGCCTL_STOPCLK_Msk</a></td></tr>
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<tr class="separator:ga77cb2d7ab53783663a7a6dd457d3ba25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga742b5f249d0b9b10fd616990149cf6c7" id="r_ga742b5f249d0b9b10fd616990149cf6c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga742b5f249d0b9b10fd616990149cf6c7">USB_OTG_PCGCCTL_GATECLK_Pos</a>   (1U)</td></tr>
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<tr class="separator:ga742b5f249d0b9b10fd616990149cf6c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa05b7e567009a05c0fbc460de78ece1f" id="r_gaa05b7e567009a05c0fbc460de78ece1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa05b7e567009a05c0fbc460de78ece1f">USB_OTG_PCGCCTL_GATECLK_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga742b5f249d0b9b10fd616990149cf6c7">USB_OTG_PCGCCTL_GATECLK_Pos</a>)</td></tr>
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<tr class="separator:gaa05b7e567009a05c0fbc460de78ece1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8756280c79db9bdd546f6dabce92849" id="r_gad8756280c79db9bdd546f6dabce92849"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad8756280c79db9bdd546f6dabce92849">USB_OTG_PCGCCTL_GATECLK</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa05b7e567009a05c0fbc460de78ece1f">USB_OTG_PCGCCTL_GATECLK_Msk</a></td></tr>
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<tr class="separator:gad8756280c79db9bdd546f6dabce92849"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga370573700a56720b49363b5a166303de" id="r_ga370573700a56720b49363b5a166303de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga370573700a56720b49363b5a166303de">USB_OTG_PCGCCTL_PHYSUSP_Pos</a>   (4U)</td></tr>
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<tr class="separator:ga370573700a56720b49363b5a166303de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac29bcd967dad8f66da440480b32b7b5d" id="r_gac29bcd967dad8f66da440480b32b7b5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac29bcd967dad8f66da440480b32b7b5d">USB_OTG_PCGCCTL_PHYSUSP_Msk</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga370573700a56720b49363b5a166303de">USB_OTG_PCGCCTL_PHYSUSP_Pos</a>)</td></tr>
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<tr class="separator:gac29bcd967dad8f66da440480b32b7b5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f07a7549ecc61ab2df0775ea177df12" id="r_ga8f07a7549ecc61ab2df0775ea177df12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f07a7549ecc61ab2df0775ea177df12">USB_OTG_PCGCCTL_PHYSUSP</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac29bcd967dad8f66da440480b32b7b5d">USB_OTG_PCGCCTL_PHYSUSP_Msk</a></td></tr>
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<tr class="separator:ga8f07a7549ecc61ab2df0775ea177df12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga45900186e59c0e66989c65180095d603" id="r_ga45900186e59c0e66989c65180095d603"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga45900186e59c0e66989c65180095d603">USB_OTG_CHNUM_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga45900186e59c0e66989c65180095d603"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga46419059b5b49059f5bdebe1b72722ef" id="r_ga46419059b5b49059f5bdebe1b72722ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga46419059b5b49059f5bdebe1b72722ef">USB_OTG_CHNUM_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga45900186e59c0e66989c65180095d603">USB_OTG_CHNUM_Pos</a>)</td></tr>
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<tr class="separator:ga46419059b5b49059f5bdebe1b72722ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e22ae686ec18ff21f8f576178463115" id="r_ga5e22ae686ec18ff21f8f576178463115"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga5e22ae686ec18ff21f8f576178463115">USB_OTG_CHNUM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga46419059b5b49059f5bdebe1b72722ef">USB_OTG_CHNUM_Msk</a></td></tr>
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<tr class="separator:ga5e22ae686ec18ff21f8f576178463115"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1901249182b97582cbe4a3644f31d20f" id="r_ga1901249182b97582cbe4a3644f31d20f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1901249182b97582cbe4a3644f31d20f">USB_OTG_CHNUM_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga45900186e59c0e66989c65180095d603">USB_OTG_CHNUM_Pos</a>)</td></tr>
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<tr class="separator:ga1901249182b97582cbe4a3644f31d20f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabda64fd2296cefde4a9f304c0b5150e3" id="r_gabda64fd2296cefde4a9f304c0b5150e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gabda64fd2296cefde4a9f304c0b5150e3">USB_OTG_CHNUM_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga45900186e59c0e66989c65180095d603">USB_OTG_CHNUM_Pos</a>)</td></tr>
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<tr class="separator:gabda64fd2296cefde4a9f304c0b5150e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0e852ea3f7aca27ba6cd281d1fdc5117" id="r_ga0e852ea3f7aca27ba6cd281d1fdc5117"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0e852ea3f7aca27ba6cd281d1fdc5117">USB_OTG_CHNUM_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga45900186e59c0e66989c65180095d603">USB_OTG_CHNUM_Pos</a>)</td></tr>
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<tr class="separator:ga0e852ea3f7aca27ba6cd281d1fdc5117"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga045af9896fe21c27d155de0bb98eb3bb" id="r_ga045af9896fe21c27d155de0bb98eb3bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga045af9896fe21c27d155de0bb98eb3bb">USB_OTG_CHNUM_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga45900186e59c0e66989c65180095d603">USB_OTG_CHNUM_Pos</a>)</td></tr>
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<tr class="memitem:gace8389218deec60cbc2cc42db1ff5870" id="r_gace8389218deec60cbc2cc42db1ff5870"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gace8389218deec60cbc2cc42db1ff5870">USB_OTG_BCNT_Pos</a>   (4U)</td></tr>
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<tr class="memitem:ga8835a43d2c40f61caee8af97be8de8d3" id="r_ga8835a43d2c40f61caee8af97be8de8d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8835a43d2c40f61caee8af97be8de8d3">USB_OTG_BCNT_Msk</a>   (0x7FFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#gace8389218deec60cbc2cc42db1ff5870">USB_OTG_BCNT_Pos</a>)</td></tr>
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<tr class="separator:ga8835a43d2c40f61caee8af97be8de8d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85cc2bdcb428f49f2de38db43a6da61b" id="r_ga85cc2bdcb428f49f2de38db43a6da61b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga85cc2bdcb428f49f2de38db43a6da61b">USB_OTG_BCNT</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga8835a43d2c40f61caee8af97be8de8d3">USB_OTG_BCNT_Msk</a></td></tr>
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<tr class="memitem:ga161e93b8ccc61342eb405c9956841d93" id="r_ga161e93b8ccc61342eb405c9956841d93"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga161e93b8ccc61342eb405c9956841d93">USB_OTG_DPID_Pos</a>   (15U)</td></tr>
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<tr class="separator:ga161e93b8ccc61342eb405c9956841d93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2a99858955bd807f3b3ab817ccb22dbf" id="r_ga2a99858955bd807f3b3ab817ccb22dbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga2a99858955bd807f3b3ab817ccb22dbf">USB_OTG_DPID_Msk</a>   (0x3UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga161e93b8ccc61342eb405c9956841d93">USB_OTG_DPID_Pos</a>)</td></tr>
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<tr class="memitem:gaba9fdf0a57d7a204dff9217d6b7e7a60" id="r_gaba9fdf0a57d7a204dff9217d6b7e7a60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaba9fdf0a57d7a204dff9217d6b7e7a60">USB_OTG_DPID</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#ga2a99858955bd807f3b3ab817ccb22dbf">USB_OTG_DPID_Msk</a></td></tr>
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<tr class="separator:gaba9fdf0a57d7a204dff9217d6b7e7a60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0cb8aeddd0bc7c194224de1c601c3aea" id="r_ga0cb8aeddd0bc7c194224de1c601c3aea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0cb8aeddd0bc7c194224de1c601c3aea">USB_OTG_DPID_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga161e93b8ccc61342eb405c9956841d93">USB_OTG_DPID_Pos</a>)</td></tr>
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<tr class="separator:ga0cb8aeddd0bc7c194224de1c601c3aea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8822d847cc21c903bfe427927f3ebd8f" id="r_ga8822d847cc21c903bfe427927f3ebd8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8822d847cc21c903bfe427927f3ebd8f">USB_OTG_DPID_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga161e93b8ccc61342eb405c9956841d93">USB_OTG_DPID_Pos</a>)</td></tr>
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<tr class="memitem:ga68c44befbf867cd110ad202dfbaf89bc" id="r_ga68c44befbf867cd110ad202dfbaf89bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga68c44befbf867cd110ad202dfbaf89bc">USB_OTG_PKTSTS_Pos</a>   (17U)</td></tr>
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<tr class="separator:ga68c44befbf867cd110ad202dfbaf89bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac0bbc3a438b82f7739fdb08721163c3b" id="r_gac0bbc3a438b82f7739fdb08721163c3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac0bbc3a438b82f7739fdb08721163c3b">USB_OTG_PKTSTS_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68c44befbf867cd110ad202dfbaf89bc">USB_OTG_PKTSTS_Pos</a>)</td></tr>
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<tr class="separator:gac0bbc3a438b82f7739fdb08721163c3b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga04a5d91a12a215c4eeeb06ce604c22e5" id="r_ga04a5d91a12a215c4eeeb06ce604c22e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga04a5d91a12a215c4eeeb06ce604c22e5">USB_OTG_PKTSTS</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gac0bbc3a438b82f7739fdb08721163c3b">USB_OTG_PKTSTS_Msk</a></td></tr>
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<tr class="separator:ga04a5d91a12a215c4eeeb06ce604c22e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77111a987b72536f21bfd7bb08594b35" id="r_ga77111a987b72536f21bfd7bb08594b35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga77111a987b72536f21bfd7bb08594b35">USB_OTG_PKTSTS_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68c44befbf867cd110ad202dfbaf89bc">USB_OTG_PKTSTS_Pos</a>)</td></tr>
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<tr class="memitem:gafa2fb9acefebdda4d1178fd41152354a" id="r_gafa2fb9acefebdda4d1178fd41152354a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gafa2fb9acefebdda4d1178fd41152354a">USB_OTG_PKTSTS_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68c44befbf867cd110ad202dfbaf89bc">USB_OTG_PKTSTS_Pos</a>)</td></tr>
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<tr class="memitem:gab280bdccc1f515e8b031ca572a40dbeb" id="r_gab280bdccc1f515e8b031ca572a40dbeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab280bdccc1f515e8b031ca572a40dbeb">USB_OTG_PKTSTS_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68c44befbf867cd110ad202dfbaf89bc">USB_OTG_PKTSTS_Pos</a>)</td></tr>
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<tr class="memitem:gad095ea293b9f4a79f215502575bc3c70" id="r_gad095ea293b9f4a79f215502575bc3c70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gad095ea293b9f4a79f215502575bc3c70">USB_OTG_PKTSTS_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga68c44befbf867cd110ad202dfbaf89bc">USB_OTG_PKTSTS_Pos</a>)</td></tr>
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<tr class="separator:gad095ea293b9f4a79f215502575bc3c70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b40ae8187cbd4c17738b04c43cf7fbb" id="r_ga0b40ae8187cbd4c17738b04c43cf7fbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga0b40ae8187cbd4c17738b04c43cf7fbb">USB_OTG_EPNUM_Pos</a>   (0U)</td></tr>
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<tr class="separator:ga0b40ae8187cbd4c17738b04c43cf7fbb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa45e8d6116688de705fd0d55680e1a87" id="r_gaa45e8d6116688de705fd0d55680e1a87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gaa45e8d6116688de705fd0d55680e1a87">USB_OTG_EPNUM_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b40ae8187cbd4c17738b04c43cf7fbb">USB_OTG_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:gaa45e8d6116688de705fd0d55680e1a87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga91d336fd8272e4c22fc474e468b81af9" id="r_ga91d336fd8272e4c22fc474e468b81af9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga91d336fd8272e4c22fc474e468b81af9">USB_OTG_EPNUM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gaa45e8d6116688de705fd0d55680e1a87">USB_OTG_EPNUM_Msk</a></td></tr>
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<tr class="separator:ga91d336fd8272e4c22fc474e468b81af9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga61585b0ce43fd0b1e6b228598afc219c" id="r_ga61585b0ce43fd0b1e6b228598afc219c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga61585b0ce43fd0b1e6b228598afc219c">USB_OTG_EPNUM_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b40ae8187cbd4c17738b04c43cf7fbb">USB_OTG_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:ga61585b0ce43fd0b1e6b228598afc219c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga483d3ad09cb1f0a2c0b162c8a55ed7c6" id="r_ga483d3ad09cb1f0a2c0b162c8a55ed7c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga483d3ad09cb1f0a2c0b162c8a55ed7c6">USB_OTG_EPNUM_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b40ae8187cbd4c17738b04c43cf7fbb">USB_OTG_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:ga483d3ad09cb1f0a2c0b162c8a55ed7c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2438798104047b9b51f8c773d02858a" id="r_gac2438798104047b9b51f8c773d02858a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gac2438798104047b9b51f8c773d02858a">USB_OTG_EPNUM_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b40ae8187cbd4c17738b04c43cf7fbb">USB_OTG_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:gac2438798104047b9b51f8c773d02858a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42c2df6bfed558ca73545573166296bf" id="r_ga42c2df6bfed558ca73545573166296bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga42c2df6bfed558ca73545573166296bf">USB_OTG_EPNUM_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga0b40ae8187cbd4c17738b04c43cf7fbb">USB_OTG_EPNUM_Pos</a>)</td></tr>
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<tr class="separator:ga42c2df6bfed558ca73545573166296bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b5bcd968b0874ed977dfafacb1d51f1" id="r_ga1b5bcd968b0874ed977dfafacb1d51f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga1b5bcd968b0874ed977dfafacb1d51f1">USB_OTG_FRMNUM_Pos</a>   (21U)</td></tr>
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<tr class="separator:ga1b5bcd968b0874ed977dfafacb1d51f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab3dde44ba66dda008f4f22e73d6de3eb" id="r_gab3dde44ba66dda008f4f22e73d6de3eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#gab3dde44ba66dda008f4f22e73d6de3eb">USB_OTG_FRMNUM_Msk</a>   (0xFUL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b5bcd968b0874ed977dfafacb1d51f1">USB_OTG_FRMNUM_Pos</a>)</td></tr>
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<tr class="separator:gab3dde44ba66dda008f4f22e73d6de3eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69105bca4abdabe5c66a1c44ae714776" id="r_ga69105bca4abdabe5c66a1c44ae714776"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga69105bca4abdabe5c66a1c44ae714776">USB_OTG_FRMNUM</a>   <a class="el" href="group___peripheral___registers___bits___definition.html#gab3dde44ba66dda008f4f22e73d6de3eb">USB_OTG_FRMNUM_Msk</a></td></tr>
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<tr class="separator:ga69105bca4abdabe5c66a1c44ae714776"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6a9a2d9f4d804f38e9ee29038139498d" id="r_ga6a9a2d9f4d804f38e9ee29038139498d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga6a9a2d9f4d804f38e9ee29038139498d">USB_OTG_FRMNUM_0</a>   (0x1UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b5bcd968b0874ed977dfafacb1d51f1">USB_OTG_FRMNUM_Pos</a>)</td></tr>
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<tr class="separator:ga6a9a2d9f4d804f38e9ee29038139498d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d93a3bde8de46b481691a1e87b36bfd" id="r_ga4d93a3bde8de46b481691a1e87b36bfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga4d93a3bde8de46b481691a1e87b36bfd">USB_OTG_FRMNUM_1</a>   (0x2UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b5bcd968b0874ed977dfafacb1d51f1">USB_OTG_FRMNUM_Pos</a>)</td></tr>
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<tr class="separator:ga4d93a3bde8de46b481691a1e87b36bfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8f8be72a63a9942462f0752d5371e619" id="r_ga8f8be72a63a9942462f0752d5371e619"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga8f8be72a63a9942462f0752d5371e619">USB_OTG_FRMNUM_2</a>   (0x4UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b5bcd968b0874ed977dfafacb1d51f1">USB_OTG_FRMNUM_Pos</a>)</td></tr>
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<tr class="separator:ga8f8be72a63a9942462f0752d5371e619"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b50095fee4cb94be4d1d02aadd3964e" id="r_ga9b50095fee4cb94be4d1d02aadd3964e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral___registers___bits___definition.html#ga9b50095fee4cb94be4d1d02aadd3964e">USB_OTG_FRMNUM_3</a>   (0x8UL << <a class="el" href="group___peripheral___registers___bits___definition.html#ga1b5bcd968b0874ed977dfafacb1d51f1">USB_OTG_FRMNUM_Pos</a>)</td></tr>
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<tr class="separator:ga9b50095fee4cb94be4d1d02aadd3964e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2204b62b378bcf08b3b9006c184c7c23" id="r_ga2204b62b378bcf08b3b9006c184c7c23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga2204b62b378bcf08b3b9006c184c7c23">IS_ADC_ALL_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga2204b62b378bcf08b3b9006c184c7c23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga26b4e299ac54d09082645a70f889c143" id="r_ga26b4e299ac54d09082645a70f889c143"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga26b4e299ac54d09082645a70f889c143">IS_ADC_MULTIMODE_MASTER_INSTANCE</a>(INSTANCE)   ((INSTANCE) == <a class="el" href="group___peripheral__declaration.html#ga90d2d5c526ce5c0a551f533eccbee71a">ADC1</a>)</td></tr>
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<tr class="separator:ga26b4e299ac54d09082645a70f889c143"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad8a5831c786b6b265531b890a194cbe2" id="r_gad8a5831c786b6b265531b890a194cbe2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gad8a5831c786b6b265531b890a194cbe2">IS_ADC_COMMON_INSTANCE</a>(INSTANCE)   ((INSTANCE) == <a class="el" href="group___peripheral__declaration.html#ga813de18391e45c0854aafd470c2d547f">ADC123_COMMON</a>)</td></tr>
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<tr class="separator:gad8a5831c786b6b265531b890a194cbe2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga974dd363bcb2a5f48ec032509fd4ece3" id="r_ga974dd363bcb2a5f48ec032509fd4ece3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga974dd363bcb2a5f48ec032509fd4ece3">IS_CAN_ALL_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga974dd363bcb2a5f48ec032509fd4ece3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa514941a7f02f65eb27450c05e4e8dd1" id="r_gaa514941a7f02f65eb27450c05e4e8dd1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gaa514941a7f02f65eb27450c05e4e8dd1">IS_CRC_ALL_INSTANCE</a>(INSTANCE)   ((INSTANCE) == <a class="el" href="group___peripheral__declaration.html#ga4381bb54c2dbc34500521165aa7b89b1">CRC</a>)</td></tr>
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<tr class="separator:gaa514941a7f02f65eb27450c05e4e8dd1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga94426b97cc5f1644d67f291cbcdba6d8" id="r_ga94426b97cc5f1644d67f291cbcdba6d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga94426b97cc5f1644d67f291cbcdba6d8">IS_DAC_ALL_INSTANCE</a>(INSTANCE)   ((INSTANCE) == <a class="el" href="group___peripheral__declaration.html#gaffb5ff8779fa698f3c7165a617d56e4f">DAC1</a>)</td></tr>
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<tr class="separator:ga94426b97cc5f1644d67f291cbcdba6d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca27f42a2f7dd5715c74884bd9af310d" id="r_gaca27f42a2f7dd5715c74884bd9af310d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gaca27f42a2f7dd5715c74884bd9af310d">IS_DCMI_ALL_INSTANCE</a>(INSTANCE)   ((INSTANCE) == <a class="el" href="group___peripheral__declaration.html#ga049d9f61cb078d642e68f3c22bb6d90c">DCMI</a>)</td></tr>
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<tr class="separator:gaca27f42a2f7dd5715c74884bd9af310d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafd60def465da605e33644e28072aee9c" id="r_gafd60def465da605e33644e28072aee9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gafd60def465da605e33644e28072aee9c">IS_DMA_STREAM_ALL_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gafd60def465da605e33644e28072aee9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga783626dd2431afebea836a102e318957" id="r_ga783626dd2431afebea836a102e318957"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga783626dd2431afebea836a102e318957">IS_GPIO_ALL_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga783626dd2431afebea836a102e318957"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacdf0149a4e8c41a6814c13613c38a6b2" id="r_gacdf0149a4e8c41a6814c13613c38a6b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gacdf0149a4e8c41a6814c13613c38a6b2">IS_I2C_ALL_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gacdf0149a4e8c41a6814c13613c38a6b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85b79d63f4643c0de9a7519290a0eceb" id="r_ga85b79d63f4643c0de9a7519290a0eceb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga85b79d63f4643c0de9a7519290a0eceb">IS_SMBUS_ALL_INSTANCE</a>   <a class="el" href="group___exported__macros.html#gacdf0149a4e8c41a6814c13613c38a6b2">IS_I2C_ALL_INSTANCE</a></td></tr>
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<tr class="separator:ga85b79d63f4643c0de9a7519290a0eceb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0b35685911e3c7a38ee89e5cdc5a82fa" id="r_ga0b35685911e3c7a38ee89e5cdc5a82fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga0b35685911e3c7a38ee89e5cdc5a82fa">IS_I2S_ALL_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga0b35685911e3c7a38ee89e5cdc5a82fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2f0d621c72fe4e5039562472460e29ab" id="r_ga2f0d621c72fe4e5039562472460e29ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga2f0d621c72fe4e5039562472460e29ab">IS_I2S_EXT_ALL_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga2f0d621c72fe4e5039562472460e29ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga839b019f23ec240da66dd50a21ab5025" id="r_ga839b019f23ec240da66dd50a21ab5025"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga839b019f23ec240da66dd50a21ab5025">IS_I2S_ALL_INSTANCE_EXT</a>   <a class="el" href="group___exported__macros.html#ga2f0d621c72fe4e5039562472460e29ab">IS_I2S_EXT_ALL_INSTANCE</a></td></tr>
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<tr class="separator:ga839b019f23ec240da66dd50a21ab5025"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7369db258c1b8931b427262d0673751f" id="r_ga7369db258c1b8931b427262d0673751f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga7369db258c1b8931b427262d0673751f">IS_RNG_ALL_INSTANCE</a>(INSTANCE)   ((INSTANCE) == <a class="el" href="group___peripheral__declaration.html#ga5b0885b8b55bbc13691092b704d9309f">RNG</a>)</td></tr>
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<tr class="separator:ga7369db258c1b8931b427262d0673751f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab4230e8bd4d88adc4250f041d67375ce" id="r_gab4230e8bd4d88adc4250f041d67375ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gab4230e8bd4d88adc4250f041d67375ce">IS_RTC_ALL_INSTANCE</a>(INSTANCE)   ((INSTANCE) == <a class="el" href="group___peripheral__declaration.html#ga5359a088f5d8b20ce74d920e46059304">RTC</a>)</td></tr>
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<tr class="separator:gab4230e8bd4d88adc4250f041d67375ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga59c7619a86c03df3ebeb4bd8aaef982c" id="r_ga59c7619a86c03df3ebeb4bd8aaef982c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga59c7619a86c03df3ebeb4bd8aaef982c">IS_SPI_ALL_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga59c7619a86c03df3ebeb4bd8aaef982c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba506eb03409b21388d7c5a6401a4f98" id="r_gaba506eb03409b21388d7c5a6401a4f98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gaba506eb03409b21388d7c5a6401a4f98">IS_TIM_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gaba506eb03409b21388d7c5a6401a4f98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c02efc77b1bfb640d7f6593f58ad464" id="r_ga0c02efc77b1bfb640d7f6593f58ad464"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga0c02efc77b1bfb640d7f6593f58ad464">IS_TIM_CC1_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga0c02efc77b1bfb640d7f6593f58ad464"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ef84d278cf917c7e420b94687b39c7c" id="r_ga6ef84d278cf917c7e420b94687b39c7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga6ef84d278cf917c7e420b94687b39c7c">IS_TIM_CC2_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga6ef84d278cf917c7e420b94687b39c7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c37cb8f925fd43622cce7a4c00fd95e" id="r_ga0c37cb8f925fd43622cce7a4c00fd95e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga0c37cb8f925fd43622cce7a4c00fd95e">IS_TIM_CC3_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga0c37cb8f925fd43622cce7a4c00fd95e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae72b7182a73d81c33196265b31091c07" id="r_gae72b7182a73d81c33196265b31091c07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gae72b7182a73d81c33196265b31091c07">IS_TIM_CC4_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gae72b7182a73d81c33196265b31091c07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e85353dbe9dc9d80ad06f0b935c12e1" id="r_ga7e85353dbe9dc9d80ad06f0b935c12e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga7e85353dbe9dc9d80ad06f0b935c12e1">IS_TIM_ADVANCED_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga7e85353dbe9dc9d80ad06f0b935c12e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6e06388143bb7bb111c78a3686dd753a" id="r_ga6e06388143bb7bb111c78a3686dd753a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga6e06388143bb7bb111c78a3686dd753a">IS_TIM_XOR_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga6e06388143bb7bb111c78a3686dd753a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad51d77b3bcc12a3a5c308d727b561371" id="r_gad51d77b3bcc12a3a5c308d727b561371"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gad51d77b3bcc12a3a5c308d727b561371">IS_TIM_DMA_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gad51d77b3bcc12a3a5c308d727b561371"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad80a186286ce3daa92249a8d52111aaf" id="r_gad80a186286ce3daa92249a8d52111aaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gad80a186286ce3daa92249a8d52111aaf">IS_TIM_DMA_CC_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gad80a186286ce3daa92249a8d52111aaf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8111ef18a809cd882ef327399fdbfc8f" id="r_ga8111ef18a809cd882ef327399fdbfc8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga8111ef18a809cd882ef327399fdbfc8f">IS_TIM_CCDMA_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga8111ef18a809cd882ef327399fdbfc8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ed43d4e9823446a1b9d43afc452f42e" id="r_ga1ed43d4e9823446a1b9d43afc452f42e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga1ed43d4e9823446a1b9d43afc452f42e">IS_TIM_DMABURST_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga1ed43d4e9823446a1b9d43afc452f42e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98104b1522d066b0c20205ca179d0eba" id="r_ga98104b1522d066b0c20205ca179d0eba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga98104b1522d066b0c20205ca179d0eba">IS_TIM_MASTER_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga98104b1522d066b0c20205ca179d0eba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ba7d4187dba8dfb4ffd610312e8af14" id="r_ga3ba7d4187dba8dfb4ffd610312e8af14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga3ba7d4187dba8dfb4ffd610312e8af14">IS_TIM_SLAVE_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga3ba7d4187dba8dfb4ffd610312e8af14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac41867bf288927ff8ff10a85e67a591b" id="r_gac41867bf288927ff8ff10a85e67a591b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gac41867bf288927ff8ff10a85e67a591b">IS_TIM_32B_COUNTER_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gac41867bf288927ff8ff10a85e67a591b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac71942c3817f1a893ef84fefe69496b7" id="r_gac71942c3817f1a893ef84fefe69496b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gac71942c3817f1a893ef84fefe69496b7">IS_TIM_ETR_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gac71942c3817f1a893ef84fefe69496b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6bb03cf116b07bfe1bd527f8ab61a7f9" id="r_ga6bb03cf116b07bfe1bd527f8ab61a7f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga6bb03cf116b07bfe1bd527f8ab61a7f9">IS_TIM_REMAP_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga6bb03cf116b07bfe1bd527f8ab61a7f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6517a51ea79512a42bc53c718a77f18e" id="r_ga6517a51ea79512a42bc53c718a77f18e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga6517a51ea79512a42bc53c718a77f18e">IS_TIM_CCX_INSTANCE</a>(INSTANCE, CHANNEL)</td></tr>
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<tr class="separator:ga6517a51ea79512a42bc53c718a77f18e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7181cfd1649c4e65e24b7c863e94a54f" id="r_ga7181cfd1649c4e65e24b7c863e94a54f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga7181cfd1649c4e65e24b7c863e94a54f">IS_TIM_CCXN_INSTANCE</a>(INSTANCE, CHANNEL)</td></tr>
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<tr class="separator:ga7181cfd1649c4e65e24b7c863e94a54f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac0e3e7e7a18fd8eb81734b2baf9e3be" id="r_gaac0e3e7e7a18fd8eb81734b2baf9e3be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gaac0e3e7e7a18fd8eb81734b2baf9e3be">IS_TIM_COUNTER_MODE_SELECT_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gaac0e3e7e7a18fd8eb81734b2baf9e3be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac54b9f42e8ab07c41abe7d96d13d698a" id="r_gac54b9f42e8ab07c41abe7d96d13d698a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gac54b9f42e8ab07c41abe7d96d13d698a">IS_TIM_CLOCK_DIVISION_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gac54b9f42e8ab07c41abe7d96d13d698a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f61206c3c8b20784f9d237dce300afd" id="r_ga5f61206c3c8b20784f9d237dce300afd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga5f61206c3c8b20784f9d237dce300afd">IS_TIM_COMMUTATION_EVENT_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga5f61206c3c8b20784f9d237dce300afd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7bf2abf939c55a4c8284c184735accdc" id="r_ga7bf2abf939c55a4c8284c184735accdc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga7bf2abf939c55a4c8284c184735accdc">IS_TIM_OCXREF_CLEAR_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga7bf2abf939c55a4c8284c184735accdc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ca20886f56bf7611ad511433b9caade" id="r_ga0ca20886f56bf7611ad511433b9caade"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga0ca20886f56bf7611ad511433b9caade">IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga0ca20886f56bf7611ad511433b9caade"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7beb8f84094e6a1567d10177cc4fdae9" id="r_ga7beb8f84094e6a1567d10177cc4fdae9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga7beb8f84094e6a1567d10177cc4fdae9">IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga7beb8f84094e6a1567d10177cc4fdae9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbd23fd1f9f73dc249b16c89131a671c" id="r_gacbd23fd1f9f73dc249b16c89131a671c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gacbd23fd1f9f73dc249b16c89131a671c">IS_TIM_CLOCKSOURCE_TIX_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gacbd23fd1f9f73dc249b16c89131a671c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga57882c3c75fddf0ccf0c6ecf99b3d3df" id="r_ga57882c3c75fddf0ccf0c6ecf99b3d3df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga57882c3c75fddf0ccf0c6ecf99b3d3df">IS_TIM_CLOCKSOURCE_ITRX_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga57882c3c75fddf0ccf0c6ecf99b3d3df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3b470612fd4c4e29fb985247056b1e07" id="r_ga3b470612fd4c4e29fb985247056b1e07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga3b470612fd4c4e29fb985247056b1e07">IS_TIM_REPETITION_COUNTER_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga3b470612fd4c4e29fb985247056b1e07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacb14170c4996e004849647d8cb626402" id="r_gacb14170c4996e004849647d8cb626402"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gacb14170c4996e004849647d8cb626402">IS_TIM_ENCODER_INTERFACE_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gacb14170c4996e004849647d8cb626402"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga979ea18ba0931f5ed15cc2f3ac84794b" id="r_ga979ea18ba0931f5ed15cc2f3ac84794b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga979ea18ba0931f5ed15cc2f3ac84794b">IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga979ea18ba0931f5ed15cc2f3ac84794b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga68b8d9ca22720c9034753c604d83500d" id="r_ga68b8d9ca22720c9034753c604d83500d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga68b8d9ca22720c9034753c604d83500d">IS_TIM_BREAK_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga68b8d9ca22720c9034753c604d83500d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafbce654f84a7c994817453695ac91cbe" id="r_gafbce654f84a7c994817453695ac91cbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gafbce654f84a7c994817453695ac91cbe">IS_USART_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gafbce654f84a7c994817453695ac91cbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga69c4aa0c561c4c39c621710fbbb0cb7b" id="r_ga69c4aa0c561c4c39c621710fbbb0cb7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga69c4aa0c561c4c39c621710fbbb0cb7b">IS_UART_HALFDUPLEX_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga69c4aa0c561c4c39c621710fbbb0cb7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga14e4b19f7c750110f6c27cf26347ba45" id="r_ga14e4b19f7c750110f6c27cf26347ba45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga14e4b19f7c750110f6c27cf26347ba45">IS_UART_INSTANCE</a>   <a class="el" href="group___exported__macros.html#ga69c4aa0c561c4c39c621710fbbb0cb7b">IS_UART_HALFDUPLEX_INSTANCE</a></td></tr>
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<tr class="separator:ga14e4b19f7c750110f6c27cf26347ba45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf9a11d0720f3efa780126414a4ac50ad" id="r_gaf9a11d0720f3efa780126414a4ac50ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gaf9a11d0720f3efa780126414a4ac50ad">IS_UART_HWFLOW_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gaf9a11d0720f3efa780126414a4ac50ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7905bb5a02acf0e92ddf40bdd8dcdc0" id="r_gaf7905bb5a02acf0e92ddf40bdd8dcdc0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gaf7905bb5a02acf0e92ddf40bdd8dcdc0">IS_UART_LIN_INSTANCE</a>   <a class="el" href="group___exported__macros.html#ga69c4aa0c561c4c39c621710fbbb0cb7b">IS_UART_HALFDUPLEX_INSTANCE</a></td></tr>
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<tr class="separator:gaf7905bb5a02acf0e92ddf40bdd8dcdc0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2734c105403831749ccb34eeb058988" id="r_gab2734c105403831749ccb34eeb058988"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gab2734c105403831749ccb34eeb058988">IS_SMARTCARD_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gab2734c105403831749ccb34eeb058988"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98ae6698dc54d8441fce553a65bf5429" id="r_ga98ae6698dc54d8441fce553a65bf5429"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga98ae6698dc54d8441fce553a65bf5429">IS_IRDA_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga98ae6698dc54d8441fce553a65bf5429"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadaf663c55446f04fa69ee912b8890b32" id="r_gadaf663c55446f04fa69ee912b8890b32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gadaf663c55446f04fa69ee912b8890b32">IS_PCD_ALL_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:gadaf663c55446f04fa69ee912b8890b32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6696ebd1aea007a19e831517f3e1f497" id="r_ga6696ebd1aea007a19e831517f3e1f497"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga6696ebd1aea007a19e831517f3e1f497">IS_HCD_ALL_INSTANCE</a>(INSTANCE)</td></tr>
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<tr class="separator:ga6696ebd1aea007a19e831517f3e1f497"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga73932cb2c83be6be1884d3cba2fc0063" id="r_ga73932cb2c83be6be1884d3cba2fc0063"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga73932cb2c83be6be1884d3cba2fc0063">IS_SDIO_ALL_INSTANCE</a>(INSTANCE)   ((INSTANCE) == <a class="el" href="group___peripheral__declaration.html#ga8149aa2760fffac16bc75216d5fd9331">SDIO</a>)</td></tr>
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<tr class="separator:ga73932cb2c83be6be1884d3cba2fc0063"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9ec4c52f0572ee67d043e006f1d5e39" id="r_gad9ec4c52f0572ee67d043e006f1d5e39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gad9ec4c52f0572ee67d043e006f1d5e39">IS_IWDG_ALL_INSTANCE</a>(INSTANCE)   ((INSTANCE) == <a class="el" href="group___peripheral__declaration.html#gad16b79dd94ee85d261d08a8ee94187e7">IWDG</a>)</td></tr>
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<tr class="separator:gad9ec4c52f0572ee67d043e006f1d5e39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2a8aaec233e19987232455643a04d6f" id="r_gac2a8aaec233e19987232455643a04d6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gac2a8aaec233e19987232455643a04d6f">IS_WWDG_ALL_INSTANCE</a>(INSTANCE)   ((INSTANCE) == <a class="el" href="group___peripheral__declaration.html#ga9821fd01757986612ddb8982e2fe27f1">WWDG</a>)</td></tr>
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<tr class="separator:gac2a8aaec233e19987232455643a04d6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c58971ce9062c1c7bc42e1c7ea4df32" id="r_ga4c58971ce9062c1c7bc42e1c7ea4df32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga4c58971ce9062c1c7bc42e1c7ea4df32">USB_OTG_FS_HOST_MAX_CHANNEL_NBR</a>   8U</td></tr>
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<tr class="separator:ga4c58971ce9062c1c7bc42e1c7ea4df32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaccec7ca403e63ea963c363ceb7301ca6" id="r_gaccec7ca403e63ea963c363ceb7301ca6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gaccec7ca403e63ea963c363ceb7301ca6">USB_OTG_FS_MAX_IN_ENDPOINTS</a>   4U /* Including EP0 */</td></tr>
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<tr class="separator:gaccec7ca403e63ea963c363ceb7301ca6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d58ab8276cfdef9aa868bfdd2590aae" id="r_ga1d58ab8276cfdef9aa868bfdd2590aae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga1d58ab8276cfdef9aa868bfdd2590aae">USB_OTG_FS_MAX_OUT_ENDPOINTS</a>   4U /* Including EP0 */</td></tr>
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<tr class="separator:ga1d58ab8276cfdef9aa868bfdd2590aae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e726d88af0f77cb8a49ff7b666fd990" id="r_ga1e726d88af0f77cb8a49ff7b666fd990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga1e726d88af0f77cb8a49ff7b666fd990">USB_OTG_FS_TOTAL_FIFO_SIZE</a>   1280U /* in Bytes */</td></tr>
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<tr class="separator:ga1e726d88af0f77cb8a49ff7b666fd990"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab0a3c8475d96f7bb0c8a6b8a7e0c943c" id="r_gab0a3c8475d96f7bb0c8a6b8a7e0c943c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gab0a3c8475d96f7bb0c8a6b8a7e0c943c">RCC_PLLCFGR_RST_VALUE</a>   0x24003010U</td></tr>
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<tr class="separator:gab0a3c8475d96f7bb0c8a6b8a7e0c943c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5ca7e3fcb49274bb60c660221bbca5b" id="r_gab5ca7e3fcb49274bb60c660221bbca5b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gab5ca7e3fcb49274bb60c660221bbca5b">RCC_PLLI2SCFGR_RST_VALUE</a>   0x20003000U</td></tr>
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<tr class="separator:gab5ca7e3fcb49274bb60c660221bbca5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08aeea283003a2c787227347087b5b1f" id="r_ga08aeea283003a2c787227347087b5b1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga08aeea283003a2c787227347087b5b1f">RCC_MAX_FREQUENCY</a>   168000000U</td></tr>
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<tr class="separator:ga08aeea283003a2c787227347087b5b1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga152c4bb0b78589a06d72e0170dd3b304" id="r_ga152c4bb0b78589a06d72e0170dd3b304"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga152c4bb0b78589a06d72e0170dd3b304">RCC_MAX_FREQUENCY_SCALE1</a>   <a class="el" href="group___exported__macros.html#ga08aeea283003a2c787227347087b5b1f">RCC_MAX_FREQUENCY</a></td></tr>
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<tr class="separator:ga152c4bb0b78589a06d72e0170dd3b304"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafcb2c5211d9cbed86b111c83a0ce427b" id="r_gafcb2c5211d9cbed86b111c83a0ce427b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gafcb2c5211d9cbed86b111c83a0ce427b">RCC_MAX_FREQUENCY_SCALE2</a>   144000000U</td></tr>
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<tr class="separator:gafcb2c5211d9cbed86b111c83a0ce427b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga85746dffdc6d015f5142d7e16489ca84" id="r_ga85746dffdc6d015f5142d7e16489ca84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga85746dffdc6d015f5142d7e16489ca84">RCC_PLLVCO_OUTPUT_MIN</a>   100000000U</td></tr>
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<tr class="separator:ga85746dffdc6d015f5142d7e16489ca84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga288d68c2604cea8548eccdef3873923f" id="r_ga288d68c2604cea8548eccdef3873923f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga288d68c2604cea8548eccdef3873923f">RCC_PLLVCO_INPUT_MIN</a>   950000U</td></tr>
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<tr class="separator:ga288d68c2604cea8548eccdef3873923f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3fd37dbfa74739a3c698ab4755fa27e" id="r_gad3fd37dbfa74739a3c698ab4755fa27e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gad3fd37dbfa74739a3c698ab4755fa27e">RCC_PLLVCO_INPUT_MAX</a>   2100000U</td></tr>
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<tr class="separator:gad3fd37dbfa74739a3c698ab4755fa27e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaba6ddae0375763847f8dc3e91173d714" id="r_gaba6ddae0375763847f8dc3e91173d714"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gaba6ddae0375763847f8dc3e91173d714">RCC_PLLVCO_OUTPUT_MAX</a>   432000000U</td></tr>
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<tr class="separator:gaba6ddae0375763847f8dc3e91173d714"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6015e60e123ddde47bb3ddfab170c5a1" id="r_ga6015e60e123ddde47bb3ddfab170c5a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga6015e60e123ddde47bb3ddfab170c5a1">RCC_PLLN_MIN_VALUE</a>   50U</td></tr>
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<tr class="separator:ga6015e60e123ddde47bb3ddfab170c5a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d6c2fd92a420bb80caf8ca2cadb6a62" id="r_ga9d6c2fd92a420bb80caf8ca2cadb6a62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga9d6c2fd92a420bb80caf8ca2cadb6a62">RCC_PLLN_MAX_VALUE</a>   432U</td></tr>
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<tr class="separator:ga9d6c2fd92a420bb80caf8ca2cadb6a62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga980965268c210a75ca5bb1e6b59b4052" id="r_ga980965268c210a75ca5bb1e6b59b4052"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga980965268c210a75ca5bb1e6b59b4052">FLASH_SCALE1_LATENCY1_FREQ</a>   30000000U</td></tr>
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<tr class="separator:ga980965268c210a75ca5bb1e6b59b4052"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53673600707f291baa71c30919f8da98" id="r_ga53673600707f291baa71c30919f8da98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga53673600707f291baa71c30919f8da98">FLASH_SCALE1_LATENCY2_FREQ</a>   60000000U</td></tr>
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<tr class="separator:ga53673600707f291baa71c30919f8da98"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga547cb8d59cf6a2a73a0f76331e4492df" id="r_ga547cb8d59cf6a2a73a0f76331e4492df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga547cb8d59cf6a2a73a0f76331e4492df">FLASH_SCALE1_LATENCY3_FREQ</a>   90000000U</td></tr>
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<tr class="separator:ga547cb8d59cf6a2a73a0f76331e4492df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga600fe88d1dfa0faef16947e24f52e84e" id="r_ga600fe88d1dfa0faef16947e24f52e84e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga600fe88d1dfa0faef16947e24f52e84e">FLASH_SCALE1_LATENCY4_FREQ</a>   120000000U</td></tr>
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<tr class="separator:ga600fe88d1dfa0faef16947e24f52e84e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf576f3543b7909cf6c889e05829d37a0" id="r_gaf576f3543b7909cf6c889e05829d37a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gaf576f3543b7909cf6c889e05829d37a0">FLASH_SCALE1_LATENCY5_FREQ</a>   150000000U</td></tr>
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<tr class="separator:gaf576f3543b7909cf6c889e05829d37a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga19ba80e0c72cd041274f831901f302f9" id="r_ga19ba80e0c72cd041274f831901f302f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga19ba80e0c72cd041274f831901f302f9">FLASH_SCALE2_LATENCY1_FREQ</a>   30000000U</td></tr>
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<tr class="separator:ga19ba80e0c72cd041274f831901f302f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga98847021d5de23ea0458b490c74e6299" id="r_ga98847021d5de23ea0458b490c74e6299"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga98847021d5de23ea0458b490c74e6299">FLASH_SCALE2_LATENCY2_FREQ</a>   60000000U</td></tr>
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<tr class="separator:ga98847021d5de23ea0458b490c74e6299"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6956d1ea5f9484a43213022ebff8cf03" id="r_ga6956d1ea5f9484a43213022ebff8cf03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga6956d1ea5f9484a43213022ebff8cf03">FLASH_SCALE2_LATENCY3_FREQ</a>   90000000U</td></tr>
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<tr class="separator:ga6956d1ea5f9484a43213022ebff8cf03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8fc5a396df42d76fb41f377e71513ecb" id="r_ga8fc5a396df42d76fb41f377e71513ecb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga8fc5a396df42d76fb41f377e71513ecb">FLASH_SCALE2_LATENCY4_FREQ</a>   12000000U</td></tr>
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<tr class="separator:ga8fc5a396df42d76fb41f377e71513ecb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga974d43b38d7e7578fa7ac69c64dcc473" id="r_ga974d43b38d7e7578fa7ac69c64dcc473"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga974d43b38d7e7578fa7ac69c64dcc473">USB_OTG_HS_HOST_MAX_CHANNEL_NBR</a>   12U</td></tr>
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<tr class="separator:ga974d43b38d7e7578fa7ac69c64dcc473"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae79bbfa7391870814f10c8025ade8a2a" id="r_gae79bbfa7391870814f10c8025ade8a2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gae79bbfa7391870814f10c8025ade8a2a">USB_OTG_HS_MAX_IN_ENDPOINTS</a>   6U /* Including EP0 */</td></tr>
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<tr class="separator:gae79bbfa7391870814f10c8025ade8a2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gace63bb65e2fb24f0df6ebe1e65efa560" id="r_gace63bb65e2fb24f0df6ebe1e65efa560"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#gace63bb65e2fb24f0df6ebe1e65efa560">USB_OTG_HS_MAX_OUT_ENDPOINTS</a>   6U /* Including EP0 */</td></tr>
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<tr class="separator:gace63bb65e2fb24f0df6ebe1e65efa560"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga55a4488eac406bcff895de59782fd6a7" id="r_ga55a4488eac406bcff895de59782fd6a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga55a4488eac406bcff895de59782fd6a7">USB_OTG_HS_TOTAL_FIFO_SIZE</a>   4096U /* in Bytes */</td></tr>
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<tr class="separator:ga55a4488eac406bcff895de59782fd6a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1452f42f926ec3886d3688352472f960" id="r_ga1452f42f926ec3886d3688352472f960"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga1452f42f926ec3886d3688352472f960">FMC_IRQn</a>   <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a70450df88125476d5771f2ff3f562536">FSMC_IRQn</a></td></tr>
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<tr class="separator:ga1452f42f926ec3886d3688352472f960"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3dec035cce31cf17473f915dade1ca25" id="r_ga3dec035cce31cf17473f915dade1ca25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___exported__macros.html#ga3dec035cce31cf17473f915dade1ca25">FMC_IRQHandler</a>   FSMC_IRQHandler</td></tr>
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<tr class="separator:ga3dec035cce31cf17473f915dade1ca25"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="typedef-members" name="typedef-members"></a>
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Typedefs</h2></td></tr>
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<tr class="memitem:ga304d35aeeebef1445af976d8a5248d57" id="r_ga304d35aeeebef1445af976d8a5248d57"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct__memory.html">_memory</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#ga304d35aeeebef1445af976d8a5248d57">MCU_MemoryTypeDef</a></td></tr>
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<tr class="separator:ga304d35aeeebef1445af976d8a5248d57"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a>
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Enumerations</h2></td></tr>
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<tr class="memitem:ga7e1129cd8a196f4284d41db3e82ad5c8" id="r_ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> { <br />
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  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a> = -14
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, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa">MemoryManagement_IRQn</a> = -12
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, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af">BusFault_IRQn</a> = -11
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, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf">UsageFault_IRQn</a> = -10
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, <br />
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  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a> = -5
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c">DebugMonitor_IRQn</a> = -4
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a> = -2
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a> = -1
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a971089d7566ef902dfa0c80ac3a8fd52">WWDG_IRQn</a> = 0
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab0b51ffcc4dcf5661141b79c8e5bd924">PVD_IRQn</a> = 1
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac127cca7ae48bcf93924209f04e5e5a1">TAMP_STAMP_IRQn</a> = 2
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a173ccc3f31df1f7e43de2ddeab3d1777">RTC_WKUP_IRQn</a> = 3
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a91b73963ce243a1d031576d49e137fab">FLASH_IRQn</a> = 4
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5710b22392997bac63daa5c999730f77">RCC_IRQn</a> = 5
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6aa6f87d26bbc6cf99b067b8d75c2f7">EXTI0_IRQn</a> = 6
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae4badcdecdb94eb10129c4c0577c5e19">EXTI1_IRQn</a> = 7
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a082cb3f7839069a0715fd76c7eacbbc9">EXTI2_IRQn</a> = 8
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8add889c84ba5de466ced209069e05d602">EXTI3_IRQn</a> = 9
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab70a40106ca4486770df5d2072d9ac0e">EXTI4_IRQn</a> = 10
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ee33e72512c4cfb301b216f4fb9d68c">DMA1_Stream0_IRQn</a> = 11
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa45ca2c955060e2c2a7cbbe1d6753285">DMA1_Stream1_IRQn</a> = 12
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0d9ec75e4478e70235b705d5a6b3efd8">DMA1_Stream2_IRQn</a> = 13
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af77770e080206a7558decf09344fb2e2">DMA1_Stream3_IRQn</a> = 14
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aee2aaf365c6c297a63cee41ecae2301a">DMA1_Stream4_IRQn</a> = 15
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac92efa72399fe58fa615d8bf8fd64a4e">DMA1_Stream5_IRQn</a> = 16
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aef5e2b68f62f6f1781fab894f0b8f486">DMA1_Stream6_IRQn</a> = 17
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4d69175258ae261dd545001e810421b3">ADC_IRQn</a> = 18
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ceb5175f7c10cf436955173c2246877">CAN1_TX_IRQn</a> = 19
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6bf73ac43a9856b3f2759a59f3d25b5">CAN1_RX0_IRQn</a> = 20
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af71ef06c4f9ff0e1691c21ff3670acd4">CAN1_RX1_IRQn</a> = 21
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0f5f129d88a5606a378811e43039e274">CAN1_SCE_IRQn</a> = 22
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3aa50e0353871985facf62d055faa52">EXTI9_5_IRQn</a> = 23
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab35b4ce63cfb11453f84a3695c6df368">TIM1_BRK_TIM9_IRQn</a> = 24
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3879e49013035601e17f83a51e0829f">TIM1_UP_TIM10_IRQn</a> = 25
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a744bdceb8eface6ff57dd036e608e">TIM1_TRG_COM_TIM11_IRQn</a> = 26
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af312f0a21f600f9b286427e50c549ca9">TIM1_CC_IRQn</a> = 27
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3a4e2095a926e4095d3c846eb1c98afa">TIM2_IRQn</a> = 28
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a985574288f66e2a00e97387424a9a2d8">TIM3_IRQn</a> = 29
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a368b899ca740b9ae0d75841f3abf68c4">TIM4_IRQn</a> = 30
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9852dbbe8c014e716ce7e03a7b809751">I2C1_EV_IRQn</a> = 31
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a2ec363869f4488782dc10a60abce3b34">I2C1_ER_IRQn</a> = 32
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3020193786527c47d2e4d8c92ceee804">I2C2_EV_IRQn</a> = 33
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60c35f2d48d512bd6818bc9fef7053d7">I2C2_ER_IRQn</a> = 34
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aacdff1a9c42582ed663214cbe62c1174">SPI1_IRQn</a> = 35
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a505fbd4ccf7c2a14c8b76dc9e58f7ede">SPI2_IRQn</a> = 36
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad97cb163e1f678367e37c50d54d161ab">USART1_IRQn</a> = 37
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3f9c48714d0e5baaba6613343f0da68e">USART2_IRQn</a> = 38
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afb13802afc1f5fdf5c90e73ee99e5ff3">USART3_IRQn</a> = 39
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9fb0ad0c850234d1983fafdb17378e2f">EXTI15_10_IRQn</a> = 40
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afe09d6563a21a1540f658163a76a3b37">RTC_Alarm_IRQn</a> = 41
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa612f35c4440359c35acbaa3c1458c5f">OTG_FS_WKUP_IRQn</a> = 42
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3e01328006d19f7d32354271b9f61dce">TIM8_BRK_TIM12_IRQn</a> = 43
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa8d8f67a98f24de6f0b36ad6b1f29a7d">TIM8_UP_TIM13_IRQn</a> = 44
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae252b31c3a341acbe9a467e243137307">TIM8_TRG_COM_TIM14_IRQn</a> = 45
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a637750639eff4e2b4aae80ed6f3cf67f">TIM8_CC_IRQn</a> = 46
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aedaa9c14e7e5fa9c0dcbb0c2455546e8">DMA1_Stream7_IRQn</a> = 47
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a70450df88125476d5771f2ff3f562536">FSMC_IRQn</a> = 48
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a16fe70a39348f3f27906dc268b5654e3">SDIO_IRQn</a> = 49
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aed2eb3f4bb721d55fcc1003125956645">TIM5_IRQn</a> = 50
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4e9331739fb76a2ca7781fede070ae44">SPI3_IRQn</a> = 51
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aded5314b20c6e4e80cb6ab0668ffb8d5">UART4_IRQn</a> = 52
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac55a11a64aae7432544d0ab0d4f7de09">UART5_IRQn</a> = 53
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5f581e9aedfaccd9b1db9ec793804b45">TIM6_DAC_IRQn</a> = 54
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a53cadc1e164ec85d0ea4cd143608e8e1">TIM7_IRQn</a> = 55
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1e5055722630fd4b12aff421964c2ebb">DMA2_Stream0_IRQn</a> = 56
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a98abb3f02c1feb3831706bc1b82307cb">DMA2_Stream1_IRQn</a> = 57
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8abf5e189f3ac7aad9f65e65ea5a0f3b36">DMA2_Stream2_IRQn</a> = 58
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3ff8f3439f509e6e985eb960e63e1be4">DMA2_Stream3_IRQn</a> = 59
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae54eb8b30273b38a0576f75aba24eec0">DMA2_Stream4_IRQn</a> = 60
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad71328dd95461b7c55b568cf25966f6a">ETH_IRQn</a> = 61
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0485578005e12c2e2c0fb253a844ec6f">ETH_WKUP_IRQn</a> = 62
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af6b8fbc990ac71c8425647bb684788a4">CAN2_TX_IRQn</a> = 63
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a851fd2f2ab1418710e7da80e1bdf348a">CAN2_RX0_IRQn</a> = 64
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab5023ff845be31a488ab63a0b8cf2b7a">CAN2_RX1_IRQn</a> = 65
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a56c0b5758f26f31494e74aab9273f9fd">CAN2_SCE_IRQn</a> = 66
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa60a30b7ef03446a46fd72e084911f7e">OTG_FS_IRQn</a> = 67
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a933d4686213973abc01845a3da1c8a03">DMA2_Stream5_IRQn</a> = 68
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a21570761ad0b5ed751adc831691b7800">DMA2_Stream6_IRQn</a> = 69
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3d4cc0cd9b4d71e7ee002c4f8c1f8a77">DMA2_Stream7_IRQn</a> = 70
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa92bcb2bc3a87be869f05c5b07f04b8c">USART6_IRQn</a> = 71
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8326db2d570cb865ffa1d49fa29d562a">I2C3_EV_IRQn</a> = 72
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6e954232d164a6942ebc7a6bd6f7736e">I2C3_ER_IRQn</a> = 73
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60b6cc4b6dbeca39e29a475d26c9e080">OTG_HS_EP1_OUT_IRQn</a> = 74
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1b040a7f76278a73cf5ea4c51f1be047">OTG_HS_EP1_IN_IRQn</a> = 75
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9e5c9d81dd3985a88094f8158c0f0267">OTG_HS_WKUP_IRQn</a> = 76
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aad2d5e47d27fe3a02f7059b20bb729c0">OTG_HS_IRQn</a> = 77
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ace3c0fc2c4d05a7c02e3c987da5bc8e8">DCMI_IRQn</a> = 78
|
|
, <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a90c4647e57cff99fac635c532802c4b5">RNG_IRQn</a> = 80
|
|
, <br />
|
|
  <a class="el" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa6b8ff01b016a798c6e639728c179e4f">FPU_IRQn</a> = 81
|
|
<br />
|
|
}</td></tr>
|
|
<tr class="memdesc:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="mdescLeft"> </td><td class="mdescRight">STM32F4XX Interrupt Number Definition, according to the selected device in <a class="el" href="group___library__configuration__section.html">Library_configuration_section</a>. <a href="group___peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">More...</a><br /></td></tr>
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<tr class="separator:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a>
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Variables</h2></td></tr>
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<tr class="memitem:gaf157a51d290d1383d493a6a2fe0241fc" id="r_gaf157a51d290d1383d493a6a2fe0241fc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___peripheral__memory__map.html#ga304d35aeeebef1445af976d8a5248d57">MCU_MemoryTypeDef</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc">MCU_MEM</a></td></tr>
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<tr class="separator:gaf157a51d290d1383d493a6a2fe0241fc"><td class="memSeparator" colspan="2"> </td></tr>
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