Razvalyaev/matlab_stm_emulate
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через дефайн убран поток приложения мк

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Razvalyaev
2025-03-31 16:29:01 +03:00
parent 87c9cd01ff
commit f856b33e1c
5 changed files with 60 additions and 26 deletions
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32
MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c
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@@ -40,7 +40,6 @@ void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation
break;
// включение слейв таймера по ивенту
case(TIM_SLAVEMODE_TRIGGER): // SLAVE MODE: TRIGGER MODE
Slave_Mode_Check_Source(TIMx, TIMS);
@@ -83,17 +82,34 @@ void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
if ((TIMx->CR1 & TIM_CR1_UDIS) == 0) // UPDATE enable
{
if ((TIMx->CR1 & TIM_CR1_ARPE) == 0) TIMS->RELOAD = TIMx->ARR; // PRELOAD disable - update ARR every itteration
if (TIMS->tx_cnt > TIMS->RELOAD || TIMS->tx_cnt < 0) // OVERFLOW
{
TIMS->RELOAD = TIMx->ARR; // RELOAD ARR
if (TIMS->tx_cnt > TIMx->ARR) // reset COUNTER
TIMS->tx_cnt = 0;
else if (TIMS->tx_cnt < 0)
TIMS->tx_cnt = TIMx->ARR;
switch (TIMx->CR1 & TIM_CR1_CMS)
{
case TIM_COUNTERMODE_CENTERALIGNED1:
case TIM_COUNTERMODE_CENTERALIGNED2:
case TIM_COUNTERMODE_CENTERALIGNED3:
TIMx->CR1 ^= TIM_CR1_DIR;
if(TIMx->DIER & TIM_DIER_UIE) // if update interrupt enable
call_IRQHandller(TIMx); // call HANDLER
if (TIMx->DIER & TIM_DIER_UIE) // if update interrupt enable
call_IRQHandller(TIMx); // call HANDLER
break;
// default counting
default:
TIMS->RELOAD = TIMx->ARR; // RELOAD ARR
if (TIMS->tx_cnt > TIMx->ARR) // reset COUNTER
TIMS->tx_cnt = 0;
else if (TIMS->tx_cnt < 0)
TIMS->tx_cnt = TIMx->ARR;
if (TIMx->DIER & TIM_DIER_UIE) // if update interrupt enable
call_IRQHandller(TIMx); // call HANDLER
break;
}
}
}
}