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@@ -1,13 +1,23 @@
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/**
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**************************************************************************
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* @file arm_defines.h
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* @brief Çàãîëîâî÷íûé ôàéë ïîðòèðóþùèé ARM äåôàéíû.
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**************************************************************************
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@details
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Äàííûé ôàéë ïåðåîïðåäåëÿåò ARM äåôàéíû òàê, ÷òîáû îíè êîìïèëèðîâàëèñü
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MSVC. Äåôàéíû ïðåäñòàâëÿþò ñîáîé èëè çàãëóøêó èëè çàìåíåíû âûðàæåíèåì
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ñ àíàëîãè÷íûì ARM êîìïèëÿòîðó ôóíêöèîíàëîì.
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**************************************************************************/
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#define __disable_irq()
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/* CMSIS compiler specific defines */
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __inline
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#define __inline inline
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#endif
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@@ -31,11 +41,13 @@
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#define __USED __attribute__((used))
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#endif
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#ifndef __WEAK
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#define __WEAK __declspec(selectany)
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// #define __weak __WEAK
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#endif
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#ifndef __weak
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#define __weak
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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@@ -76,21 +88,8 @@
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#ifndef __RESTRICT
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#define __RESTRICT __restrict
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#endif
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#ifndef __weak
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#define __weak
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#endif
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//#define __ASM()
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//#define __DSB()
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//#define __ISB()
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//#define __NOP()
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//#define __WFI()
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//#define __SEV()
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//#define __WFE()
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//#define __DMB()
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/* ########################## Core Instruction Access ######################### */
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/**
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\brief No Operation
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\details No Operation does nothing. This instruction can be used for code alignment purposes.
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@@ -1,10 +1,18 @@
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/************************************************************************
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/**
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**************************************************************************
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* @file core_cm4_matlab.h
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* @brief Заголовочный файл ядра Core CM4 для MATLAB.
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**************************************************************************
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@details
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Данный файл является копией core_cm4.h, только первые ~160 строк, которые
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определяют компилятор АРМ, удалены.
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МАТЛАБ компилирует через код через комплилятор MSVC для блока S-Function
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Также добавлена структура имитирующая память ядра (~1360)
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Также добавлена инклюд с имитирацией памяти ядра (~10)
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**************************************************************************/
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#ifndef __CMSIS_GENERIC
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#include "stm32f407xx_matlab_memory.h"
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/* IO definitions (access restrictions to peripheral registers) */
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/**
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\defgroup CMSIS_glob_defs CMSIS Global Defines
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@@ -1344,52 +1352,7 @@ typedef struct
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/*@} end of group CMSIS_core_bitfield */
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/**
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\ingroup CMSIS_core_register
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\defgroup CMSIS_core_base Core Definitions
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\brief Definitions for base addresses, unions, and structures.
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@{
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*/
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/* Memory mapping of Core Hardware */
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#define SCS_BASE_SHIFT (0x0000E000UL) /*!< System Control Space Base Address */
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#define ITM_BASE_SHIFT (0x00000000UL) /*!< ITM Base Address */
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#define DWT_BASE_SHIFT (0x00001000UL) /*!< DWT Base Address */
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#define TPI_BASE_SHIFT (0x00040000UL) /*!< TPI Base Address */
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#define CoreDebug_BASE_SHIFT (0x0000EDF0UL) /*!< Core Debug Base Address */
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typedef struct _cortex_memory
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{
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uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000];
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}MCU_CortexMemoryTypeDef;
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extern MCU_CortexMemoryTypeDef MCU_CORTEX_MEM;
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#define SCS_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< System Control Space Base Address */
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#define ITM_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< ITM Base Address */
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#define DWT_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< DWT Base Address */
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#define TPI_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< TPI Base Address */
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#define CoreDebug_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< Core Debug Base Address */
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#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
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#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
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#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
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#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
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#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
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#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
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#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
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#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
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#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
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#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
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#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
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#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
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#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
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#endif
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#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
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#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
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/*@} */
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/*@} */
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@@ -1,37 +1,20 @@
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/************************************************************************
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/**
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**************************************************************************
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* @file stm32f4xx_matlab.h
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* @brief Заголовочный файл для работы с STM32F4xx в MATLAB.
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**************************************************************************
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@details
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Данный файл является копией stm32f407xx.h с некоторыми изменениями:
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- добавлен кейловский stdint.h (через "", вместо <>) (~170)
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- добавлен cmsis_armcc_matlab.h с дефайнами из оригинального cmsis_armcc.h (~170)
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- добавлен core_cm4.h с дефайнами из оригинального core_cm4.h (~170)
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- добавлена структура имитирующая память МК (для работы дефайнов адресов регистров) (~950)
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(надо допилить)
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Необходимо допилить поддержку всех дефайнов, которые объявляются в
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arm_acle.h, arm_compat.h, cmsis_armclang.h, cmsis_compiler.h, cmsis_version.h,
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core_cm4.h, mpu_armv7.h, stddef
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**************************************************************************/
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/**
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******************************************************************************
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* @file stm32f407xx.h
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* @author MCD Application Team
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* @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
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*
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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* - peripherals registers declarations and bits definition
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* - Macros to access peripheral’s registers hardware
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS_Device
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* @{
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@@ -912,84 +895,9 @@ typedef struct
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* @}
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*/
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/** @addtogroup Peripheral_memory_map
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* @{
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*/
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#define FLASH_BASE_SHIFT 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
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#define FLASH_END_SHIFT 0x080FFFFFUL /*!< FLASH end address */
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#define CCMDATARAM_BASE_SHIFT 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
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#define CCMDATARAM_END_SHIFT 0x1000FFFFUL /*!< CCM data RAM end address */
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#define FLASH_OTP_BASE_SHIFT 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
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#define FLASH_OTP_END_SHIFT 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
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#define SRAM1_BASE_SHIFT 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */
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#define SRAM2_BASE_SHIFT 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */
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#define SRAM1_BB_BASE_SHIFT 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */
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#define SRAM2_BB_BASE_SHIFT 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */
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#define PERIPH_BASE_SHIFT 0x40000000UL /*!< Peripheral base address in the alias region */
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#define BKPSRAM_BASE_SHIFT 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */
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#define PERIPH_BB_BASE_SHIFT 0x42000000UL /*!< Peripheral base address in the bit-band region */
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#define BKPSRAM_BB_BASE_SHIFT 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */
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#define FSMC_R_BASE_SHIFT 0xA0000000UL /*!< FSMC registers base address */
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#define MCU_MEM_END 0xA0000FFFUL /*!< CCM data RAM end address */
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#define CCMDATARAM_SIZE 0x10000UL /* (64 KB) */
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#define SRAM1_SIZE 0x1C000UL /* (112 KB) */
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#define SRAM2_SIZE 0x4000UL /* (16 KB) */
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#define BKPSRAM_SIZE 0x1000UL /* (4 KB) */
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#define FLASH_SIZE (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT)
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//#define CCMDATARAM_SIZE (FLASH_OTP_BASE_SHIFT - CCMDATARAM_BASE_SHIFT)
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#define FLASH_OTP_SIZE (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT)
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//#define SRAM1_SIZE (SRAM2_BASE_SHIFT - SRAM1_BASE_SHIFT)
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//#define SRAM2_SIZE (SRAM1_BB_BASE_SHIFT - SRAM2_BASE_SHIFT)
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#define SRAM1_BB_SIZE (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT)
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#define SRAM2_BB_SIZE (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT)
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#define PERIPH_SIZE (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT)
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//#define BKPSRAM_SIZE (PERIPH_BB_BASE_SHIFT - BKPSRAM_BASE_SHIFT)
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#define PERIPH_BB_SIZE (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT)
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//#define BKPSRAM_BB_SIZE (FSMC_R_BASE_SHIFT - BKPSRAM_BB_BASE_SHIFT)
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#define FSMC_R_SIZE (MCU_MEM_END - FSMC_R_BASE_SHIFT)
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typedef struct _memory
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{
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//uint8_t RESERVED[FLASH_BASE_SHIFT];
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uint8_t FLASH_BASE[FLASH_SIZE];
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uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE];
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uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE];
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uint8_t SRAM1_BASE[SRAM1_SIZE];
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uint8_t SRAM2_BASE[SRAM2_SIZE];
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uint8_t SRAM1_BB_BASE[SRAM1_SIZE];
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uint8_t SRAM2_BB_BASE[SRAM2_SIZE];
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uint8_t PERIPH_BASE[PERIPH_SIZE];
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uint8_t BKPSRAM_BASE[BKPSRAM_SIZE];
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uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE];
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uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE];
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uint8_t FSMC_R_BASE[FSMC_R_SIZE];
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}MCU_MemoryTypeDef;
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extern MCU_MemoryTypeDef MCU_MEM;
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DBGMCU_TypeDef DEBUG_MCU;
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/** @addtogroup Peripheral_memory_map
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* @{
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*/
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#define FLASH_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< FLASH(up to 1 MB) base address in the alias region */
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#define CCMDATARAM_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
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#define SRAM1_BASE (MCU_MEM.SRAM1_BASE) /*!< SRAM1(112 KB) base address in the alias region */
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#define SRAM2_BASE (MCU_MEM.SRAM2_BASE) /*!< SRAM2(16 KB) base address in the alias region */
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#define PERIPH_BASE (MCU_MEM.PERIPH_BASE) /*!< Peripheral base address in the alias region */
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#define BKPSRAM_BASE (MCU_MEM.BKPSRAM_BASE) /*!< Backup SRAM(4 KB) base address in the alias region */
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#define FSMC_R_BASE (MCU_MEM.FSMC_R_BASE) /*!< FSMC registers base address */
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#define SRAM1_BB_BASE (MCU_MEM.SRAM1_BB_BASE) /*!< SRAM1(112 KB) base address in the bit-band region */
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#define SRAM2_BB_BASE (MCU_MEM.SRAM2_BB_BASE) /*!< SRAM2(16 KB) base address in the bit-band region */
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#define PERIPH_BB_BASE (MCU_MEM.PERIPH_BB_BASE) /*!< Peripheral base address in the bit-band region */
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#define BKPSRAM_BB_BASE (MCU_MEM.BKPSRAM_BB_BASE) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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#define FLASH_END (MCU_MEM.FLASH_END) /*!< FLASH end address */
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#define FLASH_OTP_BASE (MCU_MEM.FLASH_OTP_BASE) /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
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#define FLASH_OTP_END (MCU_MEM.FLASH_OTP_END) /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
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#define CCMDATARAM_END (MCU_MEM.CCMDATARAM_END) /*!< CCM data RAM end address */
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/* Legacy defines */
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#define SRAM_BASE SRAM1_BASE
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@@ -1097,8 +1005,6 @@ DBGMCU_TypeDef DEBUG_MCU;
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#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL)
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/*!< Debug MCU registers base address */
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#define DBGMCU_BASE (&DEBUG_MCU)
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/*!< USB registers base address */
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#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
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#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
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146
MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab_memory.h
Normal file
146
MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab_memory.h
Normal file
@@ -0,0 +1,146 @@
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/**
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**************************************************************************
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* @file stm32f407xx_matlab_memory.h
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* @brief Заголовочный файл для определения памяти МК STM32F4xx.
|
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**************************************************************************
|
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@details
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В данном файле переопределяются дефайны памяти STM32 таким образом, чтобы
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к ним можно было обратиться в MATLAB.
|
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Конкретно, создается структуруа имитирующая память, и далее дефайны определяются
|
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так, чтобы обращаться к этой структуре, а не по абсолютному адресу.
|
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**************************************************************************/
|
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/**
|
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\defgroup CMSIS_core_base Core Definitions
|
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\brief Definitions for base addresses, unions, and structures.
|
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@{
|
||||
*/
|
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|
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/* Memory mapping of Core Hardware */
|
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#define SCS_BASE_SHIFT (0x0000E000UL) /*!< System Control Space Base Address */
|
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#define ITM_BASE_SHIFT (0x00000000UL) /*!< ITM Base Address */
|
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#define DWT_BASE_SHIFT (0x00001000UL) /*!< DWT Base Address */
|
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#define TPI_BASE_SHIFT (0x00040000UL) /*!< TPI Base Address */
|
||||
#define CoreDebug_BASE_SHIFT (0x0000EDF0UL) /*!< Core Debug Base Address */
|
||||
|
||||
typedef struct _cortex_memory
|
||||
{
|
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uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000];
|
||||
}MCU_CortexMemoryTypeDef;
|
||||
extern MCU_CortexMemoryTypeDef MCU_CORTEX_MEM;
|
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|
||||
#define SCS_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< System Control Space Base Address */
|
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#define ITM_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< ITM Base Address */
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#define DWT_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< DWT Base Address */
|
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#define TPI_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< TPI Base Address */
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#define CoreDebug_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< Core Debug Base Address */
|
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#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
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#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
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#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
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#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
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#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
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#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
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#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
|
||||
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
||||
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @ingroup CMSIS_core_base
|
||||
* @addtogroup Peripheral_memory_map Peripheral Memory Map
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_BASE_SHIFT 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
|
||||
#define FLASH_END_SHIFT 0x080FFFFFUL /*!< FLASH end address */
|
||||
#define CCMDATARAM_BASE_SHIFT 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
|
||||
#define CCMDATARAM_END_SHIFT 0x1000FFFFUL /*!< CCM data RAM end address */
|
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#define FLASH_OTP_BASE_SHIFT 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
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#define FLASH_OTP_END_SHIFT 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
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#define SRAM1_BASE_SHIFT 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */
|
||||
#define SRAM2_BASE_SHIFT 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */
|
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#define SRAM1_BB_BASE_SHIFT 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */
|
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#define SRAM2_BB_BASE_SHIFT 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */
|
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#define PERIPH_BASE_SHIFT 0x40000000UL /*!< Peripheral base address in the alias region */
|
||||
#define BKPSRAM_BASE_SHIFT 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */
|
||||
#define PERIPH_BB_BASE_SHIFT 0x42000000UL /*!< Peripheral base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE_SHIFT 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define FSMC_R_BASE_SHIFT 0xA0000000UL /*!< FSMC registers base address */
|
||||
|
||||
#define MCU_MEM_END 0xA0000FFFUL /*!< CCM data RAM end address */
|
||||
|
||||
#define CCMDATARAM_SIZE 0x10000UL /* (64 KB) */
|
||||
#define SRAM1_SIZE 0x1C000UL /* (112 KB) */
|
||||
#define SRAM2_SIZE 0x4000UL /* (16 KB) */
|
||||
#define BKPSRAM_SIZE 0x1000UL /* (4 KB) */
|
||||
|
||||
#define FLASH_SIZE (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT)
|
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//#define CCMDATARAM_SIZE (FLASH_OTP_BASE_SHIFT - CCMDATARAM_BASE_SHIFT)
|
||||
#define FLASH_OTP_SIZE (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT)
|
||||
//#define SRAM1_SIZE (SRAM2_BASE_SHIFT - SRAM1_BASE_SHIFT)
|
||||
//#define SRAM2_SIZE (SRAM1_BB_BASE_SHIFT - SRAM2_BASE_SHIFT)
|
||||
#define SRAM1_BB_SIZE (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT)
|
||||
#define SRAM2_BB_SIZE (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT)
|
||||
#define PERIPH_SIZE (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT)
|
||||
//#define BKPSRAM_SIZE (PERIPH_BB_BASE_SHIFT - BKPSRAM_BASE_SHIFT)
|
||||
#define PERIPH_BB_SIZE (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT)
|
||||
//#define BKPSRAM_BB_SIZE (FSMC_R_BASE_SHIFT - BKPSRAM_BB_BASE_SHIFT)
|
||||
#define FSMC_R_SIZE (MCU_MEM_END - FSMC_R_BASE_SHIFT)
|
||||
#define DEBUG_MCU_SIZE (2)
|
||||
|
||||
|
||||
typedef struct _memory
|
||||
{
|
||||
//uint8_t RESERVED[FLASH_BASE_SHIFT];
|
||||
|
||||
uint8_t FLASH_BASE[FLASH_SIZE];
|
||||
uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE];
|
||||
uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE];
|
||||
uint8_t SRAM1_BASE[SRAM1_SIZE];
|
||||
uint8_t SRAM2_BASE[SRAM2_SIZE];
|
||||
uint8_t SRAM1_BB_BASE[SRAM1_SIZE];
|
||||
uint8_t SRAM2_BB_BASE[SRAM2_SIZE];
|
||||
uint8_t PERIPH_BASE[PERIPH_SIZE];
|
||||
uint8_t BKPSRAM_BASE[BKPSRAM_SIZE];
|
||||
uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE];
|
||||
uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE];
|
||||
uint8_t FSMC_R_BASE[FSMC_R_SIZE];
|
||||
uint8_t DEBUG_MCU_BASE[DEBUG_MCU_SIZE];
|
||||
}MCU_MemoryTypeDef;
|
||||
extern MCU_MemoryTypeDef MCU_MEM;
|
||||
|
||||
#define FLASH_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< FLASH(up to 1 MB) base address in the alias region */
|
||||
#define CCMDATARAM_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
|
||||
#define SRAM1_BASE (MCU_MEM.SRAM1_BASE) /*!< SRAM1(112 KB) base address in the alias region */
|
||||
#define SRAM2_BASE (MCU_MEM.SRAM2_BASE) /*!< SRAM2(16 KB) base address in the alias region */
|
||||
#define PERIPH_BASE (MCU_MEM.PERIPH_BASE) /*!< Peripheral base address in the alias region */
|
||||
#define BKPSRAM_BASE (MCU_MEM.BKPSRAM_BASE) /*!< Backup SRAM(4 KB) base address in the alias region */
|
||||
#define FSMC_R_BASE (MCU_MEM.FSMC_R_BASE) /*!< FSMC registers base address */
|
||||
#define SRAM1_BB_BASE (MCU_MEM.SRAM1_BB_BASE) /*!< SRAM1(112 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE (MCU_MEM.SRAM2_BB_BASE) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE (MCU_MEM.PERIPH_BB_BASE) /*!< Peripheral base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE (MCU_MEM.BKPSRAM_BB_BASE) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define FLASH_END (MCU_MEM.FLASH_END) /*!< FLASH end address */
|
||||
#define FLASH_OTP_BASE (MCU_MEM.FLASH_OTP_BASE) /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
|
||||
#define FLASH_OTP_END (MCU_MEM.FLASH_OTP_END) /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
|
||||
#define CCMDATARAM_END (MCU_MEM.CCMDATARAM_END) /*!< CCM data RAM end address */
|
||||
|
||||
/*!< Debug MCU registers base address */
|
||||
#define DBGMCU_BASE (MCU_MEM.DEBUG_MCU_BASE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
Reference in New Issue
Block a user