Симуляция генерации синусоидального шим и управление по модбас
note: - модбас не моделируется, в s-function просто передаются константы режимов. - лишние файлы убраны в outdate. - два канала одной фазы переключаются немного криво: на один такт симуляции проскакивает высокий уровень предыдущего канала и только потом включается текущий канал
This commit is contained in:
alexey
@@ -0,0 +1,36 @@
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#include "stm32f1xx_matlab_gpio.h"
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void GPIO_to_SFUNC(real_T *disc)
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{
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for (int i = 0; i < PORT_WIDTH; i++)
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{
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if (GPIOA->ODR & (1 << i))
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{
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disc[i] = 1;
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}
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if (GPIOB->ODR & (1 << i))
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{
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disc[PORT_WIDTH + i] = 1;
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}
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}
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}
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void SFUNC_to_GPIO(real_T* in)
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{
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for (int i = 0; i < PORT_WIDTH; i++)
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{
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if (in[i] > 0.5)
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{
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GPIOA->IDR |= (1 << i);
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}
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else
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{
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GPIOA->IDR &= ~(1 << i);
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}
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}
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}
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@@ -0,0 +1,22 @@
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#ifndef _MATLAB_GPIO_H_
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#define _MATLAB_GPIO_H_
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#include "simstruc.h"
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#include "mcu_wrapper_conf.h"
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/* äåôàéíû äëÿ ïðîâåðêè êîíôèãóðàöèè GPIO) */
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#define GET_GPIO_CONF(_reg_, _pos_) ((_pos_ < 8)? \
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GET_BITS_FROM_REG(_reg_->CRL, GPIO_CRL_CNF0 << (_pos_<<2u), (_pos_<<2u)+GPIO_CRL_CNF0_Pos): \
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GET_BITS_FROM_REG(_reg_->CRH, GPIO_CRL_CNF0 << ((_pos_-8)<<2u), ((_pos_-8)<<2u)+GPIO_CRL_CNF0_Pos) )
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/* äåôàéíû äëÿ ïðîâåðêè ðåæèìà GPIO) */
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#define GET_GPIO_MODE(_reg_, _pos_) ((_pos_ < 8)? \
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GET_BITS_FROM_REG(_reg_->CRL, GPIO_CRL_MODE0 << (_pos_<<2u), (_pos_<<2u)+GPIO_CRL_MODE0_Pos): \
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GET_BITS_FROM_REG(_reg_->CRH, GPIO_CRL_MODE0 << ((_pos_-8)<<2u), ((_pos_-8)<<2u)+GPIO_CRL_MODE0_Pos) )
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void SFUNC_to_GPIO(real_T* disc);
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void GPIO_to_SFUNC(real_T* in);
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#endif // _MATLAB_GPIO_H_
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@@ -0,0 +1,36 @@
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#ifndef _MATLAB_RCC_H_
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#define _MATLAB_RCC_H_
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#include "mcu_wrapper_conf.h"
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//#define SYSLCK_Value ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)
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//#define AHB_Prescaler ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)
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//#define AHB_Prescaler ((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)
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#define HCLK_Value (double)72000000;
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#define ABP1_Value (double)36000000;
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#define ABP1_TIMS_Value (double)72000000;
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#define ABP2_Value (double)72000000;
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#define ABP2_TIMS_Value (double)72000000;
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/* Ýòè äåôàéíû äîáàâëåíû â êîä stm32f4xx_hal_rcc.c, ÷òîáû íå ïîïàñòü â áåñêîíå÷íûé öèêë */
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/* Ìá ïåðåíåñòè â MCU_Periph_Simulation(), íî ÷åò íå õî÷åòñÿ íàãðóæàòü ñèìóëÿöèþ ýòîé õåðíåé*/
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#define _RCC_SET_FLAG(__FLAG__) \
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if(((__FLAG__) >> 5U) == 1U) RCC->CR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
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else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
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else if(((__FLAG__) >> 5U) == 3U) RCC->CSR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
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#define _RCC_CLEAR_FLAG(__FLAG__) \
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if(((__FLAG__) >> 5U) == 1U) RCC->CR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
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else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
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else if(((__FLAG__) >> 5U) == 3U) RCC->CSR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
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#define Set_Flag_If_Its_Expected(_flag_, _condition_) \
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if(_condition_) _RCC_CLEAR_FLAG(_flag_)
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#define Clear_Flag_If_Its_Expected(_flag_, _condition_) \
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if(_condition_) _RCC_SET_FLAG(_flag_)
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#endif // _MATLAB_RCC_H_
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@@ -0,0 +1,612 @@
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/**************************************************************************
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Данный файл содержит функции для симуляции таймеров STM32F407xx.
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**************************************************************************/
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#include "stm32f1xx_matlab_tim.h"
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struct SlaveChannels Slave_Channels; // структура для связи и синхронизации таймеров
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//----------------------TIMER BASE FUNCTIONS-----------------------//
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/* Базовая функция для симуляции таймера: она вызывается каждый шаг симуляции */
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void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
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{
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Overflow_Check(TIMx, TIMS);
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// Выбор режима работы таймера
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switch (TIMx->SMCR & TIM_SMCR_SMS) // TIMER MODE
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{
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// обычный счет
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case(TIM_SLAVEMODE_DISABLE):// NORMAL MODE counting
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TIMx_Count(TIMx, TIMS);
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Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation
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break;
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// включение слейв таймера по ивенту
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case(TIM_SLAVEMODE_TRIGGER): // SLAVE MODE: TRIGGER MODE
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Slave_Mode_Check_Source(TIMx, TIMS);
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TIMx_Count(TIMx, TIMS);
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Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation
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break;
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}
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}
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/* Счет таймера за один такт */
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void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
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{
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if ((TIMx->CR1 & TIM_CR1_DIR) && TIMx->CR1) // up COUNTER and COUNTER ENABLE
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TIMS->tx_cnt -= TIMS->tx_step / (TIMx->PSC + 1);
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else if (((TIMx->CR1 & TIM_CR1_DIR) == 0) && TIMx->CR1) // down COUNTER and COUNTER ENABLE
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TIMS->tx_cnt += TIMS->tx_step / (TIMx->PSC + 1);
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TIMx->CNT = (uint32_t)TIMS->tx_cnt;
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}
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/* Проверка на переполнение и дальнейшая его обработка */
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void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
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{
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// Переполнение таймера: сброс таймера и вызов прерывания
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if ((TIMx->CR1 & TIM_CR1_UDIS) == 0) // UPDATE enable
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{
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if ((TIMx->CR1 & TIM_CR1_ARPE) == 0) TIMS->RELOAD = TIMx->ARR; // PRELOAD disable - update ARR every itteration
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if (TIMS->tx_cnt > TIMS->RELOAD || TIMS->tx_cnt < 0) // OVERFLOW
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{
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TIMS->RELOAD = TIMx->ARR; // RELOAD ARR
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if (TIMS->tx_cnt > TIMx->ARR) // reset COUNTER
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TIMS->tx_cnt -= TIMS->RELOAD+1;
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else if (TIMS->tx_cnt < 0)
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TIMS->tx_cnt += TIMS->RELOAD+1;
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call_IRQHandller(TIMx); // call HANDLER
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}
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}
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}
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//-----------------------------------------------------------------//
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//----------------------------CHANNELS-----------------------------//
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/* Симуляция каналов таймера */
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void Channels_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
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{
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CC_PWM_Ch1_Simulation(TIMx, TIMS);
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CC_PWM_Ch2_Simulation(TIMx, TIMS);
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CC_PWM_Ch3_Simulation(TIMx, TIMS);
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CC_PWM_Ch4_Simulation(TIMx, TIMS);
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Write_OC_to_GPIO(TIMx, TIMS);
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Write_OC_to_TRGO(TIMx, TIMS);
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}
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//-----------------CAPTURE COPMARE & PWM FUNCTIONS------------------//
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/* Выбор режима CaptureCompare или PWM и симуляция для каждого канала */
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void CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
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{ // определяет режим канала
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switch (TIMx->CCMR1 & TIM_CCMR1_OC1M)
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{
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case (TIM_OCMODE_ACTIVE): // ACTIVE mode
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if (abs(TIMx->CNT - TIMx->CCR1) < 2*TIMS->tx_step)
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TIMS->Channels.OC1REF = 1;
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break;
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case (TIM_OCMODE_INACTIVE): // INACTIVE mode
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if (abs(TIMx->CNT - TIMx->CCR1) < 2*TIMS->tx_step)
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TIMS->Channels.OC1REF = 0;
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break;
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case (TIM_OCMODE_TOGGLE): // TOOGLE mode
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if (abs(TIMx->CNT - TIMx->CCR1) < 2*TIMS->tx_step)
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TIMS->Channels.OC1REF = ~TIMS->Channels.OC1REF;
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break;
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case (TIM_OCMODE_PWM1): // PWM MODE 1 mode
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if (TIMx->CNT < TIMx->CCR1)
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TIMS->Channels.OC1REF = 1;
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else
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TIMS->Channels.OC1REF = 0;
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break;
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case (TIM_OCMODE_PWM2): // PWM MODE 2 mode
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if (TIMx->CNT < TIMx->CCR1)
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TIMS->Channels.OC1REF = 0;
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else
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TIMS->Channels.OC1REF = 1;
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break;
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case (TIM_OCMODE_FORCED_ACTIVE): // FORCED ACTIVE mode
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TIMS->Channels.OC1REF = 1; break;
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case (TIM_OCMODE_FORCED_INACTIVE): // FORCED INACTIVE mode
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TIMS->Channels.OC1REF = 0; break;
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}
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}
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void CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
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{ // определяет режим канала
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switch (TIMx->CCMR1 & TIM_CCMR1_OC2M)
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{
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case ((TIM_OCMODE_ACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // ACTIVE mode
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if (abs(TIMx->CNT - TIMx->CCR2) < 2*TIMS->tx_step)
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TIMS->Channels.OC2REF = 1;
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break;
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case ((TIM_OCMODE_INACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // INACTIVE mode
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if (abs(TIMx->CNT - TIMx->CCR2) < 2*TIMS->tx_step)
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TIMS->Channels.OC2REF = 0;
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break;
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case ((TIM_OCMODE_TOGGLE) << (TIM_OCMODE_SECOND_SHIFT)): // Toogle mode
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if (abs(TIMx->CNT - TIMx->CCR2) < 2*TIMS->tx_step)
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TIMS->Channels.OC2REF = ~TIMS->Channels.OC2REF;
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break;
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case ((TIM_OCMODE_PWM1) << (TIM_OCMODE_SECOND_SHIFT)): // PWM mode 1 mode
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if (TIMx->CNT < TIMx->CCR2)
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TIMS->Channels.OC2REF = 1;
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else
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TIMS->Channels.OC2REF = 0;
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break;
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case ((TIM_OCMODE_PWM2) << (TIM_OCMODE_SECOND_SHIFT)): // PWM mode 2 mode
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if (TIMx->CNT < TIMx->CCR2)
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TIMS->Channels.OC2REF = 0;
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else
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TIMS->Channels.OC2REF = 1;
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break;
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case ((TIM_OCMODE_FORCED_ACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // FORCED ACTIVE mode
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TIMS->Channels.OC2REF = 1; break;
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case ((TIM_OCMODE_FORCED_INACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // FORCED INACTIVE mode
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TIMS->Channels.OC2REF = 0; break;
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}
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}
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void CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
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{ // определяет режим канала
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switch (TIMx->CCMR2 & TIM_CCMR1_OC1M)
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{
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case (TIM_OCMODE_ACTIVE): // ACTIVE mode
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if (abs(TIMx->CNT - TIMx->CCR3) < 2*TIMS->tx_step)
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TIMS->Channels.OC3REF = 1;
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break;
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case (TIM_OCMODE_INACTIVE): // INACTIVE mode
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if (abs(TIMx->CNT - TIMx->CCR3) < 2*TIMS->tx_step)
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TIMS->Channels.OC3REF = 0;
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break;
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case (TIM_OCMODE_TOGGLE): // Toogle mode
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if (abs(TIMx->CNT - TIMx->CCR3) < 2*TIMS->tx_step)
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TIMS->Channels.OC3REF = ~TIMS->Channels.OC3REF;
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break;
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case (TIM_OCMODE_PWM1): // PWM mode 1 mode
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if (TIMx->CNT < TIMx->CCR3)
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TIMS->Channels.OC3REF = 1;
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else
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TIMS->Channels.OC3REF = 0;
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break;
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case (TIM_OCMODE_PWM2): // PWM mode 2 mode
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if (TIMx->CNT < TIMx->CCR3)
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TIMS->Channels.OC3REF = 0;
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else
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TIMS->Channels.OC3REF = 1;
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break;
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case (TIM_OCMODE_FORCED_ACTIVE): // FORCED ACTIVE mode
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TIMS->Channels.OC3REF = 1; break;
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case (TIM_OCMODE_FORCED_INACTIVE): // FORCED INACTIVE mode
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TIMS->Channels.OC3REF = 0; break;
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}
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}
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void CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
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{ // определяет режим канала
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switch (TIMx->CCMR1 & TIM_CCMR1_OC2M)
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{
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case ((TIM_OCMODE_ACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // ACTIVE mode
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if (abs(TIMx->CNT - TIMx->CCR4) < 2*TIMS->tx_step)
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TIMS->Channels.OC4REF = 1;
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break;
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case ((TIM_OCMODE_INACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // INACTIVE mode
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if (abs(TIMx->CNT - TIMx->CCR4) < 2*TIMS->tx_step)
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TIMS->Channels.OC4REF = 0;
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break;
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case ((TIM_OCMODE_TOGGLE) << (TIM_OCMODE_SECOND_SHIFT)): // Toogle mode
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if (abs(TIMx->CNT - TIMx->CCR4) < 2*TIMS->tx_step)
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TIMS->Channels.OC4REF = ~TIMS->Channels.OC4REF;
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break;
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case ((TIM_OCMODE_PWM1) << (TIM_OCMODE_SECOND_SHIFT)): // PWM mode 1 mode
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if (TIMx->CNT < TIMx->CCR4)
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TIMS->Channels.OC4REF = 1;
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else
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TIMS->Channels.OC4REF = 0;
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break;
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case ((TIM_OCMODE_PWM2) << (TIM_OCMODE_SECOND_SHIFT)): // PWM mode 2 mode
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if (TIMx->CNT < TIMx->CCR4)
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TIMS->Channels.OC4REF = 0;
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else
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TIMS->Channels.OC4REF = 1;
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break;
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case ((TIM_OCMODE_FORCED_ACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // FORCED ACTIVE mode
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TIMS->Channels.OC4REF = 1; break;
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case ((TIM_OCMODE_FORCED_INACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // FORCED INACTIVE mode
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TIMS->Channels.OC4REF = 0; break;
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}
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}
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/* Запись каналов таймера в порты GPIO */
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void Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
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{
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// write gpio pin if need
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if (Check_OC1_GPIO_Output(TIMS)) // check OC OUTPUT 4 enable (GPIO AF MODE)
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{
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uint32_t temp2 = ~(uint32_t)(1 << (TIMS->Channels.OC1_PIN_SHIFT));
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if (TIMx->CCER & TIM_CCER_CC1P) // POLARITY check
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{ // low POLARITY
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if (TIMS->Channels.OC1REF)
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TIMS->Channels.OC1_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC1_PIN_SHIFT));
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else
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TIMS->Channels.OC1_GPIOx->ODR |= 1 << (TIMS->Channels.OC1_PIN_SHIFT);
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}
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else
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{ // high POLARITY
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if (TIMS->Channels.OC1REF)
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TIMS->Channels.OC1_GPIOx->ODR |= 1 << (TIMS->Channels.OC1_PIN_SHIFT);
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else
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TIMS->Channels.OC1_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC1_PIN_SHIFT));
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}
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}
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if (Check_OC2_GPIO_Output(TIMS)) // check OC OUTPUT 4 enable (GPIO AF MODE)
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{
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if (TIMx->CCER & TIM_CCER_CC2P) // POLARITY check
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{ // low POLARITY
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if (TIMS->Channels.OC2REF)
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TIMS->Channels.OC2_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC2_PIN_SHIFT));
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else
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TIMS->Channels.OC2_GPIOx->ODR |= 1 << (TIMS->Channels.OC2_PIN_SHIFT);
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}
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else
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{ // high POLARITY
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if (TIMS->Channels.OC2REF)
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TIMS->Channels.OC2_GPIOx->ODR |= 1 << (TIMS->Channels.OC2_PIN_SHIFT);
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else
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TIMS->Channels.OC2_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC2_PIN_SHIFT));
|
||||
}
|
||||
}
|
||||
if (Check_OC3_GPIO_Output(TIMS)) // check OC OUTPUT 4 enable (GPIO AF MODE)
|
||||
{
|
||||
if (TIMx->CCER & TIM_CCER_CC3P) // POLARITY check
|
||||
{ // low POLARITY
|
||||
if (TIMS->Channels.OC3REF)
|
||||
TIMS->Channels.OC3_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC3_PIN_SHIFT));
|
||||
else
|
||||
TIMS->Channels.OC3_GPIOx->ODR |= 1 << (TIMS->Channels.OC3_PIN_SHIFT);
|
||||
}
|
||||
else
|
||||
{ // high POLARITY
|
||||
if (TIMS->Channels.OC3REF)
|
||||
TIMS->Channels.OC3_GPIOx->ODR |= 1 << (TIMS->Channels.OC3_PIN_SHIFT);
|
||||
else
|
||||
TIMS->Channels.OC3_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC3_PIN_SHIFT));
|
||||
}
|
||||
}
|
||||
if (Check_OC4_GPIO_Output(TIMS)) // check OC CHANNEL 4 enable (GPIO AF MODE)
|
||||
{
|
||||
if (TIMx->CCER & TIM_CCER_CC4P) // POLARITY check
|
||||
{ // low POLARITY
|
||||
if (TIMS->Channels.OC4REF)
|
||||
TIMS->Channels.OC4_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC4_PIN_SHIFT));
|
||||
else
|
||||
TIMS->Channels.OC4_GPIOx->ODR |= (1) << (TIMS->Channels.OC4_PIN_SHIFT);
|
||||
}
|
||||
else
|
||||
{ // high POLARITY
|
||||
if (TIMS->Channels.OC4REF)
|
||||
TIMS->Channels.OC4_GPIOx->ODR |= (1) << (TIMS->Channels.OC4_PIN_SHIFT);
|
||||
else
|
||||
TIMS->Channels.OC4_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC4_PIN_SHIFT));
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Запись результата compare в глабальную структуру с TRIGGER OUTPUT */
|
||||
void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
|
||||
{
|
||||
// write trigger output from OCxREF pin if need
|
||||
unsigned temp_trgo;
|
||||
if ((TIMx->CR2 & TIM_CR2_MMS) == (0b100 << TIM_CR2_MMS_Pos))
|
||||
{
|
||||
temp_trgo = TIMS->Channels.OC1REF;
|
||||
}
|
||||
else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b101 << TIM_CR2_MMS_Pos))
|
||||
{
|
||||
temp_trgo = TIMS->Channels.OC2REF;
|
||||
}
|
||||
else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b110 << TIM_CR2_MMS_Pos))
|
||||
{
|
||||
temp_trgo = TIMS->Channels.OC3REF;
|
||||
}
|
||||
else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b111 << TIM_CR2_MMS_Pos))
|
||||
{
|
||||
temp_trgo = TIMS->Channels.OC4REF;
|
||||
}
|
||||
// select TIMx TRGO
|
||||
#ifdef USE_TIM1
|
||||
if (TIMx == TIM1)
|
||||
Slave_Channels.TIM1_TRGO = temp_trgo;
|
||||
#endif
|
||||
#ifdef USE_TIM2
|
||||
else if (TIMx == TIM2)
|
||||
Slave_Channels.TIM2_TRGO = temp_trgo;
|
||||
#endif
|
||||
#ifdef USE_TIM3
|
||||
else if (TIMx == TIM3)
|
||||
Slave_Channels.TIM3_TRGO = temp_trgo;
|
||||
#endif
|
||||
#ifdef USE_TIM4
|
||||
else if (TIMx == TIM4)
|
||||
Slave_Channels.TIM4_TRGO = temp_trgo;
|
||||
#endif
|
||||
#ifdef USE_TIM5
|
||||
else if (TIMx == TIM5)
|
||||
Slave_Channels.TIM5_TRGO = temp_trgo;
|
||||
#endif
|
||||
#ifdef USE_TIM6
|
||||
else if (TIMx == TIM6)
|
||||
Slave_Channels.TIM6_TRGO = temp_trgo;
|
||||
#endif
|
||||
#ifdef USE_TIM7
|
||||
else if (TIMx == TIM7)
|
||||
Slave_Channels.TIM7_TRGO = temp_trgo;
|
||||
#endif
|
||||
#ifdef USE_TIM8
|
||||
else if (TIMx == TIM8)
|
||||
Slave_Channels.TIM8_TRGO = temp_trgo;
|
||||
#endif
|
||||
temp_trgo = 0;
|
||||
}
|
||||
//------------------------------------------------------------------//
|
||||
|
||||
|
||||
|
||||
|
||||
//--------------------MISC (temporary) FUNCTIONS--------------------//
|
||||
/* Определение источника для запуска таймера в SLAVE MODE */
|
||||
void Slave_Mode_Check_Source(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
|
||||
{
|
||||
#ifdef USE_TIM2
|
||||
if (TIMx == TIM2)
|
||||
{
|
||||
if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR0)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM1_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR1)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM1_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR2)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM1_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR3)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM8_TRGO << TIM_CR1_CEN_Pos);
|
||||
}
|
||||
#endif
|
||||
#ifdef USE_TIM3
|
||||
else if (TIMx == TIM3)
|
||||
{
|
||||
if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR0)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM8_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR1)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM2_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR2)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM2_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR3)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM3_TRGO << TIM_CR1_CEN_Pos);
|
||||
}
|
||||
#endif
|
||||
#ifdef USE_TIM4
|
||||
else if (TIMx == TIM4)
|
||||
{
|
||||
if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR0)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM3_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR1)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM5_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR2)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM3_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR3)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM4_TRGO << TIM_CR1_CEN_Pos);
|
||||
}
|
||||
#endif
|
||||
#ifdef USE_TIM5
|
||||
else if (TIMx == TIM5)
|
||||
{
|
||||
if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR0)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM4_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR1)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM4_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR2)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM7_TRGO << TIM_CR1_CEN_Pos);
|
||||
else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR3)
|
||||
TIMx->CR1 |= (Slave_Channels.TIM7_TRGO << TIM_CR1_CEN_Pos);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
//------------------------------------------------------------------//
|
||||
|
||||
|
||||
//------------------------SIMULINK FUNCTIONS------------------------//
|
||||
// Симулирование выбранных таймеров
|
||||
void Simulate_TIMs(void)
|
||||
{
|
||||
#ifdef USE_TIM1
|
||||
TIM_Simulation(TIM1, &tim1s);
|
||||
#endif
|
||||
#ifdef USE_TIM2
|
||||
TIM_Simulation(TIM2, &tim2s);
|
||||
#endif
|
||||
#ifdef USE_TIM3
|
||||
TIM_Simulation(TIM3, &tim3s);
|
||||
#endif
|
||||
#ifdef USE_TIM4
|
||||
TIM_Simulation(TIM4, &tim4s);
|
||||
#endif
|
||||
#ifdef USE_TIM5
|
||||
TIM_Simulation(TIM5, &tim5s);
|
||||
#endif
|
||||
#ifdef USE_TIM6
|
||||
TIM_Simulation(TIM6, &tim6s);
|
||||
#endif
|
||||
#ifdef USE_TIM7
|
||||
TIM_Simulation(TIM7, &tim7s);
|
||||
#endif
|
||||
#ifdef USE_TIM8
|
||||
TIM_Simulation(TIM8, &tim8s);
|
||||
#endif
|
||||
#ifdef USE_TIM9
|
||||
TIM_Simulation(TIM9, &tim9s);
|
||||
#endif
|
||||
#ifdef USE_TIM10
|
||||
TIM_Simulation(TIM10, &tim10s);
|
||||
#endif
|
||||
#ifdef USE_TIM11
|
||||
TIM_Simulation(TIM11, &tim11s);
|
||||
#endif
|
||||
#ifdef USE_TIM12
|
||||
TIM_Simulation(TIM12, &tim12s);
|
||||
#endif
|
||||
#ifdef USE_TIM13
|
||||
TIM_Simulation(TIM13, &tim13s);
|
||||
#endif
|
||||
#ifdef USE_TIM14
|
||||
TIM_Simulation(TIM14, &tim14s);
|
||||
#endif
|
||||
}
|
||||
// Деинициализирование выбранных таймеров (вызывается в конце симуляции)
|
||||
void TIM_SIM_DEINIT(void)
|
||||
{
|
||||
#ifdef USE_TIM1
|
||||
memset(&tim1s, 0, sizeof(tim1s));
|
||||
#endif
|
||||
#ifdef USE_TIM2
|
||||
memset(&tim2s, 0, sizeof(tim2s));
|
||||
#endif
|
||||
#ifdef USE_TIM3
|
||||
memset(&tim3s, 0, sizeof(tim3s));
|
||||
#endif
|
||||
#ifdef USE_TIM4
|
||||
memset(&tim4s, 0, sizeof(tim4s));
|
||||
#endif
|
||||
#ifdef USE_TIM5
|
||||
memset(&tim5s, 0, sizeof(tim5s));
|
||||
#endif
|
||||
#ifdef USE_TIM6
|
||||
memset(&tim6s, 0, sizeof(tim6s));
|
||||
#endif
|
||||
#ifdef USE_TIM7
|
||||
memset(&tim7s, 0, sizeof(tim7s));
|
||||
#endif
|
||||
#ifdef USE_TIM8
|
||||
memset(&tim8s, 0, sizeof(tim8s));
|
||||
#endif
|
||||
#ifdef USE_TIM9
|
||||
memset(&tim9s, 0, sizeof(tim9s));
|
||||
#endif
|
||||
#ifdef USE_TIM10
|
||||
memset(&tim10s, 0, sizeof(tim10s));
|
||||
#endif
|
||||
#ifdef USE_TIM11
|
||||
memset(&tim11s, 0, sizeof(tim11s));
|
||||
#endif
|
||||
#ifdef USE_TIM12
|
||||
memset(&tim12s, 0, sizeof(tim12s));
|
||||
#endif
|
||||
#ifdef USE_TIM13
|
||||
memset(&tim13s, 0, sizeof(tim13s));
|
||||
#endif
|
||||
#ifdef USE_TIM14
|
||||
memset(&tim14s, 0, sizeof(tim14s));
|
||||
#endif
|
||||
}
|
||||
//------------------------------------------------------------------//
|
||||
|
||||
//------------------TIM'S HANDLERS (BETA) FUNCTIONS-----------------//
|
||||
// Определение обработчиков, которые не используются
|
||||
// Т.к. в MSVC нет понятия weak function, необходимо объявить все колбеки
|
||||
// И если какой-то колбек не используется, его надо определить
|
||||
//#ifndef USE_TIM1_UP_TIM10_HANDLER
|
||||
//void TIM1_UP_TIM10_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM2_HANDLER
|
||||
//void TIM2_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM3_HANDLER
|
||||
//void TIM3_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM4_HANDLER
|
||||
//void TIM4_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM5_HANDLER
|
||||
//void TIM5_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM6_HANDLER
|
||||
//void TIM6_DAC_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM7_HANDLER
|
||||
//void TIM7_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM8_UP_TIM13_HANDLER
|
||||
//void TIM8_UP_TIM13_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM1_BRK_TIM9_HANDLER
|
||||
//void TIM1_BRK_TIM9_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM1_TRG_COM_TIM11_HANDLER
|
||||
//void TIM1_TRG_COM_TIM11_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM8_BRK_TIM12_HANDLER
|
||||
//void TIM8_BRK_TIM12_IRQHandler(void) {}
|
||||
//#endif
|
||||
//#ifndef USE_TIM8_TRG_COM_TIM14_HANDLER
|
||||
//void TIM8_TRG_COM_TIM14_IRQHandler(void) {}
|
||||
//#endif
|
||||
|
||||
/* Вызов прерывания */
|
||||
void call_IRQHandller(TIM_TypeDef* TIMx)
|
||||
{ // calling HANDLER
|
||||
if (TIMx == TIM1)
|
||||
TIM1_UP_IRQHandler();
|
||||
//if ((TIMx == TIM1) || (TIMx == TIM10))
|
||||
// TIM1_UP_TIM10_IRQHandler();
|
||||
//else if (TIMx == TIM2)
|
||||
// TIM2_IRQHandler();
|
||||
//else if (TIMx == TIM3)
|
||||
// TIM3_IRQHandler();
|
||||
//else if (TIMx == TIM4)
|
||||
// TIM4_IRQHandler();
|
||||
//else if (TIMx == TIM5)
|
||||
// TIM5_IRQHandler();
|
||||
//else if (TIMx == TIM6)
|
||||
// TIM6_DAC_IRQHandler();
|
||||
//else if (TIMx == TIM7)
|
||||
// TIM7_IRQHandler();
|
||||
//else if ((TIMx == TIM8) || (TIMx == TIM13))
|
||||
// TIM8_UP_TIM13_IRQHandler();
|
||||
//else if ((TIMx == TIM1) || (TIMx == TIM9))
|
||||
// TIM1_BRK_TIM9_IRQHandler();
|
||||
//else if ((TIMx == TIM1) || (TIMx == TIM11))
|
||||
// TIM1_TRG_COM_TIM11_IRQHandler();
|
||||
//else if ((TIMx == TIM8) || (TIMx == TIM12))
|
||||
// TIM8_BRK_TIM12_IRQHandler();
|
||||
//else if ((TIMx == TIM8) || (TIMx == TIM14))
|
||||
// TIM8_TRG_COM_TIM14_IRQHandler();
|
||||
}
|
||||
//------------------------------------------------------------------//
|
||||
@@ -0,0 +1,123 @@
|
||||
/**************************************************************************
|
||||
Äàííûé ôàéë ñîäåðæèò îáúÿâëåíèÿ âñÿêîãî äëÿ ñèìóëÿöèè òàéìåðîâ STM32F407xx.
|
||||
|
||||
**************************************************************************/
|
||||
#ifndef _MATLAB_TIM_H_
|
||||
#define _MATLAB_TIM_H_
|
||||
|
||||
#include "stm32f1xx_it.h"
|
||||
#include "mcu_wrapper_conf.h"
|
||||
|
||||
|
||||
|
||||
/////////////////////////////---DEFINES---/////////////////////////////
|
||||
/* äåôàéí äëÿ ñäâèãà ìåæäó ïåðâîé è âòîðîé ïîëîâèíîé CCMRx ðåãèñòðîâ */
|
||||
#define TIM_OCMODE_SECOND_SHIFT TIM_CCMR1_OC2M_Pos - TIM_CCMR1_OC1M_Pos
|
||||
|
||||
///* äåôàéíû äëÿ ïðîâåðêè âûâîäèòü ëè êàíàë íà GPIO (íàñòðîåí ëè GPIO íà àëüòåðíàòèâíóþ ôóíêöèþ) */
|
||||
//#define READ_GPIO_CRL_CNF(_reg_, _pos_) ((_pos_ < 8)? \
|
||||
// ((((_reg_->CRL) & (GPIO_CRL_CNF0 << (_pos_ << 2u))) >> ( _pos_ << 2u)) >> 2): \
|
||||
// ((((_reg_->CRH) & (GPIO_CRL_CNF0 << ((_pos_ - 8) << 2u))) >> ((_pos_ - 8) << 2u)) >> 2) )
|
||||
|
||||
#define Check_OC1_GPIO_Output(_tims_) (GPIO_MODE_AF_PP == GET_GPIO_CONF(_tims_->Channels.OC1_GPIOx, _tims_->Channels.OC1_PIN_SHIFT))
|
||||
#define Check_OC2_GPIO_Output(_tims_) (GPIO_MODE_AF_PP == GET_GPIO_CONF(_tims_->Channels.OC2_GPIOx, _tims_->Channels.OC2_PIN_SHIFT))
|
||||
#define Check_OC3_GPIO_Output(_tims_) (GPIO_MODE_AF_PP == GET_GPIO_CONF(_tims_->Channels.OC3_GPIOx, _tims_->Channels.OC3_PIN_SHIFT))
|
||||
#define Check_OC4_GPIO_Output(_tims_) (GPIO_MODE_AF_PP == GET_GPIO_CONF(_tims_->Channels.OC4_GPIOx, _tims_->Channels.OC4_PIN_SHIFT))
|
||||
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
///////////////////////////---STRUCTURES---//////////////////////////
|
||||
/* Ñòðóêòóðà äëÿ óïðàâëåíèÿ Ñëåéâ Òàéìåðàìè */
|
||||
struct SlaveChannels
|
||||
{
|
||||
unsigned TIM1_TRGO : 1;
|
||||
unsigned TIM2_TRGO : 1;
|
||||
unsigned TIM3_TRGO : 1;
|
||||
unsigned TIM4_TRGO : 1;
|
||||
unsigned TIM5_TRGO : 1;
|
||||
unsigned TIM6_TRGO : 1;
|
||||
unsigned TIM7_TRGO : 1;
|
||||
unsigned TIM8_TRGO : 1;
|
||||
|
||||
};
|
||||
|
||||
/* Ñòðóêòóðà äëÿ ìîäåëèðîâàíèÿ êàíàëîâ òàéìåðà */
|
||||
struct Channels_Sim
|
||||
{
|
||||
// ñâÿçàííûå ñ êàíàëàìè GPIO ïîðòû è ïèíû
|
||||
GPIO_TypeDef *OC1_GPIOx;
|
||||
uint32_t OC1_PIN_SHIFT;
|
||||
|
||||
GPIO_TypeDef *OC2_GPIOx;
|
||||
uint32_t OC2_PIN_SHIFT;
|
||||
|
||||
GPIO_TypeDef *OC3_GPIOx;
|
||||
uint32_t OC3_PIN_SHIFT;
|
||||
|
||||
GPIO_TypeDef *OC4_GPIOx;
|
||||
uint32_t OC4_PIN_SHIFT;
|
||||
|
||||
// Êàíàëû òàéìåðà
|
||||
unsigned OC1REF:1;
|
||||
unsigned OC2REF:1;
|
||||
unsigned OC3REF:1;
|
||||
unsigned OC4REF:1;
|
||||
};
|
||||
|
||||
/* Ñòðóêòóðà äëÿ ìîäåëèðîâàíèÿ òàéìåðà */
|
||||
struct TIM_Sim
|
||||
{
|
||||
double tx_cnt; // ñ÷åò÷èê òàéìåðà
|
||||
double tx_step; // øàã ñ÷åòà çà îäèí øàã ñèìóëÿöèè
|
||||
int RELOAD; // áóôåð, åñëè PRELOAD = 1
|
||||
struct Channels_Sim Channels; // ñòðóêòóðà äëÿ ñèìóëÿöèè êàíàëîâ
|
||||
};
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
///////////////////////////---FUNCTIONS---///////////////////////////
|
||||
|
||||
//----------------------TIMER BASE FUNCTIONS-----------------------//
|
||||
/* Áàçîâàÿ ôóíêöèÿ äëÿ ñèìóëÿöèè òàéìåðà: îíà âûçûâàåòñÿ êàæäûé øàã ñèìóëÿöèè */
|
||||
void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS);
|
||||
/* Ñ÷åò òàéìåðà çà îäèí òàêò */
|
||||
void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
|
||||
/* Ïðîâåðêà íà ïåðåïîëíåíèå è äàëüíåéøàÿ åãî îáðàáîòêà */
|
||||
void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
|
||||
/* Âûçîâ ïðåðûâàíèÿ */
|
||||
void call_IRQHandller(TIM_TypeDef *TIMx);
|
||||
//-----------------------------------------------------------------//
|
||||
|
||||
|
||||
//------------------------CHANNELS FUNCTIONS-----------------------//
|
||||
/* Ñèìóëÿöèÿ êàíàëîâ òàéìåðà */
|
||||
void Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS);
|
||||
/*---------------- - CAPTURE COPMARE & PWM FUNCTIONS------------------*/
|
||||
/* Âûáîð ðåæèìà CaptureCompare èëè PWM è ñèìóëÿöèÿ äëÿ êàæäîãî êàíàëà */
|
||||
void CC_PWM_Ch1_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
|
||||
void CC_PWM_Ch2_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
|
||||
void CC_PWM_Ch3_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
|
||||
void CC_PWM_Ch4_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
|
||||
/* Çàïèñü êàíàëîâ òàéìåðà â ïîðòû GPIO */
|
||||
void Write_OC_to_GPIO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
|
||||
/* Çàïèñü ðåçóëüòàòà compare â ãëàáàëüíóþ ñòðóêòóðó ñ TRIGGER OUTPUT */
|
||||
void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
|
||||
//------------------------------------------------------------------//
|
||||
|
||||
|
||||
//--------------------MISC (temporary) FUNCTIONS--------------------//
|
||||
/* Îïðåäåëåíèå èñòî÷íèêà äëÿ çàïóñêà òàéìåðà â SLAVE MODE */
|
||||
void Slave_Mode_Check_Source(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
|
||||
//------------------------------------------------------------------//
|
||||
|
||||
|
||||
//------------------------SIMULINK FUNCTIONS------------------------//
|
||||
// Ñèìóëèðîâàíèå âûáðàííûõ òàéìåðîâ
|
||||
void Simulate_TIMs(void);
|
||||
// Äåèíèöèàëèçèðîâàíèå âûáðàííûõ òàéìåðîâ (âûçûâàåòñÿ â êîíöå ñèìóëÿöèè)
|
||||
void TIM_SIM_DEINIT(void);
|
||||
//------------------------------------------------------------------//
|
||||
#endif // _MATLAB_TIM_H_
|
||||
@@ -0,0 +1,47 @@
|
||||
/**************************************************************************
|
||||
Данный файл необходим для объявления структур для отображения их в watch
|
||||
В оригинальном stm32f407xx они объявлены дефайнами, которые не видны в watch.
|
||||
Поэтому дополнительно объявлены данные структуры.
|
||||
Называются также, как CMSISные, только в нижнем регистре
|
||||
|
||||
**************************************************************************/
|
||||
#include "stm32f1xx.h"
|
||||
|
||||
|
||||
|
||||
TIM_TypeDef* tim2 = TIM2;
|
||||
TIM_TypeDef* tim3 = TIM3;
|
||||
TIM_TypeDef* tim4 = TIM4;
|
||||
RTC_TypeDef* rtc = RTC;
|
||||
WWDG_TypeDef* wwdg = WWDG;
|
||||
IWDG_TypeDef* iwdg = IWDG;
|
||||
SPI_TypeDef* spi2 = SPI2;
|
||||
USART_TypeDef* usart2 = USART2;
|
||||
USART_TypeDef* usart3 = USART3;
|
||||
I2C_TypeDef* i2c1 = I2C1;
|
||||
I2C_TypeDef* i2c2 = I2C2;
|
||||
CAN_TypeDef* can1 = CAN1;
|
||||
PWR_TypeDef* pwr = PWR;
|
||||
TIM_TypeDef* tim1 = TIM1;
|
||||
USART_TypeDef* usart1 = USART1;
|
||||
ADC_TypeDef* adc1 = ADC1;
|
||||
ADC_TypeDef* adc2 = ADC2;
|
||||
SPI_TypeDef* spi1 = SPI1;
|
||||
EXTI_TypeDef* exti = EXTI;
|
||||
GPIO_TypeDef* gpioa = GPIOA;
|
||||
GPIO_TypeDef* gpiob = GPIOB;
|
||||
GPIO_TypeDef* gpioc = GPIOC;
|
||||
GPIO_TypeDef* gpiod = GPIOD;
|
||||
GPIO_TypeDef* gpioe = GPIOE;
|
||||
CRC_TypeDef* crc = CRC;
|
||||
RCC_TypeDef* rcc = RCC;
|
||||
FLASH_TypeDef* flash_r = FLASH;
|
||||
DMA_TypeDef* dma1 = DMA1;
|
||||
DMA_Channel_TypeDef* dma1_channel1 = DMA1_Channel1;
|
||||
DMA_Channel_TypeDef* dma1_channel2 = DMA1_Channel2;
|
||||
DMA_Channel_TypeDef* dma1_channel3 = DMA1_Channel3;
|
||||
DMA_Channel_TypeDef* dma1_channel4 = DMA1_Channel4;
|
||||
DMA_Channel_TypeDef* dma1_channel5 = DMA1_Channel5;
|
||||
DMA_Channel_TypeDef* dma1_channel6 = DMA1_Channel6;
|
||||
DMA_Channel_TypeDef* dma1_channel7 = DMA1_Channel7;
|
||||
DBGMCU_TypeDef* dbgmcu = DBGMCU;
|
||||
Reference in New Issue
Block a user