#ifndef _SPARTAN2E_FUNCTIONS_H
#define _SPARTAN2E_FUNCTIONS_H
#include "DSP281x_Device.h"
#define SIZE_XILINX200 90126 // count words
struct XControll_reg_bit {
unsigned int OE_BUF_Is_ON:1;
unsigned int RemotePlane_Is_Reset:1;
unsigned int Int_for_XNMI_XINT13_ON:1;
unsigned int Int_for_XINT1_XBIO_ON:1;
unsigned int line_Z_ER0_OUT_Is:1;
unsigned int line_SET_MODE_Is:1;
unsigned int line_ER0_OUT_Sorce_Is_Tms:1;
unsigned int line_ER0_OUT_Is:1;
unsigned int line_CLKS_Sorce_Is_Tms:1;
unsigned int line_CLKS_Is:1;
unsigned int line_P7_4_Sorce_Is_Tms:1;
unsigned int line_P7_4_Is:4; // 4 bits
unsigned int line_ER0_IN_Is:1; // WR has no effect
};
typedef union {
unsigned int all;
struct XControll_reg_bit bit;
} XControll_reg;
union XSeeprom_command_reg {
unsigned int all;
struct {
unsigned int WR0:1;
unsigned int P0:1;
unsigned int A1:1;
unsigned int bit3:1;
unsigned int bit4:1;
unsigned int bit5:1;
unsigned int bit6:1;
unsigned int bit7:1;
} bit;
};
struct XSerial_bus_config_bit {
unsigned int Use_Config:1;
unsigned int Number_of_Frequency_is:3;
unsigned int Use_Timer:1;
unsigned int Range_CountTimer:4;
unsigned int Use_Filtr_on_din:1;
unsigned int Use_only_fast_Filtr_on_din:1;
unsigned int Use_Tweaking:1;
unsigned int Use_compensation_delay_on_Tweaking:1;
unsigned int Use_SyncRdWr:1;
unsigned int reserve_bits:2; // unused 2 bits
};
union XSerial_bus_config_reg {
unsigned int all;
struct XSerial_bus_config_bit bit;
};
struct XSerial_bus_intc_din_bit {
unsigned int State_Is_Idle:1;
unsigned int Error_CRC:1;
unsigned int Error_Comand:1;
unsigned int Timeout_Is_Complete:1;
unsigned int Mode_Is_Config:1;
unsigned int rezerv:3;
};
typedef volatile union {
unsigned int all;
struct XSerial_bus_intc_din_bit bit;
} XSerial_bus_intc_din_reg;
struct XSerial_bus_adr_bit {
unsigned int AdrPlane:4;
unsigned int reserve_bits:3; // unused 3 bits
unsigned int RdWR:1; // '0' - WR, '1' - RD
unsigned int AdrReg:8;
};
union XSerial_bus_adr_reg {
unsigned int all;
struct XSerial_bus_adr_bit bit;
};
typedef struct {
unsigned int TypeAccess;
unsigned int AdrPlane;
unsigned int AdrReg;
unsigned int DataWr;
unsigned int DataRd;
} Xmemory_uni;
typedef volatile struct {
unsigned int BaseAddress; // Base address of registers //
unsigned int DataWr; // Data for write to selected register //
unsigned int DataRd; // Reading data from selected register //
union XSerial_bus_adr_reg Adr;
XSerial_bus_intc_din_reg ISR;
union XSerial_bus_config_reg Config;
unsigned int IsReady:1; // Device is initialized and ready //
} XSerial_bus;
struct XSeeprom_s {
unsigned int Adr_device;
unsigned long Adr;
unsigned long Adr_seeprom;
unsigned long size;
unsigned long ok_write;
unsigned long write_error;
unsigned long repeat_error;
};
typedef volatile struct XSeeprom_s XSeeprom_t;
struct XSerial_bus_intc_mer_bit {
unsigned int Master_Enable:1;
unsigned int Hardware_Int_Enable:1;
};
union XSerial_bus_intc_mer_reg {
unsigned int all;
struct XSerial_bus_intc_mer_bit bit;
};
struct XSerial_bus_INTC {
XSerial_bus_intc_din_reg ISR;
XSerial_bus_intc_din_reg IER;
XSerial_bus_intc_din_reg IPR;
union XSerial_bus_intc_mer_reg MER;
};
struct XSerial_Tweaking_Data {
unsigned int Tweaking_tr_line:4;
unsigned int Tweaking_rec_line:4;
};
/*
struct XSerial_bus_Config_Data {
unsigned int Constant_for_Timer;
unsigned int Number_Wait_State_for_TrRec:4;
unsigned int Number_Wait_State_for_Pause:4;
struct XSerial_Tweaking_Data Tweaking_chanal[8];
unsigned int Delay_clk_for_Tr:7;
unsigned int Delay_clk_for_Rec:7;
unsigned int Use_fast_Filtr:1;
unsigned int Use_fast_Transmit:1;
unsigned int Tweaking_tbuf_en:4;
};
*/
/*
typedef volatile struct {
unsigned int PlaneIsLive; // For selected DelayLine chanal is visible: QualityTrRec = 100%, bit per chanal
unsigned int CountErrors; // count errors transmit-recieve
XSerial_bus *Bus;
struct XSerial_bus_INTC INTC;
struct XSerial_bus_Config_Data Config_Data;
unsigned int Number_Chanal;
} XSerial_bus_stats;
*/
/*
struct PARALLEL_BITS { // bits description
Uint16 res0:1; // 0
Uint16 res1:1; // 1
Uint16 res2:1; // 2
Uint16 res3:1; // 3
Uint16 res4:1; // 4
Uint16 res5:1; // 5
Uint16 res6:1; // 6
Uint16 res7:1; // 7
Uint16 res8:1; // 8
Uint16 res9:1; // 9
Uint16 res10:1; // 10
Uint16 res11:1; // 11
Uint16 res12:1; // 12
Uint16 res13:1; // 13
Uint16 res14:1; // 14
Uint16 res15:1; // 15
};
struct PARALLEL_STATUS_BITS { // bits description
Uint16 err_crc:1; // 0
Uint16 not_ready:1; // 1
Uint16 res2:1; // 2
Uint16 res3:1; // 3
Uint16 res4:1; // 4
Uint16 res5:1; // 5
Uint16 res6:1; // 6
Uint16 res7:1; // 7
Uint16 res8:1; // 8
Uint16 res9:1; // 9
Uint16 res10:1; // 10
Uint16 res11:1; // 11
Uint16 res12:1; // 12
Uint16 res13:1; // 13
Uint16 res14:1; // 14
Uint16 res15:1; // 15
};
union PARALLEL1_REG {
Uint16 all;
struct PARALLEL_BITS bit;
};
union PARALLEL2_REG {
Uint16 all;
struct PARALLEL_BITS bit;
};
union PARALLEL3_REG {
Uint16 all;
struct PARALLEL_BITS bit;
};
union PARALLEL4_REG {
Uint16 all;
struct PARALLEL_BITS bit;
};
union PARALLEL5_REG {
Uint16 all;
struct PARALLEL_BITS bit;
};
union PARALLEL_STATUS_REG {
Uint16 all;
struct PARALLEL_STATUS_BITS bit;
};
typedef volatile struct { // bits description
union PARALLEL1_REG reg1;
union PARALLEL2_REG reg2;
union PARALLEL3_REG reg3;
union PARALLEL4_REG reg4;
union PARALLEL5_REG reg5;
union PARALLEL_STATUS_REG status;
} PARALLEL_REGS;
*/
int load_xilinx_new(unsigned long adr,unsigned long size);
int xflash_remote_eeprom(unsigned int adr_device, unsigned long adr,
unsigned long adr_eeprom, unsigned long size, unsigned long *ok_write,
unsigned long *write_error, unsigned long *repeat_error );
long xread_remote_eeprom(unsigned int adr_device, unsigned long adr_eeprom,
unsigned long adr, unsigned long size, unsigned long *ok_write,
unsigned long *write_error, unsigned long *repeat_error );
long xverify_remote_eeprom(unsigned int adr_device, unsigned long adr,
unsigned long adr_eeprom, unsigned long size, unsigned long *ok_write,
unsigned long *write_error, unsigned long *repeat_error );
int test_xilinx_live(void);
int enable_er0_control(void);
void ResetNPeriphPlane(unsigned int np);
#endif