#ifndef XP_PROJECT_H
#define XP_PROJECT_H

#include <project_setup.h>

#include "DSP281x_Examples.h"   // DSP281x Examples Include File
#include "DSP281x_GlobalPrototypes.h"
#include "DSP281x_SWPrioritizedIsrLevels.h"   // DSP281x Examples Include File
#include "DSP281x_Device.h"
#include "DSP281x_Ev.h"   // DSP281x Examples Include File
#include "MemoryFunctions.h"
#include "Spartan2E_Adr.h"
#include "Spartan2E_Functions.h"
#include "TuneUpPlane.h"
#include "x_int13.h"
#include "x_parallel_bus.h"
#include "x_serial_bus.h"
#include "xerror.h"
#include "xp_adc.h"
#include "xp_cds_in.h"
#include "xp_cds_out.h"
#include "xp_cds_rs.h"
#include "xp_cds_tk.h"
#include "xp_controller.h"
#include "xp_hwp.h"
#include "xp_inc_sensor.h"
#include "xPeriphSP6_loader.h"


#define WITH_RESET_ALL_PLATES		1
#define WITHOUT_RESET_ALL_PLATES	0
#define WITHOUT_RESET_ALL_PLATES_NO_STOP_ERROR	2
#define WITH_RESET_ALL_PLATES_NO_STOP_ERROR		3



/////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////
// Суммарные статусы по всем платам
/////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////
typedef struct {

#if(C_cds_tk_number>=1)
	    T_component_status tk0;
#endif
#if(C_cds_tk_number>=2)
		T_component_status tk1;
#endif
#if(C_cds_tk_number>=3)
		T_component_status tk2;
#endif
#if(C_cds_tk_number>=4)
		T_component_status tk3;
#endif
#if(C_cds_tk_number>=5)
        T_component_status tk4;
#endif
#if(C_cds_tk_number>=6)
        T_component_status tk5;
#endif
#if(C_cds_tk_number>=7)
        T_component_status tk6;
#endif
#if(C_cds_tk_number>=8)
        T_component_status tk7;
#endif

#if(C_adc_number>=1)
	    T_component_status adc0;
#endif
#if(C_adc_number>=2)
		T_component_status adc1;
#endif
#if(C_adc_number>=3)
        T_component_status adc2;
#endif

#if(C_cds_in_number>=1)
	    T_component_status in0;
#endif
#if(C_cds_in_number>=2)
		T_component_status in1;
#endif

#if(C_cds_in_number>=3)
		T_component_status in2;
#endif
#if(C_cds_out_number>=1)
	    T_component_status out0;
#endif
#if(C_cds_out_number>=2)
		T_component_status out1;
#endif
#if(C_cds_out_number>=3)
		T_component_status out2;
#endif

#if (C_cds_rs_number>=1)
		T_component_status rs0;
#endif

#if(C_hwp_number>=1)
		T_component_status hwp0;
#endif
#if(C_hwp_number>=2)
		T_component_status hwp1;
#endif
#if(C_hwp_number>=3)
        T_component_status hwp2;
#endif

} T_project_all_status_plates;







typedef struct {
	union
	{
		UInt16 all;
		struct 
		{
#if(C_cds_tk_number>=1)
	    UInt16 tk0 :1;
#endif
#if(C_cds_tk_number>=2)
		UInt16 tk1 :1;
#endif
#if(C_cds_tk_number>=3)
		UInt16 tk2 :1;
#endif
#if(C_cds_tk_number>=4)
		UInt16 tk3 :1;
#endif
#if(C_cds_tk_number>=5)
        UInt16 tk4 :1;
#endif
#if(C_cds_tk_number>=6)
        UInt16 tk5 :1;
#endif
#if(C_cds_tk_number>=7)
        UInt16 tk6 :1;
#endif
#if(C_cds_tk_number>=8)
        UInt16 tk7 :1;
#endif

		UInt16 res  :(16-C_cds_tk_number);

		} bit;
	} errors_tk;
    union
    {
        UInt16 all;
        struct
        {

#if(C_adc_number>=1)
        UInt16 adc0 :1;
#endif
#if(C_adc_number>=2)
        UInt16 adc1 :1;
#endif
#if(C_adc_number>=3)
        UInt16 adc2 :1;
#endif

#if(C_cds_in_number>=1)
        UInt16 in0 :1;
#endif
#if(C_cds_in_number>=2)
        UInt16 in1 :1;
#endif
#if(C_cds_in_number>=3)
        UInt16 in2 :1;
#endif

#if(C_cds_out_number>=1)
        UInt16 out0 :1;
#endif
#if(C_cds_out_number>=2)
        UInt16 out1 :1;
#endif
#if(C_cds_out_number>=3)
        UInt16 out2 :1;
#endif

#if (C_cds_rs_number>=1)
        UInt16 rs0 :1;
#endif

#if(C_hwp_number>=1)
        UInt16 hwp0 :1;
#endif
#if(C_hwp_number>=2)
        UInt16 hwp1 :1;
#endif
#if(C_hwp_number>=3)
        UInt16 hwp2 :1;
#endif

        UInt16 res  :1;

        } bit;
    } errors;

} T_project_all_errors_plates;

#define T_PROJECT_ALL_ERRORS_PLATES_DEFAULTS {0,0}
/////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////




typedef struct TS_project{
	T_controller 		                controller;
//	int 		controller;
    T_project_all_errors_plates         all_err_plates;
	T_project_all_status_plates         all_status_plates;
	T_cds_tk			                cds_tk[C_cds_tk_number];
	T_adc				                adc[C_adc_number];
	T_cds_in			                cds_in[C_cds_in_number];
	T_cds_out			                cds_out[C_cds_out_number];
#if (C_cds_rs_number>=1)
	T_cds_rs			                cds_rs[C_cds_rs_number];
#endif
	T_hwp				                hwp[C_hwp_number];
//	T_omega				omega[C_omega_number];
//	T_dispatcher		dispatcher;
//	T_project_soft_info	soft_info;	
	X_SERIAL_BUS 		                *x_serial_bus;
	X_PARALLEL_BUS		                *x_parallel_bus;

	int 	inited;


    void (*init)();	    // Pointer to calculation function
    void (*read_all_sbus)();	    // Pointer to calculation function
	void (*read_all_pbus)();
	void (*write_all_sbus)();
	void (*reload_all_plates_with_reset)();  //  со сбросом плат
	void (*reload_all_plates_without_reset)();  //  без сброса
	void (*reload_all_plates_with_reset_no_stop_error)();  //  со сбросом плат и без стопа на ошибках
	void (*reload_all_plates_without_reset_no_stop_error)();  //  без сброса и без стопа на ошибках
	void (*write_all_hwp)();
	void (*read_all_hwp)();
	void (*send_reset_all_plates)();
	void (*stop_parallel_bus)();
	void (*start_parallel_bus)();
	void (*clear)();
	void (*read_errors_controller)();
	void (*reset_errors_controller)();
	void (*load_cfg_to_plates)();
	void (*clear_errors_all_plates)();
	void (*disable_all_interrupt)();
	void (*enable_all_interrupt)();
    void (*enable_int13)();
	void (*disable_int13)();
	void (*find_all_cds)();
	


} T_project;

extern T_project project;


#if(C_cds_tk_number==8)
#define PROJECT_DEFAULTS_CDS_TK  {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS}
#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady
#endif
#if(C_cds_tk_number==7)
#define PROJECT_DEFAULTS_CDS_TK  {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS}
#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady
#endif
#if(C_cds_tk_number==6)
#define PROJECT_DEFAULTS_CDS_TK  {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS}
#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady
#endif
#if(C_cds_tk_number==5)
#define PROJECT_DEFAULTS_CDS_TK  {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS}
#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady
#endif
#if(C_cds_tk_number==4)
#define PROJECT_DEFAULTS_CDS_TK  {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS}
#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady,component_NotReady
#endif
#if(C_cds_tk_number==3)
#define PROJECT_DEFAULTS_CDS_TK  {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS}
#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady
#endif
#if(C_cds_tk_number==2)
#define PROJECT_DEFAULTS_CDS_TK  {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS}
#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady
#endif
#if(C_cds_tk_number==1)
#define PROJECT_DEFAULTS_CDS_TK  {T_cds_tk_DEFAULTS}
#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady
#endif

#if(C_adc_number==1)
#define PROJECT_DEFAULTS_ADC {T_adc_DEFAULTS}
#define ADC_STATUS_PLATES_DEFAULTS component_NotReady
#endif
#if(C_adc_number==2)
#define PROJECT_DEFAULTS_ADC {T_adc_DEFAULTS,T_adc_DEFAULTS}
#define ADC_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady
#endif
#if(C_adc_number==3)
#define PROJECT_DEFAULTS_ADC {T_adc_DEFAULTS,T_adc_DEFAULTS,T_adc_DEFAULTS}
#define ADC_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady
#endif


#if(C_hwp_number==1)
#define PROJECT_DEFAULTS_HWP T_hwp_DEFAULTS
#define HWP_STATUS_PLATES_DEFAULTS component_NotReady
#endif
#if(C_hwp_number==2)
#define PROJECT_DEFAULTS_HWP {T_hwp_DEFAULTS, T_hwp_DEFAULTS}
#define HWP_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady
#endif
#if(C_hwp_number==3)
#define PROJECT_DEFAULTS_HWP {T_hwp_DEFAULTS, T_hwp_DEFAULTS, T_hwp_DEFAULTS}
#define HWP_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady
#endif


#if(C_cds_out_number==1)
#define PROJECT_DEFAULTS_OUT {T_cds_out_DEFAULTS}
#define OUT_STATUS_PLATES_DEFAULTS component_NotReady
#endif
#if(C_cds_out_number==2)
#define PROJECT_DEFAULTS_OUT {T_cds_out_DEFAULTS,T_cds_out_DEFAULTS}
#define OUT_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady
#endif
#if(C_cds_out_number==3)
#define PROJECT_DEFAULTS_OUT {T_cds_out_DEFAULTS,T_cds_out_DEFAULTS,T_cds_out_DEFAULTS}
#define OUT_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady
#endif

#if(C_cds_in_number==1)
#define PROJECT_DEFAULTS_IN {T_cds_in_DEFAULTS}
#define IN_STATUS_PLATES_DEFAULTS component_NotReady
#endif
#if(C_cds_in_number==2)
#define PROJECT_DEFAULTS_IN {T_cds_in_DEFAULTS,T_cds_in_DEFAULTS}
#define IN_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady
#endif
#if(C_cds_in_number==3)
#define PROJECT_DEFAULTS_IN {T_cds_in_DEFAULTS,T_cds_in_DEFAULTS,T_cds_in_DEFAULTS}
#define IN_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady
#endif



#if(C_cds_rs_number>=1)
#define PROJECT_DEFAULTS_CDS_RS {T_cds_rs_DEFAULTS},
#define CDS_RS_STATUS_PLATES_DEFAULTS ,component_NotReady
#else
#define PROJECT_DEFAULTS_CDS_RS
#define CDS_RS_STATUS_PLATES_DEFAULTS
#endif


#define T_PROJECT_ALL_STATUS_PLATES_DEFAULTS {HWP_STATUS_PLATES_DEFAULTS, ADC_STATUS_PLATES_DEFAULTS, CDS_TK_STATUS_PLATES_DEFAULTS,  OUT_STATUS_PLATES_DEFAULTS, IN_STATUS_PLATES_DEFAULTS CDS_RS_STATUS_PLATES_DEFAULTS}




#define PROJECT_DEFAULTS 	{  T_controller_DEFAULTS, \
							T_PROJECT_ALL_ERRORS_PLATES_DEFAULTS, T_PROJECT_ALL_STATUS_PLATES_DEFAULTS, \
							PROJECT_DEFAULTS_CDS_TK, \
							PROJECT_DEFAULTS_ADC, \
							PROJECT_DEFAULTS_IN, \
							PROJECT_DEFAULTS_OUT, \
							PROJECT_DEFAULTS_CDS_RS \
							PROJECT_DEFAULTS_HWP, \
							NULL, NULL, \
							0,\
							(void (*)(Uint32))project_init, \
							(void (*)(Uint32))project_read_all_sbus, \
							(void (*)(Uint32))project_read_all_pbus,\
							(void (*)(Uint32))project_write_all_sbus,\
							(void (*)(Uint32))project_reload_all_plates_with_reset, \
							(void (*)(Uint32))project_reload_all_plates_without_reset, \
							(void (*)(Uint32))project_reload_all_plates_with_reset_no_stop_error, \
							(void (*)(Uint32))project_reload_all_plates_without_reset_no_stop_error, \
							(void (*)(Uint32))project_write_all_hwp, \
							(void (*)(Uint32))project_read_all_hwp, \
							(void (*)(Uint32))send_reset_all_plates, \
							(void (*)(Uint32))project_stop_parallel_bus, \
							(void (*)(Uint32))project_start_parallel_bus, \
							(void (*)(Uint32))project_clear, \
							(void (*)(Uint32))project_read_errors_controller,\
							(void (*)(Uint32))project_reset_errors_controller, \
							(void (*)(Uint32))project_load_cfg_to_plates, \
							(void (*)(Uint32))project_clear_errors_all_plates, \
							(void (*)(Uint32))project_disable_all_interrupts, \
							(void (*)(Uint32))project_enable_all_interrupts,\
							(void (*)(Uint32))project_enable_int13,\
							(void (*)(Uint32))project_disable_int13,\
                            (void (*)(Uint32))project_find_all_cds\
							 }


void project_init(void);
void project_read_all_sbus(void);
void project_read_all_pbus(void);
void project_write_all_sbus(void);
void project_reload_all_plates_with_reset(void);
void project_reload_all_plates_without_reset(void);
void project_reload_all_plates_with_reset_no_stop_error(void);
void project_reload_all_plates_without_reset_no_stop_error(void);
void project_write_all_hwp(void);
void project_read_all_hwp(void);
void project_autospeed_all_hwp(void);

void send_reset_all_plates(void);


unsigned int project_wait_load_all_cds(int flag_reset);
void project_find_all_cds(void);

void project_stop_parallel_bus(void);
void project_start_parallel_bus(void);
void project_load_cfg_to_plates(void);

void project_clear(void);
void project_read_errors_controller(void);

void project_reset_errors_controller(void);



void project_reload_all_plates(int reset);

void project_clear_errors_all_plates(void);

void project_all_test_hwp(void);

//////////////////////////////////////////////////////////////////////
// Обновление суммарного статуса готовности и ошибок по всем платам
//////////////////////////////////////////////////////////////////////
void project_update_all_err_status_plates(void);


void project_enable_all_interrupts(void);
void project_disable_all_interrupts(void);


void project_enable_int13(void);
void project_disable_int13(void);

void project_run_init_all_plates(void);

#endif // end XP_PROJECT_H
