#include "TuneUpPlane.h"

#include "DSP281x_Examples.h"
#include "DSP281x_Device.h"
#include "DSP281x_Xintf.h"

#define SelectWorkWithFlash()			WriteOper(0,0,0,0)
#define SelectStrob67_ForFlash()		WriteOper(1,0,1,0)

unsigned int cl_led1 = 0;
unsigned int cl_led2 = 0;

void SetupOperLine();

#pragma CODE_SECTION(Led1_Toggle,".fast_run");
#pragma CODE_SECTION(Led2_Toggle,".fast_run");

#pragma CODE_SECTION(i_led2_on_off,".fast_run");
void i_led2_on_off(int i)
{
     EALLOW;

 	 if (i) GpioDataRegs.GPDSET.bit.GPIOD6=1;
     else   GpioDataRegs.GPDCLEAR.bit.GPIOD6=1;


     EDIS;
}

#pragma CODE_SECTION(i_led1_on_off,".fast_run");
void i_led1_on_off(int i)
{
     EALLOW;
	 if (i) GpioDataRegs.GPASET.bit.GPIOA10=1;
     else   GpioDataRegs.GPACLEAR.bit.GPIOA10=1;

     EDIS;
}


//#pragma CODE_SECTION(i_led2_on_off_special,".fast_run");
//void i_led2_on_off_special(int i)
//{
//     EALLOW;
//
//     if (i) GpioDataRegs.GPDSET.bit.GPIOD6=1;
//     else   GpioDataRegs.GPDCLEAR.bit.GPIOD6=1;
//
//
//     EDIS;
//}

#pragma CODE_SECTION(i_led1_on_off_special,".fast_run");
void i_led1_on_off_special(int i)
{
     EALLOW;
     if (i)
     {
         GpioDataRegs.GPASET.bit.GPIOA10=1;
         cl_led1++;
     }
     else
     {
         if (cl_led1)
             cl_led1--;

         if (cl_led1 == 0)
            GpioDataRegs.GPACLEAR.bit.GPIOA10=1;
     }

     EDIS;
}

#pragma CODE_SECTION(i_led2_on_off_special,".fast_run");
void i_led2_on_off_special(int i)
{
     EALLOW;
     if (i)
     {
         GpioDataRegs.GPDSET.bit.GPIOD6=1;
         cl_led2++;
     }
     else
     {
         if (cl_led2)
             cl_led2--;

         if (cl_led2 == 0)
             GpioDataRegs.GPDCLEAR.bit.GPIOD6=1;
     }

     EDIS;
}


void Led1_Toggle()
{
     EALLOW;
     GpioDataRegs.GPATOGGLE.bit.GPIOA10=1; 
     EDIS;
}


void Led2_Toggle()
{
     EALLOW;
     GpioDataRegs.GPDTOGGLE.bit.GPIOD6=1;
     EDIS;
}

void SetupLedsLine()
{
    EALLOW;	 
	GpioMuxRegs.GPDMUX.bit.T4CTRIP_SOCB_GPIOD6 = 0;
	GpioDataRegs.GPDDAT.bit.GPIOD6 = 0;
	GpioMuxRegs.GPDDIR.bit.GPIOD6 = 1;
	
	GpioMuxRegs.GPAMUX.bit.CAP3QI1_GPIOA10 = 0;
	GpioDataRegs.GPADAT.bit.GPIOA10 = 0;
	GpioMuxRegs.GPADIR.bit.GPIOA10 = 1;	
    EDIS;
        
}

#pragma CODE_SECTION(pause_1000,".fast_run");
void pause_1000(unsigned long t)
{
	unsigned long i;
	
	t = t >> 1;
	
	for (i = 0; i < t; i++)
	{
		DSP28x_usDelay(40L);
	}
}
//Xilinx Zone
void XintfZone0_Timing(void)
{
    // Zone 0------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING0.bit.XWRLEAD = 3;//2;
    XintfRegs.XTIMING0.bit.XWRACTIVE = 5;//2;//1; // 1
    XintfRegs.XTIMING0.bit.XWRTRAIL = 1;//0;
    // Zone read timing
    XintfRegs.XTIMING0.bit.XRDLEAD = 3;
    XintfRegs.XTIMING0.bit.XRDACTIVE = 5;//1
    XintfRegs.XTIMING0.bit.XRDTRAIL = 1;//1

    // do not double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING0.bit.X2TIMING = 0;
 
    // Zone will not sample READY 
    XintfRegs.XTIMING0.bit.USEREADY = 0;//1;
    XintfRegs.XTIMING0.bit.READYMODE = 0;//1;  
 
    // Size must be 1,1 - other values are reserved
    XintfRegs.XTIMING0.bit.XSIZE = 3;
 

    
   //Force a pipeline flush to ensure that the write to 
   //the last register configured occurs before returning.  
   asm(" RPT #7 || NOP"); 
}

void XintfZone6_And7_Timing(void)
{

    // All Zones---------------------------------
    // Timing for all zones based on XTIMCLK = SYSCLKOUT/2 
    XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
    // Buffer up to 0 writes
    XintfRegs.XINTCNF2.bit.WRBUFF = 0;
    // XCLKOUT is enabled
    XintfRegs.XINTCNF2.bit.CLKOFF = 0;
    // XCLKOUT = XTIMCLK 
#ifdef XLOW_FREQUENCY_MODE
    XintfRegs.XINTCNF2.bit.CLKMODE = 1; 
#else
    XintfRegs.XINTCNF2.bit.CLKMODE = 0; 
#endif
	XintfRegs.XINTCNF2.bit.MPNMC = 0;
    
    
    // Zone 6------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING6.bit.XWRLEAD = 3;
    XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING6.bit.XRDLEAD = 3;
    XintfRegs.XTIMING6.bit.XRDACTIVE = 7;//3;
    XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
    
    // do not double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING6.bit.X2TIMING = 0;
 
    // Zone will not sample READY 
    XintfRegs.XTIMING6.bit.USEREADY = 0;//1;
    XintfRegs.XTIMING6.bit.READYMODE = 0;//1;  
 
    // Size must be 1,1 - other values are reserved
    XintfRegs.XTIMING6.bit.XSIZE = 3;
 

    // Zone 7------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING7.bit.XWRLEAD = 3;
    XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING7.bit.XRDLEAD = 3;
    XintfRegs.XTIMING7.bit.XRDACTIVE = 3;
    XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
    
    // don't double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING7.bit.X2TIMING = 0;
 
    // Zone will not sample XREADY signal  
    XintfRegs.XTIMING7.bit.USEREADY = 0;
    XintfRegs.XTIMING7.bit.READYMODE = 0;
 
    // Size must be 1,1 - other values are reserved
    XintfRegs.XTIMING7.bit.XSIZE = 3;
    
   //Force a pipeline flush to ensure that the write to 
   //the last register configured occurs before returning.  
   asm(" RPT #7 || NOP"); 
}

void XintfZone2_Timing(void)
{

    // All Zones---------------------------------
    // Timing for all zones based on XTIMCLK = SYSCLKOUT/2 
    XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
    // Buffer up to 0 writes
    XintfRegs.XINTCNF2.bit.WRBUFF = 0;
    // XCLKOUT is enabled
    XintfRegs.XINTCNF2.bit.CLKOFF = 0;
    // XCLKOUT = XTIMCLK 
    XintfRegs.XINTCNF2.bit.CLKMODE = 0;

	XintfRegs.XINTCNF2.bit.MPNMC = 0;
    
    
    // Zone 6------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING2.bit.XWRLEAD   = 3;//2;
    XintfRegs.XTIMING2.bit.XWRACTIVE = 4;//2;
    XintfRegs.XTIMING2.bit.XWRTRAIL  = 2;//2;
    // Zone read timing
    XintfRegs.XTIMING2.bit.XRDLEAD   = 2;
    XintfRegs.XTIMING2.bit.XRDACTIVE = 3; //1;
    XintfRegs.XTIMING2.bit.XRDTRAIL  = 1;//2;//0;
    
    // do not double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING2.bit.X2TIMING = 0;
 
    // Zone will not sample READY 
    XintfRegs.XTIMING2.bit.USEREADY = 0;//1;
    XintfRegs.XTIMING2.bit.READYMODE = 0;//1;  
 
    // Size must be 1,1 - other values are reserved
    XintfRegs.XTIMING2.bit.XSIZE = 3;
 

    
   //Force a pipeline flush to ensure that the write to 
   //the last register configured occurs before returning.  
   asm(" RPT #7 || NOP"); 
}

void FlashInit()
{
	SetupOperLine();
	
	SelectStrob67_ForFlash();
	
	XintfZone6_And7_Timing();
	SelectWorkWithFlash();
}

void SetupOperLine()
{
    EALLOW;
	 
	GpioMuxRegs.GPAMUX.bit.C1TRIP_GPIOA13=0;
	GpioMuxRegs.GPAMUX.bit.C2TRIP_GPIOA14=0;
	GpioMuxRegs.GPAMUX.bit.C3TRIP_GPIOA15=0;
	GpioMuxRegs.GPBMUX.bit.C4TRIP_GPIOB13=0;
	GpioMuxRegs.GPBMUX.bit.C6TRIP_GPIOB15=0;			
										
	GpioMuxRegs.GPADIR.bit.GPIOA13=1;
	GpioMuxRegs.GPADIR.bit.GPIOA14=1;
	GpioMuxRegs.GPADIR.bit.GPIOA15=1;
	GpioMuxRegs.GPBDIR.bit.GPIOB13=1;
	GpioMuxRegs.GPBDIR.bit.GPIOB15=1;
	
    GpioMuxRegs.GPAQUAL.all=0;   
    GpioMuxRegs.GPBQUAL.all=0;
    EDIS;
    
    WriteOper(1,1,1,1);
    
}

void WriteOper(unsigned char oper_mode1,unsigned char oper_mode2, unsigned char oper_mode3, unsigned char oper_mode4)
{
     EALLOW;
     GpioDataRegs.GPADAT.bit.GPIOA13=oper_mode1;
     GpioDataRegs.GPADAT.bit.GPIOA14=oper_mode2;
     GpioDataRegs.GPADAT.bit.GPIOA15=oper_mode3;
     GpioDataRegs.GPBDAT.bit.GPIOB13=oper_mode4;
     
     asm(" NOP");
     GpioDataRegs.GPBDAT.bit.GPIOB15=0;
     asm(" NOP");
     asm(" NOP");
     asm(" NOP");
     GpioDataRegs.GPBDAT.bit.GPIOB15=1;
     asm(" NOP");
     asm(" NOP");
     asm(" NOP");
     GpioDataRegs.GPBDAT.bit.GPIOB15=0;
     asm(" NOP");
     asm(" NOP");
     asm(" NOP");
     
     EDIS;
}
