From 67c8d0e0398a3ceed2000544686dd82a57187071 Mon Sep 17 00:00:00 2001 From: Razvalyaev Date: Fri, 7 Nov 2025 23:05:56 +0300 Subject: [PATCH] =?UTF-8?q?=D0=94=D0=BE=D0=B1=D0=B0=D0=B2=D0=BB=D0=B5?= =?UTF-8?q?=D0=BD=D1=8B=20=D1=81=D1=83=D0=B1=D0=BC=D0=BE=D0=B4=D1=83=D0=BB?= =?UTF-8?q?=D0=B8-=D0=B1=D0=B8=D0=B1=D0=BB=D0=B8=D0=BE=D1=82=D0=B5=D0=BA?= =?UTF-8?q?=D0=B8=20STM32?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 50 + .gitmodules | 13 + UPP/AllLibs/ExtMemory | 1 + UPP/AllLibs/Modbus | 1 + UPP/AllLibs/MyLibs | 1 + UPP/AllLibs/PeriphGeneral | 1 + UPP/Core/Configs/SEGGER_RTT_Conf.h | 429 ++++++++ UPP/Core/Configs/memspi_config.h | 70 ++ UPP/Core/Configs/modbus_config.h | 71 ++ UPP/Core/Configs/modbus_data.c | 141 +++ UPP/Core/Configs/modbus_data.h | 159 +++ UPP/Core/Configs/mylibs_config.h | 113 +++ UPP/Core/Configs/mylibs_include.h | 136 +++ UPP/Core/Configs/upp_config.h | 22 + UPP/Core/Inc/main.h | 3 +- UPP/Core/Src/main.c | 2 +- UPP/MDK-ARM/RTE/_UPP/RTE_Components.h | 3 + UPP/MDK-ARM/UPP.uvoptx | 1291 +++++++++++++++++++++---- UPP/MDK-ARM/UPP.uvprojx | 385 ++++++-- UPP/MDK-ARM/UPP/UPP.sct | 19 + 20 files changed, 2658 insertions(+), 253 deletions(-) create mode 100644 .gitignore create mode 100644 .gitmodules create mode 160000 UPP/AllLibs/ExtMemory create mode 160000 UPP/AllLibs/Modbus create mode 160000 UPP/AllLibs/MyLibs create mode 160000 UPP/AllLibs/PeriphGeneral create mode 100644 UPP/Core/Configs/SEGGER_RTT_Conf.h create mode 100644 UPP/Core/Configs/memspi_config.h create mode 100644 UPP/Core/Configs/modbus_config.h create mode 100644 UPP/Core/Configs/modbus_data.c create mode 100644 UPP/Core/Configs/modbus_data.h create mode 100644 UPP/Core/Configs/mylibs_config.h create mode 100644 UPP/Core/Configs/mylibs_include.h create mode 100644 UPP/Core/Configs/upp_config.h create mode 100644 UPP/MDK-ARM/UPP/UPP.sct diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..483dd9b --- /dev/null +++ b/.gitignore @@ -0,0 +1,50 @@ +# ---> uVision +# git ignore file for Keil µVision Project + +# Listing Files +*.i +*.lst +*.m51 +*.m66 +*.map + +# Object Files +*.axf +*.b[0-2][0-9] +*.b3[0-1] +*.bak +*.build_log.htm +*.crf +*.d +*.dep +*.elf +*.htm +*.iex +*.lnp +*.o +*.obj +*.sbr + +# Firmware Files +*.bin +*.h86 +*.hex + +# Build Files +*.bat + +# Debugger Files +*.ini + +# JLink Files +JLinkLog.txt + +# Other Files + +/.outdate +/Doxygen/html +/UPP/MDK-ARM/UPP +/Terminals/ + +~* +/UPP/MDK-ARM/UPP.uvguix.* diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..d45c5ca --- /dev/null +++ b/.gitmodules @@ -0,0 +1,13 @@ +[submodule "UPP/AllLibs/MyLibs"] + path = UPP/AllLibs/MyLibs + url = https://git.arktika.cyou/Razvalyaev/STM32_ExtendedLibs.git +[submodule "UPP/AllLibs/PeriphGeneral"] + path = UPP/AllLibs/PeriphGeneral + url = https://git.arktika.cyou/Razvalyaev/STM32_General.git +[submodule "UPP/AllLibs/Modbus"] + path = UPP/AllLibs/Modbus + url = https://git.arktika.cyou/set506/STM32_Modbus.git + branch = release +[submodule "UPP/AllLibs/ExtMemory"] + path = UPP/AllLibs/ExtMemory + url = https://git.arktika.cyou/set506/STM32_MemorySPI.git diff --git a/UPP/AllLibs/ExtMemory b/UPP/AllLibs/ExtMemory new file mode 160000 index 0000000..e9d2214 --- /dev/null +++ b/UPP/AllLibs/ExtMemory @@ -0,0 +1 @@ +Subproject commit e9d22149534563eca7287c9662291292bf1853f3 diff --git a/UPP/AllLibs/Modbus b/UPP/AllLibs/Modbus new file mode 160000 index 0000000..3aa2797 --- /dev/null +++ b/UPP/AllLibs/Modbus @@ -0,0 +1 @@ +Subproject commit 3aa279736d9383a06613f72d7b7462f0f23d7d4d diff --git a/UPP/AllLibs/MyLibs b/UPP/AllLibs/MyLibs new file mode 160000 index 0000000..eff6470 --- /dev/null +++ b/UPP/AllLibs/MyLibs @@ -0,0 +1 @@ +Subproject commit eff64709bccb8f8fa7297f4042f4ebb7c71a5a21 diff --git a/UPP/AllLibs/PeriphGeneral b/UPP/AllLibs/PeriphGeneral new file mode 160000 index 0000000..50c07cd --- /dev/null +++ b/UPP/AllLibs/PeriphGeneral @@ -0,0 +1 @@ +Subproject commit 50c07cd0911d11106670d25d1457c45735eaa4fa diff --git a/UPP/Core/Configs/SEGGER_RTT_Conf.h b/UPP/Core/Configs/SEGGER_RTT_Conf.h new file mode 100644 index 0000000..e386e8b --- /dev/null +++ b/UPP/Core/Configs/SEGGER_RTT_Conf.h @@ -0,0 +1,429 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2021 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 8.10g * +* * +********************************************************************** + +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_Conf.h +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 24316 $ + +*/ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#ifdef __IAR_SYSTEMS_ICC__ + #include +#endif + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +// +// Take in and set to correct values for Cortex-A systems with CPU cache +// +//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system +//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached +// +// Most common case: +// Up-channel 0: RTT +// Up-channel 1: SystemView +// +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) +#endif +// +// Most common case: +// Down-channel 0: RTT +// Down-channel 1: SystemView +// +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) +#endif + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP (4096) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) +#endif + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_TRIM // Mode for pre-initialized terminal channel (buffer 0) +#endif + +/********************************************************************* +* +* RTT memcpy configuration +* +* memcpy() is good for large amounts of data, +* but the overhead is big for small amounts, which are usually stored via RTT. +* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. +* +* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. +* This is may be required with memory access restrictions, +* such as on Cortex-A devices with MMU. +*/ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop +#endif +// +// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets +// +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) +//#endif + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) +#endif + +/********************************************************************* +* +* RTT lock configuration for SEGGER Embedded Studio, +* Rowley CrossStudio and GCC +*/ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) + #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "movs r1, #1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + + #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #elif defined(__riscv) || defined(__riscv_xlen) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "a1" \ + ); \ + } + #else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR EWARM +*/ +#ifdef __ICCARM__ + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ + (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ + (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RX +*/ +#ifdef __ICCRX__ + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RL78 +*/ +#ifdef __ICCRL78__ + #define SEGGER_RTT_LOCK() { \ + __istate_t _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for KEIL ARM +*/ +#ifdef __CC_ARM + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ + _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ + _SEGGER_RTT__PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char BASEPRI __asm( "basepri"); \ + _SEGGER_RTT__LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for TI ARM +*/ +#ifdef __TI_ARM__ + #if defined (__TI_ARM_V6M0__) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for CCRX +*/ +#ifdef __RX + #include + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = get_psw() & 0x010000; \ + clrpsw_i(); + + #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for embOS Simulation on Windows +* (Can also be used for generic RTT locking with embOS) +*/ +#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) + +void OS_SIM_EnterCriticalSection(void); +void OS_SIM_LeaveCriticalSection(void); + +#define SEGGER_RTT_LOCK() { \ + OS_SIM_EnterCriticalSection(); + +#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration fallback +*/ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#endif + +#endif +/*************************** End of file ****************************/ diff --git a/UPP/Core/Configs/memspi_config.h b/UPP/Core/Configs/memspi_config.h new file mode 100644 index 0000000..54ed13b --- /dev/null +++ b/UPP/Core/Configs/memspi_config.h @@ -0,0 +1,70 @@ +/** +****************************************************************************** +* @file memspi_config.h +* @brief Конфигурационные параметры для общения с FLASH/EEPROM по SPI +****************************************************************************** +@addtogroup MEMSPI_CONFIGS Memory SPI configs +@ingroup MEMSPI +@brief Конфигурация библиотеки +@{ +****************************************************************************** +* @details +Файл содержит настройки для работы Memory SPI: +Размеры страниц и секторов внешней памяти +Включение двойного статус регистра (если соответствующая микросхема) +- Низкоуровневые функции для приема/передачи по SPI и выбора чипа ChipSelect +******************************************************************************/ +#ifndef __SPI_MEMORY_CONFIG_H_ +#define __SPI_MEMORY_CONFIG_H_ +#include "upp_config.h" + +/////////////////////////---USER SETTINGS---///////////////////////// + +//#define MEMSPI_SEPARATED_STATUS_REGISTER ///< Использовать двойной статус регистр + +#define MEMSPI_SECTOR_SIZE (0x1000) ///< Размер одного сектора памяти (4096 байт) +#define MEMSPI_PAGE_SIZE (0x100) ///< Размер одной страницы памяти (256 байт) + + +/** @defgroup MEMSPI_LowLevel Config Hardware SPI + * @brief Конфигурация функций для доступа к SPI + * @{ + */ + +/** + * @brief SPI Transmit. + * @param _hmemspi_ Указатель на хендл внешней памяти. + * @param _data_ Указатель на данные для отправки. + * @param _size_ Размер данных для отправки. + * @param _timeout_ Время, за которое должна быть осуществлена отправка. + * @note Здесь вызывается только функция HAL, и ничего больше. + */ +#define MEMSPI_SPI_Transmit(_hmemspi_, _data_, _size_, _timeout_) HAL_SPI_Transmit(_hmemspi_->hspi, _data_, _size_, _timeout_) +/** + * @brief SPI Receive. + * @param _hmemspi_ Указатель на хендл внешней памяти. + * @param _data_ Указатель на буффер для прниема данных. + * @param _size_ Размер данных для приема. + * @param _timeout_ Время, за которое должен быть осуществлен прием. + * @note Здесь вызывается только функция HAL, и ничего больше. + */ +#define MEMSPI_SPI_Receive(_hmemspi_, _data_, _size_, _timeout_) HAL_SPI_Receive(_hmemspi_->hspi, _data_, _size_, _timeout_) + +/** + * @brief Select MEMORY chip. + */ +#define MEMSPI_Select(_hmemspi_) (_hmemspi_->CS_GPIOx->BSRR = _hmemspi_->CS_PIN << 16) +/** + * @brief Deselect MEMORY chip. + */ +#define MEMSPI_Deselect(_hmemspi_) (_hmemspi_->CS_GPIOx->BSRR = _hmemspi_->CS_PIN) + +/** //MEMSPI_LowLevel + * @} + */ + +#endif // __SPI_MEMORY_CONFIG_H_ + +/** //MEMSPI_CONFIGS + * @} + */ diff --git a/UPP/Core/Configs/modbus_config.h b/UPP/Core/Configs/modbus_config.h new file mode 100644 index 0000000..dcae48e --- /dev/null +++ b/UPP/Core/Configs/modbus_config.h @@ -0,0 +1,71 @@ +/** +****************************************************************************** +* @file modbus_config.h +* @brief Конфигурационные параметры Modbus устройства +****************************************************************************** +@addtogroup MODBUS_CONFIGS Modbus configs +@ingroup MODBUS +@brief Конфигурация библиотеки +@{ +****************************************************************************** +* @details +Файл содержит настройки для работы Modbus: +- Подключение библиотек контроллера +- ID устройства и таймауты +- Строковые идентификаторы (Vendor, Product, Revision) +- Настройки периферии (UART, TIMER) +- Подключение модулей Modbus +- Опциональные функции (переключение команд 0x03/0x04) +******************************************************************************/ +#ifndef _MODBUS_CONFIG_H_ +#define _MODBUS_CONFIG_H_ +#include "upp_config.h" + +// Общие параметры +#define MODBUS_DEVICE_ID 1 ///< Адрес устройства в сети Modbus +#define MODBUS_TIMEOUT 5000 ///< Таймаут в тиках таймера + +// Строковые идентификаторы устройства +#define MODBUS_VENDOR_NAME "NIO-12" +#define MODBUS_PRODUCT_CODE "" +#define MODBUS_REVISION "" +#define MODBUS_VENDOR_URL "" +#define MODBUS_PRODUCT_NAME "" +#define MODBUS_MODEL_NAME "" +#define MODBUS_USER_APPLICATION_NAME "" + +#define MODBUS_NUMB_OF_USEROBJECTS 0 ///< Количество пользовательских объектов +#define MODBUS_USEROBJECT_0_NAME "" ///< Строка пользовательского идентификатора 0. По аналогии можно определить строки до <=128 USEROBJECT + +// Периферия (опционально) +//#define mb_huart huart1 ///< Удобный дефайн для модбасовского uart +//#define mb_htim htim3 ///< Удобный дефайн для модбасовского таймера +//#define RS_EnableReceive() ///< Функция изменения направления передачи на ПРИЕМ для RS-485 +//#define RS_EnableTransmit() ///< Функция изменения направления передачи на ПЕРЕДАЧУ для RS-485 + + +// Модули modbus +#define MODBUS_ENABLE_SLAVE ///< Включить обработку СЛЕЙВ режима +#define MODBUS_ENABLE_MASTER ///< Включить обработку МАСТЕР режима + +#define MODBUS_ENABLE_COILS ///< Включить обработку коилов +#define MODBUS_ENABLE_HOLDINGS ///< Включить обработку регистров хранения +#define MODBUS_ENABLE_INPUTS ///< Включить обработку входных регистров +#define MODBUS_ENABLE_DEVICE_IDENTIFICATIONS ///< Включить обработку идентификаторы устройства +#define MODBUS_ENABLE_DIAGNOSTICS ///< Включить обработку диагностики модбас + +//#define MODBUS_PROTOCOL_TCP ///< Включить TCP-протокол, иначе - RTU + +/** + * @brief Поменять комманды 0x03 и 0x04 местами (для LabView терминалки от двигателей) + * @details Терминалка от двигателей использует для чтения регистров комманду R_HOLD_REGS вместо R_IN_REGS + * Поэтому чтобы считывать Input Regs - надо поменять их местами. + */ +//#define MODBUS_SWITCH_COMMAND_R_IN_REGS_AND_R_HOLD_REGS + +///////////////////////////////////////////////////////////////////// +/////////////////////////---CALC DEFINES---////////////////////////// + + + +#endif //_MODBUS_CONFIG_H_ diff --git a/UPP/Core/Configs/modbus_data.c b/UPP/Core/Configs/modbus_data.c new file mode 100644 index 0000000..1626ce8 --- /dev/null +++ b/UPP/Core/Configs/modbus_data.c @@ -0,0 +1,141 @@ +/** +****************************************************************************** +* @file modbus_data.c +* @brief Функции доступа к данным Modbus +****************************************************************************** +* @details +Модуль реализует функции валидации адресов и доступа к данным: +- Проверка корректности запрашиваемых адресов +- Определение указателей на реальные данные в памяти +- Поддержка пользовательских массивов регистров и coils + +@section Валидация адресов: +- MB_Check_Address_For_Arr() - проверка принадлежности адреса массиву +- MB_DefineRegistersAddress() - получение указателя на регистры +- MB_DefineCoilsAddress() - получение указателя на coils + +******************************************************************************/ + +#include "modbus_core.h" +#include "modbus_coils.h" +#include "modbus_holdregs.h" +#include "modbus_inputregs.h" +#include "modbus_devid.h" + + +/** + * @brief Check is address valid for certain array. + * @param Addr Начальный адресс. + * @param Qnt Количество запрашиваемых элементов. + * @param R_ARR_ADDR Начальный адресс массива R_ARR. + * @param R_ARR_NUMB Количество элементов в массиве R_ARR. + * @return ExceptionCode - ET_ILLEGAL_DATA_ADRESS если адресс недействителен, и ET_NO_ERRORS если все ок. + * + * @details Позволяет определить, принадлежит ли адресс Addr массиву R_ARR: + * Если адресс Addr находится в диапазоне адрессов массива R_ARR, то возвращаем NO_ERROR. + * Если адресс Addr находится за пределами адрессов массива R_ARR - ET_ILLEGAL_DATA_ADDRESSю. + */ +MB_ExceptionTypeDef MB_Check_Address_For_Arr(uint16_t Addr, uint16_t Qnt, uint16_t R_ARR_ADDR, uint16_t R_ARR_NUMB) +{ + // if address from this array + if(Addr >= R_ARR_ADDR) + { + // if quantity too big return error + if ((Addr - R_ARR_ADDR) + Qnt > R_ARR_NUMB) + { + return ET_ILLEGAL_DATA_ADDRESS; // return exception code + } + // if all ok - return no errors + return ET_NO_ERRORS; + } + // if address isnt from this array return error + else + return ET_ILLEGAL_DATA_ADDRESS; // return exception code +} +/** + * @brief Define Address Origin for Input/Holding Registers + * @param pRegs Указатель на указатель регистров. + * @param Addr Адрес начального регистра. + * @param Qnt Количество запрашиваемых регистров. + * @param WriteFlag Флаг регистр нужны для чтения или записи. + * @return ExceptionCode Код исключения если есть, и ET_NO_ERRORS если нет. + * + * @details Определение адреса начального регистра. + * @note WriteFlag пока не используется. + */ +MB_ExceptionTypeDef MB_DefineRegistersAddress(uint16_t **pRegs, uint16_t Addr, uint16_t Qnt, uint8_t RegisterType) +{ + /* check quantity error */ + if (Qnt > DATA_SIZE) + { + return ET_ILLEGAL_DATA_VALUE; // return exception code + } + + if(RegisterType == RegisterType_Holding) + { + // Default holding registers + if(MB_Check_Address_For_Arr(Addr, Qnt, R_HOLDING_ADDR, R_HOLDING_QNT) == ET_NO_ERRORS) + { + *pRegs = MB_Set_Register_Ptr(&MB_DATA.HoldRegs, Addr - R_HOLDING_ADDR); // указатель на выбранный по Addr регистр + } + // if address doesnt match any array - return illegal data address response + else + { + return ET_ILLEGAL_DATA_ADDRESS; + } + } + else if(RegisterType == RegisterType_Input) + { + // Default input registers + if(MB_Check_Address_For_Arr(Addr, Qnt, R_INPUT_ADDR, R_INPUT_QNT) == ET_NO_ERRORS) + { + *pRegs = MB_Set_Register_Ptr(&MB_DATA.InRegs, Addr - R_INPUT_ADDR); // указатель на выбранный по Addr регистр + } + // if address doesnt match any array - return illegal data address response + else + { + return ET_ILLEGAL_DATA_ADDRESS; + } + } + else + { + return ET_ILLEGAL_FUNCTION; + } + // if found requeried array return no err + return ET_NO_ERRORS; // return no errors +} +/** + * @brief Define Address Origin for coils + * @param pCoils Указатель на указатель коилов. + * @param Addr Адресс начального коила. + * @param Qnt Количество запрашиваемых коилов. + * @param start_shift Указатель на переменную содержащую сдвиг внутри регистра для начального коила. + * @param WriteFlag Флаг коилы нужны для чтения или записи. + * @return ExceptionCode Код исключения если есть, и ET_NO_ERRORS если нет. + * + * @details Определение адреса начального регистра запрашиваемых коилов. + * @note WriteFlag используется для определния регистров GPIO: ODR или IDR. + */ +MB_ExceptionTypeDef MB_DefineCoilsAddress(uint16_t **pCoils, uint16_t Addr, uint16_t Qnt, uint16_t *start_shift, uint8_t WriteFlag) +{ + /* check quantity error */ + if (Qnt > 2000) + { + return ET_ILLEGAL_DATA_VALUE; // return exception code + } + + // Default coils + if(MB_Check_Address_For_Arr(Addr, Qnt, C_COILS_ADDR, C_COILS_QNT) == ET_NO_ERRORS) + { + *pCoils = MB_Set_Coil_Reg_Ptr(&MB_DATA.Coils, Addr - C_COILS_ADDR); // указатель на выбранный по Addr массив коилов + } + // if address doesnt match any array - return illegal data address response + else + { + return ET_ILLEGAL_DATA_ADDRESS; + } + + *start_shift = Addr % 16; // set shift to requested coil + // if found requeried array return no err + return ET_NO_ERRORS; // return no errors +} diff --git a/UPP/Core/Configs/modbus_data.h b/UPP/Core/Configs/modbus_data.h new file mode 100644 index 0000000..848006b --- /dev/null +++ b/UPP/Core/Configs/modbus_data.h @@ -0,0 +1,159 @@ +/** +****************************************************************************** +* @file modbus_data.h +* @brief Определения структур данных Modbus устройства +****************************************************************************** +@defgroup MODBUS_DATA Modbus Registers Map +@ingroup MODBUS +@brief Определение карты регистров и коилов +****************************************************************************** +* @details +Файл содержит объявления структур данных, доступных через Modbus: +- Holding Registers (R/W) - регистры хранения +- Input Registers (R/O) - входные регистры +- Coils (R/W) - дискретные выходы + +@section datinit Базовая настройка под устройство: +1. Настроить диапазоны адресов + - @ref R_INPUT_ADDR и @ref R_INPUT_QNT для входных регистров + - @ref R_HOLDING_ADDR и @ref R_HOLDING_QNT для регистров хранения + - @ref C_COILS_ADDR и @ref C_COILS_ADDR для коилов +3. Настроить структуры данных: + - @ref MB_DataInRegsTypeDef + - @ref MB_DataHoldRegsTypeDef + - @ref MB_DataCoilsTypeDef + + +@section datexpert Расширенная настройка под устройство: +1. Добавить новый массив с нужными данными. +2. Добавить дефайны для определения его начального адреса и количества элементов +3. Добавить проверку адресов в MB_DefineRegistersAddress/MB_DefineCoilsAddress. + + Пример: + @code + #define R_USER_ADDR 555 + #define R_USER_QNT 16 + uint16_t user_regs[16]; + + //... + else if(MB_Check_Address_For_Arr(Addr, Qnt, R_USER_ADDR, R_USER_QNT) == ET_NO_ERRORS) + { + *pRegs = MB_Set_Register_Ptr(&user_regs, Addr-R_USER_ADDR); // ВАЖНО! + // -R_USER_ADDR нужен чтобы взять адрес относительно начала массива + } + else + { + return ET_ILLEGAL_DATA_ADDRESS; + } + @endcode +******************************************************************************/ + +#ifndef _MODBUS_DATA_H_ +#define _MODBUS_DATA_H_ + +#include "stdint.h" + + + +//--------------SIZES OF DATA--------------- + +// DEFINES FOR INPUT REGISTERS ARRAYS +#define R_INPUT_ADDR 0 ///< Начальный адрес входных регистров +#define R_INPUT_QNT 16 ///< Количество входных регистров + +// DEFINES FOR HOLDING REGISTERS ARRAYS +#define R_HOLDING_ADDR 0 ///< Начальный адрес регистров хранения +#define R_HOLDING_QNT 16 ///< Количество регистров хранения + +// DEFINES FOR COIL ARRAYS +#define C_COILS_ADDR 0 ///< Начальный адрес коилов +#define C_COILS_QNT 16 ///< Количество регистров коилов + +//--------------DEFINES FOR REGISTERS--------------- +// DEFINES FOR ARRAYS +/** + * @addtogroup MODBUS_DATA_RERISTERS_DEFINES Registers structures + * @ingroup MODBUS_DATA + * @brief Стуруктура регистров (входных и хранения) + @code + Для массивов регистров: + R__ADDR - модбас адресс первого регистра в массиве + R__QNT - количество регистров в массиве + @endcode + * @{ + */ + + +/** + * @brief Регистры хранения + */ +typedef struct //MB_DataInRegsTypeDef +{ + uint16_t in[16]; +}MB_DataInRegsTypeDef; + + +/** + * @brief Входные регистры + */ +typedef struct //MB_DataInRegsTypeDef +{ + uint16_t out[16]; +}MB_DataHoldRegsTypeDef; + + +/** MODBUS_DATA_RERISTERS_DEFINES + * @} + */ + +//----------------DEFINES FOR COILS----------------- +/** + * @addtogroup MODBUS_DATA_COILS_DEFINES Coils Structure + * @ingroup MODBUS_DATA + * @brief Структура коилов + @code + Структура дефайна + Для массивов коилов: + C__ADDR - модбас адресс первого коила в массиве + C__QNT - количество коилов в массиве (минимум 16) + @endcode + * @{ + */ + + + +/** + * @brief Коилы + * @details Желательно с помощью reserved делать стркутуру кратной 16-битам + */ +typedef struct //MB_DataCoilsTypeDef +{ + unsigned reserved:16; +}MB_DataCoilsTypeDef; + +/** MODBUS_DATA_COILS_DEFINES + * @} + */ + + +//-----------MODBUS DEVICE DATA SETTING------------- +// MODBUS DATA STRUCTTURE +/** + * @brief Структура со всеми регистрами и коилами модбас + * @ingroup MODBUS_DATA + */ +typedef struct // tester modbus data +{ + MB_DataInRegsTypeDef InRegs; ///< Modbus input registers @ref MB_DataInRegsTypeDef + + MB_DataCoilsTypeDef Coils; ///< Modbus coils @ref MB_DataCoilsTypeDef + + MB_DataHoldRegsTypeDef HoldRegs; ///< Modbus holding registers @ref MB_DataHoldRegsTypeDef +}MB_DataStructureTypeDef; +extern MB_DataStructureTypeDef MB_DATA; + + +#endif //_MODBUS_DATA_H_ + +///////////////////////////////////////////////////////////// +///////////////////////TEMP/OUTDATE/OTHER//////////////////// diff --git a/UPP/Core/Configs/mylibs_config.h b/UPP/Core/Configs/mylibs_config.h new file mode 100644 index 0000000..4ceb40b --- /dev/null +++ b/UPP/Core/Configs/mylibs_config.h @@ -0,0 +1,113 @@ +/** +************************************************************************** +* @file mylibs_config.h +* @brief Конфигурации для библиотек MyLibs +************************************************************************** +* @defgroup MYLIBS_CONFIG Configs +* @ingroup MYLIBS_ALL +* @brief Конфигурации для библиотек MyLibs +* @{ +*************************************************************************/ +#ifndef __MYLIBS_CONFIG_H_ +#define __MYLIBS_CONFIG_H_ +#include "upp_config.h" + +// user includes + +/** + * @addtogroup TRACE_CONFIG Trace configs + * @ingroup MYLIBS_CONFIG + * @brief Конфигурация трекеров и трассировки + * @{ + */ + +//#define TRACKERS_ENABLE ///< Включить трекеры +//#define SERIAL_TRACE_ENABLE ///< Включить serial трассировку +//#define RTT_TRACE_ENABLE ///< Включить serial трассировку через RTT +//#define SWO_TRACE_ENABLE ///< Включить serial трассировку через SWO +/** + * @brief Уровень log serial трассировки @ref log_printf + * - LOG_LEVEL == 0 - логирование отключено (макрос пустой) + * - LOG_LEVEL == 1 - выводится время и TAG + * - LOG_LEVEL >= 2 - выводится время, TAG, имя файла и номер строки + */ +#define LOG_LEVEL 1 + +#define RTT_FLASH_BUFFER_SIZE 1024 ///< Размер буфера RTT в Flash +#define RTT_FLASH_SECTOR FLASH_SECTOR_11 ///< Сектор FLASH куда положится RTT буфер +#define RTT_FLASH_SECTOR_START 0x080E0000 ///< Начало сектора RTT_FLASH_SECTOR +#define RTT_FLASH_SECTOR_END 0x080FFFFF ///< Конец сектора RTT_FLASH_SECTOR + + +#define HARDFAULT_SERIAL_TRACE ///< Включить обработку и serial трассировку Hardfault +#define HF_RTT_TAG_BASE 0xDEAD0000 ///< базовый тег для HardFault +#define HF_RTT_TAIL_SIZE RTT_FLASH_BUFFER_SIZE ///< Размер буфера RTT, который сохранится при Hardfault +#define HF_STACK_DUMP_WORDS 32 ///< Сколько слов стека будет проанализировано во время Hardfault +#define HF_FLASH_ADDR ((uint32_t)0x080FF000) ///< Адрес FLASH куда положится RTT буфер +#define HF_RAM_END 0x20030000 ///< Конец RAM памяти (чтобы во время анализа стека не выйти за пределы) + +#define GPIO_TRACE_ENABLE ///< Включить GPIO трассировку + +/** TRACE_CONFIG + * @} + */ + + +/** + * @addtogroup GEN_CONFIG Genetic configs + * @ingroup MYLIBS_CONFIG + * @brief Конфигурация генетического алгоритма обучения + * @{ + */ + +//#define GEN_OPTIMIZATION_ENABLE ///< Включить оптимизацию параметров +#define GEN_MAX_PARAMS 20 ///< Максимальное количество параметров +#define GEN_MAX_CANDIDATES 100 ///< Максимальное количество кандидатов для обучения + +/** GEN_CONFIG + * @} + */ + + +/** + * @addtogroup GEN_CONFIG Genetic configs + * @ingroup MYLIBS_CONFIG + * @brief Конфигурация генетического алгоритма обучения + * @{ + */ + + +//#define BENCH_TIME_ENABLE ///< Включить бенч времени +#define BENCH_TIME_MAX_CHANNELS 16 ///< Максимальное количество каналов измерения + +/** GEN_CONFIG + * @} + */ + + + +/** + * @addtogroup LIBS_CONFIG Libraries configs + * @ingroup MYLIBS_CONFIG + * @brief Подключение различных модулей библиотеки + * @{ + */ + +#define local_time() uwTick ///< Локальное время + +#define INCLUDE_GEN_OPTIMIZER ///< Подключить библиотеку для оптимизации параметров +#define INCLUDE_BIT_ACCESS_LIB ///< Подключить библиотеку с typedef с битовыми полями +#define INCLUDE_TRACKERS_LIB ///< Подключить библиотеку с трекерами +#define INCLUDE_TRACE_LIB ///< Подключить библиотеку с трейсами +#define INCLUDE_GENERAL_PERIPH_LIBS ///< Подключить библиотеку с периферией +#define INCLUDE_BENCH_TIME ///< Подключить библиотеку с периферией +//#define FREERTOS_DELAY ///< Использовать FreeRTOS задержку, вместо HAL + +/** LIBS_CONFIG + * @} + */ + +/** MYLIBS_CONFIG + * @} + */ +#endif //__MYLIBS_CONFIG_H_ \ No newline at end of file diff --git a/UPP/Core/Configs/mylibs_include.h b/UPP/Core/Configs/mylibs_include.h new file mode 100644 index 0000000..dc7b4fa --- /dev/null +++ b/UPP/Core/Configs/mylibs_include.h @@ -0,0 +1,136 @@ +/** +************************************************************************** +* @file mylibs_include.h +* @brief Заголочный файл для всех библиотек +************************************************************************** +* @details +Здесь нужно собрать библиотеки и дефайны, которые должны быть видны во всем проекте, +чтобы не подключать 100 инклюдов в каждом ".c" файле +************************************************************************** +* @defgroup MYLIBS_ALL My Libs +* @brief Все используемые MyLibs библиотеки +* @details +Для подключения библиотеки необходимо: +- Сконфигурировать mylibs_config.h: + - Подключить заголовочный файл HAL библиотеки конкретного МК (напр. stm32f4xx_hal.h) + - Подключить другие заголовочные файлы которые общие для всего проекта и должны быть видны + - Подключить mylibs_include.h туда, где необходим доступ к библиотекам. + +*************************************************************************/ +#ifndef __MYLIBS_INCLUDE_H_ +#define __MYLIBS_INCLUDE_H_ + +#include "mylibs_defs.h" + + +#ifdef ARM_MATH_CM4 + #include "arm_math.h" +#else + #include "math.h" +#endif + + +#ifdef INCLUDE_BIT_ACCESS_LIB +#include "bit_access.h" +#endif + +#ifdef INCLUDE_TRACKERS_LIB +#include "trackers.h" +#else + #define TrackerTypeDef(num_user_vars) void * + #define num_of_usercnts(_user_) 0 + #define assert_tracecnt(_cntstruct_, _uservarnumb_) 0 + #define if_assert_usertracker(_cntstruct_, _uservarnumb_) if(0) + #define tern_assert_usertracker(_cntstruct_, _uservarnumb_) 0 + #define TrackerGet_Ok(_cntstruct_) dummy + #define TrackerGet_Err(_cntstruct_) dummy + #define TrackerGet_Warn(_cntstruct_) dummy + #define TrackerGet_User(_cntstruct_, _uservarnumb_) dummy + #define TrackerCnt_Ok(_cntstruct_) + #define TrackerCnt_Err(_cntstruct_) + #define TrackerCnt_Warn(_cntstruct_) + #define TrackerCnt_User(_cntstruct_, _uservarnumb_) + #define TrackerWrite_User(_cntstruct_, _uservarnumb_, _val_) + #define TrackerClear_All(_cntstruct_) + #define TrackerClear_Ok(_cntstruct_) + #define TrackerClear_Err(_cntstruct_) + #define TrackerClear_Warn(_cntstruct_) + #define TrackerClear_User(_cntstruct_) + #define TrackerClear_UserAll(_cntstruct_) +#endif + +#ifdef INCLUDE_TRACE_LIB +#include "trace.h" +#else +#define my_printf(...) +#define log_printf(TAG, fmt, ...) +#define TRACE_GPIO_SET(_gpio_,_pin_) +#define TRACE_GPIO_RESET(_gpio_,_pin_) +#define RTT_FlashPrepare(...) +#define RTT_EraseFlash(...) 0 +#define RTT_SaveToFlash(...) 0 +#define RTT_ReadFromFlash(...) 0 +#define HF_CheckRecovered(...) 0 +#define HF_HandleFault(...) +#endif + +#ifdef INCLUDE_GEN_OPTIMIZER +#include "gen_optimizer.h" +#else +typedef struct { + uint16_t n_params; + uint16_t n_cand; + uint16_t n_best; + uint16_t iq_mutation; + int32_t loss[0]; + int32_t candidates[0][0]; +} GenOptimizer_t; +#define GenOptimizer_Init(opt, n_params, n_cand, n_best, iq_mutation, start_params) +#define GenOptimizer_Step(opt, params, LossFunc) +#define PARAM_SCALE_Q16(x, min_val, max_val) (x) +#define PARAM_UNSCALE_Q16(q16_val, min_val, max_val) (q16_val) +#endif + + + +#ifdef INCLUDE_BENCH_TIME +#include "bench_time.h" +#else //BENCH_TIME_ENABLE +#define BenchTime_Init() +#define BenchTime_Start(channel, ticks, tick_period) 0 +#define BenchTime_End(channel, ticks) 0 +#define BenchTime_GetMin(channel) 0 +#define BenchTime_GetMax(channel) 0 +#define BenchTime_GetAverage(channel) 0 +#define BenchTime_GetCount(channel) 0 +#define BenchTime_GetLast(channel) 0 +#define BenchTime_ResetStats(channel) +#endif //BENCH_TIME_ENABLE + +#ifdef INCLUDE_GENERAL_PERIPH_LIBS + +#include "__general_flash.h" +#include "general_gpio.h" +#ifdef HAL_SPI_MODULE_ENABLED +#include "general_spi.h" +#endif +#ifdef HAL_UART_MODULE_ENABLED +#include "general_uart.h" +#endif +#ifdef HAL_TIM_MODULE_ENABLED +#include "general_tim.h" +#endif + +#endif //INCLUDE_GENERAL_PERIPH_LIBS + + + + +/////////////////////////---USER SETTINGS---///////////////////////// +// user includes + +// user settings +/////////////////////////---USER SETTINGS---///////////////////////// + + +#endif // __MYLIBS_INCLUDE_H_ \ No newline at end of file diff --git a/UPP/Core/Configs/upp_config.h b/UPP/Core/Configs/upp_config.h new file mode 100644 index 0000000..19180c0 --- /dev/null +++ b/UPP/Core/Configs/upp_config.h @@ -0,0 +1,22 @@ +/** +****************************************************************************** +* @file upp_config.h +* @brief Конфигурационные параметры УПП +****************************************************************************** +@addtogroup UPP_CONFIG UPP configs +@ingroup UPP_MAIN +@brief Конфигурация УПП +@{ +****************************************************************************** +* @details +******************************************************************************/ +#ifndef _UPP_CONFIG_H_ +#define _UPP_CONFIG_H_ +#include "stm32f4xx_hal.h" + +///////////////////////////////////////////////////////////////////// +/////////////////////////---CALC DEFINES---////////////////////////// + + + +#endif //_UPP_CONFIG_H_ diff --git a/UPP/Core/Inc/main.h b/UPP/Core/Inc/main.h index b4a33eb..b7e0a1e 100644 --- a/UPP/Core/Inc/main.h +++ b/UPP/Core/Inc/main.h @@ -31,7 +31,8 @@ extern "C" { /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ - +#include "mylibs_include.h" +#include "modbus.h" /* USER CODE END Includes */ /* Exported types ------------------------------------------------------------*/ diff --git a/UPP/Core/Src/main.c b/UPP/Core/Src/main.c index da91e21..2ff4e27 100644 --- a/UPP/Core/Src/main.c +++ b/UPP/Core/Src/main.c @@ -71,7 +71,7 @@ int main(void) { /* USER CODE BEGIN 1 */ - + /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ diff --git a/UPP/MDK-ARM/RTE/_UPP/RTE_Components.h b/UPP/MDK-ARM/RTE/_UPP/RTE_Components.h index 3df6892..a8a406a 100644 --- a/UPP/MDK-ARM/RTE/_UPP/RTE_Components.h +++ b/UPP/MDK-ARM/RTE/_UPP/RTE_Components.h @@ -16,6 +16,9 @@ */ #define CMSIS_device_header "stm32f4xx.h" +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:ITM:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ #endif /* RTE_COMPONENTS_H */ diff --git a/UPP/MDK-ARM/UPP.uvoptx b/UPP/MDK-ARM/UPP.uvoptx index 5bb3435..c6f0d58 100644 --- a/UPP/MDK-ARM/UPP.uvoptx +++ b/UPP/MDK-ARM/UPP.uvoptx @@ -1,171 +1,1124 @@ - + - 1.0 -
### uVision Project, (C) Keil Software
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../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c + stm32f4xx_hal_flash.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c + stm32f4xx_hal_flash_ex.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c + stm32f4xx_hal_flash_ramfunc.c + 0 + 0 + + + 7 + 54 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c + stm32f4xx_hal_gpio.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c + stm32f4xx_hal_dma_ex.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c + stm32f4xx_hal_dma.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c + stm32f4xx_hal_pwr.c + 0 + 0 + + + 7 + 58 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c + stm32f4xx_hal_pwr_ex.c + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c + stm32f4xx_hal_cortex.c + 0 + 0 + + + 7 + 60 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c + stm32f4xx_hal.c + 0 + 0 + + + 7 + 61 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c + stm32f4xx_hal_exti.c + 0 + 0 + + + 7 + 62 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c + stm32f4xx_hal_can.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c + stm32f4xx_hal_iwdg.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c + stm32f4xx_hal_rtc.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c + stm32f4xx_hal_rtc_ex.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c + stm32f4xx_hal_spi.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c + stm32f4xx_hal_tim.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c + stm32f4xx_hal_tim_ex.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c + stm32f4xx_hal_uart.c + 0 + 0 + + + + + Drivers/CMSIS + 0 + 0 + 0 + 0 + + 8 + 70 + 1 + 0 + 0 + 0 + ../Core/Src/system_stm32f4xx.c + system_stm32f4xx.c + 0 + 0 + + + + + Application/MDK-ARM + 0 + 0 + 0 + 0 + + 9 + 71 + 2 + 0 + 0 + 0 + startup_stm32f427xx.s + startup_stm32f427xx.s + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Compiler + 0 + 0 + 0 + 1 + + diff --git a/UPP/MDK-ARM/UPP.uvprojx b/UPP/MDK-ARM/UPP.uvprojx index c57012e..75168fa 100644 --- a/UPP/MDK-ARM/UPP.uvprojx +++ b/UPP/MDK-ARM/UPP.uvprojx @@ -1,39 +1,47 @@ - - + + + 2.1 +
### uVision Project, (C) Keil Software
+ UPP 0x4 ARM-ADS + 6190000::V6.19::ARMCLANG + 6190000::V6.19::ARMCLANG + 1 STM32F427ZGTx STMicroelectronics + Keil.STM32F4xx_DFP.2.16.0 + http://www.keil.com/pack/ IRAM(0x20000000-0x2002FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) FPU2 CPUTYPE("Cortex-M4") TZ - - - + + + 0 - - - - - - - - - - - + + + + + + + + + + + $$Device:STM32F427ZGTx$CMSIS\SVD\STM32F427x.svd 0 0 - - - - - + + + + + 0 0 @@ -48,15 +56,15 @@ 1 1 1 - ./UPP/ + 1 0 0 0 0 - - + + 0 0 0 @@ -65,8 +73,8 @@ 0 0 - - + + 0 0 0 @@ -74,16 +82,16 @@ 0 - 1 - - + 0 + + 0 0 0 0 1 - + 0 @@ -97,8 +105,8 @@ 0 0 3 - - + + 0 @@ -131,11 +139,11 @@ 1 BIN\UL2V8M.DLL - - - - - + + + + + 0 @@ -168,7 +176,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -179,8 +187,9 @@ 2 0 0 - 0 - 1 + 0 + 1 + 0 8 0 0 @@ -199,7 +208,7 @@ 0 0 1 - 1 + 0 0 0 0 @@ -238,13 +247,13 @@ 0 - 0x0 - 0x0 + 0x20000000 + 0x30000 1 - 0x0 - 0x0 + 0x8000000 + 0x100000 0 @@ -268,8 +277,8 @@ 1 - - + 0x8000000 + 0x100000 1 @@ -293,20 +302,20 @@ 0 - 0x0 - 0x0 + 0x20000000 + 0x30000 0 - 0x0 - 0x0 + 0x10000000 + 0x10000 - + 1 - 4 + 1 0 0 1 @@ -315,24 +324,24 @@ 0 0 0 - 2 + 3 0 0 1 0 0 - 5 - 3 + 3 + 5 1 1 0 0 0 - + USE_HAL_DRIVER,STM32F427xx - - ../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include + + ../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;..\AllLibs\ExtMemory\Inc;..\AllLibs\Modbus\Inc;..\AllLibs\MyLibs\MyLibs\Inc;..\AllLibs\MyLibs\RTT;..\AllLibs\PeriphGeneral\Inc;..\Core\Configs @@ -347,10 +356,10 @@ 0 1 - - - - + + + + @@ -360,26 +369,61 @@ 0 1 0 - - - - - - - - - + + + + + + + + + - Application/MDK-ARM + Configs - startup_stm32f427xx.s - 2 - startup_stm32f427xx.s + memspi_config.h + 5 + ..\Core\Configs\memspi_config.h + + + modbus_config.h + 5 + ..\Core\Configs\modbus_config.h + + + modbus_data.c + 1 + ..\Core\Configs\modbus_data.c + + + modbus_data.h + 5 + ..\Core\Configs\modbus_data.h + + + mylibs_config.h + 5 + ..\Core\Configs\mylibs_config.h + + + mylibs_include.h + 5 + ..\Core\Configs\mylibs_include.h + + + SEGGER_RTT_Conf.h + 5 + ..\Core\Configs\SEGGER_RTT_Conf.h + + + upp_config.h + 5 + ..\Core\Configs\upp_config.h @@ -448,6 +492,151 @@ + + MyLibs + + + bench_time.h + 5 + ..\AllLibs\MyLibs\MyLibs\Inc\bench_time.h + + + bit_access.h + 5 + ..\AllLibs\MyLibs\MyLibs\Inc\bit_access.h + + + gen_optimizer.h + 5 + ..\AllLibs\MyLibs\MyLibs\Inc\gen_optimizer.h + + + mylibs_defs.h + 5 + ..\AllLibs\MyLibs\MyLibs\Inc\mylibs_defs.h + + + trace.h + 5 + ..\AllLibs\MyLibs\MyLibs\Inc\trace.h + + + trackers.h + 5 + ..\AllLibs\MyLibs\MyLibs\Inc\trackers.h + + + + + Modbus + + + __crc_algs.c + 1 + ..\AllLibs\Modbus\Src\__crc_algs.c + + + __modbus_compat.c + 1 + ..\AllLibs\Modbus\Src\__modbus_compat.c + + + modbus.c + 1 + ..\AllLibs\Modbus\Src\modbus.c + + + modbus_coils.c + 1 + ..\AllLibs\Modbus\Src\modbus_coils.c + + + modbus_core.c + 1 + ..\AllLibs\Modbus\Src\modbus_core.c + + + modbus_devid.c + 1 + ..\AllLibs\Modbus\Src\modbus_devid.c + + + modbus_diag.c + 1 + ..\AllLibs\Modbus\Src\modbus_diag.c + + + modbus_holdregs.c + 1 + ..\AllLibs\Modbus\Src\modbus_holdregs.c + + + modbus_inputregs.c + 1 + ..\AllLibs\Modbus\Src\modbus_inputregs.c + + + modbus_master.c + 1 + ..\AllLibs\Modbus\Src\modbus_master.c + + + modbus_slave.c + 1 + ..\AllLibs\Modbus\Src\modbus_slave.c + + + rs_message.c + 1 + ..\AllLibs\Modbus\Src\rs_message.c + + + + + ExtMemory + + + memspi.c + 1 + ..\AllLibs\ExtMemory\Src\memspi.c + + + memspi_core.c + 1 + ..\AllLibs\ExtMemory\Src\memspi_core.c + + + + + PeriphGeneral + + + __general_flash.c + 1 + ..\AllLibs\PeriphGeneral\Src\__general_flash.c + + + general_gpio.c + 1 + ..\AllLibs\PeriphGeneral\Src\general_gpio.c + + + general_spi.c + 1 + ..\AllLibs\PeriphGeneral\Src\general_spi.c + + + general_tim.c + 1 + ..\AllLibs\PeriphGeneral\Src\general_tim.c + + + general_uart.c + 1 + ..\AllLibs\PeriphGeneral\Src\general_uart.c + + + Drivers/STM32F4xx_HAL_Driver @@ -583,20 +772,52 @@ + + Application/MDK-ARM + + + startup_stm32f427xx.s + 2 + startup_stm32f427xx.s + + + + + ::CMSIS + + + ::Compiler + + - + - - + + - + + + + + + + - + - + + + + UPP + 1 + + + + + diff --git a/UPP/MDK-ARM/UPP/UPP.sct b/UPP/MDK-ARM/UPP/UPP.sct new file mode 100644 index 0000000..9b7da60 --- /dev/null +++ b/UPP/MDK-ARM/UPP/UPP.sct @@ -0,0 +1,19 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00030000 { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM2 0x10000000 0x00010000 { + .ANY (+RW +ZI) + } +} +